Memory device using a semiconductor

Abstract

The present invention comprises: a p layer 1 that extends in a direction horizontal to a substrate 20, at a position away from the substrate; an n+ layer 2 that serves as a first impurity layer and that is located on one side of the p layer; a first gate insulating layer 4 that covers the p layer 1 and a portion of the n+ layer 2; a first gate conductor layer 5 that covers a portion of the gate insulating layer 4; a second gate insulating layer 6 that covers a portion of the p layer 1, at a position away from the gate insulating layer 4; a second gate conductor layer 7 that covers a portion of the gate insulating layer 6; an n+ layer 3 that serves as a second impurity layer and that is located in a portion of the p layer sandwiched by the gate conductor layer 5 and the gate conductor layer 7; and a dynamic flush memory cell that performs memory operation by connecting a bit line to the first impurity layer, a source line to the second impurity layer, a word line to the first gate conductor layer, and a plate line to the second gate conductor layer, and by manipulating respective voltages therein.

Description

Technical Field

[0001] The present invention relates to a memory device using a semiconductor.

Background Art

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, higher integration, higher performance, lower power consumption, and higher functionality of memory elements have been demanded.

[0003] In a normal planar MOS transistor, the channel extends in a horizontal direction along the upper surface of the semiconductor substrate. In contrast, the channel of an SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Non-Patent Document 1). Therefore, compared with a planar MOS transistor, an SGT enables higher density of semiconductor devices. Using this SGT as a select transistor, high integration can be achieved for a DRAM (Dynamic Random Access Memory, see, for example, Non-Patent Document 2) connected with a capacitor, a PCM (Phase Change Memory, see, for example, Non-Patent Document 3) connected with a resistive change element, an RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), an MRAM (Magneto-resistive Random Access Memory, see, for example, Non-Patent Document 5) that changes the resistance by changing the direction of magnetic spin by current, etc. Also, there are a DRAM memory cell composed of one MOS transistor without a capacitor (see, for example, Non-Patent Documents 6 and 9), a DRAM memory cell having a groove for storing carriers and two gate electrodes (see, for example, Non-Patent Document 8), etc. However, a DRAM without a capacitor has a problem that the voltage margin cannot be sufficiently obtained because it is greatly affected by the coupling of the gate electrode from the floating body word line. Further, when the substrate is completely depleted, the adverse effect becomes large. The present application relates to a memory device using a semiconductor element that can be composed only of MOS transistors without a resistive change element or a capacitor.

Prior Art Documents

Non-Patent Literature

[0004]

Non-Patent Literature 1

Non-Patent Literature 2

Non-Patent Literature 3

Non-Patent Literature 4

Non-Patent Document 5

Non-Patent Document 6

Non-Patent Document 7

Non-Patent Document 8

Non-Patent Document 9

Non-Patent Document 10

Summary of the Invention

Problems to be Solved by the Invention

[0005] This application provides a memory device that is a single transistor-type DRAM without a capacitor, which solves problems such as noise caused by the coupling capacitance between the word line and the body, misreading due to memory instability, and incorrect rewriting of stored data. Further, by introducing a structure in which memory cells are stacked vertically using GAA (Gate All Around) technology (see, for example, Non-Patent Document 10), a semiconductor memory device that realizes a high-density and high-speed MOS circuit is provided.

[0006] In order to solve the above problems, a memory device using a semiconductor element according to the present invention includes: a semiconductor matrix extending in a horizontal direction with respect to a substrate, and a first impurity layer in the extending direction of the semiconductor matrix a first gate oxide film covering a part of the semiconductor matrix and the first impurity layer; a first gate conductor layer covering a part of the first gate insulating layer and being close to the first impurity layer; a second gate insulating layer covering a part of the first semiconductor matrix without contacting the first gate conductor layer; a second gate conductor layer covering a part of the second gate insulating layer without contacting the first gate conductor layer; a second impurity layer formed in a part of the semiconductor matrix between the first gate conductor layer and the second gate conductor layer; and having a memory cell composed of the above (First Invention).

[0007]

[0008] In the first invention described above, by controlling the voltages applied to the bit line, the source line, the word line, and the plate line, an impact ionization phenomenon or a gate-induced drain leakage current is generated by the current flowing between the first impurity layer and the second impurity layer, and electrons and holes are generated in the semiconductor matrix and the second impurity layer. Then, among the generated electrons and holes, some or all of either the electrons or the holes, which are the majority carriers in the semiconductor matrix, are left in the semiconductor matrix to perform a memory write operation. By controlling the voltages applied to the bit line, the source line, the word line, and the plate line, either the electrons or the holes, which are the majority carriers in the remaining semiconductor matrix, are extracted from at least one of the first impurity layer and the second impurity layer to perform a memory erase operation (second invention).

[0009] In the first invention described above, it is characterized in that the work functions of the first gate conductor layer and the second gate conductor layer are different (third invention).

[0010] In the first invention described above, it is characterized in that a semiconductor matrix is included in a vertical cross section of a portion where the second impurity layer is located (fourth invention).

[0011] A plurality of memory cells of the first invention are provided away from the first insulating layer on the substrate such that their central axes are parallel in a direction perpendicular to the substrate. A first conductor layer connected to the plurality of first impurity layers of the plurality of memory cells; A second conductor layer connected to the plurality of second impurity layers of the plurality of memory cells; It is characterized by having (fifth invention).

[0012] The plurality of memory cells of the fifth invention described above are arranged in a plurality in a horizontal direction parallel to the substrate such that the central axes of the respective memory cells are parallel. In the vertical direction of the substrate, the distance between the semiconductor matrices of adjacent memory cells is wider than the distance between the semiconductor matrices of adjacent memory cells in the horizontal direction of the substrate. (Sixth Invention).

[0013] In the sixth invention described above, the first gate conductor layer of the plurality of memory cells is shared by a plurality of adjacent memory cells in the horizontal direction of the substrate (Seventh Invention).

[0014] In the sixth invention described above, the second gate conductor layer is shared by a plurality of cells adjacent to the substrate in the horizontal direction or the vertical direction (Eighth Invention).

[0015] In the fifth invention described above, the contact area between the first conductor layer and the first impurity layer is equal to or larger than the cross-sectional area of the semiconductor matrix connected to the first impurity layer (Ninth Invention).

[0016] In the fifth invention described above, the first impurity layer is shared by adjacent cells in the horizontal direction with respect to the substrate (Tenth Invention).

[0017] In the fifth invention described above, the second conductor layer is shared by adjacent cells in the horizontal direction and is separated from the cells in the vertical direction (Eleventh Invention).

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0019] Hereinafter, the structure, driving method, behavior of stored carriers, cell layout, and wiring structure of a memory device using a semiconductor element according to the present invention will be described with reference to the drawings.

[0020] (First Embodiment) The structure and operation mechanism of a memory cell using the semiconductor element according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3. The cell structure of the memory using the semiconductor element according to the present embodiment will be described with reference to FIG. 1. The writing mechanism and carrier behavior of the memory using the semiconductor element will be described with reference to FIG. 2, and the data erasure mechanism will be described with reference to FIG. 3. In addition, with reference to FIG. 4, an example of the arrangement of four memory cells of the semiconductor device according to the present embodiment will be described, and with reference to FIGS. 5 and 6, the method of developing the memory cell according to the present embodiment will be described.

[0021] FIG. 1 shows the structure of a memory cell using the semiconductor element according to the first embodiment of the present invention. FIG. 1(a) is a plan view, (b) is a cross-sectional view taken along the line X-X' of (a), and (c) shows a bird's-eye view of the memory cell. Above the substrate 20 (an example of the "substrate" in the claims), away from the substrate 20 and in the horizontal direction, there is a p-layer 1 (an example of the "semiconductor matrix" in the claims), which is a silicon semiconductor matrix having a p-type or i-type (intrinsic type) conductivity type containing acceptor impurities. (Hereinafter, the p-layer semiconductor is referred to as the "p-layer".) On one side in the horizontal direction of the p-layer 1, there is an n+ layer 2 (hereinafter, a semiconductor region containing a high concentration of donor impurities is referred to as the "n+ layer"). (An example of the "first impurity layer" in the claims) On a part of the surface of the p-layer 1, there is a gate insulating layer 4 (an example of the "first gate insulating layer" in the claims). Surrounding a part of the gate insulating layer 4, a first gate conductor layer 5 (an example of the "first gate conductor layer" in the claims) is close to the n+ layer 2. Also, without contacting the gate conductor layer 5, on a part of the surface of the p-layer 1, there is a gate insulating layer 6 (an example of the "second gate insulating layer" in the claims). A gate conductor layer 7 (an example of the "second gate conductor layer" in the claims) covers a part of the gate insulating layer 6 without contacting the gate conductor layer 5. Also, from the surface of the p-layer 1 between the gate insulating layer 4 and the gate insulating layer 6, there is an n+ layer 3 (an example of the "second impurity layer" in the claims) so that the p-layer 1 remains inside. Thus, a single dynamic flash memory cell is formed by the p-layer 1, the n+ layer 2, the n+ layer 3, the gate insulating layer 4, the gate insulating layer 6, the gate conductor layer 5, and the gate conductor layer 7.

[0022] Furthermore, the n+ layer 3 is connected to a source line SL (an example of the "source line" in the claims), the gate conductor layer 7 is connected to a plate line PL (an example of the "plate line" in the claims), the n+ layer 2 is connected to a bit line BL (an example of the "bit line" in the claims), and the gate conductor layer 5 is connected to a word line WL (an example of the "word line" in the claims). By operating the potentials of the source line, the bit line, the plate line, and the word line respectively, the memory is operated. This memory device is hereinafter referred to as a dynamic flash memory.

[0023] FIG. 1(c) shows a bird's-eye view of the memory cell structure according to this embodiment.

[0024] In addition, although the n+ layer 3 is formed around the p layer 1 in FIG. 1, as shown in FIG. 1(b), it is necessary that a portion of the p layer 1 remains between the n+ layers 3. Also, in FIG. 1, the n+ layer 3 does not have to cover the entire periphery of the p layer 1, and it is sufficient that the n+ layer 3 exists at the portion in contact with the source line.

[0025] Also, in FIG. 1, the p layer 1 is a p-type semiconductor, but a profile may exist in the impurity concentration. Also, a profile may exist in the impurity concentration of the n+ layer 2 and the n+ layer 3.

[0026] Also, when the n+ layer 2 and the n+ layer 3 are formed of a p+ layer (hereinafter, a semiconductor region containing a high concentration of acceptor impurities is referred to as a "p+ layer") in which holes are the majority carriers, if the p layer 1 is an n-type semiconductor, the operation of the dynamic flash memory is performed by using electrons as the writing carriers.

[0027] Also, the substrate 20 in FIG. 1 can be made of any material as long as it is an insulator, a semiconductor, or a conductor, an insulator is formed thereon, and it can support the memory cell.

[0028] Also, as long as the gate conductor layers 5 and 7 can change the potential of a part of the memory cell through the gate insulating layers 4 and 6 respectively, they may be, for example, metals such as W, Pd, Ru, Al, TiN, TaN, WN, nitrides of metals, or alloys thereof (including silicides), such as a laminated structure like TiN / W / TaN, or may be formed of a semiconductor doped at a high concentration.

[0029] Also, when the majority carriers of the first and second impurity layers are electrons as the semiconductor matrix, it is more effective for the memory operation that the work function of the gate conductor layer 7 is higher than the work function of the gate conductor layer 5, and when the majority carriers of the first and second impurity layers are holes, it is more effective for the memory operation that the work function of the gate conductor layer 7 is lower than the work function of the gate conductor layer 5.

[0030] Alternatively, the gate conductor layer 5 and the gate conductor layer 7 may be formed simultaneously and then separated by using a patterning technique.

[0031] Also, for the gate insulating layer 4 and the gate insulating layer 6, any insulating film used in a normal MOS process, such as an SiO2 film, a SiON film, a HfSiON film, or a laminated film of SiO2 / SiN, can be used.

[0032] Also, the gate insulating layer 4 and the gate insulating film 6 may be formed simultaneously of the same material and then separated by using a separation method.

[0033] Also, in FIG. 1, the memory cell has been described as having a rectangular vertical cross section, but the vertical cross section may be trapezoidal, polygonal, or cylindrical.

[0034] Note that in FIG. 1, the gate conductor layer 5 and the gate conductor layer 7 are each shown as an integral unit, but they may be divided in the horizontal or vertical direction with respect to the substrate 20.

[0035] Using FIG. 2, the carrier behavior, storage, and cell current during the write operation of the dynamic flash memory according to the first embodiment of the present invention will be described. As shown in FIG. 2(a), first, the majority carriers in the n+ layer 2 and the n+ layer 3 are electrons. For example, n+ poly (hereinafter, poly Si containing a high concentration of donor impurities is referred to as "n+ poly") is used for the gate conductor layer 5 connected to the word line WL, and p+ poly (hereinafter, poly Si containing a high concentration of acceptor impurities is referred to as "p+ poly") is used for the gate conductor layer 7 connected to the plate line PL. The case where a p-type semiconductor is used as the p layer 1 will be described. For example, 3V is input to the conductor layer n+ layer 2 to which the bit line BL is connected, 0V is input to the n+ layer 3 to which the source line SL is connected, 1.5V is input to the gate conductor layer 5 connected to the word line WL, and 0V is input to the gate conductor layer 7 connected to the plate line PL.

[0036] In this voltage application state, electrons flow from the n+ layer 3 towards the n+ layer 2. An inversion layer 14 is formed directly under the gate insulating layer 4. Further, the electric field becomes maximum at the pinch-off point 15, and the impact ionization phenomenon occurs in this region. Due to this impact ionization phenomenon, the electrons accelerated from the n+ layer 3 connected to the source line SL towards the n+ layer 2 connected to the bit line BL collide with the Si lattice, and electron-hole pairs are generated by their kinetic energy. A part of the generated electrons flows into the gate conductor layer 5, but most of them flow into the n+ layer 2 connected to the bit line BL.

[0037] Figure 2(b) shows a hole group 17 in the p layer 1 when all biases become 0V immediately after writing. The generated hole group 17 is the majority carrier of the p layer 1 and is accumulated in the p layer 1 partially surrounded by the depletion layer 16 and the p layer 1 surrounded by the gate insulating film 6 without a depletion layer, and in the non-equilibrium state, it substantially charges the p layer 1, which is the substrate of the MOSFET having the gate conductor layer 5, to a positive bias. As a result, the threshold voltage of the MOSFET having the gate conductor layer 5 is lowered by the positive substrate bias effect due to the holes temporarily accumulated in the p layer 1. Thus, as shown in Figure 2(c), the threshold voltage of the MOSFET having the gate conductor layer 5 connected to the word line WL becomes lower than in the neutral state. This write state is assigned to the logical memory data "1". By using a material with a larger work function than the gate conductor layer 5 for the gate conductor layer 7, a depletion layer does not occur at the interface between the gate insulating layer 6 and the p layer 1, and it becomes easier to accumulate surplus holes.

[0038] Note that the voltage conditions applied to the above bit line BL, source line SL, word line WL, and plate line PL are an example for performing the write operation, and other operating voltage conditions that enable the write operation may also be used.

[0039] In addition, the amount of holes to be accumulated is determined by the volume of the p-layer 1 surrounded by the gate conductor layer 7 shown in Fig. 1(b). In order to increase the amount of holes to be accumulated, the cross-sectional area of the P-layer 1 may be increased or the horizontal length of the p-layer 1 may be increased. In particular, by increasing the dimension in the direction perpendicular to the substrate of the p-layer 1, the amount of holes to be accumulated can be increased without sacrificing the area of the memory cell in plan view.

[0040] Note that instead of causing the above impact ionization phenomenon, a gate-induced drain leakage (GIDL) current may be passed to generate a hole group (see, for example, Non-Patent Document 8).

[0041] Next, with reference to Fig. 3, the erasing operation mechanism of the dynamic flash memory of the first embodiment shown in Fig. 1 will be described. From the state shown in Fig. 2(b), a voltage of 0.6 V is applied to the bit line BL, 0 V to the source line SL, 3 V to the plate line PL, and 0 V to the word line WL. As a result, an inversion layer 19 is formed at the interface of the p-layer 1 by the 3 V voltage applied to the plate line and is electrically connected to the n+-layer 3. Since the hole concentration of the p-layer 1 written with "1" is sufficiently higher than that of the n+-layer 3 and the inversion layer 19, holes flow into the n+-layer 3 and the inversion layer 19 by diffusion due to the concentration gradient. Conversely, since the electron concentration of the n+-layer 3 and the inversion layer 19 is higher than the electron concentration of the p-layer 1, electrons 18 flow into the p-layer 1 by diffusion due to the concentration gradient. The electrons flowing into the p-layer 1 recombine with holes in the p-layer 1 and disappear. Note that during erasing, since the inversion layer 19 is formed and electrically connected to the n+-layer 3, the recombination opportunity of holes and electrons can be increased. On the other hand, not all of the injected electrons 18 disappear, and the electrons 18 that do not disappear flow into the n+-layer 2 through the depletion layer 16 by drift due to the potential gradient between the bit line BL and the source line SL. Since electrons are continuously supplied from the source line SL, excess holes recombine with electrons in a very short time and return to the initial state. As a result, as shown in Fig. 3(b), the MOSFET having the gate conductor layer 5 to which this word line WL is connected returns to the original threshold value. The erased state of this memory element becomes the logical memory data "0".

[0042] Note that, regardless of whether the voltage applied to the bit line is higher or lower than 0.6V, as long as the electron drift occurs within the depletion layer 16, it is within the adjustable range. As another data erasure method, the voltage conditions applied to the above bit line BL, source line SL, word line WL, and plate line PL can also be combinations such as 1.5V (BL) / 0V (SL) / 3V (PL) / 0V (WL), 0.6V (BL) / -0.6V (SL) / 3V (PL) / 0V (WL). The voltage conditions applied to the above bit line BL, source line SL, word line WL, and plate line PL are an example for performing the erasure operation, and other operating conditions that can perform the erasure operation may also be used.

[0043] FIG. 4 is a diagram for explaining the cell arrangement of a memory device using the semiconductor element according to the first embodiment. (a) is a plan view, (b) is a vertical cross-sectional view taken along the S-S' line of (a), and (c) and (d) are vertical cross-sectional views taken along the S1-S1' line and S2-S2' line of (a), respectively. In the example of FIG. 4, the above-described dynamic flash memory cells are arranged separately from each other in the vertical direction (hereinafter referred to as the "column direction" or "column", y direction) on the substrate 20 and the insulating layer 21 (an example of the "first insulating layer" in the claims), and they are further arranged in the horizontal direction (hereinafter referred to as the "row direction" or "row", x direction). FIG. 4 shows an example in which the memory cells are arranged in two rows and two columns, but in an actual memory device, more memory cells can be arranged than this.

[0044] A cross-sectional view of two cells arranged in the first column of FIG. 4(b) is shown. As described above, the memory cell in the first row and the first column is composed of a p layer 1aa, an n+ layer 2aa, an n+ layer 3aa, a gate insulating layer 4aa, a gate conductor layer 5a, a gate insulating layer 6aa, and a gate conductor layer 7a. The first row and the second column are composed of a p layer 1ba, an n+ layer 2ba, an n+ layer 3ba, a gate insulating layer 4ba, a gate conductor layer 5b, a gate insulating layer 6ba, and a gate conductor layer 7b to form a memory cell. Further, the n+ layers 2aa and 2ba are connected to a first conductor layer 13a (an example of the "first conductor layer" in the claims). Further, the n+ layers 3aa and 3ba are connected to a second conductor layer 12 (an example of the "second conductor layer" in the claims) to form a memory cell array in the first row. By expanding this in the horizontal direction with respect to the substrate 20 (upward in FIG. 1(a)), a memory device having a total of four memory cells in two rows and two columns can be formed.

[0045] FIG. 4(c) shows a cross-sectional structure of four cell arrays along the line S1 - S1'. As drawing numbers, they are shown in the form of a p layer 1xy and a gate insulating layer 4xy for each cell. Here, x after each number indicates the row and y indicates the column. When this letter is a, it represents the first row or the first column. Similarly, b represents the second row or the second column (hereinafter, these rows and columns may be comprehensively represented only by numbers. For example, the p layer 1aa to p layer 1bb may be comprehensively represented as the p layer 1). The gate conductor layer 5x is shared by the cells in each row direction. For example, in the cells including the p layers 1aa and 1ab, the gate conductor layer 5a is shared. Similarly, in the cells including the p layers 1ba and 1bb, the gate conductor layer 5b is shared.

[0046] Although not shown, similar to the gate conductor layer 5, the gate conductor layer 7a is in contact with the gate insulating layers 6aa and 6ab of the cells in common. Also, the gate conductor layer 7b is in contact with the gate insulating layers 6ba and 6bb of the cells in common.

[0047] Also, if the conductor layer 12 is in contact with the n+ layer 3, it may be separated in the vertical direction similar to the gate conductor layer 5 and the gate conductor layer 7.

[0048] In addition, FIG. 4(d) shows the cross-sectional structure of four cell arrays along the S2-S2' line in the portion of the conductor layer 12. The conductor layer 12 is in common contact with the impurity layers 3aa to 3bb of the cells. Further, a p layer 1 is present in the cross-section of each cell.

[0049] Using FIGS. 5(a) and 5(b), an example of the arrangement of memory cells for realizing a further high-density memory device according to the first embodiment of the present invention is shown. In FIG. 5, (a) is a plan view and (b) is a vertical cross-sectional view taken along S-S' of (a). In FIGS. 5(a) and 5(b), components that are the same as or similar to those in FIG. 1 are labeled with the same numerals only.

[0050] In FIG. 5(a), the p layers 1aa to 1bb in FIG. 4 are comprehensively represented as the p layer 1, the n+ layers 2aa to 2bb are comprehensively represented as the n+ layer 2, the n+ layers 3aa to 3bb are comprehensively represented as the n+ layer 3, the gate insulating layers 4aa to 4bb are comprehensively represented as the gate insulating layer 4, the gate conductor layers 5a to 5b are comprehensively represented as the gate conductor layer 5, and the wiring conductor layers 13a and 13b are represented as the wiring conductor layer 13. FIG. 5(b) shows a cross-sectional view taken along the S-S' line of FIG. 5(a).

[0051] The components placed from the central portion of the conductor layer 12 to the central portion of the conductor layer 13 in FIG. 5(a) are denoted as "CELL". FIG. 5(a) shows an example in which the unit CELLs in FIG. 5(a) are arranged in the forward direction, the left-right reversed direction (denoted as ), and the forward direction from left to right on the insulating layer 21 in contact with the substrate 20, and the conductor layer 13 is shared between adjacent ones, and a total of 4x3 = 12 cells are arranged. Similarly, FIG. 5(b) shows a cross-sectional view in which the unit CELLs in FIG. 5(a) are arranged in the forward direction, the left-right reversed direction, and the forward direction from left to right, and the conductor layer 13 is shared between adjacent ones.

[0052] Note that, although FIG. 5 shows an example in which the memory cells are expanded in the right direction, in FIG. 5(a), the memory cells can also be expanded in the upward direction, and in FIG. 5(b), they can also be expanded in the vertical direction from the substrate 20.

[0053] Also, although FIG. 5 is based on the memory cell of FIG. 1, adjacent cells as shown in FIG. 6 may have the n+ layer 2 connected and a part thereof covered with the conductor layer 12.

[0054] This embodiment has the following features. (Feature 1) The dynamic flash memory according to the first embodiment of the present invention is composed of a semiconductor substrate p layer 1, a first impurity layer 2, a second impurity layer 3, a first gate insulating layer 4, a second gate insulating layer 6, a first gate conductor layer 5, and a second gate conductor layer 7. Due to this structure, the majority carriers generated in the case of writing logical data “1” can be accumulated in the first semiconductor substrate p layer 1 and the number thereof can be increased, so that the information retention time becomes longer. Also, at the time of data erasure, by applying a positive voltage to the second gate conductor layer 7 connected to the plate line PL, an inversion layer is formed at the interface between the second gate insulating layer and the p layer 1, and the recombination area of surplus holes and electrons is widened, making erasure easier. Therefore, the operation margin of the memory can be expanded, the power consumption can be reduced, leading to high-speed operation of the memory.

[0055] (Feature 2) In the dynamic flash memory according to the first embodiment of the present invention, a plurality of memory cells are stacked in the vertical direction of the substrate, and adjacent cells are electrically shielded by the gate conductor layer 5. In the cell arrangement of a conventional memory, when memory cells are arranged at a high density with the minimum line width, the electrical interaction between the memory cells becomes large. On the other hand, if the word line interval of the cells is increased to prevent this interaction, the density of the memory becomes low. According to the first embodiment of the present invention, without changing the planar area, a cell arrangement with less interaction between the memory cells can be achieved, so that a memory cell arrangement with high density and a margin can be achieved.

[0056] (Feature 3) In the dynamic flash memory according to the first embodiment of the present invention, without sacrificing the planar memory density, the vertical thickness and the horizontal length of the p-layer 1 of the memory cell can be freely adjusted. Therefore, the number of carriers during writing can be increased, and the margin of memory operation can be widened.

[0057] (Feature 4) In the dynamic flash memory according to the first embodiment of the present invention, without sacrificing the memory density, the interval between the memory cells in the vertical direction with respect to the substrate can be widened. Therefore, the interval between the gate conductor layers 5 in the vertical direction of each memory can be widened, the parasitic capacitance can be made smaller than in the conventional example, and furthermore, since the vertical film thickness of the gate conductor layer 5 can be substantially increased, the parasitic resistance can be made smaller, contributing to the high-speed operation of the memory.

[0058] (Feature 5) In the dynamic flash memory according to the first embodiment of the present invention, since a plurality of memory cells can be connected to the conductor layer 13 connected to the bit line BL in the vertical direction, compared with the conventional two-dimensional arrangement of memory cells, short wiring can be realized, and the parasitic resistance and parasitic capacitance are reduced compared with the conventional example, enabling the memory to operate at high speed and widening the operation margin of the memory. In the conventional arrangement of memory cells, it is important how many memory cells are connected to the same bit line in order to reduce the planar area. On the other hand, when many cells are connected to the same bit line, the two-dimensional layout dependence of the parasitic resistance and parasitic capacitance increases, resulting in a problem of narrowing the memory operation margin.

[0059] Also, the present invention can be implemented in various embodiments and modifications without departing from the broad spirit and scope of the present invention. In addition, each of the above-described embodiments is for explaining an example of the present invention and does not limit the scope of the present invention. The above examples and modifications can be arbitrarily combined. Furthermore, even if some of the constituent elements of the above embodiments are excluded as necessary, it is still within the scope of the technical idea of the present invention.

Industrial Applicability

[0060] By using a semiconductor element according to the present invention, it is possible to provide a semiconductor memory device having higher density, higher speed, and a higher operation margin than conventional ones.

Explanation of Signs

[0061] 1 Semiconductor substrate 2, 2aa, 2ab, 2ba, 2bb, 2ax, 2bx n+ layer 3, 3aa, 3ab, 3ba, 3bb, 3ax, 3bx n+ layer 4, 4aa, 4ab, 4ba, 4bb, 4ax, 4bx First gate insulating film 5, 5a, 5b First gate conductor layer 6, 6aa, 6ab, 6ba, 6bb, 6ax, 6bx Second gate insulating film 7 Second gate conductor layer 12 First wiring conductor layer 13, 13a, 13b Second wiring conductor layer 14 Inversion layer 15 Pinch-off point 16 Depletion layer 17 Excess holes 18 Injected electrons 19 Inversion layer 20 Substrate 21 First insulating film

Claims

1. a semiconductor matrix extending horizontally with respect to a substrate, a first impurity layer in the extending direction of the semiconductor matrix, a first gate insulating layer covering a part of the semiconductor matrix and a part of the first impurity layer, a first gate conductor layer covering a part of the first gate insulating layer and being close to the first impurity layer, a second gate insulating layer covering a part of the semiconductor matrix without contacting the first gate conductor layer, a second gate conductor layer covering a part of the second gate insulating layer without contacting the first gate conductor layer, a memory cell composed of a second impurity layer formed in a part of the semiconductor matrix between the first gate conductor layer and the second gate conductor layer, the first impurity layer is connected to a bit line, the second impurity layer is connected to a source line, the first gate conductor layer is connected to a word line, the second gate conductor layer is connected to a plate line, and independent voltages are applied to the source line, the bit line, the plate line, and the word line respectively to perform writing and / or erasing of the memory, controlling the voltages applied to the bit line, the source line, the word line, and the plate line, and generating an electron group and a hole group in the semiconductor matrix and the second impurity layer by an impact ionization phenomenon or a gate-induced drain leakage current with the current flowing between the first impurity layer and the second impurity layer, and performing an operation of leaving a part or all of either the electron group or the hole group, which is a majority carrier in the semiconductor matrix, in the semiconductor matrix to perform a memory writing operation, and controlling the voltages applied to the bit line, the source line, the word line, and the plate line, extracting either the electron group or the hole group, which is a majority carrier in the remaining semiconductor matrix, from at least one of the first impurity layer and the second impurity layer to perform a memory erasing operation, A memory device using a semiconductor device characterized by the above.

2. a semiconductor matrix extending horizontally with respect to a substrate, a first impurity layer in the extending direction of the semiconductor matrix, a first gate insulating layer covering a part of the semiconductor matrix and a part of the first impurity layer, a first gate conductor layer covering a part of the first gate insulating layer and being close to the first impurity layer, A second gate insulating layer that covers a part of the semiconductor substrate without contacting the first gate conductor layer, and A second gate conductor layer that covers a part of the second gate insulating layer without contacting the first gate conductor layer, and A second impurity layer formed in a part of the semiconductor substrate between the first gate conductor layer and the second gate conductor layer, constitute a memory cell, The first impurity layer is connected to a bit line, the second impurity layer is connected to a source line, the first gate conductor layer is connected to a word line, the second gate conductor layer is connected to a plate line, and independent voltages are applied to the source line, bit line, plate line, and word line respectively to perform writing and / or erasing of the memory, A memory device using a semiconductor element, characterized in that the work functions of the first gate conductor layer and the second gate conductor layer are different.

3. A memory device using the semiconductor element according to claim 1 or 2, characterized in that the semiconductor substrate is included in a vertical cross-section of a portion where the second impurity layer is located.

4. A plurality of memory cells according to claim 1 or 2 are provided above the first insulating layer on the substrate such that their central axes are parallel in a direction perpendicular to the substrate, A first conductor layer connected to the plurality of first impurity layers of the plurality of memory cells, and A second conductor layer connected to the plurality of second impurity layers of the plurality of memory cells, A memory device using a semiconductor element, characterized by having.

5. The plurality of memory cells according to claim 4 are arranged in a plurality such that their central axes are parallel in a horizontal direction parallel to the substrate, In the vertical direction of the substrate, the distance between the semiconductor substrates of adjacent memory cells is wider than the distance between the semiconductor substrates of adjacent memory cells in the horizontal direction of the substrate, A memory device using a semiconductor element, characterized by this.

6. The first gate conductor layers of the plurality of memory cells are shared by a plurality of adjacent memory cells in the horizontal direction of the substrate, A memory device using the semiconductor element according to claim 5, characterized by this.

7. The second gate conductor layer is shared by a plurality of adjacent cells in a horizontal direction or a vertical direction with respect to the substrate, A memory device using the semiconductor element according to claim 5, characterized by this.

8. The cross-sectional area of the semiconductor substrate where the contact surface between the first conductor layer and the first impurity layer connects to the first impurity layer is equal to or larger than that, A memory device using the semiconductor device according to claim 4, characterized by the above.

9. The first impurity layer is shared by adjacent cells in the horizontal direction with respect to the substrate, A memory device using the semiconductor device according to claim 4, characterized by the above.

10. The second conductor layer is shared by adjacent cells in the horizontal direction and is separated from the cells in the vertical direction, A memory device using the semiconductor device according to claim 4, characterized by the above.

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