Semiconductor device

Abstract

To propose a storage device capable of increasing storage capacity per unit area while ensuring a data retention period.SOLUTION: In a semiconductor device: a plurality of bit lines are divided into some groups and a plurality of word lines are also divided into some groups; and to memory cells connected to the bit lines belonging to one group, the word lines belonging to one group are connected; and further, the plurality of bit lines are controlled to be driven with respect to each group by a plurality of bit line drive circuits; and in addition, on drive circuits including the plurality of bit line drive circuits and the word line drive circuit, a cell array is formed. By stacking the drive circuits and the cell array in an overlapping manner to form a three dimensional stacking, an occupied area of a storage device can be reduced though a plurality of bit line drive circuits are provided.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory device. Further, it relates to a semiconductor device having the memory device.

Background Art

[0002] In recent years, as a material for the active layer of a transistor, metal oxides exhibiting semiconductor characteristics, called oxide semiconductors, which have both high mobility and uniform device characteristics, have attracted attention. Metal oxides are used in various applications. For example, indium oxide is used as a material for pixel electrodes in liquid crystal display devices. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using such metal oxides exhibiting semiconductor characteristics in the channel formation region are already known (Patent Literature 1 and Patent Literature 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, semiconductor memory devices (hereinafter, also simply referred to as memory devices) include DRAM and SRAM classified as volatile memories, mask ROM, EPROM, EE PROM, flash memory, ferroelectric memory, etc., which are classified as non-volatile memories, and use single-crystal semiconductor substrates ​Many of these formed memories have already been put into practical use. Among the above-mentioned storage devices, D RAM has a simple structure that consists of transistors and capacitors (hereinafter also referred to as capacitive elements) to form memory cells, and has fewer semiconductor elements for forming memory cells compared to other storage devices such as SRAM. Therefore, the storage capacity per unit area can be increased compared to other storage devices, and cost reduction can be achieved. As described above, although DRAM is suitable for large storage capacity, in order to suppress the increase in chip size and realize a more highly integrated integrated circuit, it is necessary to increase the storage capacity per unit area as in other storage devices. For this purpose, the area of the capacitive element provided in each memory cell for holding charge must be reduced, and the area of each memory cell must be reduced. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases.

[0005] As described above, DRAM is suitable for large storage capacity, but in order to suppress the increase in chip size and realize a more highly integrated integrated circuit, it is necessary to increase the storage capacity per unit area as in other storage devices. For this purpose, the area of the capacitive element provided in each memory cell for holding charge must be reduced, and the area of each memory cell must be reduced. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases.

[0006] However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases.

[0007] Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases. However, when the capacitance value becomes small due to the reduction in the area of the capacitive element, the difference in the amount of charge between each digital value becomes small. Therefore, if the off-current value of the transistor is high, it is difficult to maintain the accuracy of the data, and the holding period tends to be short. As a result, the frequency of the refresh operation increases and the power consumption increases. Also, when the number of memory cells is increased to achieve a large storage capacity, the number of memory cells connected to one bit line increases, or the distance that one bit line is routed becomes longer. Therefore, since the parasitic capacitance and parasitic resistance of the bit line increase, when the difference in the amount of charge between each digital value becomes small due to the reduction in the area of the capacitive element, it becomes difficult to accurately read the difference in the amount of charge, that is, the data, through the above bit line, and the error rate increases.

[0008] Also, when the number of memory cells is increased, similar to the case of bit lines, the number of memory cells connected to one word line increases, or the distance that one word line is routed becomes longer. Therefore, the parasitic capacitance and parasitic resistance of the word line increase, so that the pulse of the signal input to the word line is delayed, or the potential drop of the word line becomes larger. Therefore, when a signal for controlling the switching of the transistor is supplied to the memory cell via the word line, the memory cell fails to write data, fails to sufficiently hold the data and the data is lost, or the reading time is too long and accurate data cannot be read, etc., and problems occur in the series of operations of writing, holding, and reading data, increasing the error occurrence rate. In view of the above problems, one aspect of the present invention aims to propose a memory device that can increase the storage capacity per unit area while ensuring the data retention period. Alternatively, one aspect of the present invention aims to propose a memory device that can increase the storage capacity per unit area while suppressing the error occurrence rate. Alternatively, one aspect of the present invention aims to realize a highly integrated semiconductor device by using the above memory device. Alternatively, one aspect of the present invention

[0009] aims to realize a highly reliable semiconductor device by using the above memory device. Means for Solving the Problems The inventors of the present invention keep the number of memory cells connected to one bit line small, and instead increase the number of bit lines, so that even when the number of memory cells increases, the parasitic capacitance and parasitic resistance of the bit lines are small.

[0010] I thought that it might be possible to suppress it. However, when the number of bit lines increases, the layout of the cell array composed of a plurality of memory cells becomes a shape that extends long in one direction, and its aspect ratio deviates from 1. When the aspect ratio of the cell array deviates from 1, the versatility of the memory device decreases. Also,

[0011] when designing an integrated circuit using the memory device, the constraints on the layout become large. Therefore, in the memory device according to one aspect of the present invention, a plurality of bit lines are divided into several groups, and a plurality of word lines are also divided into several groups. Then, the word lines belonging to one group are connected to the memory cells connected to the bit lines belonging to one group. Further, the driving of the plurality of bit lines is controlled for each group by a plurality of bit line driving circuits. By the above configuration, it becomes easy to design the layout of the cell array so that the aspect ratio approaches 1.

[0012] Furthermore, in one aspect of the present invention, the cell array is formed on a drive circuit including the plurality of bit line drive circuits and the word line drive circuit. By three-dimensionally overlapping the drive circuit and the cell array, even if a plurality of bit line drive circuits are provided, the occupied area of the memory device can be reduced.

[0013] Specifically, one aspect of the present invention includes a first bit line drive circuit that drives a plurality of first bit lines, a second bit line drive circuit that drives a plurality of second bit lines, a word line drive circuit that drives a plurality of first word lines and a plurality of second word lines, and a first cell having a plurality of first memory cells.

[0014] It has an array and a second cell array having a plurality of second memory cells, and the first memory cell has a gate electrode electrically connected to any one of the plurality of first word lines, and one of a source electrode and a drain electrode is electrically connected to any one of the plurality of first bit lines of the first transistor, and one electrode is electrically connected to the other of the source electrode and the drain electrode of the first transistor of the first capacitor element, and the second memory cell has a gate electrode electrically connected to any one of the plurality of second word lines, and one of a source electrode and a drain electrode is electrically connected to any one of the plurality of second bit lines of the second transistor and one electrode is electrically connected to the other of the source electrode and the drain electrode of the second transistor of the second capacitor element, and the first cell array is provided so as to overlap on the first bit line drive circuit, and the second cell array is provided so as to overlap on the second bit line drive circuit, and is a storage device characterized in that

[0015] In addition, in one aspect of the present invention, a semiconductor such as silicon or germanium is used for a semiconductor element such as a transistor used in a drive circuit. Further, a semiconductor such as an oxide semiconductor having a wider band gap than the above silicon or germanium is used for the transistor included in the memory cell of the cell array

[0016] A transistor using a semiconductor having a wide band gap such as an oxide semiconductor for the active layer has a significantly lower off-current than a transistor using a semiconductor such as silicon or germanium . Therefore, by using the transistor having a significantly low off-current for the memory cell, leakage of charge from the capacitor element can be prevented. Therefore, due to the miniaturization of the memory cell, the capacitor element​ Even if the child becomes smaller, the frequency of refresh operations can be prevented from increasing.

[0017] That is, the first transistor and the second transistor use an oxide semiconductor for an active layer. A memory device including a transistor having the same structure is also one embodiment of the present invention.

[0018] On the other hand, semiconductors such as polycrystalline or single-crystalline silicon or germanium are used for the active layer. Compared to transistors that use the above-mentioned wide band gap semiconductors in the active layer, Therefore, by using the transistor with high mobility in a driver circuit, The storage device can be driven at high speed.

[0019] That is, the first bit line driving circuit, the second bit line driving circuit, and the word line The driving circuit is a transistor that uses polycrystalline or single-crystalline silicon or germanium as the active layer. A storage device having the above structure is also one aspect of the present invention. Effect of the Invention

[0020] The memory device according to one embodiment of the present invention has a feature of reducing the number of elements electrically connected to a bit line. That is, it is possible to reduce the parasitic capacitance of the bit line. By reducing the number of elements electrically connected to the bit line, the bit line can be shortened. In other words, the parasitic resistance of the bit line can be reduced. This reduces the capacitance value (size of the capacitance element) of the capacitance element provided in the memory cell. Even if the data is lost, the data in the memory cell can be retained. The storage capacity per unit area can be increased. With the above configuration, it is possible to increase the memory capacity per unit area while suppressing the error occurrence rate. Alternatively, the semiconductor device according to one aspect of the present invention can increase the integration degree and miniaturize by using the above memory device. Alternatively, the semiconductor device according to one aspect of the present invention can improve the reliability by using the above memory device.

Brief Description of the Drawings

[0021]

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[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present The invention should not be construed as being limited to the description of the embodiments shown below.

[0023] Note that all kinds of semiconductor devices that can use a storage device, such as integrated circuits such as a microprocessor and an image processing circuit, an RF tag, a storage medium, and a semiconductor display device, are included in the scope of the present invention. In addition, semiconductor display devices include liquid crystal display devices, light-emitting devices having a light-emitting element such as an organic light-emitting element (OLED) provided in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc., and semiconductor display devices having circuit elements using a semiconductor film in a pixel portion or a driving circuit are included in the scope thereof.

[0024] (Embodiment 1) First, a storage device according to an aspect of the present invention will be described with reference to FIGS. 1 to 5.

[0025] <Structural example of a storage device> FIG. 1 is a conceptual diagram showing a structural example of a storage device according to an aspect of the present invention. The storage device shown in FIG. 1 includes a word line driving circuit 101 provided using a semiconductor substrate 100, a first bit line driving circuit 102a, a second bit line driving circuit 102b, a third bit line driving circuit 102c, a first cell array 103a provided so as to overlap on the first bit line driving circuit 102a, a second bit line driving circuit 102b, a second cell array 103b provided so as to overlap on the second bit line driving circuit 102b, and a third bit line driving circuit 102c, and a third cell array 103c provided so as to overlap on the third bit line driving circuit 102c. Note that in FIG. 1, the word line driving circuit 101 and the first bit line driving circuit 102a to 102c The bit line driver circuit 102c and the first cell array 103a to the third cell array 103c are Although they are shown spaced apart, they are overlapped in the storage device.

[0026] The semiconductor substrate 100 may be made of silicon, germanium, silicon germanium, carbon, or the like. Semiconductor substrates made of Group 14 elements such as silicon hydride, as well as gallium arsenide and indium phosphide. Compound semiconductor substrates such as SOI substrates can be used. The term "substrate" refers to a substrate having a silicon layer provided on an insulating surface. The present invention also includes a substrate having a semiconductor layer made of a material other than silicon on an insulating surface. The SOI substrate is a semiconductor device that is formed on an insulating substrate such as a glass substrate via an insulating layer. The term "electrode" includes a structure in which a conductor layer is provided.

[0027] In FIG. 1, the memory device has three types of bit line driver circuits and three types of cell arrays. The memory device has k types (k is a natural number of 2 or more) of bit lines. A driver circuit and k types of cell arrays each of which is provided on the corresponding bit line driver circuit. It is also possible to have a configuration having a ray.

[0028] <Example of cell array configuration> FIG. 2 shows an example of the configuration of the cell arrays (first cell array 103a to third cell array 103c). The first cell array 103a shown in FIG. , a plurality of first bit lines 105a, and a plurality of first memory cells 10 arranged in a matrix. Each of the first memory cells 106a has a gate electrode. The source electrode and the drain electrode are electrically connected to any one of the first word lines 104a. A transistor having one pole electrically connected to any one of the first bit lines 105a. 107a, one electrode of which is the source electrode and the drain electrode of the transistor 107a. a capacitor 108a having one electrode electrically connected to a capacitor line and the other electrode electrically connected to a capacitor line; Each of the first word lines 104a is connected to a word line driving circuit 101. In other words, the word line driver circuit 101 controls the potential of the first memory cell 106. A circuit for controlling the switching of a transistor included in the first bit Each of the lines 105a is controlled by the first bit line driving circuit 102a. Specifically, data is written to a specific first memory cell 106a. When performing this, the first bit line 106a electrically connected to the specific first memory cell 106a is The potential of 05a becomes a potential corresponding to the data by the first bit line driving circuit 102a. When data is read from the specific first memory cell 106a, , the potential of the first bit line 105a electrically connected to the specific first memory cell 106a That is, the first bit line driving circuit 1 02a writes data to the first memory cell 106a and reads the data. It is a detour.

[0029] The second cell array 103b and the third cell array 103c shown in FIG. The second cell array 103b has a similar configuration to the array 103a. A second word line 104b, a plurality of second bit lines 105b, and a plurality of It has a second memory cell 106b of a number. Note that the second memory cell 106b has the same circuit configuration as the first memory cell 106a. Specifically, each of the plurality of second memory cells 106b has a gate electrode electrically connected to any one of the plurality of second word lines 104b, and one of the source electrode and the drain electrode is electrically connected to any one of the plurality of second bit lines 105b through a transistor 107b, and a capacitor element 108b having one electrode electrically connected to the other of the source electrode and the drain electrode of the transistor 107b and the other electrode electrically connected to a capacitance line. Also, each of the plurality of second word lines 104b has its potential controlled by a word line driving circuit 101. Also, each of the plurality of second bit lines 10 5b has its potential controlled and its potential discriminated by a second bit line driving circuit 102b. Similarly, the third cell array 103c has a plurality of third word lines 104c, a plurality of third bit lines 105c, and a plurality of third memory cells 106c arranged in a matrix. Note that the third memory cell 106c has the same circuit configuration as the first memory cell 106a and the second memory cell 106b. Specifically, each of the plurality of third memory cells 106c

[0030] has a gate electrode electrically connected to any one of the plurality of third word lines 104c, and one of the source electrode and the drain electrode is electrically connected to any one of the plurality of third bit lines 105c through a transistor 107c, and a capacitor element 108c having one electrode electrically connected to the other of the source electrode and the drain electrode of the transistor 107c and the other electrode electrically connected to a capacitance line. Also, each of the plurality of third word lines 104c has its potential controlled by a word line driving circuit. Specifically, each of the plurality of third memory cells 106c has a gate electrode electrically connected to any one of the plurality of third word lines 104c, and one of the source electrode and the drain electrode is electrically connected to any one of the plurality of third bit lines 105c through a transistor 107c, and a capacitor element 108c having one electrode electrically connected to the other of the source electrode and the drain electrode of the transistor 107c and the other electrode electrically connected to a capacitance line. Also, each of the plurality of third word lines 104c has its potential controlled by a word line driving circuit 101. The potential is controlled by the driving circuit 101. Also, each of the plurality of third bit lines 105c has its potential controlled and its potential discriminated by the third bit line driving circuit 102c.

[0031] <Configuration example of driving circuit> FIG. 3 is a block diagram showing a configuration example of a driving circuit (word line driving circuit 101 and first bit line driving circuits 102a to third bit line driving circuit 102c, etc.). In FIG. 3, circuits classified by function are shown as mutually independent blocks, but in an actual circuit, it is difficult to completely separate them by function, and one circuit may be related to multiple functions.

[0032] The memory device shown in FIG. 3 has a first cell array 103a, a second cell array 103b, a third cell array 103c, and a driving circuit 120. The driving circuit 120 has a word line driving circuit 10 1 and first bit line driving circuits 102a to third bit line driving circuits 102c. Furthermore, the driving circuit 120 has a control circuit 110 that controls the operations of the word line driving circuit 101 and the first bit line driving circuits 102a to third bit line driving circuit 102c.

[0033] Also, the first bit line driving circuit 102a shown in FIG. 3 has a writing circuit 810 that writes data to a selected memory cell in the first cell array 103a, and a reading circuit 811 that generates a signal including the data read from the first cell array 103a as information. And the writing circuit 810 has a decoder 812, a level shifter 813 and a selector 814.

[0034] Note that the second bit line driving circuit 102b and the third bit line driving circuit 102c have their circuit configurations is the same as the first bit line driving circuit 102a. Therefore, for the specific circuit configurations of the second bit line driving circuit 102 b and the third bit line driving circuit 102c, reference can be made to the circuit configuration of the first bit line driving circuit 102a described above.

[0035] Also, the word line driving circuit 101 shown in FIG. 3 includes a decoder 815, a level shifter 816, and a buffer 817.

[0036] Next, a specific operation example of the driving circuit shown in FIG. 3 will be described.

[0037] When a signal AD including an address (Ax, Ay) as information is input to the control circuit 110 shown in FIG. 3, the control circuit 110 determines to which of the first cell array 103a, the second cell array 103b, and the third cell array 103c the memory cell of the above address belongs. And for example, when the memory cell belongs to the first cell array 103a, the address Ax, which is information regarding the column direction of the address, is sent to the first bit line driving circuit 102a corresponding to the first cell array 103a. Also, the control circuit 110 sends a signal DAT A including data as information to the first bit line driving circuit 102a. Further, the address Ay, which is information regarding the row direction of the address, is sent to the word line driving circuit 101.

[0038] The selection of the data writing operation and the reading operation in the first cell array 103a to the third cell array 103c is selected by signals RE (Read enable) and WE (Write enable) supplied to the control circuit 110.

[0039] For example, when a write operation by the signal WE is selected in the first cell array 103a, in accordance with an instruction from the control circuit 110, a signal for selecting a memory cell corresponding to the address Ay is generated in the decoder 815 included in the word line driving circuit 101. After the amplitude of the signal is adjusted by the level shifter 816, the waveform is processed in the buffer 817 and input to the first cell array 103a via the first word line. On the other hand, in the first bit line driving circuit 102a, in accordance with an instruction from the control circuit 110, a signal for selecting a memory cell corresponding to the address Ax among the memory cells selected in the decoder 812 is generated. After the amplitude of the signal is adjusted by the level shifter 813, the signal is input to the selector 814.

[0040] In the selector 814, the signal DATA is sampled according to the input signal, and the sampled signal is input to the memory cell corresponding to the address (Ax, Ay).

[0041] When a read operation is selected by the signal RE, in accordance with an instruction from the control circuit 110, a signal for selecting a memory cell corresponding to the address Ay is generated in the decoder 815 included in the word line driving circuit 101. After the amplitude of the signal is adjusted by the level shifter 816, the waveform is processed in the buffer 817 and input to the first cell array 103a. On the other hand, the read circuit 811 included in the first bit line driving circuit 102a selects a memory cell corresponding to the address Ax among the memory cells selected by the decoder 815 in accordance with an instruction from the control circuit 110. Then, the read circuit 811 reads the data stored in the selected memory cell and outputs it to the control circuit 110 after being amplified by the amplifier 818. ​​​Read the data stored in the memory cell corresponding to the response (Ax, Ay), and generate a signal including the data as information.

[0042] Note that the memory device according to one aspect of the present invention may be in a so-called packaged state where connection terminals that can be mounted on a printed wiring board or the like are provided and are protected with resin or the like. That is, it may be in a state where connection terminals that can be mounted on a printed wiring board or the like are provided and are protected with resin or the like. That's okay.

[0043] Also, the control circuit 110 may be formed using a single substrate together with other circuits (word line drive circuit 101 and first bit line drive circuit 102a to third bit line drive circuit 102c and first cell array 1 03a to third cell array 103c) that constitute the memory device, or may be formed using different substrates. That is, it may be formed using a single substrate together with other circuits (word line drive circuit 101 and first bit line drive circuit 102a to third bit line drive circuit 102c and first cell array 1 03a to third cell array 103c) that constitute the memory device, or may be formed using different substrates.

[0044] When using different substrates, electrical connection can be ensured via an FPC (Flexible Printed Circuit it) or the like. In this case, a part of the control circuit 110 may be connected to the FPC using the COF (Chip On Film) method. That is, a part of the control circuit 110 may be connected to the FPC using the COF (Chip On Film) method. Alternatively, electrical connection can be ensured using the COG (Chip On Glass) method. That is, electrical connection can be ensured using the COG (Chip On Glass) method.

[0045] <Configuration example of the read circuit> Next, a specific configuration example of the read circuit will be described.

[0046] The potential read from the cell array is determined according to the data written in the memory cell, and its level is determined accordingly. Therefore, ideally, if the same digital value data is stored in a plurality of memory cells, the potentials read from the plurality of memory cells are all at the same level. The potential read from the cell array is determined according to the data written in the memory cell, and its level is determined accordingly. Therefore, ideally, if the same digital value data is stored in a plurality of memory cells, the potentials read from the plurality of memory cells are all at the same level. stored, then the potentials read from the plurality of memory cells are all at the same level. is. However, in reality, the characteristics of the capacitive element and the transistor functioning as a switching element may vary between memory cells. In this case, even if all the data to be read out are the same digital value, there is a variation in the actually read potential, so its distribution has a width. However, the read circuit can include more accurate data as information even if there is some variation in the potential read from the cell array, and can form a signal whose amplitude and waveform are processed according to the desired specifications.

[0047] FIG. 4 is a circuit diagram showing a configuration example of a read circuit. The read circuit shown in FIG. 4 has a transistor 260 that functions as a switching element for controlling the input of the potential Vdata read from the cell array to the read circuit. Also, the read circuit shown in FIG. 4 has an operational amplifier 262.

[0048] The transistor 260 that functions as a switching element controls the supply of the potential Vdata to the non-inverting input terminal (+) of the operational amplifier 262 according to the potential of the signal Sig applied to its gate electrode. For example, when the transistor 260 is turned on, the potential Vdata is applied to the non-inverting input terminal (+) of the operational amplifier 262. On the other hand, a reference potential Vref is applied to the inverting input terminal (-) of the operational amplifier 262. Then, depending on whether the potential applied to the non-inverting input terminal (+) is higher or lower than the reference potential Vref, the level of the potential Vout at the output terminal can be made different, thereby indirectly

[0049] Even for memory cells storing data of the same value, due to the variation in characteristics between memory cells, the level of the read potential Vdata also varies, and its distribution may have a width. Therefore, the level of the reference potential Vref is determined in consideration of the variation in the potential Vdata in order to accurately read the value of the data.

[0050] Also, in FIG. 4, since it is an example of a read circuit for handling binary digital values, one operational amplifier is used for each node to which the potential Vdata is applied, but the number of operational amplifiers is not limited to this. When handling n-valued (n is a natural number of 2 or more) data, the number of operational amplifiers for the nodes to which the potential Vdata is applied is set to n - 1.

[0051] <Example of the cross-sectional structure of the memory device> FIG. 5 is a cross-sectional view showing an example of the structure of the memory device. The memory device shown in FIG. 5 has a cell array 201 in which a plurality of memory cells 670 are provided in the upper part, and a drive circuit 210 in the lower part. The upper cell array 201 has a transistor 662 using an oxide semiconductor, and the lower drive circuit 210 has a transistor 660 using a semiconductor such as polycrystalline or single-crystalline silicon or germanium.

[0052] Either an n-channel type transistor or a p-channel type transistor can be used for the transistor 660 and the transistor 662. Here, the case where both the transistor 660 and the transistor 662 are of the n-channel type will be taken as an example for the following explanation.

[0053] The transistor 660 is provided on a substrate 600 containing a semiconductor such as silicon or germanium.​​​​​​​​​​​​ formed channel formation region 616 and impurities provided so as to sandwich the channel formation region 616 region 620, a metal compound region 624 in contact with the impurity region 620, and a channel formation region 6 16, a gate insulating film 608 provided thereon, and a gate electrode provided on the gate insulating film 608 610, and source electrodes or drain electrodes 6 30a, 630b. Further, an insulating film 628 is provided so as to cover the transistor 660. The source electrodes or drain electrodes 630a, 630b are electrically connected to the metal compound region 624 through openings formed in the insulating film 628. Also, on the insulating film 628, an electrode 636a is formed in contact with the source electrode or drain electrode 630a, and an electrode 636b is formed in contact with the source electrode or drain electrode 630b. An element isolation insulating layer 606 is provided on the substrate 600 so as to surround the transistor 660. In order to achieve high integration, it is desirable that the transistor 660 has a configuration without a sidewall insulating film as shown in FIG. 5. On the other hand, when emphasizing the characteristics of the transistor 66 0, a sidewall insulating film is provided on the side surface of the gate electrode 610, and an impurity region 620 may be provided including regions having different impurity concentrations formed in a region overlapping with the sidewall insulating film. The transistor 662 includes an oxide semiconductor film 644 and source electrodes or drain electrodes 642a, 642b electrically connected to the oxide semiconductor film 644 on an insulating film 640 covering the electrodes 636a and 636b. formed, and source electrodes or drain electrodes 630b.

[0054] Also, an element isolation insulating layer 606 is provided on the substrate 600 so as to surround the transistor 660. In order to achieve high integration, it is desirable that the transistor 660 has a configuration without a sidewall insulating film as shown in FIG. 5. On the other hand, when emphasizing the characteristics of the transistor 66 0, a sidewall insulating film is provided on the side surface of the gate electrode 610, and an impurity region 620 may be provided including regions having different impurity concentrations formed in a region overlapping with the sidewall insulating film. 0, a sidewall insulating film is provided on the side surface of the gate electrode 610, and an impurity region 620 may be provided including regions having different impurity concentrations formed in a region overlapping with the sidewall insulating film. including regions having different impurity concentrations formed in a region overlapping with the sidewall insulating film. The impurity region 620 may be provided.

[0055] The transistor 662 includes an oxide semiconductor film 644 and source electrodes or drain electrodes 642a, 642b electrically connected to the oxide semiconductor film 644 on an insulating film 640 covering the electrodes 636a and 636b. On the insulating film 640 covering the electrodes 636a and 636b, an oxide semiconductor film 644, a source electrode or drain electrode 642a, 642b electrically connected to the oxide semiconductor film 644, and a source electrode or drain electrode 642a, 642b electrically connected to the oxide semiconductor film 644 are provided. On the insulating film 640 covering the electrodes 636a and 636b, an oxide semiconductor film 644, a source electrode or drain electrode 642a, 642b electrically connected to the oxide semiconductor film 644, and a source electrode or drain electrode 642a, 642b electrically connected to the oxide semiconductor film 644 are provided. It has a gate insulating film 646 that covers the drain electrodes 642a and 642b, and a gate electrode 648a provided so as to overlap with the oxide semiconductor film 644 on the gate insulating film 646. .

[0056] The oxide semiconductor film 644 has a measured hydrogen concentration by secondary ion mass spectrometry (SIMS) of 5×10 / 19 / cm 3 or less, preferably 5×10 18 / cm 3 or less, more preferably 5×10 17 / cm 3 or less, still more preferably 1×10 16 / cm 3 or less. Also, the carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 / cm 14 / cm 3 less than, preferably 1 ×10 12 / cm 3 less than, still more preferably 1×10 11 / cm 3 less than. Also, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film with sufficiently reduced impurity concentrations such as moisture or hydrogen and highly purified, the off-current of the transistor 662 can be reduced. .

[0057] Here, the analysis of the hydrogen concentration in the oxide semiconductor film will be described. The measurement of the hydrogen concentration in the oxide semiconductor film and the conductive film is performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). SIMS analysis, in principle, Ion Mass Spectrometry). ​​​It is known that it is difficult to accurately obtain data near the sample surface or near the laminated interface with a film of a different material. Therefore, when analyzing the thickness-direction distribution of the hydrogen concentration in a film by SIMS, in the range where the target film exists, the average value in the region where there is no extreme fluctuation in the value and a substantially constant value is obtained is adopted as the hydrogen concentration. Also, when the thickness of the film to be measured is small, there may be a case where a region where a substantially constant value can be obtained cannot be found due to the influence of the hydrogen concentration in the adjacent film. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is adopted as the hydrogen concentration in the film. Furthermore, when there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value in the region where the film exists, the value at the inflection point is adopted as the hydrogen concentration. Specifically, the fact that the off-current of a transistor using a highly purified oxide semiconductor film as an active layer is low can be proven by various experiments. For example, even in an element with a channel width of 1×10 μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. In this case it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element by the transistor is used to measure the off-current density. In this measurement, the above transistor is made of a highly purified oxide In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration. In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration.

[0058] Specifically, the fact that the off-current of a transistor using a highly purified oxide semiconductor film as an active layer is low can be proven by various experiments. For example, even in an element with a channel width of 1×10 6 μm and a channel length of 10 μm, in the range where the voltage between the source electrode and the drain electrode (drain voltage) is from 1 V to 10 V, the off-current can be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. In this case it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 -13 zA / μm or less. Also, a circuit that connects a capacitor element and a transistor and controls the charge flowing into or out of the capacitor element by the transistor is used to measure the off-current density. In this measurement, the above transistor is made of a highly purified oxide In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration. In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration. In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration. In the region where there are no peak-shaped peaks with a maximum value or valley-shaped peaks with a minimum value, the value at the inflection point is adopted as the hydrogen concentration. A semiconductor film is used for the channel formation region, and the off-current density of the transistor is measured from the change in the amount of charge per unit time of the capacitor element. As a result, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, an even lower off-current density of several tens of yA / μm was obtained. It was found that. Therefore, in the semiconductor device according to one aspect of the present invention, the off-current density of a transistor using a highly purified oxide semiconductor film as an active layer is, depending on the voltage between the source electrode and the drain electrode, 100 yA / μm or less, preferably 10 yA / μm or less, and more preferably 1 yA / μm or less. Therefore, a transistor using a highly purified oxide semiconductor film as an active layer has a significantly lower off-current than a transistor using crystalline silicon. Note that the transistor 662 uses an oxide semiconductor film processed into an island shape in order to suppress leakage generated between elements due to miniaturization, but a configuration that is not processed into an island shape may be adopted. When the oxide semiconductor film is not processed into an island shape, the number of masks can be reduced. The capacitor element 664 is composed of a source electrode or a drain electrode 642a, a gate insulating film 646, and a conductive film 648b. That is, the source electrode or the drain electrode 642a functions as one electrode of the capacitor element 664, and the conductive film 648b functions as the other electrode of the capacitor element 664. By adopting such a configuration, a sufficient capacitance can be ensured.

[0059] Note that in the transistor 662 and the capacitor element 664, the source electrode or the drain electrode is used. However, a configuration that is not processed into an island shape may be adopted. When the oxide semiconductor film is not processed into an island shape, the number of masks can be reduced. Note that in the transistor 662 and the capacitor element 664, the source electrode or the drain electrode

[0060] The capacitor element 664 is composed of a source electrode or a drain electrode 642a, a gate insulating film 646, and a conductive film 648b. That is, the source electrode or the drain electrode 642a functions as one electrode of the capacitor element 664, and the conductive film 648b functions as the other electrode of the capacitor element 664. By adopting such a configuration, a sufficient capacitance can be ensured. Note that in the transistor 662 and the capacitor element 664, the source electrode or the drain electrode Note that in the transistor 662 and the capacitor element 664, the source electrode or the drain electrode

[0061] In the transistor 662 and the capacitor element 664, the source electrode or the drain electrode The ends of 642a and 642b are preferably tapered. The source electrode or the ends of the drain electrode 642a and the source electrode or drain electrode 642b are tapered so as to improve the coverage of the gate insulating film 646 and prevent the gate insulating film from breaking at the above ends. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle refers to the inclination angle formed by the side surface and the bottom surface of a film having a tapered shape (for example, the source electrode or drain electrode 642a) when observed from a direction perpendicular to its cross-section (a plane perpendicular to the surface of the substrate).

[0062] An insulating film 650 and an insulating film 652 are provided over the transistor 662 and the capacitor element 664. Electrodes 654a and 654b are provided in openings formed in the gate insulating film 646, the insulating film 650, the insulating film 652, etc., and wirings 656 that connect to the electrodes 654a and 6 54b are formed over the insulating film 652. The wiring 656 is a wiring that connects one memory cell to another memory cell. Also, the wiring 656 is connected to the electrode 636c via the electrode 654b, the electrode 642c, and the electrode 626. With the above configuration, the lower drive circuit 210 and the upper cell array 201 can be connected. Note that in FIG. 5, the case where the electrode 642c is electrically connected to the electrode 636c via the electrode 626 is shown, but a structure may be adopted in which an opening is provided in the insulating film 640 and the electrode 642c and the electrode 636c are in direct contact with each other.

[0063] Note that in FIG. 5, an example in which a single-layer cell array 201 is stacked over the drive circuit 210 is shown, but one aspect of the present invention is not limited to this, and two or more cell arrays may be stacked. This is also possible. That is, the cell array 201 can be configured using a plurality of cell array layers. The second cell array layer is provided above the first cell array layer. The same applies to the third and higher cell array layers. Also, for the second and higher cell array layers, the same configuration as the first cell array layer can be applied. Alternatively, for the second and higher cell array layers, a configuration different from that of the first cell array layer can also be applied. By applying such a stacked structure, further integration of the memory device can be achieved.

[0064] <Regarding the memory device disclosed in this specification> In the memory device disclosed in this specification, by increasing the number of bit lines, even if the number of memory cells increases, the number of memory cells connected to one bit line can be kept small. Therefore, the parasitic capacitance and parasitic resistance of the bit lines can be reduced. Thus, even if the difference in the amount of charge between digital values becomes small due to the reduction in the area of the capacitive elements, the accuracy of the data read through the above bit lines can be improved, and the error occurrence rate can be kept low.

[0065] In addition, the memory device disclosed in this specification divides a plurality of bit lines into several groups, and controls the driving of the bit lines for each group by a plurality of bit line driving circuits. With the above configuration, even if the number of bit lines increases, the aspect ratio of the cell array can be prevented from deviating extremely from 1. Therefore, the versatility of the memory device can be enhanced. Also, when designing an integrated circuit using the memory device, the constraints on the layout can be reduced.

[0066] ​In addition, the memory device disclosed in this specification divides a plurality of word lines into several groups, and memory cells connected to bit lines belonging to one group are connected to word lines belonging to one group. With the above configuration, even if the number of memory cells increases, the number of memory cells connected to one word line can be kept small. Therefore, the parasitic capacitance and parasitic resistance of the word lines can be reduced, so that the pulse of the signal input to the word line is delayed, or the potential drop of the word line is prevented from increasing, and thus the error occurrence rate of the memory device can be kept low.

[0067] In addition, the memory device disclosed in this specification uses a transistor with extremely low off-current as a switching element for holding the charge stored in the capacitive element, so that the leakage of the charge from the capacitive element can be prevented. Therefore, long-term data retention becomes possible, and even if the capacitance value of the capacitive element becomes small due to miniaturization of the memory cell, the frequency of the refresh operation can be prevented from increasing.

[0068] In addition, in the memory device disclosed in this specification, by three-dimensionally arranging the drive circuit and the cell array so as to overlap, even if a plurality of bit line drive circuits are provided, the occupied area of the memory device can be reduced.

[0069] <Modification example of transistor> FIGS. 6 and 7 show configuration examples of transistors different from the transistor 662 shown in FIG. 5.

[0070] The transistor 312 shown in FIG. 6(A) includes an oxide semiconductor film 644 and a source electrode or a drain. ​​​​​Oxide conductive films 643a and 643b that function as a source region or a drain region are provided between the rain electrodes 642a and 642b. By providing oxide conductive films 643a and 643b between the oxide semiconductor film 644 and the source electrode or the drain electrodes 642a and 642b that function as a source region or a drain region, the source region and the drain region can be made to have a lower resistance, and the transistor 312 can be operated at high speed. Also, by laminating the oxide semiconductor film 644, the oxide conductive films 643a and 643b, and the source electrode or the drain electrodes 642a and 642b, the breakdown voltage of the transistor 312 can be improved. Further, the capacitor element 314 is composed of the oxide conductive film 643b, the source electrode or the drain electrode 642b, the gate insulating film 646, and the conductive film 648b.

[0071] The transistor 322 shown in FIG. 6(B) is common to FIG. 6(A) in that oxide conductive films 643a and 643b that function as a source region or a drain region are provided between the oxide semiconductor film 644 and the source electrode or the drain electrodes 642a and 642b. In the transistor 312 shown in FIG. 6(A), the oxide conductive films 643a and 643b are in contact with the upper surface and the side surface of the oxide semiconductor film 644, whereas in the transistor 322 shown in FIG. 6(B), the oxide conductive films 643a and 643b are in contact with the upper surface of the oxide semiconductor film 644. Even in such a configuration, the source region and the drain region can be made to have a lower resistance, and the transistor 322 can be operated at high speed. Also, the oxide semiconductor film 644 and the oxide conductive films 643a and 643b and the source electrode or the drain electrodes 642a and 64 Even in such a configuration, the source region and the drain region can be made to have a lower resistance, and the transistor 322 can be operated at high speed. Also, the oxide semiconductor film 644 and the oxide conductive films 643a and 643b and the source electrode or the drain electrodes 642a and 64 By laminating with 2b, the breakdown voltage of the transistor 322 can be improved. Also, Regarding the configuration of the capacitive element 324, the description in FIG. 5 can be referred to.

[0072] The transistor 332 shown in FIG. 7(A) is common to the transistor 662 shown in FIG. 5 in that it includes source electrodes or drain electrodes 642a, 642b, an oxide semiconductor film 644, a gate insulating film 646, and a gate electrode 64 8a. The difference between the transistor 332 shown in FIG. 7(A) and the transistor 662 shown in FIG. 5 lies in the position where the oxide semiconductor film 644 connects to the source electrodes or drain electrodes 642a, 642b. That is, in the transistor 662, after forming the oxide semiconductor film 644, by forming the source electrodes or drain electrodes 642a, 642b, at least a part of the upper surface of the oxide semiconductor film 644 is in contact with the source electrodes or drain electrodes 642a, 642b. In contrast, in the transistor 332, a part of the upper surface of the source electrodes or drain electrodes 642a, 642b is in contact with the oxide semiconductor film 644. Also, regarding the configuration of the capacitive element 334, the description in FIG. 5 can be referred to.

[0073] In FIGS. 5, 6, and 7(A), transistors with a top gate structure are shown, but a bottom gate structure may also be used. FIGS. 7(B) and 7(C) show transistors with a bottom gate structure.

[0074] The transistor 342 shown in FIG. 7(B) has a gate electrode 648a provided on the insulating film 640, a gate insulating film 646 provided on the gate electrode 648a, and on the gate insulating film 646 ​​​​A source electrode or drain electrode 642a, 642b is provided, and a gate insulating film 646, and an oxide semiconductor film 644 is provided so as to overlap with a gate electrode 648a on the source electrode or drain electrode 642a, 642b. Further, the capacitor element 344 is composed of a conductive film 648b provided on the insulating film 64 0, the gate insulating film 646, and the source electrode or drain electrode 642b.

[0075] Also, an insulating film 650 and an insulating film 652 may be provided on the transistor 342 and the capacitor element 344.

[0076] The transistor 352 shown in FIG. 7(C) is common to the transistor 342 shown in FIG. 7(B) in that it includes a gate electrode 648a, a gate insulating film 646, a source electrode or drain electrode 642a, 642b, and an oxide semiconductor film 6 44 on the insulating film 640. The difference between the transistor 352 shown in FIG. 7(C) and the transistor 342 shown in FIG. 7(B) is the position where the oxide semiconductor film 644 and the source electrode or drain electrode 642a, 642b are in contact. That is, in the transistor 342, after forming the source electrode or drain electrode 642a, 642 b, by forming the oxide semiconductor film 644, at least a part of the lower surface of the oxide semiconductor film 64 4 is in contact with the source electrode or drain electrode 642a, 642b. In contrast, in the transistor 352, a part of the lower surface of the source electrode or drain electrode 642a, 642b is in contact with the oxide semiconductor film 644. Also, regarding the configuration of the capacitor element 354, the description in FIG. 7(B) can be referred to.

[0077] ​​​​​​Further, the structure of the transistor may be a dual-gate structure having two gate electrodes disposed via gate insulating films above and below the channel formation region. Figure 7(D) shows a transistor with a dual-gate structure.

[0078] The transistor 362 shown in Figure 7(D) is common to the transistor 342 shown in Figure 7(B) in that it includes a gate electrode 648a, a gate insulating film 646, source electrodes or drain electrodes 642a and 642b, and an oxide semiconductor film 644 on an insulating film 640. In Figure 7(D), further, an insulating film 650 is provided so as to cover the source electrodes or drain electrodes 642a and 642b and the oxide semiconductor film 644, and a conductive film 659 is provided on the insulating film 650 so as to overlap the oxide semiconductor film 644. The insulating film 650 functions as a second gate insulating film, and the conductive film 659 functions as a second gate electrode. By adopting such a structure, in a bias-temperature stress test (hereinafter referred to as a BT test) for examining the reliability of the transistor, the amount of change in the threshold voltage of the transistor before and after the BT test can be further reduced. The potential of the conductive film 659 may be the same as that of the gate electrode 648a or different. Further, the potential of the conductive film 659 may be in a GND, 0V, or floating state.

[0079] <An example of a method for manufacturing a transistor> Next, an example of a method for manufacturing the transistor 662 shown in Figure 5 will be described with reference to Figure 8.

[0080] First, an oxide semiconductor film is formed on the insulating film 640, and the oxide semiconductor film is processed to form an oxide semiconductor film 644 (see Figure 8(A)). ​​​​​​​​​​​​

[0081] The insulating film 640 is formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, etc. By using a material with a low dielectric constant (low-k) for the insulating film 640, it is possible to sufficiently reduce the capacitance caused by the overlap of various electrodes and wirings, which is preferable. Note that a porous insulating layer using the above-described materials may be applied to the insulating film 640. In the porous insulating layer, since the dielectric constant is lower compared to a dense insulating layer, it is possible to further reduce the capacitance caused by electrodes and wirings. Moreover, the insulating film 640 can also be formed using an organic insulating material such as polyimide or acrylic. The insulating film 640 can be formed in a single-layer structure or a laminated structure using the above-described materials. Here, the case where silicon oxide is used as the insulating film 640 will be described.

[0082] Note that as the oxide semiconductor to be used, it is preferably contained at least indium (In) or zinc (Zn ). In particular, it is preferably contained In and Zn. Further, as a stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferably further provided with gallium (Ga). Further, it is preferably provided with tin (Sn) as a stabilizer. Further, it is preferably provided with hafnium (Hf) as a stabilizer. Further, it is preferably provided with aluminum (Al) as a stabilizer. (Sn)

[0083] Further, as another stabilizer, lanthanum (La), cerium, which are lanthanoids ​​​​​​​​​​(Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol mium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lut etium (Lu) may have any one or more of them.

[0084] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn system oxide, Sn-Zn system oxide, Al-Zn system oxide, Zn-Mg system oxide, Sn-Mg system oxide, In-Mg system oxide, In-Ga system oxide, ternary metal oxides such as In-Ga-Zn system oxide (also denoted as IGZO), In-Al-Zn system oxide, In-Sn-Zn system oxide, Sn-Ga-Zn system oxide, Al-Ga-Zn system acid oxide, Sn-Al-Zn system oxide, In-Hf-Zn system oxide, In-La-Zn system oxide such as In-Ce-Zn system oxide, In-Pr-Zn system oxide, In-Nd-Zn system oxide such as In-Sm-Zn system oxide, In-Eu-Zn system oxide, In-Gd-Zn system oxide, In-Tb-Zn system oxide, In-Dy-Zn system oxide, In-Ho-Zn system oxide, I n-Er-Zn system oxide, In-Tm-Zn system oxide, In-Yb-Zn system oxide, In -Lu-Zn system oxide, quaternary metal oxides such as In-Sn-Ga-Zn system oxide, I n-Hf-Ga-Zn system oxide, In-Al-Ga-Zn system oxide, In-Sn-Al- Zn system oxide, In-Sn-Hf-Zn system oxide, In-Hf-Al-Zn system oxide can be used.

[0085] ​Here, for example, the In-Ga-Zn-based oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn is not limited. Also, other metal elements may be contained in addition to In, Ga, and Zn.

[0086] Also, as the oxide semiconductor, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, In3SnO5 (ZnO) n (n > 0 and n is an integer) may be used.

[0087] For example, In-Ga-Zn-based oxides with an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G a:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) and oxides in the vicinity of their compositions can be used. Alternatively, In:Sn:Zn = 1 :1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3:1 / 6:1 / 2) or In:Sn:Zn = 2:1:5 (= 1 / 4:1 / 8:5 / 8) of In-Sn-Zn-based oxides and oxides in the vicinity of their compositions may be used.

[0088] However, it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Also, in order to obtain the required semiconductor characteristics, it is preferable to make the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, etc. appropriate.

[0089] ​​​​​​​For example, in an In-Sn-Zn-based oxide, a relatively high mobility can be obtained relatively easily. However, even in an In-Ga-Zn-based oxide, the mobility can be increased by reducing the density of defects in the bulk.

[0090] Note that, for example, an oxide with an atomic ratio of In, Ga, and Zn of In:Ga:Zn = a:b:c (a + b + c = 1) is in the vicinity of r of an oxide with an atomic ratio of In:Ga:Zn = A:B:C (A + B + C = 1) means that a, b, and c satisfy (a - A) 2 + (b - B) 2 + (c - C) 2 ≤ r 2 . For r, for example, 0.05 may be used. The same applies to other oxides.

[0091] The oxide semiconductor may be single crystal or polycrystal. In the latter case, it may be amorphous or polycrystalline. It may also have a structure including a crystalline portion in the amorphous state or may be non-amorphous.

[0092] An amorphous oxide semiconductor can relatively easily obtain a flat surface, so that interface scattering when manufacturing a transistor using this can be reduced, and relatively high mobility can be relatively easily obtained.

[0093] In addition, in a crystalline oxide semiconductor, more defects in the bulk can be reduced, and if the flatness of the surface is increased, mobility higher than that of an amorphous oxide semiconductor can be obtained. In order to increase the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably ​​​​​It may be formed on a surface of 0.1 nm or less.

[0094] Note that Ra is the center line average roughness defined in JIS B0601 extended three-dimensionally so as to be applicable to a surface, and can be expressed as "a value obtained by averaging the absolute values of the deviations from the reference surface to the specified surface" and is defined by the following formula. Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope). Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope).

[0095]

Equation

[0096] Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope). Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope). Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope). Note that in the above, S0 refers to the area of the measurement surface (a rectangular region surrounded by four points represented by coordinates (x1,y1), (x1,y2), (x2,y1), and (x2,y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope).

[0097] In addition, the oxide semiconductor film is preferably formed in such a way that impurities such as hydrogen, water, hydroxyl groups, or hydrides are less likely to be mixed in. The oxide semiconductor film can be formed, for example, using a sputtering method or the like. In addition, the oxide semiconductor film is preferably formed in such a way that impurities such as hydrogen, water, hydroxyl groups, or hydrides are less likely to be mixed in. The oxide semiconductor film can be formed, for example, using a sputtering method or the like. In addition, the oxide semiconductor film is preferably formed in such a way that impurities such as hydrogen, water, hydroxyl groups, or hydrides are less likely to be mixed in. The oxide semiconductor film can be formed, for example, using a sputtering method or the like.

[0098] Here, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-based oxide target. Here, the oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-based oxide target.

[0099] As the In-Ga-Zn-based oxide target, for example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio] can be used. Note that it is not necessary to limit the material and composition of the target as described above. For example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used. As the In-Ga-Zn-based oxide target, for example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio] can be used. Note that it is not necessary to limit the material and composition of the target as described above. For example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used. As the In-Ga-Zn-based oxide target, for example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio] can be used. Note that it is not necessary to limit the material and composition of the target as described above. For example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used. As the In-Ga-Zn-based oxide target, for example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:1 [mole ratio] can be used. Note that it is not necessary to limit the material and composition of the target as described above. For example, an oxide target with a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] can be used. It can also be done.

[0100] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9 % or less. By using a metal oxide target with a high filling rate, the formed oxide semiconductor film can be made into a dense film.

[0101] The film formation atmosphere may be an inert gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of an inert gas and oxygen, etc. Also, in order to prevent the mixing of hydrogen, water, hydroxyl groups , hydrides, etc. into the oxide semiconductor film, it is desirable to use an atmosphere of a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently removed.

[0102] For example, the oxide semiconductor film can be formed as follows.

[0103] First, a substrate is held in a film formation chamber maintained in a reduced pressure state, and the substrate temperature is higher than 200 °C and 5 00 °C or lower, preferably higher than 300 °C and 500 °C or lower, more preferably 350 °C or higher and 4 50 °C or lower, and it is heated.

[0104] Next, while removing the residual moisture in the film formation chamber, a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently removed is introduced, and an oxide semiconductor film is formed on the substrate using the above target. In order to remove the residual moisture in the film formation chamber, as an exhaust means, it is desirable to use an adsorption type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Also, the exhaust means may be a turbo pump with a cold trap added thereto. The film formation chamber evacuated using a cryopump, for example, contains hydrogen, water, hydroxyl groups, or hydrogen in it. Since impurities such as compounds (more preferably compounds containing carbon atoms) have been removed the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0105] When the substrate temperature during film formation is low (for example, 100°C or lower), there is a risk that substances containing hydrogen atoms may be mixed into the oxide semiconductor. Therefore, it is preferable to heat the substrate at the above-described temperature. By heating the substrate at the above-described temperature and forming the oxide semiconductor film, the substrate temperature becomes high. As a result, hydrogen bonds are broken by heat, and substances containing hydrogen atoms are less likely to be incorporated into the oxide semiconductor film. Therefore, by forming the oxide semiconductor film while the substrate is heated at the above-described temperature, the concentration of impurities such as hydrogen, water, hydroxyl groups, or hydrides contained in the oxide semiconductor film can be sufficiently reduced. Also, damage due to sputtering can be reduced.

[0106] As an example of the film formation conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, the direct current (DC) power supply is 0.5 kW, the substrate temperature is 400°C, and the film formation atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere. Note that when a pulsed DC power supply is used, it is preferable because powdery substances (also referred to as particles or dust) generated during film formation can be reduced and the film thickness distribution becomes uniform.

[0107] Note that before forming the oxide semiconductor film by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove powdery substances (also referred to as particles or dust) adhering to the surface to be formed of the oxide semiconductor film. Reverse sputtering means that the substrate A method of applying a voltage to a plate, forming a plasma near the substrate, and modifying the surface on the substrate side . Note that instead of argon, gases such as nitrogen, helium, and oxygen may be used.

[0108] Also, an oxide semiconductor film 644 is formed by processing an oxide semiconductor film. Oxidation The processing of the oxide semiconductor film can be performed by forming a mask of a desired shape on the oxide semiconductor film and then etching the oxide semiconductor film. The above-mentioned mask can be formed by using a method such as photolithography . Or, a mask may be formed by using a method such as the inkjet method . Note that the etching of the oxide semiconductor film may be either dry etching or wet etching. Of course, these may be used in combination .

[0109] Thereafter, a heat treatment (first heat treatment) may be performed on the oxide semiconductor film 644. By performing the heat treatment , substances containing hydrogen atoms contained in the oxide semiconductor film 644 can be further removed, the structure of the oxide semiconductor film 644 can be adjusted, and the defect levels in the energy gap can be reduced . The temperature of the heat treatment is 250°C or higher and 700°C or lower, preferably 450°C or higher and 600°C or lower, or less than the distortion point of the substrate, in an inert gas atmosphere. As the inert gas atmosphere , an atmosphere mainly composed of nitrogen or a rare gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9 999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower). 999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0110] The heat treatment can be carried out, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, under a nitrogen atmosphere, at 450°C for 1 hour. During this time, the oxide semiconductor film 644 is not exposed to the atmosphere, and water and hydrogen are prevented from mixing in.

[0111] By performing the heat treatment to reduce impurities and forming an oxide semiconductor film that is of the i-type (intrinsic semiconductor) or extremely close to the i-type, a transistor with extremely excellent characteristics can be realized.

[0112] Incidentally, since the above-mentioned heat treatment has the effect of removing hydrogen, water, etc., the heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. The heat treatment can be performed, for example, at the timing such as before processing the oxide semiconductor film into an island shape or after forming the gate insulating film. Also, such dehydration treatment and dehydrogenation treatment can be performed not only once but multiple times.

[0113] Note that oxide semiconductors are insensitive to impurities, and there is no problem even if a considerable amount of metal impurities are contained in the film. It has been pointed out that inexpensive soda lime glass containing a large amount of alkali metals such as sodium can also be used (Kamiya, Nomura, Hosono, " Physical properties of amorphous oxide semiconductors and the current status of device development", Solid State Physics, September 2009 issue, Vol. 44, pp. 62 1-633.). However, such a statement is inappropriate. Since alkali metals are not elements that constitute oxide semiconductors, they are impurities. Alkaline earth metals also become impurities when they are not elements that constitute oxide semiconductors. In particular, among alkali metals, Na diffuses into the insulating film when the insulating film in contact with the oxide semiconductor film is an oxide, ​​​​​​​​+ It becomes. In addition, Na separates the bonds between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may shift in the negative direction. The shift leads to degradation of transistor characteristics such as normally on and reduced mobility. In addition, the transistor characteristics may vary. The deterioration and variation in characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, when the hydrogen concentration in the oxide semiconductor film is 5×10 19 cm -3 Below Below, especially 5×10 18 cm -3 If the concentration of the impurities is less than or equal to the above, the concentration of the impurities can be reduced. Specifically, the measured value of Na concentration by secondary ion mass spectrometry is 5×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 More preferably, 1×10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 The following is preferred: 1×10 15 / cm 3 Similarly, the measured value of K concentration should be 5×10 15 / cm 3 Less than or equal to 1×10 15 / cm 3 The following should be used.

[0114] In addition, an impurity element that imparts p-type conductivity, such as tin (Sn), is added to the oxide semiconductor film 644. In this case, the oxide semiconductor film 644 may have weak p-type conductivity. By including SnOx in the oxide semiconductor target, the oxide semiconductor film 644 As described above, the highly purified oxide semiconductor can be doped with p-type impurity elements. Since the solid film 644 is intrinsic or substantially intrinsic, impurity elements for valence control are not included. By adding a small amount of , it is possible to obtain an oxide semiconductor film that exhibits weak p-type conductivity. As a result, a transistor formed using the oxide semiconductor film 644 can be obtained. (a state in which drain current flows even when no voltage is applied to the gate electrode) In order to prevent the normally-on state, the oxide semiconductor A second gate electrode is provided on the side opposite to the gate electrode across the body membrane 644, thereby The threshold voltage may be controlled.

[0115] Note that the oxide semiconductor film 644 may be amorphous. It is preferable to use a crystalline oxide semiconductor film as the region. By using a semiconductor film, the reliability of the transistor (gate bias stress resistance) is improved. Because it can be increased.

[0116] A crystalline oxide semiconductor film is ideally single-crystal. Axis-aligned crystal (also called CAAC) It is preferable that the oxide contains .

[0117] Here, the c-axis is oriented and the ab-plane, surface, or interface is triangular or hexagonal. In the c-axis, the metal atoms are layered or the metal atoms and oxygen atoms are layered. arranged, and on the ab plane, the directions of the a-axis or b-axis are different (rotated around the c-axis ) and includes a crystal (CAAC: C Axis Aligned Crystal) in an oxide will be described.

[0118] An oxide containing CAAC, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab plane, it has an atomic arrangement in the shape of a triangle, hexagon, equilateral triangle or regular hexagon, and contains a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from a direction perpendicular to the c-axis direction. oxide.

[0119] CAAC is not a single crystal, nor is it formed only from amorphous materials. Also, CA AC contains crystallized parts (crystalline parts), but there are cases where the boundary between one crystalline part and another crystalline part cannot be clearly distinguished.

[0120] When oxygen is contained in CAAC, part of the oxygen may be replaced by nitrogen. Also, the c-axes of the individual crystalline parts that make up CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface that supports CAAC, the surface of CAAC, etc.). Or, the normal lines of the ab planes of the individual crystalline parts that make up CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface that supports CAAC, the surface of CAAC, etc.).

[0121] Depending on its composition, etc., CAAC can be a conductor, a semiconductor, or an insulator. Also, depending on its composition, etc., it can be transparent or opaque to visible light.

[0122] As an example of such CAAC, it is formed in a film shape and is perpendicular to the film surface or the substrate surface that supports it. When observed from a certain direction, a triangular or hexagonal atomic arrangement is recognized, and when observing the cross-section of the film a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is recognized. Crystals can also be cited.

[0123] CAAC will be described in detail with reference to FIGS. 12 to 14. Unless otherwise specified, in FIGS. 12 to 14, the upward direction is the c-axis direction, and the plane perpendicular to the c-axis direction is the ab-plane. Also, when simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary.

[0124] FIG. 12(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter 4 coordinate O) adjacent to In. Here, the structure showing only the adjacent oxygen atoms for one metal atom is called a small group. The structure of FIG. 12(A) takes an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 12(A). The small group shown in FIG. 12(A) has a charge of 0.

[0125] FIG. 12(B) shows a structure having one 5-coordinate Ga, three 3-coordinate oxygen atoms (hereinafter 3 coordinate O) adjacent to Ga, and two 4-coordinate O adjacent to Ga. All the 3-coordinate O atoms are present in the ab-plane. There is one 4-coordinate O atom each in the upper half and the lower half of FIG. 12(B). Also, since In can also take a 5-coordinate structure, the structure shown in FIG. 12(B) can be taken. The small group shown in FIG. 12(B) has a charge of 0.

[0126] FIG. 12(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to Zn. There is one 4-coordinate O atom in the upper half of FIG. 12(C) and three 4-coordinate O atoms in the lower half.​​​​​ There is an O. Or, there may be three 4 - coordinated Os in the upper half of Fig. 12(C) and one 4 - coordinated O in the lower half. The small group shown in Fig. 12(C) has a charge of 0.

[0127] Fig. 12(D) shows a structure having one 6 - coordinated Sn and six 4 - coordinated Os adjacent to the Sn. There are three 4 - coordinated Os in the upper half of Fig. 12(D) and three 4 - coordinated Os in the lower half. The small group shown in Fig. 12(D) has a charge of +1.

[0128] Fig. 12(E) shows a small group containing two Zns. There is one 4 - coordinated O in the upper half of Fig. 12(E) and one 4 - coordinated O in the lower half. The small group shown in Fig. 12(E) has a charge of -1.

[0129] Here, an aggregate of a plurality of small groups is called a middle group, and an aggregate of a plurality of middle groups is called a large group (also referred to as a unit cell).

[0130] Here, the rule for the combination of these small groups will be explained. The three Os in the upper half of the 6 - coordinated In shown in Fig. 12(A) each have three adjacent Ins downward, and the three Os in the lower half each have three adjacent Ins upward. The one O in the upper half of the 5 - coordinated Ga has one adjacent Ga downward, and the one O in the lower half has one adjacent Ga upward. The one O in the upper half of the 4 - coordinated Zn has one adjacent Zn downward, and the three Os in the lower half each have three adjacent Zns upward. In this way, the number of 4 - coordinated Os above the metal atom is equal to the number of adjacent metal atoms below that O, and similarly, the number of 4 - coordinated Os below the metal atom is equal to the number of adjacent metal atoms above that O. O is 4 ​ Since it is a coordination, the sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4 Thus, when the sum of the number of 4 - coordinated O atoms above a metal atom and the number of 4 - coordinated O atoms below another metal atom is 4, two small groups having metal atoms can bond to each other For example, when a 6 - coordinated metal atom (In or Sn) bonds through the 4 - coordinated O atoms in the lower half, since there are 3 4 - coordinated O atoms, it will bond to either the 4 - coordinated O atoms in the upper half of a 5 - coordinated metal atom (Ga or In) or a 4 - coordinated metal atom (Zn) Metal atoms having these coordination numbers bond through 4 - coordinated O atoms in the c - axis direction In addition, a plurality of small groups bond to form a medium - sized group so that the total charge of the layer structure becomes 0 Fig. 13(A) shows a model diagram of a medium - sized group constituting the layer structure of the In - Sn - Zn - O system Fig. 13(B) shows a large - sized group composed of three medium - sized groups. Note that Fig. 13(C) shows the atomic arrangement when observing the layer structure of Fig. 13(B) from the c - axis direction

[0131] In Fig. 13(A), for simplicity, 3 - coordinated O atoms are omitted, and only the number of 4 - coordinated O atoms is shown. For example, there are 3 4 - coordinated O atoms each in the upper and lower halves of Sn, which is shown as 3 in the round frame Similarly, in Fig. 13(A), there is 1 4 - coordinated O atom each in the upper and lower halves of In, which is shown as 1 in the round frame Also, similarly, in Fig. 13(A), there is 1 4 - coordinated O atom in the lower half and 3 4 - coordinated O atoms in the upper half

[0132]

[0133] ​​​​​​​​Zn with one 4 - coordinate O in the upper half and three 4 - coordinate O in the lower half is shown.

[0134] In Fig. 13(A), in the middle group constituting the layer structure of the In - Sn - Zn - O system, from the top in order, Sn with three 4 - coordinate O in each of the upper and lower halves, In with one 4 - coordinate O in each of the upper and lower halves are combined, and the In is combined with Zn having three 4 - coordinate O in the upper half, and through one 4 - coordinate O in the lower half of the Zn, it is combined with In having three 4 - coordinate O in each of the upper and lower halves. The In is combined with a small group consisting of two Zn having one 4 - coordinate O in the upper half, and through one 4 - coordinate O in the lower half of this small group, it is combined with Sn having three 4 - coordinate O in each of the upper and lower halves. This middle loop is combined in multiple numbers to form a large group.

[0135] Here, in the case of 3 - coordinate O and 4 - coordinate O, the charge per bond can be considered as - 0.6 67 and - 0.5 respectively. For example, the charges of In (6 - coordinate or 5 - coordinate), Zn (4 - coordinate), and Sn (5 - coordinate or 6 - coordinate) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Therefore, in order to form a layer structure containing Sn, a charge of - 1 to cancel the charge + 1 is required. As a structure with a charge of - 1, as shown in Fig. 1 2(E), a small group containing two Zn can be mentioned. For example, if there is one small group containing Sn and one small group containing two Zn, the charges can be canceled, so that the total charge of the layer structure can be made 0.

[0136] Specifically, by repeating the large group shown in Fig. 13(B), In-Sn-Zn -O-based crystals (In2SnZn3O8) can be obtained. Note that the obtained In-Sn -Zn-O-based layer structure can be represented by the composition formula of In2SnZn2O7(ZnO) m (m is 0 or a natural number.) and can be expressed as such a composition formula.

[0137] In addition to this, there are also In-Sn-Ga-Zn-based oxides which are quaternary metal oxides, and ternary metal oxides such as In-Ga-Zn-based oxides (also denoted as IGZO), In- Al-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-A l-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-C e-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm -Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb- Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn -based oxides, and binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I n-Ga-based oxides, etc. are the same when used.

[0138] For example, Fig. 14(A) shows a model diagram of the middle group that constitutes the In-Ga-Zn-O-based layer structure. Fig. 14(A) shows a model diagram of the middle group that constitutes the In-Ga-Zn-O-based layer structure.

[0139] In Fig. 14(A), the middle group that constitutes the In-Ga-Zn-O-based layer structure is from the top In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to Zn at the bottom of the Zn atom, and one tetracoordinate O atom is bonded to the Zn atom via the three tetracoordinate O atoms in the bottom half of the Zn atom. It bonds to Ga in the upper and lower halves, respectively, and is bonded to one tetracoordinate O in the lower half of the Ga. The structure is such that three 4-coordinate O atoms are bonded to In atoms in the upper and lower halves. These medium groups combine to form large groups.

[0140] Figure 14(B) shows a large group consisting of three medium groups. 14B is viewed from the c-axis direction.

[0141] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0142] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0143] The oxide semiconductor film composed of CAAC can also be fabricated by a sputtering method. To obtain an oxide semiconductor film made of CAAC by sputtering, The crystals are formed in a hexagonal crystal structure in the initial stage of deposition of the semiconductor film. It is important to grow the crystals using the target as a seed. Increase the distance between the substrates (for example, about 150 mm to 200 mm), and set the substrate heating temperature to 100 °C to 500°C, preferably 200°C to 400°C, more preferably 250°C to 300°C is preferable. In addition to this, at a temperature higher than the substrate heating temperature during film formation, the deposited oxide semiconductor film is heat-treated to repair microscopic defects contained in the film and defects at the lamination interface .

[0144] The oxide semiconductor film composed of CAAC is highly purified, reduces defects due to oxygen deficiency, and has a c-axis oriented crystal, making it insensitive to impurity elements for valence electron control and facilitating valence electron control to a weak p-type.

[0145] Next, a conductive layer for forming a source electrode and a drain electrode (including wirings formed in the same layer as this) is formed on the oxide semiconductor film 644 or the like, and the conductive layer is processed to form a source electrode or drain electrodes 642a, 642b (see FIG. 8(B)).

[0146] The conductive layer can be formed using a PVD method or a CVD method. Also, as the material of the conductive layer , elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten , or alloys containing the above-described elements as components can be used. Manganese, magnesium , any one of zirconium, beryllium, neodymium, scandium, or a combination of a plurality of these can also be used.

[0147] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, an aluminum A two-layer structure in which a titanium film is laminated on a mu film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Also, when the conductive layer is a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that it is easy to process into a source electrode or drain electrode 642a, 642b having a tapered shape. Furthermore, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. Etching of the conductive layer is preferably performed so that the ends of the source electrode or drain electrode 642a, 642b to be formed have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. By etching the ends of the source electrode or drain electrode 642a, 642b to have a tapered shape, the coverage of the gate insulating film 646 to be formed later can be improved, and step discontinuity can be prevented. The channel length (L) of the upper transistor is determined by the interval between the source electrode or drain electrode 642a and the lower end of the source electrode or drain electrode 642b. When forming a transistor with a channel length (L) of less than 25 nm, the exposure for mask formation used is as follows.

[0148] Also, the conductive layer may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. Indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO), indium zinc oxide alloy (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. Indium zinc oxide alloy (In2O3 - ZnO), or those containing silicon or silicon oxide in these metal oxide materials can be used. For the etching of the conductive layer, it is preferable to perform it so that the ends of the source electrode or drain electrode 642a, 642b to be formed have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. By etching the ends of the source electrode or drain electrode 642a, 642b to have a tapered shape, the coverage of the gate insulating film 646 to be formed later can be improved, and step discontinuity can be prevented.

[0149] The channel length (L) of the upper transistor is determined by the interval between the source electrode or drain electrode 642a and the lower end of the source electrode or drain electrode 642b. When forming a transistor with a channel length (L) of less than 25 nm, the exposure for mask formation used is as follows. The channel length (L) of the upper transistor is determined by the interval between the source electrode or drain electrode 642a and the lower end of the source electrode or drain electrode 642b. When forming a transistor with a channel length (L) of less than 25 nm, the exposure for mask formation used is as follows. By etching the ends of the source electrode or drain electrode 642a, 642b to have a tapered shape, the coverage of the gate insulating film 646 to be formed later can be improved, and step discontinuity can be prevented.

[0150] The channel length (L) of the upper transistor is determined by the interval between the source electrode or drain electrode 642a and the lower end of the source electrode or drain electrode 642b. When forming a transistor with a channel length (L) of less than 25 nm, the exposure for mask formation used is as follows. When forming a transistor with a channel length (L) of less than 25 nm, the exposure for mask formation used When performing this, it is desirable to use extreme ultraviolet rays with a wavelength as short as several nm to several 10 nm (Extreme Ultra violet). Exposure with extreme ultraviolet rays has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor formed later to 10 nm or more and 10 00 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. In addition, miniaturization can also reduce the power consumption of the memory device.

[0151] Next, a gate insulating film 646 is formed so as to cover the source electrode or the drain electrode 642a, 642b and be in contact with a part of the oxide semiconductor film 644 (see FIG. 8(C)).

[0152] The gate insulating film 646 can be formed using a CVD method, a sputtering method, or the like. In addition, the gate insulating film 646 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, gallium oxide, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium silicate (HfSixOy (x > 0, y > 0)), hafnium silicate (HfSixOy (x > 0, y > 0)) added with nitrogen, hafnium aluminate (HfAlxOy (x > 0, y > 0)) added with nitrogen, and the like. The gate insulating film 646 may have a single-layer structure or a laminated structure formed by combining the above materials. Also, its thickness is not particularly limited, but when miniaturizing the memory device, it is desirable to make it thin to ensure the operation of the transistor. For example, when using silicon oxide it can be set to 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less.

[0153] As described above, when the gate insulating film 646 is made thinner, gate leakage due to the tunneling effect or the like becomes a problem. To solve the problem of gate leakage, it is preferable to use a high-k (high dielectric constant) material such as hafnium oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy ( x>0, y>0)), hafnium silicate with nitrogen added (HfSixOy (x>0 y>0)), hafnium aluminate with nitrogen added (HfAlxOy (x>0, y >0)), etc. for the gate insulating film 646. By using a high-k material for the gate insulating film 646, it becomes possible to increase the film thickness in order to suppress gate leakage while ensuring electrical characteristics. Note that a laminated structure of a film containing a high-k material and a film containing any one of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. may be used. Also, the insulating film in contact with the oxide semiconductor film 644 (in FIG. 8(C), the gate insulating film 64 6) may be an insulating material containing a Group 13 element and oxygen. Many oxide semiconductors contain a Group 13 element, and an insulating material containing a Group 13 element has good compatibility with the oxide semiconductor. By using this for the insulating film in contact with the oxide semiconductor film, the state of the interface with the oxide semiconductor film can be kept favorable. Here, the insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Here, aluminum gallium oxide means that the content of aluminum (atomic %) is higher than that of gallium. In addition, a laminated structure with any of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. may be used. Moreover, the insulating film in contact with the oxide semiconductor film 644 (in FIG. 8(C), the gate insulating film 64

[0154] 6) may be an insulating material containing a Group 13 element and oxygen. Since many oxide semiconductors contain a Group 13 element, an insulating material containing a Group 13 element has good compatibility with the oxide semiconductor. By using this for the insulating film in contact with the oxide semiconductor film, the state of the interface with the oxide semiconductor film can be kept favorable. Here, the insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Here, aluminum gallium oxide means that the content of aluminum (atomic %) is higher than that of gallium. By using this for the insulating film in contact with the oxide semiconductor film, the state of the interface with the oxide semiconductor film can be kept favorable. That is, by using this for the insulating film in contact with the oxide semiconductor film, the state of the interface with the oxide semiconductor film can be kept favorable.

[0155] Here, the insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Here, aluminum gallium oxide means that the content of aluminum (atomic %) is higher than that of gallium. Examples of the insulating material containing a Group 13 element include gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, etc. Here, aluminum gallium oxide means that the content of aluminum (atomic %) is higher than that of gallium. Indicates those with a large quantity (atomic %), and gallium oxide aluminum refers to those in which the content of gallium ( (atomic %) is equal to or more than the content of aluminum (atomic %).

[0156] For example, when forming a gate insulating film in contact with an oxide semiconductor film containing gallium, by using a material containing gallium oxide for the gate insulating film, the interface characteristics between the oxide semiconductor film and the gate insulating film can be kept good. Also, by providing an insulating film containing gallium oxide in contact with the oxide semiconductor film, the hydrogen pile-up at the interface between the oxide semiconductor film and the insulating film can be reduced. When using an element in the same group as the component element of the oxide semiconductor for the insulating film, the same effect can be obtained. For example, it is also effective to form an insulating film using a material containing aluminum oxide. Since aluminum oxide has the property of being difficult to permeate water, using this material is also preferable in terms of preventing water from entering the oxide semiconductor film.

[0157] Also, the insulating film in contact with the oxide semiconductor film 644 is preferably made to have a state where oxygen is more than the stoichiometric composition ratio of the insulating material by heat treatment in an oxygen atmosphere or an oxygen doping process. Oxygen doping means adding oxygen to the bulk. The term bulk is used to clarify that oxygen is added not only to the thin film surface but also to the inside of the thin film. Also, oxygen doping includes oxygen plasma doping in which plasmaized oxygen is added to the bulk. Also, oxygen doping may be performed using the ion implantation method or the ion doping method.

[0158] For example, when using gallium oxide as the insulating film in contact with the oxide semiconductor film 644, in an oxygen atmosphere By performing heat treatment in an atmosphere or oxygen doping, the composition of gallium oxide can be made Ga2O x (X = 3 + α, 0 < α < 1). Also, when aluminum oxide is used as the insulating film in contact with the oxide semiconductor film 644, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of aluminum oxide can be made Al2O By performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of aluminum oxide can be made Al2O (X = 3 + α, 0 < α < 1). Or, when gallium aluminum oxide (aluminum gallium oxide) is used as the insulating film in contact with the oxide semiconductor film 644, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of gallium aluminum oxide (aluminum gallium oxide) can be made Ga X (X = 3 + α, 0 < α < 1). Or, when gallium aluminum oxide (aluminum gallium oxide) is used as the insulating film in contact with the oxide semiconductor film 644, by performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of gallium aluminum oxide (aluminum gallium oxide) can be made Ga Al By performing heat treatment in an oxygen atmosphere or oxygen doping, the composition of gallium aluminum oxide (aluminum gallium oxide) can be made Ga Al O X Al 2-X O 3+α (0 < X < 2, 0 < α < 1).

[0159] By performing oxygen doping treatment or the like, an insulating film having a region where oxygen is more than the stoichiometric composition ratio can be formed. When such an insulating film having such a region is in contact with the oxide semiconductor film, excess oxygen in the insulating film is supplied to the oxide semiconductor film, reducing oxygen deficiency defects in the oxide semiconductor film and at the interface between the oxide semiconductor film and the insulating film, and making the oxide semiconductor film an i-type oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type. oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type. oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type. oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type.

[0160] Note that the insulating film having a region where oxygen is more than the stoichiometric composition ratio may be applied to the underlying film of the oxide semiconductor film 644 instead of the gate insulating film 646, or may be applied to both the gate insulating film 646 and the underlying insulating film. oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type. oxide semiconductor or an oxide semiconductor that is infinitely close to the i-type.

[0161] After the formation of the gate insulating film 646, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. It is desirable to perform the treatment. The temperature of the heat treatment is 200°C or higher and 450°C or lower, desirably 25 0°C or higher and 350°C or lower. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, variations in the electrical characteristics of the transistor can be reduced. Further, when the gate insulating film 646 contains oxygen, oxygen is supplied to the oxide semiconductor film 644 to compensate for oxygen deficiencies in the oxide semiconductor film 644, and an oxide semiconductor film of type-i (intrinsic semiconductor) or an oxide semiconductor film that is infinitely close to type-i can also be formed.

[0162] Here, the second heat treatment is performed after the formation of the gate insulating film 646, but the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0163] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor film 644 can be purified to a high purity so that the substance containing its hydrogen atoms is minimized.

[0164] Next, a conductive layer for forming a gate electrode (including wiring formed in the same layer) is formed, and the conductive layer is processed to form a gate electrode 648a and a conductive film 648b (see FIG. 8 (D)).

[0165] The gate electrode 648a and the conductive film 648b are made of a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or a material mainly composed of these.​​ It can be formed using an alloy material. Note that the gate electrode 648a and the conductive film 648 b may have a single-layer structure or a laminated structure.

[0166] As described above, the transistor 662 and the capacitor element 664 using the highly purified oxide semiconductor film 644 are completed (see FIG. 8(D)).

[0167] When forming the transistor 332 and the capacitor element 334 shown in FIG. 7(A), source electrodes or drain electrodes 642a and 642b are formed on the insulating film 640, and the oxide semiconductor film 644 is formed on the insulating film 640 and the source electrodes or drain electrodes 642a and 642b. Next, a gate insulating film 646 is formed on the source electrodes or drain electrodes 642a and 642b and the oxide semiconductor film 644. Then, a gate electrode 648a is formed on the gate insulating film 646 so as to overlap the oxide semiconductor film 644, and a conductive film 648b is formed so as to overlap the source electrode or drain electrode 642b.

[0168] When forming the transistor 342 and the capacitor element 344 shown in FIG. 7(B), the gate electrode 648a and the conductive film 648b are formed on the insulating film 640, and the gate insulating film 646 is formed on the insulating film 640, the gate electrode 648a, and the conductive film 648b. Next, source electrodes or drain electrodes 642a and 642b are formed on the gate insulating film 646. Then, the oxide semiconductor film 644 is formed on the gate insulating film 646 so as to overlap the gate electrode 648a, thereby completing the transistor 342 and the capacitor element 344. Note that the insulating films 650 and 652 may be formed so as to cover the transistor 342 and the capacitor element 344. For example, ​​​​​​​​​​​​For example, the insulating film 650 is preferably in a state where oxygen is more than the stoichiometric composition ratio by heat treatment in an oxygen atmosphere or by oxygen doping. The insulating film 652 is preferably in a state where it is difficult for water and hydrogen to permeate. By making the insulating film 652 in a state where it is difficult for water and hydrogen to permeate, it is possible to prevent water and hydrogen from entering the oxide semiconductor film 644. By making the insulating film 650 in a state where oxygen is more than the stoichiometric composition ratio, oxygen vacancies in the oxide semiconductor film 644 can be filled, and an oxide semiconductor film 644 of type i or extremely close to type i can be formed. This is because it is possible to prevent water and hydrogen from entering the oxide semiconductor film 644, and by making the insulating film 650 in a state where oxygen is more than the stoichiometric composition ratio, oxygen vacancies in the oxide semiconductor film 644 can be filled, and an oxide semiconductor film 644 of type i or extremely close to type i can be formed.

[0169] Also, when forming the transistor 352 and the capacitor element 354 shown in FIG. 7(C), a gate electrode 648a and a conductive film 648b are formed on the insulating film 640, and a gate insulating film 646 is formed on the insulating film 640, the gate electrode 648a, and the conductive film 648b. Next, an oxide semiconductor film 644 is formed on the gate insulating film 646 so as to overlap with the gate electrode 648a. Thereafter, source electrodes or drain electrodes 642a and 642b are formed on the oxide semiconductor film 644, whereby the transistor 352 and the capacitor element 354 are completed. Note that for the insulating film 650 and the insulating film 652, reference can be made to the description in FIG. 7(B).

[0170] Also, when forming the transistor 362 and the capacitor element 364 shown in FIG. 7(D), a gate electrode 648a and a conductive film 648b are formed on the insulating film 640, and a gate insulating film 646 (the first gate insulating film in FIG. 7(D)) is formed on the insulating film 640, the gate electrode 648a (the first gate electrode in FIG. 7(D)), and the conductive film 648b. Next, an oxide semiconductor film 644 is formed on the gate insulating film 646 so as to overlap with the gate electrode 648a, and an oxide ​ Source electrodes or drain electrodes 642a and 642b are formed on the semiconductor film 644. Then, an insulating film 650 (the second gate insulating film in FIG. 7(D)) is formed on the oxide semiconductor film 644 and the source electrodes or drain electrodes 642a and 642b, and a conductive film 659 (the second gate electrode in FIG. 7(D)) is formed so as to overlap the oxide semiconductor film 64 4. Thus, the transistor 362 and the capacitor element 364 are completed. Note that the description of the gate electrode 648a can be referred to for the conductive film 659.

[0171] Next, a method for manufacturing the transistor and the capacitor element shown in FIGS. 6(A) and 6(B) will be described.

[0172] A method for manufacturing the transistor 312 and the capacitor element 314 shown in FIG. 6(A) will be described.

[0173] First, an oxide semiconductor film 644 is formed on the insulating film 640, and a stack of an oxide conductive film and a conductive layer is formed on the insulating film 640 and the oxide semiconductor film 644.

[0174] As a method for forming the oxide conductive film, a sputtering method, a vacuum evaporation method (such as an electron beam evaporation method), an arc discharge ion plating method, or a spray method can be used. As materials for the oxide conductive film, zinc oxide, aluminum zinc oxide, aluminum zinc oxide nitride, gallium zinc oxide, indium tin oxide, or the like can be applied. Further, silicon oxide may be included in the above materials. Note that for the method and materials for forming the conductive layer, the description of the conductive layer for forming the source electrodes or drain electrodes 642a and 642b can be referred to.

[0175] ​​​​​​Next, a mask is formed on the conductive layer, and the conductive layer and the oxide conductive film are selectively etched to form the source electrode or drain electrodes 642a, 642b, and the oxide conductive films 64 3a, 643b.

[0176] Note that during the etching process of the conductive layer and the oxide conductive film, the etching conditions (type of etching material, concentration, etching time, etc.) are appropriately adjusted so that the oxide semiconductor film is not over-etched.

[0177] Next, a gate insulating film 646 is formed on the source electrode or drain electrodes 642a, 642b, and the oxide semiconductor film 644. Thereafter, a gate electrode 648a is formed on the gate insulating film 646 so as to overlap with the oxide semiconductor film 6 44, and a conductive film 648b is formed so as to overlap with the source electrode or drain electrode 64 2b.

[0178] Thus, the transistor 312 and the capacitor element 314 are completed (see FIG. 6(A)).

[0179] When manufacturing the transistor 322 and the capacitor element 324 shown in FIG. 6(B), a stack of the oxide semiconductor film and the oxide conductive film is formed, and the stack of the oxide semiconductor film and the oxide conductive film is shaped by the same photolithography process to form island-shaped oxide semiconductor films and oxide conductive films. Next, after forming the source electrode or drain electrodes 642a, 642 b on the island-shaped oxide conductive film, the island-shaped oxide conductive film is etched using the source electrode or drain electrodes 642a, 642b as a mask to form the oxide conductive films 643a, 643b that will become the source region or drain region.

[0180] ​​​​​​Next, the source and drain electrodes 642a and 642b and the oxide semiconductor film 644 A gate insulating film 646 is then formed on the gate insulating film 646. A gate electrode 648a is formed so as to overlap with the source electrode or drain electrode 64 A conductive film 648b is formed so as to overlap with 2b.

[0181] Through the above steps, the transistor 322 and the capacitor 324 are completed (see FIG. 6B).

[0182] In the above-described transistor, the oxide semiconductor film 644 is highly purified. The concentration is 5 x 10 19 / cm 3 Less than 5×10 18 / cm 3 The following is more preferable: 5×10 17 / cm 3 The carrier density of the oxide semiconductor film 644 is as follows: The carrier density in a typical silicon wafer (1×10 14 / cm 3 Compared to the degree , a sufficiently small value (e.g., 1×10 12 / cm 3 Less than 1.45×1 0 10 / cm 3 The off-state current of the transistor is also sufficiently small. For example, the off-state current of the transistor at room temperature (25° C.) (here, unit channel width (1μm) is 100zA (1zA (zeptoampere) is 1×10 -21 A) The current is preferably 10zA or less.

[0183] In addition, the oxide semiconductor film 644 has a sufficiently low concentration of alkali metal and alkaline earth metal. is reduced, and the concentration of the alkali metal or alkaline earth metal is, for example, in the case of Na, 5× 10 16 cm -3 or less, preferably 1×10 16 cm -3 or less, more preferably 1×1 0 15 cm -3 or less, in the case of Li, 5×10 15 cm -3 or less, preferably 1×10 15 cm -3 or less, in the case of K, 5×10 15 cm -3 or less, preferably 1×10 15 cm -3 or less.

[0184] By using the thus highly purified and true oxide semiconductor film 644, it becomes easy to sufficiently reduce the off-current of the transistor. And by using such a transistor, a memory device capable of retaining the memory content for an extremely long time can be obtained.

[0185] <Usage examples of the memory device> Hereinafter, the usage examples of the above-described memory device will be described with reference to FIGS. 9 and 10.

[0186] FIG. 9 is a block diagram showing a configuration example of a microprocessor. The microprocessor shown in FIG. 9 includes a CPU 401, a main memory 402, a clock controller 403, a cache controller 404, a serial interface 405, an I / O port 406, a terminal 4 07, an interface 408, a cache memory 409, etc. Of course, the microprocessor shown in FIG. 9 is only an example shown with its configuration simplified, and the actual micro processor The microprocessor has a wide variety of configurations depending on its application.

[0187] To operate the CPU 401 at a higher speed, a memory with a speed commensurate with it is required. However, when using a high-speed and large-capacity memory with an access time corresponding to the operating speed of the CPU 401, the cost generally becomes high. Therefore, in addition to the large-capacity main memory 402, a cache memory 409, which is a high-speed memory with a smaller capacity than the main memory 402, is interposed between the CPU 401 and the main memory 402. When the CPU 401 accesses the cache memory 409, it can operate at high speed regardless of the speed of the main memory 402.

[0188]

[0189] In the microprocessor shown in FIG. 9, the storage device described above can be used for the main memory 402. With the above configuration, a highly integrated microprocessor and a highly reliable microprocessor can be realized.

[0190] The program executed by the CPU 401 is stored in the main memory 402. And for example, at the initial stage of execution, the program stored in the main memory 402 is downloaded to the cache memory 409. The program to be downloaded is not limited to that stored in the main memory 402, and it can also be downloaded from other external memories. The cache memory 409 not only stores the program executed by the CPU 401, but also functions as a work area and temporarily stores the calculation results of the CPU 401 and the like.​​​​​​​​​​​​Note that the number of CPUs is not limited to one, and multiple CPUs may be provided. By providing multiple CPUs and performing parallel processing, the operating speed can be improved. In that case, since there may be a problem when looking at the entire process if the processing speeds between the CPUs are uneven, the balance of the processing speeds of the slave CPUs may be adjusted by the master CPU. When this is done, the operating speed can be improved. However, if the processing speeds of the CPUs are uneven, there may be a problem when looking at the entire process. Therefore, the balance of the processing speeds of the slave CPUs may be adjusted by the master CPU.

[0191] Note that although a microprocessor has been exemplified here, the storage device described above is not limited to being used as the main memory of a microprocessor. For example, it is also preferably used as a video RAM required for a drive circuit of a display device or a large-capacity memory required for an image processing circuit. In addition, it can be used as a memory for large-capacity or small-size applications in various system LSIs. Other uses, such as a video RAM required for a drive circuit of a display device or a large-capacity memory required for an image processing circuit, are also preferable. In addition, it can be used as a memory for large-capacity or small-size applications in various system LSIs.

[0192] FIG. 10 is a block diagram showing a configuration example of an RF tag. In FIG. 10, the RF tag 550 has an antenna circuit 551 and an integrated circuit 552. The integrated circuit 552 has a power supply circuit 553, a demodulation circuit 554, a modulation circuit 555, a regulator 556, an arithmetic circuit 557, a storage device 558, and a booster circuit 559. Note that the storage device 558 is the storage device described above.

[0193] Next, an example of the operation of the RF tag 550 will be described. When a radio wave is sent from an interrogator, the radio wave is converted into an AC voltage in the antenna circuit 551. In the power supply circuit 553, the AC voltage from the antenna circuit 551 is rectified to generate a power supply voltage. The power supply voltage generated in the power supply circuit 553 is supplied to the arithmetic circuit 557 and the regulator 556. The regulator 556 stabilizes the power supply voltage from the power supply circuit 553 or ​ After adjusting the height, it is supplied to various circuits such as the demodulation circuit 554, modulation circuit 555, arithmetic circuit 5 57, memory device 558, or boost circuit 559 in the integrated circuit 552.

[0194] The demodulation circuit 554 demodulates the AC signal received by the antenna circuit 551 and outputs it to the subsequent arithmetic circuit 557. The arithmetic circuit 557 performs arithmetic processing according to the signal input from the demodulation circuit 554 and generates a separate signal. When performing the above arithmetic processing, the memory device 558 can be used as a primary cache memory or a secondary cache memory. Also, the arithmetic circuit 557 analyzes the signal input from the demodulation circuit 554 and, according to the content of the instruction sent from the interrogator, outputs the information in the memory device 558 or executes the content of the instruction in the memory device 558. The signal output from the arithmetic circuit 557 is encoded and sent to the modulation circuit 555. The modulation circuit 555 modulates the radio wave received by the antenna circuit 551 according to the signal. The radio wave modulated in the antenna circuit 551 is received by the interrogator.

[0195] In this way, the communication between the RF tag 550 and the interrogator is performed by modulating the radio wave used as the carrier (carrier wave). The carrier varies according to standards such as 125 kHz, 13.56 MHz, 950 MHz and so on. Also, there are various modulation methods such as amplitude modulation, frequency modulation, and phase modulation according to the standard, but any modulation method can be used as long as it conforms to the standard modulation method.

[0196] The signal transmission method can be classified into various types such as electromagnetic coupling method, electromagnetic induction method, and microwave method according to the wavelength of the carrier.

[0197] The boost circuit 559 boosts the voltage output from the regulator 556 and supplies it to the storage device 558.

[0198] In the RF tag 550 shown in FIG. 10, by using the above-described storage device as the storage device 558, high integration and high reliability can be achieved.

[0199] Here, the configuration of the RF tag 550 having the antenna circuit 551 is described. However, the RF tag shown in FIG. 10 does not necessarily need to include an antenna circuit as its component. Further, an oscillation circuit or a secondary battery may be provided in the RF tag shown in FIG. 10.

[0200] (Embodiment 2) Not limited to oxide semiconductors, the field-effect mobility of an actually measured insulated-gate type transistor is lower than the original mobility for various reasons. As factors for reducing the mobility, there are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. However, using the Levinson model, the field-effect mobility can be theoretically derived assuming that there are no defects inside the semiconductor. Therefore, in the present embodiment, the field-effect mobility of an ideal oxide semiconductor without defects inside the semiconductor is theoretically derived, and the calculation results of the characteristics when a fine transistor is manufactured using such an oxide semiconductor are shown.

[0201] Assuming that the original mobility of the semiconductor is μ0, the measured field-effect mobility is μ, and there is some potential barrier (grain boundary, etc.) in the semiconductor, it can be expressed by the following formula.

[0202] [Equation]

[0203] ​​​​​​​​​​​ Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Assuming that the potential barrier is derived from defects, in the Levinson model , it can be expressed by the following equation.

[0204]

Equation

[0205] Here, e is the elementary charge, N is the average defect density per unit area in the channel, ε is the dielectric constant of the semiconductor, n is the number of carriers contained in the channel per unit area, C ox is the capacitance per unit area , V g is the gate voltage, and t is the thickness of the channel. For a semiconductor layer with a thickness of 30 nm or less, the thickness of the channel can be regarded as the same as the thickness of the semiconductor layer. In the linear region, the drain current I can be expressed by the following equation. d

Equation

[0206]

Equation

[0207] Here, L is the channel length and W is the channel width. Here, L = W = 10 μm. Also, V d is the drain voltage. Divide both sides of the above equation by V g , and then take the logarithm of both sides, then it becomes as follows.

[0208]

Equation

[0209] The right side of Equation 5 is a function of V g . As can be seen from this equation, with the vertical axis being ln(I d / Vg ) The defect density N can be obtained from the slope of the straight line with the horizontal axis being 1 / V. That is, for the transistor g the defect density can be evaluated from the I -V d characteristics. As the oxide semiconductor, when the ratio of indium (In), tin (Sn), and zinc (Zn) is In:Sn:Zn = 1:1:1, g the defect density N is on the order of 1×10 / cm 12 2 .

[0210] Based on the defect density and the like obtained in this way, μ0 = 120 cm 2 / Vs is derived from Equations (2) and (3). The mobility measured for the defective In-Sn-Zn oxide is about 35 cm 2 / V s. However, it can be predicted that the mobility μ0 of the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film is 120 cm / Vs. 2

[0211] However, even if there are no defects inside the semiconductor, the transport characteristics of the transistor are affected by scattering at the interface between the channel and the gate insulating film. That is, the mobility μ1 at a location x away from the gate insulating film interface can be expressed by the following equation.

[0212]

Equation

[0213] Here, D is the electric field in the gate direction, and B and G are constants. B and G can be obtained from actual measurement results. From the above measurement results, B = 4.75×10 cm / s and G = 10 7 nm (the depth to which interface scattering extends). As D increases (i.e., the gate voltage increases) ​​​​​​Since the second term on the right-hand side of Equation 6 increases, it can be seen that the mobility μ1 decreases.

[0214] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects The results of calculating μ2 are shown in Figure 15. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software that can be used to measure the bandgap of oxide semiconductors. The top, electron affinity, dielectric constant, and thickness are 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0215] In addition, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating film had a thickness of 100 nm and a relative dielectric constant of 4.6 electron volts. The channel length and width are both 10 μm, and the drain voltage V d is 0 .1V.

[0216] As shown in Figure 15, the mobility is 100 cm at a gate voltage of just over 1 V. 2 Peaks above / Vs However, if the gate voltage is increased further, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the surface of the semiconductor layer must be flattened at the atomic level (At omic layer flatness is preferred.

[0217] The characteristics of a miniaturized transistor manufactured using an oxide semiconductor having such mobility are as follows: The results of the calculation of the characteristics are shown in FIG. 16 to FIG. 18. Note that the cross-sectional structure of the transistor used in the calculation is The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 8103a and the semiconductor region 8103c are included. The resistivity of the semiconductor region 8103c is 2×10 -3 Let it be Ωcm.

[0218] The transistor shown in FIG. 19A includes a base insulating layer 8101 and a buried insulating layer 8102. A buried insulating layer 8102 made of aluminum oxide is formed on the buried insulating layer 8102. The transistor is made up of a semiconductor region 8103a, a semiconductor region 8103c, and a semiconductor region 8103c sandwiched between them. It has an intrinsic semiconductor region 8103 b which becomes a channel formation region, and a gate 8105 .

[0219] Between the gate 8105 and the semiconductor region 8103b, there is a gate insulating film 8104. On both sides of the gate 8105, there are sidewall insulators 8106a and 8106b. On the top of 8105, there is an insulator 810 to prevent short circuits between the gate 8105 and other wiring. The width of the sidewall insulator is set to 5 nm. A source 8108a and a drain 8108b are provided in contact with the region 8103c. The channel width in this transistor is set to 40 nm.

[0220] The transistor shown in FIG. 19B has a base insulating layer 8101 and a thin film transistor made of aluminum oxide. A semiconductor region 8103a and a semiconductor region 8103c are formed on the buried insulating layer 8102. The intrinsic semiconductor region 8103b sandwiched between them, and the gate 8105 with a width of 33 nm and the gate The gate insulating film 8104 and the sidewall insulator 8106a, and the sidewall insulator 8106b and the insulator 810 19(A) in that it has a source 8108a and a drain 8108b. Same as Zysta.

[0221] The difference between the transistor shown in FIG. 19(A) and the transistor shown in FIG. 19(B) lies in the conductivity type of the semiconductor regions under the sidewall insulators 8106a and 8106b. In the transistor shown in FIG. 19( A), the semiconductor regions under the sidewall insulator 8106a and the sidewall insulator 8106b are the semiconductor regions 8103a and 8103c that exhibit an n conductivity type. However, in the transistor shown in FIG. 19(B), it is the intrinsic semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much in the Loff state is formed. This region is called the offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). type semiconductor regions 8103a and 8103c, but in the transistor shown in FIG. 19(B), it is the intrinsic semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much in the Loff state is formed. This region is called the offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). + type semiconductor regions 8103a and 8103c, but in the transistor shown in FIG. 19(B), it is the intrinsic semiconductor region 8103b. That is, a region where the semiconductor region 8103a (semiconductor region 8103c) and the gate 8105 do not overlap much in the Loff state is formed. This region is called the offset region, and its width Loff is called the offset length. As is clear from the figure, the offset length is the same as the width of the sidewall insulator 8106a (sidewall insulator 8106b). As for the other parameters used in the calculation, they are as described above. For the calculation, the device simulation software Sentaurus Device manufactured by Synopsys was used. FIG. 16 shows the dependence of the drain current (I , solid line) and mobility (μ, dotted line) on the gate voltage (V ), the potential difference between the gate and the source) of the transistor having the structure shown in FIG. 19(A). The drain current I

[0222] is calculated with the drain voltage (the potential difference between the drain and the source) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. the dependence of the drain current (I ), solid line) and mobility d (μ, dotted line) on the gate voltage (V (, the potential difference between the gate and the source) of the transistor having the structure shown in FIG. 19(A). The drain current I g is calculated with the drain voltage (the potential difference between the drain and the source) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. current I d is calculated with the drain voltage (the potential difference between the drain and the source) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V. is calculated with the drain voltage (the potential difference between the drain and the source) set to +1V, and the mobility μ is calculated with the drain voltage set to +0.1V.

[0223] FIG. 16(A) shows the case where the thickness of the gate insulating film is 15 nm, FIG. 16(B) shows the case where it is 10 n m, and FIG. 16(C) shows the case where it is 5 nm. As the gate insulating film becomes thinner to such an extent that the drain current I, especially in the off state d (off current) decreases significantly. On the other hand, the mobility μ at its peak value and the drain current I d (on current) show no noticeable change. At around a gate voltage of 1 V, the drain current exceeds 10 μA, which is required for a memory cell or the like .

[0224] Figure 17 shows the gate voltage dependence of the drain current I (solid line) and the mobility μ (dotted line) for a transistor having the structure shown in Fig. 19(B) with an offset length Loff of 5 nm . The drain current I d is calculated with the drain voltage set to +1 V, and the mobility μ is calculated with the drain voltage set to g +0.1 V. Fig. 17(A) shows the case where the thickness of the gate insulating film is 15 nm , Fig. 17(B) shows the case where it is 10 nm, and Fig. 17(C) shows the case where it is 5 nm d . . .

[0225] Also, Fig. 18 shows the gate voltage dependence of the drain current I (solid line) and the mobility μ (dotted line) for a transistor having the structure shown in Fig. 19(B) with an offset length Loff of 15 nm . The drain current I d is calculated with the drain voltage set to +1 V, and the mobility μ is calculated with the drain voltage set to +0.1 V. Fig. 18(A) shows the case where the thickness of the gate insulating film is 15 nm d , Fig. 18(B) shows the case where it is 10 nm, and Fig. 18(C) shows the case where it is 5 nm . . .

[0226] In all cases, as the gate insulating film becomes thinner, the off current decreases significantly, while there is no noticeable change in the peak value of the mobility μ or the on current.

[0227] Note that the peak of the mobility μ is about 80 cm 2 / Vs in Fig. 16, but about 60 cm 2 / Vs in Fig. 17, and about 40 cm 2 / Vs in Fig. 18, and it decreases as the offset length Loff increases. Also, the off-current has a similar tendency. On the other hand, the on-current decreases as the offset length Loff increases, but it is much gentler compared to the decrease in the off-current. Also, in both cases, around a gate voltage of 1 V, the drain current was shown to exceed 10 μA which is required for memory cells etc. This embodiment can be implemented in appropriate combination with the above embodiment.

[0228] This embodiment can be implemented in appropriate combination with the above embodiment.

[0229] (Embodiment 3) For a transistor having an oxide semiconductor containing In, Sn, and Zn as main components in the channel formation region, good characteristics can be obtained by heating the substrate during film formation of the oxide semiconductor, or by performing a heat treatment after forming the oxide semiconductor film. Note that the main component refers to an element contained in a composition ratio of 5 atomic% or more. Therefore, in this embodiment, by intentionally heating the substrate after forming the oxide semiconductor film, the case where the field-effect mobility of the transistor is improved will be described with reference to Figs. 20 to 26. It is possible to improve the field-effect mobility of the transistor by intentionally heating the substrate after forming the oxide semiconductor film containing In, Sn, and Zn as main components. Also, it is possible to shift the threshold voltage of the transistor to positive and make it normally-off.

[0230] By intentionally heating the substrate after forming the oxide semiconductor film containing In, Sn, and Zn as main components, it becomes possible to improve the field-effect mobility of the transistor. Also, it is possible to shift the threshold voltage of the transistor to positive and make it normally-off.

[0231] For example, FIGS. 20(A) to (C) show the characteristics of a transistor using an oxide semiconductor film containing In, Sn, and Zn as main components, with a channel length L of 3 μm and a channel width W of 10 μm, and a gate insulating film with a thickness of 100 nm . Here, V d is set to 10 V

[0232] FIG. 20(A) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by sputtering without intentionally heating the substrate . At this time, a field-effect mobility of 18.8 cm / Vsec is obtained. On the other hand, when the substrate is intentionally heated to form an oxide semiconductor film containing In, S 2 n, and Zn as main components, it becomes possible to improve the field-effect mobility . FIG. 20(B) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by heating the substrate to 200°C, and the field-effect mobility is 32.2 cm / Vsec is obtained cm 2 / Vsec is obtained

[0233] The field-effect mobility can be further increased by performing heat treatment after forming an oxide semiconductor film containing In, Sn, and Zn as main components . FIG. 20(C) shows the transistor characteristics when an oxide semiconductor film containing In, Sn, and Zn as main components is formed by sputtering at 200°C and then heat-treated at 650°C. At this time, the field-effect mobility is 34.5 cm / V sec is obtained 2 / V sec is obtained

[0234] By intentionally heating the substrate, it is expected to reduce the incorporation of moisture in the sputtering film formation process into the oxide semiconductor film . Also, by performing heat treatment after film formation, the acid It is possible to release and remove hydrogen, hydroxyl groups, or moisture from the oxide semiconductor film, and as described above the field-effect mobility can be improved. Such an improvement in the field-effect mobility is not only due to the removal of impurities by dehydration and dehydrogenation, but also presumably because the interatomic distance becomes shorter due to densification . Also, crystallization can be achieved by removing impurities from the oxide semiconductor to increase its purity . The non-single-crystalline oxide semiconductor thus highly purified is ideally estimated to be able to achieve a field-effect mobility exceeding 10 0 cm 2 / Vsec.

[0235] Oxygen ions can be implanted into an oxide semiconductor mainly composed of In, Sn, and Zn, and heat treatment can be used to release hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor. At the same time as or after this heat treatment, the oxide semiconductor can be crystallized . By such crystallization or recrystallization treatment, a non-single-crystalline oxide semiconductor with good crystallinity can be obtained .

[0236] The effects of intentionally heating the substrate during film formation and / or performing heat treatment after film formation contribute not only to the improvement of the field-effect mobility but also to making the transistor normally off . For a transistor with an oxide semiconductor film formed without intentionally heating the substrate as the channel formation region, the threshold voltage tends to shift negatively . However, in the case of using an oxide semiconductor film formed by intentionally heating the substrate, this negative shift of the threshold voltage is eliminated . That is, the threshold voltage moves in the direction for the transistor to be normally off, and such a tendency can also be confirmed from the comparison between Fig. 20(A) and Fig. 20(B ). ).

[0237] The threshold voltage can also be controlled by changing the ratios of In, Sn, and Zn, and it is possible to expect normal-off characteristics of the transistor by setting the composition ratio to In:Sn:Zn = 2:1:3. Also, a highly crystalline oxide semiconductor film can be obtained by setting the target composition ratio to In:Sn:Zn = 2:1:3.

[0238] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher, more preferably 400°C or higher. By forming the film or performing the heat treatment at a higher temperature, it becomes possible to achieve normal-off characteristics of the transistor.

[0239] Also, by intentionally heating the substrate during film formation and / or performing heat treatment after film formation, the stability against gate bias stress can be enhanced. For example, under the conditions of 2 MV / cm, 150°C, and application for 1 hour, drifts of less than ±1.5 V, preferably less than 1.0 V, can be obtained respectively.

[0240] Actually, a BT test was performed on the transistors of sample 1, which had not undergone heat treatment after forming the oxide semiconductor film, and sample 2, which had undergone heat treatment at 650°C.

[0241] First, the substrate temperature was set to 25°C, V ds was set to 10 V, and the V gs -I ds characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C, and V was set to 0.1 V. Next, 20 V was applied to V ds so that the electric field strength applied to the gate insulating film 608 became 2 MV / cm, and it was held for 1 hour as it was. Next, V gs gswas set to 0 V. Next, the substrate temperature was set to 25°C, and V ds was set to 10 V, and the V of the transistor gs -I ds measurement was performed. This is called the plus BT test .

[0242] Similarly, first the substrate temperature was set to 25°C, and V ds was set to 10 V, and the V of the transistor gs -I d s characteristics were measured. Next, the substrate temperature was set to 150°C, and V ds was set to 0.1 V. Next , -2 gs 0 V was applied to V so that the electric field strength applied to the gate insulating film 608 became -2 MV / cm, and it was held for 1 hour as it was. Next, V was set to 0 V. Next, the substrate temperature 2 gs was set to 5°C, and V was set to 10 V, and the V of the transistor ds -I gs -I ds measurement was performed. This is called the minus BT test .

[0243] The results of the plus BT test of sample 1 are shown in Fig. 21(A), and the results of the minus BT test are shown in Fig. 21(B ). Also, the results of the plus BT test of sample 2 are shown in Fig. 22(A), and the results of the minus BT test of sample 2 are shown in Fig. 22(B).

[0244] The variations in the threshold voltage due to the plus BT test and the minus BT test of sample 1 were 1.80 V and -0.42 V, respectively . Also, the variations in the threshold voltage due to the plus BT test and the minus BT test of sample 2 were 0.79 V and 0.76 V, respectively . It can be seen that both sample 1 and sample 2 have small variations in the threshold voltage before and after the BT test, indicating high reliability .

[0245] The heat treatment can be carried out in an oxygen atmosphere, but first, it can be carried out in a nitrogen or inert gas atmosphere, or under reduced pressure, and then in an atmosphere containing oxygen. By first performing dehydration and dehydrogenation and then adding oxygen to the oxide semiconductor, the effect of the heat treatment can be enhanced. Also, to add oxygen later, a method of accelerating oxygen ions by an electric field and injecting them into the oxide semiconductor film can be applied. Defects due to oxygen deficiency are likely to be generated at the interface between the oxide semiconductor and the laminated film. However, by making the oxide semiconductor contain an excessive amount of oxygen by such heat treatment, it becomes possible to compensate for the constantly generated oxygen deficiency with excessive oxygen. The excessive oxygen mainly exists in the interstitial sites, and if the oxygen concentration is 1×10 / cm or more and 2×10 / cm

[0246] or less, it can be made to be contained in the oxide semiconductor without giving strain or the like to the crystal. Also, by making at least a part of the oxide semiconductor contain crystals by heat treatment, a more stable oxide semiconductor film can be obtained. For example, an oxide semiconductor film formed by sputtering without intentionally heating the substrate using a target with a composition ratio of In:Sn:Zn = 1 :1:1 shows a halo pattern in X-ray diffraction (XRD). This formed oxide semiconductor film can be crystallized by heat treatment. The heat treatment temperature is arbitrary, but for example, by performing heat treatment at 650°C, distinct diffraction peaks can be observed by X-ray diffraction. 16 / cm 3 20 / cm 3

[0247]

[0247]

[0248] ​​​​​​​​ Actually, XRD analysis of the In-Sn-Zn-O film was performed. For the XRD analysis, an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used, and the measurement was carried out by the Out-of-Plane method.

[0249] As samples for which XRD analysis was performed, Sample A and Sample B were prepared. The manufacturing methods of Sample A and Sample B will be described below.

[0250] An In-Sn-Zn-O film was formed with a thickness of 100 nm on a dehydrogenated quartz substrate.

[0251] The In-Sn-Zn-O film was formed using a sputtering apparatus with a power of 100 W ( DC) in an oxygen atmosphere. As the target, an In-Sn-Zn-O target with an atomic ratio of In:Sn:Zn = 1:1:1 was used. The substrate heating temperature during film formation was 200 °C. The sample thus prepared was designated as Sample A.

[0252] Next, heat treatment was performed on the sample prepared in the same manner as Sample A at a temperature of 650 °C. The heat treatment was initially carried out in a nitrogen atmosphere for 1 hour, and then, without lowering the temperature, further heat treatment was carried out in an oxygen atmosphere for 1 hour. The sample thus prepared was designated as Sample B.

[0253] Fig. 25 shows the XRD spectra of Sample A and Sample B. In Sample A, no peaks derived from crystals were observed, but in Sample B, peaks derived from crystals were observed at around 2θ = 35 deg and 37 deg - 38 deg.

[0254] Thus, an oxide semiconductor mainly composed of In, Sn, and Zn is intentionally heated during film formation. and / or by subjecting the film to heat treatment after deposition, the characteristics of the transistor can be improved. Cut.

[0255] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing the oxide semiconductor from being included in the film or removing it from the film. By removing hydrogen, which acts as a donor impurity in the conductor, high purification can be achieved. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By this, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0256] Figure 26 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the reciprocal of the substrate temperature during measurement is multiplied by 1000 (1000 / T) is the horizontal axis.

[0257] Specifically, as shown in FIG. 26, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the resistance is 0.1 aA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature At 0.1zA / μm (1×10 -22 It is possible to achieve a value of less than 100 A / μm.

[0258] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during film formation, leakage from outside the film formation chamber and outgassing from the inner wall of the film formation chamber are sufficiently suppressed, and the sputtering gas is made highly pure. This is preferable. For example, it is preferable to use a gas with a dew point of -70°C or lower so that moisture is not contained in the sputtering gas. In addition, it is preferable to use a highly purified target so that the target itself does not contain impurities such as hydrogen and moisture. Oxide semiconductors mainly composed of In, Sn, and Zn can remove moisture in the film by heat treatment. However, since the moisture release temperature is higher than that of oxide semiconductors mainly composed of In, Ga, and Zn, it is preferably formed into a film that does not contain moisture from the beginning.

[0259] In addition, in the transistors of the samples that were heat-treated at 650°C after forming the oxide semiconductor film, the relationship between the substrate temperature and the electrical characteristics was evaluated.

[0260] The transistors used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, Lov of 0 μm, and dW of 0 μm. Note that V ds was set to 10 V. Note that the substrate temperature was -40 °C, -25°C, 25°C, 75°C, 125°C, and 150°C. Here, in the transistor, the overlapping width of the gate electrode and the pair of electrodes is called Lov, and the overhang of the pair of electrodes with respect to the oxide semiconductor film is called dW.

[0261] Figure 23 shows the V ds (solid line) and the field-effect mobility (dotted line) dependencies. Also, gs Figure 24(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 24(B) shows the relationship between the substrate temperature and the field-effect mobility.

[0262] As can be seen from FIG. 24(A), the threshold voltage decreases as the substrate temperature increases. Note that the range was 1.09 V to -0.23 V at -40°C to 150°C.

[0263] Also, as can be seen from FIG. 24(B), the field-effect mobility decreases as the substrate temperature increases. Note that the range was 36 cm 2 / Vs to 32 cm 2 / Vs at -40°C to 150°C. Therefore, it can be seen that the variation in electrical characteristics is small in the above temperature range.

[0264] In a transistor having a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as main components as described above, while keeping the off-current at 1 aA / μm or less, the field-effect mobility can be 30 c m 2 / Vsec or more, preferably 40 cm 2 / Vsec or more, more preferably 60 cm 2 / Vsec or more, and the value of the on-current required for LSI can be satisfied. For example, in an FET with L / W = 33 nm / 40 nm, an on-current of 12 μA or more can flow when the gate voltage is 2.7 V and the drain voltage is 1.0 V. Also, sufficient electrical characteristics can be ensured even in the temperature range required for the operation of the transistor. With such characteristics, even if a transistor formed of an oxide semiconductor is mixed in an integrated circuit made of an Si semiconductor, an integrated circuit having a new function can be realized without sacrificing the operation speed.

[0265] The present embodiment can be implemented in appropriate combination with the above embodiment.

Example

[0266] ​​​ In this embodiment, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be described with reference to FIG. 27 and the like.

[0267] FIG. 27 is a top view and a cross-sectional view of a transistor having a coplanar top-gate and top-contact structure. FIG. 27(A) shows the top view of the transistor. Further, FIG. 27( B) shows a cross-section A1-A2 corresponding to the dashed line A1-A2 in FIG. 27(A). The transistor shown in FIG. 27(B) includes a substrate 1101, an underlying insulating layer 1102 provided on the substrate 1101, a protective insulating film 1104 provided around the underlying insulating layer 1102, a high-resistance region 1106a and a low

[0268] resistance region 1106b provided on the underlying insulating layer 1102 and the protective insulating film 1104, an oxide semiconductor film 1106 having a high-resistance region 1106a and a low resistance region 1106b, a gate insulating film 1108 provided on the oxide semiconductor film 1106, a gate electrode 1110 provided to overlap the oxide semiconductor film 110 6 with the gate insulating film 1108 interposed therebetween, a sidewall insulating film 1112 provided in contact with the side surface of the gate electrode 1110, a pair of electrodes 1114 provided in contact with at least the low-resistance region 1106b, an interlayer insulating film 1116 provided to cover at least the oxide semiconductor film 1106, the gate electrode 1110, and the pair of electrodes 1114, and a wiring 11 18 provided to be connected to at least one of the pair of electrodes 1114 through an opening provided in the interlayer insulating film 1116. Although not shown, a protective film covering the interlayer insulating film 1116 and the wiring 1118 may be provided. By providing the protective film, surface conduction of the interlayer insulating film 1116 can be prevented from occurring and the like. and the like. and has.

[0269] Although not shown, a protective film covering the interlayer insulating film 1116 and the wiring 1118 may be provided. By providing the protective film, surface conduction of the interlayer insulating film 1116 can be prevented from occurring It is possible to reduce the minute leakage current generated thereby and reduce the off-current of the transistor. It is possible.

[0270] This example can be implemented in appropriate combination with the above-described embodiment.

Example

[0271] In this example, another example of a transistor using an In-Sn-Zn-O film different from the above is shown. is shown.

[0272] FIG. 28 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. FIG. 28(A) is a top view of the transistor. Further, FIG. 28(B) shows a cross-section B1-B2 corresponding to the dashed line B1-B2 in FIG. 28(A). is shown.

[0273] The transistor shown in FIG. 28(B) includes a substrate 1600, an underlying insulating layer 1602 provided on the substrate 1600, an oxide semiconductor film 1606 provided on the underlying insulating layer 1602, a pair of electrodes 1614 in contact with the oxide semiconductor film 1606, a gate insulating film 1608 provided on the oxide semiconductor film 1606 and the pair of electrodes 1614, a gate electrode 1610 provided so as to overlap the oxide semiconductor film 1606 with the gate insulating film 1608 interposed therebetween, an interlayer insulating film 1616 provided so as to cover the gate insulating film 1608 and the gate electrode 1610, a wiring 1618 connected to the pair of electrodes 1614 through an opening provided in the interlayer insulating film 1616, and a protective film 1620 provided so as to cover the interlayer insulating film 1616 and the wiring 1618. As the substrate 1600, a glass substrate is used, and as the underlying insulating layer 1602, a silicon oxide film is used. and a pair of electrodes 1614 in contact with the oxide semiconductor film 1606, a gate insulating film 1608 provided on the oxide semiconductor film 1606 and the pair of electrodes 1614, a gate electrode 1610 provided so as to overlap the oxide semiconductor film 1606 with the gate insulating film 1608 interposed therebetween, an interlayer insulating film 1616 provided so as to cover the gate insulating film 1608 and the gate electrode 1610, a wiring 1618 connected to the pair of electrodes 1614 through an opening provided in the interlayer insulating film 1616, and a protective film 1620 provided so as to cover the interlayer insulating film 1616 and the wiring 1618.

[0274] As the substrate 1600, a glass substrate is used, and as the underlying insulating layer 1602, a silicon oxide film is used. As the oxide semiconductor film 1606, an In-Sn-Zn-O film is used, and as the pair of electrodes 1614, a tungsten film is used. As the gate insulating film 1608, a silicon oxide film is used, and as the gate electrode 161 0, a laminated structure of a tantalum nitride film and a tungsten film is used. As the interlayer insulating film 1616, a laminated structure of a silicon oxynitride film and a polyimide film is used. As the wiring 1618, a laminated structure in which a titanium film, an aluminum film, and a titanium film are formed in this order is used. As the protective film 1620, a po lyimide film can be used respectively.

[0275] In the transistor having the structure shown in Fig. 28(A), the overlapping width between the gate electrode 1610 and the pair of electrodes 1614 is called Lov. Similarly, the overhang of the pair of electrodes 1614 with respect to the oxide semiconductor film 1606 is called dW.

[0276] This embodiment can be implemented in appropriate combination with the above-described embodiment.

Example

[0277] In this example, an example of a semiconductor device having the above-described memory device will be described. The semiconductor device can enhance reliability and achieve miniaturization by using the memory device according to one aspect of the present invention. Particularly, in the case of a portable semiconductor device, if miniaturization is achieved by using the memory device according to one aspect of the present invention, the advantage that the usability of the user is improved can be obtained.

[0278] The memory device according to one aspect of the present invention is used in a display device, a notebook personal computer, an image playback device equipped with a recording medium (typically, a device having a display capable of playing a recording medium such as a DVD: Digital Versatile D isc and displaying the image). It can be used. Additionally, semiconductor devices that can use the memory device according to one aspect of the present invention include mobile phones, portable game consoles, portable information terminals, e-books, video cameras, digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (AT M), vending machines, and the like. Specific examples of these semiconductor devices are shown in FIG. 11.

[0279] FIG. 11(A) shows a portable game console, which includes a housing 7031, a housing 7032, a display unit 7033, a display unit 7034, a microphone 7035, a speaker 7036, operation keys 7037, a start button 7038, and the like. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of the portable game console. By using the memory device according to one aspect of the present invention in an integrated circuit for controlling the operation of the portable game console, a highly reliable and compact portable game console can be provided. Note that the portable game console shown in FIG. 11(A) has two display units 7033 and 7034, but the number of display units of the portable game console is not limited to this. FIG. 11(B) shows a mobile phone, which includes a housing 7041, a display unit 7042, an audio input unit 7043, an audio output unit 7044, operation keys 7045, a light receiving unit 7046, and the like. By converting the light received by the light receiving unit 7046 into an electrical signal, an external image can be captured. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of the mobile phone.

[0280] ​​​​​is achievable. By using the memory device according to one aspect of the present invention in an integrated circuit for controlling the operation of a mobile phone, a highly reliable and compact mobile phone can be provided.

[0281] FIG. 11(C) shows a portable information terminal, which includes a housing 7051, a display unit 7052, operation keys 7053, etc. In the portable information terminal shown in FIG. 11(C), a modem may be built in the housing 7051. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of the portable information terminal. By using the memory device according to one aspect of the present invention in an integrated circuit for controlling the operation of the portable information terminal, a highly reliable and compact portable information terminal can be provided.

Explanation of Reference Numerals

[0282] 100 Semiconductor substrate 101 Word line drive circuit 102a First bit line drive circuit 102b Second bit line drive circuit 102c Third bit line drive circuit 103a First cell array 103b Second cell array 103c Third cell array 104a First word line 104b Second word line 104c Third word line 105a First bit line 105b Second bit line 105c Third bit line 106a First memory cell 106b Second memory cell 106c Third memory cell 107a Transistor 107b Transistor 107c Transistor 108a Capacitive element ​​​​​108b Capacitance element 108c Capacitance element 110 Control circuit 120 Drive circuit 201 Cell array 210 Drive circuit 260 Transistor 262 Operational amplifier 312 Transistor 314 Capacitance element 322 Transistor 324 Capacitance element 332 Transistor 334 Capacitance element 342 Transistor 344 Capacitance element 352 Transistor 354 Capacitance element 362 Transistor 364 Capacitance element 401 CPU 402 Main memory 403 Clock controller 404 Cache controller 405 Serial interface 406 I / O port 407 Terminal 408 Interface 409 Cache memory 550 RF tag 551 Antenna circuit 552 Integrated circuit 553 Power supply circuit 554 Demodulation circuit 555 Modulation circuit 556 Regulator 557 Arithmetic circuit 558 Memory device 559 Boost circuit 600 Substrate 606 Element isolation insulating layer 608 Gate insulating film 610 Gate electrode 616 Channel formation region 620 Impurity region 624 Metal compound field 626 Electrode 628 Insulating film 630a Source electrode or drain electrode 630b Source electrode or drain electrode 636a Electrode 636b Electrode 636c Electrode 640 Insulating film 642a Source electrode or drain electrode 642b Source electrode or drain electrode 642c Electrode 643a Oxide conductive film 643b Oxide conductive film 644 Oxide semiconductor film 646 Gate insulating film 648a Gate electrode 648b Conductive film 650 Insulating film 652 Insulating film 654a Electrode 654b Electrode 656 Wiring 659 Conductive film 660 Transistor 662 Transistor 664 Capacitive element 670 Memory cell 810 Writing circuit 811 Reading circuit 812 Decoder 813 Level shifter 814 Selector 815 Decoder 816 Level shifter 817 Buffer 1101 Substrate 1102 Underlying insulating layer 1104 Protective insulating film 1106a High-resistance region 1106b Low-resistance region 1106 Oxide semiconductor film 1108 Gate insulating film 1110 Gate electrode 1112 Sidewall insulating film 1114 Pair of electrodes 1116 Interlayer insulating film 1118 Wiring 1600 Substrate 1602 Underlying insulating layer 1606 Oxide semiconductor film 1608 Gate insulating film 1610 Gate electrode 1614 Pair of electrodes 1616 Interlayer insulating film 1618 Wiring 1620 Protective film 7031 Housing 7032 Housing 7033 Display unit 7034 Display unit 7035 Microphone 7036 Speaker 7037 Operation key 7038 Stylus 7041 Housing 7042 Display unit 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Housing 7052 Display unit 7053 Operation key 8101 Underlying insulating layer 8102 Embedded insulating layer 8103a Semiconductor region 8103b Semiconductor region 8103c Semiconductor region 8104 Gate insulating film 8105 Gate 8106a Sidewall insulator 8106b Sidewall insulator 8107 Insulator 8108a Source 8108b Drain

Claims

1. A semiconductor device including a first transistor having a first channel formation region containing silicon, a second transistor having a second channel formation region containing an oxide semiconductor, and a capacitor element, a first gate electrode of the first transistor having a region positioned above the first channel formation region, a first insulating film having a region positioned above the first gate electrode, an oxide semiconductor film having a region positioned above the first insulating film and containing the second channel formation region, a second gate electrode of the second transistor having a region positioned above the second channel formation region, a first conductive layer having a region positioned above the first insulating film and functioning as one of a source electrode and a drain electrode of the second transistor, a second conductive layer having a region positioned above the first insulating film and functioning as the other of the source and drain of the second transistor, a second insulating film having a region positioned above the first conductive layer and a region positioned above the second conductive layer, a third conductive layer having a region positioned above the second insulating film and made of the same material as the second gate electrode, a third insulating film having a region positioned above the second gate electrode and a region positioned above the third conductive layer, a fourth insulating film having a region positioned above the third insulating film, a fourth conductive layer provided in a first opening formed in the third insulating film and the fourth insulating film and electrically connected to the second conductive layer, a fifth conductive layer provided in a second opening formed in the third insulating film and the fourth insulating film, and a sixth conductive layer having a region positioned above the fourth conductive layer and a region positioned above the fifth conductive layer and functioning as a wiring, wherein the third conductive layer has a region overlapping the first conductive layer via the second insulating film, the first conductive layer functions as one electrode of the capacitor element, and the third conductive layer functions as the other electrode of the capacitor element.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film contains In.

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