Optical sensor and method for driving the optical sensor

Abstract

Provided is a photosensor comprising: a light-receiving unit which generates charges according to incident light; a charge transfer gate for transferring the charges generated in the light-receiving unit; and a signal generation unit for generating a charge transfer signal to be applied to the charge transfer gate, wherein the signal generation unit generates the charge transfer signal so that the charge transfer gate is made to assume a charge transfer state in a first time range of a first period belonging to an n-th frame (where n is an integer equal to or greater than 1) and the charge transfer gate is made to assume the charge transfer state in a second time range of a second period belonging to an m-th frame (where m is an integer different from n and equal to or greater than 1), and, when the start time of the first period is matched with the start time of the second period, a portion of the first time range overlaps a portion of the second time range.

Description

Technical Field

[0001] The present disclosure relates to an optical sensor and a method for driving the optical sensor.

Background Art

[0002] Patent Document 1 describes a fluorescence lifetime measurement device. This device includes a measurement unit that irradiates a sample with excitation light to generate fluorescence photons and detects the generated fluorescence photons, a signal processing unit that measures the number of fluorescence photons for each of a plurality of time gates from the signal of the fluorescence photons detected by the measurement unit, an arithmetic processing unit that calculates the fluorescence lifetime based on the number of fluorescence photons measured for each of the plurality of time gates, and a control unit that controls the measurement unit, the signal processing unit, and the arithmetic processing unit. The measurement unit includes a detector that converts the fluorescence photons emitted from the excited sample into an electrical signal and outputs it to the signal processing unit. The signal processing unit amplifies the electrical signal input from the detector by an amplifier and branches it into two switches. The switches are controlled in the timing of ON / OFF operation by a gate control signal from the control unit and output the electrical signal only during the ON operation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Incidentally, according to the findings of the present inventor, in order to improve the time resolution of an image sensor and thereby improve the detection accuracy, it is necessary to control the charge transfer gate in a shorter time. However, considering the carrier migration time, there is a limit. On the other hand, in the device described in Patent Document 1, as described above, after the electrical signal from the detector is I-V converted by an amplifier, it is branched into two switches. And the ON periods of the two switches are partially overlapped. According to this, it is considered that the time resolution is improved.

[0005] However, although signals can be acquired by overlapping the ON periods of a plurality of switches for signals after I-V conversion as in the device of Patent Document 1, in an image sensor using a charge transfer gate, if the charge transfer period of the charge transfer gate is to be overlapped as in the device of Patent Document 1, it becomes difficult to distribute charges evenly. If the light receiving part is one (single element), it is considered that the configuration of the device of Patent Document 1 can be realized. However, when the light receiving parts are arranged in a one-dimensional or two-dimensional manner, the circuit scale becomes extremely large and it is lacking in practicality.

[0006] Therefore, an object of the present disclosure is to provide an optical sensor capable of improving detection accuracy by controlling a charge transfer gate, and a driving method of the optical sensor.

Means for Solving the Problems

[0007] The optical sensor according to the present disclosure includes a light receiving part that generates charges in response to incident light, a charge transfer gate for transferring the charges generated in the light receiving part, and a signal generation part for generating a charge transfer signal to be applied to the charge transfer gate. The signal generation part sets the charge transfer gate in a charge transfer state in a first time range of a first period belonging to the nth (n is an integer of 1 or more) frame, and sets the charge transfer gate in a charge transfer state in a second time range of a second period belonging to the mth (m is an integer of 1 or more different from n) frame, and generates a charge transfer signal. When the start time of the first period coincides with the start time of the second period, a part of the first time range and a part of the second time range overlap each other.

[0008] The driving method of the optical sensor according to the present disclosure is a driving method of an optical sensor having a light receiving unit that generates charges in response to incident light and a charge transfer gate for transferring the charges generated in the light receiving unit. The charge transfer gate is set to the charge transfer state in the first time range of the first period belonging to the n-th (n is an integer of 1 or more) frame, and the charge transfer gate is set to the charge transfer state in the second time range of the second period belonging to the m-th (m is an integer of 1 or more different from n) frame. A charge transfer signal applied to the charge transfer gate is generated. When the start time of the first period and the start time of the second period are made to coincide, a part of the first time range and a part of the second time range overlap with each other.

[0009] In these optical sensors and the driving method of the optical sensor, the charge transfer signal applied to the charge transfer gate for transferring the charges generated in the light receiving unit is such that the charge transfer gate is set to the charge transfer state in the first time range of the first period belonging to the n-th frame, and the charge transfer gate is set to the charge transfer state in the second time range of the second period belonging to the m-th frame. The first time range and the second time range are the ON periods of the charge transfer gate. When the start time of the first period and the start time of the second period are made to coincide, a part of the first time range and a part of the second time range overlap with each other. In this way, by overlapping the ON periods of the charge transfer gate between different frames, it becomes possible to capture at time intervals corresponding to the shift amount of the ON periods the phenomena that repeatedly occur at least corresponding to each frame. That is, the time resolution can be improved and the detection accuracy can be improved.

[0010] In the optical sensor according to the present disclosure, the n-th frame and the m-th frame may be consecutive frames to each other. In this way, the configuration in which the ON periods partially overlap between consecutive frames is effective for a phenomenon that repeatedly occurs while changing slightly. This is because the change of the phenomenon between frames becomes relatively small compared to the case where the interval between the frames having partially overlapping ON periods is long. Note that the fact that the n-th frame and the m-th frame are consecutive to each other corresponds to the case where m is n±1.

[0011] In the optical sensor according to the present disclosure, the signal generation unit may generate a charge transfer signal such that, within one frame, when the start times of a plurality of periods are made to coincide over the plurality of periods, the charge transfer gate is in a charge transfer state in an overlapping range. In this case, it becomes possible to perform charge integration within one frame.

[0012] In the optical sensor according to the present disclosure, the charge transfer gate includes a first charge transfer gate and a second charge transfer gate, and the signal generation unit may generate a charge transfer signal such that, in a first time range, one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state, and in a second time range, the above one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state. Thus, in an optical sensor including a plurality of charge transfer gates, the ON periods of at least the same charge transfer gate may be overlapped between the n-th frame and the m-th frame.

[0013] In the optical sensor according to the present disclosure, the charge transfer gate includes a first charge transfer gate and a second charge transfer gate, and the signal generation unit may generate a charge transfer signal such that, in a first time range, one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state, and in a second time range, the other of the first charge transfer gate and the second charge transfer gate is in a charge transfer state. Thus, in an optical sensor including a plurality of charge transfer gates, the ON periods of at least different charge transfer gates may be overlapped between the n-th frame and the m-th frame.

[0014] In the optical sensor according to the present disclosure, the charge transfer gate includes a first charge transfer gate and a second charge transfer gate. The signal generation unit sets the first charge transfer gate in a charge transfer state in a first time range, sets the first charge transfer gate in a charge transfer state in a second time range, and sets the second charge transfer gate in a charge transfer state in a third time range of a first period and sets the second charge transfer gate in a charge transfer state in a fourth time range of a second period, and generates a charge transfer signal. When the start time of the first period coincides with the start time of the second period, a part of the third time range and a part of the fourth time range may overlap with each other. In this way, for an optical sensor including a plurality of charge transfer gates, by partially overlapping the ON periods of the respective charge transfer gates, it is possible to reduce the number of frames while improving the time resolution.

[0015] In the optical sensor according to the present disclosure, the signal generation unit further generates a signal for the light source to output light periodically, and the start times of the first period and the second period may be synchronized with the timing at which the light source outputs light. In this case, it is possible to improve the time resolution and the detection accuracy for a phenomenon (for example, fluorescence) that repeatedly occurs in response to light from the light source.

[0016] Here, the optical sensor according to the present disclosure includes a light receiving unit that generates charges in response to incident light, a first charge transfer gate and a second charge transfer gate for transferring the charges generated in the light receiving unit, a discharge gate for discharging the charges generated in the light receiving unit, and a signal generation unit for generating a charge transfer signal to be applied to the first charge transfer gate, the second charge transfer gate, and the discharge gate. The signal generation unit generates a charge transfer signal such that the first charge transfer gate is in a charge transfer state in a first time range, the second charge transfer gate is in a charge transfer state in a second time range separated from the first time range, and the discharge gate is in a charge discharge state in a third time range between the first time range and the second time range.

[0017] Also, a method for driving an optical sensor according to the present disclosure is a method for driving an optical sensor including a light receiving unit that generates charges in response to incident light, a first charge transfer gate and a second charge transfer gate for transferring the charges generated in the light receiving unit, and a discharge gate for discharging the charges generated in the light receiving unit, the method including: setting the first charge transfer gate in a charge transfer state in a first time range, setting the second charge transfer gate in a charge transfer state in a second time range separated from the first time range, and generating a charge transfer signal such that the discharge gate is in a charge discharge state in a third time range between the first time range and the second time range.

[0018] In these optical sensors and the method for driving an optical sensor, the charge transfer signals applied to the first and second charge transfer gates for transferring the charges generated in the light receiving unit are such that the first charge transfer gate is in a charge transfer state in a first time range, the second charge transfer gate is in a charge transfer state in a second time range separated from the first time range, and the discharge gate is in a charge discharge state in a third time range between the first time range and the second time range. The first time range and the second time range are the ON periods of the charge transfer gates, and the third time range is the charge discharge period. In this way, by separating the ON periods of the charge transfer gates and providing a charge discharge period therebetween, it is possible to discharge the remaining charges generated in the light receiving unit. As a result, the detection accuracy can be improved.

[0019] In the optical sensor according to the present disclosure, the signal generation unit may generate a charge transfer signal such that each of a plurality of frames includes a first time range, a second time range, and a third time range, and when the start times of the nth (n is an integer of 1 or more) frame and the mth (m is an integer of 1 or more different from n) frame are made to coincide, the first time range of the mth frame is located between the first time range and the second time range of the nth frame. In this way, by arranging the ON periods of the charge transfer gates more densely over a plurality of frames, the detection accuracy can be further improved.

[0020] In the optical sensor according to the present disclosure, the signal generation unit may generate a charge transfer signal such that, within one frame, when the start times of a plurality of periods are made to coincide over the plurality of periods, the first charge transfer gate and the second charge transfer gate are in a charge transfer state in a time range where they overlap. In this case, it becomes possible to perform charge integration within one frame.

Advantages of the Invention

[0021] According to the present disclosure, it is possible to provide an optical sensor capable of improving detection accuracy by controlling a charge transfer gate, and a method for driving the optical sensor.

Brief Description of the Drawings

[0022]

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Mode for Carrying Out the Invention

[0023] Hereinafter, an embodiment will be described in detail with reference to the drawings. In each figure, elements that are the same or equivalent to each other are denoted by the same reference numerals, and redundant descriptions may be omitted. [First Embodiment]

[0024] FIG. 1 is a block diagram showing an optical detection device according to an embodiment. The optical detection device 100 shown in FIG. 1 is, for example, an image sensor (gate image sensor), a motion sensor, a distance measurement sensor, a distance measurement image sensor, or the like. The optical detection device 100 includes an optical sensor 50 and a light source 51. The optical sensor 50 has a sensor unit 52, a timing generator (signal generation unit) 53, and a delay circuit 54. The light source 51 includes, for example, an LED or the like and outputs pulsed light to the object. The sensor unit 52 detects light (reflected light or fluorescence) from the object in response to the pulsed light from the light source 51. The sensor unit 52 includes a plurality of pixel units RS arranged in a two-dimensional manner. The sensor unit 52 can be configured by monolithically forming the pixel unit RS and the CMOS readout circuit unit on a semiconductor substrate (for example, a silicon substrate).

[0025] FIG. 2 is a schematic plan view of the pixel portion shown in FIG. 1. FIG. 3 is a cross-sectional view of the pixel portion shown in FIG. 2. FIG. 3(a) is a cross-sectional view taken along line IIIa-IIIa of FIG. 2, and FIG. 3(b) is a cross-sectional view taken along line IIIb-IIIb of FIG. 2. As shown in FIGS. 2 and 3, the photosensor 50 includes a semiconductor substrate 1 having a first main surface 1a and a second main surface 1b facing each other in the sensor portion 52 (pixel portion RS). The semiconductor substrate 1 includes a p-type first semiconductor region 3 located on the first main surface 1a side and a p - type second semiconductor region 5 having an impurity concentration lower than that of the first semiconductor region 3 and located on the second main surface 1b side. The semiconductor substrate 1 can be obtained, for example, by growing a p - type epitaxial layer having an impurity concentration lower than that of the semiconductor substrate on the p-type semiconductor substrate. An insulating layer 7 is formed on the second main surface 1b (second semiconductor region 5) of the semiconductor substrate 1.

[0026] A photogate electrode PG is disposed on the insulating layer 7. The photogate electrode PG has a rectangular shape in plan view. In the present embodiment, the photogate electrode PG has a rectangular shape. The region of the semiconductor substrate 1 (second semiconductor region 5) corresponding to the photogate electrode PG (the region located below the photogate electrode PG in FIG. 3) functions as a light receiving portion 2 that generates charges in response to incident light. That is, the photosensor 50 includes a plurality of light receiving portions 2 arranged two-dimensionally (the arrangement of the light receiving portions 2 may be one-dimensional).

[0027] In the second semiconductor region 5, n-type third semiconductor regions 9a and 9b having a high impurity concentration are formed to face regions that are separated from the photogate electrode PG. The third semiconductor region 9a is a first charge storage portion for storing charges generated in the light receiving portion 2, and the third semiconductor region 9b is similarly a second charge storage portion for storing charges generated in the light receiving portion 2. The third semiconductor regions 9a and 9b are arranged to face each other with the photogate electrode PG interposed therebetween. The third semiconductor regions 9a and 9b have a rectangular shape in plan view. In the present embodiment, the third semiconductor regions 9a and 9b have a square shape.

[0028] In the second semiconductor region 5, n-type third semiconductor regions 9c and 9d with high impurity concentrations are formed to face regions that are located away from the photogate electrode PG, respectively. The third semiconductor region 9c is a third charge storage portion for storing charges generated in the light receiving portion 2, and the third semiconductor region 9d is similarly a fourth charge storage portion for storing charges generated in the light receiving portion 2. The third semiconductor regions 9c and 9d are arranged to face each other with the photogate electrode PG interposed therebetween.

[0029] The third semiconductor regions 9a and 9c are arranged to face each other with a fourth semiconductor region 11a, which will be described later, interposed therebetween. The third semiconductor regions 9b and 9d are arranged to face each other with a fourth semiconductor region 11b, which will be described later, interposed therebetween. The third semiconductor regions 9c and 9d are rectangular in plan view. In the present embodiment, the third semiconductor regions 9c and 9d are square.

[0030] In the second semiconductor region 5, n-type fourth semiconductor regions 11a and 11b with high impurity concentrations are formed in regions that are located away from the respective photogate electrodes PG. The fourth semiconductor regions 11a and 11b are charge discharge portions for discharging charges generated in the light receiving portion 2 to the outside. In the present embodiment, three pairs of the fourth semiconductor regions 11a and 11b are arranged with respect to the photogate electrode PG. The fourth semiconductor regions 11a and 11b are arranged to face each other with the photogate electrode PG interposed therebetween. The fourth semiconductor regions 11a and 11b are rectangular in plan view. In the present embodiment, the fourth semiconductor regions 11a and 11b are square.

[0031] Note that in the present embodiment, "high impurity concentration" means, for example, an impurity concentration of 1×10 17 cm -3 or more, and is indicated by attaching "+" to the conductivity type. On the other hand, "low impurity concentration" means, for example, 10×10 15 cm -3 or less, and is indicated by attaching "-" to the conductivity type. The thickness / impurity concentration of each semiconductor region is as follows. First semiconductor region 3: thickness 10 to 1000 μm / impurity concentration 1×10 12~10 19 cm -3 。The second semiconductor region 5: thickness 1 to 50 μm / impurity concentration 1×10 12 ~10 15 cm -3 。The third semiconductor regions 9a, 9b and the fourth semiconductor regions 11a, 11b: thickness 0.1 to 1 μm / impurity concentration 1×10 18 ~10 20 cm -3 。

[0032] A reference potential such as a ground potential is applied to the semiconductor substrate 1 (the first semiconductor region 3 and the second semiconductor region 5) via a back gate or a through electrode or the like.

[0033] On the insulating layer 7, transfer electrodes TX1, TX2, TX3, and transfer electrode TX4 are arranged corresponding to the photogate electrode PG. The transfer electrode TX1 is located between the photogate electrode PG and the third semiconductor region 9a and is arranged away from the photogate electrode PG. The transfer electrode TX2 is located between the photogate electrode PG and the third semiconductor region 9b and is arranged away from the photogate electrode PG.

[0034] The transfer electrode TX3 is located between the photogate electrode PC and the third semiconductor region 9c and is arranged away from the photogate electrode PG. The transfer electrode TX4 is located between the photogate electrode PG and the third semiconductor region 9d and is arranged spaced apart from the photogate electrode PG. The transfer electrodes TX1 to TX4 are rectangular in plan view. In the present embodiment, the transfer electrodes TX1 to TX4 are rectangular.

[0035] The region corresponding to the transfer electrode TX1 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below the transfer electrode TX1) functions as a charge transfer gate 4a for transferring the charges generated in the light receiving part 2 to the third semiconductor region 9a which is the first charge accumulation part. The region corresponding to the transfer electrode TX2 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below the transfer electrode TX2) functions as a charge transfer gate 4b for transferring the charges generated in the light receiving part 2 to the third semiconductor region 9b which is the second charge accumulation part.

[0036] The region corresponding to the transfer electrode TX3 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below the transfer electrode TX3) functions as a charge transfer gate 4c for transferring the charges generated in the light receiving part 2 to the third semiconductor region 9c which is the third charge accumulation part. The region corresponding to the transfer electrode TX4 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below the transfer electrode TX4) functions as a charge transfer gate 4d for transferring the charges generated in the light receiving part 2 to the third semiconductor region 9d which is the fourth charge accumulation part.

[0037] On the insulating layer 7, corresponding to the photogate electrode PG, a plurality (here, six) of transfer electrodes TX5 are arranged. A part on one side of the photogate electrode PG among the plurality of transfer electrodes TX5 is located between the photogate electrode PG and the fourth semiconductor region 11a, and is arranged away from the photogate electrode PG with the transfer electrode TX1 and the transfer electrode TX3 interposed therebetween. The remaining part on the other side of the photogate electrode PG among the plurality of transfer electrodes TX5 is located between the photogate electrode PG and the fourth semiconductor region 11b, and is arranged away from the photogate electrode PG with the transfer electrode TX2 and the transfer electrode TX4 interposed therebetween. The transfer electrode TX5 has a rectangular shape in plan view. In the present embodiment, the transfer electrode TX5 has a rectangular shape and has the same shape as the transfer electrode TX1 and the like.

[0038] The region corresponding to one transfer electrode TX5 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below one transfer electrode TX5) functions as a discharge gate 6a for transferring the charges generated in the light receiving portion 2 to the fourth semiconductor region 11a which is a charge discharging portion. The region corresponding to the other transfer electrode TX5 in the semiconductor substrate 1 (the second semiconductor region 5) (in FIG. 3, the region located below the other transfer electrode TX5) functions as a discharge gate 6b for transferring the charges generated in the light receiving portion 2 to the fourth semiconductor region 11b which is a charge discharging portion. Thus, the discharge gates 6a and 6b are for discharging the charges generated in the light receiving portion 2.

[0039] Note that the length dimension in the facing direction of the transfer electrodes TX1 to TX5 with respect to the photogate electrode PG, that is, the gate width of the transfer electrodes TX1 to TX5, is determined according to the transferable distance of the signal charges and unnecessary charges so as to cover the region of the photogate electrode PG where the high-speed transfer of the signal charges and unnecessary charges is possible in the transfer electrodes TX1 to TX5.

[0040] The insulating layer 7 is provided with contact holes for exposing the surface of the first semiconductor region 3. Conductors 13 for externally connecting the third semiconductor regions 9a and 9b and the fourth semiconductor regions 11a and 11b are disposed in the contact holes. The semiconductor substrate is made of Si as an example, and the insulating layer 7 is made of SiO2 as an example. The photogate electrode PG and the transfer electrodes TX1 to TX5 are made of polysilicon as an example. Note that these may be made of other materials.

[0041] As described above, the third semiconductor regions 9a and 9b are for accumulating the charges generated in the light receiving portion 2 in response to incident light. The phases of the charge transfer signals applied to the transfer electrodes TX1 to TX4 are different from each other. The light incident on one pixel portion RS is converted into charges in the semiconductor substrate 1 (the second semiconductor region 5), and a part of the charges thus generated travels in the direction of the transfer electrodes TX1 to TX4 along the potential gradient formed by the voltage applied to the photogate electrode PG and the transfer electrodes TX1 to TX4 as signal charges.

[0042] When a positive potential is applied to the transfer electrodes TX1 to TX4, the potential under the transfer electrodes TX1 to TX4 becomes lower for electrons than the potential of the semiconductor substrate 1 (second semiconductor region 5) in the portion under the photogate electrode PG. Negative charges (electrons) are drawn in the direction of the transfer electrodes TX1 to TX4 and accumulated in the potential wells formed by the third semiconductor regions 9a to 9d.

[0043] The n-type semiconductor contains positively ionized donors, has a positive potential, and attracts electrons. When a potential (ground potential) lower than the positive potential is applied to the transfer electrodes TX1 to TX4, a potential barrier is generated by the transfer electrodes TX1 to TX4, and the charges generated in the semiconductor substrate 1 are not drawn into the third semiconductor regions 9a to 9d.

[0044] The fourth semiconductor regions 11a and 11b are for collecting unnecessary charges generated in the light receiving portion 2 in response to incident light and discharging them to the outside. Of the charges generated in the semiconductor substrate 1 (second semiconductor region 5) when light is incident on one pixel portion RS, some charges, as unnecessary charges, travel in the direction of the transfer electrode TX5 according to the potential gradient formed by the voltage applied to the photogate electrode PG and the transfer electrode TX5.

[0045] When a positive potential is applied to the transfer electrode TX5, the potential under the transfer electrode TX5 becomes lower for electrons than the potential of the semiconductor substrate 1 (second semiconductor region 5) in the portion under the photogate electrode PG. Negative charges (electrons) are drawn in the direction of the transfer electrode TX5 and accumulated in the potential wells formed by the fourth semiconductor regions 11a and 11b. When a potential (ground potential) lower than the positive potential is applied to the transfer electrode TX5, a potential barrier is generated by the transfer electrode TX5, and the charges generated in the semiconductor substrate 1 are not drawn into the fourth semiconductor regions 11a and 11b.

[0046] FIG. 4 is a diagram showing the potential distribution in the vicinity of the second main surface 1b of the semiconductor substrate 1 for explaining the signal charge accumulation operation. FIG. 5 is a diagram showing the potential distribution in the vicinity of the second main surface 1b of the semiconductor substrate 1 for explaining the unnecessary charge discharge operation. In FIGS. 4 and 5, the downward direction is the positive direction of the potential. In FIG. 4, (a) and (b) show the potential distribution along the lateral direction of the lateral cross-section of FIG. 2, and (c) shows the potential distribution along the lateral direction of the lateral cross-section of FIG. 3. In FIG. 5, (a) shows the potential distribution along the lateral direction of the lateral cross-section of FIG. 2, and (b) shows the potential distribution along the lateral direction of the lateral cross-section of FIG. 3.

[0047] In FIGS. 4 and 5, the potential φ TX1 in the region directly below the transfer electrode TX1 (charge transfer gate 4a), the potential φ TX2 in the region directly below the transfer electrode TX2 (charge transfer gate 4b), the potential φ TX5 in the region directly below the transfer electrode TX5 (discharge gates 6a, 6b), the potential φ PG of the light receiving portion 2 directly below the photogate electrode PG, the potential φ FD1 of the third semiconductor region 9a, the potential φ FD2 of the third semiconductor region 9b, the potential φ OFD1 of the fourth semiconductor region 11a, and the potential φ OFD2 of the fourth semiconductor region 11b are shown.

[0048] The potential φ PG of the light receiving portion 2 directly below the photogate electrode PG is set higher than this reference potential with respect to the potential (φ TX1 , φ TX2 , φ TX5 ) of the adjacent transfer electrodes TX1, TX2 and the region directly below the transfer electrode TX5 when there is no bias. This potential φ PG of the light receiving portion 2 is higher than φ TX1 , φ TX2 , φ TX5 , and the potential distribution in this region has a shape concave downward in the drawing.

[0049] Referring to FIG. 4, the charge storage operation of the signal charge will be described. When the phase of the charge transfer signal applied to the transfer electrode TX1 is 0 degrees, a positive potential is applied to the transfer electrode TX1, and an inverted-phase potential, that is, a potential with a phase of 180 degrees (ground potential), is applied to the transfer electrode TX2. In this case, as shown in FIG. 4(a), the negative charge e generated in the light receiving section 2 causes the potential φ TX1 in the region directly below the transfer electrode TX1 to drop, and thus flows into the potential well of the third semiconductor region 9a.

[0050] On the other hand, the potential φ TX2 in the region directly below the transfer electrode TX2 does not drop, and no charge flows into the potential well of the third semiconductor region 9b. In the third semiconductor regions 9a and 9b, since n-type impurities are added, the potential is recessed in the positive direction.

[0051] When the phase of the charge transfer signal applied to the transfer electrode TX2 is 0 degrees, a positive potential is applied to the transfer electrode TX2, and an inverted-phase potential, that is, a potential with a phase of 180 degrees (ground potential), is applied to the transfer electrode TX1. In this case, as shown in FIG. 4(b), the negative charge e generated in the light receiving section 2 causes the potential φ TX2 in the region directly below the transfer electrode TX2 to drop, and thus flows into the potential well of the third semiconductor region 9b. On the other hand, the potential φ TX1 in the region directly below the transfer electrode TX1 does not drop, and no charge flows into the potential well of the third semiconductor region 9a. As a result, the signal charge is collected and stored in the potential well of the third semiconductor region 9b. In this way, a potential gradient is formed with respect to the light receiving section 2 here.

[0052] While charge transfer signals with a phase shift of 180 degrees are applied to the transfer electrode TX1 and the transfer electrode TX2, a ground potential is applied to the transfer electrode TX5. For this reason, as shown in FIG. 4(c), the potential φ TX5 in the region directly below the transfer electrode TX5 does not drop, and no charge flows into the potential wells of the fourth semiconductor regions 11a and 11b.

[0053] As described above, the signal charges are collected and stored in the potential wells of the third semiconductor regions 9a and 9b. The signal charges stored in the potential wells of the third semiconductor regions 9a and 9b are read out externally. In the above example, the pair of transfer electrodes TX1 and TX2 has been described, but the same applies to the pair of transfer electrodes TX3 and TX4.

[0054] As described above, when a predetermined potential is applied to the transfer electrodes TX1 to TX4, the regions directly below them, that is, the charge transfer gates 4a to 4d, are in a state where they can transfer charges to the respective third semiconductor regions 9a to 9d, which may be referred to as a charge transfer state. Also, the fact that the charge transfer gates 4a to 4d are in the charge transfer state may also be referred to as the charge transfer gates 4a to 4d being in the ON state.

[0055] Subsequently, referring to FIG. 5, the operation of discharging unnecessary charges will be described. The transfer electrodes TX1 and TX2 (and further, the transfer electrodes TX3 and TX4) are given a ground potential. Therefore, as shown in FIG. 5(a), the potentials φ TX1 , φ TX2 below the transfer electrodes TX1 and TX2 do not decrease, and charges do not flow into the potential wells of the third semiconductor regions 9a and 9b.

[0056] On the other hand, a positive potential is applied to the transfer electrode TX5. In this case, as shown in FIG. 5(b), the negative charges e generated in the light receiving portion 2 flow into the potential wells of the fourth semiconductor regions 11a and 11b due to the decrease in the potential φ TX5 below the transfer electrode TX5. As described above, the unnecessary charges are collected in the potential wells of the fourth semiconductor regions 11a and 11b. The unnecessary charges collected in the potential wells of the fourth semiconductor regions 11a and 11b are discharged externally.

[0057] As described above, a predetermined potential is applied to the transfer electrodes TX5, and the regions immediately below them, i.e., the discharge gates 6a and 6b, are in a state where they can transfer charges to the respective fourth semiconductor regions 11a and 11b, which may be referred to as the charge discharge state. Also, the state where the discharge gates 6a and 6b are in the charge discharge state may be referred to as the state where the discharge gates 6a and 6b are in the ON state.

[0058] Note that the optical sensor 50 includes a reset transistor (not shown) provided in the sensor unit 52 (pixel unit RS). By applying a reset voltage to the reset transistor, a reset process is executed. The reset voltage is a positive voltage with reference to the potential of the photogate electrode PG. As a result, the charges accumulated in the third semiconductor regions 9a to 9d, which are charge accumulation units, are discharged to the outside and the state where no charges are accumulated is achieved.

[0059] Continuing to refer to FIG. 1, the timing generator 53 generates the above charge transfer signal S1 and provides the charge transfer signal S1 to each of the transfer electrodes TX1 to TX5. Also, the timing generator 53 generates a drive signal S2 for the light source 51. The timing generator 53 provides the generated drive signal S2 to the delay circuit 54.

[0060] Here, the charge transfer signal S1 and the drive signal S2 are associated with each other (synchronized). The delay circuit 54 inputs the drive signal S2 from the timing generator 53, applies a certain delay to generate a new drive signal S3, and provides the drive signal S3 to the light source 51. The charge transfer signal S1 is associated with (synchronized with) the drive signal S3 via the drive signal S2. The light source 51 is driven by the drive signal S3 and outputs pulsed light. Note that the timing generator 53 and the delay circuit 54 may be integrated inside the sensor unit 52.

[0061] The above light detection device 100 (optical sensor 50) is used, for example, in fluorescence lifetime measurement. As shown in FIG. 6, in this case, the object is irradiated with excitation light L1, which is pulsed light, from the light source 51 at time T1, and the sensor unit 52 receives fluorescence L2 from the object excited by the excitation light L1. The fluorescence L2 enters the sensor unit 52, for example, at time T2 and decays within a predetermined time.

[0062] In the optical sensor 50, a plurality of time ranges t k (k = 1, 2, …, 16) are set for a predetermined period from the peak of the fluorescence L2, and for each time range t k , the charges generated in the light receiving unit 2 are distributed and transferred to the charge transfer gates 4a to 4d and accumulated in each of the third semiconductor regions 9a to 9d, which are charge accumulation units. For this purpose, the timing generator 53 generates a charge transfer signal S1 to be applied to the charge transfer gates 4a to 4d via the transfer electrodes TX1 to TX4.

[0063] As described above, here, since 16 time ranges t k are set for the fluorescence L2, one charge transfer gate is in a charge transfer state (ON state) in each of the four frames for different time ranges t k . As an example, in the first frame, the charge transfer gate 4a is in the time range t1, the charge transfer gate 4b is in the time range t5, the charge transfer gate 4c is in the time range t9, and the charge transfer gate 4d is in the time range t 13 and is set to the ON state. In the second frame, the charge transfer gate 4a is in the time range t2, the charge transfer gate 4b is in the time range t6, the charge transfer gate 4c is in the time range t 10 , and the charge transfer gate 4d is in the time range t 14 and is set to the ON state.

[0064] In the third frame, the charge transfer gate 4a is in the time range t3, the charge transfer gate 4b is in the time range t7, the charge transfer gate 4c is in the time range t 11 , and the charge transfer gate 4d is in the time range t 15is set to the ON state. Further, in the fourth frame, the charge transfer gate 4a is in the time range t4, the charge transfer gate 4b is in the time range t8, the charge transfer gate 4c is in the time range t 12 , and the charge transfer gate 4d is in the time range t 14 is set to the ON state. As a result, for all the time ranges t k , any one of the charge transfer gates is set to the ON state, and charges are accumulated in the third semiconductor regions 9a to 9d.

[0065] Note that the time range t k may be set such that at least a pair of time ranges t n , t m (n, m are different numbers from 1 to 16) partially overlap. Alternatively, the time range t k may be set such that at least a pair of time ranges t n , t m are set to be separated from each other, and a time range in which the discharge gates 6a and 6b are set to the ON state is interposed between the time range t n and the time range t m .

[0066] Subsequently, a specific driving method of the optical sensor 50 will be described. FIGS. 7 and 8 are timing charts of signals generated by the timing generator shown in FIG. 1. In FIGS. 7 and 8, Pixel_reset indicates a reset signal and shows the timing at which the reset process is executed. Lightsource is the driving signal S2 provided to the light source 51 (delay circuit 54) and shows the timing of the emission of the excitation light L1.

[0067] Also, VTX1 represents the charge transfer signal applied to the charge transfer gate 4a via the transfer electrode TX1, VTX2 represents the charge transfer signal applied to the charge transfer gate 4b via the transfer electrode TX2, VTX3 represents the charge transfer signal applied to the charge transfer gate 4c via the transfer electrode TX3, and VTX4 represents the charge transfer signal applied to the charge transfer gate 4d via the transfer electrode TX4. Further, VTX5=Drain represents the charge transfer signal applied to the discharge gates 6a, 6b via the transfer electrode TX5.

[0068] Also, (a) of FIG. 7 shows the first frame A1, (b) of FIG. 7 shows the second frame A2, (a) of FIG. 8 shows the third frame A3, and (b) of FIG. 8 shows the fourth frame A4. The frames A1 to A4 are temporally continuous in this order. Each of the frames A1 to A4 is defined as, for example, the period between a pair of reset processes.

[0069] Also, frame A1 includes a plurality of periods B1. The period B1 is defined as the period during the emission of the excitation light L1 in frame A1. That is, the start time B1a of the period B1 is the emission time of one excitation light L1 in frame A1, and the end time B1b of the period B1 is the emission time of the next excitation light L1 of the one excitation light L1 in frame A1. Frame A2 includes a plurality of periods B2. The period B2 is defined as the period during the emission of the excitation light L1 in frame A2. That is, the start time B2a of the period B2 is the emission time of one excitation light L1 in frame A2, and the end time B2b of the period B2 is the emission time of the next excitation light L1 of the one excitation light L1 in frame A2.

[0070] Further, frame A3 includes a plurality of periods B3. Period B3 is defined as the period during the emission of the excitation light L1 in frame A3. That is, the start time B3a of period B3 is the emission time of one excitation light L1 in frame A3, and the end time B3b of period B3 is the emission time of the next excitation light L1 of the one excitation light L1 in frame A3. Furthermore, frame A4 includes a plurality of periods B4. Period B4 is defined as the period during the emission of the excitation light L1 in frame A4. That is, the start time B4a of period B4 is the emission time of one excitation light L1 in frame A4, and the end time B4b of period B4 is the emission time of the next excitation light L1 of the one excitation light L1 in frame A4.

[0071] Here, periods B1 to B4 have the same length as each other, and the time differences from the start times of frames A1 to A4 are also the same. Therefore, when the start times B1a to B4a of periods B1 to B4 are made to coincide, the end times B1b to B4b also coincide (that is, they all overlap).

[0072] In period B1 belonging to frame A1, first, in time range C1, a charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer electrode TX1 so that charge transfer gate 4a becomes in a charge transfer state (ON state). Subsequently, in period B1, in time range C2, a charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer electrode TX2 so that charge transfer gate 4b becomes in the ON state. Subsequently, in period B1, in time range C3, a charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer electrode TX3 so that charge transfer gate 4c becomes in the ON state.

[0073] Thereafter, in period B1, in time range C4, a charge transfer signal VTX4 is applied to charge transfer gate 4d via transfer electrode TX4 so that charge transfer gate 4d becomes in the ON state. Frame A1 includes a plurality (here, continuously) of such periods B1.

[0074] Subsequently, in period B2 belonging to frame A2, first, in time range D1, a charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer electrode TX1 so that the charge transfer gate 4a becomes ON. Subsequently, in period B2, in time range D2, a charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer electrode TX2 so that the charge transfer gate 4b becomes ON. Subsequently, in period B2, in time range D3, a charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer electrode TX3 so that the charge transfer gate 4c becomes ON.

[0075] Thereafter, in period B2, in time range D4, a charge transfer signal VTX4 is applied to charge transfer gate 4d via transfer electrode TX4 so that the charge transfer gate 4d becomes ON. Frame A2 includes a plurality (here, continuously) of such periods B2.

[0076] Subsequently, in period B3 belonging to frame A3, first, in time range E1, a charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer electrode TX1 so that the charge transfer gate 4a becomes ON. Subsequently, in period B3, in time range E2, a charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer electrode TX2 so that the charge transfer gate 4b becomes ON. Subsequently, in period B3, in time range E3, a charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer electrode TX3 so that the charge transfer gate 4c becomes ON.

[0077] Thereafter, in period B3, in time range E4, a charge transfer signal VTX4 is applied to charge transfer gate 4d via transfer electrode TX4 so that the charge transfer gate 4d becomes ON. Frame A3 includes a plurality (here, continuously) of such periods B3.

[0078] Furthermore, in period B4 belonging to frame A4, first, in time range F1, a charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer electrode TX1 so that charge transfer gate 4a becomes ON. Subsequently, in period B4, in time range F2, a charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer electrode TX2 so that charge transfer gate 4b becomes ON. Subsequently, in period B4, in time range F3, a charge transfer signal VTX3 is applied to charge transfer gate 4c via transfer electrode TX3 so that charge transfer gate 4c becomes ON.

[0079] Thereafter, in period B4, in time range F4, a charge transfer signal VTX4 is applied to charge transfer gate 4d via transfer electrode TX4 so that charge transfer gate 4d becomes ON. Frame A4 includes a plurality (here, continuously) of such periods B4. Note that each of time ranges C1 to C4, time ranges D1 to D4, time ranges E1 to E4, and time ranges F1 to F4 has the same length.

[0080] As described above, the timing generator 53 sets the charge transfer gate in the charge transfer state in the first time range of the first period belonging to the nth (n is an integer of 1 or more) frame, and sets the charge transfer gate in the charge transfer state in the second time range of the second period belonging to the mth (m is an integer of 1 or more different from n) frame, and generates a charge transfer signal.

[0081] Here, as an example, n and m are consecutive integers (that is, m = n ± 1). Therefore, as an example, when n = 1 and m = 2, the timing generator 53 sets charge transfer gate 4a to the ON state in time range C1 (the first time range) of period B1 (the first period) belonging to frame A1, and generates charge transfer signal VTX1 so that charge transfer gate 4a is set to the ON state in time range D1 (the second time range) of period B2 (the second period) belonging to frame A2. The same applies to other combinations of n and m.

[0082] On the other hand, the timing generator 53 similarly generates charge transfer signals VTX2 to VTX4 for the charge transfer gates 4b to 4c. As an example, assuming n = 1, m = 2, and focusing on the charge transfer gate 4b, the timing generator 53 turns on the charge transfer gate 4b in the time range (the third time range) C2 of the period (the first period) B1 belonging to the frame A1, and turns on the charge transfer gate 4b in the time range (the fourth time range) D2 of the period (the second period) B2 belonging to the frame A2, so as to generate the charge transfer signal VTX2. The same applies when the first charge transfer gate and the second charge transfer gate are the charge transfer gates 4c and 4d.

[0083] Here, when the timing generator 53 makes the start time of the first period coincide with the start time of the second period, it generates the charge transfer signals VTX1 to VTX4 such that a part of the first time range and a part of the second time range overlap each other. Also, when the timing generator 53 makes the start time of the first period coincide with the start time of the second period, it generates the charge transfer signals VTX1 to VTX4 such that a part of the third time range and a part of the fourth time range overlap each other.

[0084] As an example, assuming n = 1, m = 2, the first time range is the time range C1, and the second time range is the time range D1, when the timing generator 53 makes the start time B1a of the period (the first period) B1 belonging to the frame A1 coincide with the start time B2a of the period (the second period) B2 belonging to the frame A2, it generates the charge transfer signal VTX1 such that only a part of the time range (the first time range) C1 within the period B1 and the time range (the second time range) D1 within the period B2 overlap. Here, the deviation amount between the time range C1 and the time range D1 is, for example, half of the time of the time ranges C1 and D1.

[0085] Also, when n = 1, m = 2, the third time range is set as time range C2, and the fourth time range is set as time range D2, the timing generator 53 makes the start time B1a of the period (the first period) B1 belonging to frame A1 coincide with the start time B2a of the period (the second period) B2 belonging to frame A2, and then generates the charge transfer signal VTX2 such that only a part of the time range (the third time range) C2 within period B1 and the time range (the fourth time range) D2 within period B2 overlap. Here, as an example, the deviation amount between time range C2 and time range D2 is also half of the time of time ranges C2 and D2. The same applies to other combinations of n and m, and combinations of time ranges.

[0086] As described above, among the plurality of charge transfer gates 4a to 4d, when the charge transfer gate 4a is the first charge transfer gate and the charge transfer gate 4b is the second charge transfer gate, the above example can be paraphrased as follows. That is, the timing generator 53 turns on the first charge transfer gate among the first charge transfer gate and the second charge transfer gate in the first time range (here, time range C1) which is one of a pair of mutually overlapping time ranges, and turns on the first charge transfer gate among the first charge transfer gate and the second charge transfer gate in the second time range (here, time range D1) which is the other of the pair of mutually overlapping time ranges, so as to generate the charge transfer signal VTX1.

[0087] At this time, the timing generator 53 further generates the charge transfer signal VTX2 such that the second charge transfer gate is turned on in the third time range (here, time range C2) which is one of another pair of mutually overlapping time ranges, and the second charge transfer gate is turned on in the fourth time range (here, time range D2) which is the other of the another pair of mutually overlapping time ranges. Note that any of the charge transfer gates 4a to 4d can be the first charge transfer gate and the second charge transfer gate.

[0088] Note that the amount of deviation between the time range C1 and the time range D1, and the amount of deviation between the time range C2 and the time range D2, i.e., the amount of deviation during the ON period, is not limited to 1 / 2 of the respective time ranges C1, C2, D1, D2, etc., but is arbitrary, such as 1 / 4, 1 / 8, or 3 / 4.

[0089] Also, the timing generator 53 generates a charge transfer signal so that, within one frame, when the start times of the periods are made to coincide over a plurality of periods, the charge transfer gate is in the charge transfer state for the overlapping time ranges. As an example, the timing generator 53 generates a charge transfer signal VTX1 so that, within the frame A1, when the start time B1a of the period B1 is made to coincide over a plurality of periods B1, the charge transfer gate 4a is in the ON state for the overlapping time range C1. Thereby, charge integration is performed in the charge accumulation unit. The same applies to other frames, periods, and charge transfer gates.

[0090] As described above, in the optical sensor 50 and the driving method of the optical sensor 50, the charge transfer signal applied to the charge transfer gate for transferring the charge generated in the light receiving unit 2 is such that the charge transfer gate (e.g., the charge transfer gate 4a) is in the ON state in the first time range (e.g., the time range C1) of the first period (e.g., the period B1) belonging to the nth frame (e.g., the frame A1), and the charge transfer gate (e.g., the charge transfer gate 4a) is in the ON state in the second time range (e.g., the time range D1) of the second period (e.g., the period B2) belonging to the mth frame (e.g., the frame A2).

[0091] The first time range and the second time range are the ON periods of the charge transfer gate. When the start time of the first period (for example, start time B1a) and the start time of the second period (for example, B2a) are made to coincide, a part of the first time range and a part of the second time range overlap each other. In this way, by overlapping the ON periods of the charge transfer gate between different frames, a phenomenon (for example, fluorescence L2 corresponding to the excitation light L1 irradiated in each period) that repeatedly occurs at least corresponding to each frame can be captured at a time interval (for example, 1 / 2 of the time ranges C1 and D1) corresponding to the shift amount of the ON period. That is, the time resolution can be improved and the detection accuracy can be improved.

[0092] Note that, as described above, the device configuration described in Patent Document 1 is considered to be realizable if the light receiving unit is one (single element). However, when the light receiving units are arranged in a one-dimensional or two-dimensional manner, the circuit scale becomes extremely large and it is lacking in realizability. On the other hand, in the optical sensor 50 according to the present embodiment, since high-precision detection is achieved by the timing control of the charge transfer gates 4a to 4d, even when a plurality of light receiving units 2 are provided in an array, the sensor structure can be prevented from being complicated, and as a result, realizability is ensured.

[0093] Further, in the optical sensor 50, the nth frame and the mth frame are consecutive frames to each other. In this way, a configuration in which the ON periods partially overlap between consecutive frames (for example, between frame A1 and frame A2) is effective for a phenomenon that repeatedly occurs while slightly changing. This is because the change of the phenomenon between the frames becomes relatively small compared to the case where the interval between the frames whose ON periods partially overlap is long.

[0094] Also, in the optical sensor 50, the timing generator 53 causes the first charge transfer gate (e.g., charge transfer gate 4a) to be in the ON state in the overlapping range (e.g., time range C1) when the start times (e.g., start time B1a) of the plurality of periods (e.g., period B1) are made to coincide within one frame (e.g., frame A1). To do this, a charge transfer signal (e.g., charge transfer signal VTX1) is generated. In this case, it becomes possible to perform charge integration within one frame.

[0095] Also, in the optical sensor 50, the timing generator 53 causes one of the first charge transfer gate (e.g., charge transfer gate 4a) and the second charge transfer gate (e.g., charge transfer gate 4b) to be in the ON state in the first time range (e.g., time range C1), and causes the above one of the first charge transfer gate and the second charge transfer gate to be in the ON state in the second time range (e.g., time range D1). To do this, a charge transfer signal (e.g., charge transfer signal VTX1) is generated. Thus, in the optical sensor 50 including a plurality of charge transfer gates 4a to 4d, the ON periods of at least the same charge transfer gate may overlap between the nth frame and the mth frame.

[0096] Further, in the optical sensor 50, the timing generator 53 further generates a charge transfer signal (e.g., charge transfer signal VTX2) to be applied to the second charge transfer gate so that the second charge transfer gate (e.g., charge transfer gate 4b) is in the ON state in the third time range (e.g., time range C2) of the first period (e.g., period B1), and the second charge transfer gate is in the ON state in the fourth time range (e.g., time range D2) of the second period (e.g., period B2). When the start time (e.g., start time B1a) of the first period and the start time (e.g., start time B2a) of the second period are made to coincide, a part of the third time range and a part of the fourth time range overlap with each other. Thus, by partially overlapping the ON periods of the respective charge transfer gates for the optical sensor 50 including a plurality of charge transfer gates, it is possible to reduce the number of frames while improving the time resolution.

[0097] Furthermore, in the optical sensor 50, the timing generator 53 further generates a drive signal S2 for the light source 51 to periodically output the excitation light L1. And the start times (for example, start times B1a and B2a) of the first period (for example, period B1) and the second period (for example, period B2) are synchronized with the timing at which the light source 51 outputs the excitation light L1. Therefore, it is possible to improve the time resolution and the detection accuracy for the phenomenon (for example, fluorescence L2) that repeatedly occurs in response to the excitation light L1 from the light source 51.

[0098] Note that, regarding the optical sensor 50 according to the first embodiment, similar to the optical sensor according to the second embodiment described later, the ON periods of the discharge gates 6a and 6b can be controlled. That is, referring to FIG. 7(a) as an example, the timing generator 53 is within the time range C5 (the seventh time range) between the time range C1 (the fifth time range) which is the ON period of the charge transfer gate 4a and the time range C2 (the sixth time range) which is the ON period of the charge transfer gate 4b and is separated from the time range C1, generates a charge transfer signal VTX5 = Drain so that the discharge gates 6a and 6b are in the ON state. If the fifth time range is regarded as the first time range described above and the sixth time range is regarded as the third time range described above, the seventh time range can be regarded as the time range between these first time range and the third time range. The same applies to the modification according to the first embodiment described below. According to this, as a result, the remaining charge generated in the light receiving unit 2 can be discharged, and thus the detection accuracy can be further improved. [Modification according to the first embodiment]

[0099] The above first embodiment has described one form of the present disclosure. Therefore, the present disclosure is not limited to the above form and can be arbitrarily modified.

[0100] FIG. 9 is a diagram showing a timing chart according to a modification of the first embodiment. As shown in FIG. 9, in this example, when the start time B1a of period B1 and the start time B2a of period B2 are made to coincide, the time range C1 and the time range D2 are made to overlap only partially. That is, this example can be rephrased as follows when the charge transfer gate 4a is the first charge transfer gate and the charge transfer gate 4b is the second charge transfer gate.

[0101] That is, in this example, the timing generator 53 turns on one of the first charge transfer gate and the second charge transfer gate in a first time range (here, the time range C1) which is one of a pair of overlapping time ranges, and turns on the other of the first charge transfer gate and the second charge transfer gate in a second time range which is the other of the pair of overlapping time ranges, so as to generate the charge transfer signals VTX1 and VTX2. Thus, in the optical sensor 50 including a plurality of charge transfer gates 4a to 4d, the ON periods of at least different charge transfer gates may be overlapped between the nth frame and the mth frame.

[0102] In the above embodiment, the ON periods (time ranges C3 and D3) of the charge transfer gate 4c with each other and the ON periods (time ranges C4 and D4) of the charge transfer gate 4d with each other also overlapped with each other over a plurality of frames. However, in the example of FIG. 9, the ON periods of the charge transfer gate 4c with each other and the ON periods of the charge transfer gate 4d with each other do not overlap with each other. Thus, in the optical sensor 50, it is sufficient that at least a pair of ON periods of at least the charge transfer gates 4a to 4d overlap between at least a pair of frames.

[0103] For example, in the first embodiment described above, the case where the timing generator 53 generates a charge transfer signal such that the ON periods of specific charge transfer gates overlap between two consecutive frames (i.e., when m = n ± 1) was explained. However, the mode of generating the charge transfer signal is not limited to this. The timing generator 53 may generate a charge transfer signal such that the ON periods of specific charge transfer gates overlap between a pair of frames separated from each other with another frame interposed therebetween.

[0104] As an example of this case, if n = 2, m = 4, the first time range is the time range D3, and the second time range is the time range F3, then when the timing generator 53 makes the start time B2a of the period (the first period) B2 belonging to frame A2 coincide with the start time B4a of the period (the second period) B4 belonging to frame A4, the charge transfer signal VTX3 is generated such that the time range (the first time range) D3 within period B2 and the time range (the second time range) F3 within period B4 only partially overlap. In this case, between frame A2 and frame A4, the ON period of the charge transfer gate 4c will partially overlap.

[0105] In this way, in the optical sensor 50, among a plurality of frames, it is sufficient if the ON periods of at least one charge transfer gate partially overlap at least once between at least two frames. Furthermore, the ON periods of a specific charge transfer gate may be made to partially overlap between three or more frames.

[0106] Also, in the first embodiment above, an example of using the optical detection device 100 for fluorescence lifetime measurement was given, but it can also be applied to other phenomena. When applying it to a phenomenon that does not require irradiation with the excitation light L1, the periods B1 to B4 do not have to be synchronized with the timing at which the light source 51 outputs the excitation light L1.

[0107] In the first embodiment described above, the case where the optical sensor 50 includes four charge transfer gates 4a to 4c for each of the pixel portions RS has been described. However, the optical sensor 50 may include at least one charge transfer gate for each of the pixel portions RS (for example, it may include eight charge transfer gates).

[0108] Further, the frames A1 to A4 are not limited to being defined as the period between a pair of reset processes, and can be arbitrarily set. For example, the frames A1 to A4 may be set based on the reading of signals from the charge storage portions (the third semiconductor regions 9a to 9d), or when the optical sensor 50 is a motion sensor, one image may be set as one frame. Furthermore, the optical sensor 50 and the driving method of the optical sensor 50 according to the first embodiment may be used for detecting non-repeating phenomena other than repeating phenomena. [Second Embodiment]

[0109] Subsequently, the second embodiment will be described. FIG. 10 is a plan view showing a part (pixel portion of the optical sensor) of the optical detection device according to the second embodiment. The overall configuration of the optical detection device according to the second embodiment is the same as that of the optical detection device 100 according to the first embodiment. The optical detection device according to the second embodiment is different from the first embodiment in that its optical sensor 50 includes two charge transfer gates 4a and 4b for each of the pixel portions RS, the charge transfer signals generated by the timing generator 53, and the driving method. In FIG. 10, transfer electrodes TX1 and TX2 corresponding to the two charge transfer gates 4a and 4b are shown.

[0110] FIGS. 11 and 12 are timing charts according to the second embodiment. FIG. 11(a) shows the first frame G1, FIG. 11(b) shows the second frame G2, FIG. 11(a) shows the third frame G3, and FIG. 12(b) shows the fourth frame G4. The frames G1 to G4 are temporally continuous in this order. Each of the frames G1 to G4 is defined as the period between a pair of reset processes as an example.

[0111] Frame G1 includes a plurality of periods H1. Period H1 is defined as the period during the emission of the excitation light L1 (in the case of fluorescence lifetime measurement) in frame G1. That is, the start time H1a of period H1 is the emission time of one excitation light L1 in frame G1, and the end time H1b of period H1 is the emission time of the next excitation light L1 of the one excitation light L1 in frame G1. Frame G2 includes a plurality of periods H2. Period H2 is defined as the period during the emission of the excitation light L1 in frame G2. That is, the start time H2a of period H2 is the emission time of one excitation light L1 in frame G2, and the end time H2b of period H2 is the emission time of the next excitation light L1 of the one excitation light L1 in frame G2.

[0112] Also, frame G3 includes a plurality of periods H3. Period H3 is defined as the period during the emission of the excitation light L1 in frame G3. That is, the start time H3a of period H3 is the emission time of one excitation light L1 in frame G3, and the end time H3b of period H3 is the emission time of the next excitation light L1 of the one excitation light L1 in frame G3. Furthermore, frame G4 includes a plurality of periods H4. Period H4 is defined as the period during the emission of the excitation light L1 in frame G4. That is, the start time H4a of period H4 is the emission time of one excitation light L1 in frame G4, and the end time H4b of period H4 is the emission time of the next excitation light L1 of the one excitation light L1 in frame G4.

[0113] Here, periods H1 to H4 have the same length as each other, and the time differences from the respective start times of frames G1 to G4 are also the same. Therefore, when the respective start times H1a to H4a of periods H1 to H4 are made to coincide, the respective end times H1b to H4b also coincide (that is, they all overlap).

[0114] In the period H1 belonging to the frame G1, first, in the time range J1, a charge transfer signal VTX1 is applied to the charge transfer gate 4a via the transfer electrode TX1 so that the charge transfer gate 4a becomes in a charge transfer state (ON state). Subsequently, in the period H1, in the time range J2, a charge transfer signal VTX2 is applied to the charge transfer gate 4b via the transfer electrode TX2 so that the charge transfer gate 4b becomes in the ON state. On the other hand, in the period H1, in the time range J3 between the time range J1 and the time range J2, a charge transfer signal VTX5 = Drain is applied to the discharge gates 6a, 6b via the transfer electrode TX5 so that the discharge gates 6a, 6b become in the ON state. The frame G1 includes a plurality (here, continuously) of such periods H1.

[0115] Here, as an example, the end time of the time range J1 and the start time of the time range J3 coincide, and the end time of the time range J3 and the start time of the time range J2 coincide. That is, here, in all time ranges between the time range J1 in which the charge transfer gate 4a is in the ON state and the time range J2 in which the charge transfer gate 4b is in the ON state, the discharge gates 6a, 6b are made in the ON state.

[0116] Subsequently, in the period H2 belonging to the frame G2, first, in the time range K1, a charge transfer signal VTX1 is applied to the charge transfer gate 4a via the transfer electrode TX1 so that the charge transfer gate 4a becomes in the ON state. Subsequently, in the period H2, in the time range k2, a charge transfer signal VTX2 is applied to the charge transfer gate 4b via the transfer electrode TX2 so that the charge transfer gate 4b becomes in the ON state. On the other hand, in the period H2, in the time range K3 between the time range K1 and the time range K2, a charge transfer signal VTX5 = Drain is applied to the discharge gates 6a, 6b via the transfer electrode TX5 so that the discharge gates 6a, 6b become in the ON state. The frame G2 includes a plurality (here, continuously) of such periods H2.

[0117] Here, as an example, the end time of time range K1 coincides with the start time of time range K3, and the end time of time range K3 coincides with the start time of time range K2. That is, here, the discharge gates 6a and 6b are set to the ON state in all time ranges between the time range K1 in which the charge transfer gate 4a is in the ON state and the time range K2 in which the charge transfer gate 4b is in the ON state.

[0118] Subsequently, in period H3 belonging to frame G3, first, in time range M1, a charge transfer signal VTX1 is applied to the charge transfer gate 4a via the transfer electrode TX1 so that the charge transfer gate 4a is in the ON state. Subsequently, in period H3, in time range M2, a charge transfer signal VTX2 is applied to the charge transfer gate 4b via the transfer electrode TX2 so that the charge transfer gate 4b is in the ON state. On the other hand, in period H3, in time range M3 between time range M1 and time range M2, a charge transfer signal VTX5 = Drain is applied to the discharge gates 6a and 6b via the transfer electrode TX5 so that the discharge gates 6a and 6b are in the ON state. Frame G3 includes a plurality (here, continuously) of such periods H3.

[0119] Here, as an example, the end time of time range M1 coincides with the start time of time range M3, and the end time of time range M3 coincides with the start time of time range M2. That is, here, the discharge gates 6a and 6b are set to the ON state in all time ranges between the time range M1 in which the charge transfer gate 4a is in the ON state and the time range M2 in which the charge transfer gate 4b is in the ON state.

[0120] Furthermore, in period H4 belonging to frame G4, first, in time range N1, a charge transfer signal VTX1 is applied to charge transfer gate 4a via transfer electrode TX1 so that charge transfer gate 4a is in the ON state. Subsequently, in period H4, in time range N2, a charge transfer signal VTX2 is applied to charge transfer gate 4b via transfer electrode TX2 so that charge transfer gate 4b is in the ON state. On the other hand, in period H4, in time range N3 between time range N1 and time range N2, a charge transfer signal VTX5 = Drain is applied to drain gates 6a, 6b via transfer electrode TX5 so that drain gates 6a, 6b are in the ON state. Frame G4 includes a plurality (here, continuously) of such periods H4. Note that each of time ranges J1, J2, time ranges K1, K2, time ranges M1, M2, and time ranges N1, N2 has the same length as each other.

[0121] Here, as an example, the end time of time range N1 and the start time of time range N3 coincide, and the end time of time range N3 and the start time of time range N2 coincide. That is, here, in all time ranges between time range N1 in which charge transfer gate 4a is in the ON state and time range N2 in which charge transfer gate 4b is in the ON state, drain gates 6a, 6b are in the ON state.

[0122] As described above, here, the timing generator 53 sets the first charge transfer gate in the charge transfer state in the first time range, sets the second charge transfer gate in the charge transfer state in the second time range separated from the first time range, and sets the drain gate in the charge discharge state in the third time range between the first time range and the second time range, and generates a charge transfer signal.

[0123] As an example, focusing on frame G1, the timing generator 53 turns on the charge transfer gate 4a (first charge transfer gate) in the time range J1 (first time range), turns on the charge transfer gate 4b (second charge transfer gate) in the time range J2 (second time range) separated from the time range J1, and turns on the discharge gates 6a and 6b in the time range J3 (third time range) between the time range J1 and the time range J2, to generate the charge transfer signals VTX1, VTX2, VTX5 = Drain. The same applies to the other frames G2 to G4.

[0124] Here, taking the time ranges J1, K1, M1, N1 when the charge transfer gate 4a is in the ON state as the first time range, the time ranges J2, K2, M2, N2 when the charge transfer gate 4b is in the ON state as the second time range, and the time ranges J3, K3, M3, N3 when the discharge gates 6a and 6b are in the ON state as the third time range, all of the frames G1 to G4 include the first time range, the second time range, and the third time range. Further, as an example, when the start times of frame G1 and frame G2 are made to coincide, the time range K2 is located between the time range J1 and the time range J2. The same applies to frame G2 and frame G3, and frame G3 and frame G4.

[0125] That is, here, the timing generator 53 generates the charge transfer signal such that each of the plurality of frames includes the first time range, the second time range, and the third time range, and when the start times of the nth (n is an integer of 1 or more) frame and the mth (m is an integer of 1 or more different from n) frame coincide, the first time range of the mth frame is located between the first time range and the second time range of the nth frame.

[0126] Further, the timing generator 53 generates a charge transfer signal such that, within one frame, when the start times of a plurality of periods are made to coincide over the plurality of periods, the first charge transfer gate and the second charge transfer gate are in a charge transfer state in a time range where they overlap. As an example, within frame G1, the timing generator 53 generates charge transfer signals VTX1 and VTX2 such that when the start time H1a of period H1 is made to coincide over a plurality of periods H1, charge transfer gates 4a and 4b are in an ON state in overlapping time ranges J1 and J2. Thereby, charge integration is performed in the charge accumulation unit. The same applies to other frames and periods.

[0127] As described above, in the photosensor 50 and the driving method of the photosensor 50 according to the second embodiment, the charge transfer signals VTX1 and VTX2 applied to the charge transfer gates 4a and 4b for transferring the charge generated in the light receiving unit 2 turn the charge transfer gate 4a on in the first time range (for example, time range J1), turn the charge transfer gate 4b on in a second time range (for example, time range J2) separated from the first time range, and turn the discharge gates 6a and 6b on in a third time range (for example, time range J3) between the first time range and the second time range. In this way, by separating the ON periods of the charge transfer gates 4a and 4b and providing a charge discharge period therebetween, it is possible to discharge the remaining unread charge generated in the light receiving unit 2. As a result, the detection accuracy can be improved.

[0128] Also, in the optical sensor 50 according to the second embodiment, the timing generator 53 is configured such that each of a plurality of frames includes a first time range, a second time range, and a third time range, and when the start times of the nth frame (e.g., frame G1) and the mth frame (e.g., frame G2) are made to coincide, the first time range (e.g., time range J1) of the nth frame and the first time range (e.g., time range K2) of the mth frame are positioned between the first time range (e.g., time range J2) and the second time range (e.g., time range J2) of the nth frame. For this reason, by arranging the ON periods of the charge transfer gates 4a and 4b more densely over a plurality of frames, the detection accuracy can be further improved.

[0129] Furthermore, in the optical sensor 50 according to the second embodiment, the timing generator 53 generates the charge transfer signals VTX1 and VTX2 such that the charge transfer gates 4a and 4b are in the ON state in overlapping time ranges when the start times of a plurality of periods (e.g., period H1) are made to coincide within one frame (e.g., frame G1). For this reason, it becomes possible to perform charge integration within one frame. [Modification Example According to the Second Embodiment]

[0130] The above second embodiment has described one form of the present disclosure. Therefore, the present disclosure is not limited to the above form and can be arbitrarily modified.

[0131] For example, in the second embodiment described above, the case where the optical sensor 50 includes two charge transfer gates 4a and 4b for each of the pixel portions RS has been described. However, the optical sensor 50 may include, for example, four charge transfer gates 4a to 4d for each of the pixel portions RS. In this case, for at least one pair (or all) of the four charge transfer gates 4a to 4d and the discharge gates 6a and 6b, the above relationship, that is, the timing generator 53 sets the first charge transfer gate to the charge transfer state in the first time range, sets the second charge transfer gate to the charge transfer state in the second time range separated from the first time range, and sets the discharge gate to the charge discharge state in the third time range between the first time range and the second time range, so that a charge transfer signal can be generated.

[0132] Also, in the second embodiment described above, an example has been given in which the discharge gates 6a and 6b are in the ON state in all time ranges between the first time range (for example, time range J1) in which the charge transfer gate 4a is in the ON state and the second time range (for example, time range J2) in which the charge transfer gate 4b is in the ON state. However, the timing generator 53 may generate charge transfer signals VTX1, VTX2, and VTX5 = Drain such that the discharge gates 6a and 6b are in the ON state in some time ranges between the first time range (for example, time range J1) in which the first charge transfer gate (for example, charge transfer gate 4a) is in the ON state and the second time range (for example, time range J2) in which the second charge transfer gate (for example, charge transfer gate 4b) is in the ON state. In this case, the discharge gates 6a and 6b can be in the ON state until immediately before the second charge transfer gate becomes in the ON state.

[0133] Also, in the second embodiment described above, the case where the timing generator 53 generates charge transfer signals VTX1, VTX2, and VTX5 = Drain over a plurality of frames G1 to G4 has been described. However, it may be only one frame.

[0134] Further, in the second embodiment, when applying to a phenomenon that does not require irradiation of the excitation light L1, the periods H1 to H4 do not have to be synchronized with the timing at which the light source 51 outputs the excitation light L1. In particular, the optical sensor 50 and the driving method of the optical sensor 50 according to the second embodiment can improve the detection accuracy by discharging the read residue of the light receiving unit 2 even for the detection of non-repeating phenomena other than the repeatedly occurring phenomena.

[0135] Furthermore, the frames G1 to G4 are not limited to being defined as the period between a pair of reset processes, and can be arbitrarily set. For example, the frames G1 to G4 may be set based on the readout of signals from the charge storage units (third semiconductor regions 9a to 9d), or when the optical sensor 50 is a motion sensor, one image may be set as one frame.

[0136] Note that, regarding all matters related to the operations and controls of the discharge gates 6a and 6b of the above-described second embodiment and the modification examples of the second embodiment, all or part of them can be arbitrarily selected and applied to the optical sensor 50 according to the first embodiment. [Modification Examples Common to the First Embodiment and the Second Embodiment]

[0137] In the optical sensor 50, within one frame, signals may be read out from the charge transfer gates 4a to 4d and accumulated in the charge storage units (third semiconductor regions 9a to 9d), or regardless of the presence or absence of the charge storage units, they may be read out to the subsequent circuit every time the charge transfer gates 4a to 4d are turned on.

[0138] Also, in the optical sensor 50, a photogate structure is exemplified as the light receiving unit 2. However, the light receiving unit 2 is not limited to the photogate structure and may have other structures. As an example, as shown in Fig. 13(a), the light receiving unit 2 may have an embedded PD structure. In this case, the light receiving unit 2 is composed of a p + -type semiconductor region 2B provided in the second semiconductor region 5 on the second main surface 1b side and an n-type semiconductor region 2A provided in the second semiconductor region 5 directly below the semiconductor region 2B.

[0139] Also in this case, in order to perform high-speed charge transfer, a potential gradient can be provided in the light-receiving portion 2. As an example of the configuration therefor, as shown in FIGS. 13(b) and 13(c), a plurality (here, three) of n-type semiconductor regions 21, 22, 23 in which the n-type semiconductor region 2A is arranged such that the impurity concentration increases as it approaches the charge transfer gate 4a, for example, can be included, and a configuration for creating an electric field gradient can be cited. Note that FIG. 13(b) is a schematic cross-sectional view, and FIG. 13(c) is a plan view.

[0140] Further, as a configuration for providing a potential gradient in the light-receiving portion 2, as shown in FIG. 14, the n-type semiconductor region 2A includes a pair of n-type semiconductor regions 25, 26 and an n-type semiconductor region 27 sandwiched between the semiconductor regions 25, 26 and having a width W that expands as it approaches the charge transfer gate 4a, for example. + This may also be a configuration for creating an electric field gradient. Note that FIG. 14 is a plan view from the second main surface 1b side.

[0141] Also, the above-described optical sensor 50 can be used, for example, for detecting a moving object. In this case, the optical sensor 50 can detect a moving object by taking the difference between the shutter signal of the n-th frame and another shutter signal of the same n-th frame (or the shutter signal of the (n + 1)-th frame) so that a change appears only in the moved pixel portion RS. Even in such a case, by controlling (driving method) the charge transfer gates 4a to 4d and the discharge gates 6a and 6b as described above, the detection accuracy can be improved. Further, the light generated by the light source 51 is not limited to pulsed light such as the excitation light L1 described above, and can be light of any waveform such as a sine wave or a sawtooth wave.

Industrial Applicability

[0142] An optical sensor capable of improving detection accuracy and a driving method for the optical sensor are provided.

Explanation of Signs

[0143] 2... light-receiving part, 4a~4d... charge transfer gates (first charge transfer gate, second charge transfer gate), 6a, 6b... discharge gates, 50... optical sensor, 53... timing generator (signal generation part), A1~A4, G1~G4... frames, B1~B4... periods (first period, second period), H1~H4... periods (first period, second period), C1~C4, D1~D4, E1~E4, F1~F4... time ranges (first time range, second time range), J1, J2, K1, K2, M1, M2, N1, N2... time ranges (first time range, second time range), J3, K3, M3, N3... time ranges (third time range).

Claims

1. A light sensor comprising: a light receiving portion that generates electric charges in response to incident light from an object excited by excitation light; a charge transfer gate for transferring the electric charges generated in the light receiving portion; a signal generation portion for generating a charge transfer signal to be applied to the charge transfer gate; a discharge gate for discharging the electric charges generated in the light receiving portion; wherein the signal generation portion generates the charge transfer signal such that the charge transfer gate is in a charge transfer state in a first time range of a first period belonging to the n-th (n is an integer of 1 or more) frame and the charge transfer gate is in a charge transfer state in a second time range of a second period belonging to the m-th (m is an integer of 1 or more different from n) frame; when the start time of the first period and the start time of the second period are made to coincide, a part of the first time range and a part of the second time range overlap each other; when the start time of the first period and the start time of the second period are made to coincide, a part of the time range in which the discharge gate is in a non-charge discharge state in the first time range and the second time range overlaps each other; the start time of the first period is the emission time of the excitation light in the n-th frame; the start time of the second period is the emission time of the excitation light in the m-th frame; the signal generation portion generates the charge transfer signal such that the charge transfer gate is in a charge transfer state in a time range that overlaps when the start times of the periods are made to coincide over a plurality of periods within one frame. A light sensor.

2. The n-th frame and the m-th frame are consecutive frames to each other. The light sensor according to Claim 1.

3. The charge transfer gate includes a first charge transfer gate and a second charge transfer gate; the signal generation portion generates the charge transfer signal such that, in the first time range, one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state and, in the second time range, the one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state. The light sensor according to Claim 1 or 2.

4. The charge transfer gate includes a first charge transfer gate and a second charge transfer gate; The signal generation unit generates the charge transfer signal such that, in the first time range, one of the first charge transfer gate and the second charge transfer gate is in a charge transfer state, and in the second time range, the other of the first charge transfer gate and the second charge transfer gate is in a charge transfer state. The optical sensor according to claim 1 or 2.

5. The charge transfer gate includes a first charge transfer gate and a second charge transfer gate. The signal generation unit generates the charge transfer signal such that, in the first time range, the first charge transfer gate is in a charge transfer state, in the second time range, the first charge transfer gate is in a charge transfer state, and in a third time range of the first period, the second charge transfer gate is in a charge transfer state, and in a fourth time range of the second period, the second charge transfer gate is in a charge transfer state. When the start time of the first period coincides with the start time of the second period, a part of the third time range and a part of the fourth time range overlap with each other. The optical sensor according to any one of claims 1 to 3.

6. The signal generation unit generates the charge transfer signal such that, in a fifth time range, the charge transfer gate is in a charge transfer state, in a sixth time range separated from the fifth time range, the charge transfer gate is in a charge transfer state, and in a seventh time range between the fifth time range and the sixth time range, the discharge gate is in a charge discharge state. The optical sensor according to any one of claims 1 to 5.

7. The signal generation unit further generates a signal for the light source to output light periodically. The start times of the first period and the second period are synchronized with the timing at which the light source outputs the light. The optical sensor according to any one of claims 1 to 6.

8. A method for driving an optical sensor, comprising: a light receiving unit that generates charges in response to incident light from an object excited by excitation light; a charge transfer gate for transferring the charges generated by the light receiving unit; and a discharge gate for discharging the charges generated by the light receiving unit. Generate a charge transfer signal to be applied to the charge transfer gate such that the charge transfer gate is in a charge transfer state during a first time range of a first period belonging to the n-th (n is an integer of 1 or more) frame and the charge transfer gate is in a charge transfer state during a second time range of a second period belonging to the m-th (m is an integer of 1 or more different from n) frame. When the start time of the first period is made to coincide with the start time of the second period, a part of the first time range and a part of the second time range overlap each other. When the start time of the first period is made to coincide with the start time of the second period, a part of the time range in which the discharge gate is in a non-charge discharge state in the first time range and the second time range overlaps each other. The start time of the first period is the emission time of the excitation light in the n-th frame. The start time of the second period is the emission time of the excitation light in the m-th frame. Generate the charge transfer signal such that the charge transfer gate is in a charge transfer state in a time range that overlaps when the start times of the periods are made to coincide over a plurality of periods within one frame. A method for driving an optical sensor.

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