Memory device and electronic device

Abstract

Provided is a storage device having high storage capacity and low power consumption. The storage device comprises a first layer and a second layer which includes the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit comprises a bit-line driver circuit and / or word-line driver circuit for transmitting a signal to the first memory cell. The first memory cell comprises a first transistor, a second transistor, a conductor, and a MTJ element. The MTJ element comprises a free layer. The free layer is electrically connected to the conductor, and a first terminal of the first transistor is electrically connected to a first terminal of the second transistor via the conductor. The free layer is positioned above the conductor. The circuit has a transistor in which silicon is included in a channel formation region, and a metal oxide is included in respective channel formation regions of the first transistor and the second transistor.

Description

Technical Field

[0001] One aspect of the present invention relates to a memory device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification or the like relates to an object, an operation method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a sensor, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

Background Art

[0003] In recent years, with the increase in the amount of data to be handled, a memory device having a larger storage capacity has been demanded. In order to increase the storage capacity per unit area, it is effective to form memory cells by stacking them, such as a 3D NAND type memory device (see Patent Document 1, Patent Document 2, and Patent Document 3). By stacking and providing memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] As a storage device applicable to a cache memory, main memory, etc. of a computer, it is required that the access time be short, in other words, for example, the write speed and read speed be fast. For example, the access time (sometimes called delay time, latency, etc.) of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) is approximately several ns to several tens of ns, so it is used as a cache memory, main memory, etc. of a computer. However, since SRAM, DRAM, etc. are volatile memories, the power consumption may increase while holding data. Therefore, as a storage device used for a cache memory, main memory of a computer, in addition to having a large storage capacity, it is required to have low power consumption.

[0006] One aspect of the present invention aims to provide a storage device with low power consumption. Or, one aspect of the present invention aims to provide a storage device with a large storage capacity.

[0007] Or, one aspect of the present invention aims to provide a novel storage device, etc. Or, one aspect of the present invention aims to provide an electronic device having the above storage device.

[0008] Note that the problems of one aspect of the present invention are not limited to the above-listed problems. The above-listed problems do not prevent the existence of other problems. Other problems are those not mentioned in this item as described below. Problems not mentioned in this item can be derived by those skilled in the art from the description in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the above-listed problems and other problems. Note that one aspect of the present invention does not necessarily need to solve all of the above-listed problems and other problems.

Means for Solving the Problems

[0009] (1) One aspect of the present invention is a memory device having a first layer and a second layer overlapping the first layer. The first layer has a circuit, and the second layer has a first memory cell. The circuit has a bit line driver circuit and / or a word line driver circuit that transmits a signal to the first memory cell. The first memory cell has a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer. The free layer is electrically connected to the conductor, and the first terminal of the first transistor is electrically connected to the first terminal of the second transistor via the conductor. The circuit has a transistor in which silicon is included in a channel formation region, and each of the first transistor and the second transistor includes a metal oxide in the channel formation region.

[0010] (2) Alternatively, one aspect of the present invention is a memory device having a first layer and a second layer overlapping the first layer and different from the configuration of (1) above. The first layer has a circuit, and the second layer has a first memory cell. The circuit has a bit line driver circuit and / or a word line driver circuit that transmits a signal to the first memory cell. The first memory cell has a first transistor, a second transistor, a conductor, and an MTJ element, and the MTJ element has a free layer and a fixed layer. The free layer is electrically connected to the conductor, the first terminal of the first transistor is electrically connected to the first terminal of the second transistor, the second terminal of the second transistor is electrically connected to the conductor, and the second terminal of the first transistor is electrically connected to the fixed layer. Also, the fixed layer is located above the free layer. The circuit has a transistor in which silicon is included in a channel formation region, and each of the first transistor and the second transistor includes a metal oxide in the channel formation region.

[0011] (3) Alternatively, in one aspect of the present invention in (1) or (2) above, the conductor preferably has a metal material in which a spin hall effect occurs when an electric current flows.

[0012] (4) Alternatively, in one aspect of the present invention, in any one of (1) to (3) above, it may be configured to have a third layer. Note that the third layer has a second memory cell, and the third layer is preferably laminated on the second layer.

[0013] (5) Alternatively, one aspect of the present invention is an electronic device having any one of the storage devices of (1) to (4) above and a housing.

[0014] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, etc. are semiconductor devices themselves and may have a semiconductor device.

[0015] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. It is assumed that X and Y are objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0016] As an example of the case where X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. Note that a switch has a function of controlling on / off. That is, a switch has a function of becoming a conducting state (on state) or a non-conducting state (off state) and controlling whether to allow current to flow or not.

[0017] As an example of the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (for example, logic circuits (such as inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (such as digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (such as power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0018] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, when they are connected without another element or another circuit interposed between X and Y).

[0019] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By using an expression method similar to these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0020] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component. Therefore, the electrically connected in this specification includes such a case where one conductive film has the functions of multiple components within its scope.

[0021] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistive element" can be rephrased as terms such as "resistance", "load", "region having a resistance value", etc., and conversely, terms such as "resistance", "load", "region having a resistance value" can be rephrased as terms such as "resistive element". The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it can be 1 Ω or more and 1×10 9 Ω or less.

[0022] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, parasitic capacitance, gate capacitance of a transistor, and the like. Therefore, in this specification and the like, terms such as "capacitive element", "parasitic capacitance", "gate capacitance", etc. can be rephrased as terms such as "capacitance", etc., and conversely, the term "capacitance" can be rephrased as terms such as "capacitive element", "parasitic capacitance", "gate capacitance", etc. Also, the term "pair of electrodes" of "capacitance" can be rephrased as "pair of conductors", "pair of conductive regions", "pair of regions", etc. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it can be 1 pF or more and 10 μF or less.

[0023] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conduction type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are assumed to be interchangeable with each other. Also, in this specification and the like, when explaining the connection relationship of the transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0024] Also, on a circuit diagram, even if a single circuit element is illustrated, the circuit element may have a plurality of circuit elements. For example, when one resistor is described on the circuit diagram, it shall include the case where two or more resistors are electrically connected in series. Also, for example, when one capacitor is described on the circuit diagram, it shall include the case where two or more capacitors are electrically connected in parallel. Also, for example, when one transistor is described on the circuit diagram, it shall include the case where two or more transistors are electrically connected in series and the gates of the respective transistors are electrically connected to each other. Also, similarly, for example, when one switch is described on the circuit diagram, it shall include the case where the switch has two or more transistors, two or more transistors are electrically connected in series, and the gates of the respective transistors are electrically connected to each other.

[0025] Also, in this specification and the like, a node can be equivalently referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. according to the circuit configuration, device structure, etc. Also, it is possible to equivalently refer to a terminal, wiring, etc. as a node.

[0026] Also, in this specification and the like, "voltage" and "electric potential" can be equivalently replaced as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be replaced with "electric potential". Note that the ground potential does not necessarily mean 0V. Also, the electric potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, etc., and the potential output from the circuit, etc. also change.

[0027] In addition, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, in the case where both of two wirings are described as "functioning as a wiring for supplying a high-level potential", the respective high-level potentials provided by the two wirings do not have to be equal to each other. Similarly, in the case where both of two wirings are described as "functioning as a wiring for supplying a low-level potential", the respective low-level potentials provided by the two wirings do not have to be equal to each other.

[0028] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "current" refers to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in a wiring or the like is defined as the direction in which the carrier becomes a positive charge, and is described with a positive current amount. In other words, the direction in which the carrier becomes a negative charge is the direction opposite to the direction of the current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0029] In addition, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, a component referred to as "first" may be a component referred to as "second" in other embodiments or in the claims. Also, for example, a component referred to as "first" in one of the embodiments of this specification and the like may be omitted in other embodiments or in the claims.

[0030] In addition, in this specification and the like, phrases indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the phrases described in the specification and the like and can be appropriately rephrased according to the situation. For example, in the expression "an insulator located on the upper surface of a conductor", by rotating the orientation of the shown drawing by 180 degrees, it can be rephrased as "an insulator located on the lower surface of a conductor".

[0031] Also, terms such as "above" and "below" do not limit that the positional relationship of components is directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary that electrode B is directly formed in contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0032] Also, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or depending on the situation, it is possible to interchange with another term without using terms such as "film" and "layer". For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0033] Also, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and / or "wiring" also include cases where a plurality of "electrodes" and / or "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" and / or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and also, for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced with terms such as "region" in some cases.

[0034] Also, in this specification and the like, terms such as "wiring", "signal line", and "power supply line" can be interchanged with each other in some cases or according to the situation. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power supply line". Conversely, in the same way, terms such as "signal line" and "power supply line" may be changed to the term "wiring". Terms such as "power supply line" may be changed to terms such as "signal line". Conversely, in the same way, terms such as "signal line" may be changed to terms such as "power supply line". Also, the term "potential" applied to the wiring may be changed to terms such as "signal" in some cases or according to the situation. Conversely, in the same way, terms such as "signal" may be changed to the term "potential".

[0035] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, there are hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of the impurities that change the characteristics of the semiconductor include Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, Group 15 elements, oxygen, etc.

[0036] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether current flows or not. Or, a switch refers to a device that has a function of selecting and switching a current flow path. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific type.

[0037] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating a transistor merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0038] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0039] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0040] According to one aspect of the present invention, a memory device with low power consumption can be provided. Or, according to one aspect of the present invention, a memory device with a large storage capacity can be provided.

[0041] Or, according to one aspect of the present invention, a novel memory device or the like can be provided. Or, according to one aspect of the present invention, an electronic device having the above memory device can be provided.

[0042] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of the Drawings

[0043] FIG. 1A and FIG. 1B are block diagrams showing a configuration example of a memory device. FIG. 2 is a block diagram showing a configuration example of a memory device. FIGS. 3A to 3D are circuit diagrams showing a configuration example of a memory cell. FIG. 4 is a schematic diagram for explaining a configuration example of a memory element included in a memory cell. FIGS. 5A and 5B are block diagrams showing a configuration example of a storage device. FIGS. 6A to 6C are circuit diagrams showing a configuration example of a memory cell. FIG. 7 is a cross-sectional schematic diagram showing a configuration example of a storage device. FIGS. 8A to 8C are cross-sectional schematic diagrams showing a configuration example of a transistor. FIG. 9 is a cross-sectional schematic diagram showing a configuration example of a storage device. FIG. 10 is a cross-sectional schematic diagram showing a configuration example of a storage device. FIG. 11A is a diagram for explaining the classification of the crystal structure of IGZO, FIG. 11B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 11C is a diagram for explaining the electron backscatter diffraction pattern of crystalline IGZO. FIG. 12A is a perspective view showing an example of a semiconductor wafer, FIG. 12B is a perspective view showing an example of a chip, and FIGS. 12C and 12D are perspective views showing an example of an electronic component. FIG. 13 is a block diagram for explaining a CPU. FIGS. 14A to 14J are perspective views or schematic diagrams for explaining an example of a product. FIGS. 15A to 15E are perspective views or schematic diagrams for explaining an example of a product.

DETAILED DESCRIPTION OF THE INVENTION

[0044] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Further, when described as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0045] In this specification and the like, a metal oxide having nitrogen may also be generically referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0046] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0047] Note that the content described in one embodiment (even part of the content) can be applied to, combined with, or replaced with at least one of the content described in another content (even part of the content) described in the same embodiment and the content (even part of the content) described in one or more other embodiments.

[0048] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0049] Note that the figure (which may be a part) described in a certain embodiment can be combined with at least one of another part of that figure, another figure (which may be a part) described in that embodiment, and a figure (which may be a part) described in one or more other embodiments to form even more figures.

[0050] The embodiments described in this specification will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and the forms and details can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and the repeated description may be omitted. Also, in perspective views and the like, for the sake of clarity of the drawings, the description of some components may be omitted.

[0051] In this specification and the like, when the same reference numerals are used for a plurality of elements, particularly when it is necessary to distinguish them, identification symbols such as “_1”, “[n]”, “[m,n]” may be appended to the reference numerals for description.

[0052] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0053] (Embodiment 1) In this embodiment, a memory device according to one aspect of the present invention will be described.

[0054] <Configuration example of the memory device> Figure 2 shows the configuration of a memory device according to an aspect of the present invention. The memory device MDV has a peripheral circuit PHL and a memory cell array MCA. The peripheral circuit PHL has a row decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.

[0055] The bit line driver circuit 2630 has a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634. The precharge circuit 2632 has a function of precharging a wiring (not shown in FIG. 2) electrically connected to a memory cell MC described later to a predetermined potential. The sense amplifier 2633 has a function of acquiring a potential (or current) read from the memory cell MC as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the memory device MDV as a digital data signal RDATA via the output circuit 2640.

[0056] Also, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit PHL, and a power supply voltage (VIL) for the memory cell array MCA are supplied to the memory device MDV from the outside.

[0057] Also, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the memory device MDV from the outside. The address signal ADDR is input to the row decoder 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit 2634.

[0058] The control logic circuit 2660 processes input signals (CE, WE, RE) from the outside and generates control signals for the row decoder 2621 and the column decoder 2631. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 2660 are not limited to these, and other control signals may be input as necessary.

[0059] In addition, each of the above circuits or each signal can be appropriately selected or discarded as necessary.

[0060] Note that the configuration example of this embodiment is not limited to the configuration of FIG. 2. For example, the configuration may be appropriately changed such that all or part of the peripheral circuit PHL is provided below the memory cell array MCA.

[0061] Specifically, for example, as shown in FIG. 1A, the storage device MDV may have a configuration in which the peripheral circuit PHL is provided below and the memory cell array MCA is provided above the peripheral circuit PHL.

[0062] In the storage device MDV of FIG. 1A, the memory cell array MCA has, as an example, m×n memory cells MC. Also, in the memory cell array MCA, the memory cells MC are arranged in an m-row and n-column matrix. Note that in FIG. 1A, among the plurality of memory cells MC, the memory cells MC[1,1], MC[m,1], MC[1,n], and MC[m,n] are extracted and shown.

[0063] Also, in the storage device MDV of FIG. 1A, the peripheral circuit PHL includes a circuit WD, a circuit BD, a circuit SD, a circuit CLC, and a circuit OPC. Note that the peripheral circuit PHL does not have to have all of the circuit WD, the circuit BD, the circuit SD, the circuit CLC, and the circuit OPC, and may have a configuration having one or more circuits selected from the circuit WD, the circuit BD, the circuit SD, the circuit CLC, and the circuit OPC.

[0064] The circuit WD can be, as an example, a circuit corresponding to the word line driver circuit 2622 in FIG. 2. Also, the circuit WD is, as an example, electrically connected to the wirings WL[1] to WL[m]. The circuit WD functions to transmit a selection signal to a plurality of memory cells MC included in the memory cell array MCA via the wirings WL[1] to WL[m].

[0065] Note that in FIG. 1A, an example is shown in which the wirings WL[1] to WL[m] are provided one by one for each row of the memory cell array MCA. However, a plurality of wirings may be provided for one row of the memory cell array MCA.

[0066] As an example, the circuit BD can be a circuit corresponding to the bit line driver circuit 2630 in FIG. 2. Further, as an example, the circuit BD is electrically connected to the wirings BL[1] to BL[n]. The circuit BD functions as a circuit for transmitting a write signal to the memory cells MC included in the memory cell array MCA via the wirings BL[1] to BL[n]. Further, the circuit BD functions as a circuit for applying a predetermined voltage or current to the memory cells MC included in the memory cell array MCA at the time of reading via the wirings BL[1] to BL[n].

[0067] Note that in FIG. 1A, an example is shown in which the wirings BL[1] to BL[n] are provided one by one for each column of the memory cell array MCA. However, a plurality of wirings may be provided for one column of the memory cell array MCA. For example, for one column of the memory cell array MCA, a wiring for transmitting a write signal and a wiring for transmitting a read signal may be provided.

[0068] As an example, the circuit SD can be a voltage generation circuit for applying a predetermined voltage to a plurality of memory cells MC of the memory cell array MCA. Further, as an example, the circuit SD is electrically connected to the wirings SL[1] to SL[m]. Note that the storage device MDV may be configured to directly input the power supply voltage (VIL) for the memory cell array MCA shown in FIG. 2 without providing the circuit SD in FIG. 1A.

[0069] Note that in FIG. 1A, an example is shown in which the wirings SL[1] to SL[m] are provided one by one for each column of the memory cell array MCA. However, a plurality of wirings may be provided for one column of the memory cell array MCA.

[0070] The circuit CLC can be, for example, a circuit corresponding to the control logic circuit 2660 in FIG. 2.

[0071] The circuit OPC can be, for example, a circuit corresponding to the output circuit 2640 in FIG. 2.

[0072] In the configuration example of the storage device MDV in FIG. 1A, the peripheral circuit PHL can be formed, for example, on a semiconductor substrate. That is, the circuit WD, the circuit BD, the circuit SD, the circuit OPC, and the circuit CLC can be formed on the semiconductor substrate. Further, as the semiconductor substrate, for example, a substrate made of silicon can be used, and a transistor (hereinafter referred to as an Si transistor) including silicon in a channel formation region can be formed on the substrate. Therefore, an Si transistor can be applied as the transistor included in the peripheral circuit PHL.

[0073] Alternatively, the semiconductor substrate may be, for example, a substrate made of germanium. Further, the peripheral circuit PHL may be formed on a compound semiconductor substrate, and examples of the compound semiconductor substrate include substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and the like. Further, the peripheral circuit PHL may be formed on a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate.

[0074] Also, the peripheral circuit PHL can be formed, for example, on an insulator substrate. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate, and the like. Further, the peripheral circuit PHL can be formed, for example, on a conductor substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, and the like. However, since the insulator substrate and the conductor substrate are different from the semiconductor substrate in that a channel formation region cannot be formed in the substrate itself, a transistor cannot be directly formed on the insulator substrate and the conductor substrate. Therefore, in order to form a transistor on the insulator substrate or the conductor substrate, it is necessary to separately provide a semiconductor film above the insulator substrate or the conductor substrate.

[0075] In the configuration example of the memory device MDV in FIG. 1A, as a method of providing the memory cell array MCA above the peripheral circuit PHL, for example, a method of forming by a semiconductor process can be mentioned. In particular, since the OS transistor can be formed by a semiconductor process, by applying the OS transistor as the transistor included in the memory cell array MCA, the memory cell array MCA can be provided above the semiconductor substrate and the peripheral circuit PHL.

[0076] Also, in FIG. 1A, a configuration in which one memory cell array MCA is provided above the peripheral circuit PHL is shown, but the memory device according to an aspect of the present invention is not limited thereto. For example, in the memory device according to an aspect of the present invention, a plurality of stacked memory cell arrays MCA may be provided above the peripheral circuit PHL. FIG. 1B shows a configuration of a memory device in which memory cell arrays MCA[1] to MCA[p] (where p is an integer of 2 or more) are stacked above the peripheral circuit PHL.

[0077] <<Configuration Example 1 of Memory Cell>> FIG. 3A shows an example of a memory cell that can be provided in the memory device MDV. Note that the memory cell MC shown in FIG. 3A can be an example of a three-terminal memory element, Spin Orbit Torque-Magnetoresistive Random Access Memory (SOT-MRAM).

[0078] The memory cell MC has, for example, a transistor M1, a transistor M2, and a resistive change device MD.

[0079] As the transistor M1 and the transistor M2, for example, an OS transistor can be applied. The channel formation region of the OS transistor is preferably an oxide containing at least one of indium, gallium, and zinc. Further, instead of the oxide, an oxide containing at least one of indium, element M (element M includes, for example, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.), and zinc may be used. The OS transistor is more preferably the structure of the transistor described in Embodiment 2 in particular.

[0080] Also, although the transistor M1 and the transistor M2 illustrated in FIG. 3A have a back gate, the memory device according to one aspect of the present invention is not limited thereto. For example, the transistor M1 and the transistor M2 illustrated in FIG. 3A may be configured without a back gate, that is, as a transistor having a single gate structure. Further, some transistors may have a configuration with a back gate, and another part of the transistors may have a configuration without a back gate.

[0081] Also, the sizes of the transistor M1 and the transistor M2 (for example, channel length, channel width, transistor configuration, etc.) are preferably equal to each other. By making the transistor sizes equal to each other, the electrical characteristics of each transistor can be made substantially equal. Therefore, by making the sizes of the transistor M1 and the transistor M2 equal, each of the transistor M1 and the transistor M2 can perform substantially the same operation when they are under the same conditions. The same conditions here refer to, for example, the input potentials to the sources, drains, gates, etc. of the transistor M1 and the transistor M2 respectively.

[0082] Note that each of the transistor M1 and the transistor M2 includes the case of operating as a switching element unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of each of the transistors described above include the case where they are within the voltage range for operating as a switching element. Also, each of the transistor M1 and the transistor M2 may operate in the linear region or the saturation region when in the on state.

[0083] Note that the modification examples regarding the structure, operation, etc. of the above transistors are not limited to only the transistor M1 and the transistor M2. For example, the structure, operation, etc. of the transistors described in other parts of the specification or illustrated in other drawings may be modified in the same way.

[0084] The resistance change device MD has an MTJ (magnetic tunnel junction) element ME. The resistance change device MD also has a terminal IT1, a terminal IT2, and a terminal OT. The details of the resistance change device MD will be described later.

[0085] The first terminal of transistor M1 is electrically connected to terminal IT1 of the resistance change device MD, the second terminal of transistor M1 is electrically connected to wiring BL1, and the gate of transistor M1 is electrically connected to wiring WL. The first terminal of transistor M2 is electrically connected to terminal IT2 of the resistance change device MD, the second terminal of transistor M2 is electrically connected to wiring BL2, and the gate of transistor M2 is electrically connected to wiring WL. The terminal OT of the resistance change device MD is electrically connected to wiring RBL.

[0086] Wiring BL1 and wiring BL2 function, as an example, as write bit lines for memory cell MC or as wiring for supplying a constant voltage.

[0087] Wiring WL functions, as an example, as a word line for memory cell MC.

[0088] Wiring RBL functions, as an example, as a read bit line for memory cell MC.

[0089] In FIG. 3A, a back gate is shown for transistor M1 and / or transistor M2, and although the connection configuration of the back gate is not shown, the electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. That is, for example, the gate and the back gate of transistor M1 may be electrically connected, or the gate and the back gate of transistor M2 may be electrically connected. Also, for example, in a transistor having a back gate, in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit or the like may be provided, and a configuration may be adopted in which a potential is applied to the back gate of the transistor by the external circuit or the like. Specifically, the memory cell MC can be configured as shown in FIG. 3B. The memory cell MC in FIG. 3B has a configuration in which a wiring BGE is electrically connected to the respective back gates of the transistors M1 and M2 included in the memory cell MC in FIG. 3A. By applying a predetermined potential to the wiring BGE, the threshold voltages of the transistors M1 and M2 can be varied.

[0090] Next, the resistive change device MD will be described.

[0091] FIG. 4 is a block diagram showing an example of the resistive change device MD. The resistive change device MD in FIG. 4 includes a layer RL, a layer TIS, a layer FL, and a layer CA. Note that the layer RL, the layer TIS, and the layer FL are included in the MTJ element ME.

[0092] The layer CA has, for example, a film having conductivity. Also, the terminal IT1 and the terminal IT2 are electrically connected through the film. Therefore, by applying a voltage between the terminal IT1 and the terminal IT2, a current flows between the terminal IT1 and the terminal IT2. Also, the layer CA may be called a channel layer.

[0093] Further, the film is made of a material in which the spin Hall effect occurs when an electric current flows between terminals IT1 and IT2. The spin Hall effect is a phenomenon in which a spin current is generated in a direction substantially perpendicular to the direction of the electric current flow. Specifically, for example, when an electric current flows in a two-dimensional plane such as a thin film, electrons with different spin directions are polarized on the upper and lower surfaces of the thin film, respectively, and thereby a spin current is generated in a direction substantially perpendicular to the thin film. Therefore, when an electric current flows between terminals IT1 and IT2, layer CA can generate a spin current in a direction substantially perpendicular to layer CA.

[0094] Layer CA preferably has a metal material in which the spin Hall effect occurs. Specifically, as the metal material, it is preferable to use a transition metal with strong spin-orbit interaction. Examples of the transition metal include tungsten, platinum, tantalum, etc. Further, layer CA may have a topological insulator that causes the spin Hall effect instead of a metal material, and in this case, an alloy of bismuth and antimony, an alloy of bismuth and selenium, etc. may be used.

[0095] Layer FL functions as a free layer in MTJ element ME. Layer FL has a ferromagnetic material, and the ferromagnetic material can take a state of magnetic moment parallel or antiparallel to the magnetization direction of layer RL described later.

[0096] As the ferromagnetic material contained in layer FL, for example, it is preferable that the magnetization of the ferromagnetic material is a material that is reversed by a small spin current. Further, as the ferromagnetic material contained in layer FL, it is preferable that the material is a material in which magnetization reversal hardly occurs due to thermal energy.

[0097] As the ferromagnetic material, for example, one selected from iron, cobalt, and nickel, or an alloy of two or more thereof can be used. For example, an alloy of cobalt, iron, and boron can be used. Further, an alloy of manganese and gallium, an alloy of manganese and germanium, etc. can be mentioned.

[0098] The magnetic moment of layer FL is subject to spin torque by the spin current generated in layer CA. For example, the magnetic moment of layer FL reverses its direction when the spin torque exceeds a threshold value. That is, by flowing a current through layer CA (between terminal IT1 and terminal IT2), the magnetization direction of layer FL can be changed. By this operation, information can be recorded in MTJ element ME.

[0099] Layer TIS functions as a layer having a tunnel insulator in MTJ element ME. When a voltage is applied between layer FL and layer RL (terminal OT), a tunnel current can flow through layer TIS due to the tunnel magnetoresistance effect. At this time, the electrical resistance value of layer TIS changes depending on the direction of the magnetic moment of layer FL. Specifically, the electrical resistance value of layer TIS changes depending on whether the magnetization directions of layer FL and layer RL are parallel or antiparallel.

[0100] As the tunnel insulator, for example, magnesium oxide, aluminum oxide, etc. can be used. In particular, it is preferable to use crystalline magnesium oxide as the tunnel insulator.

[0101] Layer RL functions as a fixed layer in MTJ element ME. Layer RL has a ferromagnetic material. Note that the ferromagnetic material of layer RL has a fixed magnetization direction, unlike the ferromagnetic material of layer FL.

[0102] As the ferromagnetic material contained in layer RL, for example, a material applicable to the ferromagnetic material contained in layer FL can be used.

[0103] Note that the ferromagnetic material and the tunnel insulator included in MTJ element ME are preferably combined so that the magnetoresistance ratio (MR ratio) of MTJ element ME becomes large.

[0104] Here, an example of an information writing method and an example of a reading method in memory cell MC of FIG. 3A will be described.

[0105] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on each of the transistor M1 and the transistor M2. Next, a first potential is applied to the terminal IT1 from the wiring BL1 via the transistor M1, and a second potential is applied to the terminal IT2 from the wiring BL2 via the transistor M2. As a result, in the resistance change device MD, a current corresponding to the potential difference between the first potential and the second potential flows between the terminal IT1 and the terminal IT2. For this reason, a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the magnetization direction of the ferromagnetic body in the layer FL is determined by the spin current. Note that the first potential may be higher or lower than the second potential. Further, the potential applied by the wiring RBL is preferably a potential in a range where no current flows between the terminal IT1 and the terminal OT and / or between the terminal IT2 and the terminal OT.

[0106] When reading information from the memory cell MC, a high-level potential is applied to the wiring WL to turn on each of the transistor M1 and the transistor M2. Next, a predetermined voltage is applied to each of the terminals IT1, IT2, and OT so that a current flows between the terminal IT1 and the terminal OT and / or between the terminal IT2 and the terminal OT. At this time, since the electrical resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layer RL and the layer FL are parallel or anti-parallel, the amount of tunnel current flowing through the layer TIS of the MTJ element ME also changes. Here, the information recorded in the MTJ element ME can be read by measuring the amount of current flowing between the MTJ element ME and the terminal OT. Further, the information recorded in the MTJ element ME can also be read by applying a predetermined potential to each of the terminals IT1 and IT2, flowing a constant current between the MTJ element ME and the terminal OT, and measuring the potential of the terminal OT.

[0107] [Configuration Example 1 of Peripheral Circuit] Next, a configuration example in which the memory cell MC in FIG. 3A is applied to the storage device MDV in FIG. 1A is shown in FIG. 5A. Note that in FIG. 5A, for ease of viewing, each component is illustrated on a plane, but the memory cell array MCA is provided above the peripheral circuit PHL as in the storage device MDV in FIG. 1A.

[0108] In the memory device MDV of FIG. 5A, the description of the parts overlapping with the content of the memory device MDV of FIG. 1A will be omitted.

[0109] In the memory device MDV of FIG. 5A, the peripheral circuit PHL includes a circuit WD, a circuit BD, and a circuit RBD. Refer to the description of the memory device MDV of FIG. 1A for the circuit WD and the circuit BD.

[0110] The circuit RBD is electrically connected to wiring RBL[1] to wiring RBL[m] as an example. Further, the circuit RBD functions as a circuit for receiving read information from the memory cells MC included in the memory cell array MCA via the wiring RBL[1] to wiring RBL[m]. That is, the circuit RBD can be a circuit corresponding to the sense amplifier 2633 in the memory device MDV of FIG. 2, for example. Therefore, the circuit RBD may be configured to be included in the circuit BD corresponding to the bit line driver circuit 2630.

[0111] Also, the circuit BD is electrically connected to wiring BL1[1] to wiring BL1[n] and wiring BL2[1] to wiring BL2[n] as the wiring BL[1] to wiring BL[n] in the memory device MDV of FIG. 1A. That is, wiring BL1 and wiring BL2 are provided for each column of the memory cell array MCA.

[0112] At this time, it is preferable that the circuit BD is configured to input different voltages (or currents) to the wiring BL1 and the wiring BL2 in each of the case of writing information to the memory cell MC and the case of reading information from the memory cell MC.

[0113] Note that the configuration example in which the memory cell MC of FIG. 3A is applied to the memory device MDV of FIG. 1A is not limited to the configuration of the memory device MDV of FIG. 5A. The memory device MDV of FIG. 5A may change its circuit configuration according to the situation.

[0114] <<Configuration Example 2 of Memory Cell>> Figure 3C shows an example of a memory cell that can be provided in the memory device MDV, which is different from that in Figure 3A. Note that the memory cell MC shown in Figure 3C can also be regarded as an example of SOT-MRAM.

[0115] The memory cell MC has, for example, a transistor M3, a transistor M4, and a resistance change device MD.

[0116] As the transistor M3 and the transistor M4, for example, an OS transistor can be applied in the same manner as the transistor M1 and the transistor M2. Also, the resistance change device MD has the MTJ element ME in Figure 4 in the same manner as the resistance change device MD in Figure 3A.

[0117] The first terminal of the transistor M3 is electrically connected to the terminal IT2 of the resistance change device MD, the second terminal of the transistor M3 is electrically connected to the wiring SL, and the gate of the transistor M3 is electrically connected to the wiring WLa. The first terminal of the transistor M4 is electrically connected to the terminal OT of the resistance change device MD, the second terminal of the transistor M4 is electrically connected to the wiring SL, and the gate of the transistor M4 is electrically connected to the wiring WLb. The terminal IT1 of the resistance change device MD is electrically connected to the wiring BL.

[0118] As an example, the wiring BL functions as a bit line for the memory cell MC or a wiring for applying a constant voltage.

[0119] As an example, the wiring SL functions as a wiring for applying a constant voltage.

[0120] As an example, the wiring WLa functions as a write word line and a read word line for the memory cell MC.

[0121] As an example, the wiring WLb functions as a read word line for the memory cell MC.

[0122] Next, an example of a method for writing information and an example of a method for reading information in the memory cell MC of FIG. 3C will be described. Note that, as an example, a low-level potential is applied to the wiring SL.

[0123] When writing information to the memory cell MC, a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a low-level potential is applied to the wiring WLb to turn off the transistor M4. Next, a third potential higher than the low-level potential is applied from the wiring BL to the terminal IT1. As a result, in the resistance change device MD, a current corresponding to the potential difference between the third potential and the low-level potential flows between the terminal IT1 and the terminal IT2. For this reason, a current flows through the layer CA of the MTJ element ME, a spin current is generated in the layer CA, and the magnetization direction of the ferromagnetic body in the layer FL is determined by the spin current.

[0124] When reading information from the memory cell MC, a high-level potential is applied to the wiring WLa to turn on the transistor M3, and a high-level potential is applied to the wiring WLb to turn on the transistor M4. Next, by applying a fourth potential higher than the low-level potential and lower than the third potential from the wiring BL to the terminal IT1, a current flows between the terminal IT1 and the terminal IT2 and / or between the terminal IT1 and the terminal OT. At this time, since the electrical resistance value of the MTJ element ME changes depending on whether the magnetization directions of the layer RL and the layer FL are parallel or anti-parallel, the amount of tunnel current flowing through the layer TIS of the MTJ element ME also changes. That is, by measuring the amount of current flowing through the MTJ element ME and the terminal IT1, the information recorded in the MTJ element ME can be read. Also, by applying a predetermined potential to the wiring SL, flowing a constant current from the wiring BL to the terminal IT1 of the MTJ element ME, and measuring the potential of the terminal IT1, the information recorded in the MTJ element ME can also be read.

[0125] Further, the memory cell MC in FIG. 3C may be configured such that the back gates of the transistor M3 and the transistor M4 are electrically connected to the wiring BGE, similarly to FIG. 3B. Specifically, the memory cell MC can have the configuration shown in FIG. 3D. By applying a predetermined potential to the wiring BGE, the threshold voltages of the transistor M3 and the transistor M4 can be varied.

[0126] [Configuration Example 2 of Peripheral Circuit] Next, FIG. 5B shows a configuration example in which the memory cell MC in FIG. 3C is applied to the storage device MDV in FIG. 1A. In FIG. 5B, each component is illustrated in a plane for easy viewing, but the memory cell array MCA is provided above the peripheral circuit PHL as in the storage device MDV in FIG. 1A, as shown in FIG. 5A.

[0127] Note that in the storage device MDV in FIG. 5B, descriptions of portions overlapping with the content of the storage device MDV in FIG. 1A are omitted.

[0128] In the storage device MDV in FIG. 5B, the peripheral circuit PHL includes a circuit WD, a circuit BD, and a circuit SD. For the circuit WD, the circuit BD, and the circuit SD, refer to the description of the storage device MDV in FIG. 1A.

[0129] In the storage device MDV in FIG. 5B, the wirings SL[1] to SL[n] are provided in the column direction instead of the row direction, which is different from the storage device MDV in FIG. 1A. Thus, in the storage device MDV, the direction in which the wirings are extended is not particularly limited.

[0130] Further, the circuit WD is electrically connected to the wirings WLa[1] to WLa[m] and the wirings WLb[1] to WLb[m] as the wirings WL[1] to WL[m] in the storage device MDV in FIG. 1A. That is, for each row of the memory cell array MCA, the wirings WLa and the wirings WLb are provided.

[0131] At this time, it is preferable that the circuit WD is configured to input different voltages to the wiring WLa and the wiring WLb, respectively, when writing information to the memory cell MC and when reading information from the memory cell MC.

[0132] Note that the configuration example in which the memory cell MC in FIG. 3C is applied to the storage device MDV in FIG. 1A is not limited to the configuration of the storage device MDV in FIG. 5B. The storage device MDV in FIG. 5B may change its circuit configuration according to the situation.

[0133] <<Configuration Example 3 of Memory Cell>> FIG. 6A shows an example of a memory cell that can be provided in the storage device MDV. Note that the memory cell shown in FIG. 6A can be said to be an example of STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory).

[0134] The memory cell MC includes a transistor M10 and the MTJ element ME described above.

[0135] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0136] The MTJ element ME has a layer FL having a free layer, a layer TIS having a tunnel insulator, and a layer RL having a fixed layer, and the layer FL and the layer RL overlap via the layer TIS, similar to the MTJ element shown in FIG. 4.

[0137] The first terminal of the transistor M10 is electrically connected to the layer RL of the MTJ element ME, the second terminal of the transistor M10 is electrically connected to the wiring SL, and the gate of the transistor M10 is electrically connected to the wiring WL. The layer FL of the MTJ element ME is electrically connected to the wiring BL.

[0138] As an example, the wiring BL functions as a write bit line or a read bit line for the memory cell MC.

[0139] The wiring WL functions as a word line for the memory cell MC as an example.

[0140] The wiring SL functions as a wiring for applying a fixed voltage as an example. As the fixed voltage, for example, a low-level potential can be used.

[0141] Here, an example of a method for writing information and an example of a method for reading information in the memory cell MC of FIG. 6A will be described.

[0142] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, the layer RL and the wiring SL are in a conductive state. Also, depending on the voltage condition between the wiring BL and the wiring SL, a tunnel current is generated in the layer TIS, so a current flows between the wiring BL and the wiring SL. At this time, by flowing a large amount of electrons with spins aligned in a certain direction in the layer FL, the magnetization direction of the layer FL can be changed. Thereby, information can be recorded in the MTJ element ME.

[0143] When reading information from the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, the layer RL and the wiring SL are in a conductive state. Here, when a fixed voltage is applied to the wiring BL, the amount of current flowing through the MTJ element ME is determined by whether the magnetization directions of the layer RL and the layer FL are parallel or antiparallel. Specifically, for example, the amount of current when the magnetization directions of the layer RL and the layer FL are parallel is larger than the amount of current when the magnetization directions of the layer RL and the layer FL are antiparallel. That is, by measuring the amount of current flowing through the MTJ element ME, the information recorded in the MTJ element ME can be read out.

[0144] The memory cell MC in FIG. 6A can record information by flowing electrons with their spins aligned in a certain direction through the MTJ element ME and changing the magnetization direction of the layer FL. However, the configuration of the memory cell MC provided in the memory device according to one aspect of the present invention is not limited to this. For example, a configuration may be adopted in which a wiring having a function of generating a magnetic field is provided near the MTJ element ME. In this configuration, information can be written into the MTJ element ME by generating a magnetic field from the wiring and changing the magnetization direction of the layer FL of the MTJ element ME.

[0145] <<Example Configuration 4 of Memory Cell>> FIG. 6B shows an example of a memory cell that can be provided in the memory device MDV. Note that the memory cell shown in FIG. 6B can be referred to as an example of a ReRAM (Resistive Random Access Memory).

[0146] The memory cell MC includes a transistor M10 and a resistive change element RM.

[0147] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0148] As shown in FIG. 6B, the memory cell MC in FIG. 6B has a configuration in which the MTJ element ME of the memory cell MC in FIG. 6A is replaced with a resistive change element RM. Note that in the memory cell MC in FIG. 6B, the first terminal of the resistive change element RM is electrically connected to the first terminal of the transistor M10, and the second terminal of the resistive change element RM is electrically connected to the wiring BL.

[0149] As an example, the wiring BL functions as a write bit line or a read bit line for the memory cell MC.

[0150] As an example, the wiring WL functions as a word line for the memory cell MC.

[0151] The wiring SL functions as wiring for supplying a constant voltage as an example. As the constant voltage, for example, a reference potential can be used.

[0152] Here, an example of a method for writing information and an example of a method for reading information in the memory cell MC of FIG. 6B will be described.

[0153] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, conduction is established between the wiring BL and the wiring SL. Further, by applying a pulse voltage (positive pulse voltage) higher than the reference potential or a pulse voltage (negative pulse voltage) lower than the reference potential to the wiring BL, the pulse voltage is input to the second terminal of the resistive change element RM. At this time, depending on whether the voltage applied to the second terminal of the resistive change element RM is a positive pulse voltage or a negative pulse voltage, the electrical resistance of the resistive change element RM changes. Thereby, information can be recorded in the resistive change element RM of the memory cell MC.

[0154] When reading information from the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, conduction is established between the wiring BL and the wiring SL. Here, when a constant voltage greater than the negative pulse voltage and less than the positive pulse voltage is applied to the wiring BL, the amount of current flowing through the resistive change element RM is determined by the value of the electrical resistance of the resistive change element RM. That is, by measuring the amount of current flowing through the resistive change element RM, the information recorded in the resistive change element RM can be read.

[0155] <<Example Configuration 5 of Memory Cell>> FIG. 6C shows an example of a memory cell that can be provided in the storage device MDV. Note that the memory cell shown in FIG. 6C can be an example of a phase change memory (sometimes referred to as PCM, PRAM, etc.).

[0156] The memory cell MC includes a transistor M10 and a phase change memory PCM1.

[0157] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0158] The phase change memory PCM1 has, as an example, an electrode TE, a phase change layer CHL, and an electrode BE, and is electrically connected in the order of the electrode TE, the phase change layer CHL, and the electrode BE.

[0159] Also, as the phase change layer CHL, for example, chalcogenide glass can be applied. In this embodiment, the phase change layer CHL will be described as being made of chalcogenide glass.

[0160] It is preferable that the electrode TE and the electrode BE have different contact areas with the phase change layer CHL. For example, in FIG. 6C, the contact area between the electrode TE and the phase change layer CHL is shown to be larger than the contact area between the electrode BE and the phase change layer CHL. By reducing the contact area of the electrode BE with the phase change layer CHL, heat can be locally applied to the phase change layer CHL, so that a phase change is more likely to occur in the phase change layer CHL near the electrode BE than in the phase change layer CHL near the electrode TE.

[0161] As shown in FIG. 6C, the memory cell MC in FIG. 6C has a configuration in which the MTJ element ME of the memory cell MC in FIG. 6A is replaced with the phase change memory PCM1. In the memory cell MC of FIG. 6C, it is assumed that the electrode BE of the phase change memory PCM1 is electrically connected to the first terminal of the transistor M10, and the electrode TE of the phase change memory PCM1 is electrically connected to the wiring BL.

[0162] The wiring BL functions, as an example, as a write bit line or a read bit line for the memory cell MC.

[0163] The wiring WL functions, as an example, as a word line for the memory cell MC.

[0164] The wiring SL functions as wiring for applying a constant voltage as an example. As the constant voltage, for example, a low-level potential can be used.

[0165] Here, an example of a method for writing information and an example of a method for reading information in the memory cell MC of FIG. 6C will be described.

[0166] When writing information to the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, conduction is established between the wiring BL and the wiring SL. Also, when the chalcogenide glass of the phase change layer CHL is in an amorphous state, for example, a high-level potential is applied from the wiring BL (specifically, a high voltage is applied between the electrode TE and the electrode BE), and by increasing the amount of current flowing through the phase change memory PCM1, impact ionization occurs in the chalcogenide glass and carriers increase, causing the electrical resistance of the chalcogenide glass to rapidly decrease. As a result, a larger current flows through the chalcogenide glass, generating Joule heat in the chalcogenide glass and increasing the temperature of the chalcogenide glass. Thereby, the chalcogenide glass melts. Thereafter, by controlling the voltage from the wiring BL to maintain the temperature of the chalcogenide ride glass in the crystallization temperature range, the chalcogenide glass can transition to a polycrystalline state. After the chalcogenide glass is made polycrystalline, even if the voltage supply from the wiring BL and the wiring SL is stopped, the chalcogenide glass can maintain the polycrystalline state.

[0167] Also, after raising the temperature of the chalcogenide glass by Joule heat to melt the chalcogenide glass, the voltage supply from the wiring BL and the wiring SL is stopped, and by rapidly cooling the chalcogenide glass, the chalcogenide glass can be transitioned to an amorphous state.

[0168] The memory cell MC can record information in the phase change memory PCM1 by changing the phase of the chalcogenide glass contained in the phase change layer CHL.

[0169] When reading information from the memory cell MC, a high-level potential is applied to the wiring WL to turn on the transistor M10. As a result, the wiring BL and the wiring SL are in a conductive state. Here, when a voltage lower than that during writing is applied to the wiring BL, the amount of current flowing between the electrode TE and the electrode BE of the phase change memory PCM1 depends on whether the chalcogenide glass of the phase change layer CHL is in an amorphous state or a polycrystalline state. Specifically, for example, when the chalcogenide glass is in an amorphous state, the amount of current is small, and when the chalcogenide glass is in a polycrystalline state, the amount of current is large. That is, by measuring the amount of current flowing through the phase change memory PCM1, the information recorded in the phase change memory PCM1 can be read out.

[0170] A memory cell having memory elements such as the MTJ element ME, the resistance change element RM, and the phase change memory PCM1 functions as a non-volatile memory, so that the power for retaining data can be reduced. Therefore, by applying the above-described configuration as a storage device, a storage device with low power consumption can be provided. Further, by applying an OS transistor or the like as the transistor of the memory cell, the memory cell array can be manufactured by a semiconductor process, so that the memory cell array can be stacked above the peripheral circuit. By stacking a plurality of memory cell arrays, a storage device with a large storage capacity can be provided.

[0171] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0172] (Embodiment 2) In this embodiment, an example of the cross-sectional structure of the storage device described in the above embodiment will be described.

[0173] FIG. 7 is a cross-sectional view schematically showing a configuration example of the memory device MDV in FIG. 1B. Specifically, the memory device MDV shown in FIG. 7 includes a layer SIL and layers OSL[1] to OSL[p] (where p is an integer of 1 or more) provided above the layer SIL. Note that the layer SIL has, for example, the peripheral circuit PHL described in Embodiment 1. Each of the layers OSL[1] to OSL[p] has, for example, the memory cell array MCA described in Embodiment 1.

[0174] As an example, the layer SIL has a transistor 300, and each of the layers OSL[1] to OSL[p] has a transistor 500A, a transistor 500B, and a memory element 400. In particular, in this specification and the like, one or both of the transistor 500A and the transistor 500B may be referred to as the transistor 500.

[0175] FIG. 8A shows a cross-sectional view of the transistor 500 in the channel length direction, FIG. 8B shows a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 8C shows a cross-sectional view of the transistor 300 in the channel width direction. Note that the transistors shown in each of FIGS. 8A to 8C may have a partially different shape from the transistors shown in FIG. 7 for the purpose of explanation.

[0176] Each of the layers OSL[1] to OSL[p] has a memory cell 600, and the memory cell 600 includes a transistor 500A, a transistor 500B, and a memory element 400.

[0177] Further, as an example of the configuration of the memory cell 600, it is the memory cell MC in FIG. 3A. Specifically, the transistor 500A corresponds to one of the transistors M1 or M2, the transistor 500B corresponds to the other of the transistors M1 or M2, and the memory element 400 corresponds to the resistance change device MD. Therefore, in the storage device MDV in FIG. 7, the first terminal of the transistor 500A is electrically connected to the first terminal of the transistor 500B and the first terminal of the memory element 400.

[0178] Note that one of the wirings BL1 or BL2 in FIG. 3A can be the conductor 450 that is electrically connected to, for example, one of the second terminals of the transistor 500A or the transistor 500B. Also, the other of the wirings BL1 or BL2 in FIG. 3A can be the conductor 450 that is electrically connected to, for example, the other of the second terminals of the transistor 500A or the transistor 500B. The conductor 450 will be described later.

[0179] Also, the wiring WL in FIG. 3A can be the conductor 560 corresponding to the gates of the transistors 500A and 500B, respectively. Also, the wiring RBL in FIG. 3A can be the conductor 460 that is electrically connected to the second terminal of the memory element 400. The conductor 460 will be described later.

[0180] The transistor 500 is a transistor (OS transistor) having a metal oxide in the channel formation region. The transistor 500 has characteristics of a small off-current and a low change in the field-effect mobility even at high temperatures. By applying the transistor 500 to, for example, the transistors included in the above storage device, a storage device with a low reduction in operating ability even at high temperatures can be realized.

[0181] The peripheral circuit PHL included in the layer SIL has, for example, a circuit WD, a circuit BD, a circuit SD, a circuit CLC, a circuit OPC, etc., as shown in the configuration of the storage device MDV in FIG. 1B. Therefore, the transistor 300 can be a transistor included in the circuit WD, the circuit BD, the circuit RBD, the circuit SD, the circuit CLC, the circuit OPC, etc.

[0182] The transistor 300 has a semiconductor region 313 composed of a part of a conductor 316, an element isolation layer 312, an insulator 315, and a substrate 310, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0183] As the substrate 310, for example, a semiconductor substrate can be applied. Examples of the semiconductor substrate include a substrate made of silicon and a substrate made of germanium as described above. Alternatively, as the substrate 310, for example, a compound semiconductor substrate can be applied. Examples of the compound semiconductor substrate include substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, etc. as described above.

[0184] As shown in FIG. 8C, the upper surface and the side surface in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with the conductor 316 via the insulator 315. In this way, by making the transistor 300 a Fin type, the effective channel width is increased, so that the on characteristics of the transistor 300 can be improved. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0185] Note that the transistor 300 can be either a p-channel type or an n-channel type.

[0186] In a region where a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, a source region, or a drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is more preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs, GaAlAs, etc., the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0187] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0188] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0189] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0190] The element isolation layer 312 is provided to separate a plurality of transistors formed on the substrate 310. The element isolation layer 312 can be formed, for example, by using a LOCOS (Local Oxidation of Silicon) method, a STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

[0191] Note that the transistor 300 shown in FIGS. 7 and 8C is an example and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration, driving method, and the like. For example, the transistor 300 shown in FIGS. 7 and 8C may be a planar type transistor.

[0192] In the transistor 300 shown in FIG. 7, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked and provided in this order from the substrate 310 side.

[0193] As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, nitrided silicon oxide, silicon nitride, aluminum oxide, aluminum oxynitride, nitrided aluminum oxide, aluminum nitride, or the like may be used.

[0194] Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and nitrided silicon oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and nitrided aluminum oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0195] The insulator 322 may function as a planarization film that planarizes steps generated by the transistor 300 and the like covered by the insulator 320 and the insulator 322. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0196] In addition, for the insulator 324, it is preferable to use a film having a barrier property such that impurities such as water and hydrogen do not diffuse into the region where the transistor 500 is provided from the substrate 310 or the transistor 300 or the like.

[0197] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0198] The amount of hydrogen desorption can be analyzed, for example, using temperature programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0199] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0200] In addition, conductors 328, 330, etc. are embedded in insulators 320, 322, 324, and 326. Note that conductors 328 and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Further, in this specification and the like, a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0201] As materials for each plug and wiring (conductors 328, 330, etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a laminated manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0202] A wiring layer may be provided on insulator 326 and conductor 330. For example, in FIG. 7, insulators 350, 352, and 354 are sequentially laminated and provided on insulator 326 and conductor 330. Also, a conductor 356 is formed in insulators 350, 352, and 354. Conductor 356 has a function as a plug connected to transistor 300 or a wiring as an example. Note that conductor 356 can be provided using the same material as conductors 328 and 330.

[0203] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen for the insulator 350. Further, for the insulator 352 and the insulator 354, as with the insulator 326, it is preferable to use an insulator having a relatively low dielectric constant in order to reduce the parasitic capacitance generated between the wirings. Further, the conductor 356 preferably includes a conductor having a barrier property against water, hydrogen, etc. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0204] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0205] Further, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are laminated in this order.

[0206] As with the insulator 324 and the like, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen for the insulator 360. Therefore, as the insulator 360, for example, a material applicable to the insulator 324 and the like can be used.

[0207] The insulator 362 and the insulator 364 have functions as an interlayer insulating film and a planarization film. Further, as with the insulator 324, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen for the insulator 362 and the insulator 364. Therefore, as the insulator 362 and / or the insulator 364, a material applicable to the insulator 324 can be used.

[0208] In addition, openings are formed in regions of the insulators 360, 362, and 364 that overlap with some of the conductors 356, and conductors 366 are provided to fill the openings. Also, the conductors 366 are formed on the insulator 362. The conductors 366, as an example, have the function of a plug connected to the transistor 300 or a wiring. Note that the conductors 366 can be provided using the same materials as the conductors 328 and 330.

[0209] On the insulator 364 and the conductors 366, an insulator 510, an insulator 512, an insulator 513, an insulator 514, and an insulator 516 are sequentially stacked. Any one of the insulators 510, 512, 513, 514, and 516 is preferably made of a material having barrier properties against oxygen and / or hydrogen.

[0210] For example, for the insulators 510 and 514, it is preferable to use a film having barrier properties such that impurities such as water and hydrogen do not diffuse into the region where the transistor 500 is provided from the substrate 310 or the like. Therefore, the same materials as those of the insulator 324 or the like can be used.

[0211] As an example of a film having barrier properties against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the substrate 310. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0212] Also, as a film having barrier properties against hydrogen, for example, for the insulators 510 and 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0213] In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which are factors causing fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the incorporation of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0214] Also, for example, as the insulator 513, it is preferable to use a film having a barrier property that prevents the diffusion of impurities such as water and hydrogen, similar to the insulator 510 and the insulator 514. In particular, in FIG. 7, the insulator 513 functions as a film that seals the transistor 500 together with the insulator 576 to be described later. For this reason, it is preferable to use a material applicable to the insulator 576 for the insulator 513. Also, the insulator 513 may use a material applicable to the insulator 510 or the insulator 514.

[0215] Also, for example, the same materials as the insulator 320 or the insulator 326 can be used for the insulator 512 and the insulator 516. In addition, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, silicon oxide, silicon oxynitride, etc. can be used as the insulator 512 and the insulator 516.

[0216] Also, conductors such as the conductor 518 and the conductors constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 8A and 8B) are embedded in the insulator 510, the insulator 512, the insulator 513, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a plug or a wiring that connects the conductor 450, the conductor 460, the transistor 300, etc. to be described later. The conductor 518 can be provided using, for example, the same materials as the conductor 328 and the conductor 330.

[0217] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 500 can be separated by a layer having a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0218] Above the insulator 516, a transistor 500 is provided.

[0219] As shown in FIGS. 8A and 8B, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an oxide 530c disposed on the bottom surface and the side surface of the opening, an insulator 550 disposed on the formation surface of the oxide 530c, and a conductor 560 disposed on the formation surface of the insulator 550. In this specification and the like, the conductors 542a and 542b are collectively referred to as a conductor 542.

[0220] Also, as shown in FIGS. 8A and 8B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Also, as shown in FIGS. 8A and 8B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 8A and 8B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 550.

[0221] Note that in the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0222] Note that in the transistor 500, a configuration in which three layers of the oxide 530a, the oxide 530b, and the oxide 530c are stacked in a region where a channel is formed and in its vicinity is shown, but one aspect of the present invention is not limited to this. For example, a single layer of the oxide 530b, a two-layer structure of the oxide 530b and the oxide 530a, a two-layer structure of the oxide 530b and the oxide 530c, or a stacked structure of four or more layers may be provided. Further, in the transistor 500, the conductor 560 is shown as a two-layer stacked structure, but one aspect of the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. Further, the transistor 500 shown in FIGS. 7, 8A, and 8B is an example, and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration, driving method, and the like.

[0223] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-aligned with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the memory device can be achieved.

[0224] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved, and it can have high frequency characteristics.

[0225] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560, the threshold voltage of the transistor 500 can be controlled. In particular, by applying a negative potential to the conductor 503, it becomes possible to increase the threshold voltage of the transistor 500 and reduce the off-current. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0226] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected and can cover the channel formation region formed in the oxide 530. In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of a first gate electrode and a second gate electrode is called a surrounded channel (S-channel) structure.

[0227] Further, the conductor 503 has the same configuration as the conductor 518. A conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside. Note that in the transistor 500, a configuration in which the conductor 503a and the conductor 503b are laminated is shown, but one aspect of the present invention is not limited thereto. For example, the conductor 503 may be provided as a single layer or a laminated structure of three or more layers.

[0228] Here, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0229] For example, by having the function of suppressing the diffusion of oxygen in the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0230] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. Also, when the conductivity of the wiring can be maintained high, the conductor 503a does not necessarily have to be provided. Note that the conductor 503b is shown as a single layer, but it may have a laminated structure. For example, it may be a laminate of titanium or titanium nitride and the above conductive material.

[0231] The insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

[0232] Here, as the insulator 524 in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. That is, it is preferable that an excess oxygen region is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. In this specification and the like, the oxygen vacancies in the metal oxide may be referred to as V O (oxygen vacancy).

[0233] In a transistor using a metal oxide, if there are impurities or oxygen vacancies (V O ) in the region where the channel in the metal oxide is formed, the electrical characteristics are likely to fluctuate, and the reliability may deteriorate. Also, hydrogen near the oxygen vacancy (V O ) may form a defect in which hydrogen enters the oxygen vacancy (hereinafter, may be referred to as V O H), and may generate electrons serving as carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen vacancies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible. In other words, the region where the channel in the oxide semiconductor is formed preferably has a reduced carrier concentration and is of the i-type (intrinsic) or substantially i-type. O H

[0234] Specifically, as the insulator having an excess oxygen region, it is preferable to use an oxide material in which some oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating means that, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3More preferably, it is 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more. The oxide film is as described above. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0235] Further, the insulator having the above excess oxygen region and the oxide 530 may be brought into contact with each other and subjected to any one or a plurality of treatments such as heat treatment, microwave treatment, or RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the bond of VoH is broken. In other words, a reaction of "V O H→V O +H" occurs, and dehydrogenation can be achieved. Part of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from the oxide 530 or the insulator near the oxide 530. In addition, part of the hydrogen may diffuse or be trapped (also referred to as gettering) in the conductor 542a and the conductor 542b.

[0236] Further, for the above microwave treatment, it is suitable to use, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Further, for the above microwave treatment, the pressure may be 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. As the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0237] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment while the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce oxygen vacancies (V O O

[0238] In addition, by performing an oxygen addition treatment on the oxide 530, the oxygen vacancies in the oxide 530 can be repaired by the supplied oxygen. In other words, the reaction of "V O O O +O→null" can be promoted. Further, by reacting the oxygen supplied to the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. Thereby, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with oxygen vacancies to form V

[0239] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0240] Since the insulator 522 has a function of suppressing the diffusion of oxygen, impurities, etc., the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side, which is preferable. Also, it is possible to suppress the conductor 503 from reacting with the oxygen contained in the insulator 524 and the oxide 530.

[0241] The insulator 522 preferably uses, as a single layer or a laminate, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0242] In particular, it is preferable to use an insulator containing one or both of the oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the oxygen is difficult to permeate). As the insulator containing one or both of the oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0243] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated and used on the above insulators.

[0244] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining a high-k material insulator with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0245] Note that in the transistors 500 of FIGS. 8A and 8B, the insulators 520, 522, and 524 are shown as a second gate insulating film having a three-layer laminated structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0246] For the transistor 500, it is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (the element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. In particular, the In-M-Zn oxide applicable as the oxide 530 is preferably CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) or CAC-OS (Cloud-Aligned Composite Oxide Semiconductor). Further, an In-Ga oxide, an In-Zn oxide, an In oxide, etc. may be used as the oxide 530.

[0247] In addition, for the transistor 500, it is preferable to use a metal oxide with a low carrier concentration. When reducing the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be reduced and the defect level density may be reduced. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0248] In particular, hydrogen contained in the metal oxide may react with oxygen bonded to the metal atom to form water, and thus oxygen vacancies may be formed in the metal oxide. Further, when hydrogen enters the oxygen vacancies in the oxide 530, oxygen vacancies and hydrogen may combine to form V O H. There is a case where V O H functions as a donor, and electrons that are carriers may be generated. Further, a part of hydrogen may combine with oxygen bonded to the metal atom to generate electrons that are carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the metal oxide is likely to move due to stress such as heat and an electric field, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain a metal oxide in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the metal oxide (which may be described as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to fill oxygen vacancies (which may be described as oxygen addition treatment). V O By using a metal oxide in which impurities such as V

[0249] H are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.Defects in which hydrogen enters oxygen deficiencies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, in metal oxides, evaluation may be performed using carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the metal oxide, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as "donor concentration" in some cases.

[0250] Therefore, when using a metal oxide for the oxide 530, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0251] Also, when using a metal oxide for the oxide 530, the metal oxide is a semiconductor having a large bandgap, being intrinsic (also referred to as type I) or substantially intrinsic, and the carrier concentration of the metal oxide in the channel formation region is preferably less than 1×10 18 cm -3 , more preferably less than 1×10 17 cm -3 , still more preferably less than 1×10 16 cm -3 , still more preferably less than 1×10 13 cm -3 , still more preferably less than 1×10 12 cm -3It is more preferably less. Note that the lower limit value of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, and for example, it can be 1×10 -9 cm -3 .

[0252] Further, when a metal oxide is used for the oxide 530, oxygen in the oxide 530 may diffuse into the conductor 542a and the conductor 542b when the conductor 542a and the conductor 542b are in contact with the oxide 530, and the conductor 542a and the conductor 542b may be oxidized. When the conductor 542a and the conductor 542b are oxidized, the probability that the conductivity of the conductor 542a and the conductor 542b decreases is high. Note that the diffusion of oxygen in the oxide 530 into the conductor 542a and the conductor 542b can be rephrased as the conductor 542a and the conductor 542b absorbing oxygen in the oxide 530.

[0253] Further, when oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, a different layer may be formed between the conductor 542a and the oxide 530b, and between the conductor 542b and the oxide 530b. Since the different layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the different layer has insulating properties. At this time, the three-layer structure of the conductor 542a or the conductor 542b, the different layer, and the oxide 530b can be regarded as a three-layer structure composed of a metal-insulator-semiconductor, and may be referred to as a MIS (Metal-Insulator-Semiconductor) structure, or may be referred to as a diode junction structure mainly having a MIS structure.

[0254] Note that the above different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b. For example, the different layer may be formed between the conductor 542a and the conductor 542b and the oxide 530c.

[0255] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0256] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed below the oxide 530a to the oxide 530b. Also, by having the oxide 530c on the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the structure formed above the oxide 530c to the oxide 530b.

[0257] Note that the oxide 530 preferably has a stacked structure with a plurality of oxide layers having different atomic number ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M in the constituent elements is preferably larger than the atomic number ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic number ratio of the element M to In is preferably larger than the atomic number ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic number ratio of In to the element M is preferably larger than the atomic number ratio of In to the element M in the metal oxide used for the oxide 530a. Also, the oxide 530c can use the metal oxide that can be used for the oxide 530a or the oxide 530b.

[0258] Specifically, as the oxide 530a, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4 or 1:1:0.5 may be used. As the oxide 530b, a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3 or 1:1:1 may be used. As the oxide 530c, a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4, or an atomic ratio of Ga:Zn = 2:1, or Ga:Zn = 2:5 may be used. Specific examples of the case where the oxide 530c has a laminated structure include a laminated structure of In:Ga:Zn = 4:2:3 and In:Ga:Zn = 1:3:4, a laminated structure of Ga:Zn = 2:1 and In:Ga:Zn = 4:2:3, a laminated structure of Ga:Zn = 2:5 and In:Ga:Zn = 4:2:3, a gallium oxide, and a laminated structure of In:Ga:Zn = 4:2:3, etc.

[0259] Further, for example, when the atomic ratio of In to element M in the metal oxide used for the oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for the oxide 530b, as the oxide 530b, an In-Ga-Zn oxide having a composition such as In:Ga:Zn = 5:1:6 or in the vicinity thereof, In:Ga:Zn = 5:1:3 or in the vicinity thereof, In:Ga:Zn = 10:1:3 or in the vicinity thereof can be used.

[0260] As compositions other than those described above, for the oxide 530b, for example, metal oxides having a composition such as In:Zn = 2:1, In:Zn = 5:1, In:Zn = 10:1, or a composition in the vicinity of any one of these can be used.

[0261] It is preferable to combine these oxides 530a, 530b, and 530c so as to satisfy the above-described relationship of the atomic ratios. For example, it is preferable that the oxide 530a and the oxide 530c be metal oxides having a composition of In:Ga:Zn = 1:3:4 and compositions in the vicinity thereof, and that the oxide 530b be a metal oxide having a composition of In:Ga:Zn = 4:2:3 to 4.1 and compositions in the vicinity thereof. Note that the above compositions indicate the atomic ratios in the oxide formed on the substrate or the atomic ratios in the sputtering target. In addition, as the composition of the oxide 530b, increasing the ratio of In is preferable because it can increase the on-current of the transistor, the field-effect mobility, or the like.

[0262] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a and the oxide 530c be higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a and the oxide 530c be smaller than the electron affinity of the oxide 530b.

[0263] Here, at the junction of the oxide 530a, the oxide 530b, and the oxide 530c, the energy level of the lower end of the conduction band changes smoothly. In other words, it can be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a, the oxide 530b, and the oxide 530c changes continuously or is continuously joined. To achieve this, it is preferable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c.

[0264] Specifically, by having a common element (as a main component) other than oxygen in the oxide 530a and the oxide 530b and between the oxide 530b and the oxide 530c, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like as the oxide 530a and the oxide 530c.

[0265] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxides 530a and 530c as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0266] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0267] In FIGS. 8A and 8B, the conductors 542a and 542b are shown as single-layer structures, but they may also be multilayer structures of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0268] Also, a three-layer structure in which a titanium film or a titanium nitride film is provided, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon, and the like. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0269] Also, as shown in FIG. 8A, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductors 542a and 542b and in the vicinity thereof, respectively. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0270] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier concentration in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0271] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may cover the respective side surfaces of the oxide 530 and the insulator 524 and be provided to contact the insulator 522.

[0272] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulator 544, silicon oxynitride or silicon nitride can also be used.

[0273] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize in the heat treatment in the subsequent process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or the conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0274] By having the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 to the oxide 530b. Further, oxidation of the conductor 560 can be suppressed by the excess oxygen contained in the insulator 580.

[0275] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (upper surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0276] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0277] By providing an insulator that releases oxygen upon heating as insulator 550 in contact with the upper surface of oxide 530c, oxygen can be effectively supplied from insulator 550, through oxide 530c, to the channel formation region of oxide 530b. Further, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 550 is reduced. The film thickness of insulator 550 is preferably 1 nm or more and 20 nm or less.

[0278] Further, in order to efficiently supply the excess oxygen possessed by insulator 550 to oxide 530, a metal oxide may be provided between insulator 550 and conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from insulator 550 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 550 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Further, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0279] Note that insulator 550 may have a laminated structure similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a laminated structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Further, a laminated structure that is thermally stable and has a high relative dielectric constant can be formed.

[0280] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 8A and 8B, but it may also be a single-layer structure or a laminated structure of three or more layers.

[0281] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By the conductor 560a having a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by oxygen contained in the insulator 550 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. In addition, an oxide semiconductor applicable to the oxide 530 can be used as the conductor 560a. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0282] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Further, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0283] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0284] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 that releases oxygen upon heating in contact with the oxide 530c, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that it is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0285] The opening of the insulator 580 is formed to overlap with the region between the conductors 542a and 542b. Thereby, the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.

[0286] When miniaturizing the memory device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 may have a high aspect ratio shape. In the present embodiment, since the conductor 560 is provided to be embedded in the opening of the insulator 580, even if the conductor 560 has a high aspect ratio shape, it can be formed without collapsing the conductor 560 during the process.

[0287] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 550. By forming the insulator 574 by sputtering, an excess oxygen region can be provided in the insulator 550 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0288] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0289] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0290] A part of the insulator 574, the insulator 580, the insulator 544, the insulator 522, the insulator 520, the insulator 516, and the insulator 514 is removed to form an opening so as to surround the transistor 500 and expose the insulator 513, and an insulator 576 having high barrier properties against hydrogen or water is formed. For this reason, the side surfaces of the insulator 574, the insulator 580, the insulator 544, the insulator 522, the insulator 520, the insulator 516, and the insulator 514 are in contact with the insulator 576. Thereby, it is possible to prevent moisture and hydrogen from entering the transistor 500 from the outside.

[0291] As described above, it is preferable that the insulators 513 and 576 have a high function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.) or water molecules. For example, as the insulators 513 and 576, it is preferable to use silicon nitride or silicon oxynitride, which are materials having high hydrogen barrier properties. Thereby, since the diffusion of hydrogen or the like into the oxide 530 can be suppressed, the degradation of the characteristics of the transistor 500 can be suppressed. Therefore, the reliability of the memory device according to one aspect of the present invention can be enhanced.

[0292] Further, it is preferable to provide an insulator 581 that functions as an interlayer film and a planarization film on the insulator 576. Similar to the insulator 524 and the like, it is preferable that the insulator 581 has a reduced concentration of impurities such as water or hydrogen in the film.

[0293] Further, an insulator 552 is provided on the side surfaces of the openings formed in the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544. Then, conductors 540a and 540b are provided so as to be in contact with the side surface of the insulator 552 and the bottom surface of the opening. In FIG. 8A, the conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween.

[0294] The insulator 552 is provided in contact with, for example, the insulator 581, the insulator 576, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, it is possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 580 or the like through the conductors 540a and 540b to the oxide 530. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b. As described above, the reliability of the memory device according to one aspect of the present invention can be improved.

[0295] As the conductors 540a and 540b, for example, the same materials as the conductor 328, the conductor 330, the conductor 503, etc. can be used for provision. In particular, each of the conductors 540a and 540b has a laminated structure of two or more layers. In the first layer in contact with the insulator 552, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate) is formed. In the second layer and subsequent layers, it is preferable to form a highly conductive material mainly composed of tungsten, copper, aluminum, or the like.

[0296] In FIG. 7, an insulator 582 is provided on the insulator 581. As the insulator 582, it is preferable to use a material having a barrier property against oxygen and / or hydrogen. Therefore, the same material as the insulator 514 can be used for the insulator 582. For example, as the insulator 582, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0297] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the incorporation of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0298] Also, an insulator 586 is provided on the insulator 582. The insulator 586 can use the same material as the insulator 320. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0299] Also, as shown in FIGS. 7 and 8A, conductors 540a, 540b, 546, etc. are embedded in the insulators 520, 522, 524, 544, 580, 574, 576, 581, 582, and 586. Note that as the conductor 546, for example, a material applicable to the conductors 540a and 540b can be used.

[0300] The conductors 540a, 540b, and 546 function as plugs or wirings connecting the transistor 500, the transistor 300, conductors 450, 460, etc. to be described later. Also, the conductors 540a and 540b can be provided using the same material as the conductors 328 and 330. In particular, in FIG. 7, the conductor 546 is formed so as to be in contact with the conductor 518.

[0301] Further, a conductor 450 may be provided on the conductor 540a, the conductor 540b, the conductor 546, and the insulator 586. The conductor 450 functions as a wiring for connecting the conductor 460, the transistor 300, the transistor 500, etc., which will be described later. In particular, in FIG. 7, the conductor 450 is formed so as to be in contact with the conductor 540a, the conductor 540b, the conductor 546, etc.

[0302] For the conductor 450, for example, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-described elements as components can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0303] In FIG. 7, the conductor 450 shows a single-layer structure, but it is not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties, and a conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0304] Next, the configuration of the memory element 400 will be described. In this configuration example, the memory element 400 is an MTJ element ME included in the resistance change device MD of the memory cell MC in FIGS. 3A, 3B, etc.

[0305] The memory element 400 is provided in a partial region on the conductor 450. The memory element 400 has a conductor 401, an insulator 402, a conductor 403, and a conductor 404, and the conductor 401, the insulator 402, the conductor 403, and the conductor 404 are laminated in this order in the region.

[0306] Conductor 401 is the free layer in the memory element 400 and corresponds to layer FL of MTJ element ME in FIG. 4. Insulator 402 is the tunnel insulator in the memory element 400 and corresponds to layer TIS of MTJ element ME in FIG. 4. Conductor 403 is the fixed layer in MTJ element ME and corresponds to layer RL of MTJ element ME in FIG. 4. Therefore, for the materials applicable to each of conductor 401, insulator 402, and conductor 403, refer to the description of MTJ element ME in FIG. 4.

[0307] Conductor 404 is provided as a hard mask for forming conductor 401, insulator 402, and conductor 403. Therefore, for conductor 404, materials applicable to, for example, conductor 328 and conductor 330 can be used.

[0308] Insulator 452 is provided to cover insulator 586, conductor 450, conductor 401, insulator 402, conductor 403, and conductor 404.

[0309] As insulator 452, for example, similar to insulator 324, it is preferable to use a film having a barrier property that prevents diffusion of impurities such as water and hydrogen in the region where transistor 500 is provided. That is, as insulator 452, it is preferable to use materials applicable to insulator 324 and the like.

[0310] Insulator 454 is provided on insulator 452. Insulator 454 functions as a planarization film for planarizing the steps caused by conductor 450, memory element 400, insulator 452, etc. Also, insulator 454 can be formed, for example, by performing a planarization process using a chemical mechanical polishing (CMP) method or the like until conductor 404 is exposed after an insulator to become insulator 454 is formed on insulator 452.

[0311] Insulator 456 is provided on insulator 454, insulator 452, and conductor 404.

[0312] As the insulators 454 and 456, for example, similar to the insulator 326, it is preferable to use an insulator having a relatively low relative permittivity. That is, as the insulators 454 and 456, it is preferable to use a material applicable to the insulator 326.

[0313] A conductor 457 is embedded in the insulator 456. Also, a conductor 458 is embedded in the insulators 452, 454, and 456. Note that the conductors 457 and 458 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be collectively given the same reference numeral in some cases. Further, in this specification and the like, a wiring and a plug connected to the wiring may be an integral body. That is, in some cases, a part of the conductor functions as a wiring, and in some cases, a part of the conductor functions as a plug.

[0314] A conductor 460 is provided on the insulator 456, the conductor 457, and the conductor 458. The conductor 460 can be, for example, a wiring electrically connected to the memory element 400. Specifically, it can be the wiring RBL shown in the memory cell MC of FIG. 4.

[0315] As the conductor 460, for example, a material applicable to the conductor 450 can be used.

[0316] An insulator 459 is provided on the insulator 456. Also, in some cases, the insulator 459 may also be provided on the conductor 457 and / or the conductor 458. The insulator 459 functions, for example, as an insulator for separating wirings. In the memory device MDV of FIG. 7, the insulator 459 has the same height as the conductor 460 by a planarization process such as a chemical mechanical polishing (CMP) method.

[0317] As the insulator 459, for example, similar to the insulator 326, it is preferable to use an insulator having a relatively low relative permittivity. That is, as the insulator 459, it is preferable to use a material applicable to the insulator 326.

[0318] Further, an insulator 462 is provided on the conductor 460 and the insulator 459.

[0319] The insulator 462 is preferably a film having a barrier property such that impurities such as water and hydrogen do not diffuse between the upper and lower OSL layers. Therefore, as the insulator 462, it is preferable to use an insulator having a barrier property against impurities such as water and hydrogen, similar to the insulator 324, for example.

[0320] Further, above the insulator 462, layers OSL[2] (not shown) to layer OSL[p] are provided, and the layers OSL[2] to layer OSL[p] can be manufactured by the same process as the layer OSL[1]. For this reason, the insulator 462 may be formed of the same material as the insulator 510. Also, by manufacturing the layers OSL[2] to layer OSL[p] by the same process as the layer OSL[1], memory cell arrays MCA included in the layer OSL[2] to layer OSL[p] can be stacked above the memory cell array MCA included in the layer OSL[1], for example. In other words, memory cells 600 included in the layers OSL[2] to layer OSL[p] can be stacked above the memory cell 600 included in the layer OSL[1]. Note that the configuration example of the storage device MDV shown in FIG. 7 can be applied to the storage device MDV of FIG. 1B.

[0321] Note that FIG. 7 shows a configuration example of the storage device MDV with the memory cell 600 being the memory cell MC of FIG. 3A, but one aspect of the present invention is not limited to this.

[0322] For example, the storage device MDV may be configured with the memory cell 600 being the memory cell MC of FIG. 3C. FIG. 9 shows the configuration of the storage device MDV with the memory cell 600 being the memory cell MC of FIG. 3C.

[0323] Specifically, in the memory device MDV of FIG. 9, the transistor 500A corresponds to the transistor M4 in FIG. 3C, the transistor 500B corresponds to the transistor M3, and the memory element 400 corresponds to the resistive change device MD.

[0324] Incidentally, in the memory device MDV of FIG. 9, the transistor 500A and the transistor 500B are formed so as to share the insulator 524, the oxide 530a, the oxide 530b, and one of the conductors 542a or 542b with each other. And, two openings reaching the oxide 530 are provided in the insulator 580 and the conductor 542, and the oxide 530c, the insulator 550, and the conductor 560 are provided in each opening. Thereby, the first terminal of the transistor 500A and the first terminal of the transistor 500B can be provided in a configuration that shares one of the conductors 542a or 542b with each other. In addition, the area in which the transistor 500A and the transistor 500B are formed can be made smaller than the area in which the transistor 500A and the transistor 500B are formed separately. Thereby, since the area for forming the memory cell 600 can be made smaller, the area per bit as the bit density can be made smaller.

[0325] In the memory device MDV of FIG. 9, the first terminal of the transistor 500A is electrically connected to the first terminal of the transistor 500B, the second terminal of the transistor 500B is electrically connected to the first terminal of the memory element 400, and the second terminal of the memory element 400 is electrically connected to the second terminal of the transistor 500A.

[0326] Note that the wiring SL in FIG. 3C can be, for example, the conductor 450 that is electrically connected to the first terminal of the transistor 500A and the first terminal of the transistor 500B. Also, the wiring BL in FIG. 3C can be, for example, the conductor 450 that is electrically connected between the second terminal of the transistor 500B and the memory element 400.

[0327] Further, the wiring WLa in FIG. 3C can be, for example, the conductor 560 corresponding to the gate of the transistor 500B. Also, the wiring WLb in FIG. 3C can be, for example, the conductor 560 corresponding to the gate of the transistor 500A.

[0328] Also, for example, the memory cell 600 may be used as the memory cell MC in FIGS. 6A to 6C to configure the memory device MDV. FIG. 10 shows the configuration of the memory device MDV using the memory cell 600 as the memory cell MC in FIGS. 6A to 6C.

[0329] Specifically, in the memory device MDV of FIG. 10, the transistor 500A corresponds to the transistor M10 in FIGS. 6A to 6C, and the memory element 400 corresponds to the MTJ element in FIG. 6A, the resistance change element RM in FIG. 6B, the phase change memory PCM1 in FIG. 6C, and the like. Therefore, in the memory device MDV of FIG. 10, the first terminal of the transistor 500A is electrically connected to the first terminal of the memory element 400.

[0330] Note that the wiring SL in FIGS. 6A to 6C can be, for example, the conductor 450 electrically connected to the second terminal of the transistor 500A. Also, the wiring BL in FIGS. 6A to 6C can be, for example, the conductor 460 electrically connected to the second terminal of the memory element 400. Also, the wiring WL in FIGS. 6A to 6C can be, for example, the conductor 560 electrically connected to the gate of the transistor 500A.

[0331] Note that the configuration of the memory element 400 is different for each memory cell MC in FIGS. 6A to 6C. Therefore, in the memory device MDV of FIG. 10, the location where the memory element 400 is formed is indicated by vertical hatching. Also, in FIG. 10, the insulator 452 is provided on the side surface of the memory element 400, but depending on the configuration of the memory element 400, the insulator 452 may not be provided on the side surface of the memory element 400.

[0332] By applying the above configuration as a memory device, a memory device with low power consumption can be provided. Or, a memory device with a large memory capacity can be provided. Or, a novel memory device can be provided.

[0333] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0334] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0335] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0336] <Classification of crystal structures> First, the classification of crystal structures in the oxide semiconductor will be described with reference to FIG. 11A. FIG. 11A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0337] As shown in FIG. 11A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Also, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0338] Note that the structure within the thick frame shown in FIG. 11A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is completely different from the energetically unstable "Amorphous" and "Crystal".

[0339] Incidentally, the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained from the grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 11B (the vertical axis represents the intensity in arbitrary units (a.u.)). Note that the GIXD method is also referred to as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained from the GIXD measurement shown in Fig. 11B may be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 11B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 11B is 500 nm.

[0340] As shown in Fig. 11B, peaks indicating distinct crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in Fig. 11B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0341] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Fig. 11C. Fig. 11C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in Fig. 11C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0342] As shown in Fig. 11C, a plurality of spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0343] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 11A. For example, the oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, the non-single-crystalline oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0344] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0345] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axis of the plurality of crystal regions is oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. In addition, the crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in the region where the plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0346] Note that each of the above-mentioned plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. In addition, when the crystal region is composed of a large number of minute crystals, the size of the crystal region may be about several tens of nm.

[0347] Also, in an In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0348] When a structural analysis is performed on a CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in the vicinity thereof. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0349] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0350] When observing the crystal region from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be an irregular hexagon. Further, in the above-mentioned strain, there may be a lattice arrangement such as a pentagon or a heptagon. In CAAC-OS, even in the vicinity of the strain, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is considered to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0351] A crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries serve as recombination centers, and carriers are likely to be trapped, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. In addition, for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0352] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundary confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is unlikely to occur. In addition, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities and the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiency). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. Therefore, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. In addition, CAAC-OS is also stable against a high temperature (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, it is possible to expand the degree of freedom in the manufacturing process.

[0353] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and an amorphous oxide semiconductor. For example, when performing structural analysis on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scan. Further, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0354] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film than nc-OS and CAAC-OS.

[0355] <<Constitution of Oxide Semiconductor>> Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0356] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0357] Furthermore, CAC-OS is a composite metal oxide having a structure in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0358] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0359] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. The above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. The above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0360] Note that there may be cases where no clear boundary can be observed between the above-described first region and the second region.

[0361] For example, in CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0362] When CAC-OS is used in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, thereby enabling the function of switching (the function of turning on / off) to be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0363] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0364] <Transistor having an oxide semiconductor> Subsequently, the case where the above-described oxide semiconductor is used in a transistor will be described.

[0365] By using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0366] For the transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 or less, and 1×10 -9 cm -3 or more. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0367] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0368] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is long, and it may behave as if it were a fixed charge. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may become unstable.

[0369] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0370] <Impurity> Here, the effects of various impurities in the oxide semiconductor will be described.

[0371] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0372] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0373] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the oxide semiconductor obtained by SIMS is 5×10 19 atoms / cm 3 less than, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0374] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 or less.

[0375] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0376] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0377] (Embodiment 4) This embodiment shows an example of a semiconductor wafer on which a storage device or the like is formed, and an example of an electronic component in which the storage device is incorporated.

[0378] <Semiconductor wafer> First, an example of a semiconductor wafer on which a storage device or the like is formed will be described with reference to FIG. 12A.

[0379] The semiconductor wafer 4800 shown in FIG. 12A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion where no circuit portion 4802 is provided is a spacing 4803, which is a dicing region.

[0380] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warping of the wafer 4801 or the like can be reduced, and miniaturization as a component can be achieved.

[0381] As the next process, a dicing process is performed. Dicing is performed along scribe lines SCL1 and SCL2 (which may be referred to as dicing lines or cutting lines) indicated by dashed lines. Note that the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel to each other, a plurality of scribe lines SCL2 are parallel to each other, and the scribe line SCL1 and the scribe line SCL2 are perpendicular to each other in order to facilitate the dicing process.

[0382] By performing a dicing process, a chip 4800a as shown in FIG. 12B can be cut out from a semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately the same length as the scribe width of the scribe line SCL1 or the scribe width of the scribe line SCL2.

[0383] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 12A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0384] <Electronic component> FIG. 12C shows a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 12C has a chip 4800a inside a mold 4711. Note that the chip 4800a shown in FIG. 12C shows a configuration in which circuit portions 4802 are stacked. That is, as the circuit portion 4802, the storage device described in the above embodiment can be applied. FIG. 12C omits a part to show the inside of the electronic component 4700. The electronic component 4700 has lands 4712 outside the mold 4711. The lands 4712 are electrically connected to electrode pads 4713, and the electrode pads 4713 are electrically connected to the chip 4800a by wires 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined, and each is electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0385] FIG. 12D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). On the package substrate 4732 (printed circuit board), an interposer 4731 is provided, and on the interposer 4731, a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided.

[0386] The electronic component 4730 includes the semiconductor device 4710. As the semiconductor device 4710, for example, the storage device, the wideband memory (HBM: High Bandwidth Memory), etc. described in the above embodiment can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0387] As the package substrate 4732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used. As the interposer 4731, a silicon interposer, a resin interposer, etc. can be used.

[0388] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or a multilayer. Further, the interposer 4731 has a function of electrically connecting the integrated circuit provided on the interposer 4731 to the electrode provided on the package substrate 4732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate". Further, through electrodes may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrodes. In the case of a silicon interposer, TSV (Through Silicon Via) can also be used as the through electrode.

[0389] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since wiring formation of a silicon interposer can be performed by a semiconductor process, formation of fine wiring, which is difficult in a resin interposer, is easy.

[0390] In HBM, many wirings need to be connected to realize a wide memory bandwidth. Therefore, a fine and high-density wiring formation is required for the interposer on which HBM is mounted. Thus, it is preferable to use a silicon interposer for the interposer on which HBM is mounted.

[0391] Also, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to a difference in the coefficient of thermal expansion between the integrated circuit and the interposer hardly occurs. Also, since the silicon interposer has high flatness on its surface, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer hardly occurs. In particular, in a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0392] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 4710 and the semiconductor device 4735 uniform.

[0393] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. In FIG. 12D, an example of forming the electrodes 4733 with solder balls is shown. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed with conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0394] The electronic component 4730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0395] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0396] (Embodiment 5) In this embodiment, a CPU including the storage device of the above embodiment will be described.

[0397] FIG. 13 is a block diagram showing a configuration example of a CPU that partially uses the storage device described in the above embodiment.

[0398] The CPU shown in FIG. 13 has, on a substrate 1190, an ALU 1191 (ALU: Arithmetic Logic Unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 13 is merely an example shown with its configuration simplified, and an actual CPU has various configurations depending on its use. For example, a configuration including the CPU or arithmetic circuit shown in FIG. 13 may be regarded as one core, and a configuration including a plurality of such cores operating in parallel, that is, a configuration such as a GPU, may be adopted. Also, the number of bits that the CPU can handle with its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0399] Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

[0400] The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. Also, the interrupt controller 1194, during program execution of the CPU, judges and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priorities, mask states, etc. The register controller 1197 generates addresses of the register 1196 and reads from and writes to the register 1196 according to the state of the CPU.

[0401] Also, the timing controller 1195 generates signals for controlling the operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0402] In the CPU shown in FIG. 13, memory cells are provided in the register 1196. The register 1196 may have, for example, a storage device shown in the previous embodiment.

[0403] In the CPU shown in FIG. 13, the register controller 1197 selects the holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the memory cells included in the register 1196, it is selected whether to hold data by a flip-flop or to hold data by a capacitive element. When holding data by a flip-flop is selected, a power supply voltage is supplied to the memory cells in the register 1196. When holding data by a capacitive element is selected, data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cells in the register 1196 can be stopped.

[0404] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0405] (Embodiment 6) In this embodiment, an example of an electronic device having the storage device described in the above embodiment will be described. FIGS. 14A to 14J and FIGS. 15A to 15E illustrate a state in which an electronic component 4700 having the storage device is included in each electronic device.

[0406] [Mobile phone] The information terminal 5500 shown in FIG. 14A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0407] By applying the storage device described in the above embodiment, the information terminal 5500 can hold temporary files (for example, caches when using a web browser, etc.) generated during the execution of an application.

[0408] [Wearable Terminal] Also, FIG. 14B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 has a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc.

[0409] Similar to the information terminal 5500 described above, the wearable terminal can hold temporary files generated during the execution of an application by applying the storage device described in the above embodiment.

[0410] [Information Terminal] Also, FIG. 14C shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0411] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the storage device described in the above embodiment.

[0412] In the above description, smartphones, wearable terminals, and desktop information terminals are taken as examples of electronic devices and are illustrated in FIGS. 14A to 14C respectively. However, information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0413] [Electrical Appliance] In addition, FIG. 14D shows an electric refrigerator 5800 as an example of an electrical appliance. The electric refrigerator 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0414] By applying the storage device described in the above embodiment to the electric refrigerator 5800, the electric refrigerator 5800 can be used, for example, as an IoT (Internet of Things). By using the IoT, the electric refrigerator 5800 can transmit and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of the food to and from information terminals as described above through the Internet or the like. Also, when transmitting the information, the electric refrigerator 5800 can hold the information as a temporary file in the storage device.

[0415] In this example, an electric refrigerator is described as an electrical appliance. Other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual devices, and the like.

[0416] [Game Machine] In addition, FIG. 14E shows a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0417] Furthermore, FIG. 14F shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 14F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a slide knob, and the like. Also, the controller 7522 is not limited to the shape shown in FIG. 14F, and the shape of the controller 7522 may be variously changed according to the genre of the game. For example, in a shooting game such as a first-person shooter (FPS), a controller in the shape of a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller in the shape of a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to operate by the gestures and / or voices of the game player, without using a controller, but instead equipped with a camera, a depth sensor, a microphone, and the like.

[0418] In addition, the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, or a head-mounted display.

[0419] By applying the storage device described in the above embodiment to the portable game machine 5200 and the stationary game machine 7500, a portable game machine 5200 with low power consumption can be realized. Also, since the heat generation from the circuit can be reduced due to the low power consumption, the influence on the circuit itself, the peripheral circuits, and the modules caused by the heat generation can be minimized.

[0420] Furthermore, by applying the storage device described in the above embodiment to the portable game machine 5200 and the stationary game machine 7500, it is possible to hold temporary files and the like necessary for the operations that occur during the execution of the game.

[0421] In FIGS. 14E and 14F, a portable game machine and a stationary game machine are illustrated as examples of a game machine, but the electronic device according to one aspect of the present invention is not limited thereto. Examples of the electronic device according to one aspect of the present invention include, for example, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), a pitching machine for batting practice installed in a sports facility, and the like.

[0422] [Mobile body] The storage device described in the above embodiment can be applied to an automobile, which is a mobile body, and the periphery of the driver's seat of the automobile.

[0423] FIG. 14G shows an automobile 5700, which is an example of a mobile body.

[0424] Around the driver's seat of the automobile 5700, there is an instrument panel that provides various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. Further, a display device for indicating such information may be provided around the driver's seat.

[0425] In particular, the display device can project an image from an imaging device (not shown) provided in the automobile 5700 to supplement a field of view blocked by a pillar or a blind spot of the driver's seat, thereby enhancing safety.

[0426] Since the storage device described in the above embodiment can temporarily hold information, for example, the storage device can be used to hold necessary temporary information in an automatic driving system of the automobile 5700, a system for performing road guidance, danger prediction, and the like. Further, the display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold an image of a driving recorder provided in the automobile 5700.

[0427] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc.

[0428] [Camera] The storage device described in the above embodiment can be applied to a camera.

[0429] FIG. 14H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Also, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0430] By applying the storage device described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence of the heat on the circuit itself, the peripheral circuits, and the modules can be minimized.

[0431] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0432] FIG. 14I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0433] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the storage device described above, the video camera 6300 can hold temporary files generated during encoding.

[0434] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0435] FIG. 14(J) is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0436] The ICD body 5400 is implanted into the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0437] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia, ventricular fibrillation, etc.), treatment by electric shock is performed.

[0438] In order for the ICD main body 5400 to perform pacing and electric shock appropriately, it is necessary to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate obtained by the sensor, etc., the number of times and time of treatment by pacing, etc. in the electronic component 4700.

[0439] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, by having a plurality of batteries in the ICD main body 5400, the safety can be enhanced. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0440] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activity may be configured such that physiological signals such as pulse, respiration rate, heart rate, body temperature, etc. can be confirmed by an external monitor device.

[0441] [Expansion device for PC] The storage device described in the above embodiment can be applied to a computer such as a PC (Personal Computer) or an expansion device for an information terminal.

[0442] FIG. 15A shows an expansion device 6100 that can be carried and is externally attached to a PC and equipped with a chip capable of storing information as an example of the expansion device. The expansion device 6100 can store information by the chip by being connected to the PC via, for example, a USB (Universal Serial Bus). Note that FIG. 15A illustrates the expansion device 6100 in a portable form, but the expansion device according to an aspect of the present invention is not limited thereto, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.

[0443] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. A circuit for driving the storage device and the like described in the above embodiment is provided on the substrate 6104. For example, an electronic component 4700 and a controller chip 6106 are attached to the substrate 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0444] [SD card] The storage device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0445] FIG. 15B is a schematic diagram of the appearance of an SD card, and FIG. 15C is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, a writing circuit, a loader, a reading circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 4700.

[0446] By providing the electronic component 4700 also on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Thereby, wireless communication can be performed between the external device and the SD card 5110, and data of the electronic component 4700 can be read and written.

[0447] [SSD] The storage device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0448] FIG. 15D is a schematic diagram of the appearance of the SSD, and FIG. 15E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 4700, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. By providing the electronic component 4700 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used for the memory chip 5155. A processor, an ECC circuit, etc. are incorporated in the controller chip 5156. Note that the circuit configurations of each of the electronic component 4700, the memory chip 5155, and the controller chip 5156 are not limited to the above description, and the circuit configuration may be appropriately changed according to the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0449] By applying the storage device of Embodiment 1 or Embodiment 2 to the storage device included in the above-described electronic device, a novel electronic device can be provided.

[0450] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

Description of Reference Numerals

[0451] MDV: Memory device, MCA: Memory cell array, MCA[1]: Memory cell array, MCA[p - 1]: Memory cell array, MCA[p]: Memory cell array, PHL: Peripheral circuit, MC: Memory cell, MC[1,1]: Memory cell, MC[m,1]: Memory cell, MC[1,n]: Memory cell, MC[m,n]: Memory cell, BD: Circuit, WD: Circuit, SD: Circuit, RBD: Circuit, CLC: Circuit, OPC: Circuit, M1: Transistor, M2: Transistor, M3: Transistor, M4: Transistor, M10: Transistor, MD: Resistance change device, ME: MTJ element, RM: Resistance change element, PCM1: Phase change memory, IT1: Terminal, IT2: Terminal, OT: Terminal, BL1: Wiring, BL1[1]: Wiring, BL1[n]: Wiring, BL2: Wiring, BL2[1]: Wiring, BL2[n]: Wiring, WL: Wiring, WLa: Wiring, WLa[1]: Wiring, WLa[m]: Wiring, WLb: Wiring, WLb[1]: Wiring, WLb[m]: Wiring, WL[1]: Wiring, WL[m]: Wiring, RBL: Wiring, RBL[1]: Wiring, RBL[m]: Wiring, SL[1]: Wiring, SL[m]: Wiring, BGE: Wiring, RL: Layer, TIS: Layer, FL: Layer, CA: Layer, TE: Electrode, CHL: Phase change layer, BE: Electrode, SIL: Layer, OSL[1]: Layer, OSL[p]: Layer, 300: Transistor, 310: Substrate, 312: Element isolation layer, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 400: Memory element, 401: Conductor, 402: Insulator, 403: Conductor, 404: Conductor, 450: Conductor, 452: Insulator, 454: Insulator, 456: Insulator, 457: Conductor, 458: Conductor, 459: Insulator, 460: Conductor, 462: Insulator, 500A: Transistor, 500B: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 510: Insulator, 512: Insulator, 513: Insulator, 514: Insulator, 516: Insulator, 518: Conductor, 520: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide,530c: Oxide, 540a: Conductor, 540b: Conductor, 542: Conductor, 542a: Conductor, 542b: Conductor, 543a: Region, 543b: Region, 544: Insulator, 546: Conductor, 550: Insulator, 552: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 574: Insulator, 576: Insulator, 580: Insulator, 581: Insulator, 582: Insulator, 586: Insulator, 600: Memory Cell, 1189: ROM Interface, 1190: Substrate, 1191: ALU, 1192: ALU Controller, 1193: Instruction Decoder, 1194: Interrupt Controller, 1195: Timing Controller, 1196: Register, 1197: Register Controller, 1198: Bus Interface, 2621: Loader, 2622: Word Line Driver Circuit, 2630: Bit Line Driver Circuit, 2631: Column Decoder, 2632: Precharge Circuit, 2633: Sense Amp, 2634: Write Circuit, 2640: Output Circuit, 2660: Control Logic Circuit, 4700: Electronic Component, 4702: Printed Circuit Board, 4704: Mounting Substrate, 4710: Semiconductor Device, 4714: Wire, 4730: Electronic Component, 4731: Interposer, 4732: Package Substrate, 4733: Electrode, 4735: Semiconductor Device, 4800: Semiconductor Wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit Section, 4803: Spacing, 4803a: Spacing, 5110: SD Card, 5111: Housing, 5112: Connector, 5113: Substrate, 5115: Controller Chip, 5150: SSD, 5151: Housing, 5152: Connector, 5153: Substrate, 5155: Memory Chip, 5156: Controller Chip, 5200: Portable Game Console, 5201: Housing, 5202: Display Unit, 5203: Button, 5300: Desktop Information Terminal, 5301: Main Body, 5302: Display, 5303: Keyboard, 5400: ICD Main Body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian Vein, 5406: Superior Vena Cava, 5500: Information Terminal, 5510: Housing, 5511: Display Unit, 5700: Automobile, 5800: Electric Refrigerator-Freezer, 5801: Housing, 5802: Refrigerator Door, 5803: Freezer Door, 5900: Information Terminal,5901: Housing, 5902: Display section, 5903: Operation button, 5904: Operator, 5905: Band, 6100: Expansion device, 6101: Housing, 6102: Cap, 6103: USB connector, 6104: Substrate, 6106: Controller chip, 6240: Digital camera, 6241: Housing, 6242: Display section, 6243: Operation button, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display section, 6304: Operation key, 6305: Lens, 6306: Connection section, 7520: Main body, 7522: Controller

Claims

1. having a first layer and a second layer overlapping the first layer, wherein the first layer has a circuit, the second layer has a first memory cell, the circuit has a bit line driver circuit and / or a word line driver circuit for transmitting a signal to the first memory cell, the first memory cell has a first transistor, a second transistor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and an MTJ element, the first conductor and the second conductor contain tungsten or tantalum as a main component, each of the first conductor, the second conductor, the third conductor, and the fourth conductor is arranged to contact an upper surface of an insulator, the MTJ element has a free layer, the free layer is electrically connected to the first conductor, a first terminal of the first transistor is electrically connected to a first terminal of the second transistor via the first conductor, a second terminal of the first transistor is electrically connected to the third conductor having a function as a write bit line, a second terminal of the second transistor is electrically connected to the fourth conductor having a function as a wiring to which a constant voltage is applied, a fixed layer of the MTJ element is electrically connected to the fifth conductor having a function as a read bit line, the fifth conductor has a region intersecting each of the third conductor and the fourth conductor, the circuit has a third transistor in which silicon is included in a channel formation region, each of the first transistor and the second transistor includes a metal oxide in a channel formation region, the first transistor or the second transistor is electrically connected to the third transistor via the second conductor, a memory device.

2. having a first layer and a second layer overlapping the first layer, wherein the first layer has a circuit, the second layer has a first memory cell, the circuit has a bit line driver circuit and / or a word line driver circuit for transmitting a signal to the first memory cell, the first memory cell has a first transistor, a second transistor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, and an MTJ element, the first conductor and the second conductor contain tungsten or tantalum as a main component, Each of the first conductor, the second conductor, the third conductor, and the fourth conductor is arranged to contact the upper surface of one insulator. The MTJ element has a free layer. The free layer has a region that contacts the upper surface of the first conductor. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor via the first conductor. The second terminal of the first transistor is electrically connected to the third conductor that functions as a write bit line. The second terminal of the second transistor is electrically connected to the fourth conductor that functions as a wiring to which a constant voltage is applied. The fixed layer of the MTJ element is electrically connected to the fifth conductor that functions as a read bit line. The fifth conductor has a region that intersects each of the third conductor and the fourth conductor. The circuit has a third transistor in which silicon is included in a channel formation region. Each of the first transistor and the second transistor includes a metal oxide in a channel formation region. The first transistor or the second transistor is electrically connected to the third transistor via the second conductor. Memory device.

3. In claim 1 or claim 2, having a third layer, the third layer has a second memory cell, the third layer is laminated on the second layer. Memory device.

4. An electronic device having any one of the memory devices according to claims 1 to 3 and a housing. Electronic device.

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