Control System and Method for a Voltage-Adjustable Multilayer Capacitor

Abstract

To provide a controller and a system for adjusting a voltage-adjustable capacitor.SOLUTION: A system includes a voltage-adjustable capacitor and a controller for adjusting the capacitor. In the system, a controller 200 includes: at least one analog-digital converters A / D 1 to A / D N that receive at least one input signal and convert at least one input signal 204, 210 into at least one digital signal; a processor 216 that generates an output signal 217 by processing the at least one digital signal using a logic; and a charge pump 218 that generates a boosted output signal 219 by raising a voltage of the output signal. For adjusting a bias voltage VBIAS of the voltage-adjustable capacitor, the boosted output signal is supplied to the voltage-adjustable capacitor.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Cross - References to Related Applications

[0001] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 62 / 784,879, filed Dec. 26, 2018. By this reference to this patent application, the entire content thereof is hereby incorporated into this application. Prior Art

[0002]

[0002] Tunable capacitors based on the variable dielectric properties of dielectrics have been proposed for various applications. In such capacitors, typically, the capacitance at zero bias is near its maximum value and the capacitance decreases with the application of voltage. Due to this capacitance change, these units can be used to create tunable circuits in filters, matching networks, resonant circuits, and other applications from audible frequencies to RF and microwave frequencies. Despite these advantages, the use of such capacitors is relatively limited because, for one reason, the capacitance values achieved even at high power and voltage levels are relatively low. Furthermore, a control system and method for voltage - tunable multilayer capacitors would be advantageous for circuits employing voltage - tunable multilayer capacitors.

Summary of the Invention

Problems to be Solved by the Invention

[0003]

[0003] An exemplary embodiment of the present disclosure is directed to a controller for adjusting a voltage-adjustable capacitor. The controller can include at least one digital / analog converter configured to receive at least one input signal and convert the at least one input signal into at least one digital signal. The controller can include a processor configured to process the at least one digital signal using logic and generate an output signal. The controller can include a charge pump configured to boost the output signal and generate a boosted output signal. The controller can be configured to supply the boosted output signal to a voltage-adjustable capacitor to adjust a bias voltage of the voltage-adjustable capacitor.

[0004]

[0004] These and other features, aspects, and advantages of the various embodiments will be further understood by reference to the following description and the appended claims. The accompanying drawings, which are incorporated herein and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the related principles.

[0005]

[0005] In the remaining part of this specification, reference is made to the accompanying drawings, and the best mode, including all aspects of the invention and its practical implementation, will be described in more detail for those skilled in the art.

Brief Description of the Drawings

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007]

[0030] When reference numerals are repeatedly used throughout this specification and the accompanying drawings, it is intended to represent the same or similar structures, elements, or steps.

[0008]

[0031] This description is merely an illustration of exemplary embodiments and is not intended to limit the broader aspects of the present invention. It should be understood by those skilled in the art that the broader aspects may be embodied in exemplary structures.

[0009]

[0032] Generally speaking, the present disclosure is directed to a regulation system and method for a voltage - adjustable capacitor. The voltage - adjustable capacitor can be configured for a relatively high operating voltage. In some embodiments, the controller can be configured to adjust the voltage - adjustable capacitor based on one or more input signals having a relatively low voltage. That is, this controller can enable the implementation of a voltage - adjustable capacitor in a circuit where it is difficult or impractical to supply a high - voltage input signal and / or a bias voltage. This controller may enable the voltage - adjustable capacitor to be employed in a wider variety of applications, including those involving relatively high voltages.

[0010]

[0033] In some embodiments, the controller can include at least one analog - to - digital converter configured to receive at least one input signal and convert the at least one input signal into at least one digital signal. The controller can include a processor configured to process the at least one digital signal using logic that generates an output signal. The controller can include a charge pump configured to boost the output signal to generate a boosted output signal. The controller can be configured to supply the boosted output signal to the voltage - adjustable capacitor to adjust the bias voltage of the voltage - adjustable capacitor.

[0011]

[0034] In some embodiments, the boost output signal can adjust the capacitance of a voltage-adjustable capacitor. For example, the controller can supply a boost output signal ranging from about 0 volts to at least about 500 volts, in some embodiments at least about 300 volts, in some embodiments at least about 200 volts, in some embodiments at least about 100 volts, in some embodiments at least about 70 volts, in some embodiments at least about 50 volts, in some embodiments at least about 30 volts, and in some embodiments at least about 20 volts.

[0012]

[0035] In some embodiments, the input signal(s) can include various suitable signals. By way of example, the input signal(s) can indicate the voltage, current, capacitance, temperature, and / or other suitable parameters associated with a voltage-adjustable capacitor. As an example, the input signal(s) may indicate the capacitance of a voltage-adjustable capacitor (e.g., for performing closed-loop control with respect to the capacitance of a voltage-adjustable capacitor).

[0013]

[0036] In some embodiments, the input signal(s) can also indicate the voltage, current, capacitance, temperature, and / or other suitable parameters associated with a circuit including a voltage-adjustable capacitor, a circuit connected to or associated with a voltage-adjustable capacitor otherwise. By way of example, the input signal(s) can also indicate the temperature of a component (e.g., a heat sink or other temperature-sensitive component) of a circuit associated with a voltage-adjustable capacitor. As another example, the input signal(s) can indicate the desired output voltage or current of a circuit.

[0014]

[0037] The input signal(s) can range from about 0 volts to at least about 20 volts, in some embodiments at least about 15 volts, in some embodiments at least about 10 volts, in some embodiments at least about 7 volts, in some embodiments at least about 5 volts, and in some embodiments at least about 3 volts.

[0015]

[0038] The upper limit of the bias voltage of the voltage adjustable capacitor is the upper limit of the input signal voltage. The ratio may range from about 1 to about 500 or more, in some embodiments from about 1 to about 250, in some embodiments from about 1 to about 150, in some embodiments from about 1 to about 100, in some embodiments from about 1 to about 75, in some embodiments from about 1 to about 50, in some embodiments from about 1 to about 20, in some embodiments from about 1 to about 10, and in some embodiments from about 1 to about 5.

[0016]

[0039] In some embodiments, the input signal(s) may also represent a manual control signal indicative of a desired capacitance associated with the voltage-adjustable capacitor, or a desired voltage associated with the voltage-adjustable capacitor. The manual control signal may range from about 0 volts to at least about 3 volts, in some embodiments from about 0 volts to at least about 2 volts, in some embodiments from about 0 volts to at least about 1 volt, from about 0 volts to at least about 0.5 volts, and in some embodiments from about 0 volts to at least about 0.1 volts.

[0017]

[0040] The ratio of the upper limit of the bias voltage of the voltage adjustable capacitor to the upper limit of the manual control signal can range from about 1 to about 500 or more, in some embodiments from about 1 to about 250, in some embodiments from about 1 to about 150, in some embodiments from about 1 to about 100, in some embodiments from about 1 to about 75, in some embodiments from about 1 to about 50, in some embodiments from about 1 to about 20, in some embodiments from about 1 to about 16, and in some embodiments from about 1 to about 10.

[0018]

[0041] In one embodiment, one or more components of a system for controlling a voltage adjustable capacitor may be incorporated within a monolithic device. For example, a controller may be encapsulated within a molding material or packaging material to form the monolithic device. In one embodiment, an analog / digital converter(s) and / or a charge pump may be incorporated within the monolithic device. The monolithic device may include external terminals for electrically connecting the controller and the adjustable capacitor to the voltage adjustable capacitor and / or other electrical components. The monolithic device may also be configured to be surface-mounted on a printed circuit board.

[0019]

[0042] The charge pump may be any suitable form of a voltage boosting device (e.g., a DC / DC converter). For example, the charge pump may employ rapid switching of an alternating current to generate a boosted output signal. The charge pump may not require an inductor. The boosted output signal of the charge pump may be positively correlated with the DC voltage received by the charge pump. In other words, the charge pump may be configured to boost the DC voltage received by the charge pump according to a linear gain and / or a non-decreasing function. For example, the charge pump may be configured to boost the DC voltage received by the charge pump by a factor of two or more than a gain of two (e.g., a "doubling" charge pump), in one embodiment by a factor of four or more, in one embodiment by a factor of eight or more, and in one embodiment by a factor of sixteen or more. ductor may not be required. The boosted output signal of the charge pump may be positively correlated with the DC voltage received by the charge pump. In other words, the charge pump may be configured to boost the DC voltage received by the charge pump according to a linear gain and / or a non-decreasing function. For example, the charge pump may be configured to boost the DC voltage received by the charge pump by a factor of two or more than a gain of two (e.g., a "doubling" charge pump), in one embodiment by a factor of four or more, in one embodiment by a factor of eight or more, and in one embodiment by a factor of sixteen or more.

[0020]

[0043] Aspects of the present disclosure are directed to a system for adjusting a voltage - adjustable capacitor. The system can include one or more control devices (e.g., one or more controllers). The control device(s) can include a charge pump. The system can include a voltage - adjustable capacitor that includes a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes. At least a portion of the dielectric layer can contain an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage. The control device(s) can be configured to receive at least one input signal. The control device(s) can be configured to use logic to process the input signal(s) to generate an output signal. The control device(s) can be configured to use a charge pump to boost the output signal. The control device(s) can be configured to supply the boosted output signal to the voltage - adjustable capacitor to adjust a bias voltage applied across the ends of the plurality of bias electrodes.

[0021]

[0044] The voltage - adjustable capacitor can be, or include, a multilayer capacitor. The multilayer voltage - adjustable capacitor includes a plurality of dielectric layers sandwiched between alternating active electrode layers. At least a portion of the dielectric layer can include an adjustable material that exhibits a variable dielectric constant upon application of an applied voltage. More specifically, such a material typically has a "voltage tunability coefficient" in the range of about 10% to about 90%, in certain embodiments about 20% to about 80%, and in certain embodiments about 30% to about 70%, and the "voltage tunability coefficient" is determined according to the following general formula. T = 100 x (ε0 - ε V ) / ε0 where T is the voltage tunability coefficient, ε0 is the static dielectric constant of the material when no voltage is applied, ε v is the variable dielectric constant of the material after applying an applied voltage (DC).

[0022]

[0045] The static dielectric constant of the material is, when determined according to ASTM D2149-13 at an operating temperature (e.g., 25°C) ranging from about -55°C to about 150°C and a frequency (e.g., 1 kHz) ranging from about 100 Hz to about 1 GHz, as such, generally ranges from about 100 to about 25,000, in certain embodiments from about 200 to about 10,000, and in certain embodiments from about 500 to about 9,000. Of course, the specific value of the static dielectric constant is generally to be understood as being selected based on the individual application in which the capacitor is employed. The higher the applied DC bias, the more the dielectric constant generally decreases within the range described above. The adjustment voltage applied to induce a desired change in the dielectric constant can generally vary compared to the voltage at which the dielectric composition begins to become conductive upon application of an electric field (the "breakdown voltage"). The breakdown voltage can be determined according to ASTM D149-13 at a temperature of 25°C to be. In most embodiments, the maximum applied DC bias voltage is about 50% or less of the breakdown voltage of the dielectric composition, in certain embodiments about 30% or less, and in certain embodiments from about 0.5% to about 10%.

[0023]

[0046] Any of a variety of tunable dielectric materials may generally be employed, as is known in the art. Particularly suitable materials are dielectrics that include one or more ferroelectric fundamental phases in their base composition, such as perovskites, tungsten copper materials (e.g., sodium barium niobate), and layered structure materials (e.g., bismuth titanate). Illustratively, suitable perovskites may include barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc. In one particular embodiment, illustratively, a perovskite having the chemical formula Ba x Sr 1-x Barium strontium titanate ("BSTO") of TiO3 may be employed, where x is from 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other electronically tunable dielectric materials may be used in place of barium strontium titanate, either in part or in whole. Illustratively, one example is Ba x Ca 1-x TiO3, where x is from about 0.2 to about 0.8, and in some embodiments In some cases, the ZnO content is about 0.4 to about 0.6. Other suitable perovskites include Pb x Zr 1-x TiO3 ("PZT"), where x ranges from about 0.05 to about 0.4, may include lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3), and NaBa2(NbO3)5KHb2PO4. Still other complex perovskites include A[B1 1 / 3 B2 2 / 3 ]O3 material, where A is Ba x Sr1-x (x can range from 0 to 1), and B1 is Mg y Zinc 1-y (y can range from 0 to 1), B2 is Ta z Nb 1-z (z can range from 0 to 1). Potential dielectric materials of interest can be formed by combining two endmember compositions in alternating layers, as shown in the exemplary embodiment of FIG. 14. Such endmember compositions are chemically similar but may have different ratios of A-site dopants, as discussed above. For example, compound 1 (132 in FIG. 14) has the general formula (A1 x ,A2( 1-x Compound 2 (134) may be a perovskite compound of the general formula (A1 y , A2 (1-y ))BO3 perovskite, where A1 and A2 are selected from Ba, Sr, Mg, and Ca. Potential B-site components are Zr, Ti, and Sn, with "x" and "y" being the mole fractions of each component. An example of compound 1 is (Ba 0. 8Sr 0.2 )TiO3, and compound 2 may be (Ba 0.6 Sr 0.4 )TiO3. These two compounds can be combined in alternating layers in a stacked capacitor sintered with a tunable electrode structure, as shown in FIG. 14, so that the dielectric properties of each material are superimposed. If desired, the perovskite material can also be doped with rare earth oxides ("REO"), in amounts up to 5.0 mole percent, and more preferably from 0.1 to 1 mole percent. Rare earth oxides suitable for this purpose include The dopants may include, by way of example only, scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0024]

[0047] A tunable dielectric material can enable the capacitance adjustment of the resulting capacitor by applying a DC bias voltage through a bias terminal. More specifically, the capacitor includes a set of first active electrodes that are in electrical contact with a first active terminal (e.g., an input terminal), and a set of second active electrodes that are in electrical contact with a second active terminal (e.g., an output terminal). Also, this capacitor includes a set of first DC bias electrodes that are in electrical contact with a first DC bias terminal, and a set of second DC bias electrodes that are in electrical contact with a second DC bias terminal. When provided in a circuit, a DC power source (e.g., a battery, a constant voltage power source, a multi-output power source, a DC / DC converter, etc.) can supply a DC bias to the capacitor through the first and second bias terminals. This is typically bipolar since the first and second bias terminals have opposite polarities. The electrodes and terminals can be formed of any of a variety of different materials well-known in the art, such as noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, etc.), and various combinations thereof. The dielectric layer is sandwiched between the respective active electrodes and bias electrodes. A voltage-tunable capacitor can exhibit excellent tunability over a wide range of high capacitance values and, exceptionally, provide a very low equivalent series resistance at medium and high operating voltages. In one embodiment, as will be described in more detail in subsequent chapters, these capacitors can also be incorporated into an array. In other embodiments, these capacitors can also be used as individual components. An individual tunable multilayer capacitor can have a value of 0.1 microfarad (「μF」) or more, in one embodiment about 1 μF or more, in one

[0025]

[0048] embodiment about 10 μF or more, etc. In the form, it can be used in applications that require a high capacitance, such as about 10 μF or more, and in some embodiments, 200 μF or more. For example, such a capacitor can range from 0.1 to 100 μF, in some embodiments from about 0.5 μF to about 50 μF, in some embodiments from about 1 μF to about 40 μF, and in some embodiments from about 2 μF to about 30 μF, and can provide an adjustment ability with an initial capacitance value. In an alternative embodiment, the initial capacitance value of the adjustable multilayer capacitor is about 100 picofarads (「pF」) or more, in some embodiments about 10,000 pF or more, in some embodiments from about 100,000 pF to about 10,000,000 pF, in some embodiments from about 200,000 pF to 5,000,000 pF, and in some embodiments from about 400,000 pF to about 3,500,000 pF. The adjustable multilayer capacitor can be configured to have any suitable initial capacitance value.

[0026]

[0049] The degree to which the capacitance can be adjusted can be changed as desired. For example, the initial capacitance of the capacitor, that is, from about 10% to about 1 00% of the capacitance when no DC bias voltage is applied, and in some embodiments from about 20% to about 95% of the initial capacitance, and in some embodiments from about 30% to about 80% of the capacitance can be adjusted.

[0027]

[0050] As shown above, an individual adjustable capacitor can exhibit a low ESR. In some embodiments, the equivalent series resistance (ESR) of the adjustable capacitor here can range from about 50 milliohms (mΩ) and below, in some embodiments from about 20 mΩ and below, and in some embodiments from about 10 mΩ and below. For example, in some embodiments, the ESR of the adjustable capacitor can range from about 1 mΩ to about 50 mΩ, in some embodiments from about 5 mΩ to about 40 mΩ, and in some embodiments from about 5 mΩ to about 20 mΩ.

[0028]

[0051] As shown above, each adjustable capacitor can operate at medium to high operating voltages. The operating voltage may refer to the DC bias voltage (i.e., the voltage across both ends of the bias electrode) and / or the signal voltage (i.e., the voltage across both ends of the active electrode). The operating voltage can generally vary with respect to the voltage at which the dielectric composition begins to become conductive upon application of an electric field, i.e., the "breakdown voltage". The breakdown voltage can be determined in accordance with ASTM D149-13 at a temperature of 25°C. In most embodiments, the operating voltage is about 5 0% or less of the breakdown voltage of the dielectric composition, in some embodiments about 30% or less, and in some embodiments from about 0.5% to about 10%.

[0029]

[0052] For example, an adjustable capacitor can operate at an AC voltage (e.g., peak-to-peak amplitude) higher than about 10V, in some embodiments higher than about 50V, and in some embodiments higher than about 100V. For example, in some embodiments, an adjustable capacitor can operate at voltages ranging from about 10V to about 300V, in some embodiments from about 15V to about 150V, and in some embodiments from about 20V to about 100V. In some embodiments, an adjustable capacitor can operate at a DC voltage higher than about 10V, in some embodiments higher than about 50V, and in some embodiments higher than about 100V. For example, in some embodiments, an adjustable capacitor can operate at voltages ranging from about 10V to about 300V, in some embodiments from about 15V to about 150V, and in some embodiments from about 20V to about 100V. In some embodiments, an adjustable capacitor can also operate at a voltage having both an AC component and a DC component.

[0030]

[0053] In some embodiments, the dielectric layer is from about 0.5 micrometers (μm) to about 50 μm, in some embodiments from about 1 μm to about 40 μm, and in some embodiments about It can have a thickness ranging from 2 μm to about 15 μm. The electrode layer can have a thickness ranging from about 0.5 μm to about 3.0 μm, in certain embodiments from about 1 μm to about 2.5 μm, and in certain embodiments from about 1 μm to about 2 μm, for example, about 1.5 μm.

[0031]

[0054] The total number of active and bias electrode layers can vary. For example, in certain embodiments, the total number of active electrode layers can range from 2 to about 1,000, in certain embodiments from about 10 to about 700, and in certain embodiments from about 100 to about 500. For example, in certain embodiments, the total number of bias electrodes can range from 2 to about 1,000, and in certain embodiments from about 10 to about 500. It should be understood that the number of electrodes and bias layers shown in the drawings and described herein is merely an example.

[0032]

[0055] In certain embodiments, this capacitor can be made small while imparting a high capacitance and occupying a small volume and / or surface area of the surface on which it is mounted. Thus, it can be said that this capacitor is very suitable for installation on, for example, a printed circuit board. The length of an individual capacitor can range, by way of example, from about 1 mm to about 50 mm, in certain embodiments from about 2 mm to about 35 mm, in certain embodiments from about 3 mm to about 10 mm, and in certain embodiments from about 3 mm to about 7 mm. The width of an individual capacitor can range, by way of example, from about 1 mm to about 50 mm, in certain embodiments from about 2 mm to about 35 mm, in certain embodiments from about 3 mm to about 10 mm, and in certain embodiments from about 3 mm to about 7 mm.

[0033]

[0056] Similarly, the capacitor can be made thin, for example, suitable for installation on a printed circuit board. The thickness of each individual capacitor can range, by way of example, from about 1 mm to about 500 mm, in certain embodiments from about 2 mm to about 35 mm, in certain embodiments from about 3 mm to about 10 mm, and in certain embodiments from about 2 mm to about 4 mm.

[0034]

[0057] In addition, in certain embodiments, the systems and methods described herein can also be used to adjust a partially adjustable multilayer capacitor. The partially multilayer capacitor can include at least one non-adjustable region and at least one adjustable region. The partially adjustable multilayer capacitor can allow for adjustments with higher resolution or accuracy compared to an equivalent fully adjustable multilayer capacitor. In certain embodiments, the partially adjustable multilayer capacitor can reduce the change in capacitance per unit change in the applied voltage and enable more accurate adjustments.

[0035]

[0058] Partially adjustable multilayer capacitors may be adjustable over a narrower range of capacitance values than equivalent fully adjustable multilayer capacitors. By way of example, fully adjustable capacitors may be adjustable, for example, from about 10% to about 95% of an initial capacitance value. This can be achieved by applying a DC bias voltage ranging from 0% to 100% of a maximum DC bias voltage to a fully adjustable capacitor. In contrast, a partially adjustable multilayer capacitor fabricated to a comparable size may only be adjustable, for example, from about 50% to about 95% of an initial capacitance value for the same applied DC bias voltage range. Thus, a partially adjustable multilayer capacitor can reduce the capacitance change with respect to an applied voltage change per unit. In certain embodiments, a partially adjustable multilayer capacitor may be adjustable over a range from about 20% to about 95% of an initial capacitance value, in certain embodiments from about 30% to about 95% of an initial capacitance value, in certain embodiments from 40% to 95% of an initial capacitance value, in certain embodiments from about 50% to about 95% of an initial capacitance value, in certain embodiments from about 60% to about 95% of an initial capacitance value, in certain embodiments from about 70% to about 95% of an initial capacitance value, and in certain embodiments from about 80% to about 95% of an initial capacitance value. It is also possible to make it adjustable within the range.

[0036]

[0059] In certain embodiments, the systems and methods described herein may also be used to adjust an array of adjustable multilayer capacitors. An array of adjustable multilayer capacitors can include a plurality of voltage-adjustable capacitors and / or non-adjustable capacitors. These capacitors may be connected in parallel to increase capacitance. These capacitors may be connected in series to increase the operating voltage.

[0037] I. Embodiment Examples of the System and Controller

[0060] FIG. 1 shows an embodiment of a system 100 for adjusting a voltage-adjustable capacitor 102 in accordance with an aspect of the present disclosure. The system 100 can include a controller 104 and a voltage-adjustable capacitor 102. The controller can be configured to receive at least one input signal. As an example, the controller 102 can be configured to receive a manual control signal 106, V CONTROL can be configured to receive. The manual control signal 106 can indicate a desired capacitance and / or a desired voltage associated with the voltage-adjustable capacitor 102. In some embodiments, the manual control signal can range from about 0 volts to at least about 3 volts. However, in some embodiments, the controller 104 can also be configured to not receive any manual control signal(s) 106.

[0038]

[0061] In some embodiments, the controller 102 can be configured to receive a feedback signal 108 (e.g., voltage, capacitance, current, temperature, etc.) associated with the voltage-adjustable capacitor 102. In this way, the controller 102 can be configured for closed-loop operation. In other embodiments, however, the controller 102 can also be configured for open-loop operation. In other words, the controller 102 may not receive a feedback signal associated with the voltage-adjustable capacitor 102.

[0039]

[0062] The controller 104 can also be configured to receive other input signals 109. Examples of input signals include signals indicative of the voltage, capacitance, current, or temperature of a circuit including the voltage-adjustable capacitor, a circuit otherwise coupled to or associated with the voltage-adjustable capacitor.

[0040]

[0063] The controller 104 is a voltage common collector 110, V CCIt can be coupled to. The voltage common collector 110 can be configured to supply power to the controller 104. The controller 104 can be configured to process the input signal(s). For example, the input signal can be V CONTROL 110, the feedback signal 108, and / or one or more of the other input signals 109, such as those described below with reference to FIG. 2. The controller 104 can be configured to process the input signal(s) using logic to generate a boost output signal 112 and supply the boost output signal 112 to the voltage adjustable capacitor 102 to adjust the bias voltage of the voltage adjustable capacitor 102. By adjusting the bias voltage of the voltage adjustable capacitor 102, the capacitance of the voltage adjustable capacitor 102 or the capacitor array can be adjusted, for example, as described below with reference to FIGS. 4 to 19.

[0041]

[0064] In some embodiments, the controller 104 or the system 100 can also be incorporated into a monolithic device. For example, the controller 104 can be sealed in a molding material or a packaging material to form a monolithic device. The monolithic device can include external terminals for electrically connecting the controller 104 to the adjustable capacitor 102, the input, and / or or other electrical components. The monolithic device can be configured for surface mounting on a printed circuit board.

[0042]

[0065] FIG. 2 shows an embodiment of a controller 200 for adjusting a voltage adjustable capacitor according to aspects of the present disclosure. The controller 200 may correspond to the controller 104 of the system 100 described above with reference to FIG. 1. The controller 200 can be coupled to a voltage common collector 201, V CC It can be coupled to. The voltage common collector 201 can be configured to supply power to the controller 200.

[0043]

[0066] The controller 200 can be configured to receive one or more input signals. As an example, the controller 200 can receive, for example, the manual control signals 203, V as previously described with reference to FIG. 1. CONTROL The manual control signal 214 can indicate at least one of a desired capacitance or a desired voltage associated with a voltage-adjustable capacitor. In certain embodiments, the manual control signal can range from about 0 volts to at least about 3 volts.

[0044]

[0067] The controller 200 can be configured to receive one or more input signals (e.g., in addition to, or instead of, the manual control signal 202). The controller 202 can include an analog-to-digital converter 203 configured to receive the input signal 204 and convert the input signal 204 to a digital signal 206. The controller 200 can include an analog-to-digital converter 203 (e.g., A / D1) configured to receive the signal input 204 (e.g., INPUT1) and convert the input signal 204 to a digital signal 206. In certain embodiments, the controller 200 can also include additional analog-to-digital converters 208 (e.g., from “A / D2” to “A / DN”). The additional analog-to-digital converters 208 can be configured to receive additional input signals 210 (e.g., from “INPUT1” to “INPUTN”). The additional analog-to-digital converters 208 can be configured to convert the additional input signals 210 to respective digital signals 212.

[0045]

[0068] The controller 200 can include a processor 216 configured to process digital signal(s) 206, 212 using logic to generate an output signal 217. The processor 216 can be, or include, any suitable type of circuit (e.g., an integrated circuit) capable of performing logical operations. By way of example, in one embodiment, the processor 216 can be, or include, an Advanced RISC Machines (ARM) processor-memory device(s) (e.g., an “Armcore” processor). The processor 216 can be any suitable processing device (e.g., a processor core, a microprocessor, an ASIC, an FPGA, a controller, a microcontroller, etc.) and can be one processor or multiple processors operably connected. The processor 216 can include or be coupled to memory element(s). The memory elements include one or more non-transitory computer-readable storage media such as RAM, ROM, EEPROM, EPROM, flash memory devices, magnetic disks, etc., and combinations thereof. The memory can store data and instructions. The instructions are executed by the processor to cause the computing device to perform various operations such as one or more aspects of method 300 described below with reference to FIG. 3. The processor 216 can be configured to employ any suitable form of logic such as open-loop control or closed-loop control. Examples of open-loop control include proportional, proportional-integral (PI), or proportional-integral-derivative (PID) control loops. The processor 216 can implement Boolean logic, fuzzy logic, and / or can implement machine learning techniques or models.

[0046]

[0069] The controller 200 can include a charge pump 218 configured to boost the output signal 217 to generate a boosted output signal 219. The charge pump 218 can be any suitable type of boosting device (e.g., a DC / DC converter). For example, the charge pump 218 may employ high-speed switching of an alternating current to generate the boosted output signal. In some embodiments, the charge pump 218 may not have an inductor. Typically, the charge pump 218 may not be regulated such that the boosted output signal 219 is positively correlated with the DC voltage received by the charge pump (e.g., the output signal 217 of the processor 216). In other words, the charge pump 218 can be configured to boost the output signal 217 of the processor 216 by a linear gain or according to a non-decreasing function. For example, the charge pump 218 can be configured to boost the output signal 217 of the processor 216 with a gain of two or more (e.g., as a "doubling" charge pump).

[0047]

[0070] The controller 200 can be configured to supply V to a voltage-adjustable capacitor to adjust the bias voltage of the voltage-adjustable capacitor, for example, as described with reference to FIG. 1 with respect to the boosted output signal 219. BIAS

[0048]

[0071] The input signal(s) 204, 210 can include various different inputs or parameters. By way of example, the input signal(s) 204, 210 can indicate a voltage, current, capacitance, temperature, and / or other suitable parameters associated with a voltage-adjustable capacitor, for example, as previously described with respect to the feedback signal 108 of FIG. 1.

[0049]

[0072] ​As another example, the input signal(s) 204, 210 can also indicate voltage, current, capacitance, temperature, and / or other suitable parameters associated with a circuit including a voltage-adjustable capacitor, a circuit connected to or associated with a voltage-adjustable capacitor otherwise. The input signal(s) 204, 210 can also indicate the temperature of a component (e.g., other than the voltage-adjustable capacitor) of a circuit associated with the voltage-adjustable capacitor. By way of example, the input signal(s) 204, 210 can also indicate the temperature of a component of a heat sink or other temperature-sensitive circuit. As another example, the input signal(s) 204, 210 can also indicate a desired output voltage or current of a circuit.

[0050]

[0073] The temperature of a voltage-adjustable capacitor or other component can be detected by a temperature sensor such as a thermocouple. The controller 200 can be configured to receive a signal indicating the detected temperature from the temperature sensor.

[0051]

[0074] The controller 200 can control the capacitance of a voltage-adjustable capacitor that can have a relatively high operating voltage based on one or more input signals having a relatively low voltage. For example, the controller 200 can be configured to adjust the bias voltage of the voltage-adjustable capacitor from about 0 volts to at least about 50 volts. The input signal(s) can range from about 0 volts to at least about 5 volts. Thus, the ratio of the bias voltage of the voltage-adjustable capacitor to the input signal voltage can range from about 1 to about 10 or more. Similarly, the manual control signal can range from about 0 volts to at least about 3 volts. Thus, the ratio of the bias voltage of the voltage-adjustable capacitor to the manual control signal can range from about 1 to about 16 or more.

[0052]

[0075] FIG. 3 shows a flowchart of a method 300 for adjusting a voltage-adjustable capacitor, in accordance with an aspect of the present disclosure. FIG. 3 shows steps executed in a particular order for purposes of illustration and discussion. It should be understood that any of the methods described herein can be performed in various ways, without departing from the scope of the present disclosure, by omitting, expanding, executing simultaneously, rearranging, and / or changing the various steps. Additionally, without departing from the scope of the present disclosure, various steps (not shown) can be performed. Additionally, method 300 will be described generally with reference to the system 100 and controller 200 described above with reference to FIGS. 1 and 2. However, it should be understood that aspects of this method 300 are applicable to any control system and / or controller suitable for adjusting a voltage-adjustable capacitor.

[0053]

[0076] Method 300 can include, at (302), receiving at least one input signal, such as the manual control signals 106, 202 described above with reference to FIGS. 1 and 2, and / or other input signals 109, 204, 210 described above with reference to FIGS. 1 and 2.

[0054]

[0077] Method 300 can include, at (304), converting the input signal(s) into at least one digital signal. The input signal(s) can be converted into the digital signal(s) using, for example, one or more analog-to-digital converters 206, 212 as described above with reference to FIG. 2.

[0055]

[0078] Method 300 can include, at (306), processing the digital signal(s) using logic to generate an output signal, such as described above with reference to the output signals 112, 217 of FIGS. 1 and 2.

[0056]

[0079] Method 300 can include, at (308), boosting the output signal(s) using, for example, the charge pump 218 as described above with reference to FIG. 2 to generate a boosted output signal.

[0057]

[0080] Method 300 can include, at (310), supplying the boosted output signal to a voltage-adjustable capacitor to adjust the bias voltage of the voltage-adjustable capacitor, for example, as described above with reference to FIGS. 1 and 2.

[0058] II. Embodiment Examples of Adjustable Multilayer Capacitors

[0081] FIG. 4 shows in graph form the capacitance change that can be achieved over a range of normalized bias voltage changes. Specifically, the horizontal axis represents the normalized bias voltage as a percentage of the rated voltage of the device, such as from 0% to 150%. As shown, the corresponding change in the effective capacitance of the device is represented on the vertical axis as a percentage change from the capacitance value when there is no bias. As shown by the graph of FIG. 4, when the normalized bias voltage amount increases by 150%, it approaches an 80% decrease in the capacitance value when there is no bias along a relatively linear curve as shown. Thus, the voltage-adjustable capacitor device according to the subject matter disclosed herein helps to maximize efficiency over a range of operating conditions.

[0059]

[0082] With reference now to FIGS. 5A through 5D, a particular embodiment of capacitor 10 that can be formed in accordance with the present disclosure will be described in more detail. As shown, capacitor 10 incorporates a plurality of dielectric layers 12. The dielectric layers 12 are separated into two sets of active electrodes 14 and 20 and two sets of bias electrodes 22 and 26 They are alternately laminated in relation to []. This capacitor may be a hexahedron such as a rectangular parallelepiped body. In the illustrated embodiment, the first active terminal 16 is electrically connected to the first active electrode 14, and the second active terminal 18 is electrically connected to the second active electrode 20. The first bias electrode 22 is electrically connected to the first DC bias (+) terminal 30 via an extension member 24 (e.g., a tab) that reaches the side surface of the capacitor 10. Similarly, the second bias electrode 26 is electrically connected to the second DC bias (-) terminal 32 via an extension member 28. Therefore, the resulting capacitor 10 incorporates four separate terminals. In one embodiment, the active terminals 16, 18 wrap around each end of the capacitor 10, and larger terminals 16, 18 can be provided to electrically connect the capacitor 10 in a circuit. The DC bias terminals 30, 32 may be configured as strips that do not extend across the entire side surface of the capacitor 10. In other embodiments, however, the DC bias terminals 30, 32 may instead wrap around the side surfaces of the capacitor 10, and the active terminals 16, 18 may be configured as strips that do not extend along the entire ends of the capacitor.

[0060]

[0083] FIGS. 6A and 6B are diagrams showing the shunt configuration and the series configuration of the exemplary embodiments from FIGS. 5A to 5D above, respectively. As shown, a ground 34 is also provided in relation to the bias input, showing the shunt configuration.

[0061]

[0084] In the embodiments discussed above, the active electrodes are stacked such that the alternating electrodes are connected to opposite terminals. In certain embodiments, by using a "cascade" configuration, the alternating layers can also be connected to the same terminal. In a "cascade" configuration, each set of active electrodes is spaced apart laterally rather than stacked. An embodiment of such a cascaded capacitor 49 is shown in FIGS. 7A through 7C. As shown, capacitor 49 includes a plurality of dielectric layers 44 arranged in relation to two separate sets of active electrodes 36 and 40, and two separate sets of bias electrodes 46 and 50. In the illustrated embodiment, in this example, the first active terminal 38 is electrically connected to the first active electrode 36, and the second active terminal 42 is electrically connected to the second active electrode 40. The first bias electrode 46 is electrically connected to the first DC bias (-) terminal 54 via an extension member 48 that reaches the side of capacitor 49. Similarly, the second bias electrode 50 is electrically connected to the second DC bias (+) terminal 56 via an extension member 52. FIGS. 7D and 7E are diagrams representing the shunt configuration and the series configuration, respectively, of the exemplary embodiment of FIGS. 7A through 7C above. As shown, a ground 58 is also provided in relation to the bias input, shown for the shunt configuration.

[0062]

[0085] Figures 8A through 8C illustrate other embodiments of capacitor 59 that can be formed in a partial cascade configuration in accordance with the present disclosure. The capacitor 59 is considered to be in a "partial cascade" because only a partial region 60 within the entire active capacitance region is biased (see Figure 8A). As shown, adding a biased floating electrode allows the dielectric properties of the total capacitance to be varied by the application of an external voltage, as determined by other factors and features. As shown in such figures, the dielectric layer 62 may be alternately laminated with respect to the first and second sets of active electrodes 64 and 66, the first and second sets of bias electrodes 68 and 72, and the plurality of floating electrodes 76. The first active electrode 64 is electrically connected to the first active terminal 78, while the second active electrode 66 is electrically connected to the second active terminal 80. The first bias electrode 68 is electrically connected to the first DC bias (+) terminal 82 via an extension member 70 that reaches the side surface of the capacitor 59. Similarly, the second bias electrode 72 is electrically connected to the second DC bias (-) terminal 84 via an extension member 74. It should be understood that the number of electrode layers shown in Figure 8A is merely an example.

[0063]

[0086] Further other embodiments of capacitors that can be adjusted by the controllers and / or systems described herein are shown in FIGS. 11A and 11B. In this embodiment, the first and second sets of active electrodes 1014, 1020 are alternately laminated with the first and second sets of bias electrodes 1022, 1026, respectively, in a 1:1 ratio pattern. Referring to FIG. 11B, in one embodiment, the leads 1024, 1028 of the bias electrodes 1022, 1026 can be configured like protruding tabs. The leads 1024, 1028 can contact the DC bias terminals 30, 32 in the completed form as shown in FIG. 2D. It should be understood that the number of electrode layers shown in FIGS. 11A and 11B is merely an example.

[0064]

[0087] Other embodiments of the capacitor that can be adjusted by the controller and / or system disclosed herein are shown in FIGS. 11C and 11D. In this embodiment, the active electrodes 1014, 1020 can include respective leads 1025 and 1027 that can be configured like protruding tabs. The leads 1025, 1027 can be electrically connected to the respective active terminals 16, 18 shown in FIG. 11D. This can improve the lamination between the edges of the capacitor layers, especially at the corners of the layers, resulting in a more robust capacitor. Additionally, this configuration can also reduce the occurrence of peeling problems during manufacturing.

[0065]

[0088] Additionally, the respective widths of the tabs 1024, 1025, 1026, 1027 can be selected such that the advantage of increased (e.g., reduced resistance) electrical contact to the respective electrodes 1014, 1020, 1022, 1026 is obtained. Additionally, the widths of the tabs 1024, 1028, and the widths of the terminals 30, 32 associated with the DC bias electrodes 1022, 1026 can also be selected to avoid contact between the bias electrode terminals 30, 32 and the signal electrode terminals 16, 18. For example, in certain embodiments, the tabs 1024, 1025, 1026, 1027 may extend along more than 10%, in certain embodiments more than 30%, and in certain embodiments more than 60% of the edge of the capacitor. It should be understood that the number of electrode layers shown in FIGS. 11A through 11D is merely an example.

[0066]

[0089] In the embodiments discussed above, generally, electrodes of a "symmetric" configuration are employed, and the distance between the first active electrode and the second active electrode (or the thickness of the dielectric) is substantially the same as the distance between the first bias electrode and the second bias electrode. In certain embodiments, however, it may be desirable to vary this thickness in order to obtain an "asymmetric" configuration. For example, the distance between the first and second active electrodes may be made shorter than the distance between the first and second bias electrodes. In still other embodiments, the distance between the first and second active electrodes may be made greater than the distance between the first and second bias electrodes. In particular, this can increase the DC electric field formed for a given level of applied DC bias and raise the level of adjustability for a given DC bias voltage. Also, such an arrangement can allow for relatively large adjustability for a relatively modest DC voltage and can also allow for the use of materials having more modest adjustability (potentially less loss and lower temperature / frequency variability). Such an asymmetric configuration can be achieved in a variety of ways, but typically it is desirable to use additional "floating" bias electrodes between each pair of active electrodes. Referring to FIG. 10 by way of example, an embodiment of such an asymmetric capacitor is shown, incorporating first and second active electrodes 1014 and 1020, respectively, along with first and second bias electrodes 1022 and 1026, respectively.

[0067]

[0090] FIG. 12A shows another embodiment of an asymmetric capacitor where every 11th electrode is an active electrode rather than a bias electrode (an 11:1 ratio design). In this case, each such active electrode (e.g., an AC electrode) can be bound by a pair of DC bias electrodes having opposite polarities. That is, a biasing field can be generated across each AC electrode. Such a configuration can provide for interaction between the AC signal and the DC bias. signal and the DC bias. Capacitive coupling can be formed between the two polarities of the bias voltage and vice versa. Each AC electrode 214, 220 may be disposed between a pair of bias electrodes 222, 226 having opposite polarities. The first set of bias electrodes 222 can all have the same polarity, and the second set of bias electrodes 226 (shown in dashed lines) can each have a polarity opposite to that of the first set of bias electrodes 222. This configuration can form capacitive coupling between each AC electrode 214, 220 and both DC bias polarities.

[0068]

[0091] FIG. 12B shows a cross-sectional view of an exemplary embodiment of a "shielded" asymmetric design with a ratio of 11:1 of a bias stacked capacitor according to the subject matter disclosed herein. This is similar to the example shown in FIG. 8, except that each AC electrode 314, 320 is sandwiched between a pair of DC electrodes (322 or 326) having the same polarity. The first set of bias electrodes 322 can all have the same polarity, and the other set of bias electrodes 326 (shown in dashed lines) can all have the opposite polarity. Among the materials between the two DC electrodes (322 or 326) and having the same polarity, some cannot be adjusted, but this material can potentially provide shielding against the AC signal and reduce the accompanying noise. Also, such a configuration can form a coupling only between each of the first set of AC electrodes 314 and one DC bias polarity. Similarly, such a configuration can form a capacitive coupling only between the second set of AC electrodes 320 and the opposite DC bias polarity. It should be understood that the number of electrode layers shown in FIGS. 8 and 9 is merely an example.

[0069]

[0092] FIG. 13A shows a cross-sectional view of an exemplary embodiment of a partially tunable stacked capacitor 400 according to aspects of the subject matter disclosed herein. The partially tunable stacked capacitor 400 can include a first set of AC electrodes 402 electrically connected to a first active terminal 404 and a second set of AC electrodes 406 electrically connected to a second active terminal 408. The partially tunable stacked capacitor 400 can also include a DC bias electrode 410 configured to apply a DC bias voltage across both ends of one or more variable dielectric regions 412 so as to vary the dielectric constant of the variable dielectric regions 412 as discussed in detail above. The partially tunable stacked capacitor 400 can also include a non-tunable region 414 that cannot be adjusted by the application of the DC bias voltage. For example, in one embodiment, the non-tunable region 414 may not include any DC bias electrodes 410 at all. Alternatively, in other embodiments, the non-tunable region 414 may incorporate electrodes that are not connected to any terminals such that no DC bias voltage is applied within the non-tunable region 414. Thus, in one embodiment, the capacitance of the dielectric material in the non-tunable section 402 can be made unaffected by the DC bias voltage applied across both ends of the DC bias electrode 410.

[0070]

[0093] FIG. 13B is a schematic diagram of the partially tunable stacked capacitor shown in FIG. 13A. In this embodiment, the non-tunable region 414 is connected in parallel with one or more variable dielectric regions 412. When a DC bias voltage is applied across both ends of the DC bias terminals, the capacitance of the tunable region(s) 412 can be varied, but the capacitance of the non-tunable region 414 cannot be varied. As a result, the partially tunable stacked capacitor can be tuned over a narrower range of capacitance values than an equivalent fully tunable stacked capacitor. As a result, the capacitance change per unit change in the applied DC bias voltage can be made less than that of an equivalent fully tunable stacked capacitor. That is, the partially tunable stacked capacitor can have improved tuning resolution or accuracy.

[0071]

[0094] In certain embodiments, the active and DC bias terminals are symmetrically disposed about the axis of the capacitor. For example, in one embodiment, the capacitor can include longitudinally spaced, opposing first and second end regions and laterally spaced opposing first and second side regions. In a particular embodiment, the active terminals can be disposed in each end region of the capacitor, while the DC bias terminals can be disposed in each side region of the capacitor. When symmetrically disposed, the active terminals and / or the DC bias terminals may be equidistantly spaced from longitudinal and lateral axes passing through the geometric center of the capacitor. Referring to FIG. 15A, for example, an embodiment of a capacitor 1000 is shown, including a longitudinal axis “x” and a lateral axis “y” that are perpendicular to each other and pass through the geometric center “C”. In this particular embodiment, the capacitor 1000 includes first and second active terminals 1100 and 1120, respectively disposed in the end regions of the capacitor 1000 and positioned about both axes “x” and “y”. Similarly, the capacitor 1000 also includes first and second bias terminals 1140 and 1160, which are disposed in the side regions of the capacitor 1000 and positioned about both axes “x” and “y”.

[0072]

[0095] In certain embodiments, it may be desirable to arrange two or more terminals on the same side of the capacitor. Taking an example in FIG. 15B, an embodiment of capacitor 2000 is shown, including a first active terminal 2100 and a second active terminal 2140 arranged in the same side region. Also, capacitor 2000 includes a first bias terminal 2160 and a second bias terminal 2120, both arranged in the other side region opposite to the active terminals. Although arranged only in the side region, since the active terminals 2100 and 2140 are both positioned equidistant from the axes "x" and "y", it can be said that they are symmetrically arranged. Similarly, the bias terminals 2160 and 2120 are also arranged equidistant from the axes "x" and "y". In the embodiment cited above, the first active terminal and the first bias terminal are positioned opposite to their respective second active terminal and second bias terminal. Of course, this is not at all essential. Taking an example in FIG. 15C, capacitor 3000 is shown, including first and second active electrode terminals 3100 and 3160, respectively arranged in an offset configuration in opposite side regions. However, since the first active terminal 3100 and the second active terminal 3160 are both positioned equidistant from the axes "x" and "y", they are symmetrically arranged. Similarly, capacitor 3000 also includes first and second bias terminals 3120 and 3140, arranged in an offset configuration in opposite side regions and equidistant from the axes "x" and "y". In other embodiments, the terminals, for example, the bias terminals and / or the active electrode terminals, can be configured symmetrically about the "x" and "y" axes described above.

[0073]

[0096] The subject matter disclosed in this specification also encompasses, among other things, methods and / or corresponding means related to improvements in voltage regulating devices, including, for example, the production of such devices and their use in combination with associated circuitry. As yet another example, FIG. 9 represents a chip manufacturing automated process (CMAP) 86. This process 86 can be used in conjunction with exemplary embodiments of device manufacturing disclosed herein. As illustrated, the process 86 can include a plurality of sequential stages, which, in one example, typically includes three ovens, along with a ceramic station or other steps / facets such as the use of a screen head or elevator and conveyor structures therebetween. It should be understood by those skilled in the art that the exact provision of the sequential steps will vary depending on which of the exemplary device embodiments (or modifications thereof) disclosed herein are being produced. Also, the individual steps illustrated are intended only to represent the type of steps shown and do not specify the use of other aspects that may be required beyond the general nature of the steps shown. For example, the screen head step may involve using a stainless steel screen in conjunction with an electrode paste for screen pasting of an electrode layer, or other techniques for such a step may be implemented. For example, the step of conventional alternating stacking and laminating (by tape) may be carried out. It will be recognized by those skilled in the art that for any process (or other means), the selected steps can be implemented to produce a particular design selected for a given application of the subject matter disclosed herein. It will be understood by those skilled in the art that the exact provision of the sequential steps will vary depending on which of the exemplary device embodiments (or modifications thereof) disclosed herein are being produced. Also, the individual steps illustrated are intended only to represent the type of steps shown and do not specify the use of other aspects that may be required beyond the general nature of the steps shown. For example, the screen head step may involve using a stainless steel screen in conjunction with an electrode paste for screen pasting of an electrode layer, or other techniques for such a step may be implemented. For example, the step of conventional alternating stacking and laminating (by tape) may be carried out. It will be recognized by those skilled in the art that for any process (or other means), the selected steps can be implemented to produce a particular design selected for a given application of the subject matter disclosed herein.

[0074]

[0097] Referring to FIGS. 16A through 16C, an adjustable stacked capacitor array 4000 can be formed by arranging the individual capacitors 10 in a "horizontal stack" configuration. The individual capacitors can be configured as described, for example, with reference to FIGS. 2 and 7. The stacked capacitor array 4000 can provide an increase in capacitance and a reduction in ESR compared to a single capacitor 10. In addition, the stacked capacitor array 400 can enable easy manufacturing and, for example, mounting on a printed circuit board. In addition, the stacked capacitor array 400 can also provide an improvement in mechanical stability and heat dissipation.

[0075]

[0098] In one embodiment, the capacitors 10 of the capacitor array 4000 can be connected in parallel. For example, the first lead frame 4002 can be connected to each first active terminal 16, and the second lead frame 4004 can be connected to each second active terminal 18. The first single-wire lead 4006 can be connected to each first DC bias terminal 30, and the second single-wire lead 4008 can be connected to each second DC bias terminal 32. In one embodiment, the DC bias terminals 30, 32 can wrap around the sides of the capacitor as shown in FIGS. 16B and 16C. This configuration can improve the mechanical and / or electrical connection between the DC bias terminals 30, 32 and the respective bias electrodes to which each bias terminal 30, 32 is connected. In addition, such a configuration can also improve the electrical connection between the various first DC bias terminals 30 and the various second DC bias terminals 32 of adjacent capacitors 10. This can provide a more resilient array 4000.

[0076]

[0099] In other embodiments, the DC bias terminals 30, 32 may be provided only on the side surfaces of the capacitor 10, as shown in FIG. 16A. In such a configuration, the capacitors 10 can be arranged more closely in the array 4000, and for example, a further miniaturized array 4000 can be obtained.

[0077]

[0100] By applying a DC bias voltage across the ends of the first and second single-wire leads 4006, 4008, a DC bias voltage can be applied to each of the capacitors 10 within the array 4000. For clarity, the single-wire leads 4006, 4008 are omitted from FIGS. 16A and 16B. Each of the first and second lead frames 4002, 4004 can include a plurality of leads 4010 extending from the capacitor array 4000 for connection to a circuit, for example, a printed circuit board. In one embodiment, the leads 4010 may be straight, as shown in FIG. 16A, and in other embodiments, the leads 4010 may be curved outward in a "J" shape, as shown in FIG. 16B. In still other embodiments, the leads 4010 may be curved inward or may have any other configuration suitable for mounting.

[0078]

[0101] The adjustable stacked capacitor array 4000 can have a length 4012 in the longitudinal direction 4014, a width 4016 in the width direction 4018, and a height 4020 in the height direction 4022. Each capacitor 10 may be arranged in a "horizontal stack" configuration such that the thickness of each of the plurality of adjustable stacked capacitors 10 extends in the longitudinal direction 4014 of the array 4000. As shown in FIGS. 16A and 16B, the height 4020 of the array 4000 may include a gap distance 4021 between the array 4000 and the surface (shown by the dotted line) on which the array 4000 is mounted. The gap distance 4021 is the bottom surface of the array 400 (including the terminal 32) It is only necessary to measure between the surface on which the array 4000 is mounted. The lead frames 4002 and 4004 can support the array 4000 above this surface. The gap distance 4021 can thermally isolate the array 4000 from the surface and help mechanically disconnect the array 4000 from the distortion on the surface.

[0079]

[0102] Referring to FIGS. 17A through 17C, a partially adjustable stacked capacitor array 5000 can be formed by arranging both an adjustable stacked capacitor 10 and a non-adjustable capacitor 5002, i.e., a capacitor without an adjustment function, in a "horizontal stack" configuration. Similar to the embodiment shown in FIGS. 16A through 16C, the partially adjustable stacked capacitor array 5000 can include a first lead frame 4002 connected to each first active terminal 16 of the adjustable stacked capacitor 10 and a second lead frame 4004 connected to each second active terminal 19 of the adjustable stacked capacitor 10. Additionally, a first single-wire lead 4006 can be connected to each first DC bias terminal 30 of the adjustable stacked capacitor 10, and a second single-wire lead 4008 can be connected to each second DC bias terminal 32 of the adjustable stacked capacitor 10. For clarity, the single-wire leads 4006 and 4008 are omitted from FIGS. 17A and 17B. Similar to the array 4000 described with reference to FIGS. 16A through 16C, the adjustable capacitors 10 of the partially adjustable array 5000 can include DC bias terminals 30 and 32 that wrap around the sides of the capacitor 10, as shown in FIGS. 17B and 17C. In other embodiments, the DC bias terminals 30 and 32 can be arranged only on the sides of the adjustable capacitor, as shown in FIG. 17A, for example.

[0080]

[0103] The partially adjustable stacked capacitor array 5000 can enhance the adjustment resolution or accuracy, similar to the partially adjustable stacked capacitor 400 described previously with reference to FIGS. 13A and 13B. The non-adjustable capacitor 5002 can increase the minimum capacitance of the array 5000 when the maximum DC bias voltage is applied across both ends of the DC bias electrodes 30 and 32 of the array using the single-wire leads 4006 and 4008.

[0081]

[0104] Referring to FIGS. 18A through 18C, in one embodiment, a bottom-terminated array 6000 can be formed. This has first and second DC bias terminals 30 and 32 arranged along the bottom surface of the array 6000. For example, each capacitor 10 can have its respective first and second DC bias terminals 30 and 32 arranged along the same side. In other embodiments, the DC bias terminals 30 and 32 can both be arranged along the top surface of the array 4000. The DC bias terminals 30 and 32 can, however, have any suitable configuration. The configuration shown from FIGS. 18A through 18C can provide advantages, including, for example, easier implementation and improved mechanical durability. By way of example, the DC bias terminals 30 and 32 can facilitate the connection to their respective terminals on the surface on which the array 400 is implemented, such as on a printed circuit board. In one embodiment, the single-wire leads 4006 and 4008 can connect the respective DC bias terminals 30 and 32 to their respective terminals on the mounting surface. In other embodiments, however, the DC bias terminals can be directly connected to their respective terminals on the mounting surface, for example, by soldering, without using the single-wire leads 4006 and 4008.

[0082]

[0105]

[0083]

[0106] In addition, the bottom-end configuration described above can also be employed to form a partial-adjustment capacitor array, similar to the embodiments described with reference to FIGS. 17A through 17C. For example, in one embodiment, a combination of bottom-end adjustable capacitors 10, similar to the partially adjustable array 5000 described above with reference to FIGS. 17A through 17C, may be connected in parallel with non-adjustable capacitors 5002.

[0084]

[0107] In other embodiments, for example, as shown in FIGS. 16A through 16C, a first set of adjustable capacitors 10 having DC bias terminals 30, 32 arranged on opposite side surfaces can be used to form an array together with a second set of adjustable capacitors 10 having DC bias terminals 30, 32 arranged on the same side surface (e.g., the bottom surface), as shown in FIGS. 18A through 18C. Such a configuration can enable applying a first DC bias voltage to the first set of adjustable capacitors 10 and applying a second bias voltage different from the first DC bias voltage to the second set of adjustable capacitors 10. This can provide an adjustable array 4000 that can be adjusted based on two different DC bias voltages. In yet other embodiments, a first set of adjustable capacitors 10 having DC bias terminals 30, 32 arranged on the bottom surface can be connected into an array having a second set of adjustable capacitors 10 having DC bias terminals 30, 32 arranged on, for example, the top surface. Also, this configuration can enable applying a first DC bias voltage to the first set of adjustable capacitors 10 and applying a second DC bias voltage different from the first DC bias voltage to the second set of adjustable capacitors 10. This can provide an adjustable array 4000 that can be adjusted based on two different DC bias voltages.

[0085]

[0108] Those skilled in the art will understand that still other combinations of adjustable capacitors having the various configurations described and illustrated herein can form additional arrays that specifically exceed those described herein. Similarly, still other combinations of adjustable and non-adjustable capacitors having the configurations as described and illustrated herein are possible.

[0086]

[0109] Referring to FIG. 19, in one embodiment, the capacitor array 4000 can have a vertical stack configuration. The vertical stack capacitor array 4000 can similarly have a first lead frame 4002 connected to a part or all of the first active terminal 16, and the second lead frame 4004 can be connected to a part or all of the second active terminal 18. The first single-wire lead 4006 can be connected to a part or all of the first DC bias terminals 30, and the second single-wire lead 4008 can be connected to a part or all of the second DC bias terminals 32. Thus, the vertical stack capacitor array 4000 can be configured as a fully adjustable capacitor array in one embodiment and as a partially adjustable capacitor array in other embodiments. In one embodiment, for example, an adjustable capacitor 10 configured like the capacitor 10 described above with reference to the bottom terminal adjustable array shown in FIGS. 18A - 18C can be used to form a vertical stack array having both bias terminals 30, 32 on the same side. Similarly, combinations of different adjustable and / or non-adjustable capacitors can also be incorporated into the vertical stack array 4000 as described above with reference to the horizontal stack arrays 4000, 5000.

[0087]

[0110] The horizontal stack configuration described above with reference to FIGS. 12 through 14 can improve the mechanical stability of a capacitor array that includes a large number of capacitors. For example, in an array that includes more than five capacitors, the height of a vertical stack array may be impractically high for mounting on the surface of a printed circuit board, for example. Additionally, the height of such an array may also risk making the array mechanically unstable. However, in an array that has a small number of capacitors, for example, five or fewer capacitors, the vertical stack array can have a narrow footprint and a lower profile.

[0088] III. Applications

[0111] A controller and / or system for adjusting a voltage-adjustable capacitor as described herein can be employed in a wide variety of applications, including, for example, a power conversion circuit. Being adjustable at high capacitance and voltage, it can address the optimization of circuit performance. Further other applications can include a point-of-load filter circuit and smoothing capacitors in various load circuits. Other suitable applications can include, by way of example, waveguides, RF applications (such as delay lines), antenna structures, matching networks, resonant circuits, and other applications.

[0089] Inspection Methods Capacitance

[0112] The capacitance can be measured in accordance with MIL-STD-202 Method 305 using a Keithley 3330 Precision LCZ meter with a DC bias of 0.0 volts, 1.1 volts, or 2.1 volts (a 1-volt root mean square sine wave signal). The operating frequency is 1 kHz and the temperature is approximately 25°C. The relative humidity can be 25% or 85%.

[0090] Equivalent series resistance (ESR)

[0113] Using a Keithley 2400, 2602, or 3330 Precision LCZ meter, the equivalent series resistance can be measured with the DC bias set to 0.0 volts, 1.1 volts, or 2.1 volts (a 0.5 volt peak-to-peak sine wave signal) and the operating frequency set to 10 kHz, 50 kHz, or 100 kHz. Various temperature and relative humidity levels can be examined. For example, the temperature may be 23°C, 80°C, or 105°C, and the relative humidity may be 25% or 85%.

[0091] Examples of Capacitor Arrays

[0114] To adjust the capacitor array, the aforementioned controller and / or system can be used. Examples of adjustable stacked capacitor arrays according to aspects of the present disclosure are shown in Table 1.

Table 1

[0092]

[0115] The initial capacitances listed in Table 1 may be the capacitances of the array without applying a DC bias voltage. The array may be adjustable from about 10% to about 95% of the initial capacitance.

[0093]

[0116] Those skilled in the art could make these and other changes and modifications to the present invention without departing from the spirit and scope of the invention. Additionally, it should be understood that aspects of various embodiments may be interchanged, in whole or in part. Furthermore, it will be recognized by those skilled in the art that the above description is merely an example and is not intended to limit the invention beyond the description in the appended claims.

Claims

1. A controller for adjusting a voltage-adjustable capacitor, at least one analog / digital converter configured to receive at least one input signal and convert the at least one input signal into at least one digital signal; a processor configured to process the at least one digital signal using logic and generate an output signal; a charge pump configured to boost the output signal and generate the boosted output signal; comprising the controller is configured to supply the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage of the voltage-adjustable capacitor, and a ratio of the bias voltage of the voltage-adjustable capacitor to a voltage of the at least one input signal ranges from about 1 to about 16. A controller.

2. The controller according to claim 1, configured to adjust the bias voltage from about 0 volts to at least about 50 volts. A controller.

3. The controller according to claim 1, wherein the boosted output signal adjusts a capacitance of the voltage-adjustable capacitor. A controller.

4. The controller according to claim 1, wherein the at least one input signal indicates at least one of voltage, current, or capacitance. A controller.

5. The controller according to claim 1, wherein the at least one input signal indicates a capacitance associated with the voltage-adjustable capacitor. A controller.

6. The controller according to claim 1, wherein the at least one input signal indicates temperature. A controller.

7. The controller according to claim 1, wherein the at least one input signal includes at least two input signals. A controller.

8. The controller according to claim 1, wherein the at least one input signal includes a manual control signal indicating at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor. A controller.

9. The controller according to claim 8, wherein the manual control signal ranges from about 0 volts to at least about 3 volts. A controller.

10. A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump A voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied. Comprising The one or more control devices Receives at least one input signal Processes the at least one input signal using logic to generate an output signal Boosts the output signal using the charge pump Supplies the boosted output signal to the voltage-adjustable capacitor to adjust the bias voltage applied across the plurality of bias electrodes Configured to The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor The manually generated control signal ranges from about 0 volts to at least about 3 volts The boosted output signal adjusts the capacitance of the voltage-adjustable capacitor. **Claim 11** A system for adjusting a voltage-adjustable capacitor, One or more control devices including a charge pump, A voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied. Comprising The one or more control devices Receives at least one input signal Processes the at least one input signal using logic to generate an output signal Boosts the output signal using the charge pump Supplies the boosted output signal to the voltage-adjustable capacitor to adjust the bias voltage applied across the plurality of bias electrodes Configured to The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor The manually generated control signal ranges from about 0 volts to at least about 3 volts A system in which the at least one input signal indicates at least one of voltage, current, or capacitance. **Claim 12** A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump, a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage, comprising wherein the one or more control devices receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, supply the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes configured to wherein the at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor, wherein the manually generated control signal ranges from about 0 volts to at least about 3 volts, and a system wherein the at least one input signal indicates a capacitance associated with the voltage-adjustable capacitor. **Claim 13** A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump, a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage, comprising wherein the one or more control devices receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, supply the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes configured to The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor, the manually generated control signal ranging from about 0 volts to at least about 3 volts, the at least one input signal being a system indicating temperature. **Claim 14** A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump, a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, at least a portion of the dielectric layers containing an adjustable dielectric material exhibiting a variable dielectric constant upon application of an applied voltage, comprising: the one or more control devices being configured to receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, and supply the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes, configured as such, the at least one input signal including a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor, the manually generated control signal ranging from about 0 volts to at least about 3 volts, the at least one input signal being a system including at least two input signals. **Claim 15** A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump, a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, at least a portion of the dielectric layers containing an adjustable dielectric material exhibiting a variable dielectric constant upon application of an applied voltage, comprising: the one or more control devices being configured to receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, To adjust the bias voltage applied across both ends of the plurality of bias electrodes, the boosted output signal is supplied to the voltage-adjustable capacitor configured to wherein the at least one input signal includes a manual control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor wherein the manual control signal ranges from about 0 volts to at least about 3 volts The system, wherein the one or more control devices further comprise an analog-to-digital converter configured to generate a digital signal from the input signal, and wherein processing of the input signal includes processing of the digital signal **Claim 16** A system for adjusting a voltage-adjustable capacitor, comprising one or more control devices including a charge pump a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage comprising wherein the one or more control devices receive at least one input signal process the at least one input signal using logic to generate an output signal boost the output signal using the charge pump supply the boosted output signal to the voltage-adjustable capacitor to adjust the bias voltage applied across both ends of the plurality of bias electrodes configured to wherein the at least one input signal includes a manual control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor wherein the manual control signal ranges from about 0 volts to at least about 3 volts wherein the adjustable dielectric material has a voltage-adjustability coefficient ranging from about 10% to about 90%, and the voltage-adjustability coefficient is determined according to the following general formula T = 100 x (ε 0 -ε V ) / ε 0 in accordance with where T is the voltage-adjustability coefficient ε ０ is the static dielectric constant of the material when no voltage is applied, and ε ｖ is a system that is the variable dielectric constant of the material after applying an applied voltage (DC). **Claim 17** A system for adjusting a voltage-adjustable capacitor, comprising one or more control devices including a charge pump A voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied. Comprising The one or more control devices Receive at least one input signal Process the at least one input signal using logic to generate an output signal Boost the output signal using the charge pump Supply the boosted output signal to the voltage-adjustable capacitor to adjust the bias voltage applied across the plurality of bias electrodes Is configured to The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor The manual control signal ranges from about 0 volts to at least about 3 volts A system in which the static dielectric constant of the dielectric material ranges from about 100 to about 10,000 when determined according to ASTM D2149-13 at an operating temperature of 25 °C and a frequency of 1 kHz.

18. A system for adjusting a voltage-adjustable capacitor, One or more control devices including a charge pump, A voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied. Comprising The one or more control devices Receive at least one input signal Process the at least one input signal using logic to generate an output signal Boost the output signal using the charge pump Supply the boosted output signal to the voltage-adjustable capacitor to adjust the bias voltage applied across the plurality of bias electrodes Is configured to The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor The manual control signal ranges from about 0 volts to at least about 3 volts, and the voltage - adjustable capacitor is adjustable to a capacitance value of about 100 pF or more, a system. **Claim 19** A system for adjusting a voltage - adjustable capacitor, comprising: one or more control devices including a charge pump; a voltage - adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layers contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage; comprising the one or more control devices being configured to receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, and supply the boosted output signal to the voltage - adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes; configured as wherein the at least one input signal includes a manually - generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage - adjustable capacitor, the manual control signal ranges from about 0 volts to at least about 3 volts, and the voltage - adjustable capacitor is adjustable to a capacitance value less than about 100 pF, a system. **Claim 20** A system for adjusting a voltage - adjustable capacitor, comprising: one or more control devices including a charge pump; a voltage - adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layers contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage; comprising the one or more control devices being configured to receive at least one input signal, process the at least one input signal using logic to generate an output signal, boost the output signal using the charge pump, and supply the boosted output signal to the voltage - adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes; configured as The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage adjustable capacitor, the manually generated control signal ranges from about 0 volts to at least about 3 volts, and a system in which the one or more control devices are incorporated into a monolithic device. **Claim 21** A system for adjusting a voltage adjustable capacitor, comprising: one or more control devices including a charge pump; a voltage adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a portion of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant upon application of an applied voltage; comprising: the one or more control devices are configured to: receive at least one input signal; process the at least one input signal using logic to generate an output signal; boost the output signal using the charge pump; and supply the boosted output signal to the voltage adjustable capacitor to adjust a bias voltage applied across the plurality of bias electrodes. The at least one input signal includes a manually generated control signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage adjustable capacitor, the manually generated control signal ranges from about 0 volts to at least about 3 volts, the voltage adjustable capacitor further includes a first active terminal, a second active terminal, a first bias terminal, and a second bias terminal, the plurality of active electrodes includes a plurality of first active electrodes electrically connected to the first active terminal, the plurality of active electrodes includes a plurality of second active electrodes electrically connected to the second active terminal, the plurality of bias electrodes includes a plurality of first bias electrodes electrically connected to the first bias terminal, and the plurality of bias electrodes includes a plurality of second bias electrodes electrically connected to the second bias terminal. **Claim 22** A system for adjusting a voltage adjustable capacitor, comprising: one or more control devices including a charge pump; ​ A voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied, the voltage-adjustable capacitor, comprising, the one or more control devices being, receiving at least one input signal, processing the at least one input signal using logic to generate an output signal, boosting the output signal using the charge pump, supplying the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage applied across both ends of the plurality of bias electrodes configured to, the at least one input signal including a manually controlled signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor, the manually controlled signal ranging from about 0 volts to at least about 3 volts, a system in which the thickness of the plurality of dielectric layers ranges from about 0.5 micrometers to about 15 micrometers.

23. A system for adjusting a voltage-adjustable capacitor, one or more control devices including a charge pump, a voltage-adjustable capacitor including a plurality of active electrodes, a plurality of bias electrodes, and a plurality of dielectric layers disposed between the plurality of active electrodes and the bias electrodes, wherein at least a part of the dielectric layer contains an adjustable dielectric material that exhibits a variable dielectric constant when a voltage is applied, the voltage-adjustable capacitor, comprising, the one or more control devices being, receiving at least one input signal, processing the at least one input signal using logic to generate an output signal, boosting the output signal using the charge pump, supplying the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage applied across both ends of the plurality of bias electrodes configured to, the at least one input signal including a manually controlled signal generated to indicate at least one of a desired capacitance or a desired voltage associated with the voltage-adjustable capacitor, the manually controlled signal ranging from about 0 volts to at least about 3 volts, A system in which the thickness of the plurality of dielectric layers ranges from about 15 micrometers to about 150 micrometers.

24. A method for controlling a voltage-adjustable capacitor, comprising: receiving at least one input signal; converting the at least one input signal into at least one digital signal; processing the at least one digital signal using logic to generate an output signal; boosting the output signal using a charge pump to generate the boosted output signal; supplying the boosted output signal to the voltage-adjustable capacitor to adjust a bias voltage of the voltage-adjustable capacitor; wherein a ratio of the bias voltage of the voltage-adjustable capacitor to the voltage of the at least one input signal ranges from about 1 to about 16.

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