Packaged Electronic Circuit with Moisture Protection Encapsulation and Method of Forming the Same

Abstract

To provide a packaged electronic circuit with a protective sealing.SOLUTION: In an electronic circuit, a flat plate capacitor 300 that is used together with a spiral inductor to form an output impedance matching circuit includes a substrate 310 having a top surface, a first metal layer forming a lower electrode 320 on the top surface of the substrate, a capacitor dielectric layer 330 on the first metal layer opposite the substrate, a second metal layer forming an upper electrode 340 on the capacitor dielectric layer opposite the first metal layer, a dielectric crossover 350 on at least a portion of the capacitor dielectric layer and the second metal layer, a protective dielectric layer 360, and a protective polymer layer 370 on the protective dielectric layer.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The concepts of the present invention described herein relate to electronic circuits, and more particularly, to packaged electronic circuits having a protective encapsulation.

Background Art

[0002] A wide variety of packaged electronic circuits are known in the art. These circuits can include one or more semiconductor integrated circuit chips and / or other electronic circuit substrates having individual electronic components such as capacitors, inductors, and / or resistors formed thereon, included within a common protective package. As an example, an internally matched field effect transistor (FET) power amplifier is one type of packaged electronic circuit known in the art. An internally matched FET power amplifier can include one or more integrated circuit chips having a plurality of unit cell transistors arranged in parallel to provide a plurality of parallel amplification paths. For example, the unit cell transistor can comprise a high electron mobility transistor formed using a wide bandgap semiconductor material such as, for example, silicon carbide and / or gallium nitride-based semiconductor materials. The integrated circuit chip can be packaged within a protective package together with other electronic circuit substrates such as, for example, a printed circuit board or a ceramic circuit board, including, for example, an impedance matching network, a transmission line, a power splitting and combining structure, and the like. The protective package can include one or more input and output leads or pads. Bond wires can be used to connect the integrated circuit chip and the electronic circuit substrate to each other and / or to the input / output leads of the protective package.

[0003] A monolithic microwave integrated circuit ("MMIC": monolithic microwave integrated circuit) is another packaged electronic circuit known in the art. The MMIC chip is designed to operate at radio or microwave frequencies, and all of the circuit elements are formed on a single "monolithic" integrated circuit chip encapsulated within a protective package having appropriate inputs and outputs (e.g., leads). Bond wires may be used to electrically connect the circuit elements on the integrated circuit chip to the input / output leads of the protective package. MMIC amplifiers are currently widely used and include high-power MMIC amplifiers (usually used on the transmit side of communication circuits) and low-noise MMIC amplifiers (usually used on the receive side of communication circuits). MMIC amplifiers typically include one or more stages of transistor amplifiers and may further include other elements such as impedance matching networks and feed networks, all implemented on a single integrated circuit chip. MMIC amplifiers typically have a unit cell transistor design where each amplification stage of the device is implemented as a plurality of "unit cell" transistors arranged in parallel to provide a plurality of parallel amplification paths. The unit cell transistors may comprise, for example, high electron mobility transistors formed using a wide bandgap semiconductor material. Other common MMIC devices include RF mixers and high-frequency switching circuits.

[0004] Reliability can be an important performance characteristic for many packaged electronic circuits. For example, MMIC amplifiers are often deployed within or adjacent to the antennas of cellular base stations and can thus be installed dozens or hundreds of feet above the ground. Network outages must be minimized, and replacing a failed "tower top" component requires climbing the tower by trained technicians, which is costly, so cellular base station operators often require a very high level of reliability from component manufacturers.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2017 / 0271497 [Summary of the Invention] [Means for Solving the Problems]

[0006] According to an embodiment of the present invention, a method of fabricating an electronic circuit is provided. According to these methods, a first metal layer is formed on a substrate. A first polymer layer is formed on a portion of the first metal layer at a first temperature. A second metal layer is formed on the first polymer layer on the side opposite to the first metal layer. A dielectric layer is formed on the second metal layer and on the first polymer layer at a second temperature, and the second temperature is lower than the first temperature. A second polymer layer is formed on the dielectric layer at a third temperature, and the third temperature is lower than the second temperature. The electronic circuit can be a packaged electronic circuit.

[0007] In some embodiments, the dielectric layer can be a second dielectric layer, and the method can further include the step of forming a first dielectric layer on the first metal layer before forming the second metal layer. In some such embodiments, the first metal layer, the first dielectric layer, and the second metal layer can form a capacitor.

[0008] In some embodiments, the first polymer layer is formed between the first metal layer and the periphery of the second metal layer, and the first polymer layer has a thickness greater than the thickness of the first dielectric layer in a direction perpendicular to the upper surface of the substrate.

[0009] In some embodiments, the periphery of the second metal layer can be spaced apart from above the first metal layer further than the center of the second metal layer.

[0010] In some embodiments, the first metal layer can be coupled to the gate of a transistor.

[0011] In some embodiments, the first polymer layer may not be disposed between the center of the second metal layer and the first metal layer.

[0012] In some embodiments, the first dielectric layer may be formed on the upper surface of the first metal layer, the first polymer layer may be formed on at least one of the upper surfaces of the first metal layer and the first dielectric layer, the second metal layer may be formed on the upper surface of the first dielectric layer, the second dielectric layer may be formed on the upper surface of the first polymer layer, and the second polymer layer may be formed on the upper surface of the second dielectric layer.

[0013] In some embodiments, the dielectric layer can include silicon and at least one of oxygen and nitrogen, and the first and second polymer layers can each be a carbon-based layer.

[0014] In some embodiments, the dielectric layer and the second polymer layer may be formed on a wafer, and the method may further include a step of dicing the wafer into individual chips after forming the dielectric layer and the second polymer layer.

[0015] In some embodiments, the second metal layer can be a gate jumper coupled between the gate electrode and the gate finger of a transistor.

[0016] In some embodiments, the first metal layer can be a metal trace including a self-bonding section having substantially the same instantaneous current direction.

[0017] In some embodiments, the packaged electronic circuit can be a monolithic microwave integrated circuit.

[0018] In some embodiments, the method may further include a step of forming a plurality of transistors on a substrate. In such embodiments, the dielectric layer may be formed on the upper surface of the transistors, and the second polymer layer may not be formed on the upper surface of the transistors.

[0019] In some embodiments, the first polymer layer and the second polymer layer may be thicker than the first dielectric layer in a direction perpendicular to the upper surface of the substrate.

[0020] According to other embodiments of the present invention, additional methods of fabricating an electronic circuit are provided. According to these methods, a first metal layer is formed on the upper surface of a substrate. A first dielectric layer is formed on the upper surface of the first metal layer. A first polymer layer is formed on the upper surface of the first metal layer, and the first polymer layer has a thickness greater than the thickness of the first dielectric layer in a direction perpendicular to the upper surface of the substrate. A second metal layer is formed on the first dielectric layer on the side opposite to the first metal layer, and the second metal layer extends over the first polymer layer. A second dielectric layer is formed on the second metal layer and on the first polymer layer. A second polymer layer is formed on the second dielectric layer. The first polymer layer is formed between the first metal layer and the periphery of the second metal layer, and the first metal layer, the first dielectric layer, and the second metal layer form a capacitor.

[0021] In some embodiments, the first polymer layer is formed at a first temperature, and the second dielectric layer is formed at a second temperature lower than the first temperature.

[0022] In some embodiments, the second polymer layer is formed at a third temperature lower than the second temperature.

[0023] In some embodiments, the method further includes forming a plurality of transistors on the substrate, the dielectric layer is formed on the upper surface of the transistors, and the second polymer layer is not formed on the upper surface of the transistors.

[0024] In some embodiments, the second dielectric layer and the second polymer layer are formed on a wafer, and the method further includes dicing the wafer into individual chips after the formation of the second dielectric layer and the second polymer layer.

[0025] According to an additional embodiment of the present invention, a method of fabricating an electronic circuit is provided, wherein a first metal trace is formed on a substrate. The first metal trace includes parallel self-coupling sections having substantially the same instantaneous current direction. A first polymer layer is formed on the first metal layer. A second metal layer is formed on the first polymer layer on the side opposite to the first metal layer. A dielectric layer is formed on the second metal layer and on the first polymer layer. A second polymer layer is formed on the dielectric layer.

[0026] According to another additional embodiment of the present invention, an electronic circuit is provided, which includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer on the side opposite to the substrate, a second metal layer on the first polymer layer on the side opposite to the first metal layer, a dielectric layer on at least a portion of the first polymer layer and the second metal layer, and a second polymer layer on the dielectric layer.

[0027] In some embodiments, the second metal layer includes one of a capacitor electrode, a portion of a spiral inductor, and a gate bypass jumper.

[0028] In some embodiments, the dielectric layer includes a second dielectric layer, and the packaged electronic circuit further includes a first dielectric layer between the first metal layer and the second metal layer such that the first metal layer, the first dielectric layer, and the second metal layer form a capacitor.

[0029] In some embodiments, the first polymer layer is formed between the first metal layer and the periphery of the second metal layer, and the first polymer layer has a thickness greater than the thickness of the first dielectric layer in a direction perpendicular to the upper surface of the substrate.

[0030] In some embodiments, the periphery of the second metal layer is spaced further away from the center of the second metal layer and above the first metal layer.

[0031] In some embodiments, the first polymer layer is not between the center of the second metal layer and the first metal layer.

[0032] In some embodiments, the first metal layer is coupled to the gate of the transistor.

[0033] In some embodiments, the second metal layer comprises a gate jumper coupled between the gate electrode of the transistor and the gate fin.

[0034] In some embodiments, the first metal layer comprises a metal trace including a self - coupling section having substantially the same instantaneous current direction.

[0035] In some embodiments, the packaged electronic circuit is a monolithic microwave integrated circuit, a plurality of transistors are provided on a substrate, a dielectric layer is formed on the upper surface of the transistors, and the second polymer layer is not formed on the upper surface of the transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 6C

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0037] Internally matched FET power amplifiers, MMIC chips, and various other packaged electronic circuits can include, for example, combinations of transistors, capacitors, inductors, resistors, circuit traces, and / or dielectric crossovers arranged to implement the desired functionality. In many cases, the packaged electronic circuit will be free of encapsulation except for the protective package. Other packaged electronic circuits include integrated circuit chips or other electronic circuit substrates (collectively referred to herein as “chips”) having so-called “die” level passivation, where a potting material or dielectric layer is deposited on the upper side of the chip after the chip has been singulated from a larger structure (e.g., a semiconductor wafer) by a dicing operation.

[0038] Packaged electronic circuits are often operated at high temperatures (since heat builds up within the packaged electronic circuit during operation), and can also be operated in a high humidity environment for at least some of the time. When a packaged electronic circuit is operated at high temperature in a humid environment, water vapor in the ambient air can result in hydrogen or other ions (e.g., chlorine, sodium) that can lead to undesirable chemical reactions within the packaged electronic circuit. Even when chip-level passivation is provided, small cracks or defects within the passivation layer can allow moisture to pass through the passivation and reach the interior of the device. Ions can act as a catalyst for hydroxide formation or other chemical reactions, particularly when located near a portion of the packaged electronic circuit that is under a high electric field. These chemical reactions can degrade the performance of some of the circuit elements over time and can result in device failure. Most typically, humidity-induced failures in integrated circuit chips or other circuit boards occur in a portion of the device that is energized (i.e., has a voltage applied thereto) and not passivated or insufficiently passivated. Such failures may be referred to herein as "humidity failures in the biased state."

[0039] In accordance with an embodiment of the present invention, there is provided a packaged electronic circuit that includes one or more encapsulated integrated circuit chips or other electronic circuit boards within a protective package. The encapsulation can prevent the ingress of moisture to the electronic circuit elements on the chip. In some embodiments, the moisture encapsulation can be performed at the "wafer" level (i.e., the moisture encapsulation layer is applied during wafer processing before the wafer is diced into a plurality of integrated circuit chips). The encapsulation can include, for example, a protective dielectric layer such as a silicon oxide, silicon nitride, or silicon oxynitride passivation layer, and a protective polymer layer (e.g., a polyimide layer) that overlays the protective dielectric layer. The combination of the protective dielectric layer and the protective polymer layer can encapsulate the circuit elements on the chip and thus provide a moisture barrier that can keep ions from moisture away from the circuit elements.

[0040] In various integrated circuit chip and other electronic circuit board designs, two or more metal layers can be stacked vertically. As used herein, the term "metal layer" encompasses both continuous and patterned metal layers, and two metal layers (or other circuit elements) are "stacked vertically" when an axis perpendicular to the major surface of the chip extends through each of the layers / elements. Examples of such vertically stacked metal layers include the two electrodes of a planar capacitor formed on a circuit board, or the traces of a spiral inductor that cross over the spiral and connect the inner portion of the spiral to circuit elements outside the spiral. In some designs, a so-called dielectric crossover can be placed between two vertically stacked conductive elements to prevent short circuits. In some cases, the dielectric crossover can be formed from a polymer-based material. In such cases, when a dielectric layer is formed over the polymer-based dielectric crossover, pinholes and / or small cracks can occur in the dielectric layer, particularly when the polymer-based dielectric crossover contains depressions or voids. These pinholes / cracks in the dielectric layer can act as a path for moisture ingress through the dielectric layer. Providing a protective polymer layer over the top of the dielectric layer can cover these pinholes / cracks, and thus the dielectric layer and the protective polymer layer together can seal the device for moisture protection purposes.

[0041] In some embodiments, a polymer-based dielectric crossover can be formed (e.g., deposited) on a circuit board at a first temperature. A protective dielectric layer can then be formed on the polymer-based dielectric crossover at a second temperature below the first temperature. By forming the protective dielectric layer at a lower temperature, outgassing of materials within the polymer-based dielectric crossover during the formation of the protective dielectric layer can be reduced or prevented. Such outgassing of materials, if it occurs, can cause pinholes in the thin film, delamination of the thin film layers, or thin film adhesion problems. A protective polymer layer can then be formed on the protective dielectric layer at a third temperature below the second temperature. By forming the protective polymer layer at a temperature lower than the protective dielectric layer (and the polymer-based dielectric crossover), outgassing of materials within the polymer-based dielectric crossover and / or the protective dielectric layer during the formation of the protective polymer layer can be reduced or prevented. As used herein, reference to a layer being formed at a temperature below a particular temperature means that the layer is grown, sprayed, coated, or otherwise deposited at a temperature below the particular temperature, and that post-deposition steps related to the proper formation of the layer, such as an annealing step, are performed at a temperature below the particular temperature.

[0042] In some embodiments, a polymer-based dielectric crossover can be provided under the periphery of the upper electrode of a planar capacitor. In such embodiments, the capacitor can comprise a first metal layer acting as the lower electrode of the capacitor, a second metal layer acting as the upper electrode of the capacitor, and a capacitor dielectric layer disposed between the first and second metal layers, and the lower electrode, the capacitor dielectric layer, and the upper electrode are vertically stacked. The polymer-based dielectric crossover can be formed between the first metal layer and the periphery of the second metal layer, and may not be formed under the central portion of the second metal layer. The polymer-based dielectric crossover can have a thickness greater than the thickness of the capacitor dielectric layer. In an exemplary embodiment, the polymer-based dielectric crossover can have a thickness between 1 and 3 microns, between 3 and 10 microns, or between 10 and 100 microns. Since the polymer-based dielectric crossover can have an increased thickness compared to the capacitor dielectric layer, the periphery of the second metal layer can be spaced further above the first metal layer than the central portion of the second metal layer.

[0043] In other embodiments, a polymer-based dielectric crossover can be used to isolate a spiral inductive trace formed in the first metal layer from a connection trace that is part of the second metal layer. The connection trace connects the end of the spiral inductive trace inside the spiral to a circuit element outside the spiral. The spiral inductive trace can include parallel sections having the same or substantially the same instantaneous current direction.

[0044] In other embodiments, the packaged electronic circuit can comprise a power amplifier integrated circuit chip having gate jumpers and segmented gate fingers. The gate jumpers can be formed at different vertical levels (above the underlying substrate) on the chip compared to the gate fingers, and the polymer-based dielectric crossover is provided between the gate jumpers and the underlying conductive layer.

[0045] According to another embodiment of the present invention, a packaged electronic circuit is provided, and the negatively biased electrodes of the capacitors included within the device are all positioned closer to the substrate than the electrodes coupled to a higher voltage (e.g., ground, positive voltage, or a smaller negative voltage). This configuration moves the electrodes of the capacitors that receive a high negative voltage further away from the upper surface of the device, and thus further away from a potential source of ions that can lead to device failure, for example, during a humidity accelerated stress test.

[0046] Next, embodiments of the present invention will be described in more detail with reference to the accompanying figures. Before describing the encapsulation techniques according to embodiments of the present invention, two exemplary packaged electronic circuits that may include the encapsulation techniques according to embodiments of the present invention will be described with reference to FIGS. 1 and 2.

[0047] FIG. 1 is a schematic plan view (i.e., a view looking down on the device from above) of a packaged internally matched FET power amplifier 100 that includes a plurality of electronic circuit boards included within package 110. The electronic circuit boards can include one or more integrated circuit chips, and can also include other electronic circuit boards such as, for example, printed circuit boards or ceramic circuit boards. As used herein, integrated circuit chips and other electronic circuit boards such as printed circuit boards or ceramic circuit boards may be collectively referred to as "chips." In FIG. 1, package 110 is shown in a shadow view to illustrate the various elements within package 110. Package 110 includes an input lead 112 electrically connected to input pad 114 and an output lead 118 electrically connected to output pad 116.

[0048] As shown in FIG. 1, the circuit board may include input / output circuit boards 130-1 and 130-2, impedance matching circuit boards 140-1, 140-2, 140-3, and 140-4, and field effect transistor amplifier integrated circuit chips 150-1 and 150-2. Bond wires 120 are provided to interconnect circuit boards 130, 140, and 150 and to connect circuit board 130 to package 110. In this specification, when two or more instances of a particular element are included in a device, the elements may be referred to individually by their full reference numbers (e.g., transistor amplifier integrated circuit chip 150-2) and collectively by the first part of the reference number (e.g., transistor amplifier integrated circuit chip 150).

[0049] Each input / output circuit board 130 may comprise a ceramic circuit board (e.g., an alumina substrate) having, for example, a conductive ground plane on one side thereof and conductive traces forming pads such as RF transmission lines 134 and input / output bond pads 132 on the opposite side thereof. The RF transmission lines 134 form a parallel feed network 136 that connects the input / output bond pads 132 to the gate fingers of the unit cell transistors included in the transistor amplifier integrated circuit chips 150.

[0050] The unit cell transistors for amplifying the input signal are mounted on the first and second transistor amplifier integrated circuit chips 150-1 and 150-2. Examples of suitable integrated circuit chips are disclosed, for example, in U.S. Patent Application Publication No. 2017 / 0271497, the entire content of which is incorporated herein by reference as if fully set forth herein.

[0051] The impedance of each transistor amplifier integrated circuit chip 150 typically becomes not well matched to the impedance seen at the input lead 112 or the output lead 118 (which can be, for example, 50 ohms each). Accordingly, the internally matched FET power amplifier 100 further includes an impedance matching circuit board 140 that improves the impedance matching between the transistor amplifier integrated circuit chip 150 and the input lead 112 and the output lead 118 over the operating frequency band of the internally matched FET power amplifier 100. Each input impedance matching circuit board 140 can include a transmission line and reactive components such as capacitors and / or inductive elements.

[0052] Each impedance matching circuit board 140 can comprise a substrate such as a ceramic substrate (e.g., an alumina substrate) or a printed circuit board, having, for example, capacitors, inductors, and / or resistors formed thereon. In some cases, the bond wires 120 extending between the circuit boards 130, 140, 150 can act as inductors and capacitors can be formed on the circuit board 140, such that, for example, an inductor-capacitor-inductor (LCL) reactive circuit is formed at the input and output of each transistor amplifier integrated circuit chip 150.

[0053] FIG. 2 is a schematic plan view of a two-stage MMIC power amplifier 200 including a matching circuit. As shown in FIG. 2, the MMIC amplifier 200 includes an FET driver stage 210 and an FET output stage 220, which represent the two amplification stages of the two-stage MMIC amplifier 200. The MMIC amplifier 200 further includes an input impedance matching circuit 230-1, an inter-stage impedance matching circuit 230-2, and an output impedance matching circuit 230-3. Input pads 240 and output pads 242 are also provided together with other pads 244 that provide power and ground connections for the MMIC amplifier 200.

[0054] An input signal (e.g., a 700 MHz RF signal) can be input to the MMIC amplifier 200 at the input pad 240. The input signal passes through an input stage impedance matching circuit 230-1 that can improve the impedance matching between the input of the FET driver stage 210 and the input pad 240. The FET driver stage 210 amplifies the RF signal input thereto, resulting in a higher-power RF signal. The higher-power RF signal output by the FET driver stage 210 can be provided as an input signal to the FET output stage 220 (after appropriate impedance matching by the inter-stage impedance matching circuit 230-2). The FET output stage 220 further amplifies the RF signal. The high-power RF signal output by the FET output stage 220 passes through the output stage impedance matching circuit 230-3 and is output at the output pad 242. The FET driver stage 210 and the FET output stage 220 can each be implemented, for example, as a plurality of unit cell FET transistors (e.g., HEMT transistors) electrically connected in parallel to each other.

[0055] Each of the impedance matching circuits 230 can include, for example, one or more capacitors, inductors, resistors, and / or other circuit elements arranged to improve the matching from the impedance of the RF signal input at the input of the impedance matching circuit 230 to the impedance of the circuit elements at the output of the impedance matching circuit 230. The impedance matching circuit 230 is schematically illustrated in FIG. 2, and the planar capacitor 300 and the spiral inductor 400 are illustrated to exemplify a typical implementation form of these components within the output impedance matching circuit 230-3.

[0056] As described above, both the internally matched FET 100 and the MMIC amplifier 200 include reactive components such as capacitors and / or inductors. FIG. 3 is a schematic cross-sectional view of a capacitor 300' having a design similar to that of the capacitor 300 shown in FIG. 2, except that the capacitor 300' does not include a moisture seal. For context, the cross-section of FIG. 3 is taken along line 3-3' of FIG. 2 (as an added note, the capacitor 300' of FIG. 3 does not include a moisture seal).

[0057] As shown in FIG. 3, the capacitor 300' can be formed on a substrate 310. When the capacitor 300' is included in an MMIC device such as the MMIC amplifier 200 of FIG. 2, the substrate 310 can typically be a semiconductor substrate such as a silicon carbide substrate or any other substrate on which a semiconductor layer can be grown, such as a sapphire substrate. However, it will be recognized that in other cases, such as when the capacitor 300' is used in one of the impedance matching circuit substrates 140 of the internally matched FET 100 of FIG. 1, the substrate 310 can comprise some other type of substrate, such as a printed circuit board or a ceramic substrate. Also, it will be recognized that the term "substrate" as used herein is used broadly to encompass a substrate having other layers grown or formed thereon, such as a bare substrate, or a semiconductor or non-semiconductor substrate having an epitaxial layer, a dielectric layer, a metal layer, etc. formed thereon.

[0058] The first metal layer can be formed on the substrate 310 and acts as the lower electrode 320 of the capacitor 300'. The capacitor dielectric layer 330 is formed on the upper surface of the lower electrode 320. For example, any suitable capacitor dielectric layer can be used, including silicon oxide, silicon nitride, high-k dielectric layers, etc. The second metal layer is formed on the capacitor dielectric layer 330 and acts as the upper electrode 340 of the capacitor 300. The dielectric crossover 350 is placed between the lower electrode 320 and the upper electrode 340 around the periphery of the capacitor 300'. In some embodiments, the dielectric crossover 350 can comprise a dielectric material (including air) that is significantly thicker (in the direction perpendicular to the substrate) than the capacitor dielectric layer 330. The dielectric crossover 350 can comprise, for example, a carbon-based polymer material such as polyimide or bcb cyclotene, PBO (P-phenylene-2,6-benzobisoxazole), polyamide, spin-on glass, etc. Including the dielectric crossover 350 around the periphery of the capacitor 300' can improve the reliability of the capacitor 300'. The dielectric crossover 350 is not placed between the central portions of the lower and upper electrodes 320, 340. In the illustrated embodiment, the capacitor dielectric layer 330 is provided between the lower electrode 320 and the dielectric crossover 350, but as shown in FIG. 8, it will be recognized that in other embodiments, the capacitor dielectric layer 330 can be completely or partially omitted in this region of the capacitor.

[0059] When the capacitor 300’ of FIG. 3 operates in a humid environment, water vapor in the ambient air can act as a source of hydrogen ions (or other halogen ions) that can lead to undesirable chemical reactions within the packaged electronic circuit. When such ions are located near a part of the packaged electronic circuit under an electric field, the ions can act as a catalyst for hydroxide formation or other chemical reactions. These chemical reactions can degrade the performance of some of the circuit elements. This can short-circuit the capacitor 300’, resulting in a failure of the packaged electronic circuit (e.g., the MMIC amplifier 200 of FIG. 2, or the internally matched FET 100 of FIG. 1) that includes the capacitor 300’. For example, the packaged electronic circuit can be subjected to a humidity-accelerated stress test to ensure that the packaged electronic circuit does not fail prematurely due to a humidity-induced failure mechanism. High-power packaged electronic circuits are particularly prone to failure because the high electric fields and higher operating temperatures associated with such devices can result in increased ion migration and accelerated chemical reactions. The humidity-accelerated stress test can involve placing the packaged electronic circuit in a high-humidity, high-pressure environment for several hours or days while the device operates at or near its rated maximum power capability. These stress tests can be performed prior to packaging the chips included within the device. If the chip has moisture pathways that can lead into the interior of the chip, the circuit is typically more likely to fail during the stress test by a short circuit that permanently damages the device. Thus, while the stress test can identify devices that are susceptible to humidity-induced failures, the stress test also reduces manufacturing yield.

[0060] FIG. 4 is a schematic cross-sectional view of a capacitor 300 according to an embodiment of the present invention that includes a moisture seal.

[0061] Referring to FIG. 4, capacitor 300 may include one or more protective layers that encapsulate the capacitor to protect against such moisture ingress. For example, a protective dielectric layer 360 may be formed that encapsulates the upper surface of capacitor 300. The protective dielectric layer 360 may comprise, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, etc. The protective dielectric layer 360 may be formed by any suitable means including chemical vapor deposition and / or atomic layer deposition. In some embodiments, the protective dielectric layer 360 may be deposited entirely over the top surface of the chip including capacitor 300. In some embodiments, the protective dielectric layer 360 may be formed during wafer processing (i.e., before the wafer is diced to yield multiple chips). In such embodiments, the protective dielectric layer 360 may be deposited entirely over the wafer, or entirely except for portions along scribe lines along which the wafer will later be diced. In some embodiments, the protective dielectric layer 360 may be made prior to any "backside processing" of the wafer, such as any grinding operations to reduce the thickness of the substrate, drilling of via holes within the wafer, and / or backside metallization.

[0062] When the protective dielectric layer 360 is formed on the sidewalls of the underlying layer, especially when the protective dielectric layer 360 is formed using chemical vapor deposition, it may not provide a good coverage rate. In addition, the dielectric crossover 350 may contain voids, especially when the dielectric crossover 350 is formed by chemical vapor deposition, for example, within the region labeled 352 in FIG. 3. When the protective dielectric layer 360 is formed on this void 352, microcracks can be formed within the protective dielectric layer 360 that can act as a path for moisture intrusion through the protective dielectric layer 360. Accordingly, as shown in FIG. 4, a protective polymer layer 370 can be formed on the protective dielectric layer 360 to block those paths. The protective polymer layer 370 can also be formed before the backside processing of the wafer. The protective polymer layer 370 can comprise, for example, bcb cyclotene, PBO (P-phenylene-2,6-benzobisoxazole), polyamide, spin-on glass, a permanent resist such as SU-8 2000 - MicroChem, an epoxy molding compound, an epoxy resin, and the like.

[0063] The capacitor 300 can be formed, for example, by sequentially forming a lower electrode 320, a capacitor dielectric layer 330, and an upper electrode 340 using conventional deposition, masking, and etching processes. The dielectric crossover 350 can be formed before or after the upper electrode 340. The dielectric crossover 350 can substantially fill the space between the outer periphery of the upper electrode 340 and the lower electrode 320 as shown in FIG. 8, or alternatively, the space between the outer periphery of the upper electrode 340 and the capacitor dielectric layer 330 as shown in FIG. 3. The dielectric crossover 350 may not be formed in the middle portion of the capacitor (i.e., it is formed only along the outer edge). In some embodiments, the dielectric crossover 350 can be formed after the formation of the upper electrode 340. As discussed above, the dielectric crossover 350 can include, for example, a carbon-based polymer layer. The dielectric crossover 350 can be formed at a first temperature. In some embodiments, the first temperature can be higher than 200°C. In some embodiments, the first temperature can be between 200°C and 450°C. In other embodiments, the first temperature can be higher than 220°C or 240°C. In some additional exemplary embodiments, the first temperature can be between 220°C and 450°C, between 220°C and 400°C, between 240°C and 450°C, or between 240°C and 400°C.

[0064] The protective dielectric layer 360 can be formed over the dielectric crossover 350 and the upper electrode 340. In some embodiments, the protective dielectric layer 360 can be deposited entirely to cover the entire chip or the entire wafer including a plurality of chips. The protective dielectric layer 360 can be formed at a second temperature. The second temperature can be lower than the first temperature. This can reduce or prevent the gas emission of materials from the dielectric crossover. In some embodiments, the second temperature can be at least 160°C or at least 180°C while being lower than the first temperature. In some exemplary embodiments, the second temperature can also be between 160°C and 400°C, between 180°C and 400°C, between 160°C and 340°C, or between 180°C and 340°C while being lower than the first temperature.

[0065] The protective polymer layer 370 can be formed on the protective dielectric layer 360. In some embodiments, the protective polymer layer 370 can be deposited entirely to cover the entire chip or wafer. In other embodiments, the protective polymer layer 370 can be deposited entirely and then selectively removed (e.g., by etching or photolithography), or alternatively, the protective polymer layer 370 can be selectively deposited so as to cover only a part of the chip (including the part having the dielectric crossover 350). For example, in some embodiments, the protective polymer layer 370 may not cover some or all of the transistors included on the chip. Omitting (or removing) the protective polymer layer 370 from above the transistors can improve the performance of the transistors, especially in high-frequency (e.g., RF) applications. Omitting the protective polymer layer 370 above the transistors also facilitates allowing the heat generated in the FET transistors during device operation to dissipate from the chip. The dashed box labeled 250 in FIG. 2 illustrates the region of the MMIC chip 200 where the protective polymer layer 370 can be omitted. The protective dielectric layer 360 can be deposited entirely over the entire upper surface of the MMIC amplifier 200, and the protective polymer layer 370 can be provided over the entire upper surface except within the dashed box 250.

[0066] The protective polymer layer 370 can be formed at a third temperature. The third temperature can be less than the second temperature. This can reduce or prevent the gas evolution of materials from the dielectric crossover 350 and / or the protective dielectric layer 360. In some embodiments, the third temperature can be at least 130 °C or at least 150 °C while being less than the second temperature. In some exemplary embodiments, the third temperature can also be between 130 and 240 °C, between 130 and 200 °C, between 150 and 240 °C, or between 150 and 200 °C while being less than both the first temperature and the second temperature. The protective polymer 370 can be cured so that the polymer is at least partially crosslinked.

[0067] For example, the protective polymer layer 370 may comprise a carbon-containing material such as polyimide. In some embodiments, the protective polymer layer 370 may be spin-coated onto the chip.

[0068] In a typical design, the first metal layer forming the lower electrode 320 for the capacitor 300 may have a thickness of, for example, about 1 to 5 microns. The capacitor dielectric layer 330 can have a thickness of, for example, 0.1 to 0.7 microns, and the thickness can be varied based on the material used to form the capacitor dielectric layer 330 (or its dielectric constant) and the desired level of capacitance of the capacitor 300. The second metal layer forming the upper electrode 340 may have a thickness of, for example, about 1 to 5 microns. The polymer-based dielectric crossover 350 can have a thickness of, for example, about 1 to 3 microns. The protective dielectric layer 360 can be a thinner layer having a thickness of, for example, about 0.2 to 1 micron in some embodiments. In other embodiments, the thickness can be between 0.4 and 0.8 microns, or between 0.4 and 0.6 microns. The protective polymer layer 370 can have a thickness of about 1.5 to 5 microns in some embodiments. In other embodiments, the thickness can be between 2.0 and 4.0 microns, or between 2.5 and 3.5 microns.

[0069] In other embodiments, the protective polymer layer 370 may be formed on the dielectric crossover 350, and then the protective dielectric layer 360 can be formed on the protective polymer layer 370. The protective polymer layer 370 and the dielectric crossover 350 can be made of different materials. In such embodiments, the protective dielectric layer 360 can be deposited at least in part by atomic layer deposition.

[0070] In some embodiments, additional layers may be formed on the dielectric crossover 350. For example, an adhesive layer may be provided between the protective dielectric layer 360 and the protective polymer layer 370. Further, in the illustrated embodiments, the capacitor dielectric layer 330 is provided between the lower electrode 320 and the dielectric crossover 350, but it will be appreciated that in other embodiments, the capacitor dielectric layer 330 may be completely or partially omitted in this region of the capacitor.

[0071] In some embodiments, the protective dielectric layer 360 and the protective polymer layer 370 may be formed before dicing the semiconductor wafer. For example, the protective dielectric layer 360 and the protective polymer layer 370 may be formed after the processing on the upper (device) side of the wafer is completed, but before wafer grinding to reduce its thickness, formation of via holes through the wafer, and / or backside processing of the wafer such as backside metallization. Also for example, it will be appreciated that other layers such as an adhesive layer may be formed directly under the protective dielectric layer 360 and / or between the protective dielectric layer 360 and the protective polymer layer 370.

[0072] As described above, when a dielectric crossover is included on a circuit board, small voids can occur within its upper surface, particularly at the upper edge of the dielectric crossover. When a passivation layer is formed over these voids, microcracks may occur within the passivation layer, which can act as a moisture path into the device. As discussed above with reference to FIGS. 3 and 4, the dielectric crossover can be used within a capacitor, but it will be appreciated that the dielectric crossover can be used in the formation of other circuit elements such as inductors and gate jumpers.

[0073] For example, FIG. 5 is a cross-sectional view taken along line 5-5' of FIG. 2, which illustrates in detail the design of one of the inductors 400 of the MMIC amplifier 200. The inductor 400 also includes a seal according to an embodiment of the present invention. It will be recognized that the inductor 400 can also be included in one of the impedance matching circuit boards 140 of the internally matched FET amplifier 100 of FIG. 1.

[0074] As shown in FIG. 5, the inductor 400 can be formed on a substrate 410. In the embodiment of FIG. 5 where the inductor 400 is part of an MMIC device, the substrate 410 can typically be a semiconductor substrate such as a silicon carbide substrate, or a substrate such as a silicon or sapphire substrate on which a semiconductor layer can be grown. The substrate 410 can include an epitaxially grown semiconductor layer. However, in other cases, such as when the inductor 400 is part of one of the impedance matching circuit boards 140 of the internally matched FET 100 of FIG. 1, it will be recognized that the substrate 410 can comprise some other type of substrate, such as a printed circuit board or a ceramic substrate.

[0075] The first metal trace 420 can be formed on the substrate 410. The metal trace 420 can have a spiral shape (see FIG. 2). As a result, the first metal trace 420 has adjacent parallel sections with intervals having substantially the same instantaneous current direction. The second metal trace 440 is formed on the first metal trace 420. The dielectric crossover 450 is placed between the first metal trace 420 and the second metal trace 440 to prevent a short circuit between the first and second metal traces 420, 440. The dielectric crossover 450 can comprise, for example, a carbon-based polymer material such as polyimide, or any of the materials discussed above that can be used to form the dielectric crossover 350.

[0076] The inductor 400 further includes a protective dielectric layer 460 and a protective polymer layer 470 that are sequentially formed on the second metal trace 440 and the dielectric crossover 450. The protective dielectric layer 460 may seal the upper surface of the inductor 400. The protective dielectric layer 460 may include, for example, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, etc. The protective dielectric layer 460 may be formed by any suitable means including chemical vapor deposition and / or atomic layer deposition. In some embodiments, the protective dielectric layer 460 may be deposited entirely over the top surface of the chip. In some embodiments, the protective dielectric layer 460 may be formed during wafer processing (i.e., before the wafer is diced to provide multiple chips). In such embodiments, the protective dielectric layer 460 may be deposited entirely over the wafer or entirely except for portions along scribe lines along which the wafer will later be diced. The protective polymer layer 470 may be formed on the protective dielectric layer 460. The protective dielectric layer 460 and the protective polymer layer 470 may be the same as the protective dielectric layer 360 and the protective polymer layer 370 discussed above with reference to FIG. 4, and thus further description thereof is omitted.

[0077] When manufacturing the inductor 400, the dielectric crossover 450 can be formed at a first temperature (e.g., a temperature between 200 and 450 °C). The protective dielectric layer 460 can be formed on the dielectric crossover 450 and the second metal trace 440. The protective dielectric layer 460 can be formed at a second temperature below the first temperature to prevent gas release of materials from the dielectric crossover 450 or other underlying layers of the device. In some embodiments, the second temperature can also be between 180 and 400 °C while being below the first temperature. The protective polymer layer 470 can be formed on the protective dielectric layer 460 at a third temperature below the second temperature to prevent gas release from the underlying layers. In some embodiments, the third temperature can also be between 150 and 240 °C while being below both the first temperature and the second temperature. The protective polymer layer 470 can be cured or partially cured in some embodiments such that the polymer crosslinks. The protective polymer layer 470 can comprise, for example, a carbon-containing material. In some embodiments, the protective polymer layer 470 can be spin-coated on the chip. It will be recognized that the additional ranges for the first, second, and third temperatures discussed above with reference to the embodiment of FIG. 3 are equally applicable to this embodiment.

[0078] In some embodiments, the protective polymer layer 470 may be deposited entirely to cover the entire chip. In other embodiments, the protective polymer layer 470 may be deposited entirely and then selectively removed (e.g., by etching or photolithography), or alternatively, the protective polymer layer 470 may be selectively deposited so as to cover only a portion of the chip (including the portion having the dielectric crossover 450). For example, in some embodiments, the protective polymer layer 470 need not cover some or all of the transistors included on the chip. Omitting (or removing) the protective polymer layer 470 from above the transistors can improve the performance of the transistors, particularly in high-frequency (e.g., RF) applications. Omitting the protective polymer layer 470 above the transistors also facilitates allowing the heat generated within the transistors during device operation to dissipate from the chip.

[0079] According to other embodiments of the present invention, a power amplifier integrated circuit chip having a moisture seal is provided. These integrated circuit chips may include a plurality of unit cell transistors. In some embodiments, the transistor may include a gate jumper that provides a low-resistance connection between the gate electrode or gate pad and each portion of a plurality of segmented gate fingers. The dielectric crossover may be provided between the gate jumper and a conductive portion, such as a source region for the transistor, below the device. To seal these dielectric crossovers, a moisture sealing technique according to an embodiment of the present invention can be used, thereby reducing or preventing the intrusion of moisture in the vicinity of each dielectric crossover.

[0080] 6A-6C are a schematic plan view and a pair of schematic cross-sectional views of a portion of a power amplifier integrated circuit chip 500 including a moisture seal according to an embodiment of the present invention. In FIG. 6A, only the metal portions of the device are shown to better illustrate the device structure.

[0081] As shown in FIGS. 6A to 6C, the power amplifier 500 includes a semiconductor structure 520 including one or more layers, such as, for example, a substrate 501, a channel layer 502, and a barrier layer 504. Other layers (not shown) may be included in the semiconductor structure 520. The plan view of FIG. 6A is simplified for easy understanding and includes a gate pad 512 connected to a gate bus 514 and a drain pad 532 connected to a drain bus 534. Although the source pad and the source bus are omitted from FIG. 6A for simplicity of the drawing, it will be understood that one or both of the source pad and the source bus may be provided to electrically connect each of the source contacts shown in FIG. 6A.

[0082] As shown in FIGS. 6A to 6C, a plurality of gate fingers 516 are connected to the gate bus 514 and extend in the y direction. In the illustrated embodiment, each gate finger 516 is divided in the y direction into three gate finger segments 516a, 516b, and 516c separated from each other by gaps. In other embodiments, the gate fingers 516 need not be segmented in this form, and instead it will be recognized that each gate finger 516 may comprise a single integrated gate finger. A plurality of drain contacts 536 are connected to the drain bus 534 and extend in parallel with and adjacent to each of the gate fingers 516. A source contact 562 is also provided and extends in the y direction in parallel with adjacent ones of the gate fingers 516. The source contact 562 is also divided in the y direction into respective source contact segments 562a, 562b, and 562c separated from each other by gaps. The source contact segments 562a, 562b, 562c may be electrically connected to each other, for example, by source contact plugs (not shown) that electrically connect each of the source contact segments 562a, 562b, 562c to a common conductive layer acting as a source bus.

[0083] The gate fingers 516 extend in parallel with the source contacts 562. Since the gate fingers 516 and the source contacts 562 are segmented, a plurality of unit cells are defined along each gate finger 516. The power amplifier 500 further includes a plurality of gate jumpers 572 that extend along the y-direction in parallel with the gate fingers 516. The gate jumpers 572 can be formed at a level different from the levels of the source contact segments 562, the gate fingers 516, and the gate bus 514. The gate jumpers 572 can be formed on the source contacts 562 and can be insulated from the source contacts 562, for example, by the dielectric crossover 550. The gate jumpers 572 are electrically connected to the gate bus 514. The gate jumpers 572 can electrically connect some or all of the gate finger segments 516a - 516c to the gate bus 514.

[0084] FIG. 6B is a cross-section taken along line 6B - 6B' of FIG. 6A. FIG. 6C is a cross-section taken along line 6C - 6C' of FIG. 6A. As can be seen in FIGS. 6B and 6C, each gate jumper 572 can be electrically connected to the gate finger segments 516b, 516c through the gate signal distribution bar 574 and the vertical contact plug 576 to electrically connect each gate finger segment 516b - 516c to the gate bus 514. The gate signal distribution bar 574 can be formed in a metal layer higher than the gate fingers 516 within the device. The vertical contact plug 576 can connect the gate signal distribution bar 574 to the gate finger segments 516b, 516c.

[0085] The gate jumper 572 is wider and / or thicker than the gate finger segments 516a - 516c. The signal applied to the gate bus 514 is carried through the gate jumper 574 to the gate finger segments 516b, 516c. The larger cross - sectional area of the gate jumper 572 can better handle a higher current density compared to the gate finger 516 without the problems typically associated with increased gate widths, such as electromigration and degradation of high - frequency gain performance.

[0086] The dielectric crossover 550 can be used to electrically isolate the source contact segments 562a - 562c from their respective gate jumpers 572. As can be seen from FIGS. 6B and 6C, the protective dielectric layer 560 and the protective polymer layer 570 are formed over the gate jumper 572 and the dielectric crossover 550. The dielectric layer 560 may be the same as the dielectric layers 360, 460 described above, and the protective polymer layer 570 may be the same as the protective polymer layers 370, 470 described above.

[0087] According to other embodiments of the present invention, MMIC power amplifiers are provided that can exhibit improved reliability when operating in a humid environment. These MMIC power amplifiers can include the above - described humidity - protecting encapsulation including a protective dielectric layer and a protective polymer layer formed on a pair of metal layers separated by a dielectric crossover. Additionally, the connections to the electrodes of the capacitors included in these MMIC power amplifiers can be oriented in a way that reduces the likelihood of humidity - induced failures in the bias state.

[0088] Specifically, it has been discovered that the polarity of the capacitor can be a major mechanism for humidity failures in the bias state of the MMIC power amplifier. As discussed above, capacitors are typically included on the MMIC power amplifier as part of an impedance matching circuit used to improve impedance matching and thus the reflection attenuation performance of the device. These capacitors are often electrically connected between the gate electrode of the transistor and ground (either the source electrode or the drain electrode is also coupled to ground). Capacitors are typically implemented as parallel plate capacitors formed using two metal layers separated by a capacitor dielectric layer, as shown above with reference to FIGS. 2 and 3.

[0089] Ion ingress can occur into the dielectric crossover through any of the passivation layers or humidity protection encapsulation. As described above, one electrode of the capacitor may be coupled to ground and the other electrode may be coupled to the gate electrode and thus may have a large negative bias voltage applied thereto. When the upper electrode of the capacitor is coupled to the gate electrode, ions that penetrate into the dielectric crossover through the encapsulation can be subjected to a high electric field. When this occurs, the ions can become mobile and act as a catalyst for hydroxide formation and subsequent ionic reactions near the capacitor. These reactions can result in the development of a short circuit, which typically results in device failure.

[0090] According to an embodiment of the present invention, the electrodes of each capacitor in the MMIC power amplifier coupled to the gate fingers of the transistor can be the lower electrodes because the lower electrodes are far from the humidity protection encapsulation. This design moves the negatively biased electrode of the capacitor far from the potential source of ions, which can significantly reduce the humidity failure rate in the bias state for the MMIC power amplifier.

[0091] FIG. 7 is a flow chart of a method of fabricating a packaged electronic circuit according to some embodiments of the present invention. As shown in FIG. 7, the process may begin with forming a first metal layer on a substrate (block 600). Next, a first polymer layer may be formed at a first temperature on top of at least a portion of the first metal layer (block 610). Next, a second metal layer is formed on top of the first polymer layer on the side opposite to the first metal layer (block 620). Next, a dielectric layer is formed at a second temperature on top of the second metal layer and on top of the first polymer layer (block 630). The second temperature can be less than the first temperature. Finally, a second polymer layer is formed at a third temperature on top of the dielectric layer (block 640). The third temperature can be less than the second temperature.

[0092] As used herein, terms such as first, second, etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element can also be called the second element, and similarly, the second element can also be called the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0093] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" include the plural forms as well, unless the context clearly dictates otherwise. Further, as used herein, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated features, integer values, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integer values, steps, operations, elements, components, and / or groups thereof.

[0094] Unless otherwise defined, all terms (including technical and scientific terms) used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, the terms used herein shall be interpreted to have a meaning consistent with their meaning in the context of this specification, and it will be understood that they are not to be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0095] When an element such as a layer, region, or substrate is referred to as being "on" or "extending onto" another element, it will be understood that it can be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. Also, when an element is referred to as being "connected to" or "coupled to" another element, it will be understood that it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements.

[0096] Relative terms such as "under", "above", "upper", "lower", "horizontal", "lateral", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as illustrated in the figures. It will be understood that these terms encompass different orientations of the device in addition to the orientation shown in the figures.

[0097] Embodiments of the present invention will be described with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shape of the illustrative drawings should be expected, for example, as a result of manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein, but rather include variations in shapes that result from, for example, manufacturing.

[0098] In the drawings and specification, typical embodiments of the invention are disclosed and specific terms are employed, but they are used in a general and descriptive sense only and not for purposes of limitation, and the scope of the invention is defined in the appended claims.

Claims

1. A method of fabricating an electronic circuit, comprising: forming a first metal trace on a substrate, the first metal trace including parallel self-coupling sections having substantially the same instantaneous current direction; forming a first polymer layer on the first metal trace; forming a second metal trace on the first polymer layer on the side opposite to the first metal trace; forming a dielectric layer on the second metal trace and on the first polymer layer; forming a second polymer layer on the dielectric layer; wherein the first polymer layer is formed at a first temperature, the dielectric layer is formed at a second temperature lower than the first temperature, and the second polymer layer is formed at a third temperature lower than the second temperature.

2. The method according to claim 1, wherein the first metal trace has a spiral shape.

3. The method according to claim 1, wherein the electronic circuit includes an inductor.

4. The method according to claim 3, wherein the dielectric layer seals the upper surface of the inductor.

5. The method according to claim 1, wherein the dielectric layer includes a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer.

6. The method according to claim 1, wherein the first temperature is between 200 and 450 °C, the second temperature is between 180 and 400 °C, and the third temperature is between 150 and 240 °C.

7. The method according to claim 1, wherein the substrate is a printed circuit board or a ceramic substrate.

8. The method according to claim 1, wherein the substrate is a silicon carbide substrate.

9. The method according to claim 1, wherein the electronic circuit includes a monolithic microwave integrated circuit amplifier.

10. The method according to claim 1, wherein the electronic circuit includes an internally matched field effect transistor amplifier.

11. The method according to claim 1, wherein the dielectric layer is formed by chemical vapor deposition and / or atomic layer deposition.

12. The method according to claim 1, wherein the second polymer layer includes a carbon-containing material.

13. The method according to claim 1, wherein the second polymer layer is deposited by spin coating.

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