Silicon carbide semiconductor device

Abstract

To provide a SiC semiconductor device in which the occurrence of SSF can be suppressed while the increase in on-resistance is suppressed.SOLUTION: A SiC semiconductor device includes: a semiconductor substrate 10 formed of SiC and having one surface 10a and the other surface 10b; an element region 1 formed on the semiconductor substrate 10 and having a switching element where a parasitic diode is formed; a diode region 2 formed on the semiconductor substrate and having a diode element; a first electrode 30 disposed on the one surface side of the semiconductor substrate 10 and electrically connected to the switching element and the diode element; and a second electrode 33 disposed on the other surface 10b side of the semiconductor substrate 10 and electrically connected to the switching element and the diode element. The diode element formed in the diode region has lower forward voltage at which forward current starts to flow than the parasitic diode.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device composed of silicon carbide (hereinafter also simply referred to as SiC).

Background Art

[0002] Conventionally, a SiC semiconductor device has been proposed in which a MOSFET (abbreviation for metal oxide semiconductor field effect transistor) having a base layer, a source region, etc. is formed on a semiconductor substrate made of SiC. Specifically, this SiC semiconductor device includes a semiconductor substrate made of SiC in which an n + -type substrate has an n - -type drift layer and a p-type base layer laminated in order, and a source region is formed in the surface layer portion of the base layer. Further, in this SiC semiconductor device, a trench is formed that penetrates the base layer and the source region and reaches the drift layer. And a gate insulating film and a gate electrode are formed in the trench in order.

[0003] On one surface side of the semiconductor substrate, a first electrode connected to the source region and the base layer is arranged. On the other surface side of the semiconductor substrate, a second electrode connected to the substrate constituting the drain region is arranged.

[0004] In such a SiC semiconductor device, it has been reported that a basal plane dislocation (hereinafter also referred to as BPD) is included in the semiconductor substrate made of SiC. Further, in such a SiC semiconductor device, a parasitic diode is formed including the base layer and the drift layer. And in such a SiC semiconductor device, when the parasitic diode operates, holes are injected into the drift layer, and the injected holes recombine with electrons at the BPD to form a single shockley-type stacking fault (hereinafter also simply referred to as SSF). SSF is a defect that is more likely to degrade the characteristics of the SiC semiconductor device than BPD.

[0005] For this reason, for example, Patent Document 1 proposes forming a lifetime killer in the drift layer to reduce the hole concentration when the parasitic diode operates and make it difficult to form the SSF.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, when a SiC semiconductor device is configured by forming a lifetime killer in the drift layer, there is a concern that the on-resistance increases.

[0008] In view of the above points, an object of the present invention is to provide a SiC semiconductor device capable of suppressing the occurrence of SSF while suppressing an increase in on-resistance.

Means for Solving the Problems

[0009] Claim 1 for achieving the above object 、3、5 A SiC semiconductor device composed of SiC, comprising: a semiconductor substrate (10) composed of SiC and having one surface (10a) and the other surface (10b) opposite to the one surface; an element region (1) formed on the semiconductor substrate and having a switching element that constitutes a parasitic diode; a diode region (2) formed on the semiconductor substrate and having a diode element; a first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element; and a second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element, wherein the diode element formed in the diode region has a forward voltage at which a forward current starts to flow that is smaller than that of the parasitic diode. Further, in claim 1, contact regions (23a, 23b) are formed in portions of the element region and the diode region that are connected to the first electrode, and the contact region formed in the diode region has a higher impurity concentration than the contact region formed in the element region. In claim 3, metal silicide layers (31a, 31b) are formed in portions of the semiconductor substrate that are connected to the first electrode, and the metal silicide layer formed in the diode region is configured using a material that has a lower contact resistance with the first electrode than the metal silicide layer formed in the element region. In claim 5, a guard region insulated from the first electrode is disposed between the element region and the diode region, and the guard region disposed between the element region and the diode region has a length along the arrangement direction of the element region and the diode region that is equal to or greater than the diffusion length of holes.

[0010] According to this, the forward voltage of the diode region is made lower than the forward voltage of the parasitic diode formed in the element region. Therefore, when the SiC semiconductor device operates as a diode, the diode region is more likely to operate, and the parasitic diode in the element region is less likely to operate. Accordingly, it is possible to suppress the formation of SSF in the element region.

[0011] Also, in this SiC semiconductor device, by arranging the diode region, the formation of SSF in the element region is suppressed. For this reason, it is possible to suppress an increase in the on-resistance of the element region as compared with the case where a lifetime killer or the like is formed in the element region. That is, according to this SiC semiconductor device, it is possible to suppress the occurrence of SSF in the element region (that is, within the switching element) while suppressing an increase in the on-resistance.

[0012] Note that the reference signs in parentheses attached to each component or the like indicate an example of the correspondence relationship between the component or the like and the specific components or the like described in the embodiments described later.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following respective embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.

[0015] (First Embodiment) The first embodiment will be described with reference to the drawings. The SiC semiconductor device of this embodiment is preferably mounted on a vehicle such as an automobile and applied as a device for driving various vehicle-mounted electronic devices.

[0016] As shown in FIG. 1, the SiC semiconductor device has a planar rectangular shape, and has an element region 1, a diode region 2, a guard region 3 surrounding the diode region 2, and an outer peripheral region 4 surrounding the element region 1, the diode region 2, and the guard region 3. In this embodiment, a MOSFET as a switching element is formed in the element region 1, and a diode element is formed in the diode region 2.

[0017] Note that the guard region 3 is also disposed between the element region 1 and the diode region 2 by being disposed so as to surround the diode region 2. Further, in the outer peripheral region 4, a pad portion 5 and the like connected to a gate electrode 27 and the like, which will be described later, are formed.

[0018] Hereinafter, one direction in the plane direction of the substrate 11 to be described later is defined as the X-axis direction, a direction intersecting one direction in the plane direction of the substrate is defined as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction is defined as the Z-axis direction for explanation. In this embodiment, the X-axis direction and the Y-axis direction are orthogonal to each other. In FIG. 1, the vertical direction of the paper surface corresponds to the X-axis direction, the horizontal direction of the paper surface corresponds to the Y-axis direction, and the depth direction of the paper surface corresponds to the Z-axis direction. Further, hereinafter, when indicating the orientation of the crystal, a bar (-) should originally be attached above the desired number, but due to the expression limitations based on electronic applications, in this specification, a bar is attached in front of the desired number.

[0019] As shown in FIGS. 2 and 3, the SiC semiconductor device is configured using a semiconductor substrate 10 made of SiC that is 4H-SiC type as a whole and contains BPD. In this embodiment, the X-axis direction is along the [1-100] direction, and the Y-axis direction is along the [11-20] direction.

[0020] Specifically, the semiconductor substrate 10 includes an n + -type substrate 11 made of a SiC single crystal. In this embodiment, as the substrate 11, for example, it has an off-angle of 0 to 8° in the Y-axis direction with respect to the (0001)Si plane, and the n-type impurity concentration such as nitrogen or phosphorus is 1.0×10 19 / cm 3 , and a substrate with a thickness of about 300 μm is used. The substrate 11 constitutes the drain region and the high-concentration layer in this embodiment. The substrate 11 also contains BPD. As will be described later, an epitaxial layer or the like is disposed on the substrate 11 to form the semiconductor substrate 10 containing BPD.

[0021] An n - -type buffer layer 12 made of SiC is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration that is the impurity concentration between the substrate 11 and the low-concentration layer 13 to be described later, and a thickness of about 1 μm.

[0022] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0 to 10.0×10 15 / cm 3 The thickness of the n-type SiC substrate is about 10 to 15 μm. - The low concentration layer 13 of the mold is formed by epitaxial growth. The impurity concentration of this low concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is gradient so that the low concentration layer 13 on the substrate 11 side has a higher concentration than the side away from the substrate 11. For example, the low concentration layer 13 has an impurity concentration of 2.0×10 15 / cm 3 It is preferable that the low concentration layer 13 has a higher internal resistance than the other portions. With this configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0023] In the surface layer of the low concentration layer 13, the JFET section 14 and the first deep layer 15 are formed in the element region 1. In this embodiment, the JFET section 14 and the first deep layer 15 in the element region 1 are each configured to extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET section 14 and the first deep layer 15 in the element region 1 are each configured to have stripes extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are configured to have a layout in which they are alternately arranged along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, it can also be said that when viewed from the normal direction to the surface of the substrate 11.

[0024] The JFET section 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a depth of 0.3 to 1.5 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3is set. The first deep layer 15 has, for example, a p-type impurity concentration of boron or the like of 2.0×10 17 ~2.0×10 18 / cm 3 and is set as such.

[0025] And, the first deep layer 15 of the present embodiment is formed shallower than the JFET section 14. That is, the first deep layer 15 is formed such that the bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed such that the JFET section 14 is located between the first deep layer 15 and the low-concentration layer 13.

[0026] Also, on the surface layer portion of the low-concentration layer 13, in the diode region 2, the first deep layer 15 is entirely formed. Further, on the surface layer portion of the low-concentration layer 13, in the guard region 3, the first floating region 16 is formed. A plurality of the first floating regions 16 are formed so as to surround the diode region 2. The first floating region 16 of the present embodiment is, for example, formed in a concentric shape in a rectangular frame shape with rounded corners. However, the first floating region 16 may be formed in a concentric shape in another frame shape such as a circular frame shape instead of the rectangular frame shape.

[0027] Note that the first deep layer 15 formed in the element region 1 and the diode region 2 and the first floating region 16 formed in the guard region 3 have the same depth and the same thickness on the lower surface side of the substrate 11, and the p-type impurity concentration is the same.

[0028] And, on the JFET section 14 and the first deep layer 15 in the element region 1, a current dispersion layer 17, a second deep layer 18, a base layer 21, a source region 22, and a contact region 23a are formed. On the first deep layer 15 in the diode region 2, a second deep layer 18, a base layer 21, and a contact region 23b are formed. On the low-concentration layer 13 and the first deep layer 15 in the guard region 3, a current dispersion layer 17 and a second floating region 24 are formed.

[0029] The current dispersion layer 17 is composed of an n-type impurity layer and is connected to the JFET section 14 in the element region 1. Therefore, in this embodiment, the low-concentration layer 13, the JFET section 14, and the current dispersion layer 17 are connected, and the drift layer 19 is formed by these layers.

[0030] The second deep layer 18 has the same thickness as the current dispersion layer 17. In the element region 1, the current dispersion layer 17 and the second deep layer 18 extend in a stripe-shaped portion of the JFET section 14 and in a direction intersecting the longitudinal direction of the first deep layer 15. In this embodiment, the current dispersion layer 17 and the second deep layer 18 extend with the Y-axis direction as the longitudinal direction and are arranged in a layout in which a plurality of layers are alternately arranged in the X-axis direction. The formation pitch of the current dispersion layer 17 and the second deep layer 18 is adjusted to the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 25 described later.

[0031] On the other hand, in the diode region 2, the second deep layer 18 is entirely formed on the first deep layer 15.

[0032] The base layer 21 is of p-type and is formed on the current dispersion layer 17 and the second deep layer 18 in the element region 1. Also, the base layer 21 is formed on the second deep layer 18 in the diode region 2.

[0033] In the element region 1, an n + -type source region 22 and a p + -type contact region 23a are formed on the surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to be in contact with the side surface of the trench 25 described later. The contact region 23a is formed on the side opposite to the trench 25 described later with the source region 22 interposed therebetween. In this embodiment, the source region 22 constitutes an impurity region.

[0034] In the diode region 2, a p +A contact region 23b of the type is formed.

[0035] In the guard region 3, the current dispersion layer 17 is arranged so as to constitute one surface 10a of the semiconductor substrate 10 described later. And in the guard region 3, a plurality of second floating regions 24 are formed so as to surround the diode region 2 on the surface layer portion of the current dispersion layer 17. In the present embodiment, the second floating region 24 is, for example, formed in a concentric shape with a square frame shape with rounded corners. However, the second floating region 24 may be formed in a concentric shape with other frame shapes such as a circular frame shape instead of the square frame shape.

[0036] Note that the second deep layer 18 formed in the element region 1 and the diode region 2 and the second floating region 24 formed in the guard region 3 have the same depth and the same thickness on the lower surface on the substrate 11 side, and the p-type impurity concentration is the same.

[0037] In the present embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET portion 14, the first deep layer 15, the first floating region 16, the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, the second floating region 24, and the like. And one surface 10a of the semiconductor substrate 10 is composed of the source region 22, the contact regions 23a and 23b, the current dispersion layer 17, the second floating region 24, and the like, and the other surface 10b of the semiconductor substrate 10 is composed of the substrate 11. Also, in the diode region 2, a diode element is configured with the substrate 11, the buffer layer 12, and the low concentration layer 13 as the cathode and the first deep layer 15, the second deep layer 18, the base layer 21, and the contact region 23b as the anode.

[0038] In the semiconductor substrate 10, in the element region 1, for example, trenches 25 having a width of 1.4 to 2.0 μm are formed so as to penetrate through the source region 22, the base layer 21, etc. and reach the current dispersion layer 17, and the bottom surface is located within the current dispersion layer 17. Note that the trenches 25 are formed so as not to reach the JFET portion 14 and the first deep layer 15. That is, the trenches 25 are formed such that the JFET portion 14 and the first deep layer 15 are located below the bottom surface.

[0039] Also, a plurality of trenches 25 are extended so as to extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to be formed in a stripe shape. That is, in the present embodiment, the trenches 25 are formed such that the longitudinal direction is orthogonal to the longitudinal direction of the first deep layer 15. Further, the trenches 25 are formed so as to be sandwiched by the second deep layer 18 in the normal direction.

[0040] A gate insulating film 26 is formed on the inner wall surface of the trench 25, and a gate electrode 27 composed of doped Poly-Si or the like is formed on the gate insulating film 26. Thereby, a trench gate structure is configured. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or performing a CVD (abbreviation for chemical vapor deposition) method. And the gate insulating film 26 has a thickness of about 100 nm both on the side surface side and the bottom surface side of the trench 25.

[0041] Note that the gate insulating film 26 is also formed on the surfaces other than the inner wall surface of the trench 25. Specifically, in the element region 1, the gate insulating film 26 is formed so as to cover a part of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a part of the surface of the source region 22. In other words, contact holes 26a for exposing the base layer 21 and the source region 22 are formed in a portion of the gate insulating film 26 different from the portion where the gate electrode 27 is disposed. Further, in the diode region 2, a contact hole 26b for exposing the entire one surface 10a of the semiconductor substrate 10 is formed in the gate insulating film 26. In the guard region 3, the gate insulating film 26 is formed so as to cover the entire one surface 10a of the semiconductor substrate 10.

[0042] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 28 is formed so as to cover the gate electrode 27, the gate insulating film 26, and the like. The interlayer insulating film 28 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like.

[0043] In the interlayer insulating film 28, a contact hole 28a that communicates with the contact hole 26a and exposes the source region 22 and the contact region 23a in the element region 1 is formed. Further, in the interlayer insulating film 28, a contact hole 28b that communicates with the contact hole 26b and exposes the contact region 23b in the diode region 2 is formed.

[0044] Note that the contact hole 28a formed in the interlayer insulating film 28 is formed so as to communicate with the contact hole 26a formed in the gate insulating film 26, and functions as one contact hole together with the contact hole 26a. Similarly, the contact hole 28b formed in the interlayer insulating film 28 is formed so as to communicate with the contact hole 26b formed in the gate insulating film 26, and functions as one contact hole together with the contact hole 26b. Therefore, hereinafter, the contact hole 26a and the contact hole 28a are also collectively referred to as the contact hole 29a, and the contact hole 26b and the contact hole 28b are also collectively referred to as the contact hole 29b. The patterns of the contact holes 29a and 29b are arbitrary, and examples thereof include a pattern in which a plurality of square shapes are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are arranged. In the present embodiment, the contact hole 29a formed in the element region 1 is in a line shape along the longitudinal direction of the trench 25. Further, the contact hole 29b formed in the diode region 2 is formed so as to expose the entire diode region 2.

[0045] On the interlayer insulating film 28, an upper electrode 30 is formed which is electrically connected to the source region 22 and the contact region 23a through the contact hole 29a and is also electrically connected to the contact region 23b through the contact hole 29b. That is, the contact region 23a in the element region 1 and the contact region 23b in the diode region 2 are electrically connected to the common upper electrode 30. In the present embodiment, the upper electrode 30 corresponds to the first electrode. Further, in the guard region 3, since the gate insulating film 26 and the interlayer insulating film 28 are arranged as described above, the upper electrode 30 is not electrically connected and is insulated.

[0046] The upper electrode 30 of this embodiment is composed of an Al-Si layer mainly containing Al (aluminum), and is connected to the source region 22 and the contact regions 23a and 23b as follows. Specifically, in the source region 22 and the contact regions 23a and 23b in the element region 1, a metal silicide layer 31a formed of a metal such as Ni (nickel) is formed on the portion exposed from the contact hole 29a. Similarly, in the contact region 23b in the diode region 2, a metal silicide layer 31b formed of a metal such as Ni is formed on the portion exposed from the contact hole 29a. These metal silicide layers 31a and 31b are for reducing the contact resistance between the source region 22 and the contact regions 23a and 23b and the upper electrode 30.

[0047] And a barrier metal film 32 composed of Ti (titanium), TiN (titanium nitride), etc. is formed on the metal silicide layers 31a and 31b. Note that the barrier metal film 32 is also formed on the wall surfaces of the contact holes 29a and 29b and the surface of the interlayer insulating film 28. This barrier metal film 32 suppresses the diffusion of Al constituting the upper electrode 30 to the semiconductor substrate 10 side or the interlayer insulating film 28 side, and suppresses the diffusion of Ni constituting the metal silicide layers 31a and 31b to the upper electrode 30 side.

[0048] And the upper electrode 30 is disposed on the barrier metal film 32, and is connected to the source region 22 and the contact regions 23a and 23b via the barrier metal film 32 and the metal silicide layers 31a and 31b.

[0049] A lower electrode 33 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10. Note that in this embodiment, the lower electrode 33 corresponds to the second electrode.

[0050] Here, as described above, in the element region 1, a contact hole 29a is formed to expose a part of the source region 22 and the contact regions 23a and 23b. In the diode region 2, a contact hole 29b is formed to expose the whole. Therefore, the connection area with the upper electrode 30 per unit area of the diode region 2 is larger than the connection area with the upper electrode 30 per unit area of the element region 1. Accordingly, in the SiC semiconductor device of the present embodiment, the contact resistance between the diode region 2 and the upper electrode 30 is smaller than that of the element region 1. Also, in the element region 1, a parasitic diode including the drift layer 19 and the base layer 21 is formed. Therefore, as shown in FIG. 4, when comparing the parasitic diode formed in the element region 1 and the diode element formed in the diode region 2, the forward voltage Vf (hereinafter also simply referred to as the forward voltage Vf) at which the forward current If starts to flow is smaller in the diode region 2 than in the element region 1. That is, in the SiC semiconductor device of the present embodiment, when the diode operates, the diode region 2 operates more easily than the parasitic diode formed in the element region 1.

[0051] Also, as shown in FIG. 1, the guard region 3 of the present embodiment is arranged so as to surround the diode region 2 and is thus also arranged between the element region 1 and the diode region 2. The width of the guard region 3 is set such that the interval of the portion arranged between the element region 1 and the diode region 2 is longer than the diffusion length of holes. In other words, the length of the portion of the guard region 3 arranged between the element region 1 and the diode region 2 is made longer than the length along the arrangement direction between the element region 1 and the diode region 2. That is, in the present embodiment, the length along the X-axis direction of the portion of the guard region 3 arranged between the element region 1 and the diode region 2 is made longer than the diffusion length of holes.

[0052] The above is the configuration of the SiC semiconductor device in the present embodiment. In the present embodiment, n - -type, n-type, n + -type correspond to the first conductivity type, and p-type, p +The type corresponds to the second conductivity type.

[0053] Next, the operation and effects of the SiC semiconductor device in this embodiment will be described.

[0054] First, in the SiC semiconductor device, in the off state before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, an inversion layer is not formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600 V is applied to the lower electrode 33, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in an off state where no current flows between the upper electrode 30 and the lower electrode 33.

[0055] Also, when the SiC semiconductor device is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 26. However, in the above SiC semiconductor device, the first deep layer 15 and the JFET portion 14 are provided at a position deeper than the trench 25. Therefore, the depletion layer formed between the first deep layer 15 and the JFET portion 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, and it becomes difficult for a high electric field to enter the gate insulating film 26. Therefore, in this embodiment, it is possible to suppress the gate insulating film 26 from being broken.

[0056] Furthermore, in this embodiment, the first floating region 16 and the second floating region 24 are formed in the guard region 3. Therefore, the depletion layer formed between the first floating region 16 and the second floating region 24 and the drift layer 19 can suppress the concentration of equipotential lines due to the influence of the drain voltage. Therefore, it is also possible to improve the breakdown voltage of the guard region 3.

[0057] When a voltage equal to or higher than the threshold voltage in the insulated gate structure, for example, 20 V, is applied to the gate electrode 27, an inversion layer is formed on the surface of the base layer 21 in contact with the trench 25. As a result, a current flows between the upper electrode 30 and the lower electrode 33, and the SiC semiconductor device is turned on. In this embodiment, since the electrons passing through the inversion layer flow through the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 to the substrate 11, it can be said that the drift layer 19 having the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 is formed.

[0058] Also, in such a SiC semiconductor device, a parasitic diode including the drift layer 19 and the base layer 21 is formed in the element region 1. And when a voltage higher than that of the lower electrode 33 is applied to the upper electrode 30, etc., the SiC semiconductor device may operate as a diode. In this case, in this embodiment, a diode region 2 having a lower forward voltage Vf than the parasitic diode is formed on the common semiconductor substrate 10. Therefore, in this embodiment, when the SiC semiconductor device operates as a diode, the diode region 2 is more likely to operate, and the parasitic diode in the element region 1 is less likely to operate. Therefore, it is possible to suppress the formation of SSF in the element region 1.

[0059] Also, in this embodiment, a guard region 3 is disposed between the element region 1 and the diode region 2, and the width of the portion of the guard region 3 located between the element region 1 and the diode region 2 is set to be equal to or greater than the diffusion length of holes. Therefore, it is possible to suppress the holes injected when the diode region 2 operates as a diode from reaching the element region 1. Therefore, it is also possible to suppress the formation of SSF in the element region 1 by the holes when the diode region 2 operates as a diode.

[0060] According to the present embodiment described above, the forward voltage Vf of the diode region 2 is made lower than the forward voltage Vf of the parasitic diode formed in the element region 1. Therefore, when the SiC semiconductor device operates as a diode, the diode region 2 is more likely to operate, and the parasitic diode in the element region 1 is less likely to operate. Accordingly, it is possible to suppress the formation of the SSF in the element region 1.

[0061] Also, in the SiC semiconductor device of the present embodiment, by arranging the diode region 2, the formation of the SSF in the element region 1 is suppressed. Therefore, it is possible to suppress an increase in the on-resistance of the element region 1 as compared with the case where a lifetime killer or the like is formed in the element region 1. That is, according to the SiC semiconductor device of the present embodiment, it is possible to suppress the generation of the SSF in the element region 1 while suppressing an increase in the on-resistance.

[0062] (1) In the present embodiment, the connection area with the upper electrode 30 per unit area of the diode region 2 is made larger than the connection area with the upper electrode 30 per unit area of the element region 1. Therefore, a configuration in which the forward voltage Vf of the diode region 2 becomes lower than the forward voltage Vf of the parasitic diode formed in the element region 1 can be easily realized.

[0063] (2) In the present embodiment, the guard region 3 is arranged between the element region 1 and the diode region 2. And the length of the portion of the guard region 3 located between the element region 1 and the diode region 2 is set to be equal to or greater than the diffusion length of holes. Therefore, it is possible to suppress holes injected when the diode region 2 operates as a diode from reaching the element region 1. Accordingly, it is possible to suppress the formation of the SSF in the element region 1 by the holes when the diode region 2 operates as a diode.

[0064] (3) In the present embodiment, the first floating region 16 and the second floating region 24 that form a depletion layer with the drift layer 19 are formed in the guard region 3. Therefore, it is possible to improve the breakdown voltage of the guard region 3.

[0065] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the diode region 2 is changed. For other aspects, since they are the same as those in the first embodiment, the description is omitted here.

[0066] In the SiC semiconductor device of this embodiment, as shown in FIG. 5, the contact region 23b formed in the diode region 2 has a higher impurity concentration than the contact region 23a formed in the element region 1.

[0067] According to the present embodiment described above, since the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the same effects as those in the first embodiment can be obtained.

[0068] (1) In this embodiment, the contact region 23b formed in the diode region 2 has a higher impurity concentration than the contact region 23a formed in the element region 1. Therefore, as shown in FIG. 6, the forward voltage Vf of the diode region 2 can be further reduced.

[0069] (Third Embodiment) The third embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the diode region 2 is changed. For other aspects, since they are the same as those in the first embodiment, the description is omitted here.

[0070] In the SiC semiconductor device of this embodiment, as shown in FIG. 7, the metal silicide layer 31a formed in the element region 1 and the metal silicide layer 31b formed in the diode region 2 are different metal silicide layers. Specifically, the metal silicide layer 31b formed in the diode region 2 is composed of a material with a smaller contact resistance with the upper electrode 30 than the metal silicide layer 31a formed in the element region 1. For example, the metal silicide layer 31a formed in the element region 1 is Ni silicide formed using Ni, and the metal silicide layer 31b formed in the diode region 2 is Al silicide formed using Al.

[0071] According to the present embodiment described above, since the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the same effect as that of the first embodiment can be obtained.

[0072] (1) In this embodiment, the metal silicide layer 31b formed in the diode region 2 is composed of a material with a smaller contact resistance with the upper electrode 30 than the metal silicide layer 31a formed in the element region 1. Therefore, the forward voltage Vf of the diode region 2 can be further reduced.

[0073] (Fourth Embodiment) The fourth embodiment will be described. This embodiment is obtained by adding a diode region 2 to the first embodiment. Since the rest is the same as the first embodiment, the description is omitted here.

[0074] In the SiC semiconductor device of this embodiment, as shown in FIG. 8, two diode regions 2 are provided. And the guard region 3 is provided so as to surround each diode region 2. Note that each diode region 2 and the guard region 3 have the configurations shown in FIG. 2, respectively.

[0075] According to the present embodiment described above, since the forward voltage Vf of the diode region 2 is made lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the same effects as those of the first embodiment can be obtained.

[0076] (1) In this embodiment, two diode regions 2 are provided. Therefore, it is possible to further suppress the element region 1 from operating as a diode. Although not particularly shown, the number of the diode regions 2 can be changed, and three or more diode regions 2 may be provided.

[0077] (Fifth Embodiment) The fifth embodiment will be described. In this embodiment, the arrangement position of the diode region 2 is changed with respect to the first embodiment. Since other aspects are the same as those of the first embodiment, the description is omitted here.

[0078] In the SiC semiconductor device of this embodiment, as shown in FIG. 9, the diode region 2 is arranged along the Y-axis direction with respect to the element region 1. And the guard region 3 is arranged so as to surround this diode region 2.

[0079] According to the present embodiment described above, since the forward voltage Vf of the diode region 2 is made lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the same effects as those of the first embodiment can be obtained.

[0080] (1) In this embodiment, the diode region 2 is arranged along the Y-axis direction with respect to the element region 1. Here, in the case of the SiC semiconductor device as in this embodiment, it has been reported that the SSF formed when operating as a diode tends to extend along the [1-100] direction. Therefore, the SSF that can be formed in the diode region 2 tends to extend along the X-axis direction. Accordingly, it becomes difficult for the SSF that can be formed in the diode region 2 to reach the element region 1, and it is easier to further suppress the deterioration of the characteristics of the element region 1.

[0081] (Other Embodiments) Although this disclosure has been described in accordance with embodiments, it is understood that the disclosure is not limited to such embodiments or structures. The disclosure includes various modifications and variations within an equivalent scope. In addition, various combinations and forms, as well as other combinations and forms including only one element, more, or less thereof, fall within the scope and spirit of the disclosure.

[0082] For example, in the first embodiment above, a SiC semiconductor device in which a MOSFET having a trench gate structure of n-channel type with the first conductivity type being n-type and the second conductivity type being p-type is formed in the element region 1 was described. However, this is merely an example. For example, as a switching element, a SiC semiconductor device in which a MOSFET having a trench gate structure of p-channel type with the conductivity type of each component inverted with respect to the n-channel type is formed in the element region 1 may also be used. Furthermore, in addition to the MOSFET, the SiC semiconductor device may be configured such that an IGBT having a similar structure is formed in the element region 1 as a switching element. When forming an IGBT in the element region 1, except for changing the n + -type substrate 11 to a p + -type substrate 11, it is the same as the MOSFET described in the above embodiments. Furthermore, the switching element may have a planar gate structure instead of a trench gate structure.

[0083] Also, in each of the above embodiments, other elements may be formed in the SiC semiconductor device. For example, a current sense region or the like for detecting current may be formed.

[0084] And, in each of the above embodiments, the first deep layer 15 and the second deep layer 18 may not be provided. Also, the drift layer 19 may be composed of a single layer with a uniform impurity concentration.

[0085] Furthermore, in the second and third embodiments described above, if the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the relationship between the connection area per unit area of the upper electrode 30 in the diode region 2 and the guard region 3 can be changed as appropriate.

[0086] And in each of the above embodiments, although an example in which the semiconductor substrate 10 is made of 4H-SiC has been described, the semiconductor substrate 10 may be made of 6H-SiC or the like.

[0087] Also, in each of the above embodiments, only one of the first floating region 16 and the second floating region 24 may be formed in the guard region 3, or neither the first floating region 16 nor the second floating region 24 may be formed. Furthermore, in each of the above embodiments, the guard region 3 may not be formed. Even in such a SiC semiconductor device, if the forward voltage Vf of the diode region 2 is lower than the forward voltage Vf of the parasitic diode formed in the element region 1, the same effects as those of the above embodiments can be obtained.

[0088] And a SiC semiconductor device combining the above embodiments may also be used. For example, the second embodiment may be combined with the third to fifth embodiments so that the impurity concentration of the contact region 23b of the diode region 2 is higher than that of the contact region 23a of the element region 1. The third embodiment may be combined with the fourth and fifth embodiments so that the contact resistance between the metal silicide layer 31b of the diode region 2 and the upper electrode 30 is lower than that of the metal silicide layer 31a of the element region 1. The fourth embodiment may be combined with the fifth embodiment so that a plurality of diode regions 2 are provided.

Explanation of Reference Numerals

[0089] 1 Element region 2 Diode region 10 Semiconductor substrate 10a One surface 10b The other surface 30 First electrode 33 Second electrode

Claims

1. A silicon carbide semiconductor device composed of silicon carbide, comprising: A semiconductor substrate (10) composed of silicon carbide and having one surface (10a) and the other surface (10b) opposite to the one surface; An element region (1) formed on the semiconductor substrate and having a switching element that constitutes a parasitic diode; A diode region (2) formed on the semiconductor substrate and having a diode element; A first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element; A second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element, wherein the diode element formed in the diode region has a forward voltage at which a forward current starts to flow that is smaller than that of the parasitic diode; Contact regions (23a, 23b) are formed in the element region and the diode region at portions connected to the first electrode; A silicon carbide semiconductor device in which the contact region formed in the diode region has a higher impurity concentration than the contact region formed in the element region.

2. A metal silicide layer (31a, 31b) is formed on the semiconductor substrate at a portion connected to the first electrode; The silicon carbide semiconductor device according to claim 1, wherein the metal silicide layer formed in the diode region is formed using a material having a lower contact resistance with the first electrode than the metal silicide layer formed in the element region.

3. A silicon carbide semiconductor device composed of silicon carbide, comprising: A semiconductor substrate (10) composed of silicon carbide and having one surface (10a) and the other surface (10b) opposite to the one surface; An element region (1) formed on the semiconductor substrate and having a switching element that constitutes a parasitic diode; A diode region (2) formed on the semiconductor substrate and having a diode element; A first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element; A second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element, wherein the diode element formed in the diode region has a forward voltage at which a forward current starts to flow that is smaller than that of the parasitic diode; On the semiconductor substrate, a metal silicide layer (31a, 31b) is formed at a portion connected to the first electrode. A silicon carbide semiconductor device, wherein the metal silicide layer formed in the diode region is composed of a material having a lower contact resistance with the first electrode than the metal silicide layer formed in the element region. **Claim 4** A guard region insulated from the first electrode is disposed between the element region and the diode region. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the guard region disposed between the element region and the diode region has a length along the arrangement direction of the element region and the diode region that is equal to or greater than the diffusion length of holes. **Claim 5** A silicon carbide semiconductor device composed of silicon carbide, comprising: A semiconductor substrate (10) composed of silicon carbide and having one surface (10a) and the other surface (10b) opposite to the one surface; An element region (1) formed on the semiconductor substrate and having a switching element constituting a parasitic diode; A diode region (2) formed on the semiconductor substrate and having a diode element; A first electrode (30) disposed on one surface side of the semiconductor substrate and electrically connected to the switching element and the diode element; A second electrode (33) disposed on the other surface side of the semiconductor substrate and electrically connected to the switching element and the diode element. The diode element formed in the diode region has a forward voltage at which a forward current starts to flow that is smaller than that of the parasitic diode. A guard region insulated from the first electrode is disposed between the element region and the diode region. The silicon carbide semiconductor device, wherein the guard region disposed between the element region and the diode region has a length along the arrangement direction of the element region and the diode region that is equal to or greater than the diffusion length of holes. **Claim 6** The guard region includes a drift layer (19) of a first conductivity type, and a floating region (16, 24) of a second conductivity type that forms a depletion layer between the drift layer and is insulated from the first electrode. The silicon carbide semiconductor device according to claim 4 or 5. **Claim 7** The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the connection area of the diode region with the first electrode per unit area is larger than the connection area of the element region with the first electrode per unit area.

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