Trench Contact Structure for Manufacturing Next-Generation Integrated Circuit Structures

Abstract

To provide 10-nanometer node and smaller integrated circuit structure fabrication and the resulting structures.SOLUTION: An integrated circuit structure 3900 includes an N-type semiconductor device and a P-type semiconductor device. A semiconductor source or a drain region 3958 is adjacent to a gate electrode 3952, and a semiconductor source or a drain region 3910 is adjacent to a gate electrode 3902. A trench contact structure 3970 is over the semiconductor source or a drain region 3958, and a trench contact structure 3930 is over the semiconductor source or a drain region 3910. The trench contact structure 3970 and the trench contact structure 3930 both comprise a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the entirety of the U-shaped metal layer 3916.SELECTED DRAWING: Figure 39H

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Application No. 62 / 593,149, filed on Nov. 30, 2017, entitled "Next - Generation Integrated Circuit Structure Manufacturing", the entire content of which is incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to the field of next - generation integrated circuit structure manufacturing, and in particular, to the manufacturing of 10 - nanometer nodes and smaller integrated circuit structures, and to the resulting structures.

Background Art

[0003] Over the past few decades, the scaling of features in integrated circuits has been a driving force behind the growing semiconductor industry. Scaling to ever - finer features enables an increase in the density of functional units on the limited area of a semiconductor chip. For example, by reducing the size of transistors, it becomes possible to incorporate a larger number of memory or logic devices on a chip, leading to the production of products with increased capacity. However, there are still problems in moving towards even higher capacities. The need to optimize the performance of each device is becoming increasingly prominent.

[0004] Due to variability in conventional and currently known manufacturing processes, the possibility of further advancing to the range of 10 - nanometer nodes or sub - 10 - nanometer nodes may be limited. As a result, the manufacture of functional components required for future technology nodes may require the introduction of new methods, or the integration of new technologies into current manufacturing processes, or the replacement of current manufacturing processes.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0112] The manufacturing of a next-generation integrated circuit structure will be described. In the following description, numerous specific details, such as specific integrations and material regimes, are described to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the drawings are presented illustratively and are not necessarily drawn to scale.

[0113] The following "Mode for Carrying Out the Invention" is essentially only illustrative and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the term "exemplary" means "serving as an example, instance, or illustration." None of the implementation forms described as exemplary herein should necessarily be construed as being more preferred or advantageous than other implementation forms. Furthermore, it is not intended to be bound by any explicit or implicit theory presented in the above "Technical Field," "Background Art," "Summary of the Invention," or the following "Mode for Carrying Out the Invention."

[0114] This specification includes references to "one embodiment" or "an embodiment." The appearance of the phrases "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics can be combined in any suitable manner that is not inconsistent with the present disclosure.

[0115] [Terms] The following paragraphs provide definitions or contexts for the terms described in the present disclosure (including the appended claims).

[0116] "Comprising" - This term is open-ended. When this term is used in the appended claims, it does not exclude additional structures or steps.

[0117] "Configured to" - Various units or components can be described or claimed as "configured to" perform one or more tasks. In such context, "configured to" is used to imply a structure by indicating that the unit or component includes a structure for performing one or more tasks during operation. Thus, a unit or component can be said to be configured to perform a task even when the specified unit or component is not currently operating (e.g., not activated or not active). Describing a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, ¶ 6 with respect to that unit or component.

[0118] "First", "second", etc. As used herein, these terms are used as labels with respect to the nouns that follow and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.).

[0119] "Coupled" - The following description refers to elements or nodes or features that are "coupled" together. As used herein, unless otherwise expressly stated, "coupled" means that one element or node or feature is directly or indirectly connected to (or in direct or indirect communication with) another element or node or feature, and does not necessarily require a mechanical coupling.

[0120] Furthermore, certain terms may also be used only for reference purposes in the following description and are thus not intended to be limiting. For example, terms such as "upper", "lower", "above", and "below" refer to directions within the referenced drawings. Terms such as "front", "back", "rear", "side", "outward", "inward", etc. describe the orientation or position, or both, of a component part in a consistent but arbitrary coordinate system, which becomes apparent by referring to the document describing the component being described and the associated drawings. Such terms may include the specifically mentioned words, their derivatives, and words of similar meaning.

[0121] "Suppress" - As used herein, suppress is used to describe a reduced or minimized effect. When a component or feature is described as suppressing an action, operation, or condition, it may completely prevent the resulting outcome, result, or future state. Further, "suppress" may also refer to a decrease or reduction in an outcome, performance, or effect that would otherwise occur. Thus, when a component, element, or feature is referred to as suppressing a result or state, it is not necessary to completely prevent or eliminate the result or state.

[0122] The embodiments described herein may relate to semiconductor processing and structures in the front-end-of-line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned onto a semiconductor substrate or layer. FEOL generally encompasses everything up to (but not including) the deposition of the metal interconnect layers. After the last FEOL step, typically a wafer with isolated (e.g., no wires) transistors results.

[0123] The embodiments described herein may relate to semiconductor processing and structures of the backend of line (BEOL). BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on a wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package interconnections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers may be added in BEOL.

[0124] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL processing and structures and BEOL processing and structures. In particular, exemplary processing schemes may be shown using the context of FEOL processing, but such an approach may also be applicable to BEOL processing. Similarly, exemplary processing schemes may be shown using the context of BEOL processing, but such an approach may also be applicable to FEOL processing.

[0125] Pitch splitting processes and patterning schemes may be implemented to enable the embodiments described herein or may be included as part of the embodiments described herein. Pitch splitting patterning typically refers to pitch 2 splitting, pitch 4 splitting, etc. Pitch splitting schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print lines in one direction (e.g., either strictly in one direction or mainly in one direction) at a predefined pitch. Thus, pitch splitting processing is implemented as a technique to increase line density.

[0126] In one embodiment, the term "lattice structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a dense pitch lattice structure. In such an embodiment, the dense pitch is not directly achievable through the selected lithography. For example, a pattern based on the selected lithography may first be formed, but as is known in the art, the pitch can be halved by using spacer mask patterning. Further still, the original pitch can be quartered by a second spacer mask patterning. Thus, the lattice patterns described herein may have metal lines, ILD lines, or hard mask lines of substantially consistent width spaced only by a substantially consistent pitch. For example, in some embodiments, the pitch variation is within 10 percent and the width variation is within 10 percent, and in some embodiments, the pitch variation is within 5 percent and the width variation is within 5 percent. It can be manufactured by patterning, pitch halving or pitch quartering, or other pitch division approaches. In one embodiment, the lattice is not necessarily of a single pitch.

[0127] In the first example, pitch halving can be implemented to double the line density of the manufactured lattice structure. FIG. 1A shows a cross-sectional view of the initial structure of a hard mask material layer formed on an interlayer dielectric (ILD) layer after deposition and before patterning. FIG. 1B shows a cross-sectional view of the structure of FIG. 1A after patterning of the hard mask layer by pitch halving.

[0128] Referring to FIG. 1A, the initial structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. The patterned mask 106 is disposed above the hard mask material layer 104. The patterned mask 106 has spacers 108 formed along the sidewalls of those features (lines) on the hard mask material layer 104.

[0129] Referring to FIG. 1B, the hard mask material layer 104 is patterned by a pitch doubling approach. Specifically, the patterned mask 106 is first removed. In the resulting pattern of spacers 108, the density is doubled, or the pitch or feature of the mask 106 is halved. The pattern of spacers 108 is transferred to the hard mask material layer 104, for example, by an etching process, to form the patterned hard mask 110 as shown in FIG. 1B. In such an embodiment, the patterned hard mask 110 is formed to have a grid pattern with lines in one direction. The grid pattern of the patterned hard mask 110 can be a grid structure with a dense pitch. For example, a dense pitch may not be directly achievable through the selected lithography technique. Still further, although not shown, the original pitch can be quartered by a second spacer mask patterning. Thus, the grid-like pattern of the patterned hard mask 110 in FIG. 1B can have hard mask lines that are spaced apart at a certain pitch and have a certain width relative to each other. The dimensions achieved may be much smaller than the critical dimensions of the lithography technique employed.

[0130] Accordingly, for either, or both, of the substrate process (FEOL) or the wiring process (BEOL), which are integration schemes, the blanket film can be patterned using lithography and etching processes, which can involve, for example, spacer-based double patterning (SBDP) or pitch splitting by 2, or spacer-based quadruple patterning (SBQP) or pitch splitting by 4. It should be understood that other pitch splitting approaches can also be implemented. In any case, in one embodiment, a grid layout can be manufactured by a selected lithography approach, such as 193nm immersion lithography (193i). The pitch splitting can be implemented to increase the line density of the grid layout by n times. A grid layout formed using 193i lithography and n-fold pitch splitting can be denoted as 193i + P / n pitch splitting. In such an embodiment, 193nm immersion scaling can be extended over multiple generations by cost-effective pitch splitting.

[0131] In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. Tri-gate transistors are generally manufactured on either a bulk silicon substrate or a silicon-on-insulator substrate. In some cases, the bulk silicon substrate is preferred due to its lower cost and compatibility with the infrastructure of existing high-yield bulk silicon substrates.

[0132] However, it has not been possible to scale multi-gate transistors without incurring an impact. As the dimensions of these basic building blocks of microelectronic circuits decrease, and as the number of very many basic building blocks manufactured in a given area increases, the constraints on the semiconductor processes used to manufacture these building blocks have been increasing.

[0133] According to one or more embodiments of the present disclosure, a pitch quadrupling approach is implemented to pattern a semiconductor layer to form semiconductor fins. In one or more embodiments, an integrated fin pitch quadrupling approach is implemented.

[0134] FIG. 2A is a schematic diagram of a pitch quadrupling approach 200 used to manufacture semiconductor fins according to one embodiment of the present disclosure. FIG. 2B shows a cross-sectional view of semiconductor fins manufactured using the pitch quadrupling approach according to one embodiment of the present disclosure.

[0135] Referring to FIG. 2A, in step (a), a photoresist layer (PR) is patterned to form photoresist feature 202. The photoresist feature 202 can be patterned using standard lithography processing techniques such as 193 immersion lithography. In step (b), the photoresist feature 202 is used to pattern a material layer such as an insulator or dielectric hard mask layer to form a first backbone (BB1) feature 204. Next, a first spacer (SP1) feature 206 is formed adjacent to the sidewalls of the first backbone feature 204. In step (c), the first backbone feature 204 is removed, leaving only the first spacer feature 206. Before or during the removal of the first backbone feature 204, the first spacer feature 206 can be thinned to form a thinned first spacer feature 206' as shown in FIG. 2A. This thinning can be performed before (as shown) or after the removal of BB1 (feature 204), depending on the required spacing and size for the BB2 feature (208, described later). In step (d), the first spacer feature 206 or the thinned first spacer feature 206' is used to pattern a material layer such as an insulator or dielectric hard mask layer to form a second backbone (BB2) feature 208. Next, a second spacer (SP2) feature 210 is formed adjacent to the sidewalls of the second backbone feature 208. In step (e), the second backbone feature 208 is removed, leaving only the second spacer feature 210. Next, the remaining second spacer feature 210 can be used to pattern a semiconductor layer to provide a plurality of semiconductor fins having a pitch of four times the dimensions of the initially patterned photoresist feature 202. As an example, referring to FIG. 2B, a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer feature 210 as a mask for patterning, such as dry or plasma etching patterning. In the example of FIG. 2B, the plurality of semiconductor fins 250 have substantially the same pitch and spacing throughout.

[0136] It should be understood that by modifying the spacing between the initially patterned photoresist features, the structural results of the pitch quadrupling process can be changed. In one example, FIG. 3A is a schematic diagram of an integrated fin pitch quadrupling approach 300 used to fabricate semiconductor fins according to one embodiment of the present disclosure. FIG. 3B shows a cross-sectional view of semiconductor fins fabricated using the integrated fin pitch quadrupling approach according to one embodiment of the present disclosure.

[0137] Referring to FIG. 3A, in step (a), the photoresist layer (PR) is patterned to form photoresist feature 302. The photoresist feature 302 can be patterned using standard lithography processing techniques such as 193 immersion lithography, but the spacing (e.g., the spacing called sub-design rule space) that may ultimately interfere with the design rules required to generate a uniform pitch doubling pattern. In step (b), the photoresist feature 302 is used to pattern a material layer such as an insulator or dielectric hard mask layer to form the first backbone (BB1) feature 304. Next, the first spacer (SP1) feature 306 is formed adjacent to the sidewalls of the first backbone feature 304. However, in contrast to the scheme shown in FIG. 2A, a portion of the adjacent first spacer feature 306 is an integrated spacer feature as a result of the photoresist feature 302 being denser. In step (c), the first backbone feature 304 is removed, leaving only the first spacer feature 306. Before or after the removal of the first backbone feature 304, a portion of the first spacer feature 306 can be thinned to form the thinned first spacer feature 306' as shown in FIG. 3A. In step (d), the first spacer feature 306 and the thinned first spacer feature 306' are used to pattern a material layer such as an insulator or dielectric hard mask layer to form the second backbone (BB2) feature 308. Next, the second spacer (SP2) feature 310 is formed adjacent to the sidewalls of the second backbone feature 308. However, at positions where the BB2 feature 308 is an integrated feature, such as the central BB2 feature 308 in FIG. 3A, the second spacer is not formed. In step (e), the second backbone feature 308 is removed, leaving only the second spacer feature 310. Next, the remaining second spacer feature 310 is used to pattern the semiconductor layer, which may provide a plurality of semiconductor fins having a pitch quartering dimension compared to the initially patterned photoresist feature 302.

[0138] As an example, referring to FIG. 3B, a plurality of semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer feature 310 as a mask for patterning, such as dry or plasma etching patterning. However, in the example of FIG. 3B, the plurality of semiconductor fins 350 have various pitches and spacings. Such an integrated fin spacer patterning approach can be implemented to substantially remove the presence of fins at specific positions of the pattern of the plurality of fins. Thus, integrating the first spacer feature 306 at a specific position enables the fabrication of 6 or 4 fins based on two first backbone features 304 that typically produce 8 fins, as described in connection with FIGS. 2A and 2B. As an example, the fins within a board can have a more dense pitch that is normally enabled by generating fins at a uniform pitch and then cutting away the unwanted fins. However, the latter approach can still be implemented in accordance with the embodiments described herein.

[0139] In an exemplary embodiment, referring to FIG. 3B which is an integrated circuit structure, a first plurality of semiconductor fins 352 have a longest dimension along a first direction (y going into the page). Adjacent individual semiconductor fins 353 among the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount (S1) in a second direction (x) orthogonal to the first direction y. A second plurality of semiconductor fins 354 have a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 among the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount (S1) in the second direction. The closest semiconductor fin 356 of the first plurality of semiconductor fins 352 and the semiconductor fin 357 of the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1 but less than twice the first amount S1. In another embodiment, the second amount S2 is greater than twice the first amount S1.

[0140] In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with the underlying single-crystalline silicon substrate. In one embodiment, each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 has sidewalls that are tapered outwardly along the second direction x from the top to the bottom of each of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

[0141] In another exemplary embodiment, referring to FIGS. 3A and 3B, a method of manufacturing an integrated circuit structure includes forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). A primary spacer structure 306 is formed adjacent to the sidewalls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). The primary spacer structure 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) is integrated. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and first, second, third, and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (e.g., the pair of central secondary backbone structures 308) are integrated. A secondary spacer structure 310 is formed adjacent to the sidewalls of the first, second, third, and fourth secondary backbone structures 308. Next, the first, second, third, and fourth secondary backbone structures 308 are removed. Next, semiconductor material is patterned with the secondary spacer structure 310, and semiconductor fins 350 are formed in the semiconductor material.

[0142] In one embodiment, the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are patterned at a sub - design rule spacing between the first primary backbone structure and the second primary backbone structure. In one embodiment, the semiconductor material includes silicon. In one embodiment, each of the semiconductor fins 350 has sidewalls that are tapered outward along a second direction x from the top to the bottom of each of the semiconductor fins 350. In one embodiment, the semiconductor fins 350 are continuous with the underlying single - crystal silicon substrate. In one embodiment, patterning the semiconductor material with the secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, and adjacent individual semiconductor fins among the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x that is orthogonal to the first direction y. A second plurality of semiconductor fins 354 having a longest dimension along the first direction y are formed, and adjacent individual semiconductor fins among the second plurality of semiconductor fins 354 are spaced apart from each other by the first amount S1 in the second direction x. The closest semiconductor fin 356 of the first plurality of semiconductor fins 352 and the semiconductor fin 357 of the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount S2 in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1. In such an embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is greater than twice the first amount S1 but less than three times the first amount S1. In one embodiment, as illustrated in FIG. 3B, the first plurality of semiconductor fins 352 has exactly five semiconductor fins, and the second plurality of semiconductor fins 254 has exactly five semiconductor fins.

[0143] In another aspect, in a fin trimming process where fin removal is performed instead of the integrated fin approach, it should be understood that the fins can be trimmed (removed) by physically removing the fins during the patterning of the hard mask. As an example of the latter approach, FIGS. 4A through 4C show cross-sectional views representing various steps in a method of manufacturing a plurality of semiconductor fins according to one embodiment of the present disclosure.

[0144] Referring to FIG. 4A, a patterned hard mask layer 402 is formed over a semiconductor layer 404, such as a bulk single crystal silicon layer. Referring to FIG. 4B, fins 406 are then formed in the semiconductor layer 404, for example, by a dry or plasma etching process. Referring to FIG. 4C, selected fins 406 are removed, for example, by using a masking and etching process. In the example shown, one of the fins 406 is removed, leaving a remaining fin stub 408 as illustrated in FIG. 4C. In such an "after fin trimming" approach, the hard mask 402 is patterned as a whole, providing a lattice structure without removing or modifying individual features. The number of fins is not changed until after the fins are manufactured.

[0145] In another aspect, a multilayer trench isolation region, which may be referred to as a shallow trench isolation (STI) structure, can be implemented between semiconductor fins. In one embodiment, a multilayer STI structure is formed between silicon fins formed in a bulk silicon substrate, defining sub-fin regions of the silicon fins.

[0146] It may be desirable to use bulk silicon for fins or tri-gate based transistors. However, there is a concern that the region (sub-fin) below the active silicon fin portion of the device (e.g., the gate control region or HSi) has weak or no gate control. Therefore, when the source or drain region is at or below the HSi position, a leakage path through the sub-fin region may exist. For proper device operation, it may be necessary to control the leakage path in the sub-fin region.

[0147] One approach to address the above problem involves the use of well implant operations where the sub-fin region is doped at a high concentration (e.g., much higher than 2E18 / cm 3 This prevents sub-fin leakage but also leads to significant doping in the fins. The addition of halo implants further increases fin doping, such that the ends of the linear fins are doped at a high level (e.g., higher than about 1E18 / cm 3 ).

[0148] Another approach involves doping provided through sub-fin doping that does not necessarily supply the same level of doping to the HSi portion of the fin. The process may involve selectively doping the sub-fin region of a tri-gate or FinFET transistor fabricated on a bulk silicon wafer, for example, through the out-diffusion of tri-gate doping glass. For example, by selectively doping the sub-fin region of a tri-gate or FinFET transistor, sub-fin leakage can be reduced while keeping fin doping low. After recessing from the fin sidewalls, a solid state doping source (e.g., p-type and n-type doping oxides, nitrides, or carbides) is incorporated into the transistor process flow to provide sufficient doping to the sub-fin region while keeping the fin body relatively undoped.

[0149] Accordingly, the process scheme can include the use of a solid source doping layer (e.g., boron-doped oxide) deposited on the fins following fin etching. Subsequently, after trench filling and polishing, the doping layer is recessed together with the trench fill material to define the height of the fins (HSi) of the device. This process removes the doping layer from the fin sidewalls above HSi. Accordingly, the doping layer is present only in the portion along the fin sidewalls in the sub-fin region, thereby ensuring precise control of the doping profile. After drive-in annealing, the high-concentration doping is limited to the sub-fin region and rapidly transitions to low-concentration doping in the adjacent regions of the fins above HSi (which form the channel region of the transistor). Generally, borosilicate glass (BSG) is implemented for NMOS fin doping, while phosphosilicate glass (PSG) or arsenic phosphosilicate glass (AsSG) layers are implemented for PMOS fin doping. In one example, such a p-type solid state dopant source layer is a BSG layer having a boron concentration in the range of approximately 0.1 to 10 wt%. In another example, such an n-type solid state dopant source layer is a PSG layer or an AsSG layer having a concentration of phosphorus or arsenic in the range of approximately 0.1 to 10 wt% respectively. A silicon nitride capping layer can be included in the doping layer, while silicon dioxide or silicon oxide fill material can be included in the silicon nitride capping layer.

[0150] According to another embodiment of the present disclosure, the sub-fin leakage is small enough for relatively thin fins (e.g., fins having a width less than about 20 nanometers), and an undoped or slightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fins, a silicon nitride layer is formed on the undoped or slightly doped silicon oxide or silicon dioxide film, and silicon dioxide or silicon oxide fill material is included in the silicon nitride capping layer. It should be understood that doping of the sub-fin region, such as halo doping, can also be implemented with such a structure.

[0151] FIG. 5A shows a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present disclosure.

[0152] Referring to FIG. 5A, the integrated circuit structure includes fins 502 such as silicon fins. The fin 502 includes a lower fin portion (sub-fin) 502A and an upper fin portion 502B (H Si ). A first insulating layer 504 is immediately above the sidewalls of the lower fin portion 502A of the fin 502. A second insulating layer 506 is immediately above the first insulating layer 504 that is immediately above the sidewalls of the lower fin portion 502A of the fin 502. A dielectric filling material 508 is adjacent immediately beside the second insulating layer 506 that is immediately above the first insulating layer 504 that is immediately above the sidewalls of the lower fin portion 502A of the fin 502.

[0153] In one embodiment, the first insulating layer 504 is an undoped insulating layer containing silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 504 contains silicon and oxygen and does not contain other atomic species with an atomic concentration higher than 1E15 atoms per cubic centimeter. In one embodiment, the thickness of the first insulating layer 504 ranges from 0.5 to 2 nanometers.

[0154] In one embodiment, the second insulating layer 506 contains silicon and nitrogen, such as a silicon nitride insulating layer with a normal composition of Si3N4, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the thickness of the second insulating layer 506 ranges from 2 to 5 nanometers.

[0155] In one embodiment, the dielectric filling material 508 contains silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. Finally, in one embodiment, a gate electrode is formed above the top of the upper fin portion 502B of the fin 502 and laterally adjacent to its sidewalls.

[0156] During processing, it should be understood that the upper fin portion of the semiconductor fin can be eroded or consumed. Also, the trench isolation structure between fins can similarly be eroded and have a non-planar topography, or can be formed by non-planar topography up manufacturing. As an example, FIG. 5B shows a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present disclosure.

[0157] Referring to FIG. 5B, the integrated circuit structure includes a first fin 552 such as a silicon fin. The first fin 552 includes a lower fin portion 552A and an upper fin portion 552B, and a shoulder feature 554 in the region between the lower fin portion 552A and the upper fin portion 552B. A second fin 562 such as a second silicon fin includes a lower fin portion 562A and an upper fin portion 562B, and a shoulder feature 564 in the region between the lower fin portion 562A and the upper fin portion 562B. A first insulating layer 574 is immediately above the sidewalls of the lower fin portion 552A of the first fin 552 and immediately above the sidewalls of the lower fin portion 562A of the second fin 562. The first insulating layer 574 has a first end 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 further has a second end 574B that is substantially coplanar with the shoulder feature 564 of the second fin 562. A second insulating layer 576 is immediately above the first insulating layer 574 that is immediately above the sidewalls of the lower fin portion 552A of the first fin 552 and immediately above the sidewalls of the lower fin portion 562A of the second fin 562.

[0158] The dielectric fill material 578 is immediately adjacent to the side of the second insulating layer 576 that is immediately above the first insulating layer 574 that is immediately above the sidewalls of the lower fin portion 552A of the first fin 552 and immediately above the sidewalls of the lower fin portion 562A of the second fin 562. In one embodiment, the dielectric fill material 578 has an upper surface 578A, and as shown in FIG. 5B, a portion of the upper surface 578A of the dielectric fill material 578 is under at least one of the shoulder features 554 of the first fin 552 and under at least one of the shoulder features 564 of the second fin 562.

[0159] In one embodiment, the first insulating layer 574 is an undoped insulating layer containing silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 574 contains silicon and oxygen and does not contain other atomic species with an atomic concentration higher than 1E15 atoms per cubic centimeter. In one embodiment, the thickness of the first insulating layer 574 is in the range of 0.5 to 2 nanometers.

[0160] In one embodiment, the second insulating layer 576 contains silicon and nitrogen, such as a silicon nitride insulating layer with a stoichiometric composition of Si3N4, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the thickness of the second insulating layer 576 is in the range of 2 to 5 nanometers.

[0161] In one embodiment, the dielectric filling material 578 contains silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, finally, the gate electrode is formed above the top of the upper fin portion 552B of the first fin 552 and laterally adjacent to its sidewalls, and above the top of the upper fin portion 562B of the second fin 562 and laterally adjacent to its sidewalls. The gate electrode is further above the dielectric filling material 578 between the first fin 552 and the second fin 562.

[0162] FIGS. 6A to 6D show cross-sectional views of various steps in the manufacture of a three-layer trench isolation structure according to an embodiment of the present disclosure.

[0163] Referring to FIG. 6A, a method of manufacturing an integrated circuit structure includes forming fins 602 such as silicon fins. As shown in FIG. 6B, a first insulating layer 604 is conformally formed immediately above the fins 602. In one embodiment, the first insulating layer 604 contains silicon and oxygen and does not contain other atomic species with an atomic concentration higher than 1E15 atoms per cubic centimeter.

[0164] Referring to FIG. 6C, a second insulating layer 606 is conformally formed immediately above the first insulating layer 604. In one embodiment, the second insulating layer 606 contains silicon and nitrogen. A dielectric filling material 608 is formed immediately above the second insulating layer 606, as shown in FIG. 6D.

[0165] In one embodiment, the method further involves recessing the dielectric filling material 608, the first insulating layer 604, and the second insulating layer 606 to provide a fin 602 having an exposed upper fin portion 602A (e.g., the upper fin portions 502B, 552B, or 562B of FIGS. 5A and 5B, etc.). The resulting structure can be described in connection with FIG. 5A or FIG. 5B. In one embodiment, recessing the dielectric filling material 608, the first insulating layer 604, and the second insulating layer 606 involves the use of a wet etching process. In another embodiment, recessing the dielectric filling material 608, the first insulating layer 604, and the second insulating layer 606 involves the use of a plasma etching or dry etching process.

[0166] In one embodiment, the first insulating layer 604 is formed using a chemical vapor deposition process. In one embodiment, the second insulating layer 606 is formed using a chemical vapor deposition process. In one embodiment, the dielectric filling material 608 is formed using a spin-on process. In such an embodiment, the dielectric filling material 608 is a spin-on material and is, for example, subjected to a steam treatment either before or after a recess etching process to provide a cured material containing silicon and oxygen. In one embodiment, a gate electrode is finally formed above the top of the upper fin portion of the fin 602 and laterally adjacent to its sidewall.

[0167] In another aspect, a gate sidewall spacer material can be held above a particular trench isolation region to protect against erosion of the trench isolation region during subsequent processing steps. For example, FIGS. 7A through 7E show perspective three-dimensional cross-sectional views of various steps in a method of manufacturing an integrated circuit structure according to one embodiment of the present disclosure.

[0168] Referring to FIG. 7A, a method of manufacturing an integrated circuit structure includes forming fins 702 such as silicon fins. The fins 702 have a lower fin portion 702A and an upper fin portion 702B. An insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portion 702A of the fins 702. A gate structure 706 is formed above the upper fin portion 702B and above the insulating structure 704. In one embodiment, the gate structure is a placeholder or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is conformally formed on the upper fin portion 702B of the fins 702, conformally on the gate structure 706, and conformally on the insulating structure 704.

[0169] Referring to FIG. 7B, a hard mask material 710 is formed above the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0170] Referring to FIG. 7C, the hard mask material 710 is recessed to form a recessed hard mask material 712, exposing a portion of the dielectric material 708 that is conformal to the upper fin portion 702B of the fins 702 and conformal to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that is conformal to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0171] Referring to FIG. 7D, the dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as dielectric spacers 714A), along a portion of the sidewalls of the upper fin portion 702B of the fins 702, and above the insulating structure 704.

[0172] Referring to FIG. 7E, the recessed hard mask material 712 is removed from the structure of FIG. 7D. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as will be described in more detail below.

[0173] Referring again to FIG. 7E, in one embodiment, the integrated circuit structure 700 includes a first fin (left 702), such as a first silicon fin, which has a lower fin portion 702A and an upper fin portion 702B. The integrated circuit structure further includes a second fin (right 702), such as a second silicon fin, which has a lower fin portion 702A and an upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portion 702A of the first fin and directly adjacent to the sidewalls of the lower fin portion 702A of the second fin. The gate electrode 706 is above the upper fin portion 702B of the first fin (left 702), above the upper fin portion 702B of the second fin (right 702), and above a first portion 704A of the insulating structure 704. The first dielectric spacer 714A is along the sidewall of the upper fin portion 702B of the first fin (left 702), and the second dielectric spacer 702C is along the sidewall of the upper fin portion 702B of the second fin (right 702). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B above a second portion 704B of the insulating structure 704 between the first fin (left 702) and the second fin (right 702).

[0174] In one embodiment, the first and second dielectric spacers 714B and 714C include silicon and nitrogen, such as a regular composition Si3N4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-pure silicon nitride material.

[0175] In one embodiment, the integrated circuit structure 700 further includes an embedded source or drain structure on opposite side surfaces of the gate electrode 706. As will be described later in connection with FIG. 9B, the embedded source or drain structure has a bottom surface along the sidewalls of the upper fin portions 702B of the first and second fins 702 and below the top surfaces of the first and second dielectric spacers 714B and 714C, and the source or drain structure has a top surface along the sidewalls of the upper fin portions 702B of the first and second fins 702 and above the top surfaces of the first and second dielectric spacers 714B and 714C. In one embodiment, as will also be described later in connection with FIG. 9B, the insulating structure 704 includes a first insulating layer, a second insulating layer immediately above the first insulating layer, and a dielectric filling material immediately beside the second insulating layer.

[0176] FIGS. 8A through 8F show slightly projected cross-sectional views, cut along axis a-a' of FIG. 7E, of various steps in a method of manufacturing an integrated circuit structure, according to one embodiment of the present disclosure.

[0177] Referring to FIG. 8A, a method of manufacturing an integrated circuit structure includes forming fins 702, such as silicon fins. The fins 702 have a lower fin portion (not shown in FIG. 8A) and an upper fin portion 702B. The insulating structure 704 is formed directly adjacent to the sidewalls of the lower fin portions 702A of the fins 702. A pair of gate structures 706 are formed above the upper fin portions 702B and above the insulating structure 704. It should be understood that the viewpoints shown in FIGS. 8A through 8F are slightly projected in order to show a portion of the gate structure 706 and the insulating structure in front of (out of the page) the upper fin portion 702B such that the upper fin portion is slightly into the page. In one embodiment, the gate structure 706 is a placeholder or dummy gate structure that includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0178] Referring to FIG. 8B corresponding to the process steps described in relation to FIG. 7A, the dielectric material 708 is conformally formed on the upper fin portion 702B of the fin 702, conformally on the gate structure 706, and conformally on the exposed portion of the insulating structure 704.

[0179] Referring to FIG. 8C corresponding to the process steps described in relation to FIG. 7B, a hard mask material 710 is formed over the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0180] Referring to FIG. 8D corresponding to the process steps described in relation to FIG. 7C, the hard mask material 710 is recessed to form a recessed hard mask material 712, exposing a portion of the dielectric material 708 that is conformal to the upper fin portion 702B of the fin 702 and conformal to the gate structure 706. The recessed hard mask material 712 covers a portion of the dielectric material 708 that is conformal to the insulating structure 704. In one embodiment, the hard mask material 710 is recessed using a wet etching process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

[0181] Referring to FIG. 8E corresponding to the process steps described in relation to FIG. 7D, the dielectric material 708 is anisotropically etched to form a patterned dielectric material 714 along the sidewalls of the gate structure 706 (as portion 714A), along a portion of the sidewalls of the upper fin portion 702B of the fin 702, and over the insulating structure 704.

[0182] Referring to FIG. 8F corresponding to the process steps described in connection with FIG. 7E, the recessed hard mask material 712 is removed from the structure of FIG. 8E. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming an embedded source or drain structure on opposite sidewalls of the gate structure 706, as will be described in more detail below.

[0183] Referring again to FIG. 8F, in one embodiment, the integrated circuit structure 700 includes fins 702 such as silicon fins, and the fins 702 have a lower fin portion (not shown in FIG. 8F) and an upper fin portion 702B. The insulating structure 704 is directly adjacent to the sidewalls of the lower fin portion of the fin 702. The first gate electrode (left 706) is above the upper fin portion 702B and above the first portion 704A of the insulating structure 704. The second gate electrode (right 706) is above the upper fin portion 702B and above the second portion 704A' of the insulating structure 704. The first dielectric spacer (right 714A of left 706) is along the sidewall of the first gate electrode (left 706), and the second dielectric spacer (left 714A of right 706) is along the sidewall of the second gate electrode (right 706), and the second dielectric spacer is continuous with the first dielectric spacer above the third portion 704A" of the insulating structure 704 between the first gate electrode (left 706) and the second gate electrode (right 706).

[0184] FIG. 9A shows a slightly projected cross-sectional view taken along the axis a-a' of FIG. 7E of an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region according to an embodiment of the present disclosure. FIG. 9B shows a cross-sectional view taken along the axis b-b' of FIG. 7E of an integrated circuit structure including an epitaxial source or drain region and a multilayer trench isolation structure according to an embodiment of the present disclosure.

[0185] Referring to FIGS. 9A and 9B, in one embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on opposite side surfaces of the gate electrode 706. The embedded source or drain structure 910 has a bottom surface 910A below the top surface 990 of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702. The embedded source or drain structure 910 has a top surface 910B above the top surface of the first and second dielectric spacers 714B and 714C along the sidewalls of the upper fin portions 702B of the first and second fins 702.

[0186] In one embodiment, the gate stack 706 is a permanent gate stack 920. In such an embodiment, the permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, as illustrated in FIG. 9A. In one embodiment, where the permanent gate structure 920 is above the insulating structure 704, the permanent gate structure 920 is formed on a residual polycrystalline silicon portion 930 that can be the remainder of a replacement gate process with a sacrificial polycrystalline silicon gate electrode.

[0187] In one embodiment, the insulating structure 704 includes a first insulating layer 902, a second insulating layer 904 immediately above the first insulating layer 902, and a dielectric fill material 906 immediately adjacent to the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer containing silicon and oxygen. In one embodiment, the second insulating layer 904 contains silicon and nitrogen. In one embodiment, the dielectric fill material 906 contains silicon and oxygen.

[0188] In another aspect, the embedded epitaxial source or drain region is implemented as a source or drain structure for a semiconductor fin. By way of example, FIG. 10 shows a cross-sectional view of an integrated circuit structure cut at a source or drain location, according to one embodiment of the present disclosure.

[0189] Referring to FIG. 10, the integrated circuit structure 1000 includes P-type devices such as P-type metal oxide semiconductor (PMOS) devices. Also, the integrated circuit structure 1000 includes N-type devices such as N-type metal oxide semiconductor (NMOS) devices.

[0190] The PMOS devices in FIG. 10 include a first plurality of semiconductor fins 1002 such as silicon fins formed from a bulk silicon substrate 1001. At the source or drain positions, the upper portions of the fins 1002 are removed and the same or different semiconductor materials are grown to form source or drain structures 1004. It should be understood that the source or drain structures 1004 will appear identical in a cross-sectional view cut on either side of the gate electrode. For example, they will appear substantially the same on the source side as on the drain side. In one embodiment, as shown, the source or drain structure 1004 has a portion below and a portion above the upper surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structure 1004 is strongly faceted. In one embodiment, a conductive contact 1008 is formed above the source or drain structure 1004. However, in such an embodiment, the strong faceting and relatively wide growth of the source or drain structure 1004 at least somewhat inhibits good coverage by the conductive contact 1008.

[0191] The NMOS device of FIG. 10 includes a plurality of second semiconductor fins 1052, such as silicon fins, formed from a bulk silicon substrate 1001. At the source or drain location, the upper portion of the fin 1052 is removed and the same or a different semiconductor material is grown to form the source or drain structure 1054. It should be understood that the source or drain structure 1054 will appear the same in a cross-sectional view cut on either side of the gate electrode. For example, they will appear essentially the same on the source side as on the drain side. In one embodiment, as shown, the source or drain structure 1054 includes a portion below and a portion above the upper surface of the insulating structure 1006. In one embodiment, as shown, the source or drain structure 1054 is less faceted compared to the source or drain structure 1004. In one embodiment, the conductive contact 1058 is formed above the source or drain structure 1054. In such an embodiment, the relatively weak faceting of the source or drain structure 1054 (compared to the source or drain structure 1004) and the resulting relatively narrow growth facilitate good coverage by the conductive contact 1058.

[0192] The shape of the source or drain structure of the PMOS device can be diverse so as to improve the contact area with the upper layer contact. For example, FIG. 11 shows a cross-sectional view of another integrated circuit structure cut at the source or drain location according to an embodiment of the present disclosure.

[0193] Referring to FIG. 11, the integrated circuit structure 1100 includes P-type semiconductor (e.g., PMOS) devices. The PMOS devices include a first fin 1102 such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is on a first side of a first gate electrode (which may be formed above an upper fin portion such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is embedded in the first fin 1102 on a second side of such a first gate electrode opposite the first side. In one embodiment, the first and second epitaxial source or drain structures 1104 include silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick-like profile as illustrated in FIG. 11. A first conductive electrode 1108 is above the first epitaxial source or drain structure 1104.

[0194] Referring again to FIG. 11, in one embodiment, the integrated circuit structure 1100 also includes N-type semiconductor (e.g., NMOS) devices. The NMOS devices include a second fin 1152 such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In one embodiment, although not shown, the third epitaxial source or drain structure 1154 is on a first side of a second gate electrode (which may be formed above an upper fin portion such as a channel portion of the fin 1152), and a fourth epitaxial source or drain structure is embedded in the second fin 1152 on a second side of such a second gate electrode opposite the first side. In one embodiment, the third and fourth epitaxial source or drain structures 1154 include silicon and have a profile that is substantially the same as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is above the third epitaxial source or drain structure 1154.

[0195] In one embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In one embodiment, the height of the first epitaxial source or drain structure 1104 is about 50 nanometers, and the width is in the range of 30 - 35 nanometers. In such an embodiment, the height of the third epitaxial source or drain structure 1154 is about 50 nanometers, and the width is in the range of 30 - 35 nanometers.

[0196] In one embodiment, in the first epitaxial source or drain structure 1104, there is a gradient from a germanium concentration of about 20% at the bottom 1104A of the first epitaxial source or drain structure 1104 to a germanium concentration of about 45% at the top 1104B of the first epitaxial source or drain structure 1104. In one embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In such an embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

[0197] Figures 12A through 12D show cross-sectional views taken at a source or drain location, representing various steps in the manufacture of an integrated circuit structure, according to one embodiment of the present disclosure.

[0198] Referring to FIG. 12A, a method of manufacturing an integrated circuit structure includes forming fins such as silicon fins formed from a silicon substrate 1201. The fin 1202 has a lower fin portion 1202A and an upper fin portion 1202B. In one embodiment, although not shown, at a position deeper in the page, a gate electrode is formed above a part of the upper fin portion 1202B of the fin 1202. Such a gate electrode has a first side facing a second side, and source or drain positions are defined on the first and second sides. For example, for purposes of illustration, the cross-sectional position of the views in FIGS. 12A - 12D is cut at one of the source or drain positions at one of the sides of the gate electrode.

[0199] Referring to FIG. 12B, the source or drain position of fin 1202 is recessed to form a recessed fin portion 1206. The recessed source or drain position of fin 1202 can be on the side surface of the gate electrode and the second side surface of the gate electrode. Referring to both FIGS. 12A and 12B, in one embodiment, a dielectric spacer 1204 is formed along a part of the sidewall of fin 1202, for example, on the side surface of the gate structure. In such an embodiment, the recessing of fin 1202 involves recessing fin 1202 below the top surface 1204A of dielectric spacer 1204.

[0200] Referring to FIG. 12C, an epitaxial source or drain structure 1208 is formed on recessed fin 1206 and thus can be formed, for example, on the side surface of the gate electrode. In such an embodiment, a second epitaxial source or drain structure is formed on a second portion of recessed fin 1206 on the second side surface of such a gate electrode. In one embodiment, epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick-shaped profile as shown in FIG. 12C. In one embodiment, as shown, dielectric spacer 1204 is included and is along the lower part 1208A of the sidewall of epitaxial source or drain structure 1208.

[0201] Referring to FIG. 12D, a conductive electrode 1210 is formed on epitaxial source or drain structure 1208. In one embodiment, conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filling material 1201B. In one embodiment, conductive electrode 1210 follows the profile of epitaxial source or drain structure 1208 as shown. In other embodiments, the upper part of epitaxial source or drain structure 1208 is etched during the manufacture of conductive electrode 1210.

[0202] In another aspect, fin trim isolation (FTI) and single gate pitch for the isolation fins are described. Non-planar transistors that utilize fins of semiconductor material protruding from a substrate surface employ gate electrodes that cover two, three, or even all sides of the fin (i.e., dual gate, tri-gate, nanowire transistors). Next, the source and drain regions are typically formed either within the fin or as regrown portions of the fin, on either side of the gate electrode. A gap or space can be formed between two adjacent fins to separate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor. Such a separation gap generally requires some kind of masked etching. Once separated, the gate stack is then typically patterned over the individual fins using some kind of masked etching (e.g., line etching or opening etching depending on the particular implementation).

[0203] One potential problem with the above-described fin separation techniques is that the gate does not self-align with the ends of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern depends on the overlay of these two patterns. Thus, the lithographic overlay tolerance is added to the dimensions of the semiconductor fin and the separation gap, and the fin needs to be of a larger length and the separation gap needs to be larger compared to the length required for a given level of transistor functionality. Therefore, device architectures and manufacturing techniques that reduce such excessive dimensions provide a highly advantageous improvement in transistor density.

[0204] Another potential problem with the fin separation techniques described above is that the stress in the semiconductor fins, which is desirable to improve carrier mobility, can be lost from the channel region of the transistor, where a very large number of fin surfaces remain exposed during manufacturing, allowing relaxation of the fin strain. Thus, device architectures and manufacturing techniques that maintain a higher level of desirable fin stress provide advantageous improvements in non-planar transistor performance.

[0205] An architecture and technique for through-gate fin separation according to an embodiment of the present disclosure are described herein. In the exemplary embodiments shown, non-planar transistors in a microelectronic device such as an integrated circuit (IC) are separated from each other in a self-aligned manner with respect to the gate electrodes of the transistors. Embodiments of the present disclosure are applicable to virtually any IC that utilizes non-planar transistors, and exemplary ICs include, but are not limited to, microprocessor cores that include logic and memory (SRAM) portions, RFICs (e.g., wireless ICs that include digital baseband and analog front-end modules), and power ICs.

[0206] In an embodiment, two ends of adjacent semiconductor fins are electrically separated from each other by a separation region positioned with respect to a gate electrode using only one patterning mask level. In one embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, with a first subset of the placeholder stripes defining the position or dimension of the separation region and a second subset of the placeholder stripes defining the position or dimension of the gate electrode. In a particular embodiment, the first subset of the placeholder stripes is removed, a separation cut is formed in the semiconductor fins at the opening resulting from the removal of the first subset, while the second subset of the placeholder stripes is ultimately replaced with a non-sacrificial gate electrode stack. Since a subset of the placeholder utilized for gate electrode replacement is employed to form the separation region, the method and the resulting architecture are herein referred to as "through-gate" separation. One or more embodiments of through-gate separation described herein may enable, for example, a higher transistor density and a higher level of advantageous transistor channel stress.

[0207] By defining the separation after the placement or definition of the gate electrode, a greater transistor density can be achieved. This is because the separation dimensions and the pitch of the fins can be perfectly matched to the pitch of the gate electrode, such that both the gate electrode and the separation region are integer multiples of the minimum feature pitch of a single masking level. In a further embodiment where the semiconductor fins have a lattice that is misaligned with the substrate on which the fins are placed, a greater degree of strain is maintained by defining the separation after the placement or definition of the gate electrode. For such embodiments, other features of the transistor (such as the gate electrode and the added source or drain material) formed before the ends of the fins are defined assist in mechanically holding the fin strain after the separation cut is made in the fins.

[0208] Providing further context, transistor scaling can benefit from a more dense packing of cells within a chip. Currently, most cells are isolated from their surroundings by two or more dummy gates having buried fins. The cells are separated by etching fins under these two or more dummy gates that connect one cell to another. Scaling can be significantly beneficial if the number of dummy gates isolating adjacent cells can be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins under two or more dummy gates are etched during fin patterning. A potential problem with such an approach is that the dummy gates consume chip space that could be used for cells. In one embodiment, the approach described herein enables isolating adjacent cells using only a single dummy gate.

[0209] In one embodiment, the fin trimming isolation approach is implemented as a self-aligned patterning scheme. Here, the fins under a single gate are removed by etching. Thus, adjacent cells can be isolated by a single dummy gate. Advantages of such an approach can include saving chip space and enabling more computing power for a given area. The approach can also enable performing fin trimming at a sub-fin pitch distance.

[0210] FIGS. 13A and 13B show plan views depicting various steps in a method of patterning fins at a multi-gate interval to form a local isolation structure according to one embodiment of the present disclosure.

[0211] Referring to FIG. 13A, a plurality of fins 1302 having a length along a first direction 1304 are shown. A grid 1306 having spaces 1307 therebetween, which defines positions for ultimately forming a plurality of gate lines, is shown along a second direction 1308 orthogonal to the first direction 1304.

[0212] Referring to FIG. 13B, a portion of the plurality of fins 1302 is cut (e.g., removed by an etching process), leaving fins 1310 having cuts 1312 therein. Thus, the isolation structure ultimately formed at the cuts 1312 has a dimension larger than that of a single gate line (e.g., the dimension of three gate lines 1306). Thus, the gate structure ultimately formed along the positions of the gate lines 1306 will be formed at least partially above the isolation structure formed at the cuts 1312. Thus, the cuts 1312 are relatively wide fin cuts.

[0213] FIGS. 14A through 14D show plan views representing various steps in a method of patterning fins having a single gate spacing for forming a local isolation structure, according to another embodiment of the present disclosure.

[0214] Referring to FIG. 14A, a method of manufacturing an integrated circuit structure includes forming a plurality of fins 1402, each of the plurality of fins 1402 having a longest dimension along a first direction 1404. A plurality of gate structures 1406 are above the plurality of fins 1402, each of the gate structures 1406 having a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In one embodiment, the gate structures 1406 are sacrificial or dummy gate lines and are made of, for example, polycrystalline silicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of a lower silicon substrate.

[0215] Referring to FIG. 14B, a dielectric material structure 1410 is formed between adjacent ones of the plurality of gate structures 1406.

[0216] Referring to FIG. 14C, a portion 1412 of one of the plurality of gate structures 1406 is removed, exposing a portion 1414 of each of the plurality of fins 1402. In one embodiment, removing a portion 1412 of one of the plurality of gate structures 1406 involves using a lithography window 1416 wider than the width 1418 of a portion 1412 of one of the plurality of gate structures 1406.

[0217] Referring to FIG. 14D, the exposed portions 1414 of each of the plurality of fins 1402 are removed, forming a cut region 1420. In one embodiment, the exposed portions 1414 of each of the plurality of fins 1402 are removed using a dry or plasma etching process. In one embodiment, removing the exposed portions 1414 of each of the plurality of fins 1402 involves etching to a depth less than the height of the plurality of fins 1402. In such an embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins 1402. In one embodiment, to provide a separation margin, the depth is deeper than the depth of the active portions of the plurality of fins 1402. In one embodiment, the exposed portions 1414 of each of the plurality of fins 1402 are removed without etching, or substantially without etching, the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402. In such an embodiment, the exposed portions 1414 of each of the plurality of fins 1402 are removed without laterally etching, or substantially without laterally etching, the source or drain regions (such as epitaxial source or drain regions) of the plurality of fins 1402.

[0218] In one embodiment, the cut region 1420 is ultimately filled with an insulating layer, for example, at the location of the removed portions 1414 of each of the plurality of fins 1402. Exemplary insulating layers, or “polycut” or “plug” structures, are described below. However, in other embodiments, the cut region 1420 is only partially filled with an insulating layer in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In one embodiment, prior to filling the cut region 1420 with an insulating layer, or with an insulating layer that houses a local interconnect structure, dopants can be implanted or supplied through the cut region 1420 into the fins or into the locally cut portions of the plurality of fins by a solid source dopant layer.

[0219] FIG. 15 shows a cross-sectional view of an integrated circuit structure comprising fins with multi-gate spacing for local isolation, according to one embodiment of the present disclosure.

[0220] Referring to FIG. 15, the silicon fin 1502 has a first fin portion 1504 that is laterally adjacent to a second fin portion 1506. The first fin portion 1504 is isolated from the second fin portion 1506 by a relatively wide cut 1508, such as described in connection with FIGS. 13A and 13B, and the relatively wide cut 1508 has a width X. A dielectric fill material 1510 is formed in the relatively wide cut 1508 to electrically isolate the first fin portion 1504 from the second fin portion 1506. A plurality of gate lines 1512 are above the silicon fin 1502, and each of the gate lines can include a gate dielectric and gate electrode stack 1514, a dielectric cap layer 1516, and sidewall spacers 1518. Two of the gate lines (the two leftmost gate lines 1512) occupy the relatively wide cut 1508, and thus the first fin portion 1504 is effectively isolated from the second fin portion 1506 by two dummy or non-active gates.

[0221] In contrast, the fin portions can be isolated by the distance of a single gate. As an example, FIG. 16A shows a cross-sectional view of an integrated circuit structure comprising fins with a single gate spacing for local isolation, according to another embodiment of the present disclosure.

[0222] Referring to FIG. 16A, silicon fin 1602 has a first fin portion 1604 that is laterally adjacent to a second fin portion 1606. The first fin portion 1604 is isolated from the second fin portion 1606 by a relatively narrow cut 1608 as described in connection with FIGS. 14A - 14D, and the relatively narrow cut 1608 has a width Y, where Y is less than X of FIG. 15. A dielectric fill material 1610 is formed in the relatively narrow cut 1608 to electrically separate the first fin portion 1604 from the second fin portion 1606. A plurality of gate lines 1612 are above the silicon fin 1602, and each of the gate lines may include a gate dielectric and gate electrode stack 1614, a dielectric cap layer 1616, and sidewall spacers 1618. The dielectric fill material 1610 occupies the position where a single gate line was previously located, and thus the first fin portion 1604 is isolated from the second fin portion 1606 by a single "packed" gate line. In one embodiment, as shown, residual spacer material 1620 remains on the sidewalls at the location of the removed gate line portion. It should be understood that other regions of the fin 1602 can be separated from each other by two or more non-active gate lines (region 1622 having three non-active gate lines) manufactured by a previous wide fin cut process, as will be described later.

[0223] Referring again to FIG. 16A, the integrated circuit structure 1600 comprises a fin 1602, such as a silicon fin. The fin 1602 has its longest dimension along a first direction 1650. The isolation structure 1610 isolates a first upper portion 1604 of the fin 1602 from a second upper portion 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0224] The first gate structure 1612A is above the first upper portion 1604 of the fin 1602, and the first gate structure 1612A has its longest dimension along a second direction 1652 (e.g., towards the back of the page) that is orthogonal to the first direction 1650. The center 1613A of the first gate structure 1612A is spaced from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. The second gate structure 1612B is above the first upper portion 1604 of the fin, and the second gate structure 1612B has its longest dimension along the second direction 1652. The center 1613B of the second gate structure 1612B is spaced from the center 1613A of the first gate structure 1612A by a pitch along the first direction 1650. The third gate structure 1612C is above the second upper portion 1606 of the fin 1602, and the third gate structure 1612C has its longest dimension along the second direction 1652. The center 1613C of the third gate structure 1612C is spaced from the center 1611 of the isolation structure 1610 by a pitch along the first direction 1650. In one embodiment, as shown, the isolation structure 1610 has a top that is substantially in the same plane as the tops of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C.

[0225] In one embodiment, as shown for the exemplary third gate structure 1612C, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on and between sidewalls of the high-k gate dielectric layer 1662. In such an embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 on the gate electrode 1660 and on the sidewalls of the high-k gate dielectric layer 1662.

[0226] In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on a first upper portion 1604 of a fin 1602 between a first gate structure 1612A and an isolation structure 1610. A second epitaxial semiconductor region 1664B is on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is on a second upper portion 1606 of the fin 1602 between a third gate structure 1612C and the isolation structure 1610. In one embodiment, the first epitaxial semiconductor region 1664A, the second epitaxial semiconductor region 1664B, and the third epitaxial semiconductor region 1664C include silicon and germanium. In another embodiment, the first epitaxial semiconductor region 1664A, the second epitaxial semiconductor region 1664B, and the third epitaxial semiconductor region 1664C include silicon.

[0227] In one embodiment, the isolation structure 1610 induces stress on the first upper portion 1604 of the fin 1602 and the second upper portion 1606 of the fin 1602. In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In one embodiment, dopants are implanted or supplied to a locally cut portion of the fin or fins by a solid source dopant layer before forming the insulating layer, or the isolation structure 1610 having an insulating layer that houses the local interconnect structure.

[0228] In another aspect, it should be understood that an isolation structure, such as the isolation structure 1610 described above, can be formed in place of the active gate electrode at a local location of the fin cut or at a wide location of the fin cut. Further, the depth of such a local or wide location of the fin cut can be formed at various depths relative to each other within the fin. In a first example, FIG. 16B shows a cross-sectional view showing a location where a fin isolation structure can be formed in place of the gate electrode according to one embodiment of the present disclosure.

[0229] Referring to FIG. 16B, fins 1680, such as silicon fins, can be formed continuously above and connected to substrate 1682. Fins 1680 have fin ends or wide fin cuts 1684, which can be formed during fin patterning, for example, in the above-described approach of trimming the fins last. Also, fins 1680 have local cuts 1686 where a portion of fins 1680 is removed using, for example, the fin trim isolation approach where dummy gates are replaced with dielectric plugs as described above. Active gate electrode 1688 is formed above the fins. For illustrative purposes, and with fins 1680 in the background, it is shown slightly in front of fins 1680, and the dashed line represents the area hidden from the front view. Dielectric plug 1690 can be formed at the fin ends or wide fin cuts 1684 instead of using an active gate at such positions. Additionally, or alternatively, dielectric plug 1692 can be formed at local cuts 1686 instead of using an active gate at such positions. Epitaxial source or drain regions 1694 are also shown at the positions of fins 1680 between active gate electrode 1688 and plug 1690 or 1692. Further, in one embodiment, as shown in FIG. 16B, the surface roughness of the fin ends at local cuts 1686 is rougher than that of the fin ends at the positions of the wide cuts.

[0230] FIGS. 17A through 17C show various possible depths for fin cuts manufactured using the fin trim isolation approach according to one embodiment of the present disclosure.

[0231] Referring to FIG. 17A, a semiconductor fin 1700, such as a silicon fin, can be formed continuously above and connected to a lower substrate 1702. The fin 1700 has a lower fin portion 1700A and an upper fin portion 1700B as defined by the height of the insulating structure 1704 with respect to the fin 1700. A local fin separation cut 1706A isolates the fin 1700 in the first fin portion 1710 from the second fin portion 1712. In the example of FIG. 17A, as shown along the axis a-a', the depth of the local fin separation cut 1706A is the overall depth of the fin 1700 to the substrate 1702.

[0232] Referring to FIG. 17B, in a second example, as shown along the axis a-a', the depth of the local fin separation cut 1706B is deeper than the overall depth of the fin 1700 to the substrate 1702. That is, the cut 1706B extends into the lower substrate 1702.

[0233] Referring to FIG. 17C, in a third example, as shown along the axis a-a', the depth of the local fin separation cut 1706C is less than the overall depth of the fin 1700 but deeper than the upper surface of the isolation structure 1704. Referring again to FIG. 17C, in a fourth example, as shown along the axis a-a', the depth of the local fin separation cut 1706D is less than the overall depth of the fin 1700 and is at approximately the same height as the upper surface of the isolation structure 1704.

[0234] FIG. 18 shows a plan view illustrating possible options for the depth of local and wide positions of fin cuts within a fin, according to an embodiment of the present disclosure, and a corresponding cross-sectional view taken along the axis a-a'.

[0235] Referring to FIG. 18, a first semiconductor fin 1800 and a second semiconductor fin 1802, such as a silicon fin, have upper fin portions 1800B and 1802B that extend above an insulating structure 1804. Both fins 1800 and 1802 have fin ends or wide fin cuts 1806 that can be formed, for example, during fin patterning in an approach such as trimming the fins described above last. Also, both fins 1800 and 1802 have local cuts 1808 where a portion of fin 1800 or 1802 has been removed using, for example, a fin trim isolation approach where a dummy gate is replaced with a dielectric plug as described above. In one embodiment, as illustrated in FIG. 18, the surface roughness of the ends of fins 1800 and 1802 at local cut 1808 is rougher than the ends of the fins at the location of 1806.

[0236] Referring to the cross-sectional view of FIG. 18, lower fin portions 1800A and 1802A can be seen below the height of insulating structure 1804. Also, as described above, a remnant 1810 of the fin removed in the process of trimming the fins last before the formation of insulating structure 1804 can be seen in the cross-sectional view. Although shown as protruding above the substrate, remnant 1810 can also be at the same height as the substrate or within the substrate, as illustrated by the depth of an additional exemplary wide cut 1820. It should be understood that the wide cuts 1806 for fins 1800 and 1802 can also be at the height described for the cut depth 1820 of the illustrated example. Local cut 1808 can have an exemplary depth corresponding to the depth described for FIGS. 17A through 17C, as illustrated.

[0237] Referring collectively to FIGS. 16A, 16B, 17A-17C, and 18, according to one embodiment of the present disclosure, an integrated circuit structure includes fins containing silicon. The fins have a top and sidewalls, and the top has a longest dimension along a first direction. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin along the first direction. The first isolation structure has a width along the first direction. The first end of the first portion of the fin has a surface roughness. The gate structure includes a gate electrode that is laterally adjacent to its sidewall above the top of the region of the first portion of the fin. The gate structure has a width along the first direction, and the center of the gate structure is spaced from the center of the first isolation structure by a pitch along the first direction. A second isolation structure is above a second end of the first portion of the fin, and the second end faces the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness smaller than the surface roughness of the first end of the first portion of the fin. The center of the second isolation structure is spaced from the center of the gate structure by a pitch along the first direction.

[0238] In one embodiment, the first end of the first portion of the fin has a scalloped topography as shown in FIG. 16B. In one embodiment, a first epitaxial semiconductor region is on the first portion of the fin between the gate structure and the first isolation structure. A second epitaxial semiconductor region is on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, and the width along the second direction is wider than the width of the first portion of the fin along the second direction under the gate structure. For example, the epitaxial features described in connection with FIGS. 11 and 12D have a wider width than the fin portions on which they grow at the perspectives shown in FIGS. 11 and 12D. In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first portion of the fin along the sidewall of the gate electrode.

[0239] Referring collectively to FIGS. 16A, 16B, 17A - 17C, and 18, according to another embodiment of the present disclosure, an integrated circuit structure includes fins including silicon. The fins have a top and sidewalls, and the top has a longest dimension along a direction. A first isolation structure isolates a first end of a first portion of the fin from a first end of a second portion of the fin along the direction. The first end of the first portion of the fin has a depth. A gate structure includes a gate electrode laterally adjacent to its sidewall and above the top of the region of the first portion of the fin. A second isolation structure is above a second end of the first portion of the fin, and the second end faces the first end. The second end of the first portion of the fin has a depth different from the depth of the first end of the first portion of the fin.

[0240] In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, the center of the gate structure is spaced from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is spaced from the center of the gate structure by a pitch along the direction.

[0241] Referring collectively to FIGS. 16A, 16B, 17A-17C, and 18, according to another embodiment of the present disclosure, an integrated circuit structure includes a first fin including silicon. The first fin has a top and sidewalls, and the top has a longest dimension along a direction. A discontinuity separates a first end of a first portion of the first fin from a first end of a second portion of the fin along the direction. The first portion of the first fin has a second end opposite the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin including silicon. The second fin has a top and sidewalls, and the top has a longest dimension along the direction. The integrated circuit structure also includes a remaining or residual fin portion between the first fin and the second fin. The residual fin portion has a top and sidewalls, and the top has a longest dimension along the direction, and the top is in a non-coplanar plane with the depth of the first end of the first portion of the fin.

[0242] In one embodiment, the depth of the first end of the first portion of the fin is below the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth above the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is above the top of the remaining or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth above the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth below the top of the residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth above the top of the residual fin portion.

[0243] In another aspect, the dielectric plugs formed at local or wide fin cut locations can be tailored to provide specific stress to the fins or fin portions. The dielectric plugs can be referred to as fin end stressors in such implementations.

[0244] One or more embodiments relate to the manufacture of fin-based semiconductor devices. Performance improvements for such devices can be made through channel stress induced from the polyplug filling process. Embodiments can include utilizing material properties in the polyplug filling process to induce mechanical stress in a metal-oxide-semiconductor field-effect transistor (MOSFET) channel. As a result, the induced stress can improve the mobility and drive current of the transistor. Further, the plug filling methods described herein can enable the elimination of any seam or void formation during deposition.

[0245] Providing context, stress can be induced in the channel by manipulating the inherent material properties of the plug filling in contact with the fin. According to one or more embodiments, by adjusting the composition, deposition, and post-treatment conditions of the plug filling material, the stress in the channel is regulated to be beneficial for both NMOS and PMOS transistors. Further, such plugs can be deeply embedded within the fin substrate compared to other common stressor techniques such as epitaxial source or drain. The nature of the plug filling to achieve such effects also eliminates seams or voids during deposition and reduces specific defect modes during the process.

[0246] Providing further context, there is currently no intentional stress engineering technology for gate (poly) plugs. Stress enhancement from conventional stressors, such as epitaxial source or drain, dummy poly gate removal, stress liners, etc., unfortunately tends to decay as the device pitch shrinks. To address one or more of the above problems, according to one or more embodiments of the present disclosure, additional stress sources are incorporated into the transistor structure. Another possible benefit of such a process may be to eliminate seams or voids within the plug, which may be common in other chemical vapor deposition methods.

[0247] FIGS. 19A and 19B show cross-sectional views of various steps in a method of selecting fin end stressor positions at the ends of fins having wide cuts as part of a process of trimming fins last, as in one embodiment of the present disclosure, such as described above.

[0248] Referring to FIG. 19A, a fin 1900, such as a silicon fin, is formed over a substrate 1902 and may be continuous therewith. The fin 1900 has fin ends, or wide fin cuts 1904, which may be formed during fin patterning, for example, in the above-described approach of trimming the fin last. Active gate electrode positions 1906 and dummy gate electrode positions 1908 are formed over the fin 1900 and are shown slightly in front of the fin 1900 for illustrative purposes, with the fin 1900 in the background, and the dashed lines represent regions hidden from the front view. It should be understood that the epitaxial source or drain regions 1910 are also shown at the position of the fin 1900 between the gate position 1906 and the gate position 1908. Further, the interlayer dielectric material 1912 is included at the position of the fin 1900 between the gate position 1906 and the gate position 1908.

[0249] Referring to FIG. 19B, the gate placeholder structure or dummy gate position 1908 is removed, and the fin end or wide fin cut 1904 is exposed. This removal forms an opening 1920 where a dielectric plug, such as a fin end stressor dielectric plug, can be ultimately formed.

[0250] FIGS. 20A and 20B show cross-sectional views of various steps in a method of selecting fin end stressor positions at the ends of fins having local cuts, as part of a process of fin trim isolation, according to an embodiment of the present disclosure, such as described above.

[0251] Referring to FIG. 20A, a fin 2000, such as a silicon fin, is formed over a substrate 2002 and may be continuous therewith. The fin 2000 has a local cut 2004, where a portion of the fin 2000 is removed using a fin trim isolation approach where the dummy gate is removed and the fin is etched to a local position, as described above. The active gate electrode position 2006 and the dummy gate electrode position 2008 are formed over the fin 2000 and are shown slightly in front of the fin 2000 for illustrative purposes, with the dashed lines representing areas hidden from a front view. It should be understood that the epitaxial source or drain region 2010 is also shown at the position of the fin 2000 between the gate position 2006 and the gate position 2008. Further, the interlayer dielectric material 2012 is included at the position of the fin 2000 between the gate position 2006 and the gate position 2008.

[0252] Referring to FIG. 20B, the gate placeholder structure or dummy gate electrode position 2008 is removed, and the fin end having the local cut 2004 is exposed. This removal forms an opening 2020 where a dielectric plug, such as a fin end stressor dielectric plug, can be ultimately formed.

[0253] Figures 21A through 21M show cross-sectional views of various steps in a method of manufacturing an integrated circuit structure with a differentiated fin end dielectric plug according to an embodiment of the present disclosure.

[0254] Referring to FIG. 21A, an initial structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the initial structure 2100 includes a first fin 2102, such as a first silicon fin, formed over and continuous with a substrate 2104. The first fin 2102 has a fin end 2106 that can be formed from a local or wide fin cut. A first active gate electrode position 2108 and a first dummy gate electrode position 2110 are formed over the first fin 2102 and are shown slightly in front of the first fin 2102 with the first fin 2102 as a background for illustrative purposes. Dashed lines represent regions hidden from a front view. Also, an epitaxial N-type source or drain region 2112, such as an epitaxial silicon source of a drain structure, is shown at a position of the first fin 2102 between the gate position 2108 and the gate position 2110. Further, an interlayer dielectric material 2114 is included at a position of the first fin 2102 between the gate position 2108 and the gate position 2110.

[0255] The PMOS region of the initial structure 2100 includes a second fin 2122, such as a second silicon fin, formed over and continuous with the substrate 2104. The second fin 2122 has a fin end 2126 that can be formed from a local or wide fin cut. A second active gate electrode position 2128 and a second dummy gate electrode position 2130 are formed over the second fin 2122 and are shown slightly in front of the second fin 2122 with the second fin 2122 as a background for illustrative purposes. Dashed lines represent regions hidden from a front view. Also, an epitaxial P-type source or drain region 2132, such as an epitaxial silicon germanium source of a drain structure, is shown at a position of the second fin 2122 between the gate position 2128 and the gate position 2130. Further, an interlayer dielectric material 2134 is included at a position of the second fin 2122 between the gate position 2128 and the gate position 2130.

[0256] Referring to FIG. 21B, the first dummy gate electrode at position 2110 and the second dummy gate electrode at position 2130 are removed. By this removal, the fin end portions 2106 of the first fin 2102 and the fin end portions 2126 of the second fin 2122 are exposed. Also, by this removal, openings 2116 and 2136 are respectively formed, and dielectric plugs such as fin end stressor dielectric plugs can be finally formed therein.

[0257] Referring to FIG. 21C, a conformal material liner 2140 is formed on the structure of FIG. 21B. In one embodiment, the material liner includes silicon and nitrogen such as a silicon nitride material liner.

[0258] Referring to FIG. 21D, a protective capping layer 2142 such as a metal nitride layer is formed on the structure of FIG. 21C.

[0259] Referring to FIG. 21E, a hard mask material 2144 such as a carbon-based hard mask material is formed above the structure of FIG. 21D. A lithography mask or mask stack 2146 is formed above the hard mask material 2144.

[0260] Referring to FIG. 21F, a part of the hard mask material 2144 or a part of the protective capping layer 2142 in the PMOS region is removed from the structure of FIG. 21E. The lithography mask or mask stack 2146 is also removed.

[0261] Referring to FIG. 21G, a second conformal material liner 2148 is formed on the structure of FIG. 21F. In one embodiment, the second material liner includes silicon and nitrogen such as a second silicon nitride material liner. In one embodiment, the second material liner 2148 has different stress states to adjust the stress in the exposed plugs.

[0262] Referring to FIG. 21H, a second hard mask material 2150, such as a second carbon-based hard mask material, is formed above the structure of FIG. 21G and then recessed into the opening 2136 of the PMOS region of the structure.

[0263] Referring to FIG. 21I, the second material liner 2148 is etched from the structure of FIG. 21H, so that the second material liner 2148 is removed from the NMOS region and the second material liner 2148 is recessed into the PMOS region of the structure.

[0264] Referring to FIG. 21J, the hard mask material 2144, the protective capping layer 2142, and the second hard mask material 2150 are removed from the structure of FIG. 21I. Due to this removal, two different filling structures remain in the opening 2116 as compared to the opening 2136.

[0265] Referring to FIG. 21K, an insulating filling material 2152 is formed and planarized in the openings 2116 and 2136 of the structure of FIG. 21J. In one embodiment, the insulating filling material 2152 is a flowable oxide material such as flowable silicon oxide or silicon dioxide material.

[0266] Referring to FIG. 21L, the insulating filling material 2152 is recessed into the openings 2116 and 2136 of the structure of FIG. 21K to form a recessed insulating filling material 2154. In one embodiment, a steam oxidation process is performed as part of or after the recessing process to cure the recessed insulating filling material 2154. In such an embodiment, the recessed insulating filling material 2154 shrinks and induces a tensile stress on the fins 2102 and 2122. However, the PMOS region has relatively less tensile stress inducing material than the NMOS region.

[0267] Referring to FIG. 21M, the third material liner 2156 is above the structure of FIG. 21L. In one embodiment, the third material liner 2156 includes silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 prevents the recessed insulating filling material 2154 from being removed by etching during or after source or drain contact etching.

[0268] FIGS. 22A through 22D show cross-sectional views of an exemplary structure of a PMOS fin end stressor dielectric plug according to an embodiment of the present disclosure.

[0269] Referring to FIG. 22A, the opening 2136 over the PMOS region of the structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. The second material liner 2148 is conformal to the lower part of the material liner 2140 but is recessed with respect to the upper part of the material liner 2140. The recessed insulating filling material 2154 is within the second material liner 2148 and has an upper surface that is coplanar with the upper surface of the second material liner 2148. The third material liner 2156 is within the upper part of the material liner 2140, on the upper surface of the insulating filling material 2154, and on the upper surface of the second material liner 2148. The third material liner 2156 has a seam 2157, such as an artifact of the film-forming process used to form the third material liner 2156.

[0270] Referring to FIG. 22B, the opening 2136 over the PMOS region of the structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. The second material liner 2148 is conformal to the lower part of the material liner 2140 but is recessed with respect to the upper part of the material liner 2140. The recessed insulating filling material 2154 is within the second material liner 2148 and has an upper surface that is coplanar with the upper surface of the second material liner 2148. The third material liner 2156 is within the upper part of the material liner 2140, on the upper surface of the insulating filling material 2154, and on the upper surface of the second material liner 2148. The third material liner 2156 has no seam.

[0271] Referring to FIG. 22C, the opening 2136 over the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but is recessed with respect to the upper portion of the material liner 2140. The recessed insulating fill material 2154 is within and above the second material liner 2148 and has an upper surface that is above the upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140 and on the upper surface of the insulating fill material 2154. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0272] Referring to FIG. 22D, the opening 2136 over the PMOS region of structure 2100 includes a material liner 2140 along the sidewalls of the opening 2136. A second material liner 2148 is conformal to the lower portion of the material liner 2140 but is recessed with respect to the upper portion of the material liner 2140. The recessed insulating fill material 2154 is within the second material liner 2148 and has an upper surface that is recessed below the upper surface of the second material liner 2148. A third material liner 2156 is within the upper portion of the material liner 2140, on the upper surface of the insulating fill material 2154, and on the upper surface of the second material liner 2148. The third material liner 2156 is shown without seams, but in other embodiments, the third material liner 2156 has seams.

[0273] Referring collectively to FIGS. 19A, 19B, 20A, 20B, 21A-21M and 22A-22D, according to one embodiment of the present disclosure, an integrated circuit structure includes fins such as silicon, and the fins have a top and sidewalls. The top has a longest dimension along a direction. A first isolation structure is above a first end of the fin. A gate structure is above the top of the region of the fin and includes a gate electrode laterally adjacent to its sidewall. The gate structure is spaced apart from the first isolation structure along a direction. A second isolation structure is above a second end of the fin, and the second end faces the first end. The second isolation structure is spaced apart from the gate structure along a direction. Both the first isolation structure and the second isolation structure include a first dielectric material (e.g., material liner 2140) that laterally surrounds a recessed second dielectric material (e.g., second material liner 2148) that is separate from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., recessed insulating fill material 2154) that is different from the first and second dielectric materials.

[0274] In one embodiment, both the first isolation structure and the second isolation structure further include a fourth dielectric material (e.g., third material liner 2156) that is laterally surrounded by an upper portion of the first dielectric material, and the fourth dielectric material is on the upper surface of the third dielectric material. In such an embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has a generally vertical central seam. In another such embodiment, the fourth dielectric material has no seam.

[0275] In one embodiment, the third dielectric material has an upper surface that is in the same plane as the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is below the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface that is above the upper surface of the second dielectric material, and the third dielectric material is further above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In such an embodiment, the gate electrode is a P-type gate electrode.

[0276] In one embodiment, the first isolation structure has a width along a direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In such an embodiment, the center of the gate structure is spaced from the center of the first isolation structure by a pitch along the direction, and the center of the second isolation structure is spaced from the center of the gate structure by a pitch along the direction. In one embodiment, both the first and second isolation structures are in corresponding trenches in the interlayer dielectric layer.

[0277] In such an embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In such an embodiment, the first and second source or drain regions are embedded in a source or drain region containing silicon and germanium. In such an embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the fin along the sidewall of the gate electrode.

[0278] In another aspect, the depth of the individual dielectric plugs can vary within the semiconductor structure or within an architecture formed on a common substrate. By way of example, FIG. 23A shows a cross-sectional view of another semiconductor structure having fin edge stress inducing features, according to another embodiment of the present disclosure. Referring to FIG. 23A, a shallow dielectric plug 2308A is included along with a pair of deep dielectric plugs 2308B and 2308C. In such an embodiment, as illustrated, the shallow dielectric plug 2308C is at a depth approximately equal to the depth of the semiconductor fin 2302 in the substrate 2304, while the pair of deep dielectric plugs 2308B and 2308C are at a depth below the depth of the semiconductor fin 2302 in the substrate 2304.

[0279] Referring back to FIG. 23A, such a configuration may enable stress amplification on a fin trim isolation (FTI) device in a trench that etches deeper into the substrate 2304 to provide separation between adjacent fins 2302. Such an approach may be implemented to increase the density of transistors on a chip. In one embodiment, the stress effect induced in the transistor from the plug fill is amplified in the FTI transistor. This is because stress transfer occurs in both the fin and the substrate, or much further below the transistor.

[0280] In another aspect, the width or amount of the tensile stress-inducing oxide layer included in the dielectric plug may vary within the semiconductor structure or within an architecture formed on a common substrate, depending, for example, on whether the device is a PMOS device or an NMOS device. As an example, FIG. 23B shows a cross-sectional view of another semiconductor structure having a fin edge stress-inducing feature according to another embodiment of the present disclosure. Referring to FIG. 23B, in a particular embodiment, the NMOS device includes a relatively greater amount of the tensile stress-inducing oxide layer 2350 than the corresponding PMOS device.

[0281] Referring back to FIG. 23B, in one embodiment, differential plug fills are implemented to induce appropriate stress in the NMOS and PMOS. For example, NMOS plugs 2308D and 2308E have a larger volume and width of the oxide layer 2350 that induces tensile stress than PMOS plugs 2308F and 2308G. The plug fills can be patterned to induce different stresses in the NMOS and PMOS devices. For example, lithographic patterning can be used to expand the PMOS device (e.g., expand the dielectric plug trench for the PMOS device), and in this regard, different fill options can be implemented to differentiate the plug fills in the NMOS and PMOS devices. In an exemplary embodiment, the induced tensile stress can be reduced by reducing the volume of the flowable oxide in the plug on the PMOS device. In such an embodiment, for example, the compressive stress from the compressive stress source and drain region can be dominant. In other embodiments, the use of different plug liners or different fill materials makes the stress control adjustable.

[0282] As described above, it should be understood that the polyplug stress effect can be beneficial for both NMOS transistors (e.g., tensile channel stress) and PMOS transistors (e.g., compressive channel stress). According to one embodiment of the present disclosure, the semiconductor fin is a uniaxial stress semiconductor fin. The uniaxial stress semiconductor fin can be subjected to uniaxial stress with tensile stress or compressive stress. For example, FIG. 24A shows a perspective view of a fin having a tensile uniaxial stress according to one or more embodiments of the present disclosure, while FIG. 24B shows a perspective view of a fin having a compressive uniaxial stress.

[0283] Referring to FIG. 24A, a separate channel region (C) is disposed within the semiconductor fin 2400. The source region (S) and the drain region (D) are disposed within the semiconductor fin 2400 on either side of the channel region (C). The separate channel region of the semiconductor fin 2400 has a direction in which current flows from the source region (S) to the drain region (D) along the direction of uniaxial tensile stress (arrows pointing to the ends 2402 and 2404 in opposite directions).

[0284] Referring to FIG. 24B, a separate channel region (C) is disposed within the semiconductor fin 2450. The source region (S) and the drain region (D) are disposed within the semiconductor fin 2450 on either side of the channel region (C). The separate channel region of the semiconductor fin 2450 has a direction in which current flows from the source region (S) to the drain region (D) along the direction of uniaxial compressive stress (arrows pointing towards each other from the ends 2452 and 2454). Accordingly, the embodiments described herein can be implemented to improve the mobility and drive current of the transistor, enabling the circuit and chip to execute faster.

[0285] In another aspect, there can be a relationship between the location where the gate line cut (poly cut) is made and the location where the fin trim isolation (FTI) local fin cut is made. In one embodiment, the FTI local fin cut is made only at the location where the poly cut is made. However, in such an embodiment, the FTI cut is not necessarily made at all the locations where the poly cut is made.

[0286] FIGS. 25A and 25B show plan views representing various steps in a method of patterning fins at a single gate pitch to form a local isolation structure at a selected gate line cut location, according to an embodiment of the present disclosure.

[0287] Referring to FIG. 25A, a method of manufacturing an integrated circuit structure includes forming a plurality of fins 2502, each of the plurality of fins 2502 having a longest dimension along a first direction 2504. A plurality of gate structures 2506 are above the plurality of fins 2502, each of the gate structures 2506 having a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In one embodiment, the gate structure 2506 is a sacrificial or dummy gate line and is made of, for example, polycrystalline silicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of a lower silicon substrate.

[0288] Referring again to FIG. 25A, a dielectric material structure 2510 is formed between adjacent ones of the plurality of gate structures 2506. Two portions 2512 and 2513 of the plurality of gate structures 2506 are removed, exposing portions of each of the plurality of fins 2502. In one embodiment, removing the two portions 2512 and 2513 of the gate structure 2506 involves using a lithography window wider than the width of each of the portions 2512 and 2513 of the gate structure 2506. The exposed portions of each of the plurality of fins 2502 at position 2512 are removed, forming a cut region 2520. In one embodiment, the exposed portion of each of the plurality of fins 2502 is removed using a dry or plasma etching process. However, the exposed portions of each of the plurality of fins 2502 at position 2513 are masked so as not to be removed. In one embodiment, both regions 2512 / 2520 represent polycut and FTI local fin cut. However, position 2513 represents polycut only.

[0289] Referring to FIG. 25B, the positions 2512 / 2520 of the polycut and FTI local fin cut and the position 2513 of the polycut are filled with an insulating structure 2530 such as a dielectric plug. An exemplary insulating structure, or “polycut” or “plug” structure, will be described later.

[0290] Figures 26A through 26C show cross-sectional views of various possibilities of the positions of polycuts and FTI local fincuts, as well as the positions of only polycuts, for various regions of the structure of FIG. 25B, according to an embodiment of the present disclosure.

[0291] Referring to FIG. 26A, a cross-sectional view of portion 2600A of dielectric plug 2530 at position 2513 is shown along axis a-a' of the structure of FIG. 25B. Portion 2600A of dielectric plug 2530 is shown above uncut fin 2502 and between dielectric material structures 2510.

[0292] Referring to FIG. 26B, a cross-sectional view of portion 2600B of dielectric plug 2530 at position 2512 is shown along axis b-b' of the structure of FIG. 25B. Portion 2600B of dielectric plug 2530 is shown above cut fin position 2520 and between dielectric material structures 2510.

[0293] Referring to FIG. 26C, a cross-sectional view of portion 2600C of dielectric plug 2530 at position 2512 is shown along axis c-c' of the structure of FIG. 25B. Portion 2600C of dielectric plug 2530 is shown above trench isolation structure 2602 between fins 2502 and between dielectric material structures 2510. In one embodiment of the example described above, trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating filling material 2602C on the second insulating layer 2602B.

[0294] Referring collectively to FIGS. 25A, 25B, and 26A - 26C, according to one embodiment of the present disclosure, a method of manufacturing an integrated circuit structure includes forming a plurality of fins, each of the plurality of fins being along a first direction. A plurality of gate structures are formed over the plurality of fins, each of the gate structures being along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first gate structure among the plurality of gate structures is removed, exposing a first portion of each of the plurality of fins. A portion of a second gate structure among the plurality of gate structures is removed, exposing a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, while the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed at the location of the removed first portion of the plurality of fins. A second insulating structure is formed at the location of the removed portion of the second gate structure among the plurality of gate structures.

[0295] In one embodiment, removing a portion of the first gate structure and the second gate structure among the plurality of gate structures involves using a lithography window wider than the width of each of the portions of the first gate structure and the second gate structure among the plurality of gate structures. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth less than the height of the plurality of fins. In such an embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins. In one embodiment, the plurality of fins includes silicon and is continuous with a portion of a silicon substrate.

[0296] Referring collectively to FIGS. 16A, 25A, 25B, and 26A - 26C, according to another embodiment of the present disclosure, an integrated circuit structure includes fins including silicon, and the fins have a longest dimension along a first direction. A isolation structure is above the upper part of the fins, and the isolation structure has a center along the first direction. A first gate structure is above the upper part of the fins, and the first gate structure has a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction. A second gate structure is above the upper part of the fins, and the second gate structure has a longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a pitch along the first direction. A third gate structure is above the upper part of the fins, on the opposite side of the isolation structure as viewed from the first and second gate structures, and the third gate structure has a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction.

[0297] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high - k gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high - k gate dielectric layer.

[0298] In one embodiment, a first epitaxial semiconductor region is on the upper part of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is on the upper part of the fin between the first gate structure and the second gate structure. A third epitaxial semiconductor region is on the upper part of the fin between the third gate structure and the isolation structure. In such an embodiment, the first, second, and third epitaxial semiconductor regions include silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions include silicon.

[0299] Referring collectively to FIGS. 16A, 25A, 25B, and 26A - 26C, according to another embodiment of the present disclosure, an integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, and the STI structure has a longest dimension along a first direction. A separation structure is on the STI structure, and the separation structure has a center along the first direction. A first gate structure is on the STI structure, and the first gate structure has a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced from the center of the separation structure by a pitch along the first direction. A second gate structure is on the STI structure, and the second gate structure has a longest dimension along the second direction. The center of the second gate structure is spaced from the center of the first gate structure by a pitch along the first direction. A third gate structure is on the STI structure on the opposite side of the separation structure as viewed from the first and second gate structures, and the third gate structure has a longest dimension along the second direction. The center of the third gate structure is spaced from the center of the separation structure by a pitch along the first direction.

[0300] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high - k gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on the sidewalls of the high - k gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0301] In another aspect, whether both polycut and FTI local fin cut or polycut only, the insulating structure or dielectric plug used to fill the cut position can extend laterally within or even beyond the dielectric spacer of the corresponding cut gate line.

[0302] In a first example where the trench contact shape is not affected by the poly cut dielectric plug, FIG. 27A shows a plan view and a corresponding cross-sectional view of an integrated circuit structure comprising a gate line cut having a dielectric plug extending into a dielectric spacer of a gate line, according to one embodiment of the present disclosure.

[0303] Referring to FIG. 27A, the integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulator material 2706 is between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, where the second direction 2709 is orthogonal to the first direction 2703. The gate line 2708 has a first side surface 2708A and a second side surface 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 has a discontinuous portion 2710 above the insulator material 2706 between the first end 2708C and the second end 2708D of the gate line 2708. The discontinuous portion 2710 is filled with a dielectric plug 2712.

[0304] A trench contact 2714 is above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 at the first side surface 2708A of the gate line 2708. The trench contact 2714 is continuous above the insulator material 2706 at a position 2715 that is laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is laterally between the trench contact 2714 and the first side surface 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side surface 2708A of the gate line 2708 and along the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) that is laterally adjacent to the dielectric plug 2712 and is thinner than a width (W1) that is laterally adjacent to the first side surface 2708A of the gate line 2708.

[0305] In one embodiment, the second trench contact 2718 is above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 on the second side surface 2708B of the gate line 2708. The second trench contact 2718 is continuous above the insulator material 2706 at a position 2719 that is laterally adjacent to the dielectric plug 2712. In such an embodiment, the second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side surface 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side surface 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width that is laterally adjacent to the dielectric 2712 plug and is thinner than the width that is laterally adjacent to the second side surface 2708B of the gate line 2708.

[0306] In one embodiment, the gate line 2708 includes a high-k gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, the dielectric plug 2712 includes the same material as the dielectric spacer 2714 but is separate from the dielectric spacer 2714. In one embodiment, the dielectric plug 2712 includes a material different from that of the dielectric spacer 2714.

[0307] In a second example where the trench contact shape is affected by a polycut dielectric plug, FIG. 27B shows a plan view and a corresponding cross-sectional view of an integrated circuit structure having a gate line cut with a dielectric plug extending beyond the dielectric spacer of the gate line, according to another embodiment of the present disclosure.

[0308] Referring to FIG. 27B, the integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753. A second silicon fin 2754 has a longest dimension along the first direction 2753. An insulator material 2756 is between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is along a second direction 2759, above the first silicon fin 2752 and above the second silicon fin 2754, and the second direction 2759 is orthogonal to the first direction 2753. The gate line 2758 has a first side surface 2758A and a second side surface 2758B, and has a first end 2758C and a second end 2758D. The gate line 2758 has a discontinuous portion 2760 above the insulator material 2756 between the first end 2758C and the second end 2758D of the gate line 2758. The discontinuous portion 2760 is filled with a dielectric plug 2762.

[0309] A trench contact 2764 is at the first side surface 2758A of the gate line 2758, along the second direction 2759, above the first silicon fin 2752 and above the second silicon fin 2754. The trench contact 2764 is continuous above the insulator material 2756 at a position 2765 that is laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is laterally between the trench contact 2764 and the first side surface 2758A of the gate line 2758. The dielectric spacer 2766 is along the first side surface 2758A of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) that is laterally adjacent to a thinner dielectric plug 2762 than a width (W2) that is laterally adjacent to the dielectric spacer 2766.

[0310] In one embodiment, the second trench contact 2768 is above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759 at a second side surface 2758B of the gate line 2758. The second trench contact 2768 is continuous above the insulator material 2756 at a position 2769 that is laterally adjacent to the dielectric plug 2762. In such an embodiment, the second dielectric spacer 2770 is laterally between the second trench contact 2768 and the second side surface 2758B of the gate line 2758. The second dielectric spacer 2770 is along the second side surface 2508B of the gate line 2758 but not along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. The second trench contact 2768 has a width that is laterally adjacent to the dielectric plug 2762 and is thinner than the width that is laterally adjacent to the second dielectric spacer 2770.

[0311] In one embodiment, the gate line 2758 includes a high-k gate dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, the dielectric plug 2762 includes the same material as the dielectric spacer 2764 but is separate from the dielectric spacer 2764. In one embodiment, the dielectric plug 2762 includes a material different from the dielectric spacer 2764.

[0312] In a third example where the dielectric plug for the polycut position is tapered from the top of the plug to the bottom of the plug, FIGS. 28A - 28F show cross-sectional views of various steps in a method of manufacturing an integrated circuit structure including a gate line cut having a dielectric plug having an upper portion extending beyond a dielectric spacer of a gate line and a lower portion extending into the dielectric spacer of the gate line, according to another embodiment of the present disclosure.

[0313] Referring to FIG. 28A, a plurality of gate lines 2802 are formed above a structure 2804, such as above a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line having, for example, a dummy gate electrode 2806 and a dielectric cap 2808. A portion of such a sacrificial or dummy gate line can be replaced later (e.g., after the formation of dielectric plugs described below) in a replacement gate process. Dielectric spacers 2810 are along the sidewalls of the gate lines 2802. A dielectric material 2812, such as an inter-dielectric layer, is between the gate lines 2802. A mask 2814 is formed and lithography is patterned to expose a portion of one of the gate lines 2802.

[0314] Referring to FIG. 28B with the mask 2814 in place, the central gate line 2802 is removed in an etching process. Next, the mask 2814 is removed. In one embodiment, a portion of the dielectric spacers 2810 of the removed gate line 2802 is etched away by the etching process, forming reduced dielectric spacers 2816. Further, the upper portion of the dielectric material 2812 exposed by the mask 2814 is etched away in the etching process, forming an etched dielectric material portion 2818. In certain embodiments, a residual dummy gate material 2820, such as residual polycrystalline silicon, remains in the structure as an artifact of the incomplete etching process.

[0315] Referring to FIG. 28C, a hard mask 2822 is formed above the structure of FIG. 28B. The hard mask 2822 can be conformal to the upper portion of the structure of FIG. 2B, particularly to the etched dielectric material portion 2818.

[0316] Referring to FIG. 28D, the residual dummy gate material 2820 is removed using an etching process that can be similar in chemistry to, for example, the etching process used to remove the central one of the gate lines 2802. In one embodiment, the hard mask 2822 protects the etched dielectric material portion 2818 from further etching during the removal of the residual dummy gate material 2820.

[0317] Referring to FIG. 28E, the hard mask 2822 has been removed. In one embodiment, the hard mask 2822 is removed without further etching, or substantially without further etching, of the etched dielectric material portion 2818.

[0318] Referring to FIG. 28F, the dielectric plug 2830 is formed in the opening of the structure of FIG. 28E. The upper portion of the dielectric plug 2830 is above the etched dielectric material portion 2818, for example, substantially exceeding the original spacer 2810. The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer 2816, for example, substantially within but not exceeding the original spacer 2810. As a result, the dielectric plug 2830 has a tapered profile as shown in FIG. 28F. It should be understood that the dielectric plug 2830 can be fabricated from the materials and processes described above for other polycut or FTI plugs or fin end stressors.

[0319] In another aspect, a portion of a placeholder gate structure or dummy gate structure can be held above a trench isolation region under a permanent gate structure to protect the trench isolation region from etching during a replacement gate process. For example, FIGS. 29A - 29C show a plan view and corresponding cross-sectional views of an integrated circuit structure including residual dummy gate material in a portion of the bottom of a permanent gate stack, according to one embodiment of the present disclosure.

[0320] Referring to FIGS. 29A - 29C, the integrated circuit structure includes fins 2902, such as silicon fins, protruding from a semiconductor substrate 2904. The fins 2902 include a lower fin portion 2902B and an upper fin portion 2902A. The upper fin portion 2902A has a top 2902C and sidewalls 2902D. A isolation structure 2906 surrounds the lower fin portion 2902B. The isolation structure 2906 includes an insulator material 2906C having a top surface 2907. A semiconductor material 2908 is on a portion of the top surface 2907 of the insulator material 2906C. The semiconductor material 2908 is isolated from the fins 2902.

[0321] The gate dielectric layer 2910 is above the top 2902C of the upper fin portion 2902A and is laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate dielectric layer 2910 is further on the semiconductor material 2908 above a part of the top surface 2907 of the insulator material 2906C. An additional gate dielectric layer 2911, such as an oxidized portion of the fin 2902, may be between the gate dielectric layers 2910 above the top 2902C of the upper fin portion 2902A and may be laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is above the gate dielectric layer 2910 above the top 2902C of the upper fin portion 2902A and is laterally adjacent to the sidewall 2902D of the upper fin portion 2902A. The gate electrode 2912 is further above the gate dielectric layer 2910 on the semiconductor material 2908 above a part of the top surface 2907 of the insulator material 2906C. The first source or drain region 2916 is adjacent to the first side surface of the gate electrode 2912, and the second source or drain region 2918 is adjacent to the second side surface of the gate electrode 2912, and the second side surface faces the first side surface. In one embodiment described above by way of example, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulator material 2906C.

[0322] In one embodiment, the semiconductor material 2908 above a portion of the top surface 2907 of the insulator material 2906C is polycrystalline silicon or includes it. In one embodiment, as shown, the top surface 2907 of the insulator material 2906C has a concave depression and the semiconductor material 2908 is in the concave depression. In one embodiment, the isolation structure 2906 includes a second insulator material (2906A, or 2906B, or both 2906A / 2906B) along the bottom and sidewalls of the insulator material 2906C. In such an embodiment, a part of the second insulator material (2906A, or 2906B, or both 2906A / 2906B) along the sidewall of the insulator material 2906C has a top surface above the uppermost surface of the insulator material 2906C as shown. In one embodiment, the top surface of the second insulator material (2906A, or 2906B, or both 2906A / 2906B) is above or in the same plane as the uppermost surface of the semiconductor material 2908.

[0323] In one embodiment, the semiconductor material 2908 on a part of the top surface 2907 of the insulator material 2906C does not extend beyond the gate dielectric layer 2910. That is, from the perspective of a plan view, the position of the semiconductor material 2908 is limited to the region covered by the gate stack 2912 / 2910. In one embodiment, the first dielectric spacer 2920 is along the first side surface of the gate electrode 2912. The second dielectric spacer 2922 is along the second side surface of the gate electrode 2912. In such an embodiment, the gate dielectric layer 2910 further extends along the sidewall of the first dielectric spacer 2920 and the second dielectric spacer 2922, as illustrated in FIG. 29B.

[0324] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., a work function layer). In such an embodiment, the work function layer 2912A includes titanium and nitrogen. In another embodiment, the work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive fill metal layer 2912B above the work function layer 2912A. In such an embodiment, the conductive fill metal layer 2912B includes tungsten. In a particular embodiment, the conductive fill metal layer 2912B includes tungsten with an atomic percentage of 95% or higher and fluorine with an atomic percentage of 0.1 - 2%. In one embodiment, the insulating cap 2924 is on the gate electrode 2912 and can extend above the gate dielectric layer 2910, as illustrated in FIG. 29B.

[0325] FIGS. 30A - 30D show cross-sectional views of various steps in a method of manufacturing an integrated circuit structure having a residual dummy gate material at a part of the bottom of a permanent gate stack according to another embodiment of the present disclosure. This perspective is along a part of the axis a - a' of the structure of FIG. 29C.

[0326] Referring to FIG. 30A, a method of manufacturing an integrated circuit structure includes forming fins 3000 from a semiconductor substrate 3002. The fins 3000 have a lower fin portion 3000A and an upper fin portion 3000B. The upper fin portion 3000B has a top 3000C and sidewalls 3000D. A isolation structure 3004 surrounds the lower fin portion 3000A. The isolation structure 3004 includes an insulator material 3004C having a top surface 3005. A placeholder gate electrode 3006 is above the top 3000C of the upper fin portion 3000B and is laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B. The placeholder gate electrode 3006 includes a semiconductor material.

[0327] Although not shown from the perspective of FIG. 30A (however, its position is shown in FIG. 29C), a first source or drain region may be formed adjacent to a first side surface of the placeholder gate electrode 3006, and a second source or drain region may be formed adjacent to a second side surface of the placeholder gate electrode 3006, where the second side surface faces the first side surface. Further, a gate dielectric spacer may be formed along the sidewalls of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode 3006.

[0328] In one embodiment, the placeholder gate electrode 3006 is or includes polycrystalline silicon. In one embodiment, the top surface 3005 of the insulator material 3004C of the isolation structure 3004 has a concave depression as shown. A portion of the placeholder gate electrode 3006 is within the concave depression. In one embodiment, as shown, the isolation structure 3004 includes a second insulator material (3004A, or 3004B, or both 3004A and 3004B) along the bottom and sidewalls of the insulator material 3004C. In such an embodiment, a portion of the second insulator material (3004A, or 3004B, or both 3004A and 3004B) along the sidewalls of the insulator material 3004C has a top surface above at least a portion of the top surface 3005 of the insulator material 3004C. In one embodiment, the top surface of the second insulator material (3004A, or 3004B, or both 3004A and 3004B) is above the lowermost surface of a portion of the placeholder gate electrode 3006.

[0329] Referring to FIG. 30B, the placeholder gate electrode 3006 is etched from above the top 3000C and sidewall 3000D of the upper fin portion 3000B, for example, along direction 3008 of FIG. 30A. The etching process may be referred to as a replacement gate process. In one embodiment, the etching or replacement gate process is incomplete, leaving a portion 3012 of the placeholder gate electrode 3006 on at least a portion of the top surface 3005 of the insulator material 3004C of the isolation structure 3004.

[0330] Referring to both FIGS. 30A and 30B, in one embodiment, the oxidized portion 3010 of the upper fin portion 3000B formed prior to the formation of the placeholder gate electrode 3006 is retained as shown during the etching process. However, in another embodiment, a placeholder gate dielectric layer is formed prior to the formation of the placeholder gate electrode 3006, and the placeholder gate dielectric layer is removed after the etching of the placeholder gate electrode.

[0331] Referring to FIG. 30C, the gate dielectric layer 3014 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In one embodiment, as shown, the gate dielectric layer 3014 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, on the oxidized portion 3010 of the upper fin portion 3000B. In another embodiment, if the oxidized portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, the gate dielectric layer 3014 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, immediately above the upper fin portion 3000B. In any case, in one embodiment, the gate dielectric layer 3014 is further formed above a part of the partial 3012 of the placeholder gate electrode 3006, on a part of the top surface 3005 of the insulator material 3004C of the isolation structure 3004.

[0332] Referring to FIG. 30D, the permanent gate electrode 3016 is formed above the top 3000C of the upper fin portion 3000B and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B, above the gate dielectric layer 3014. The permanent gate electrode 3016 is further above the gate dielectric layer 3014, above a part of the partial 3012 of the placeholder gate electrode 3006, on a part of the top surface 3005 of the insulator material 3004C.

[0333] In one embodiment, the formation of the permanent gate electrode 3016 includes the formation of a work function layer 3016A. In such an embodiment, the work function layer 3016A includes titanium and nitrogen. In another such embodiment, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed over the work function layer 3016A. In such an embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, an insulating gate cap layer 3018 is formed over the permanent gate electrode 3016.

[0334] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer in a gate dielectric structure for a gate electrode. In other embodiments, a partially or fully crystalline high-k layer is included in the gate dielectric structure for the gate electrode. In one embodiment that includes a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment that includes a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0335] In one embodiment, an approach for increasing charge in a device channel and improving sub-threshold behavior by employing a ferroelectric or antiferroelectric gate oxide is described herein. The ferroelectric and antiferroelectric gate oxides can increase the channel charge for higher current and can also perform a steeper turn-on operation.

[0336] When provided with a context, hafnium or zirconium (Hf or Zr)-based ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT), and thus can be compatible with highly scaled logic technologies. There are two characteristics of FE or AFE materials that can improve the performance of logic transistors. That is, (1) higher charge in the channel realized by the FE or AFE polarization, and (2) a steeper turn-on operation resulting from a sharp FE or AFE transition. Such characteristics can improve transistor performance by increasing the current and reducing the subthreshold swing (SS).

[0337] FIG. 31A shows a cross-sectional view of a semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure.

[0338] Referring to FIG. 31A, the integrated circuit structure 3100 includes a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is above or over a semiconductor channel structure 3106 that includes a single crystal material such as single crystal silicon. The gate structure 3102 includes a semiconductor channel structure 3106 above a gate dielectric structure and a gate dielectric above a gate electrode. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B includes a metal and can be a barrier layer, work function layer, or template layer that enhances crystallization of the FE or AFE layer. One or more gate fill layers 3102C are on or above the conductive layer 3102B. Source region 3108 and drain region 3110 are on opposite sides of the gate structure 3102. Source or drain contact 3112 is electrically connected to source region 3108 and drain region 3110 at location 3149 and is spaced from the gate structure 3102 by one or both of an interlayer dielectric layer 3114 or a gate dielectric spacer 3116. In the example of FIG. 31A, source region 3108 and drain region 3110 are regions of the substrate 3104. In one embodiment, source or drain contact 3112 includes a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacer 3116 as shown in FIG. 31A.

[0339] In one embodiment, and as applied throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf, and the ratio of Zr to Hf is 50:50 or more Zr. As the orthorhombic crystallinity increases, the ferroelectric effect can increase. In one embodiment, the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

[0340] In one embodiment, and as applied throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide containing Zr and Hf. The ratio of Zr to Hf is 80:20, i.e., there is more Zr, and it can even be 100% Zr, such as ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

[0341] In one embodiment, and as applied throughout the present disclosure, the gate dielectric of the gate stack 3102 further includes an amorphous dielectric layer 3103 such as a native silicon oxide layer, a high-k dielectric (such as HfOx, Al2O3, etc.), or a combination of an oxide and a high-k between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In one embodiment, and as applied throughout the present disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In one embodiment, and as applied throughout the present disclosure, the crystal grain size of the ferroelectric or antiferroelectric polycrystalline material layer 3102A is generally in the range of 20 nanometers or larger.

[0342] In one embodiment, for example, following the deposition of the ferroelectric or antiferroelectric polycrystalline material layer 3102A by atomic layer deposition (ALD), a layer including a metal (such as a layer 3102B of titanium nitride of 5 to 10 nanometers, or tantalum nitride, or tungsten, etc.) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Next, annealing is performed. In one embodiment, the annealing is performed for a duration in the range of 1 millisecond to 30 minutes. In one embodiment, the annealing is performed at a temperature in the range of 500 to 1100 °C.

[0343] FIG. 31B shows a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure.

[0344] Referring to FIG. 31B, the integrated circuit structure 3150 includes a gate structure 3152 over a substrate 3154. In one embodiment, the gate structure 3152 is over or above a semiconductor channel structure 3156 that includes a single crystal material such as single crystal silicon. The gate structure 3152 includes a gate dielectric over the semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B over the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or a work function layer. One or more gate fill layers 3152C are over or above the conductive layer 3152B. Raised source regions 3158 and raised drain regions 3160, such as regions of semiconductor material different from the semiconductor channel structure 3156, are on opposite sides sandwiching the gate structure 3152. Source or drain contacts 3162 are electrically connected to the source region 3158 and the drain region 3160 at location 3199 and are spaced from the gate structure 3152 by one or both of an interlayer dielectric layer 3164 or a gate dielectric spacer 3166. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, as illustrated in FIG. 31B, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacer 3166.

[0345] FIG. 32A shows a plan view of a plurality of gate lines over a pair of semiconductor fins, according to another embodiment of the present disclosure.

[0346] Referring to FIG. 32A, a plurality of active gate lines 3204 are formed above a plurality of semiconductor fins 3200. Dummy gate lines 3206 are at the ends of the plurality of semiconductor fins 3200. The spacing 3208 between the gate lines 3204 / 3206 is a position where trench contacts can be disposed to provide conductive contact to source or drain regions such as source or drain regions 3251, 3252, 3253, and 3254. In one embodiment, the patterning of the plurality of gate lines 3204 / 3206, or the patterning of the plurality of semiconductor fins 3200, is described as a lattice structure. In one embodiment, the lattice pattern includes the plurality of gate lines 3204 / 3206, or the pattern of the plurality of semiconductor fins 3200 spaced apart at a constant pitch and having a constant width, or both.

[0347] FIG. 32B shows a cross-sectional view taken along axis a-a' of FIG. 32A according to one embodiment of the present disclosure.

[0348] Referring to FIG. 32B, a plurality of active gate lines 3264 are formed above semiconductor fins 3262 formed above a substrate 3260. Dummy gate lines 3266 are at the ends of the semiconductor fins 3262. A dielectric layer 3270 is outside the dummy gate lines 3266. Trench contact material 3297 is between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. Embedded source or drain structures 3268 are in the semiconductor fins 3262 between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0349] The active gate lines 3264 include a gate dielectric structure 3272, a work function gate electrode portion 3274, a fill gate electrode portion 3276, and a dielectric capping layer 3278. Dielectric spacers 3280 are along the sidewalls of the active gate lines 3264 and the dummy gate lines 3266. In one embodiment, the gate dielectric structure 3272 includes a ferroelectric or antiferroelectric polycrystalline material layer 3298. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299.

[0350] In another aspect, for example, devices of the same conductivity type, such as N-type or P-type, may have differentiated gate electrode stacks for the same conductivity type. However, for comparison purposes, devices having the same conductivity type may have differentiated voltage thresholds (VTs) based on adjusted doping.

[0351] FIG. 33A shows a cross-sectional view having a pair of NMOS devices having differentiated voltage thresholds based on adjusted doping and a pair of PMOS devices having differentiated voltage thresholds based on adjusted doping, according to one embodiment of the present disclosure.

[0352] Referring to FIG. 33A, a first NMOS device 3302 is adjacent to a second NMOS device 3304 above a semiconductor active region 3300, such as above a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first gate electrode conductive layer 3308, such as a work function layer, and a gate electrode conductive fill 3310. In one embodiment, the first gate electrode conductive layers 3308 of the first NMOS device 3302 and the second NMOS device 3304 are of the same material and the same thickness and thus have the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304. In such an embodiment, the first NMOS device 3302 is referred to as a "standard VT" device and the second NMOS device 3304 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using adjusted or differentiated implant doping in regions 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0353] Referring back to FIG. 33A, the first PMOS device 3322 is adjacent to the second PMOS device 3324 above the semiconductor active region 3320, such as above the silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326, a first gate electrode conductive layer 3328 such as a work function layer, and a gate electrode conductive filler 3330. In one embodiment, the first gate electrode conductive layers 3328 of the first PMOS device 3322 and the second PMOS device 3324 are of the same material and the same thickness, and thus have the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324. In such an embodiment, the first PMOS device 3322 is referred to as a "standard VT" device and the second PMOS device 3324 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using adjusted or differentiated implanted doping in regions 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0354] In contrast to FIG. 33A, FIG. 33B shows a cross-sectional view of a pair of NMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure, and a pair of PMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0355] Referring to FIG. 33B, the first NMOS device 3352 is adjacent to the second NMOS device 3354 above the semiconductor active region 3350, such as above a silicon fin or a substrate. Both the first NMOS device 3352 and the second NMOS device 3354 include a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. In particular, the first NMOS device 3352 includes a first gate electrode conductive layer 3358, such as a first work function layer, and a gate electrode conductive filler 3360. The second NMOS device 3354 includes a second gate electrode conductive layer 3359, such as a second work function layer, the first gate electrode conductive layer 3358, and a gate electrode conductive filler 3360. The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In such an embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved for devices of the same conductivity type by using differentiated gate stacks.

[0356] Referring back to FIG. 33B, the first PMOS device 3372 is adjacent to the second PMOS device 3374 above the semiconductor active region 3370, such as above a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. In particular, the first PMOS device 3372 includes a gate electrode conductive layer 3378A having a first thickness, such as a work function layer, and a gate electrode conductive fill 3380. The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness and a gate electrode conductive fill 3380. In one embodiment, the gate electrode conductive layer 3378A and the gate electrode conductive layer 3378B have the same composition, but the thickness of the gate electrode conductive layer 3378B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3378A (the first thickness). The first PMOS device 3372 has a higher VT than the second PMOS device 3374. In such an embodiment, the first PMOS device 3372 is referred to as a "standard VT" device and the second PMOS device 3374 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using a differentiated gate stack for devices of the same conductivity type.

[0357] Referring again to FIG. 33B, according to one embodiment of the present disclosure, an integrated circuit structure includes fins (e.g., silicon fins such as 3350). It should be understood that the fins have a top (shown) and sidewalls (back and front of the page). The gate dielectric layer 3356 is above the top of the fin and laterally adjacent to the sidewalls of the fin. The N-type gate electrode of the device 3354 is above the top of the fin, laterally adjacent to the sidewalls of the fin, and above the gate dielectric layer 3356. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 and an N-type metal layer 3358 on the P-type metal layer 3359. As can be understood, a first N-type source or drain region may be adjacent to a first side surface (e.g., the back of the page) of the gate electrode, and a second N-type source or drain region may be adjacent to a second side surface (e.g., the front of the page) of the gate electrode, and the second side surface faces the first side surface.

[0358] In one embodiment, the P-type metal layer 3359 includes titanium and nitrogen, and the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2 to 12 angstroms, and in a particular embodiment, the P-type metal layer 3359 has a thickness in the range of 2 to 4 angstroms. In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358. In such an embodiment, the conductive fill metal layer 3360 includes tungsten. In a particular embodiment, the conductive fill metal layer 3360 includes tungsten with an atomic percentage of 95% or higher and fluorine with an atomic percentage of 0.1 to 2%.

[0359] Referring back to FIG. 33B, according to another embodiment of the present disclosure, an integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), a first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal layer 3358 on the first gate dielectric layer 3356. Also included are a second N-type device 3354 having a voltage threshold (VT), a second N-type device 3354 having a second gate dielectric layer 3356, a P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the P-type metal layer 3359.

[0360] In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

[0361] Referring back to FIG. 33B, according to another embodiment of the present disclosure, an integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), a first P-type device 3372 having a first gate dielectric layer 3376, and a first P-type metal layer 3378A on the first gate dielectric layer 3376. The first P-type metal layer 3378A has a thickness. Also included is a second P-type device 3374 having a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376. The second P-type metal layer 3378B has a thickness greater than the thickness of the first P-type metal layer 3378A.

[0362] In one embodiment, the VT of the second P-type of device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B contain titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is smaller than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not shown, the second P-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and the seam is between the first metal film and the second metal film.

[0363] Referring again to FIG. 33B, according to another embodiment of the present disclosure, the integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356 and a first N-type metal layer 3358 on the first gate dielectric layer 3356. The second N-type device 3354 has a second gate dielectric layer 3356, a first P-type metal layer 3359 on the second gate dielectric layer 3356, and a second N-type metal layer 3358 on the first P-type metal layer 3359. The first P-type device 3372 has a third gate dielectric layer 3376 and a second P-type metal layer 3378A on the third gate dielectric layer 3376. The second P-type metal layer 3378A has a thickness. The second P-type device 3374 has a fourth gate dielectric layer 3376 and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376. The third P-type metal layer 3378B has a thickness greater than the thickness of the second P-type metal layer 3378A.

[0364] In one embodiment, the first N-type device 3352 has a voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352. In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on the second metal film and a seam between the first metal film and the second metal film.

[0365] It should be understood that more than two VT devices of the same conductivity type can be included in the same structure, such as on the same die. In a first example, FIG. 34A shows a cross-sectional view of a triplet of NMOS devices having different voltage thresholds based on a differentiated gate electrode structure and adjusted doping, and a triplet of PMOS devices having different voltage thresholds based on a differentiated gate electrode structure and adjusted doping, according to one embodiment of the present disclosure.

[0366] Referring to FIG. 34A, the first NMOS device 3402 is adjacent to the second NMOS device 3404 and the third NMOS device 3403 above the semiconductor active region 3400, such as above a silicon fin or a substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 include a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a gate electrode stack that is structurally different from the first NMOS device 3402 and the third NMOS device 3403. In particular, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408, such as a first work function layer, and a gate electrode conductive filler 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409, such as a second work function layer, the first gate electrode conductive layer 3408, and a gate electrode conductive filler 3410. The first NMOS device 3402 has a lower VT than the second NMOS device 3404. In such an embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conduction type. In one embodiment, the gate electrode structure of the third NMOS device 3403 is the same as that of the first NMOS device 3402, but the third NMOS device 3403 has a VT different from the VT of the first NMOS device 3402 and the second NMOS device 3404. In one embodiment, the VT of the third NMOS device 3403 is between the VT of the first NMOS device 3402 and the second NMOS device 3404. In one embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using adjusted or differentiated implanted doping in the region 3412 of the third NMOS device 3403.In such an embodiment, the 3N-type device 3403 has a channel region having a dopant concentration different from that of the channel region of the 1N-type device 3402.

[0367] Referring back to FIG. 34A, the first PMOS device 3422 is adjacent to the second PMOS device 3424 and the third PMOS device 3423 above the semiconductor active region 3420, such as above the silicon fin or substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 include a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have gate electrode stacks that are structurally identical or similar. However, the second PMOS device 3424 has a gate electrode stack that is structurally different from the first PMOS device 3422 and the third PMOS device 3423. In particular, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conduction layer 3428A, such as a work function layer, having a first thickness, and a gate electrode conductive fill 3430. The second PMOS device 3424 includes a gate electrode conduction layer 3428B having a second thickness and a gate electrode conductive fill 3430. In one embodiment, the gate electrode conduction layer 3428A and the gate electrode conduction layer 3428B have the same composition, but the thickness of the gate electrode conduction layer 3428B (the second thickness) is greater than the thickness of the gate electrode conduction layer 3428A (the first thickness). In one embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In such an embodiment, the first PMOS device 3422 is referred to as a "standard VT" device and the second PMOS device 3424 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422, but the third PMOS device 3423 has a VT that is different from the VT of the first PMOS device 3422 and the second PMOS device 3424. In one embodiment, the VT of the third PMOS device 3423 is between the VT of the first PMOS device 3422 and the second PMOS device 3424.In one embodiment, the differentiated VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using adjusted or differentiated implanted doping in the region 3432 of the third PMOS device 3423. In such an embodiment, the third P-type device 3423 has a channel region having a dopant concentration different from that of the channel region of the first P-type device 3422.

[0368] In a second example, FIG. 34B shows a cross-sectional view of a triplet of NMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure and adjusted doping, and a triplet of PMOS devices having differentiated voltage thresholds based on a differentiated gate electrode structure and adjusted doping, according to another embodiment of the present disclosure.

[0369] Referring to FIG. 34B, the first NMOS device 3452 is adjacent to the second NMOS device 3454 and the third NMOS device 3453 above the semiconductor active region 3450, such as above a silicon fin or a substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 include a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a gate electrode stack that is structurally different from that of the second NMOS device 3454 and the third NMOS device 3453. In particular, the first NMOS device 3452 includes a first gate electrode conductive layer 3458, such as a first work function layer, and a gate electrode conductive filler 3460. The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459, such as a second work function layer, the first gate electrode conductive layer 3458, and a gate electrode conductive filler 3460. The first NMOS device 3452 has a lower VT than the second NMOS device 3454. In such an embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third NMOS device 3453 is the same as that of the second NMOS device 3454, but the third NMOS device 3453 has a VT different from the VTs of the first NMOS device 3452 and the second NMOS device 3454. In one embodiment, the VT of the third NMOS device 3453 is between the VTs of the first NMOS device 3452 and the second NMOS device 3454. In one embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using adjusted or differentiated implanted doping in the region 3462 of the third NMOS device 3453.In such an embodiment, the type-3N device 3453 has a channel region having a dopant concentration different from that of the channel region of the type-2N device 3454.

[0370] Referring again to FIG. 34B, the first PMOS device 3472 is adjacent to the second PMOS device 3474 and the third PMOS device 3473 above the semiconductor active region 3470, such as above the silicon fin or substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 include a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a gate electrode stack that is structurally different from the second PMOS device 3474 and the third PMOS device 3473. In particular, the first PMOS device 3472 includes a gate electrode conductive layer 3478A, such as a work function layer, having a first thickness, and a gate electrode conductive filler 3480. The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness and a gate electrode conductive filler 3480. In one embodiment, the gate electrode conductive layer 3478A and the gate electrode conductive layer 3478B have the same composition, but the thickness of the gate electrode conductive layer 3478B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3478A (the first thickness). In one embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In such an embodiment, the first PMOS device 3472 is referred to as a "standard VT" device, and the second PMOS device 3474 is referred to as a "low VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474, but the third PMOS device 3473 has a VT that is different from the VT of the first PMOS device 3472 and the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 is between the VT of the first PMOS device 3472 and the second PMOS device 3474.In one embodiment, the differentiated VT between the third PMOS device 3473 and the first PMOS device 3472 is realized by using adjusted or differentiated implanted doping in the region 3482 of the third PMOS device 3473. In such an embodiment, the third P-type device 3473 has a channel region with a dopant concentration different from that of the channel region of the second P-type device 3474.

[0371] FIGS. 35A - 35D show cross-sectional views of various steps in a method of manufacturing an NMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure, according to another embodiment of the present disclosure.

[0372] Referring to FIG. 35A, which shows a "standard VT NMOS" region (STD VT NMOS) and a "high VT NMOS" region (HIGH VT NMOS) branching on a common substrate, a method of manufacturing an integrated circuit structure includes forming a gate dielectric layer 3506 above a first semiconductor fin 3502, such as above the first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502 and above the second semiconductor fin 3504.

[0373] Referring to FIG. 35B, a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, while a portion 3509 of the P-type metal layer 3508 is retained on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0374] Referring to FIG. 35C, the N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502 and on a part 3509 of the P-type metal layer on the gate dielectric layer 3506 above the second semiconductor fin 3504. In one embodiment, subsequent processing includes forming a first N-type device having a voltage threshold (VT) above the first semiconductor fin 3502 and forming a second N-type device having a voltage threshold (VT) above the second semiconductor fin 3504, where the VT of the second N-type device is higher than that of the first N-type device.

[0375] Referring to FIG. 35D, in one embodiment, a conductive fill metal layer 3512 is formed on the N-type metal layer 3510. In such an embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0376] FIGS. 36A - 36D show cross-sectional views of various steps in a method of manufacturing a PMOS device having a differentiated voltage threshold based on a differentiated gate electrode structure according to another embodiment of the present disclosure.

[0377] Referring to FIG. 36A, where a "standard VT PMOS" region (STD VT PMOS) and a "low VT PMOS" region (LOW VT PMOS) are shown as branching on a common substrate, a method of manufacturing an integrated circuit structure includes forming a gate dielectric layer 3606 above the first semiconductor fin 3602, such as above the first and second silicon fins, and above the second semiconductor fin 3604. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602 and above the second semiconductor fin 3604.

[0378] Referring to FIG. 36B, a part of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, while a part 3609 of the first P-type metal layer 3608 is retained on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0379] Referring to FIG. 36C, the second P-type metal layer 3610 is formed on the gate dielectric layer 3606 above the first semiconductor fin 3602 and on a part 3609 of the first P-type metal layer on the gate dielectric layer 3606 above the second semiconductor fin 3604. In one embodiment, subsequent processing includes forming a first P-type device having a voltage threshold (VT) above the first semiconductor fin 3602 and forming a second P-type device having a voltage threshold (VT) above the second semiconductor fin 3604, and the VT of the second P-type device is lower than the VT of the first P-type device.

[0380] In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, as shown, a seam 3611 is between the first P-type metal layer 3608 and the second P-type metal layer 3610.

[0381] Referring to FIG. 36D, in one embodiment, a conductive fill metal layer 3612 is formed above the P-type metal layer 3610. In such an embodiment, forming the conductive fill metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, as shown, an N-type metal layer 3614 is formed on the P-type metal layer 3610 before forming the conductive fill metal layer 3612. In such an embodiment, the N-type metal layer 3614 is an artifact of a dual metal gate replacement process scheme.

[0382] In another aspect, a metal gate structure of a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In one example, FIG. 37 shows a cross-sectional view of an integrated circuit structure having a P / N junction according to an embodiment of the present disclosure.

[0383] Referring to FIG. 37, an integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 with a first semiconductor fin 3706 protruding therefrom and a P-well region 3708 with a second semiconductor fin 3710 protruding therefrom. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The N-well region 3704 is directly adjacent to the P-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is between the first semiconductor fin 3706 and the second semiconductor fin 3210 and on the semiconductor substrate 3702 outside thereof. The first semiconductor fin 3706 and the second semiconductor fin 3210 extend above the trench isolation structure 3712.

[0384] A gate dielectric layer 3714 is on the first semiconductor fin 3706 and the second semiconductor fin 3710 and on the trench isolation structure 3712. The gate dielectric layer 3714 is continuous between the first semiconductor fin 3706 and the second semiconductor fin 3710. A conductive layer 3716 is above the gate dielectric layer 3714 above the first semiconductor fin 3706 but not above the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is above the conductive layer 3716 above the first semiconductor fin 3706 but not above the second semiconductor fin 3710. The P-type metal gate layer 3718 is further on a part of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, but not on all of it. An n-type metal gate layer 3720 is above the second semiconductor fin 3710, above the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the P-type metal gate layer 3718.

[0385] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above a trench isolation structure 3712 and outside of first semiconductor fin 3706 and second semiconductor fin 3710. The ILD layer 3722 has an opening 3724 that exposes the first semiconductor fin 3706 and the second semiconductor fin 3710. In such an embodiment, a conductive layer 3716, a p-type metal gate layer 3718, and an n-type metal gate layer 3720 are further formed along sidewalls 3726 of the opening 3724 as shown. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along sidewalls 3726 of the opening 3724 below a top surface 3719 of the p-type metal gate layer 3718 and a top surface 3721 of the n-type metal gate layer 3720 along sidewalls 3726 of the opening 3724 as shown.

[0386] In one embodiment, the p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, the n-type metal gate layer 3720 includes titanium and aluminum. In one embodiment, a conductive fill metal layer 3730 is above the n-type metal gate layer 3720 as shown. In such an embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular embodiment, the conductive fill metal layer 3730 includes tungsten with an atomic percentage of 95% or higher and fluorine with an atomic percentage of 0.1 - 2%. In one embodiment, the gate dielectric layer 3714 has a layer including hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is between an upper portion of the first semiconductor fin 3706 and an upper portion of the second semiconductor fin 3710 as shown. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0387] Referring only to the right side of FIG. 37, according to one embodiment of the present disclosure, an integrated circuit structure includes a semiconductor substrate 3702 including an N-well region 3704 having semiconductor fins 3706 protruding therefrom. A trench isolation structure 3712 is on the semiconductor substrate 3702 around the semiconductor fins 3706. The semiconductor fins 3706 extend above the trench isolation structure 3712. A gate dielectric layer 3714 is above the semiconductor fins 3706. A conductive layer 3716 is above the gate dielectric layer 3714 above the semiconductor fins 3706. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A P-type metal gate layer 3718 is above the conductive layer 3716 above the semiconductor fins 3706.

[0388] In one embodiment, an interlayer dielectric (ILD) layer 3722 is above the trench isolation structure 3712. The ILD layer has an opening that exposes the semiconductor fins 3706. Further, the conductive layer 3716 and the P-type metal gate layer 3718 are formed along the sidewalls of the opening. In such an embodiment, the conductive layer 3716 has a top surface along the sidewalls of the opening below the top surface of the P-type metal gate layer 3718 along the sidewalls of the opening. In one embodiment, the P-type metal gate layer 3718 is on the conductive layer 3716. In one embodiment, the P-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is above the P-type metal gate layer 3718. In such an embodiment, the conductive fill metal layer 3730 includes tungsten. In a particular such embodiment, the conductive fill metal layer 3730 is composed of tungsten with an atomic percentage of 95% or higher and fluorine with an atomic percentage of 0.1 - 2%. In one embodiment, the gate dielectric layer 3714 includes a layer having hafnium and oxygen.

[0389] FIGS. 38A through 38H show cross-sectional views of various steps in a method of manufacturing an integrated circuit structure using a dual metal gate replacement gate process flow according to one embodiment of the present disclosure.

[0390] Referring to FIG. 38A showing an NMOS (n-type) region and a PMOS (p-type) region, a method of manufacturing an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 3802 over a substrate 3800 and over a first semiconductor fin 3804 and a second semiconductor fin 3806. An opening 3808 is formed in the ILD layer 3802, and the opening 3808 exposes the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the opening 3808 is formed by removing a gate placeholder or dummy gate structure that was initially placed over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0391] A gate dielectric layer 3810 is formed in the opening 3808, over the first semiconductor fin 3804 and the second semiconductor fin 3806, and over a portion of a trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, as illustrated, the gate dielectric layer 3810 is formed over a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, formed over the first semiconductor fin 3804 and the second semiconductor fin 3806. In another embodiment, the gate dielectric layer 3810 is formed directly over the first semiconductor fin 3804 and the second semiconductor fin 3806.

[0392] A conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first semiconductor fin 3804 and the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 contains titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed over the first semiconductor fin 3804 and over the conductive layer 3814 formed over the second semiconductor fin 3806.

[0393] Referring to FIG. 38B, a dielectric etch stop layer 3818 is formed on a p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 includes a first layer of silicon oxide (e.g., SiO2), a layer of aluminum oxide (e.g., Al2O3) on the first layer of silicon oxide, and a second layer of silicon oxide (e.g., SiO2) on the layer of aluminum oxide.

[0394] Referring to FIG. 38C, a mask 3820 is formed over the structure of FIG. 38B. The mask 3820 covers the PMOS region and exposes the NMOS region.

[0395] Referring to FIG. 38D, the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819 and a patterned p-type metal gate layer 3817 above a patterned conductive layer 3815 above the first semiconductor fin 3804, but not above the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during patterning.

[0396] Referring to FIG. 38E, the mask 3820 is removed from the structure of FIG. 38D. Referring to FIG. 38F, the patterned dielectric etch stop layer 3819 is removed from the structure of FIG. 38E.

[0397] Referring to FIG. 38G, an n-type metal gate layer 3822 is formed above the second semiconductor fin 3806, above a part of the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and above the patterned p-type metal gate layer 3817. In one embodiment, the patterned conductive layer 3815, the patterned p-type metal gate layer 3817, and the n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808. In such an embodiment, the patterned conductive layer 3815 has a top surface along the sidewall 3824 of the opening 3808, below the top surface of the patterned p-type metal gate layer 3817 and below the top surface of the n-type metal gate layer 3822 along the sidewall 3824 of the opening 3808.

[0398] Referring to FIG. 38H, a conductive fill metal layer 3826 is formed above the n-type metal gate layer 3822. In one embodiment, the conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0399] In another aspect, a dual silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As an exemplary process flow, FIGS. 39A - 39H show cross-sectional views representing various steps in a method of manufacturing a dual silicide-based integrated circuit according to an embodiment of the present disclosure.

[0400] Referring to FIG. 39A, which shows an NMOS region and a PMOS region branching on a common substrate, a method of manufacturing an integrated circuit structure comprises forming a first gate structure 3902 that may include a dielectric sidewall spacer 3903 above a first fin 3904 such as a first silicon fin. A second gate structure 3952 that may include a dielectric sidewall spacer 3953 is formed above a second fin 3954 such as a second silicon fin. An insulator material 3906 is formed adjacent to the first gate structure 3902 above the first fin 3904 and adjacent to the second gate structure 3952 above the second fin 3954. In one embodiment, the insulator material 3906 is a sacrificial material and is used as a mask in a dual silicide process.

[0401] Referring to FIG. 39B, a first portion of the insulator material 3906 is not removed from above the second fin 3954, but is removed from above the first fin 3904, exposing a first source or drain region 3908 and a second source or drain region 3910 of the first fin 3904 adjacent to the first gate structure 3902. In one embodiment, the first source or drain region 3908 and the second source or drain region 3910 are epitaxial regions formed in the recesses of the first fin 3904 as shown. In such an embodiment, the first source or drain region 3908 and the second source or drain region 3910 include silicon and germanium.

[0402] Referring to FIG. 39C, a first metal silicide layer 3912 is formed on the first source or drain region 3908 and the second source or drain region 3910 of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by depositing a layer containing nickel and platinum on the structure of FIG. 39B, annealing the layer containing nickel and platinum, and removing the unreacted portion of the layer containing nickel and platinum.

[0403] Referring to FIG. 39D, after the formation of the first metal silicide layer 3912, the second portion of the insulator material 3906 is removed from above the second fin 3954, exposing the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the second source or drain region 3958 and the third source or drain region 3960 are formed within the second fin 3954, such as within the second silicon fin as shown. However, in another embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 are epitaxial regions formed within the recesses of the second fin 3954. In such an embodiment, the third source or drain region 3958 and the fourth source or drain region 3960 contain silicon.

[0404] Referring to FIG. 39E, the first metal layer 3914 is formed over the structure of FIG. 39D, that is, over the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960. Next, the second metal silicide layer 3962 is formed over the third source or drain region 3958 and the fourth source or drain region 3960 of the second fin 3954. The second metal silicide layer 3962 is formed from the first metal layer 3914 using, for example, an annealing process. In one embodiment, the second metal silicide layer 3962 has a composition different from that of the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is a titanium layer or includes it. In one embodiment, as shown, the first metal layer 3914 is formed as a conformal metal layer, conformally, for example, to the opening trenches of FIG. 39D.

[0405] Referring to FIG. 39F, in one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer 3916 over each of the first source or drain region 3908, the second source or drain region 3910, the third source or drain region 3958, and the fourth source or drain region 3960.

[0406] Referring to FIG. 39G, in one embodiment, the second metal layer 3918 is formed on the U-shaped metal layer 3916 having the structure of FIG. 39F. In one embodiment, the second metal layer 3918 has a composition different from that of the U-shaped metal layer 3916.

[0407] Referring to FIG. 39H, in one embodiment, the third metal layer 3920 is formed on the second metal layer 3918 having the structure of FIG. 39G. In one embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0408] Referring again to FIG. 39H, according to one embodiment of the present disclosure, the integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) above a substrate. The P-type semiconductor device includes a first fin 3904 such as a first silicon fin. It should be understood that the first fin has a top (shown as 3904A) and sidewalls (for example, the back and front of the page). The first gate electrode 3902 includes a first gate dielectric layer laterally adjacent to the sidewalls of the first fin 3904 above the top 3904A of the first fin 3904, and above the first gate dielectric layer laterally adjacent to the sidewalls of the first fin 3904 above the top 3904A of the first fin 3904, includes the first gate electrode. The first gate electrode 3902 has a first side surface 3902A and a second side surface 3902B opposite to the first side surface 3902A.

[0409] The first semiconductor source or drain region 3908 and the second semiconductor source or drain region 3910 are adjacent to the first side surface 3902A and the second side surface 3902B of the first gate electrode 3902, respectively. The first trench contact structure 3930 and the second trench contact structure 3932 are respectively above the first semiconductor source or drain region 3908 and the second semiconductor source or drain region 3910 that are adjacent to the first side surface 3902A and the second side surface 3902B of the first gate electrode 3902. The first metal silicide layer 3912 is directly sandwiched between the first trench contact structure 3930 and the first semiconductor source or drain region 3908, and between the second trench contact structure 3932 and the second trench contact structure 3910, respectively.

[0410] The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) above a substrate. The N-type semiconductor device includes a second fin 3954 such as a second silicon fin. It should be understood that the second fin has a top (shown as 3954A) and sidewalls (for example, the back and the front of the page). The second gate electrode 3952 includes a second gate dielectric layer laterally adjacent to the sidewalls of the second fin 3954 above the top 3954A of the second fin 3954, and includes a second gate electrode above the second gate dielectric layer laterally adjacent to the sidewalls of the second fin 3954 above the top 3954A of the second fin 3954. The second gate electrode 3952 has a first side surface 3952A and a second side surface 3952B opposite to the first side surface 3952A.

[0411] The third semiconductor source or drain region 3958 and the fourth semiconductor source or drain region 3960 are adjacent to the first side surface 3952A and the second side surface 3952B of the second gate electrode 3952, respectively. The third trench contact structure 3970 and the fourth trench contact structure 3972 are respectively above the third semiconductor source or drain region 3958 and the fourth semiconductor source or drain region 3960, which are adjacent to the first side surface 3952A and the second side surface 3952B of the second gate electrode 3952. The second metal silicide layer 3962 is directly sandwiched between the third trench contact structure 3970 and the third semiconductor source or drain region 3958, and between the fourth trench contact structure 3972 and the fourth semiconductor source or drain region 3960, respectively. In one embodiment, the first metal silicide layer 3912 contains at least one kind of metal not included in the second metal silicide layer 3962.

[0412] In one embodiment, the second metal silicide layer 3962 contains titanium and silicon. The first metal silicide layer 3912 contains nickel, platinum and silicon. In one embodiment, the first metal silicide layer 3912 further contains germanium. In one embodiment, the first metal silicide layer 3912 further contains titanium. Titanium is incorporated into the first metal silicide layer 3912, for example, during the formation of the second metal silicide layer 3962 together with the first metal layer 3914 later. In such an embodiment, the silicide layer already formed on the PMOS source or drain region is further changed by an annealing process used to form a silicide region on the NMOS source or drain region. As a result, a silicide layer on the PMOS source or drain region having all silicide metals in a small proportion may occur. However, in other embodiments, such a silicide layer already formed on the PMOS source or drain region does not change, or substantially does not change, by an annealing process used to form a silicide region on the NMOS source or drain region.

[0413] In one embodiment, the first semiconductor source or drain region 3908, and the second semiconductor source or drain region 3910 are a first embedded semiconductor source or drain region and a second embedded semiconductor source or drain region that include silicon and germanium. In such an embodiment, the third semiconductor source or drain region 3958, and the fourth semiconductor source or drain region 3960 are a third embedded semiconductor source or drain region, and a fourth embedded semiconductor source or drain region that include silicon. In another embodiment, the third semiconductor source or drain region 3958, and the fourth semiconductor source or drain region 3960 are formed in the fin 3954 and are not an embedded epitaxial region.

[0414] In one embodiment, the first trench contact structure 3930, the second trench contact structure 3932, the third trench contact structure 3970, and the fourth trench contact structure 3972 all include a U-shaped metal layer 3916 and a T-shaped metal layer 3918 that is above and over the entire U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 includes titanium, and the T-shaped metal layer 3918 includes cobalt. In one embodiment, the first trench contact structure 3930, the second trench contact structure 3932, the third trench contact structure 3970, and the fourth trench contact structure 3972 all further include a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer include titanium, and the T-shaped metal layer 3918 includes cobalt.

[0415] In another aspect, a trench contact structure is described, for example, for a source or drain region. In one example, FIG. 40A shows a cross-sectional view of an integrated circuit structure including a trench contact for an NMOS device according to an embodiment of the present disclosure. FIG. 40B shows a cross-sectional view of an integrated circuit structure including a trench contact for a PMOS device according to another embodiment of the present disclosure.

[0416] Referring to FIG. 40A, the integrated circuit structure 4000 includes fins 4002 such as silicon fins. The gate dielectric layer 4004 is above the fin 4002. The gate electrode 4006 is above the gate dielectric layer 4004. In one embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010. In one embodiment, the dielectric cap 4012 is above the gate electrode 4006 and above the gate dielectric layer 4004. The gate electrode has a first side surface 4006A and a second side surface 4006B opposite the first side surface 4006A. The dielectric spacer 4013 is along the sidewalls of the gate electrode 4006. In one embodiment, as shown, the gate dielectric layer 4004 is further between the first dielectric spacer 4013 and the first side surface 4006A of the gate electrode 4006, and between the second dielectric spacer 4013 and the second side surface 4006B of the gate electrode 4006. In one embodiment, although not shown, a thin oxide layer such as a thermally or chemically oxidized silicon or silicon dioxide layer is between the fin 4002 and the gate dielectric layer 4004.

[0417] The first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are adjacent to the first side surface 4006A and the second side surface 4006B of the gate electrode 4006, respectively. In one embodiment, as shown, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are within the fin 4002. However, in another embodiment, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are embedded epitaxial regions formed in recesses of the fin 4002.

[0418] The first trench contact structure 4018 and the second trench contact structure 4020 are respectively above the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 adjacent to the first side surface 4006A and the second side surface 4006B of the gate electrode 4006. Both the first trench contact structure 4018 and the second trench contact structure 4020 include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and above the entire U-shaped metal layer 4022. In one embodiment, the U-shaped metal layer 4022 and the T-shaped metal layer 4024 have different compositions. In such an embodiment, the U-shaped metal layer 4022 contains titanium and the T-shaped metal layer 4024 contains cobalt. In one embodiment, both the first trench contact structure 4018 and the second trench contact structure 4020 further include a third metal layer 4026 on the T-shaped metal layer 4024. In such an embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 contain titanium and the T-shaped metal layer 4024 contains cobalt.

[0419] The first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is on and coupled to the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further above and in contact with a portion of one of the dielectric spacers 4013 and above and in contact with a portion of the dielectric cap 4012. The second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is on and coupled to the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further above and in contact with a portion of another dielectric spacer 4013 and above and in contact with a portion of another dielectric cap 4012.

[0420] In one embodiment, the metal silicide layer 4032 is directly sandwiched between the first trench contact structure 4018 and the first semiconductor source or drain region 4014, and between the second trench contact structure 4020 and the second semiconductor source or drain region 4016, respectively. In one embodiment, the metal silicide layer 4032 includes titanium and silicon. In certain such embodiments, the first semiconductor source or drain region 4014 and the second semiconductor source or drain region 4016 are the first N-type semiconductor source or drain region and the second N-type semiconductor source or drain region.

[0421] Referring to FIG. 40B, the integrated circuit structure 4050 includes fins 4052 such as silicon fins. The gate dielectric layer 4054 is above the fin 4052. The gate electrode 4056 is above the gate dielectric layer 4054. In one embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive filler 4060. In one embodiment, the dielectric cap 4062 is above the gate electrode 4056 and above the gate dielectric layer 4054. The gate electrode has a first side surface 4056A and a second side surface 4056B opposite the first side surface 4056A. The dielectric spacer 4063 is along the sidewalls of the gate electrode 4056. In one embodiment, as shown, the gate dielectric layer 4054 is further between the first dielectric spacer 4063 and the first side surface 4056A of the gate electrode 4056, and between the second dielectric spacer 4063 and the second side surface 4056B of the gate electrode 4056. In one embodiment, although not shown, a thin oxide layer such as a thermal or chemical oxide silicon or silicon dioxide layer is between the fin 4052 and the gate dielectric layer 4054.

[0422] The first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 are adjacent to the first side surface 4056A and the second side surface 4056B of the gate electrode 4056, respectively. In one embodiment, as illustrated, the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 are each an embedded epitaxial region formed in the recesses 4065 and 4067 of the fin 4052. However, in another embodiment, the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 are within the fin 4052.

[0423] The first trench contact structure 4068 and the second trench contact structure 4070 are each above the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 adjacent to the first side surface 4056A and the second side surface 4056B of the gate electrode 4056. Both the first trench contact structure 4068 and the second trench contact structure 4070 include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 on and above the entire U-shaped metal layer 4072. In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In such an embodiment, the U-shaped metal layer 4072 contains titanium and the T-shaped metal layer 4074 contains cobalt. In one embodiment, both the first trench contact structure 4068 and the second trench contact structure 4070 further include a third metal layer 4076 on the T-shaped metal layer 4074. In such an embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 contain titanium and the T-shaped metal layer 4074 contains cobalt.

[0424] The first trench contact via 4078 is electrically connected to the first trench contact 4068. In certain embodiments, the first trench contact via 4078 is on and coupled to the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is further above and in contact with a portion of one of the dielectric spacers 4063 and above and in contact with a portion of the dielectric cap 4062. The second trench contact via 4080 is electrically connected to the second trench contact 4070. In certain embodiments, the second trench contact via 4080 is on and coupled to the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further above and in contact with a portion of another dielectric spacer 4063 and above and in contact with another portion of the dielectric cap 4062.

[0425] In one embodiment, the metal silicide layer 4082 is directly sandwiched between the first trench contact structure 4068 and the first semiconductor source or drain region 4064, and between the second trench contact structure 4070 and the second semiconductor source or drain region 4066, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In certain such embodiments, the first semiconductor source or drain region 4064 and the second semiconductor source or drain region 4066 are a first P-type semiconductor source or drain region and a second P-type semiconductor source or drain region. In one embodiment, the metal silicide layer 4082 further comprises germanium. In one embodiment, the metal silicide layer 4082 further comprises titanium.

[0426] One or more embodiments described herein relate to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. Embodiments may be applicable to or may include one or more of chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

[0427] Certain embodiments may include the manufacture of titanium or similar metal layers using low-temperature (e.g., below 500 °C, or in the range of 400 - 500 °C) chemical vapor deposition of contact metals to provide conformal source or drain contacts. The implementation of such conformal source or drain contacts may improve three-dimensional (3D) transistor complementary metal oxide semiconductor (CMOS) performance.

[0428] Providing context, the metal for the semiconductor contact layer can be deposited using sputtering. Sputtering is a line of sight process and may not be well-suited for 3D transistor manufacturing. Known sputtering solutions have a weak or incomplete metal-semiconductor junction at the device contact surface and an oblique deposition incidence.

[0429] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented for the manufacture of contact metals to provide three-dimensional conformality and maximize the metal-semiconductor junction contact area. The resulting larger contact area may reduce the resistance of the junction. Embodiments may include deposition on a semiconductor surface having a non-planar topography, where the topography of the region refers to the shape and features of its own surface, and non-planar topography includes the shape and features of a surface that is non-flat, or the shape and features of a portion of the surface, i.e., the shape and features of a surface that is not entirely flat.

[0430] The embodiments described herein may include the manufacture of a wraparound contact structure. In one such embodiment, the use of a pure metal conformally deposited on a transistor source drain contact by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or plasma enhanced atomic layer deposition is described. Such conformal deposition may be used to increase the available area of the metal semiconductor contact and reduce resistance in order to improve the performance of the transistor device. In one embodiment, relatively low temperature deposition results in a minimized contact resistance per unit area.

[0431] As described herein, it should be understood that various integrated circuit structures can be fabricated using an integration scheme involving a metal layer deposition process. According to one embodiment of the present disclosure, a method of fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber having an RF source, the substrate having features thereon. The method also includes reacting titanium tetrachloride (TiCl4) with hydrogen (H2) to form a titanium (Ti) layer on the features of the substrate.

[0432] In one embodiment, the titanium layer has a total atomic composition comprising 98% or more titanium and 0.5 - 2% chlorine. In an alternative embodiment, a similar process is used to produce a high-purity metal layer of zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In one embodiment, the variation in film thickness is relatively small. For example, in one embodiment, on all coated surfaces, it is greater than 50%, nominally 70% or more (i.e., the variation in thickness is 30% or less). In one embodiment, Si or SiGe reacts during deposition to speed up the incorporation of Ti, so the thickness is measurably thicker on silicon (Si) or silicon germanium (SiGe) than on other surfaces. In one embodiment, the film composition contains generally 0.5% (or less than 1%) Cl as an impurity and basically no other observed impurities. In one embodiment, the film-forming process enables the coating of metal on off-line-of-sight surfaces, such as surfaces hidden by line-of-sight sputter deposition. The embodiments described herein can be implemented to improve transistor device performance by reducing the external resistance of the current driven through the source and drain contacts.

[0433] According to one embodiment of the present disclosure, the feature of the substrate is a source or drain contact trench that exposes a semiconductor source or drain structure. The titanium layer (or other high-purity metal layer) is a conductive contact layer for the semiconductor source or drain structure. Exemplary embodiments of such an implementation will be described later in connection with FIGS. 41A, 41B, 42, 43A - 43C, and 44.

[0434] FIG. 41A shows a cross-sectional view of a semiconductor device having a conductive contact on a source or drain region according to one embodiment of the present disclosure.

[0435] Referring to FIG. 41A, the semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. Source region 4108 and drain region 4110 are on opposite sides of the gate structure 4102. Source or drain contact 4112 is electrically connected to the source region 4108 and drain region 4110 and is spaced from the gate structure 4102 by one or both of an interlayer dielectric layer 4114 or a gate dielectric spacer 4116. The source region 4108 and drain region 4110 are regions of the substrate 4104.

[0436] In one embodiment, the source or drain contact 4112 includes a high purity metal layer 4112A as described above and a conductive trench fill material 4112B. In one embodiment, the high purity metal layer 4112A has an all-atom composition that includes 98% or more titanium. In such an embodiment, the all-atom composition of the high purity metal layer 4112A further includes 0.5 to 2% chlorine. In one embodiment, the thickness variation of the high purity metal layer 4112A is 30% or less. In one embodiment, the conductive trench fill material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or an alloy thereof.

[0437] FIG. 41B shows a cross-sectional view of another semiconductor device having a conductive contact over a raised source or drain region, according to an embodiment of the present disclosure.

[0438] Referring to FIG. 41B, a semiconductor structure 4150 includes a gate structure 4152 over a substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. Source region 4158 and drain region 4160 are on opposite sides of and sandwich the gate structure 4152. A source or drain contact 4162 is electrically connected to the source region 4158 and the drain region 4160 and is spaced from the gate structure 4152 by one or both of an interlayer dielectric layer 4164 or a gate dielectric spacer 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in regions of the substrate 4154 that have been etched away. As shown, in one embodiment, the source region 4158 and the drain region 4160 are raised source and drain regions. In such a particular embodiment, the raised source and drain regions are raised silicon source and drain regions, or raised silicon germanium source and drain regions.

[0439] In one embodiment, the source or drain contact 4162 includes a high purity metal layer 4162A as described above, and a conductive trench fill material 4162B. In one embodiment, the high purity metal layer 4162A has an overall atomic composition that includes 98% or more titanium. In such an embodiment, the overall atomic composition of the high purity metal layer 4162A further includes 0.5 to 2% chlorine. In one embodiment, the thickness variation of the high purity metal layer 4162A is 30% or less. In one embodiment, the conductive trench fill material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or an alloy thereof.

[0440] Accordingly, in one embodiment, referring collectively to FIGS. 41A and 41B, an integrated circuit structure includes features having surfaces (source or drain contact trenches that expose semiconductor source or drain structures). High purity metal layer 4112A or 4162A is on the surface of the source or drain contact trench. It is to be understood that the contact formation process may involve consumption of the exposed silicon or germanium or silicon germanium material of the source or drain region. Such consumption may degrade device performance. In contrast, according to one embodiment of the present disclosure, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not eroded or consumed, or is substantially not eroded or consumed, below the source or drain contact trench. In such an embodiment, the lack of consumption or erosion results from the low temperature deposition of the high purity metal contact layer.

[0441] FIG. 42 shows a plan view of a plurality of gate lines above a pair of semiconductor fins according to one embodiment of the present disclosure.

[0442] Referring to FIG. 42, a plurality of active gate lines 4204 are formed above a plurality of semiconductor fins 4200. Dummy gate lines 4206 are at the ends of the plurality of semiconductor fins 4200. The spacing 4208 between gate lines 4204 and 4206 is in a position where trench contacts can be formed as conductive contacts to source or drain regions such as source or drain regions 4251, 4252, 4253, and 4254.

[0443] FIGS. 43A - 43C show cross-sectional views taken along axis a - a' of FIG. 42 for various steps in a method of manufacturing an integrated circuit structure according to one embodiment of the present disclosure.

[0444] Referring to FIG. 43A, a plurality of active gate lines 4304 are formed above a semiconductor fin 4302 formed above a substrate 4300. A dummy gate line 4306 is at an end of the semiconductor fin 4302. A dielectric layer 4310 is between the active gate lines 4304, between the dummy gate line 4306 and the active gate lines 4304, and outside the dummy gate line 4306. An embedded source or drain structure 4308 is in the semiconductor fin 4302 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate lines 4304. The active gate line 4304 includes a gate dielectric layer 4312, a work function gate electrode portion 4314, a fill gate electrode portion 4316, and a dielectric capping layer 4318. Dielectric spacers 4320 are along sidewalls of the active gate lines 4304 and the dummy gate line 4306.

[0445] Referring to FIG. 43B, a portion of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate lines 4304 is removed to provide an opening 4330 at a location where a trench contact is to be formed. Removing a portion of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate lines 4304 can result in erosion of the embedded source or drain structure 4308, thereby providing an eroded embedded source or drain structure 4332 having an upper saddle-shaped topography as illustrated in FIG. 43B.

[0446] Referring to FIG. 43C, a trench contact 4334 is formed in the opening 4330 between the active gate lines 4304 and between the dummy gate line 4306 and the active gate lines 4304. Each of the trench contacts 4334 can include a metal contact layer 4336 and a conductive fill material 4338.

[0447] FIG. 44 shows a cross-sectional view taken along axis b-b' of FIG. 42 of an integrated circuit structure according to an embodiment of the present disclosure.

[0448] Referring to FIG. 44, fin 4402 is shown above substrate 4404. The lower portion of fin 4402 is surrounded by trench isolation material 4404. The upper portion of fin 4402 has been removed to enable the growth of the embedded source and drain structure 4406. Trench contact 4408 is formed in an opening in dielectric layer 4410, and the opening exposes the embedded source and drain structure 4406. The trench contact includes metal contact layer 4412 and conductive fill material 4414. It should be understood that, according to one embodiment, metal contact layer 4412 extends to the top of trench contact 4408 as shown in FIG. 44. However, in another embodiment, metal contact layer 4412 does not extend to the top of trench contact 4408 and is recessed somewhat into trench contact 4408, similar to the illustration of metal contact layer 4336 in FIG. 43C, for example.

[0449] Accordingly, referring collectively to FIGS. 42, 43A - 43C, and 44, according to one embodiment of the present disclosure, an integrated circuit structure includes semiconductor fins (4200, 4302, 4402) over a substrate (4300, 4400). The semiconductor fins (4200, 4302, 4402) have a top and sidewalls. Gate electrodes (4204, 4304) are above the top of the semiconductor fins (4200, 4302, 4402) and adjacent to a portion of their sidewalls. The gate electrodes (4204, 4304) define a channel region in the semiconductor fins (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is at a first end of the channel region on a first side of the gate electrodes (4204, 4304), and the first semiconductor source or drain structure (4251, 4332, 4406) has a non - planar topography. A second semiconductor source or drain structure (4252, 4332, 4406) is at a second end of the channel region on a second side of the gate electrodes (4204, 4304), the second end being opposite the first end and the second side being opposite the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non - planar topography. Metal contact materials (4336, 4412) are immediately above the first semiconductor source or drain structure (4251, 4332, 4406) and immediately above the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact materials (4336, 4412) are conformal to the non - planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conformal to the non - planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0450] In one embodiment, the metal contact materials (4336, 4412) have an overall atomic composition that includes 95% or more of a single metal species. In such an embodiment, the metal contact materials (4336, 4412) have an overall atomic composition that includes 98% or more titanium. In such a particular embodiment, the overall atomic composition of the metal contact materials (4336, 4412) further includes 0.5 to 2% chlorine. In one embodiment, the variation in the thickness of the metal contact materials (4336, 4412) is 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0451] In one embodiment, both the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) include, for example, as illustrated in FIG. 44, a raised central portion and a lower side portion. In one embodiment, both the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) include, for example, as illustrated in FIG. 43C, a saddle-shaped portion.

[0452] In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) include silicon. In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) further include germanium, for example, in the form of silicon germanium.

[0453] In one embodiment, the metal contact material (4336, 4412) immediately above the first semiconductor source or drain structure (4251, 4332, 4406) further extends along the sidewalls of the trenches in the dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), and the trenches expose a part of the first semiconductor source or drain structure (4251, 4332, 4406). In such an embodiment, the thickness of the metal contact material (4336) along the sidewalls of the trenches decreases from the first semiconductor source or drain structure (4336A in 4332) towards a position (4336B) above the first semiconductor source or drain structure (4332), an example of which is shown in FIG. 43C. In one embodiment, the conductive fill material (4338, 4414) is on the metal contact material (4336, 4412) in the trenches, as illustrated in FIGS. 43C and 44.

[0454] In one embodiment, the integrated circuit structure further includes second semiconductor fins (e.g., upper fins 4200, 4302, 4402 in FIG. 42) having tops and sidewalls. Gate electrodes (4204, 4304) are further above the tops of the second semiconductor fins and adjacent to some of their sidewalls, and the gate electrodes define channel regions in the second semiconductor fins. A third semiconductor source or drain structure (4253, 4332, 4406) is at a first end of the channel region of the second semiconductor fin on a first side of the gate electrodes (4204, 4304), and the third semiconductor source or drain structure has a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is at a second end of the channel region of the second semiconductor fin on a second side of the gate electrodes (4204, 4304), the second end facing the first end, and the fourth semiconductor source or drain structure (4254, 4332, 4406) has a non-planar topography. Metal contact materials (4336, 4412) are immediately above the third semiconductor source or drain structures (4253, 4332, 4406) and immediately above the fourth semiconductor source or drain structures (4254, 4332, 4406), and the metal contact materials (4336, 4412) are conformal to the non-planar topography of the third semiconductor source or drain structures (4253, 4332, 4406) and conformal to the non-planar topography of the fourth semiconductor source or drain structures (4254, 4332, 4406). In one embodiment, the metal contact materials (4336, 4412) are continuous between the first semiconductor source or drain structures (4251, 4332, left side 4406) and the third semiconductor source or drain structures (4253, 4332, right side 4406), and continuous between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0455] In another aspect, the hard mask material can be used to protect (inhibit erosion of) the dielectric material at the trench line position (e.g., contact plug position) where the conductive trench contact is interrupted and can be held thereon. For example, FIGS. 45A and 45B respectively show a plan view and a corresponding cross-sectional view of an integrated circuit structure including a trench contact plug having a hard mask material thereon, according to one embodiment of the present disclosure.

[0456] Referring to FIGS. 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes fins 4502A such as silicon fins. A plurality of gate structures 4506 are above the fins 4502A. Each of the gate structures 4506 is along a direction 4508 orthogonal to the fins 4502A and has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is above the fins 4502A and is directly sandwiched between the first pair 4506A / 4506B of dielectric sidewall spacers 4510 of the gate structures 4506. A contact plug 4514B is above the fins 4502A and is directly sandwiched between the second pair 4506B / 4506C of dielectric sidewall spacers 4510 of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0457] In one embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-pure nitride material.

[0458] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown.

[0459] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, each dielectric cap 4528 of the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514B, as illustrated. In one embodiment, although not shown, a thin oxide layer such as thermally or chemically oxidized silicon or silicon dioxide layer is between the fin 4502A and the gate dielectric layer 4526.

[0460] Referring again to FIGS. 45A and 45B, in one embodiment, the integrated circuit structure 4500 includes a plurality of fins 4502, such as a plurality of silicon fins. Each of the plurality of fins 4502 is along a first direction 4504. A plurality of gate structures 4506 are above the plurality of fins 4502. Each of the plurality of gate structures 4506 is along a second direction 4508 that is orthogonal to the first direction 4504. Each of the plurality of gate structures 4506 has a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is above the first fin 4502A of the plurality of fins 4502 and is directly sandwiched between the dielectric sidewall spacers 4510 of a pair of gate structures 4506. A contact plug 4514A is above the second fin 4502B of the plurality of fins 4502 and is directly sandwiched between the dielectric sidewall spacers 4510 of a pair of gate structures 4506. Similar to the cross-sectional view of the contact plug 4514B, the contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0461] In one embodiment, the lower dielectric material 4516 of the contact plug 4516A includes silicon and oxygen, such as silicon oxide or silicon dioxide material. The upper hard mask material 4518 of the contact plug 4516A includes silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon pure nitride material.

[0462] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as illustrated.

[0463] In one embodiment, each of the plurality of gate structures 4506 includes a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is on the gate electrode 4524. In one embodiment, each dielectric cap 4528 of the plurality of gate structures 4506 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as illustrated. In one embodiment, although not shown, a thin oxide layer, such as thermally or chemically oxidized silicon or a silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526.

[0464] One or more embodiments of the present disclosure relate to a gate-aligned contact process. Such a process can be implemented to form contact structures for the manufacture of semiconductor structures, such as integrated circuits. In one embodiment, the contact pattern is formed to align with an existing gate pattern. In contrast, other approaches typically involve additional lithography processes with tight alignment of the lithography contact pattern to the existing gate pattern, typically in combination with selective contact etching. For example, another process can include patterning of a poly (gate) grid, along with patterning of separate contacts and contact plugs.

[0465] According to one or more embodiments described herein, the method of contact formation involves forming a contact pattern that is substantially perfectly aligned with an existing gate pattern, but eliminates the use of a lithography process with a very tight alignment margin. In such an embodiment, this approach enables the use of a wet etching that is essentially highly selective (e.g., relative to dry etching or plasma etching) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a lithography process for the contact plugs. In such an embodiment, this approach enables the elimination of the need for an otherwise critical lithography process for generating the contact pattern as used in other approaches. In one embodiment, the trench contact grid is not formed separately patterned, but rather is formed between the poly (gate) lines. For example, in such an embodiment, the trench contact grid is formed after the gate grid patterning but before the gate grid cut.

[0466] 46A through 46D show cross-sectional views representing various steps in a method of manufacturing an integrated circuit structure comprising trench contact plugs having a hard mask material thereon, in accordance with one embodiment of the present disclosure.

[0467] Referring to FIG. 46A, a method of manufacturing an integrated circuit structure comprises forming a plurality of fins, each 4602 of the plurality of fins being along a first direction 4604. Each 4602 of the plurality of fins may include a diffusion region 4606. A plurality of gate structures 4608 are formed over the plurality of fins. Each of the plurality of gate structures 4508 is along a second direction 4610 that is orthogonal to the first direction 4604 (e.g., the direction 4610 is into and out of the page). A sacrificial material structure 4612 is formed between a first pair of the gate structures 4608. A contact plug 4614 is between a second pair of the gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask material 4618 is over the lower dielectric material 4616.

[0468] In one embodiment, the gate structure 4608 includes a sacrificial or dummy gate stack and dielectric spacers 4609. The sacrificial or dummy gate stack can be composed of polycrystalline silicon or silicon nitride pillars or some other sacrificial material, which can be referred to as gate dummy materials.

[0469] Referring to FIG. 46B, the sacrificial material structure 4612 is removed from the structure of FIG. 46A to form an opening 4620 between the first pair of the gate structures 4608.

[0470] Referring to FIG. 46C, a trench contact structure 4622 is formed in the opening 4620 between the first pair of the gate structures 4608. Further, in one embodiment, as part of the formation of the trench contact structure 4622, the hard mask 4618 in FIGS. 46A and 46B is planarized. The finally finished contact plug 4614' includes a lower dielectric material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618.

[0471] In one embodiment, each of the lower dielectric materials 4616 of the contact plugs 4614' contains silicon and oxygen, and each of the upper hard mask materials 4624 of the contact plugs 4614' contains silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0472] Referring to FIG. 46D, the sacrificial or dummy gate stack of the gate structure 4608 is replaced in a replacement gate process scheme. In such a scheme, a dummy gate material such as polysilicon or silicon nitride pillar material is removed and replaced with a permanent gate electrode material. In such an embodiment, the permanent gate dielectric layer is also not carried over from a previous process but is also formed in this process.

[0473] Accordingly, the permanent gate structure 4630 includes a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Further, in one embodiment, the upper portion of the permanent gate structure 4630 is removed, for example, by an etching process and replaced with a dielectric cap 4636. In one embodiment, the dielectric cap 4636 of each individual permanent gate structure 4630 has an upper surface that is coplanar with the upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0474] Referring again to FIGS. 46A-46D, in one embodiment, after the formation of the trench contact structure 4622 as shown, a replacement gate process is performed. However, according to other embodiments, the replacement gate process is performed before the formation of the trench contact structure 4622.

[0475] In another aspect, a contact over active gate (COAG) structure and process is described. One or more embodiments of the present disclosure relate to a semiconductor structure or device having one or more gate contact structures (e.g., gate contact vias) disposed over an active portion of a gate electrode of the semiconductor structure or device. One or more embodiments of the present disclosure relate to a method of manufacturing a semiconductor structure or device having one or more gate contact structures formed over an active portion of a gate electrode of the semiconductor structure or device. The approach described herein can be used to reduce the standard cell area by enabling the formation of gate contacts over the active gate region. In one or more embodiments, the gate contact structure fabricated to contact the gate electrode is a self-aligned via structure.

[0476] In technologies where the space and layout constraints are somewhat relaxed compared to current-generation space and layout constraints, the contact to the gate structure can be fabricated by contacting a portion of the gate electrode disposed over the isolation region. As an example, FIG. 47A shows a plan view of a semiconductor device having a gate contact disposed over an inactive portion of the gate electrode.

[0477] Referring to FIG. 47A, a semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed on a substrate 4702 or within an isolation region 4706. One or more gate lines (also known as poly lines), such as gate lines 4708A, 4708B, and 4708C, are disposed above not only a portion of the isolation region 4706 but also above the diffusion or active region 4704. Source or drain contacts (also known as trench contacts), such as contacts 4710A and 4710B, are disposed above the source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contacts to trench contacts 4710A and 4710B, respectively. An isolation gate contact 4714 and an upper gate contact via 4716 provide contacts to gate line 4708B. In contrast to source or drain trench contacts 4710A or 4710B, gate contact 4714 is disposed above the isolation region 4706 but not above the diffusion or active region 4704 from a top view perspective. Further, neither gate contact 4714 nor gate contact via 4716 is disposed between source or drain trench contacts 4710A and 4710B.

[0478] FIG. 47B shows a cross-sectional view of a non-planar semiconductor device having a gate contact disposed above an inactive portion of a gate electrode. Referring to FIG. 47B, a semiconductor structure or device 4700B (e.g., a non-planar version of device 4700A of FIG. 47A) comprises a non-planar diffusion or active region 4704C (e.g., a fin structure) in isolation region 4706 formed from substrate 4702. Gate line 4708B is disposed above not only a portion of isolation region 4706 but also above non-planar diffusion or active region 4704B. As shown, gate line 4708B includes gate electrode 4750 and gate dielectric layer 4752 together with dielectric cap layer 4754. Gate contact 4714, and upper layer gate contact via 4716 are also seen from this perspective together with upper layer metal interconnect 4760, and all of these are disposed within an interlayer dielectric stack or layer 4770. Also, viewed from the perspective of FIG. 47B, gate contact 4714 is disposed above isolation region 4706 but not above non-planar diffusion or active region 4704B.

[0479] Referring again to FIGS. 47A and 47B, in the configurations of semiconductor structures or devices 4700A and 4700B respectively, the gate contacts are placed above the isolation regions. In such configurations, layout space is wasted. However, placing the gate contact above the active region requires a very tight alignment margin, or else the gate dimensions need to be increased to provide sufficient space to land the gate contact. Further, conventionally, contacts to the gate above the diffusion region have been avoided because there is a risk of piercing through other gate materials (e.g., polysilicon) to contact the underlying active region. One or more embodiments described herein address the above problems by providing a practicable approach to manufacturing a contact structure that contacts a portion of a gate electrode formed above a diffusion or active region, and the resulting structure.

[0480] As an example, FIG. 48A shows a plan view of a semiconductor device having a gate contact via disposed above an active portion of a gate electrode, according to one embodiment of the present disclosure. Referring to FIG. 48A, a semiconductor structure or device 4800A includes a substrate 4802 and a diffusion or active region 4804 disposed within isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed above not only a portion of the isolation region 4806 but also above the diffusion or active region 4804. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed above source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contacts to trench contacts 4810A and 4810B, respectively. A gate contact via 4816 without an intervening isolation gate contact layer provides a contact to gate line 4808B...

Claims

1. A nanowire having a semiconductor material, the nanowire having a channel region, a nanowire, and A gate electrode surrounding the channel region of the nanowire, the gate electrode having a first side surface and a second side surface facing the first side surface, a gate electrode, and A first semiconductor source or drain region adjacent to the first side surface of the gate electrode, and a second semiconductor source or drain region adjacent to the second side surface of the gate electrode, and A trench contact structure above one of the first semiconductor source or drain region and the second semiconductor source or drain region, the trench contact structure having a T-shaped metal layer on a U-shaped metal layer, the U-shaped metal layer having a lateral width, a trench contact structure, and A dielectric layer between the gate electrode and the trench contact structure, the dielectric layer having a top surface, a dielectric layer, and An insulating cap layer above the T-shaped metal layer of the trench contact structure, the insulating cap layer having a lateral width larger than the lateral width of the U-shaped metal layer, the insulating cap layer having a top surface coplanar with the top surface of the dielectric layer, an insulating cap layer, and An integrated circuit structure comprising.

2. The integrated circuit structure according to claim 1, wherein the U-shaped metal layer and the T-shaped metal layer have different compositions.

3. The integrated circuit structure according to claim 1 or 2, wherein the U-shaped metal layer contains titanium.

4. The integrated circuit structure according to any one of claims 1 to 3, wherein the T-shaped metal layer contains cobalt.

5. The integrated circuit structure according to any one of claims 1 to 4, wherein the trench contact structure further includes a third metal layer above the T-shaped metal layer and below the insulating cap layer.

6. The integrated circuit structure according to claim 5, wherein the third metal layer and the U-shaped metal layer have the same composition.

7. The integrated circuit structure according to any one of claims 1 to 6, further comprising a metal silicide layer sandwiched between the trench contact structure and one of the first semiconductor source or drain region and the second semiconductor source or drain region.

8. The integrated circuit structure according to claim 7, wherein the metal silicide layer contains titanium and silicon.

9. The first semiconductor source or drain region is a first N-type semiconductor source or drain region, and the second semiconductor source or drain region is a second N-type semiconductor source or drain region. The integrated circuit structure according to claim 8.

10. The metal silicide layer includes nickel, platinum, and silicon. The integrated circuit structure according to claim 7.

11. A nanowire having a semiconductor material, the nanowire having a channel region, a nanowire, A gate electrode surrounding the channel region of the nanowire, the gate electrode having a first side surface and a second side surface facing the first side surface, a gate electrode, A first semiconductor source or drain region adjacent to the first side surface of the gate electrode, and a second semiconductor source or drain region adjacent to the second side surface of the gate electrode, A trench contact structure above one of the first semiconductor source or drain region and the second semiconductor source or drain region, the trench contact structure having a U-shaped metal layer and a T-shaped metal layer above and above the entire U-shaped metal layer, a trench contact structure, A dielectric layer between the gate electrode and the trench contact structure, the dielectric layer having an upper surface above the upper surface of the T-shaped metal layer of the trench contact structure, a dielectric layer, An integrated circuit structure comprising.

12. The U-shaped metal layer and the T-shaped metal layer have different compositions. The integrated circuit structure according to claim 11.

13. The U-shaped metal layer contains titanium. The integrated circuit structure according to claim 11 or 12.

14. The T-shaped metal layer contains cobalt. The integrated circuit structure according to any one of claims 11 to 13.

15. The trench contact structure further includes a third metal layer on the T-shaped metal layer. The integrated circuit structure according to any one of claims 11 to 14.

16. The third metal layer and the U-shaped metal layer have the same composition. The integrated circuit structure according to claim 15.

17. The integrated circuit structure according to any one of claims 11 to 16, further comprising a metal silicide layer sandwiched between the trench contact structure and the one of the first semiconductor source or drain region and the second semiconductor source or drain region.

18. The metal silicide layer contains titanium and silicon, and the integrated circuit structure according to claim 17.

19. The first semiconductor source or drain region is a first N-type semiconductor source or drain region, and the second semiconductor source or drain region is a second N-type semiconductor source or drain region, and the integrated circuit structure according to claim 18.

20. The metal silicide layer contains nickel, platinum and silicon, and the integrated circuit structure according to claim 17.

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