Semiconductor device

Abstract

To manufacture a reliable display device including a thin film transistor having stable electrical characteristics.SOLUTION: In a manufacturing method of a semiconductor device including a thin film transistor having a semiconductor layer including a channel forming region as an oxide semiconductor film, after performing heat treatment (heat treatment for dehydration or dehydrogenation) to increase the purity of the oxide semiconductor film and reduce water content as an impurity, the oxide semiconductor film is slowly cooled in an oxygen atmosphere. In addition, impurities such as moisture existing not only in the oxide semiconductor film but also in a gate insulating layer are reduced, and impurities such as moisture existing at the interface between a film provided in contact with the upper and lower surfaces and the oxide semiconductor film are reduced.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Indium oxide, an example of a metal oxide, is a liquid crystal display. It is used as an electrode material with the translucency required for liquid crystal displays, etc.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include Examples of such oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga, and Zn It is known as a multi-component oxide semiconductor (also called In-Ga-Zn oxide) having the following structure: (Non-Patent Documents 2 to 4).

[0006] In addition, it has been confirmed that an oxide semiconductor composed of an In-Ga-Zn-based oxide as described above can be applied to the channel layer of a thin-film transistor (Patent Document 5, Non-Patent Document 5, and 6).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0009] To fabricate a reliable semiconductor device having a thin film transistor with stable electrical characteristics is one of the problems.

Means for Solving the Problem

[0010] In a method of manufacturing a semiconductor device having a thin film transistor with a semiconductor layer including a channel formation region made of an oxide semiconductor film, a heat treatment (heat treatment for dehydration or dehydrogenation) is performed to increase the purity of the oxide semiconductor film and reduce impurities such as moisture. In addition, not only in the oxide semiconductor film but also impurities such as moisture present in the gate insulating layer 402 are reduced, and impurities such as moisture present at the interface between the film provided in contact with the oxide semiconductor film and the oxide semiconductor film are reduced. To reduce impurities such as moisture, after forming the oxide semiconductor film, in an inert gas atmosphere of nitrogen or a noble gas (argon, helium, etc.) or under reduced pressure in a state where the oxide semiconductor film is exposed, heat treatment is performed at 200 °C or higher, preferably 400 °C or higher and 600 °C or lower, to reduce the contained moisture in the oxide semiconductor film. Next, it is slowly cooled in an oxygen atmosphere in the range of room temperature or higher and less than 100 °C. After reducing the contained moisture in the film by heat treatment in an inert gas atmosphere of nitrogen or argon or under reduced pressure, using the oxide semiconductor film cooled in an oxygen atmosphere, the electrical characteristics of the thin film transistor are improved and the mass productivity of the high-performance thin film transistor is increased. is realized.

[0011] By varying the heating temperature conditions and measuring a plurality of samples heat-treated in a nitrogen atmosphere with a thermal desorption spectroscopy (TDS) measurement using a thermal desorption analyzer

[0012] After reducing the contained moisture in the film by heat treatment in an inert gas atmosphere of nitrogen or argon or under reduced pressure, the electrical characteristics of the thin film transistor are improved using the oxide semiconductor film cooled in an oxygen atmosphere, and the mass productivity of the high-performance thin film transistor is increased.

[0013] By varying the heating temperature conditions and measuring a plurality of samples heat-treated in a nitrogen atmosphere with a thermal desorption spectroscopy (TDS) measurement using a thermal desorption analyzer TDS (Thermal Desorption Spectroscopy) measurement ​​​​​​​The results are shown in Figures 5, 6, and 7.

[0014] The thermal desorption analyzer measures the gas components that are desorbed from the sample while the sample is heated and heated in a high vacuum. This is an instrument that detects and identifies gases and gases desorbed from the surface and inside of a sample using a quadrupole mass spectrometer. Here, a thermal desorption spectrometer (product name: EM) manufactured by Electron Science Corporation is used. The measurement conditions were a temperature rise of about 10°C / min, and the measurement was performed at about 1×10 -7 The vacuum level was 1500 Pa. The SEM voltage was 1500 V, and the Dwell Time was e is set to 0.2 [sec], and the number of channels used is 23. coefficient of 1.0, H2O fragmentation coefficient of 0.805, H2O through pass coefficient The number is 1.56 and the H2O pumping rate is 1.0.

[0015] Figure 5 shows a comparison sample with only a glass substrate and a sample with a 50 nm thick In-G The results of TDS are shown in comparison with a sample (sample 1) on which a-Zn-O-based non-single crystal film was formed. Figure 5 shows the results of measurements of H2O, with a peak appearing around 300°C. This allows impurities such as moisture (H2O) to be removed from the In-Ga-Zn-O non-single crystal film. You can see that it is separated.

[0016] Figure 6 shows a non-single crystal In-Ga-Zn-O film with a thickness of 50 nm formed on a glass substrate. The deposited sample (Sample 1) and a 50 nm thick In-Ga-Zn- After forming the O-based non-single crystal film, it was heated at 350°C in air for 1 hour. The sample (sample 2) was heated at 350°C in a nitrogen atmosphere for 1 hour. It is a comparison with the sample (Sample 3) thus tested, and shows the TDS measurement results for H2O is a graph. From the results in Fig. 6, in Sample 3, since the peak intensity around 300 °C is lower than that of Sample 2, it can be confirmed that moisture (H2O) and other impurities have been desorbed by the heat treatment in a nitrogen atmosphere. Therefore, it can be seen that heating in a nitrogen atmosphere can reduce impurities such as moisture (H2O) in the film more than in an air atmosphere.

[0017] Also, Fig. 7 shows a sample (Sample 1) with a 50-nm-thick In-Ga-Zn-O-based non-single crystal film formed on a glass substrate, a sample (Sample 4) heat-treated at 250 °C for 1 hour in a nitrogen atmosphere, a sample (Sample 3) heat-treated at 350 °C for 1 hour in a nitrogen atmosphere, a sample (Sample 5) heat-treated at 450 °C for 1 hour in a nitrogen atmosphere, a sample (Sample 6) heat-treated at 350 °C for 10 hours in a nitrogen atmosphere, and graphs showing the TDS measurement results of H2O for each of them. From the results in Fig. 7, it can be seen that the higher the heating temperature in a nitrogen atmosphere, the more impurities such as moisture (H2O) desorbed from the In-Ga-Zn-O-based non-single crystal film can be reduced.

[0018] Also, from the graphs in Fig. 6 and Fig. 7, a first peak indicating the desorption of impurities such as moisture (H2O) that can be confirmed around 200 °C to 250 °C, and a second peak indicating the desorption of impurities such as moisture (H2O) above 300 °C can be confirmed.

[0019] Note that the sample heat-treated at 450 °C in a nitrogen atmosphere was then left in air at room temperature for one week. ​Even when left standing for some time, no moisture desorbing at 200 °C or higher was observed, and it has been found that the In- Ga-Zn-O based polycrystalline film is stabilized by heat treatment.

[0020] Also, the heating temperature conditions in a nitrogen atmosphere were set to 150 °C, 175 °C, 200 °C, 225 °C, 25 0 °C, 275 °C, 300 °C, 325 °C, 350 °C, 375 °C, 400 °C, 425 °C, 45 0 °C and shaken, and the results of measuring the carrier concentration for each are shown in FIG. 4.

[0021] From the results of FIGS. 4, 5, 6, and 7, it can be seen that at 250 °C or higher in the TDS measurement, impurities such as moisture (H2O) desorb from the In-G a-Zn-O based polycrystalline film, and there is a relationship with the fluctuation of the carrier concentration. The carrier concentration increases due to the desorption of impurities such as moisture (H2O) from the In-Ga-Zn-O based polycrystalline film.

[0022] Also, by performing TDS measurement, for each of H, O, OH, H2, O2, N, N2, and Ar in addition to H2O, when the measurement was carried out, peaks with intensity could be observed for H2O, H, O, and OH, but no peaks could be observed for H2, O2, N, N2, and Ar. The sample used was a glass substrate with a 50 nm thick In-Ga-Zn-O based polycrystalline film formed thereon, and the heating conditions were 250 °C for 1 hour in a nitrogen atmosphere, 350 °C for 1 hour in a nitrogen atmosphere, 350 °C for 10 hours in a nitrogen atmosphere, 350 °C for 1 hour in an air atmosphere, 450 °C for 1 hour and, as a comparative example, an In-Ga-Zn-O based polycrystalline film without heat treatment and the glass substrate were each measured.

[0023] From the above results, by performing heat treatment on the In-Ga-Zn-O based polycrystalline film, mainly it can be seen that moisture is released. That is, desorption of moisture (H2O) mainly occurs from the In-Ga-Zn-O-based non-single crystal film by heat treatment, and H, O, O H, etc. are also released by decomposition of water molecules. Note that the In-Ga-Zn-O-based non-single crystal film also contains hydrogen and OH and it is considered that these are also released concomitantly by heat treatment.

[0024] In this specification, heat treatment in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), or heat treatment under reduced pressure is referred to as heat treatment for dehydration or dehydrogenation. In this specification it does not mean that only desorbing as H2 by this heat treatment is called dehydrogenation, but for the sake of convenience, desorbing H, OH, etc. is also included and called dehydration or dehydrogenation. That's it.

[0025] By performing heat treatment under an inert gas, impurities (H2O, H, OH, etc.) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed. After slow cooling, forming an oxide insulating film in contact with the oxide semiconductor layer, etc., reducing the carrier concentration of the oxide semiconductor layer is connected to an improvement in reliability.

[0026] The oxide semiconductor layer is made to have a lower resistance (the carrier concentration increases, preferably 1×10 18 / cm 3 or more) by heat treatment in a nitrogen atmosphere, and a low-resistance oxide semiconductor layer can be obtained. After that, when an oxide insulating film in contact with the low-resistance oxide semiconductor layer is formed, at least the region in contact with the oxide insulating film in the low-resistance oxide semiconductor layer is made to have a higher resistance ( the carrier concentration decreases, preferably 1×10 18 / cm 3less than), and a high-resistance oxide semiconductor region can be formed. During the process of the semiconductor device, heating in an inert gas atmosphere (or under reduced pressure), slow cooling in an oxygen atmosphere, and formation of an oxide insulating film, etc., are important for increasing or decreasing the carrier concentration of the oxide semiconductor layer. Also, by performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer, the oxide semiconductor layer becomes oxygen-deficient type and is n-type (n , n - , n + , etc.), and then, it can be said that by forming an oxide insulating film, the oxide semiconductor layer is made into an oxygen-excessive state and thus i-type. Also, when an oxide insulating film is formed on an In-Ga-Z n-O based non-single crystal film, the carrier concentration of the oxide insulating film becomes the carrier concentration shown by the dotted line 10 in FIG. 4 (1×10 14 / cm 3 or less). As a result, , it becomes possible to fabricate and provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability.

[0027] Note that the oxide insulating film formed in contact with the low-resistance oxide semiconductor layer uses an inorganic insulating film that blocks impurities such as moisture, hydrogen ions, and OH radicals. Typically, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is used. -

[0028] Furthermore, after forming an oxide insulating film as a protective film in contact with the low-resistance oxide semiconductor layer, a second heating may be performed. When a second heating is performed after forming an oxide insulating film as a protective film in contact with the oxide semiconductor layer, the variation in the electrical characteristics of the thin film transistor can be reduced.

[0029] The hydrogen content of the oxide semiconductor layer includes not only hydrogen contained in the layer, but also various forms such as water (H2O), M - O H, M - H (where M is a metal element), etc. However, the average value or peak value of the hydrogen concentration, which is an absolute quantity, is 3×10 20 cm -3 or less, preferably 1×10 20 cm -3 or less.

[0030] These concentration ranges are obtained by secondary ion mass spectrometry (SIMS) or based on its data.

[0031] The above configuration solves at least one of the above problems.

[0032] The oxide semiconductor used in this specification forms a thin film represented by, for example, InMO3(ZnO) m (m > 0), and a thin film transistor is fabricated using this thin film as the oxide semiconductor layer. Here, M represents one or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, in addition to the case where M is Ga, there may be cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition, in the above oxide semiconductor, in addition to the metal elements contained as M, there are those containing impurity elements such as Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, among the oxide semiconductor layers having a structure represented by InMO3(ZnO) (m > 0), the oxide semiconductor having a structure containing Ga as M is referred to as an In - Ga - Zn - O - based oxide semiconductor, and its thin film is also referred to as an In - Ga - Zn - O - based non - single - crystal film. InMO3(ZnO) m (m > 0), the oxide semiconductor having a structure containing Ga as M is referred to as an In - Ga - Zn - O - based oxide semiconductor, and its thin film is also referred to as an In - Ga - Zn - O - based non - single - crystal film.

[0033] ​​​​​​In addition to the above, as the oxide semiconductor applied to the oxide semiconductor layer, there are also In-Sn-Zn- O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, S n-Al-Zn-O system, In-Zn-O system, In-Ga-O system, Sn-Zn-O system, Al -Zn-O system, In-O system, Sn-O system, Zn-O system oxide semiconductors can be applied. Further, silicon oxide may be included in the oxide semiconductor layer. By including silicon oxide (SiOx (X>0)) that inhibits crystallization in the oxide semiconductor layer, when heat treatment is performed after the formation of the oxide semiconductor layer during the manufacturing process, crystallization can be suppressed. Note that the oxide semiconductor layer is preferably in an amorphous state and may be partially crystallized.

[0034] The oxide semiconductor is preferably an oxide semiconductor containing In, and more preferably an oxide semiconductor containing In and Ga. In order to make the oxide semiconductor layer of type I (intrinsic), dehydration or dehydrogenation and the formation of an oxide insulating film in contact with the oxide semiconductor are effective.

[0035] In addition, since thin film transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for driving circuit protection on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor.

[0036] Further, the gate insulating layer and the oxide semiconductor film may be continuously processed (also referred to as continuous processing, in-situ process, continuous film formation) without exposing them to the atmosphere. By continuously processing without exposing them to the atmosphere, the interface between the gate insulating layer and the oxide semiconductor film is free from water and ​​​​​​​It can be formed without being contaminated by atmospheric components such as hydrocarbons and impurities floating in the atmosphere, so that variations in thin film transistor characteristics can be reduced.

[0037] In this specification, continuous processing means that during a series of processes from a first processing step performed by a PCVD method or a sputtering method to a second processing step performed by a PCVD method or a sputtering method, the atmosphere in which the substrate to be processed is placed is always in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without contacting a contaminated atmosphere such as the atmosphere. By performing continuous processing, reattachment of moisture etc. of the cleaned substrate to be processed can be avoided, and processes such as film formation can be performed.

[0038] Performing a series of processes from a first processing step to a second processing step within the same chamber is considered to be within the scope of continuous processing in this specification.

[0039] Also, when performing a series of processes from a first processing step to a second processing step in different chambers, after completing the first processing step, transporting the substrate between the chambers without contacting the atmosphere and performing the second processing is also considered to be within the scope of continuous processing in this specification.

[0040] Note that between the first processing step and the second processing step, there may be a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to a temperature required for the second step, etc., and it is considered to be within the scope of continuous processing in this specification.

[0041] However, processes using liquids such as a cleaning step, wet etching, and resist formation are the first If it is between the first processing step and the second processing step, it is not included in the scope of continuous processing as described in this specification. It is assumed that it does not apply.

Advantages of the Invention

[0042] A thin-film transistor having stable electrical characteristics can be manufactured. Also, a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability can be manufactured. It is possible to manufacture a semiconductor device having a thin-film transistor with good electrical characteristics and high reliability.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed. Also, the present invention is not construed as being limited to the description of the embodiments shown below. be easily understood. Further, the present invention is not to be construed as being limited to the description of the embodiments shown below. be construed as being limited thereto.

[0045] (Embodiment 1) A semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 2.

[0046] FIG. 2(A) is a plan view of a thin film transistor 470 included in the semiconductor device according to the present embodiment, and FIG. 2(B) is a cross-sectional view taken along line C1 - C2 in FIG. 2(A). The thin film transistor 470 is an inverted staggered type thin film transistor, and includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer or drain electrode layers 405a and 405b on a substrate 400 which is a substrate having an insulating surface. Further, covering the thin film transistor 470 layer or drain electrode layers 405a and 405b on a substrate 400 which is a substrate having an insulating surface. Further, covering the thin film transistor 470 An oxide insulating film 407 in contact with the oxide semiconductor layer 403 is provided.

[0047] The oxide semiconductor layer 403 is subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) to reduce impurities such as moisture, which are impurities, at least after the formation of the oxide semiconductor film. This results in a reduction in resistance (an increase in carrier concentration, preferably 1 × 10 / cm 18 / cm 3 or higher). Next, while gradually cooling in an oxygen atmosphere, the oxide insulating film 407 is formed in contact with the oxide semiconductor layer 403. As a result, the resistance increases (the carrier concentration decreases, preferably less than 1 × 10 18 / cm 3 ), and the oxide semiconductor film can be used as a channel formation region.

[0048] Furthermore, after the process of desorbing impurities such as moisture (H2O) by heat treatment for dehydration or dehydrogenation, gradual cooling is performed in an oxygen atmosphere. After heat treatment for dehydration or dehydrogenation and gradual cooling in an oxygen atmosphere, forming an oxide insulating film in contact with the oxide semiconductor layer, etc. to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the reliability of the thin film transistor 470.

[0049] Note that not only within the oxide semiconductor layer 403, but also within the gate insulating layer 402 and at the interfaces between the films provided in contact with the oxide semiconductor layer 403 above and below, specifically, the interface between the gate insulating layer 402 and the oxide semiconductor layer 403, and the interface between the oxide insulating film 407 and the oxide semiconductor layer 403, impurities such as moisture are reduced.

[0050] Also, the source electrode layer or drain electrode layers 405a, 40 ​​​​​​​As 5b, it is formed of a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, and beryllium. Also, an alloy film or the like formed by combining the above-described elements may be laminated.

[0051] As the oxide semiconductor layer 403 including the channel formation region, an oxide material having semiconductor characteristics may be used. Typically, an In-Ga-Zn-O-based non-single crystal is used.

[0052] Figs. 1(A) to (D) show cross-sectional views of the manufacturing process of the thin film transistor 470 shown in Fig. 2.

[0053] In Fig. 1(A), a gate electrode layer 401 is provided on a substrate 400 which is a substrate having an insulating surface. An insulating film serving as an underlayer may be provided between the substrate 400 and the gate electrode layer 401. The underlayer has a function of preventing diffusion of impurity elements from the substrate 400, and can be formed by a laminated structure of one or more films selected from a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon oxynitride nitride film. The material of the gate electrode layer 401 can be formed by using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these, either in a single layer or by lamination.

[0054] For example, as a two-layer laminated structure of the gate electrode layer 401, there is a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or tantalum nitride is laminated on a copper layer, or a two-layer structure of a titanium nitride layer and molybdenum. It is preferable to form a two-layer structure in which it is laminated with a Buden layer. As for the three-layer laminated structure, Tungsten a layer or tungsten nitride, an alloy layer of aluminum and silicon or an aluminum an alloy layer of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated to form a three-layer structure. It is preferable.

[0055] Next, a gate insulating layer 402 is formed on the gate electrode layer 401.

[0056] The gate insulating layer 402 can be formed by using a plasma CVD method, a sputtering method, or the like to form a single layer or a laminated structure of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. For example, by using SiH4, oxygen, and nitrogen as the film-forming gas, a silicon oxynitride layer can be formed by the plasma CVD method. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas.

[0057] In the sputtering method, there are an RF sputtering method that uses a high-frequency power source for the sputtering power source and a DC sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film. In the sputtering method, there are an RF sputtering method that uses a high-frequency power source for the sputtering power source and a DC sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film. In the sputtering method, there are an RF sputtering method that uses a high-frequency power source for the sputtering power source and a DC sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film. In the sputtering method, there are an RF sputtering method that uses a high-frequency power source for the sputtering power source and a DC sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0058] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can also laminate and deposit different material films in the same chamber, or discharge a plurality of types of materials simultaneously in the same chamber to form a film. There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can also laminate and deposit different material films in the same chamber, or discharge a plurality of types of materials simultaneously in the same chamber to form a film. There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can also laminate and deposit different material films in the same chamber, or discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0059] There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber, and an E that uses plasma generated by using microwaves without using glow discharge. There is also a sputtering apparatus that uses a magnetron sputtering method equipped with a magnet mechanism inside the chamber, and an E that uses plasma generated by using microwaves without using glow discharge. There is a sputtering apparatus using the CR sputtering method.

[0060] Also, as a film formation method using the sputtering method, during film formation, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to a substrate during film formation is also available. ring gas component to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to the substrate during film formation. ring method, or a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0061] Next, an oxide semiconductor film is formed on the gate insulating layer 402.

[0062] Note that before forming the oxide semiconductor film by the sputtering method, reverse sputtering is performed by introducing argon gas to generate plasma, and it is preferable to remove particles adhering to the surface of the gate insulating layer 402. Reverse sputtering is a method in which a voltage is applied to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side, and plasma is formed in the vicinity of the substrate to modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, an atmosphere in which oxygen, N2O, etc. are added to the argon atmosphere may be used. Also, an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere may be used. is applied, and plasma is formed in the vicinity of the substrate to modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, an atmosphere in which oxygen, N2O, etc. are added to the argon atmosphere may be used. Also, an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere may be used. may be used. Also, an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere may be used. may be used.

[0063] The oxide semiconductor film is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target. Also, the oxide semiconductor film can be formed by a sputtering method in an inert gas (typically argon) atmosphere, an oxygen atmosphere, or an inert gas (typically argon) and oxygen atmosphere. atmosphere, an oxygen atmosphere, or an inert gas (typically argon) and oxygen atmosphere. atmosphere, or an inert gas (typically argon) and oxygen atmosphere. ring method.

[0064] The gate insulating layer 402 and the oxide semiconductor film are continuously formed without being exposed to the atmosphere. This is also acceptable. By continuously forming a film without exposing it to the atmosphere, the interface can form each laminated interface without being contaminated by atmospheric components such as water and hydrocarbons or impurity elements floating in the atmosphere. Therefore, variations in thin-film transistor characteristics can be reduced.

[0065] The oxide semiconductor film is processed into island-shaped oxide semiconductor layers (first oxide semiconductor layers) by a photolithography process (see Fig. 1(A)).

[0066] After heat-treating the oxide semiconductor layer in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, it is gradually cooled in an oxygen atmosphere (see Fig. 1(B)). By heat-treating the oxide semiconductor layer 430 in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 430 can be removed.

[0067] In the heat treatment, it is preferable that nitrogen or rare gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0068] Moreover, the heat treatment can use a heating method using an electric furnace, a GRTA (Gas Rapid Thermal Anneal) method using heated gas, or an instantaneous heating method such as an LRTA (Lamp Rapid Thermal Anneal) method using lamp light.

[0069] ​​​​​​​​​​​ Here, as one form of the heat treatment of the oxide semiconductor layer 430, a heating method using an electric furnace 601 will be described with reference to FIG. 3.

[0070] FIG. 3 is a schematic diagram of the electric furnace 601. A heater 603 is provided outside the chamber 602 to heat the chamber 602. Also, a susceptor 605 for mounting the substrate 604 is provided in the chamber 602 to carry the substrate 604 into or out of the chamber 602. Further, a gas supply means 606 and an exhaust means 607 are provided in the chamber 602. The gas supply means 606 introduces gas into the chamber 602. Also, the exhaust means 607 exhausts the inside of the chamber 602 or reduces the pressure inside the chamber 602. It is preferable that the temperature rising characteristic of the electric furnace 601 be 0.1 ° C / min or more and 20 ° C / min or less. Also, it is preferable that the temperature falling characteristic of the electric furnace 601 be 0.1 ° C / min or more and 15 ° C / min or less.

[0071] The gas supply means 606 includes a gas supply source 611a, a gas supply source 611b, a pressure regulating valve 612a, a pressure regulating valve 612b, a purifier 613a, a purifier 613b, a mass flow controller 614a, a mass flow controller 614b, a stop valve 615a, and a stop valve 615b. In the present embodiment, it is preferable to provide purifiers 613a and 613b between the gas supply sources 611a and 611b and the chamber 602. By providing the purifiers 613a and 613b, impurities such as water and hydrogen in the gas introduced from the gas supply sources 611a and 611b into the chamber 602 are removed by the purifiers 613a and ​​​​​​​​​​​​​​​By removing it with the purifier 613b, the intrusion of water, hydrogen, etc. into the chamber 602 can be reduced.

[0072] In this embodiment, nitrogen or a noble gas is introduced from the gas supply source 611a into the chamber 602, the inside of the chamber is made into a nitrogen or noble gas atmosphere, and in the chamber 602 heated to 200°C or higher and 600°C or lower, preferably 400°C or higher and 450°C or lower, by heating the oxide semiconductor layer 430 formed on the substrate 604, dehydration or dehydrogenation of the oxide semiconductor layer 430 can be performed.

[0073] Alternatively, under reduced pressure by the exhaust means, in the chamber 602 heated to 200°C or higher and 600°C or lower, preferably 400°C or higher 450°C or lower, by heating the oxide semiconductor layer 430 formed on the substrate 604, dehydration or dehydrogenation of the oxide semiconductor layer 430 can be performed.

[0074] Next, the introduction of nitrogen or a noble gas from the gas supply source 611a into the chamber 602 is stopped and the heater is turned off. Next, oxygen is introduced from the gas supply source 611b into the chamber 6 02, and the chamber 602 of the heating device is gradually cooled. That is, the inside of the chamber 60 2 is made into an oxygen atmosphere, and the substrate 604 is gradually cooled. Here, it is preferable that the oxygen introduced into the chamber 602 from the gas supply source 611b does not contain impurities such as water and hydrogen. Alternatively, the purity of the oxygen introduced into the chamber 602 from the gas supply source 611b is 6N (99.9999%) or less, preferably 7N (99.99999%) or less (that is, the impurity concentration in oxygen is 1 ppm, preferably 0.1 ppm). It is preferable that the oxide semiconductor The conductor layer is gradually heated in an inert gas atmosphere or under reduced pressure and then cooled in an oxygen atmosphere. Cooling reduces the resistance (increases the carrier concentration, preferably 1×10 18 / cm 3 (End) In this way, the resistance of the oxide semiconductor layer 431 (second oxide semiconductor layer) can be reduced.

[0075] As a result, the reliability of the thin film transistor to be formed later can be improved.

[0076] In addition, when the heat treatment is performed under reduced pressure, oxygen is flowed into the chamber 602 after the heat treatment. The pressure can then be returned to atmospheric pressure and cooled.

[0077] Also, oxygen is introduced into the chamber 602 from the gas supply source 611b, and at the same time, helium, Introduce one or both of a rare gas such as neon or argon and nitrogen into the chamber 602. You may do so.

[0078] After the substrate 604 in the chamber 602 of the heating device was cooled to 300° C., 4 may be moved to a room temperature atmosphere. This can reduce the cooling time of the substrate 604. can.

[0079] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, nitrogen or a rare gas is filled and the temperature is 200°C to 600°C. In the first chamber, which is preferably heated to 400° C. or higher and 450° C. or lower, The oxide semiconductor layer on the plate is heated. Then, the plate is transferred to a transfer chamber into which nitrogen or a rare gas is introduced. The above-mentioned oxidizing agent is placed in a second chamber which is filled with oxygen and is at a temperature of 100° C. or less, preferably at room temperature. The heat-treated substrate is then moved and cooled. Through these steps, throughput is improved. It can be done.

[0080] In addition, the heat treatment of the oxide semiconductor layer in an inert gas atmosphere or under reduced pressure can also be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor layer 430 in an inert gas atmosphere or under reduced pressure, slow cooling is performed in an oxygen atmosphere from room temperature to less than 100 °C, the substrate is taken out of the heating device, and a photolithography process is performed. It can also be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor layer 430 in an inert gas atmosphere or under reduced pressure, slow cooling is performed in an oxygen atmosphere from room temperature to less than 100 °C, the substrate is taken out of the heating device, and a photolithography process is performed. In addition, the heat treatment of the oxide semiconductor layer in an inert gas atmosphere or under reduced pressure can also be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor layer 430 in an inert gas atmosphere or under reduced pressure, slow cooling is performed in an oxygen atmosphere from room temperature to less than 100 °C, the substrate is taken out of the heating device, and a photolithography process is performed. In addition, the heat treatment of the oxide semiconductor layer in an inert gas atmosphere or under reduced pressure can also be performed on the oxide semiconductor film before it is processed into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor layer 430 in an inert gas atmosphere or under reduced pressure, slow cooling is performed in an oxygen atmosphere from room temperature to less than 100 °C, the substrate is taken out of the heating device, and a photolithography process is performed. It can be done.

[0081] In addition, the state of the oxide semiconductor layer 430 after the heat treatment in an inert gas atmosphere or under reduced pressure is preferably an amorphous state, but it may be partially crystallized. In addition, the state of the oxide semiconductor layer 430 after the heat treatment in an inert gas atmosphere or under reduced pressure is preferably an amorphous state, but it may be partially crystallized.

[0082] Next, a conductive film is formed on the gate insulating layer 402 and the oxide semiconductor layer 431.

[0083] As the material of the conductive film, there are elements selected from Al, Cr, Ta, Ti, Mo, W, alloys containing the above-described elements as components, alloys combining the above-described elements, etc. As the material of the conductive film, there are elements selected from Al, Cr, Ta, Ti, Mo, W, alloys containing the above-described elements as components, alloys combining the above-described elements, etc.

[0084] In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. Heat-resistant conductive materials that can be combined with Al include elements selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), alloys containing the above-described elements as components, alloys combining the above-described elements, or nitrides containing the above-described elements as components. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material. In addition, when a heat treatment is performed after the formation of the conductive film, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment. Since single Al has poor heat resistance and problems such as being easily corroded, it is preferably formed in combination with a heat-resistant conductive material.

[0085] Etch the oxide semiconductor layer 431 and the conductive film to form an oxide semiconductor layer 432 and a source electrode layer or drain electrode layers 405a, 405b (see Fig. 1(C)). Note that only a part of the oxide semiconductor layer 432 is etched to form an oxide semiconductor layer 432 having a groove portion (recess).

[0086] Form an oxide insulating film 407 in contact with the oxide semiconductor layer 432. The oxide insulating film 407 can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the oxide insulating film 407, such as the CVD method or the sputtering method. Here, the oxide insulating film 407 is formed by using the sputtering method. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film in which moisture and OH - are reduced and these are blocked from entering from the outside. Typically, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is used.

[0087] In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the oxide insulating film 407. The substrate temperature during film formation may be from room temperature to 300°C or lower. In this embodiment, it is 100 °C. The film formation of the silicon oxide film by the sputtering method can be carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by the sputtering method in an atmosphere of oxygen and nitrogen using a silicon target.

[0088] ​​A sputtering method, a PCVD method, or the like is applied to the oxide semiconductor layer 432 having a low resistance. When the oxide insulating film 407 is formed, the oxide semiconductor layer 432 has a low resistance. In addition, the region in contact with the oxide insulating film 407 is made to have a high resistance (the carrier concentration is reduced, preferably 1×10 18 / cm 3 The semiconductor layer can be made to have a high resistance. In the device manufacturing process, heating in an inert gas atmosphere (or reduced pressure) and oxygen atmosphere The carrier concentration of the oxide semiconductor layer is increased or decreased by slow cooling at room temperature and forming an oxide insulating film. It is important that the oxide semiconductor layer 432 is an oxide semiconductor having a high resistance oxide semiconductor region. Through the above steps, a thin-film transistor is obtained. A star 470 can be fabricated (see FIG. 1(D)).

[0089] By performing the heat treatment for the dehydration treatment or the dehydrogenation treatment, After reducing the impurities (HO, H, OH, etc.) contained and increasing the carrier concentration, oxygen After the gradual cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer. The carrier concentration in the oxide semiconductor layer is reduced, and the reliability of the thin film transistor 470 is improved. It can be improved.

[0090] After the oxide insulating film 407 is formed, Then, the thin film transistor 470 is subjected to a heat treatment (preferably at 150° C. or higher and lower than 350° C.). For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. In this case, the oxide semiconductor layer 432 is heated in contact with the oxide insulating film 407. , variations in the electrical characteristics of the thin film transistor 470 can be reduced.

[0091] (Embodiment 2) In this embodiment, a semiconductor device and a method of manufacturing the semiconductor device different from those of Embodiment 1 will be described with reference to FIGS. 8 and and FIG. 9. The same parts or parts having the same functions as those in Embodiment 1, and processes can be carried out in the same manner as in Embodiment 1, and repeated descriptions will be omitted.

[0092] FIG. 9(A) is a plan view of the thin film transistor 460 included in the semiconductor device shown in this embodiment, and FIG. 9(B) is a cross-sectional view taken along line D1-D2 in FIG. 9(A). The thin film transistor 460 is a bottom gate type thin film transistor, and on a substrate 450 which is a substrate having an insulating surface, a gate electrode layer 451, a gate insulating layer 452, source electrode layers or drain electrode layers 455a, 455b, and an oxide semiconductor layer 453 are included. Further, an oxide insulating film 457 that covers the thin film transistor 4 60 and is in contact with the oxide semiconductor layer 453 is provided. The oxide semiconductor layer 453 uses an In-Ga-Zn-O based non-single crystal.

[0093] The gate insulating layer 452 exists in all regions including the thin film transistor 460, and a gate electrode layer 451 is provided between the gate insulating layer 452 and the substrate 450 which is a substrate having an insulating surface. On the gate insulating layer 452, source electrode layers or drain electrode layers 455a, 455b are provided. Then, an oxide semiconductor layer 453 is provided on the gate insulating layer 452 and the source electrode layers or drain electrode layers 455a, 455b. Further, although not shown, on the gate insulating layer 452, source electrode layers or drain layers are provided, and on the source electrode layers or drain electrode layers 455a, 455b, an oxide semiconductor layer 453 is provided. In addition to the n-type electrode layers 455a and 455b, a wiring layer is provided, and the wiring layer extends outside the outer peripheral portion of the oxide semiconductor layer 453. It extends outside the outer peripheral portion.

[0094] The oxide semiconductor layer 453 is subjected to a heat treatment (heat treatment for dehydration or dehydrogenation) to reduce impurities such as moisture, which is an impurity, at least after the formation of the oxide semiconductor film, and is slowly cooled in an oxygen atmosphere. It is reduced in resistance (the carrier concentration increases, preferably 1×10 / cm 18 / cm 3 or more ) and then an oxide insulating film 457 is formed in contact with the oxide semiconductor layer 453, resulting in an increase in resistance (the carrier concentration decreases, preferably less than 1×10 18 / cm 3 ), and the oxide semiconductor film can be used as a channel formation region. Furthermore, after the process of desorbing impurities such as moisture (H2O) by heat treatment for dehydration or dehydrogenation, slow cooling is performed in an oxygen atmosphere. After heat treatment for dehydration or dehydrogenation and slow cooling in an oxygen atmosphere, forming an oxide insulating film in contact with the oxide semiconductor layer, etc.

[0095] to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the reliability of the thin film transistor 460. After going through the process of desorbing impurities such as moisture (H2O) by heat treatment for dehydration or dehydrogenation, slow cooling is performed in an oxygen atmosphere. After heat treatment for dehydration or dehydrogenation and slow cooling in an oxygen atmosphere, forming an oxide insulating film in contact with the oxide semiconductor layer, etc. to reduce the carrier concentration of the oxide semiconductor layer leads to an improvement in the reliability of the thin film transistor 460. Furthermore, as the source electrode layer or drain electrode layer 455a, 45 5b in contact with the oxide semiconductor layer 453, a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium is used.

[0096] In addition, as the source electrode layer or drain electrode layer 455a, 45 5b in contact with the oxide semiconductor layer 453, a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium is used. It is made of a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium.

[0097] Figures 8(A) to (D) show cross-sectional views of the manufacturing process of the thin film transistor 460 shown in Figure 9. .

[0098] A gate electrode layer 451 is provided on a substrate 450 having an insulating surface. Note that an insulating film serving as an underlayer film may be provided between the substrate 450 and the gate electrode layer 451. The material of the gate electrode layer 45 1 can be formed in the same manner as the gate electrode layer 401 shown in Embodiment 1.

[0099] A gate insulating layer 452 is formed on the gate electrode layer 451. The gate insulating layer 452 can be formed in the same manner as the gate insulating layer 402 shown in Embodiment 1.

[0100] A conductive film is formed on the gate insulating layer 452 and processed into island-shaped source electrode layers or drain electrode layers 455a and 455b by a photolithography process (see Fig. 8(A)). The source electrode layers or drain electrode layers 455a and 455b can be formed in the same manner as the source electrode layer or drain electrode layers 405a and 450b shown in Embodiment 1.

[0101] Next, an oxide semiconductor film is formed on the gate insulating layer 452 and the source electrode layers or drain electrode layers 455a and 455b, and an island-shaped oxide semiconductor layer 48 3 (first oxide semiconductor layer) is formed by a photolithography process (see Fig. 8(B)). Since the oxide semiconductor layer 483 serves as a channel formation region, it is formed in the same manner as the oxide semiconductor film

[0102] in Embodiment 1. It is formed in the same manner.

[0103] Note that before forming the oxide semiconductor layer 483 by sputtering, reverse sputtering is performed to introduce argon gas to generate plasma, and it is preferable to remove particles adhering to the surface of the gate insulating layer 452.

[0104] After performing a heat treatment for dehydration or dehydrogenation on the oxide semiconductor layer 483, slow cooling is carried out in an oxygen atmosphere. As the heat treatment for dehydration or dehydrogenation, a heat treatment is carried out at 200°C or higher and 6 00°C or lower, preferably 400°C or higher and 450°C or lower, in an inert gas atmosphere ( nitrogen, or helium, neon, argon, etc.) or under reduced pressure. The oxide semiconductor layer 4 83 can be made into a low-resistance ( (the carrier concentration increases, preferably 1×10 18 / cm 3 or higher) and low-resistance oxide semiconductor layer 484 (second oxide semiconductor layer) by the heat treatment in the above atmosphere and slow cooling in an oxygen atmosphere (see Fig. 8(C)).

[0105] In the heat treatment for dehydration or dehydrogenation, it is preferable that nitrogen or a noble gas such as helium, neon, or a argon does not contain water, hydrogen, etc. Alternatively, the purity of the nitrogen or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99. 9999%) or higher, preferably 7N (99.99999%) or higher, (that is, the impurity concentration is 1 ppm or lower, preferably 0.1ppm or lower).

[0106] Also, the heat treatment of the oxide semiconductor layer in an inert gas atmosphere or under reduced pressure and the slow cooling in an oxygen atmosphere can be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, after the heat treatment of the oxide semiconductor film in an inert gas atmosphere or under reduced pressure, slow cooling is carried out in an oxygen atmosphere from room temperature to less than 100°C, the substrate is taken out of the heating apparatus, and a photolithography process is performed.

[0107] ​​​Next, an oxide is formed by sputtering or PCVD in contact with the oxide semiconductor layer 484. In this embodiment, an insulating film 457 is formed as an oxide insulating film having a film thickness of 300 nm of a silicon oxide film. The substrate temperature during film formation is preferably room temperature or higher and 300 °C or lower, and is set to 100 °C in this embodiment. When an oxide insulating film 457, which is a silicon oxide film, is formed by sputtering in contact with the oxide semiconductor layer 484 with reduced resistance, at least in the oxide semiconductor layer 484 with reduced resistance, the region in contact with the oxide insulating film 457, which is at least a silicon oxide film, becomes highly resistive (the carrier concentration decreases, preferably less than 1 × 10 / cm ), and a highly resistive oxide semiconductor region can be formed. In the manufacturing process of the semiconductor device, 18 / cm 3 not satisfied). It is important to increase or decrease the carrier concentration of the oxide semiconductor layer by heating in an inert gas atmosphere (or under reduced pressure), slow cooling in an oxygen atmosphere, and forming an oxide insulating film. The oxide semiconductor layer 484 becomes an oxide semiconductor layer 453 (the third oxide semiconductor layer) having a highly resistive oxide semiconductor region, and a thin film transistor 460 can be manufactured (see FIG. 8(D ). ). By performing a heat treatment for dehydration or dehydrogenation treatment, impurities (such as H2O, H, and OH) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed in an oxygen atmosphere. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 460. )).

[0108] By performing a heat treatment for dehydration or dehydrogenation treatment, impurities (such as H2O, H, and OH) contained in the oxide semiconductor layer are reduced to increase the carrier concentration, and then slow cooling is performed in an oxygen atmosphere. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 460. After reducing the impurities (such as H2O, H, and OH) contained in the oxide semiconductor layer and increasing the carrier concentration by performing a heat treatment for dehydration or dehydrogenation treatment, slow cooling is performed in an oxygen atmosphere. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 460. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 460. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 460. can be improved.

[0109] Also, after forming the silicon oxide film to be the oxide insulating film 457, a heat treatment (preferably 150 °C or higher and less than 350 °C) may be performed on the thin film transistor 460 in a nitrogen atmosphere or in an air atmosphere (in the air). For example, a heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. The oxide semiconductor layer 453 will be heated in a state in contact with the oxide insulating film 457. By performing this heat treatment, the variation in the electrical characteristics of the thin film transistor 460 can be reduced.

[0110] Also, this embodiment can be freely combined with Embodiment 1.

[0111] (Embodiment 3) The manufacturing process of the semiconductor device including the thin film transistor will be described with reference to FIGS. 10 to 13.

[0112] In FIG. 10(A), a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used as the light-transmissive substrate 100.

[0113] Next, after forming the conductive layer over the entire surface of the substrate 100, a first photolithography process is performed to form a resist mask, and unnecessary portions of the conductive layer are removed by etching to form wiring and electrodes (gate wiring including the gate electrode layer 101, capacitor wiring 108, and first terminal 121). At this time, etching is performed so that a tapered shape is formed at least at the end of the gate electrode layer 101.

[0114] For the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion, the materials shown for the gate electrode layer 401 shown in Embodiment 1 can be appropriately used. Also, the ​​​​​When forming the gate electrode layer 101 with a heat-resistant conductive material, titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), Nd (neodymium), a), scandium (Sc), an element selected from these, or an alloy containing the above-mentioned elements as components, or an alloy film combining the above-mentioned elements, or a nitride containing the above-mentioned elements as components is used. Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode layer 101. The gate insulating layer 102 is formed using a sputtering method, a PCVD method, etc., with a film thickness of 50 to 250 nm.

[0115] For example, a silicon oxide film is used as the gate insulating layer 102 and formed with a thickness of 100 nm by sputtering. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, and a tantalum oxide film can be used and formed as a single layer or a laminated structure composed of these materials. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen.

[0116] For example, a silicon oxide film is used as the gate insulating layer 102 and formed with a thickness of 100 nm by sputtering. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film, and other insulating films such as a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, and a tantalum oxide film can be used and formed as a single layer or a laminated structure composed of these materials. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen.

[0117] Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Next, an oxide semiconductor film (In-Ga-Zn-O-based non-single crystal film) is formed over the gate insulating layer 102. After forming the gate insulating layer 102 by sputtering, forming the In-Ga-Zn-O-based non-single crystal film without exposing it to the atmosphere is useful in that it does not deposit particles or moisture on the interface between the gate insulating layer and the semiconductor film. Here, a metal oxide target (In-Ga-Zn-O-based metal oxide target (In2O3:Ga2O3:ZnO = 1:1:1)) containing In, Ga, and Zn with a diameter of 8 inches is used, with the distance between the substrate and the target being 170 mm, the pressure being 0.4 Pa, the DC power supply being 0.5 kW, and only oxygen. Film formation is carried out only in an argon atmosphere or in an atmosphere of argon and oxygen. Note that pulsed direct current (DC) using a power supply is preferable because particles can be reduced and the film thickness distribution becomes uniform. In -The film thickness of the Ga-Zn-O-based polycrystalline film is set to 5 nm to 200 nm. As the oxide semiconductor film and using an In-Ga-Zn-O-based metal oxide target, a film with a thickness of 50 nm of an In-Ga-Zn-O-based polycrystalline film is formed by sputtering.

[0118] Next, a second photolithography process is performed to form a resist mask, and the oxide semiconductor film is etched. For example, by wet etching using a solution of phosphoric acid, acetic acid, and nitric acid mixed together, unnecessary portions of the oxide semiconductor film are removed to form an oxide semiconductor layer 133 (see Fig. 10 (A)). Note that the etching here is not limited to wet etching, and dry etching may also be used.

[0119] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0120] Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material is purified, and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced .

[0121] Note that the etching conditions (etching solution, etching time, temperature, etc.) are appropriately adjusted according to the material so that etching can be performed into a desired processed shape. ​​​​​

[0122] As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) is preferable.

[0123] In addition, as the etching gas used for dry etching, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoro methane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), a gas obtained by adding a rare gas such as helium (He) or argon (Ar) to these gases, etc. can be used.

[0124] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method, an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method, etc. can be used. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately adjusted so that the desired processing shape can be etched.

[0125] Next, a heat treatment for dehydration or dehydrogenation of the oxide semiconductor layer 133 is performed. The oxide semiconductor layer 133 is heat-treated under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then gradually cooled under an oxygen atmosphere.

[0126] The heat treatment is preferably performed at 200°C or higher. For example, a heat treatment at 450°C for 1 hour is performed under a nitrogen atmosphere. After the heat treatment under this nitrogen atmosphere, by gradually cooling under an oxygen atmosphere, ​​​ , the oxide semiconductor layer 133 has a reduced resistance (the carrier concentration increases, preferably 1×10 18 / cm 3 or higher), and the conductivity increases. Thus, a low-resistance oxide semiconductor layer 134 is formed (see Fig. 10(B)). The electrical conductivity of the oxide semiconductor layer 134 is 1×10 -1 S / cm or higher and preferably 1×10 2 S / cm or lower.

[0127] Next, a conductive film 132 made of a metal material is formed on the oxide semiconductor layer 134 by sputtering or vacuum evaporation (see Fig. 10(C)).

[0128] As the material of the conductive film 132, the same materials as the source electrode layer or drain electrode layer 4 05a, 405b shown in Embodiment 1 can be appropriately used.

[0129] When heat treatment is performed after the formation of the conductive film 132, it is preferable to endow the conductive film with heat resistance to withstand this heat treatment.

[0130] Next, a third photolithography process is performed to form a resist mask, and unnecessary portions of the conductive film 132 are removed by etching to form the source electrode layer or drain electrode layer 105a, 10 5b, and the second terminal 122 (see Fig. 10(D)). Wet etching or dry etching is used as the etching method at this time. For example, when an aluminum film or an aluminum alloy film is used as the conductive film 132, wet etching using a solution mixed with phosphoric acid, acetic acid, and nitric acid can be performed. Also, wet etching using hydrogen peroxide ammonia (hydrogen peroxide : ammonia: water = 5:2:2) can be used to etch the conductive film 13 ​Etching 2 to form the source electrode layer or the drain electrode layer 105a, 105b is also acceptable. In this etching step, a part of the exposed region of the oxide semiconductor layer 134 is also etched to become the oxide semiconductor layer 135. Therefore, the oxide semiconductor layer 135 between the source electrode layer or the drain electrode layer 105 a, 105b becomes a region with a thin film thickness. In FIG. 10(D), since the etching of the source electrode layer or the drain electrode layer 105a, 105b and the oxide semiconductor layer 135 is performed at once by dry etching, the ends of the source electrode layer or the drain electrode layer 105a, 105b and the oxide semiconductor layer 135 coincide and have a continuous structure.

[0131] Also, in this third photolithography step, the second terminal 122 made of the same material as the source electrode layer or the drain electrode layer 105a, 105b is left at the terminal portion. Note that the second terminal 122 is electrically connected to the wiring (the wiring including the source electrode layer or the drain electrode layer 105a, 105b).

[0132] In addition, when using a resist mask having regions with a plurality (typically two types) of thicknesses formed by a multi-tone mask, the number of resist masks can be reduced, so that the process can be simplified and the cost can be reduced.

[0133] Next, the resist mask is removed, and a protective insulating layer 107 covering the gate insulating layer 102, the oxide semiconductor layer 103, and the source electrode layer or the drain electrode layer 105a, 105b is formed. The protective insulating layer 107 is formed using a silicon oxynitride film formed by the PCVD method. The oxide semiconductor layer 13 provided between the source electrode layer or the drain electrode layer 105a, 105b 5 and the silicon oxynitride film which is the protective insulating layer 107 are provided in contact with each other. As a result, the region of the oxide semiconductor layer 135 in contact with the protective insulating layer 107 becomes highly resistive (carrier concentration is reduced, preferably by 1×10 18 / cm 3 (less than 1000 MHz) and the high-resistance channel formation region It is possible to form the oxide semiconductor layer 103 having the above structure (see FIG. 11A).

[0134] Next, after the protective insulating layer 107 is formed, heat treatment may be performed. The heating process may be carried out in an air or nitrogen atmosphere at a temperature of 150° C. or higher and lower than 350° C. When the oxide semiconductor layer 103 is heated in contact with the protective insulating layer 107, Furthermore, the resistance of the oxide semiconductor layer 103 can be increased, thereby improving the electrical characteristics of the transistor. In addition, the variation in electrical characteristics can be reduced.

[0135] Through the above steps, the thin film transistor 170 can be manufactured.

[0136] Next, a fourth photolithography process is performed to form a resist mask, and a protective insulating layer 107 The gate insulating layer 102 is etched to form a contact layer that reaches the drain electrode layer 105b. A hole 125 is formed. Also, a contact that reaches the second terminal 122 is formed by etching here. A contact hole 127 and a contact hole 126 reaching the first terminal 121 are also formed. A cross-sectional view at this stage is shown in FIG.

[0137] Next, the resist mask is removed, and then a transparent conductive film is formed. The material is indium oxide (In2O3) or indium tin oxide (ITO). It is formed by using a patterning method, a vacuum evaporation method, or the like. The etching process of such a material is performed using a hydrochloric acid-based solution. However, particularly in the etching of ITO, residues are likely to occur. Therefore, in order to improve the etching processability, an indium oxide-zinc oxide alloy (I n2O3―ZnO) may be used as the transparent conductive film.

[0138] Next, a fifth photolithography process is performed to form a resist mask, and unnecessary portions of the transparent conductive film are removed by etching to form the pixel electrode layer 110.

[0139] Also, in this fifth photolithography process, the gate insulating layer 102 and the protective insulating layer 107 in the capacitor portion are used as dielectrics, and a holding capacitor is formed by the capacitor wiring 108 and the pixel electrode layer 110.

[0140] Also, in this fifth photolithography process, the first terminal 121 and the second terminal 1 22 are covered with a resist mask to leave the transparent conductive films 128 and 129 formed in the terminal portion. The transparent conductive films 128 and 129 become electrodes or wirings used for connection with the FPC. The transparent conductive film 128 formed on the first terminal 121 becomes a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 is a connection terminal electrode that functions as an input terminal of the source wiring.

[0141] Next, the resist mask is removed. A cross-sectional view at this stage is shown in FIG. 11(C). Note that a plan view at this stage corresponds to FIG. 12.

[0142] Also, FIGS. 13(A1) and 13(A2) are a plan view of the gate wiring terminal portion at this stage and ​​FIG. 13(A1) and FIG. 13(A2) are sectional views respectively. FIG. 13(A1) corresponds to a sectional view taken along line E1-E2 in FIG. 13(A2). In FIG. 13(A1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(A1), in the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode layer 153 formed of the same material as the source wiring overlap via the gate insulating layer 152 and are electrically connected by the transparent conductive film 155. Note that the portion where the transparent conductive film 128 and the first terminal 121 shown in FIG. 11(C) are in contact corresponds to the portion where the transparent conductive film 155 and the first terminal 151 in FIG. 13(A1) are in contact. In FIG. 13(A1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(A1), in the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode layer 153 formed of the same material as the source wiring overlap via the gate insulating layer 152 and are electrically connected by the transparent conductive film 155. Note that the portion where the transparent conductive film 128 and the first terminal 121 shown in FIG. 11(C) are in contact corresponds to the portion where the transparent conductive film 155 and the first terminal 151 in FIG. 13(A1) are in contact. In FIG. 13(A1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(A1), in the terminal portion, the first terminal 151 formed of the same material as the gate wiring and the connection electrode layer 153 formed of the same material as the source wiring overlap via the gate insulating layer 152 and are electrically connected by the transparent conductive film 155. Note that the portion where the transparent conductive film 128 and the first terminal 121 shown in FIG. 11(C) are in contact corresponds to the portion where the transparent conductive film 155 and the first terminal 151 in FIG. 13(A1) are in contact. In FIG. 13(A1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal.

[0143] Also, FIGS. 13(B1) and 13(B2) respectively show a plan view and a sectional view of a source wiring terminal portion different from the source wiring terminal portion shown in FIG. 11(C). Also, FIG. 13(B1) corresponds to a sectional view taken along line F1-F2 in FIG. 13(B2). In FIG. 13(B1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(B1), in the terminal portion, the electrode layer 156 formed of the same material as the gate wiring overlaps below the second terminal 150 electrically connected to the source wiring via the gate insulating layer 102. The electrode layer 156 is not electrically connected to the second terminal 150. If the electrode layer 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 150 is electrically connected to the transparent conductive film 155 through the opening of the protective insulating layer 154. In FIG. 13(B1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(B1), in the terminal portion, the electrode layer 156 formed of the same material as the gate wiring overlaps below the second terminal 150 electrically connected to the source wiring via the gate insulating layer 102. The electrode layer 156 is not electrically connected to the second terminal 150. If the electrode layer 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the second terminal 150 is electrically connected to the transparent conductive film 155 through the opening of the protective insulating layer 154. In FIG. 13(B1), the transparent conductive film 155 formed on the protective insulating layer 154 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 13(B1), in the terminal portion, the electrode layer 156 formed of the same material as the gate wiring overlaps below the second terminal 150 electrically connected to the source wiring via the gate insulating layer 102. The electrode layer 156 is not electrically connected to the second terminal 150. If the electrode layer 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed.

[0144] A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. . Also, in the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal may be set to any number, and the implementer may appropriately determine it.

[0145] In this way, through five photolithography processes, using five photomasks, a pixel thin film transistor portion having a thin film transistor 170 with a bottom gate type staggered structure can be completed. Then, by arranging these in a matrix corresponding to individual pixels to form a pixel portion, it can be used as one substrate for manufacturing an active matrix type display device. In this specification, for convenience, such a substrate is referred to as an active matrix substrate. When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. A common electrode electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the

[0146] terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, such as GND, 0V, etc.

[0147] Further, without providing a capacitor wiring, a holding capacitor may be formed by overlapping a pixel electrode with a gate wiring of an adjacent pixel through a protective insulating layer and a gate insulating layer.

[0148] ​​​​​ In an active matrix type liquid crystal display device, a display pattern is formed on the screen by driving pixel electrodes arranged in a matrix. Specifically, a voltage is applied between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, and the optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed, and this optical modulation is recognized by the observer as the display pattern.

[0149] In the video display of a liquid crystal display device, since the response of the liquid crystal molecules themselves is slow, there are problems such as afterimages and blurring of the video. To improve the video characteristics of the liquid crystal display device, there is a driving technique called so-called black insertion in which all-black display is performed every other frame.

[0150] Alternatively, a driving technique called so-called double-speed driving, in which the normal vertical synchronization frequency is increased to 1.5 times or 2 times or more to improve the video characteristics, may be used.

[0151] In addition, to improve the video characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as the backlight, and there is also a driving technique in which each light source constituting the surface light source is independently driven in an intermittent lighting manner within one frame period. As the surface light source, three or more types of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be independently controlled, the light emission timing of the LEDs can be synchronized with the switching timing of the optical modulation of the liquid crystal layer. This driving technique can turn off the LEDs partially, so that in the case of video display where the ratio of the black display area occupying one screen is large, the effect of reducing power consumption can be achieved.

[0152] ​​​​​​​​​​​​By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0153] The n-channel transistor disclosed in this specification has an oxide semiconductor film as a channel formation region. These drive technologies can be combined due to their good dynamic characteristics. do.

[0154] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of an organic light-emitting element In order to set the low power supply potential, for example GND or 0V, the cathode is connected to the terminal A fourth terminal is provided for setting a potential, for example, GND, 0V, etc. When manufacturing a display device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0155] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, the heat treatment for dehydration or dehydrogenation removes the moisture, which is an impurity, In order to reduce these and increase the purity of the oxide semiconductor film, the dew point in the film formation chamber has been lowered. The electrical properties are excellent without using a special sputtering device or an ultra-high purity metal oxide target. A semiconductor device having a good and reliable thin film transistor can be manufactured.

[0156] The oxide semiconductor layer in the channel formation region is a high resistance region, so that the electrical resistance of the thin film transistor is The characteristics are stabilized and the increase in the off-current can be prevented. Therefore, the electrical characteristics are excellent. Therefore, it is possible to obtain a semiconductor device having a thin film transistor with high reliability.

[0157] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0158] (Embodiment 4) In a display device, which is an example of a semiconductor device, at least a part of a driver circuit and a An example of manufacturing a thin film transistor disposed in a pixel portion will be described below.

[0159] The thin film transistor disposed in the pixel portion is formed according to any one of the first to third embodiments. Since the thin film transistors shown in the first to third embodiments are n-channel TFTs, the Of these, a part of the driver circuit that can be configured with n-channel TFTs is a thin-film transistor in the pixel area. The transistor is formed on the same substrate.

[0160] FIG. 1 is a block diagram of an active matrix liquid crystal display device, which is an example of a semiconductor device. The display device shown in FIG. 19(A) is a display device having a display element on a substrate 5300. A pixel portion 5301 having a plurality of pixels, a scanning line driver circuit 5302 for selecting each pixel, and a signal line driver circuit 5303 for controlling input of a video signal to the pixel.

[0161] The thin film transistors described in any of the first to third embodiments are n-channel TFTs. A signal line driver circuit configured with a channel type TFT will be described with reference to FIG.

[0162] The signal line driver circuit shown in FIG. 20 includes a driver IC 5601 and a group of switches 5602_1 to 5602_56. 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613 and a wiring 56 Each of the switch groups 5602_1 to 5602_M includes It has a first thin-film transistor 5603a, a second thin-film transistor 5603b, and a third thin-film transistor 5603c.

[0163] The driver IC 5601 is connected to a first wiring 5611, a second wiring 5612, a third wiring 5613 and wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5 621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to the first thin-film transistor 5603a, the second thin-film transistor 5603b, and the third thin-film tran sistor 5603c and is connected to three signal lines. For example, the wiring 5621 _J (any one of the wirings 5621_1 to 5621_M) in the J-th column is connected to the signal lines Sj-1, signal line Sj, and signal line S through the first thin-film transistor 5603a, the second thin-film transistor 5603b, and the third thin-film transistor 5603c included in the switch group 5602 _J and is connected to the signal lines Sj + 1.

[0164] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0165] Note that it is desirable that the driver IC 5601 is formed on a single-crystal substrate. Further it is desirable that the switch groups 5602_1 to 5602_M are formed on the same substrate as the pixel portion. Therefore, it is advisable to connect the driver IC 5601 and the switch groups 5602_1 to 5602_ M via an FPC or the like.

[0166] ​​ Next, with reference to the timing chart of FIG. 21, the operation of the signal line driving circuit shown in FIG. 20 will be described. Note that the timing chart of FIG. 21 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 20 operates in the same manner as in FIG. 21 even when the scanning lines of other rows are selected. Note that the timing chart of FIG. 21 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 21 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1.

[0167] Note that the timing chart of FIG. 21 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 21 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. Note that the timing chart of FIG. 21 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. shown.

[0168] Note that the timing chart of FIG. 21 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 21 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. Note that the timing chart of FIG. 21 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column. shown. shown.

[0169] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the second sub-selection period T2 is Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, and the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. The video signal to be input is input to the signal line Sj, and in the third sub-selection period T3, it is input to the wiring 5621 _J. The video signal to be input is input to the signal line Sj + 1. Further, in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_ J are respectively set as Data_j - 1, Data_j, and Data_j + 1.

[0170] As shown in FIG. 21, in the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j - 1 input to the wiring 5621_J is input to the signal line Sj - 1 through the first thin film transistor 5603a. In the second sub-selection period T2 , the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b . In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j + 1 input to the wiring 5621_J is input to the signal line Sj + 1 through the third thin film transistor 5603c.

[0171] From the above, the signal line driving circuit in FIG. 20 divides one gate selection period into three, so that a video signal is input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driver circuit of FIG. The number of connections between the substrate on which the pixel area is formed and the substrate on which the pixel area is formed is reduced to about one-third of the number of signal lines. By reducing the number of connections to about one third, the signal line driver circuit of FIG. This can improve productivity and yield.

[0172] As shown in FIG. 20, one gate selection period is divided into multiple sub-selection periods, and multiple sub-selection periods are During each selection period, a video signal is input from one line to each of multiple signal lines. As long as this can be achieved, the arrangement, number, driving method, etc. of the thin film transistors are not limited.

[0173] For example, three or more signal lines are connected to one wiring during each of three or more sub-selection periods. When a video signal is input to each of them, a thin film transistor and a thin film transistor are controlled. However, it is necessary to divide one gate selection period into four or more sub-selection periods. Therefore, one gate selection period is divided into two. is preferably divided into three sub-selection periods.

[0174] As another example, as shown in the timing chart of FIG. 22, one selection period is precharged. The first sub-selection period T1, the second sub-selection period T2, and the third selection period T3 are Furthermore, in the timing chart of FIG. 22, the i-th scanning line Gi is selected. the timing of turning on and off the first thin film transistor 5603a; a, the on-off timing 5803b of the second thin film transistor 5603b, The on / off timing 5803c of the membrane transistor 5603c and the wiring 562 of the Jth column It shows the signal 5821_J input to 1_J. As shown in FIG. 22, during the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603 b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj- 1, the signal line Sj, and the signal line Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, the Data a_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time the Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 603b are turned off. At this time the Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c. From the above, the signal line driving circuit of FIG. 20 to which the timing chart of FIG. 22 is applied provides a precharge selection period before the sub-selection period, so that the signal line is precharged by ...

[0175] ... ... Therefore, the video signal can be written into the pixels at high speed. In FIG. 22, for components similar to those in FIG. 21, the same reference numerals are used, and detailed descriptions of the same or similar components are omitted.

[0176] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. And, since the transistors of one line of pixels must be turned on all at once, a buffer that can pass a large current is used.

[0177] A form of the shift register used in a part of the scanning line driving circuit will be described with reference to FIGS. 23 and 24.

[0178] FIG. 23 shows the circuit configuration of the shift register. The shift register shown in FIG. 23 is composed of a plurality of flip-flops 5701_1 to 5701_n. Also, a first clock signal, a second clock signal, a start pulse signal, and a reset signal are input and it operates.

[0179] The connection relationship of the shift register in FIG. 23 will be described. The shift register in FIG. 23 is the i-th stage flip-flop 5701_i (among the flip-flops 5701_1 to 5701_n of ​​In any one of them, the first wiring 5501 shown in FIG. 24 is connected to the seventh wiring 5717_i-1, and the second wiring 5502 shown in FIG. 24 is connected to the seventh wiring 5717_i+1. The third wiring 5503 shown in FIG. 24 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 24 is connected to the fifth wiring 5715.

[0180] Also, the fourth wiring 5504 shown in FIG. 24 is connected to the second wiring 5712 in the odd-numbered flip-flops and to the third wiring 5713 in the even-numbered flip-flops. The fifth wiring 5505 shown in FIG. 24 is connected to the fourth wiring 5714.

[0181] However, the first wiring 5501 shown in FIG. 24 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 24 of the nth-stage flip-flop 5701_n is connected to the sixth wiring 5716.

[0182] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the second power supply line, respectively.

[0183] Next, the details of the flip-flop shown in FIG. 23 are shown in FIG. 24. The flip-flop shown in FIG. 24 includes a first thin-film transistor 5571, a second thin-film transistor 5572, a third thin-film transistor 5573, a fourth thin-film transistor 5574, a fifth thin-film transistor 5575, a sixth thin-film transistor 5576, a seventh thin-film transistor 5577, and and has an eighth thin-film transistor 5578. The first thin-film transistor 5571, the second thin-film transistor 5572, the third thin-film transistor 5573, the fourth thin-film transistor 5574, the fifth thin-film transistor 5575, the sixth thin-film transistor 5576, the seventh thin-film transistor 5577, and the eighth thin-film transistor 5578 are n-channel type transistors, and are assumed to be in an on state when the voltage between the gate and the source (Vgs) exceeds the threshold voltage (Vth).

[0184] Next, the connection configuration of the flip-flop shown in FIG. 23 is shown below.

[0185] The first electrode (either the source electrode or the drain electrode) of the first thin-film transistor 5571 is connected to the fifth wiring 5504, and the second electrode (the other of the source electrode or the drain electrode) of the first thin-film transistor 5571 is connected to the third wiring 5503.

[0186] The first electrode of the second thin-film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the second thin-film transistor 5572 is connected to the third wiring 5503.

[0187] The first electrode of the third thin-film transistor 5573 is connected to the fifth wiring 5505, and the second electrode of the third thin-film transistor 5573 is connected to the gate electrode of the second thin-film transistor 5572 and the gate electrode of the third thin-film transistor 5573 is connected to the fifth wiring 5505.

[0188] The first electrode of the fourth thin-film transistor 5574 is connected to the sixth wiring 5506, and the second electrode of the fourth thin-film transistor 5574 is connected to the gate electrode of the second thin-film transistor 5572​​ is connected to, and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0189] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 .

[0190] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth thin film transistor 5576's second electrode is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0191] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh thin film transistor 5577's second electrode is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 . The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 and the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550 1.

[0192] Note that the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 the second electrode of the fifth thin film transistor 5575, the sixth thin film transistor Set the connection point of the second electrode of 5576 and the second electrode of the seventh thin-film transistor 5577 as node 5543. Furthermore, set the connection points of the gate electrode of the second thin-film transistor 5572, the second electrode of the third thin-film transistor 5573, the second electrode of the fourth thin-film transistor 5574, the gate electrode of the sixth thin-film transistor 5576, and the second electrode of the eighth thin-film transistor 5578 as node 5544.

[0193] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be respectively referred to as the first signal line, the second signal, the third signal line, and the fourth signal line. Furthermore, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0194] Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiments 1 to 3. Since the mobility of the n-channel type TFTs shown in Embodiments 1 to 3 is high, it is possible to increase the driving frequency of the driving circuit. Also, since the parasitic capacitance of the n-channel type TFTs shown in Embodiments 1 to 3 is reduced, the frequency characteristics (referred to as f characteristics) are high. For example, the scanning line driving circuit using the n-channel type TFTs shown in Embodiments 1 to 3 can operate at high speed, so it is possible to increase the frame frequency or realize black screen insertion.

[0195] Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or arranging a plurality of scanning line driving circuits, a higher frame frequency can be realized. ​​​​​​​​When arranging a plurality of scanning line driving circuits, when driving the scanning lines of even rows, the scanning line driving circuit is arranged on one side, and the scanning line driving circuit for driving the scanning lines of odd rows is arranged on the opposite side thereby enabling the frame frequency to be increased. Also, when a signal is output to the same scanning line by a plurality of scanning line driving circuits, it is advantageous for reducing the size of the display device.

[0196] Also, when manufacturing an active matrix light-emitting display device which is an example of a semiconductor device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 1 9(B).

[0197] The light-emitting display device shown in FIG. 19(B) has a pixel portion 5401 having a plurality of pixels each including a display element on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 5404 for inputting a signal to a scanning line connected to a selected pixel, and a signal line driving circuit 5403 for controlling the input of a video signal to a signal line connected to a selected pixel.

[0198] When the video signal input to the pixel of the light-emitting display device shown in FIG. 19(B) is in digital format, the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off. Therefore, gradation display can be performed using an area gradation method or a time gradation method. The area gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. Also, the time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light. ​​​

[0199] Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time gradation method than the liquid crystal element. Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel is made to be in a light-emitting or non-light-emitting state in each sub-frame period. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light within one frame period can be controlled by the video signal, and gradation can be displayed.

[0200] In the light-emitting display device shown in FIG. 19(B), when arranging two switching TFTs in one pixel, the signal input to the first scanning line, which is the gate wiring of one of the switching TFTs, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the other switching TFT, is generated by the second scanning line driving circuit 5404. Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit together. Also, for example, depending on the number of switching TFTs included in one pixel, a plurality of scanning lines may be provided for each pixel to control the operation of the switching elements. In this case, the signals input to the plurality of scanning lines may all be generated by one scanning line driving circuit, or may be generated by a plurality of respective scanning line driving circuits.

[0201] Also, in the light-emitting display device, a part of the driving circuit that can be composed of n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin film transistors in the pixel portion. In addition, the signal line driver circuit and the scanning line driver circuit are formed by using the n-channel TFTs shown in the embodiments 1 to 3. It is also possible to produce it using only FT.

[0202] The above-mentioned driving circuit is not limited to liquid crystal display devices and light-emitting display devices, but may also be used in devices with switching elements and It may also be used in electronic paper, where electrically connected elements are used to drive electronic ink. Electronic paper is also called an electrophoretic display (electrophoretic display) and has the same properties as paper. The advantages are ease of reading, lower power consumption compared to other display devices, and the possibility of making them thin and lightweight. It has points.

[0203] Electrophoretic displays can take a variety of forms, but the first particle has a positive charge. A microcapsule containing a negatively charged second particle and a negatively charged second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0204] Thus, electrophoretic displays operate in such a way that materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required for the display, reducing weight.

[0205] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using particles having a color filter or a pigment.

[0206] Also, if a plurality of the microcapsules are appropriately arranged on the active matrix substrate so as to be sandwiched between two electrodes, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used. capsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used. can be used.

[0207] Note that the first particles and the second particles in the microcapsules may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof. may be used.

[0208] By the above steps, a highly reliable display device can be manufactured as a semiconductor device.

[0209] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0210] (Embodiment 5) A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. Further, a part or the whole of the driving circuit of the thin film transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel. A thin film transistor can be manufactured and used in a pixel portion and further in a driving circuit to manufacture a semiconductor device (also referred to as a display device) having a display function. on panel. can be formed.

[0211] The display device includes a display element. Examples of the display element include a liquid crystal element (also referred to as a liquid crystal display element) and a light emitting An element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in that category, an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied. An element that includes an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied. An element that includes an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied. An element that includes an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied.

[0212] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable. Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, regarding the element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, the element substrate includes means for supplying current to the display element for each of a plurality of pixels. Specifically, the element substrate may be in a state where only the pixel electrodes of the display element are formed, or may be in a state after forming a conductive film to be the pixel electrodes and before etching to form the pixel electrodes, and any form is applicable.

[0213] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device. Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Further, a module to which a connector, for example, an FPC (Flexible Printed Circuit) or a TAB (Tape Automated Bonding) tape or a TCP (Tape Carrier Package) is attached, a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG (Chip On Glass) method is also included in the display device.

[0214] Regarding the appearance and cross-section of a liquid crystal display panel corresponding to one form of a semiconductor device, it will be described with reference to FIG. 15. FIG. 15 shows highly reliable thin film transistors 4010, 4011, and a liquid crystal element 4013 including an oxide semiconductor layer shown in Embodiment 3 formed on a first substrate 4001, which are sealed with a sealing material 4005 between the first substrate 4001 and a second substrate 4006. FIG. 15(A) is a plan view of the panel, and FIG. 15(B) corresponds to a cross-sectional view taken along M-N in FIGS. 15(A1)(A2). A sealing material 4005 is provided so as to surround a pixel portion 4002 and a scanning line driving circuit 4004 provided on the first substrate 4001. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with a liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0215] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 15(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 15(A2) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Also, the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are sealed together with a liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method,

[0216] a wire bonding method, or a TAB method can be used. FIG. 15(A1) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 15(A2) is an example in which the signal line driving circuit 4003 is mounted by the TAB method. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method,

[0217] a wire bonding method, or a TAB method can be used. FIG. 15(A1) , having a plurality of thin film transistors, in Fig. 15(B), the thin film transistor 4010 included in the pixel portion 4002 and the thin film transistor 401 1 included in the scanning line driving circuit 4004 are illustrated. On the thin film transistors 4010 and 4011, insulating layers 4020 and 40

[0218] The thin film transistors 4010 and 4011 can be applied with highly reliable thin film transistors including the oxide semiconductor layer shown in Embodiment 3. Alternatively, the thin film transistors shown in Embodiment 1 or Embodiment 2 may be applied. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0219] Further, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033 that function as alignment films respectively, and sandwich the liquid crystal layer 4008 via the insulating layers 4032 and 4033.

[0220] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless), ceramics, or plastic can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics) plate, PV F (polyvinyl fluoride) film, polyester film, polyester film Alternatively, an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film or a polyester film can be used.

[0221] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used. Also, the counter electrode layer 403 1 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. Using a common connection portion, the counter electrode layer 4 031 and the common potential line can be electrically connected through conductive particles disposed between a pair of substrates. Note that the conductive particles are contained in the sealing material 4 005.

[0222] Alternatively, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric liquid crystal transitions from the cholesteric phase to the isotropic phase when the temperature is raised. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 1 msec or less, is optically isotropic, does not require alignment treatment, and has little viewing angle dependence.

[0223] In addition to the transmissive liquid crystal display device, it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0224] Also, in the liquid crystal display device, a polarizing plate is provided on the outside (viewing side) of the substrate, and a coloring layer and display elements are provided on the inside. An example of providing in the order of an electrode layer used in the child is shown, but the polarizing plate may be provided inside the substrate. Also The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be appropriately set according to the materials of the polarizing plate and the colored layer and the manufacturing process conditions. Further, a light-shielding film functioning as a black matrix may be provided.

[0225] Also, in order to reduce the surface unevenness of the thin film transistor and improve the reliability of the thin film transistor, the thin film transistor obtained in the above embodiment is covered with an insulating layer (insulating layer 4020, insulating layer 4021) that functions as a protective film or a planarizing insulating film. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferred. The protective film may be a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film formed by using a sputtering method. An example of forming the protective film by a sputtering method is shown, but it is not particularly limited and may be formed by various methods. Here, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, a silicon oxide film is formed as the first layer of the insulating layer 402 0 by using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing the hillock of the aluminum film used as the source electrode layer and the drain electrode layer.

[0226] Also, an insulating layer is formed as the second layer of the protective film. Here, a silicon nitride film is formed as the second layer of the insulating layer 4020 by using a sputtering method. When a silicon nitride film is used as the protective film, using a silicon oxide film as the protective film has an effect on preventing the hillock of the aluminum film used as the source electrode layer and the drain electrode layer.

[0227] Also, an insulating layer is formed as the second layer of the protective film. Here, here, a silicon nitride film is formed as the second layer of the insulating layer 4020 by using a sputtering method. When a silicon nitride film is used as the protective film, ​​​​​When using the nitride film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT.

[0228] Also, after forming the protective film, heat treatment (at 300 °C or lower) may be performed in a nitrogen atmosphere or an air atmosphere.

[0229] Also, an insulating layer 4021 is formed as a planarization insulating film. As the insulating layer 4021, heat-resistant organic materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the insulating layer 4021 may be formed by laminating a plurality of insulating films formed of these materials.

[0230] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Also, the organic group may have a fluoro group.

[0231] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. By combining the baking process of the insulating layer 4021 with the annealing of the oxide semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device.

[0232] The pixel electrode layer 4030 and the counter electrode layer 4031 are indium oxide containing tungsten oxide , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, etc., having translucency A conductive material can be used.

[0233] Further, the pixel electrode layer 4030 and the counter electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0234] As the conductive polymer, a so-called π-electron conjugated system conductive polymer can be used. For example, polyaniline or its derivative, polypyrrole or its derivative, polythiophene or its derivative, or a copolymer of two or more of these can be mentioned.

[0235] In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003 and the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from the FPC 4018.

[0236] The connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4010 and 4011. ​​​​​​​​​

[0237] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. and is electrically connected.

[0238] Also, in FIG. 15, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted. and mounted. and mounted.

[0239] FIG. 25 shows an example of a liquid crystal display module configured as a semiconductor device using the TFT substrate 2600 manufactured by the manufacturing method disclosed in the present specification. and mounted.

[0240] FIG. 25 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including a TFT or the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display area. The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to the respective colors of red, green, and blue are provided corresponding to each pixel. Polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated therein. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. and a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display area. and a coloring layer 2605 are provided therebetween to form a display area. The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to the respective colors of red, green, and blue are provided corresponding to each pixel. and a coloring layer corresponding to each pixel is provided. Outside the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and a control circuit and external circuits such as a power supply circuit are incorporated therein. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. circuit and external circuits such as a power supply circuit are incorporated therein. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. and laminated in a state having a retardation plate.

[0241] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0242] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0243] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0244] (Embodiment 6) An example of the semiconductor device is electronic paper.

[0245] Electronic paper that uses switching elements and elements electrically connected to drive electronic ink The thin film transistor described in any of the above-mentioned Embodiments 1 to 3 may be used for the electronic paper. Also called electrophoretic display (electrophoretic display), it has the same readability as paper. It has the advantages of consuming less power than other display devices and being thinner and lighter.

[0246] An electrophoretic display can take various forms, but it is composed of microcapsules containing a first particle with a positive charge and a second particle with a negative charge dispersed in a solvent or solute. By applying an electric field to the microcapsules, the particles in the microcapsules are moved in opposite directions to each other, and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). That is, the electrophoretic display utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The above microcapsules dispersed in a solvent are called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having a color filter or a pigment. Furthermore, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used. Note that the first particle and the second particle in the microcapsules are made of a conductor material, an insulator material,

[0247] As described above, the electrophoretic display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0248] The above microcapsules dispersed in a solvent are called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having a color filter or a pigment.

[0249] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained by the thin film transistors of Embodiments 1 to 3 can be used.

[0250] Note that the first particle and the second particle in the microcapsules are made of a conductor material, an insulator material, ​​​​​​​​A semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, a composite material thereof, or a combination of these materials may be used. One material selected from the group consisting of a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used.

[0251] FIG. 14 shows an active matrix type electronic paper, which is an example of a semiconductor device. The thin film transistor 581 used in the semiconductor device is a highly reliable thin film transistor including an oxide semiconductor layer, which can be fabricated in the same manner as the thin film transistor shown in Embodiment 1. The thin film transistor 581 used in the semiconductor device is a highly reliable thin film transistor including an oxide semiconductor layer, which can be fabricated in the same manner as the thin film transistor shown in Embodiment 1. The thin film transistors shown in Embodiment 2 or Embodiment 3 can also be applied as the thin film transistor 581 of the present embodiment. The thin film transistors shown in Embodiment 2 or Embodiment 3 can also be applied as the thin film transistor 581 of the present embodiment. may also be applicable.

[0252] The electronic paper of FIG. 14 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer used in a display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer used in a display element, and generating a potential difference between the first electrode layer and the second electrode layer to control the orientation of the spherical particles. A first electrode layer and a second electrode layer, and controlling the orientation of the spherical particles by generating a potential difference between the first electrode layer and the second electrode layer. This is a method of performing display.

[0253] The thin film transistor 581 is a thin film transistor having a bottom gate structure and is covered with an insulating film 583 in contact with the oxide semiconductor layer. The source electrode layer or the drain electrode layer of the thin film transistor 581 is in contact with the first electrode layer 587 through an opening formed in the insulating layer 585 and is electrically connected thereto. The source electrode layer or the drain electrode layer of the thin film transistor 581 is in contact with the first electrode layer 587 through an opening formed in the insulating layer 585 and is electrically connected thereto. There is a cavity 594 having a black region 590a and a white region 590b and filled with a liquid around it between the first electrode layer 587 and the second electrode layer 588. Spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin. Spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin. Spherical particles 589 are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin. It is filled. The first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to the common potential line provided on the same substrate 580 as the thin film transistor 581. Using the common connection part, the second electrode layer 588 and the common potential line can be electrically connected through the conductive particles arranged between the substrate 580 and the substrate 596.

[0254] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules with a diameter of about 10 μm to 200 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. The microcapsules provided between the first electrode layer and the second electrode layer will cause the white fine particles and the black fine particles to move in opposite directions when an electric field is applied by the first electrode layer and the second electrode layer, and can display white or black. The display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, an auxiliary light is not required, and also has low power consumption, and it is possible to recognize the display part even in a dim place. Also, even when the power supply is not supplied to the display part, it is possible to hold the once-displayed image. Therefore, even when the semiconductor device with a display function (also simply called a display device or a semiconductor device equipped with a display device) is kept away from the radio wave transmission source, it is possible to save the displayed image.

[0255] Through the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0256] ​​This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0257] (Embodiment 7) An example of a light-emitting display device as a semiconductor device is shown. As the display element of the display device, here is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that utilizes electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound, and generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0258] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when those carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0259] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of the light-emitting material are dispersed in a binder and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which the light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation.

[0260] FIG. 17 shows an example of a pixel configuration to which digital time-division driving can be applied as an example of a semiconductor device. This is the figure.

[0261] The configuration and operation of a pixel to which digital time-division driving can be applied will be described. Here, an example is shown in which one pixel uses two n-channel transistors using an oxide semiconductor layer as a channel formation region. This is the example.

[0262] Pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, its first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitor element 6403, its first electrode connected to the power supply line 640 7, and its second electrode connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set on the power supply line 6407 and satisfies the low power supply

[0263] potential < high power supply potential. For example, GND, 0V, etc. may be set as the low power supply potential. By applying the potential difference between this high power supply potential and the low power supply potential to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light, the high power supply potential is used. is a potential that satisfies the condition, and for example, GND, 0V, etc. may be set as the low power supply potential. By applying the potential difference between this high power supply potential and the low power supply potential to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light, the high power supply potential is used. is applied to the light-emitting element 6404 to cause a current to flow through the light-emitting element 6404 and make the light-emitting element 6404 emit light. Therefore, the high power supply potential Set the potential difference between the potential and the low power supply potential to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Set each potential accordingly.

[0264] Note that the capacitor element 6403 can be omitted by substituting the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

[0265] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied to the signal line 6405.

[0266] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 17 can be used by changing the signal input.

[0267] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light emitting element 6404 + Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that a video signal that causes the driving transistor 6402 to operate in the saturation region is input to allow current to flow through the light emitting element 6404. ​ To operate the switch 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be passed through the light-emitting element 6404, and analog gradation driving can be performed.

[0268] Note that the pixel configuration shown in FIG. 17 is not limited to this. For example, a new switch, resistance element, capacitance element, transistor, or logic circuit, etc. may be added to the pixel shown in FIG. 17.

[0269] Next, the configuration of the light-emitting element will be described with reference to FIG. 18. Here, the case where the driving TFT is an n channel type will be taken as an example to describe the cross-sectional structure of the pixel. The driving TFTs TFT7001, 7011, 7 021 used in the semiconductor devices of (A), (B ), (C) can be fabricated in the same manner as the thin-film transistor shown in Embodiment 1, and are highly reliable thin-film transistors including an oxide semiconductor layer . Also, the thin-film transistors shown in Embodiment 2 or Embodiment 3 can be applied as TFT7001, 7011, 7021.

[0270] For the light-emitting element, at least one of the anode or the cathode needs to be transparent in order to extract light. Then, a thin-film transistor and a light-emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate for top emission, light is emitted from the surface on the substrate side for bottom emission, or there is a light-emitting element with a double-sided emission structure that emits light from both the substrate side and the surface opposite to the substrate, and the pixel configuration can be applied to the light-emitting element of any emission structure .

[0271] The light-emitting element with a top emission structure will be described with reference to FIG. 18(A).

[0272] ​​ In FIG. 18A, a TFT 7001 which is a driving TFT is an n-channel type, and a light emitting element 700 FIG. 18(A) shows a cross-sectional view of a pixel when light emitted from the cathode 7002 exits to the anode 7005 side. In the example shown in FIG. 1, the cathode 7003 of the light-emitting element 7002 and the TFT 7001 which is the driving TFT are electrically A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. The cathode 7003 can be made of various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers may be laminated. In the case where the cathode 7003 is made up of a plurality of layers, the electron injection layer 7002 is formed on the cathode 7003. The layers are laminated in this order: a layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. It is not necessary to provide all of the anodes 7005. The anode 7005 is made of a conductive material that transmits light. For example, indium oxide containing tungsten oxide, indium oxide containing tungsten oxide Indium zinc oxide, Indium oxide with titanium oxide, Indium with titanium oxide Tin oxide, indium tin oxide, indium zinc oxide, indium doped with silicon oxide A light-transmitting conductive film such as a conductive film of tin oxide may be used.

[0273] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 18(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0274] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is of the n-channel type and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side, a cross-sectional view of the pixel is shown in Fig. 18(B). In Fig. 18(B), on a light-transmissive conductive film 7017 electrically connected to the driving TFT 7011, the cathode 7013 of the light-emitting element 7012 is formed, and the light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7015 has light-transmissivity, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 18(A). However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7014 can be composed of a single layer or multiple laminated layers, either way, similar to Fig. 18(A). The anode 7015 does not necessarily need to transmit light, but can be formed using a light-transmissive conductive material, similar to Fig. 18(A). And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin with a black pigment added can also be used. The region where the cathode 7013 and the anode 7015 sandwich the light-emitting layer 7014 corresponds to the light-emitting element 7012. In the case of the pixel shown in Fig. 18(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow. Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 18(C). Fig. 18(C)

[0275]

[0276] ​​​​​​​​​​​​​​​​Then, on the light-transmitting conductive film 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed. On the cathode 7023, the light-emitting layer 7024 , and the anode 7025 are sequentially laminated. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 18(A). However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023 . And the light-emitting layer 7024 can be composed of a single layer or a plurality of laminated layers, similar to Fig. 18(A). The anode 7 025 can be formed using a light-transmitting conductive material that transmits light, similar to Fig. 18(A).

[0277] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in Fig. 18(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0278] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0279] Although an example in which a thin film transistor (driving TFT) for controlling the driving of the light-emitting element is connected to the light-emitting element has been shown, a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be used.

[0280] Note that the semiconductor device is not limited to the configuration shown in Fig. 18, and various modifications based on the technical ideas disclosed in this specification are possible.

[0281] Next, the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the semiconductor device will be described with reference to FIG. 16. FIG. 16 is a planar view of the panel in which thin film transistors and light-emitting elements formed on a first substrate are sealed with a sealing material between the first substrate and a second substrate, and FIG. 16(B) corresponds to a cross-sectional view taken along H-I of FIG. 16(A).

[0282] A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on a first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. It is preferable to package (encase) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) or a cover material so as not to be exposed to the outside air.

[0283] Also, the pixel portion 4502, signal line driving circuits 4503a and 4503b, and scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 include a plurality of thin film transistors. In FIG. 16(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are exemplified.

[0284] ​​​​​​​​​​​The thin film transistors 4509 and 4510 can apply the highly reliable thin film transistor including the oxide semiconductor layer shown in Embodiment 3. Also, the thin film transistors shown in Embodiment 1 or Embodiment 2 may be applied. The thin film transistors 4509 and 4510 are n-channel type thin film transistors. Also, the thin film transistors shown in Embodiment 1 or Embodiment 2 may be applied. The thin film transistors 4509 and 4510 are n-channel type thin film transistors. n-channel type thin film transistors.

[0285] Further, 4511 corresponds to a light emitting element, and the first electrode layer 4517 which is the pixel electrode of the light emitting element 4511 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The structure of the light emitting element 4511 is a laminated structure of the first electrode layer 4517, the light emitting layer 4512, and the second electrode layer 4513, but is not limited to the shown structure. The structure of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like. The first electrode layer 4517 which is the pixel electrode of the light emitting element 4511 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The structure of the light emitting element 4511 is a laminated structure of the first electrode layer 4517, the light emitting layer 4512, and the second electrode layer 4513, but is not limited to the shown structure. The structure of the light emitting element 4511 is a laminated structure of the first electrode layer 4517, the light emitting layer 4512, and the second electrode layer 4513, but is not limited to the shown structure. The structure of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like. The structure of the light emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light emitting element 4511 and the like.

[0286] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening to be an inclined surface formed with a continuous curvature. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and to form the side wall of the opening to be an inclined surface formed with a continuous curvature.

[0287] The light emitting layer 4512 may be composed of a single layer or may be composed of a plurality of layers laminated. The light emitting layer 4512 may be composed of a single layer or may be composed of a plurality of layers laminated.

[0288] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed. A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4511. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0289] In addition, various signals and potentials supplied to the signal line drive circuits 4503a and 4503b, and the scanning line drive circuits 4504a and 4504b , or the pixel section 4502 are supplied from the FPCs 4518a and 4518 b.

[0290] The connection terminal electrode 4515 is formed from the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4510.

[0291] The connection terminal electrode 4515 is electrically connected through the anisotropic conductive film 4519 to the terminal of the FPC 4518a.

[0292] The second substrate 4506 located in the light extraction direction from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0293] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filler.

[0294] Also, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter can be appropriately provided on the light-emitting surface of the light-emitting element. Okay. Also, an antireflection film may be provided on the polarizing plate or circular polarizing plate. For example, the unevenness on the surface can be subjected to an antiglare treatment that diffuses the reflected light more and reduces reflections.

[0295] The signal line drive circuits 4503a and 4503b and the scan line drive circuits 4504a and 4504b may be implemented by drive circuits formed of a single-crystalline semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or only a part thereof, may be separately formed and implemented, and is not limited to the configuration of FIG. 16.

[0296] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device.

[0297] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0298] (Embodiment 8) The semiconductor device disclosed in this specification can be applied as an electronic paper. The electronic paper can be used in electronic devices in all fields as long as it can display information. For example, using the electronic paper, it can be applied to electronic books (e-books), posters, in-vehicle advertisements on vehicles such as trains, and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 26 and 27.

[0299] FIG. 26 shows a poster 2631 made of electronic paper. When the advertising medium is a paper print material, the advertisement is replaced manually, but the electronic paper disclosed in this specification ​​​​​Using a parser, the advertisement display can be changed in a short time. Also, the display will not be disrupted and a stable image can be obtained. Note that the poster may be configured to wirelessly transmit and receive information .

[0300] Also, FIG. 27 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed about the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations similar to those of a paper book .

[0301] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703 . The display unit 2705 and the display unit 2707 may be configured to display consecutive screens or may be configured to display different screens. With a configuration for displaying different screens , for example, text can be displayed on the right display unit (display unit 2705 in FIG. 27), and an image can be displayed on the left display unit (display unit 2707 in FIG. 27).

[0302] Also, FIG. 27 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided . By operating the operation keys 2723, pages can be turned. Note that a key board, a pointing device, etc. may be provided on the same surface as the display unit of the housing . Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, etc. may be provided , and a configuration including such components may be adopted . It may be. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. It may be.

[0303] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is possible to purchase and download desired book data and the like from an electronic book server. It is also possible.

[0304] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television devices (also referred to as TVs or television receivers), monitors for computers, cameras such as digital cameras and digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, and large game machines such as pachinko machines. These are examples.

[0305] FIG. 28(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display an image. Here, a configuration in which the housing 9601 is supported by a stand 9605 is shown.

[0306] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation device 9610. The operation keys 9609 provided in the remote control operation device 9610 can be used to operate channels and volume, and can also be used to operate the image displayed on the display unit 9603. Also, the remote control operation device 9610 is provided with the remote control operation device ​ It may be configured to include a display unit 9607 that displays information output from 9610.

[0307] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive more general television broadcasts, and can be connected to a communication network by wire or wirelessly via a modem, enabling one-way (sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0308] FIG. 28(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0309] Note that the digital photo frame 9700 is configured to include an operation unit, external connection terminals (terminals connectable to various cables such as USB cables, USB cables, etc.), a recording medium insertion unit, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface as it improves the design. For example, by inserting a memory storing image data taken with a digital camera into the recording medium insertion

[0310] unit of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0311] FIG. 29(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 29(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, odor, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the semiconductor device disclosed in the document is included, and other auxiliary equipment is appropriately provided. The portable game machine shown in FIG. 29(A) can be configured as a game machine having a game data recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines It has a function to communicate and share information. The function to be performed is not limited to this, and may have various functions.

[0312] FIG. 29(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. It is not limited to such things, and any configuration having at least the semiconductor device disclosed in this specification may be sufficient. In addition, it can be configured such that other accessory equipment is appropriately provided.

[0313] FIG. 30(A) is a perspective view showing an example of a portable computer.

[0314] The portable computer in FIG. 30(A) can be in a state where the upper housing 9301 having a display unit 9303 and a lower housing 9302 having a keyboard 9304 are overlapped with the hinge unit connecting them in a closed state, which is convenient for carrying. When the user inputs via the keyboard, the hinge unit can be opened to view the display unit 9303 and perform an input operation. In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. If the display unit 9303 is a touch input panel, an input operation can also be performed by touching a part of the display unit. The lower housing 9302 has arithmetic function units such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. When the user inputs via the keyboard, the hinge unit can be opened to view the display unit 9303 and perform an input operation. In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. If the display unit 9303 is a touch input panel, an input operation can also be performed by touching a part of the display unit. The lower housing 9302 has arithmetic function units such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted.

[0315] Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. When the user inputs via the keyboard, the hinge unit can be opened to view the display unit 9303 and perform an input operation. In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. If the display unit 9303 is a touch input panel, an input operation can also be performed by touching a part of the display unit. The lower housing 9302 has arithmetic function units such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. In addition to the keyboard 9304, the lower housing 9302 has a pointing device 9306 for performing an input operation. If the display unit 9303 is a touch input panel, an input operation can also be performed by touching a part of the display unit. The lower housing 9302 has arithmetic function units such as a CPU and a hard disk. The lower housing 9302 also has an external connection port 9305 into which a communication cable conforming to the communication standard of another device, for example, USB, is inserted. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit.

[0316] Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit. Moreover, the upper housing 9301 further has a display unit 9307 that can be slid and stored inside the upper housing 9301, enabling a wide display screen to be realized. The user can adjust the orientation of the screen of the retractable display unit 9307. If the retractable display unit 9307 is a touch input panel, an input operation can also be performed by touching a part of the retractable display unit.

[0317] The display unit 9303 or the foldable display unit 9307 uses a video display device such as a light-emitting display panel like a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element.

[0318] Also, the portable computer in Fig. 30(A) is configured with a receiver and the like, and can receive a television broadcast and display the video on the display unit or the display unit. Further, with the hinge unit connecting the upper housing 9301 and the lower housing 9302 in the closed state, the display unit 9307 is slid to expose the entire screen, and the screen angle can be adjusted for the user to watch the television broadcast. In this case, with the hinge unit in the open state, the display unit 9303 is not displayed, and only the activation of the circuit for displaying only the television broadcast is performed, so that the minimum power consumption can be achieved, which is useful for a portable computer with a limited battery capacity.

[0319] Fig. 30(B) is a perspective view showing an example of a mobile phone having a form that can be worn on the user's wrist like a wristwatch.

[0320] This mobile phone includes a communication device having at least a telephone function, a main body having a battery, a band portion for wearing the main body on the wrist, an adjustment portion 9205 for adjusting the fixed state of the band portion with respect to the wrist, a display portion 9201, a speaker 9207, and a microphone 9208.

[0321] The main body also has an operation switch 9203, and in addition to a power input switch, a display switching switch, and an imaging start instruction switch, for example, when a switch is pressed, a program for the Internet can be started, and each function can be associated.

[0322] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating the operation switch 9203 or by voice input to the microphone 9208. FIG. 30B shows a display button 9202 displayed on a display unit 9201. Input can be made by touching the screen.

[0323] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0324] The mobile phone shown in FIG. 30(B) is equipped with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory, etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0325] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in FIG. 30(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force actuable panel.

[0326] Although FIG. 30B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0327] (Embodiment 10) In this embodiment, an example in which some steps are different from those in Embodiment 1 is shown. This embodiment is a source An example of performing dehydration or dehydrogenation heat treatment after forming the electrode layer or drain electrode layers 405a and 405b is shown in FIG. 31. Note that the same reference numerals are used for the same parts as in FIG. 1 for explanation. .

[0328] Similar to Embodiment 1, a gate electrode layer 401, a gate insulating layer 402, and an oxide semiconductor layer 430 are formed on a substrate 400 having an insulating surface (see FIG. 31(A)).

[0329] A source electrode layer or drain electrode layers 405a and 405b are formed on the oxide semiconductor layer 430, and a part of the oxide semiconductor layer 430 is etched to form an oxide semiconductor layer 441 (see FIG. 31(B)).

[0330] Next, after performing heat treatment on the oxide semiconductor layer 441 and the source electrode layer or drain electrode layers 405a and 405b in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) or under reduced pressure, slow cooling is performed in an oxygen atmosphere. By this heat treatment, the oxide semiconductor layer 441 is subjected to dehydration treatment or dehydrogenation treatment to reduce its resistance, and a low-resistance oxide semiconductor layer 432 can be obtained (see FIG. 31(C)). Note that the materials of the source electrode layer or drain electrode layers 405a and 405b are preferably materials that can withstand the heat treatment here, such as tungsten and molybdenum.

[0331] Next, without being exposed to the atmosphere after the above heat treatment and slow cooling, an oxide insulating film 407 in contact with the oxide semiconductor layer 432 is formed by a sputtering method or a PCVD method. After reducing the resistance ​When the oxide insulating film 407 in contact with the oxide semiconductor layer 432 is formed by sputtering or PCVD method, at least the region in contact with the oxide insulating film 407 in the oxide semiconductor layer 432 with reduced resistance becomes a high-resistance region (the carrier concentration decreases, preferably less than 1×10 / 18 / cm 3 ), and it can be a high-resistance oxide semiconductor region. Therefore, the oxide semiconductor layer 432 becomes an oxide semiconductor layer 403 (third oxide semiconductor layer) having a high-resistance oxide semiconductor region, and a thin film transistor 470 can be fabricated (see Fig. 31(D)). . .

[0332] By performing the heat treatment for the dehydration treatment or dehydrogenation treatment, impurities (such as H2O, H, OH, etc.) contained in the oxide semiconductor layer are reduced and the carrier concentration is increased, and then slow cooling is performed in an oxygen atmosphere. After slow cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer or the like to reduce the carrier concentration of the oxide semiconductor layer and improve the reliability of the thin film transistor 470. . . .

[0333] Also, this embodiment can be freely combined with Embodiment 1.

[0334] (Embodiment 11) A semiconductor device and a method for manufacturing a semiconductor device will be described with reference to Fig. 32. The same parts or parts having similar functions, and processes as in Embodiment 1 can be performed in the same manner as in Embodiment 1, and repeated descriptions will be omitted. . .

[0335] The thin film transistor 471 shown in Fig. 32 is an example in which a conductive layer 409 is provided via an insulating film so as to overlap the channel region of the gate electrode layer 401 and the oxide semiconductor layer 403. .

[0336] FIG. 32 is a cross-sectional view of a thin film transistor 471 included in a semiconductor device. The thin film transistor 471 is a dual gate type thin film transistor, and on a substrate 400 which is a substrate having an insulating surface, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer or drain electrode layers 405a and 405b, an oxide insulating film 407, and a conductive layer 40 8 are included. The conductive layer 408 is provided on the oxide insulating film 407 so as to overlap with the gate electrode layer 401.

[0337] The conductive layer 408 can be formed using the same materials and methods as those of the gate electrode layer 401 and the source electrode layer or drain electrode layers 405a and 405b. When providing a pixel electrode layer, it may be formed using the same materials and methods as those of the pixel electrode layer. In this embodiment, a titanium film, an aluminum film, and a stack of titanium films are used as the conductive layer 40

[0338]

[0339] 8. The potential of the conductive layer 408 may be the same as or different from that of the gate electrode layer 401, and it can also function as a second gate electrode layer. Further, the conductive layer 408 may be in a floating state.

[0340] By providing the conductive layer 408 at a position overlapping with the oxide semiconductor layer 403, in a bias - thermal stress test (hereinafter referred to as a BT test) for examining the reliability of the thin film transistor, the amount of change in the threshold voltage of the thin film transistor 471 before and after the BT test can be reduced. In particular, in a - BT test in which the voltage applied to the gate is set to -20 V after raising the substrate temperature to 150°C, fluctuations in the threshold voltage can be suppressed.

[0340] ​ This embodiment can be freely combined with Embodiment 1.

[0341] (Embodiment 12) A semiconductor device and a method of manufacturing the semiconductor device will be described with reference to FIG. 33. The same parts or parts having similar functions, and processes can be carried out in the same manner as in Embodiment 1 , and repeated descriptions will be omitted.

[0342] The thin film transistor 472 shown in FIG. 33 has a conductive layer 4 19 provided through an oxide insulating film 407 and an insulating layer 410 so as to overlap the channel region of the gate electrode layer 401 and the oxide semiconductor layer 403 .

[0343] FIG. 33 is a cross-sectional view of the thin film transistor 472 included in the semiconductor device. The thin film trans istor 472 is a dual-gate type thin film transistor, and on a substrate 400 having an insulating surface, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source region or drain regions 404a, 404b, a source electrode layer or drain electrode layers 40 5a, 405b, an oxide insulating film 407, an insulating layer 410, and a conductive layer 419 are included. The conductive layer 419 is provided on the insulating layer 410 so as to overlap the gate electrode layer 401.

[0344] By providing the source region or drain regions 404a, 404b between the oxide semiconductor layer 403 and the source electrode layer or drain electrode layers 405a, 405b respectively, it is possible to make a good junction between the source electrode layer or drain electrode layers 405a, 405b which are metal layers and the oxide semiconductor layer 4 03, and it is thermally more stable than a Schottky junction ​​In addition, the low resistance allows good mobility to be maintained even at high drain voltages. This can be done.

[0345] In addition, the present invention is not limited to the structure having the above-mentioned source and drain regions 406a and 406b. For example, a structure in which the source region and the drain region are not provided may be used.

[0346] The thin film transistor described in this embodiment has a structure that functions as a planarization film over the oxide insulating film 407. The insulating layer 410 is then laminated over the oxide insulating film 407 and the insulating layer 410. An oxide insulating film 407 having an opening reaching the rain electrode layer (here, 405b) and an insulating A conductive film is formed in the opening formed in the layer 410 and etched into a desired shape to form a conductive layer 419. In this way, in the process of forming the pixel electrode layer 411, In this embodiment, the pixel electrode layer 411, the conductive layer 419, and the like can be formed. Indium oxide tin oxide alloy containing silicon oxide (In-Sn -O-based oxides) are used.

[0347] The conductive layer 419 is formed on the gate electrode layer 401 and the source or drain electrode layer 405. They may be formed using the same materials and manufacturing methods as those of 405a and 405b.

[0348] The conductive layer 419 may have the same potential as the gate electrode layer 401. The conductive layer 419 can also function as a second gate electrode layer. 419 may be in a floating state.

[0349] By providing the conductive layer 419 so as to overlap with the oxide semiconductor layer 403, a thin film transistor In the BT test for examining the reliability of a stud, the change amount of the threshold voltage of the thin film transistor 472 can be reduced.

[0350] This embodiment can be freely combined with Embodiment 1.

[0351] (Embodiment 13) In this embodiment, an example of the channel stop type thin film transistor 1430 will be described with reference to FIGS. 3 4(A), 34(B) and 34(C). Further, FIG. 34(C) is an example of a top view of the thin film transistor, and the cross-sectional view taken along the chain line Z1-Z2 in the figure corresponds to FIG. 34( B). Further, a form in which an oxide semiconductor material containing no gallium is used for the oxide semiconductor layer 1403 of the thin film transistor 1430 is shown.

[0352] In FIG. 34(A), a gate electrode layer 1401 is formed on a substrate 1400. Next, an oxide semiconductor layer is formed on a gate insulating layer 1402 covering the gate electrode layer 1401.

[0353] In this embodiment, an Sn-Zn -O-based oxide semiconductor using a sputtering method is used as the oxide semiconductor layer 1403. By not using gallium in the oxide semiconductor layer, it is possible to form without using an expensive target, so that the cost can be reduced.

[0354] After the formation of the oxide semiconductor film or after the patterning of the oxide semiconductor film, dehydration or dehydrogenation is performed.

[0355] In order to perform dehydration or dehydrogenation, heat treatment is performed under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then slow cooling is performed under an oxygen atmosphere. The heat treatment is carried out at 200°C or higher and 600°C or lower, preferably 400°C or higher and 450°C or lower. The oxide semiconductor layer can be made to have a lower resistance (the carrier concentration increases, preferably to 1×10 / cm 18 or higher) by heat treatment in an inert gas atmosphere or under reduced pressure and slow cooling in an oxygen atmosphere (see Fig. 34(A)). 3 Reference

[0356] Next, a channel protection layer 1418 is formed in contact with the oxide semiconductor layer 1403. By forming the channel protection layer 1418 on the oxide semiconductor layer 1403, damage (such as film thinning caused by plasma or an etching agent during etching) during the subsequent source region 1406a and drain region 1406b formation processes can be prevented. Therefore, the reliability of the thin film transistor 1430 can be improved.

[0357] Also, after dehydration or dehydrogenation, the channel protection layer 1418 can be continuously formed without exposing it to the atmosphere. By continuously processing without exposing it to the atmosphere, the interfaces can be formed without being contaminated by atmospheric components such as water and hydrocarbons or impurity elements floating in the atmosphere, so that variations in thin film transistor characteristics can be reduced.

[0358] Also, when the channel protection layer 1418, which is an oxide insulating film, is formed by sputtering or PCVD in contact with the low-resistance oxide semiconductor layer 1403, at least the region in the low-resistance oxide semiconductor layer 1403 in contact with the channel protection layer 1418 becomes highly resistive (the carrier concentration decreases, preferably to 1×10 / cm 18 ​​​​​​​​​​​ / cm 3 less than, more preferably 1 ×10 14 / cm 3 or less), and a high-resistance oxide semiconductor region can be obtained. During the manufacturing process of the semiconductor device, heating in an inert gas atmosphere (or under reduced pressure), slow cooling in an oxygen atmosphere, and formation of an oxide insulating film are important for increasing or decreasing the carrier concentration of the oxide semiconductor layer. During the manufacturing process of the semiconductor device, heating in an inert gas atmosphere (or under reduced pressure), slow cooling in an oxygen atmosphere, and formation of an oxide insulating film are important for increasing or decreasing the carrier concentration of the oxide semiconductor layer. During the manufacturing process of the semiconductor device, heating in an inert gas atmosphere (or under reduced pressure), slow cooling in an oxygen atmosphere, and formation of an oxide insulating film are important for increasing or decreasing the carrier concentration of the oxide semiconductor layer. is important.

[0359] As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography. As the channel protection layer 1418, an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, silicon nitride oxide, etc.) can be used. As the manufacturing method, a vapor growth method such as plasma CVD method or thermal CVD method or a sputtering method can be used. The channel protection layer 1418 is formed by processing the shape by etching after film formation. Here, a silicon oxide film is formed by a sputtering method, and the channel protection layer 1418 is formed by etching using a mask by photolithography.

[0360] Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). Next, a source region 1406a and a drain region 1406b are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In the present embodiment, the source region 1406a and the drain region 1406b that function as a source region or a drain region are Al-Zn-O-based non-single crystal films, which are formed under film formation conditions different from those of the oxide semiconductor layer 1403 and are oxide semiconductor layers with lower resistance. Also, the source region 1406a and the drain region 1406b may be an Al-Zn-O-based non-single crystal film containing nitrogen, that is, an Al-Zn-O-N-based non-single crystal film (also called an AZON film). -N-based non-single crystal film (also called an AZON film) may be used.

[0361] Next, a source electrode layer 1405a is formed on the source region 1406a, and a drain electrode layer 1405b is formed on the drain region 1406b to fabricate the thin film transistor 1430 ( see Fig. 34(B)). The source electrode layer 1405a and the drain electrode layer 1405b can be formed in the same manner as the source electrode layer and the drain electrode layers 405a, 405b shown in Embodiment 1 . .

[0362] By providing the source region 1406a and the drain region 1406b between the oxide semiconductor layer 1403 and the source electrode layer 1405a and the drain electrode layer 1405b, it is possible to achieve a good junction between the source electrode layer 1405a and the drain electrode layer 1405b made of a metal layer and the oxide semiconductor layer 1403, and to perform thermally stable operation compared to a Schottky junction . Also, due to the reduction in resistance, it is possible to maintain good mobility even at a high drain voltage . . .

[0363] Further, the structure is not limited to the structure having the source region 1406a and the drain region 1406b described above. For example, a structure without a source region and a drain region may be used .

[0364] Also, after forming the channel protection layer 1418, a heat treatment (preferably at 150°C or higher and lower than 350°C) is performed on the thin film transistor 1430 in a nitrogen atmosphere or in an air atmosphere (in air) . For example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. By performing this heat treatment , the oxide semiconductor layer 1403 is heated in a state of being in contact with the channel protection layer 1418, and the variation in the electrical characteristics of the thin film transistor 1470 can be reduced . . This heat treatment (preferably at 150°C or higher and lower than 350°C) is performed after the formation of the channel protection layer 1418 . It is not particularly limited as long as it is, and when forming an insulating layer that functions as a planarization film in another process, for example By combining it with a heat treatment such as a heat treatment for forming an insulating layer that functions as a planarization film or a heat treatment for reducing the resistance of a transparent conductive film, the number of steps can be increased without difficulty.

[0365] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments is.

[0366] (Embodiment 14) A semiconductor device and a method for manufacturing a semiconductor device will be described with reference to FIGS. 35(A) and 35(B). Parts and processes that are the same or have similar functions as those in Embodiment 13 can be carried out in the same manner as in Embodiment 13, and repeated explanations will be omitted.

[0367] The thin film transistor 1431 shown in FIG. 35(A) is an example in which a conductive layer 1409 is provided via a channel protection layer 1418 and an insulating layer 1407 so as to overlap the channel regions of the gate electrode layer 1401 and the oxide semiconductor layer 1403.

[0368] The thin film transistor 1431 is a dual-gate type thin film transistor, and includes a gate electrode layer 1401, a gate insulating layer 1402, an oxide semiconductor layer 1403, a source region 1406a, or a drain region 1406b, a source electrode layer 1405a or a drain electrode layer 1405b, an insulating layer 1407, and a conductive layer 140 9 on a substrate 1400 which is a substrate having an insulating surface. The conductive layer 1409 is provided on the insulating layer 1407 so as to overlap the gate electrode layer 1401. 9. The conductive layer 1409 is provided on the insulating layer 1407 so as to overlap the gate electrode layer 1401.

[0369] The conductive layer 1409 is the gate electrode layer 1401, the source electrode layer 1405a, or the drain electrode It can be formed using the same materials and methods as the top layer 1405b. Provide a pixel electrode layer. In the case of providing a pixel electrode layer, it may be formed using the same materials and methods as the pixel electrode layer. In this embodiment, a stacked layer of a titanium film, an aluminum film, and a titanium film is used as the conductive layer 1409.

[0370] The potential of the conductive layer 1409 may be the same as or different from that of the gate electrode layer 1401, and it can also function as a second gate electrode layer. Also, the conductive layer 1409 may be in a floating state.

[0371] By providing the conductive layer 1409 at a position overlapping the oxide semiconductor layer 1403, in a bias-thermal stress test (hereinafter referred to as a BT test) for examining the reliability of a thin film transistor, the amount of change in the threshold voltage of the thin film transistor 1431 before and after the BT test can be reduced.

[0372] Also, FIG. 35(B) shows an example partially different from FIG. 35(A). The same parts and parts having the same functions as in FIG. 35(A), and the processes can be performed in the same manner as in FIG. 35(A), and repeated explanation is omitted.

[0373] The thin film transistor 1432 shown in FIG. 35(B) is an example in which the conductive layer 1409 is provided via the channel protection layer 1418, the insulating layer 1407, and the insulating layer 1408 so as to overlap the channel region of the gate electrode layer 1401 and the oxide semiconductor layer 1403.

[0374] In FIG. 35(B), an insulating layer 1408 that functions as a planarization film is stacked on the insulating layer 1407.

[0375] In FIG. 35(B), a source region or a drain region is not provided, and the oxide semiconductor layer 14 03 is in direct contact with the source electrode layer 1405a or the drain electrode layer 1405b. It has such a structure.

[0376] Even in the structure of FIG. 35(B), by providing the conductive layer 1409 at a position overlapping the oxide semiconductor layer 1403, in the BT test for examining the reliability of the thin film transistor, the change amount of the threshold voltage of the thin film transistor 1432 before and after the BT test can be reduced. It can be done.

[0377] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0378] (Embodiment 15) In this embodiment, an example in which the structure is partially different from that of Embodiment 1 is shown in FIG. 36. The same parts or parts having the same functions, and steps as those in Embodiment 1 can be carried out in the same manner as in Embodiment 1, and repeated explanations are omitted. It can be done, and repeated explanations are omitted.

[0379] In this embodiment, after patterning of the first oxide semiconductor layer, heat treatment is performed in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then slow cooling is performed in an oxygen atmosphere. By performing heat treatment on the first oxide semiconductor layer in the above atmosphere, impurities such as hydrogen and water contained in the oxide semiconductor layer 403 can be removed.

[0380] Next, after forming a second oxide semiconductor film to be used as a source region and a drain region (also referred to as an n layer, buffer layer) of the thin film transistor on the first oxide semiconductor layer, a conductive film + is formed. is formed.​​​​​​

[0381] Next, the first oxide semiconductor layer, the second oxide semiconductor film, and the conductive film are subjected to an etching process to be selectively etched, forming an oxide semiconductor layer 403, and source regions or drain regions 404a, 404b, and source electrode layers or drain electrode layers 405a, 405b. Note that only a part of the oxide semiconductor layer 403 is etched to have a groove portion (recess). .

[0382] Next, a silicon oxide film is formed as an oxide insulating film 407 by sputtering or PCVD in contact with the oxide semiconductor layer 403. The oxide insulating film 407 formed in contact with the low-resistance oxide semiconductor layer contains no moisture, hydrogen ions, oxygen ions, OH - , etc., and uses an inorganic insulating film that blocks these from entering from the outside. Specifically, a silicon oxide film , or a silicon oxynitride film is used.

[0383] When an oxide insulating film 407 is formed by sputtering or PCVD in contact with the low-resistance oxide semiconductor layer 403, at least the region in contact with the oxide insulating film 407 in the low-resistance oxide semiconductor layer 403 becomes high resistance (the carrier concentration decreases, preferably less than 1×10 / cm 18 ³, more preferably less than 1×10 3 / cm 14 ³ or less), and a high-resistance oxide 3 semiconductor region can be formed. By forming in contact with the oxide insulating film 407, a high-resistance oxide semiconductor layer 403 is obtained, and a thin-film transistor 470 can be fabricated (see FIG. 36).

[0384] In the structure shown in FIG. 36, as the source region or drain region 404a, 404b an In-Ga-Zn-O based non-single crystal is used.

[0385] Also, a source region is provided between the oxide semiconductor layer 403 and the source electrode layer, and a drain region is provided between the oxide semiconductor layer and the drain electrode layer. An oxide semiconductor layer showing an n-type conductivity type is used for the source region and the drain region.

[0386] Also, the second oxide semiconductor layer used as the source region or drain region 404a, 404b of the thin film transistor 473 is preferably thinner than the oxide semiconductor layer 403 used as the channel formation region and has a higher conductivity (electrical conductivity).

[0387] Also, the oxide semiconductor layer 403 used as the channel formation region has an amorphous structure, and the second oxide semiconductor layer used as the source region and the drain region may contain crystal grains (nanocrystals) in the amorphous structure. The crystal grains (nanocrystals) in the second oxide semiconductor layer used as the source region and the drain region have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0388] Also, after forming the oxide insulating film 407, heat treatment (preferably 150°C or higher and less than 350°C) may be performed on the thin film transistor 473 in a nitrogen atmosphere or in an air atmosphere (in air). For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing this heat treatment, the oxide semiconductor layer 403 is heated in a state of being in contact with the oxide insulating film 407, and variations in the electrical characteristics of the thin film transistor 473 can be reduced.

[0389] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

Example

[0390] Here, in the oxide semiconductor layer having a region with a high oxygen concentration and a region with a low oxygen concentration, The results of calculating the change in oxygen concentration before and after the heat treatment will be described with reference to FIGS. 37 and 38. Here, as the software for calculation, Mater ials Explorer 5.0 manufactured by Fujitsu Limited was used. Here, it was used.

[0391] FIG. 37 shows the model of the oxide semiconductor layer used in the calculation. Here, the oxide semiconductor layer 70 1 has a structure in which a layer 703 with a low oxygen concentration and a layer 705 with a high oxygen concentration are stacked.

[0392] Here, as the layer 703 with a low oxygen concentration, an amorphous structure composed of 15 In atoms, 15 Ga atoms, 15 Zn atoms, and 54 O atoms was used.

[0393] Also, as the layer 705 with a high oxygen concentration, an amorphous structure composed of 15 In atoms, 15 Ga atoms, 15 Zn atoms, and 66 O atoms was used.

[0394] Also, the density of the oxide semiconductor layer 701 was set to 5.9 g / cm 3 It was set.

[0395] Next, for the oxide semiconductor layer 701, the change in oxygen concentration was calculated using classical MD (molecular dynamics) calculation under the conditions of the NVT ensemble and a temperature of 250 °C. The time step width was set to 0.2 fs And the total calculation time was set to 200 ps. Also, the potential is for metal-oxygen bonds, and It was set. The Born-Mayer-Huggins type was applied to the oxygen-oxygen bond. Also, for the oxide The movement of the atoms at the upper and lower ends of the semiconductor layer 701 was fixed.

[0396] Next, the calculation results are shown in FIG. 38. From 0 nm to 1.15 nm on the z-axis coordinate is the layer 703 with a low oxygen concentration, and from 1.15 nm to 2.3 nm on the z-axis coordinate is the layer 705 with a high oxygen concentration . The density distribution of oxygen before the MD calculation is shown by the solid line 707, and the density distribution of oxygen after the MD calculation is shown by the broken line 709.

[0397] In the solid line 707, from the interface between the layer 703 with a low oxygen concentration and the layer 705 with a high oxygen concentration , in the layer 705 with a high oxygen concentration, the density of oxygen is high. On the other hand, in the broken line 709, in the layer 703 with a low oxygen concentration and the layer 705 with a high oxygen concentration, the oxygen concentration is homogeneous as can be seen.

[0398] From the above, like the laminated state of the layer 703 with a low oxygen concentration and the layer 705 with a high oxygen concentration , when there is a bias in the oxygen concentration distribution, it can be seen that the oxygen diffuses from the higher oxygen concentration side to the lower oxygen concentration side by heat treatment and the oxygen concentration becomes homogeneous.

[0399] That is, as shown in Embodiment 1, by forming the oxide insulating film 407 on the oxide semiconductor layer 431 , the oxygen concentration becomes high at the interface between the oxide semiconductor layer 431 and the oxide insulating film 407 , so that the oxygen diffuses to the side with a lower oxygen concentration of the oxide semiconductor layer 431, and the oxide semiconductor layer 431 becomes highly resistive. Also, in Embodiment 1, after heating the oxide semiconductor layer in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure, and then slowly cooling the oxide semiconductor layer in an oxygen atmosphere to form the oxide insulating film 407, oxidation ​ Since it is possible to increase the oxygen concentration on the surface of the semiconductor layer, the oxygen diffuses toward the side with the lower oxygen concentration in the oxide semiconductor layer 431, and the oxide semiconductor layer 431 becomes highly resistive. From the above it is possible to improve the reliability of the thin film transistor.

Claims

1. A gate electrode, a gate insulating film on the gate electrode, a first oxide semiconductor layer on the gate insulating film, a second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode electrically connected to the second oxide semiconductor layer, a drain electrode electrically connected to the second oxide semiconductor layer, an oxide insulating film on the source electrode and the drain electrode, an insulating film on the oxide insulating film, a first conductive layer and a second conductive layer on the insulating film, and the first conductive layer has a region overlapping with the first oxide semiconductor layer, the second conductive layer is electrically connected to the source electrode or the drain electrode through an opening provided in the oxide insulating film and the insulating film, the first oxide semiconductor layer has a channel formation region, the first oxide semiconductor layer is an In - O semiconductor device.

2. A gate electrode, a gate insulating film on the gate electrode, a first oxide semiconductor layer on the gate insulating film, a second oxide semiconductor layer on the first oxide semiconductor layer, a source electrode electrically connected to the second oxide semiconductor layer, a drain electrode electrically connected to the second oxide semiconductor layer, an oxide insulating film on the source electrode and the drain electrode, an insulating film on the oxide insulating film, a first conductive layer and a second conductive layer on the insulating film, and the first conductive layer has a region overlapping with the first oxide semiconductor layer, the second conductive layer is electrically connected to the source electrode or the drain electrode through an opening provided in the oxide insulating film and the insulating film, the first conductive layer and the second conductive layer have the same material, the first oxide semiconductor layer has a channel formation region, the first oxide semiconductor layer is an In - O semiconductor device.

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