Light-emitting device

Abstract

To provide a light-emitting device using a transistor with an oxide semiconductor which suppresses a change of electric characteristics and increases reliability.SOLUTION: A transistor 10 includes: a gate electrode 13 on an insulation surface; an oxide semiconductor film 17 overlapping with the gate electrode; a gate insulation film 15 between the gate electrode and the oxide semiconductor film, the gate insulation film being in contact with the oxide semiconductor film: a protective film 21 of the oxide semiconductor film, which is in contact with an opposite surface to a surface in contact with the gate insulation film; and a pair of electrodes 19 and 20 in contact with the oxide semiconductor film. One of the gate insulation film and the protective film discharges a gas with a mass-charge ratio m / z of 17 by thermal processing more than nitrogen oxide discharged by thermal processing.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention relates to a method, manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. In particular, one aspect of the present invention relates to a field effect transistor, a driving method thereof, and a manufacturing method thereof. The present invention relates to a semiconductor device having a transistor.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0003] It is used in many flat panel displays, such as liquid crystal displays and light-emitting displays. The transistors used are made of amorphous silicon and single crystal silicon formed on a glass substrate. The silicon semiconductor is made of silicon semiconductor such as polycrystalline silicon or polysilicon. Transistors using silicon semiconductors are also used in integrated circuits (ICs).

[0004] In recent years, metal oxides that exhibit semiconducting properties have been used in transistors instead of silicon semiconductors. In this specification, the term "oxide" refers to a metal oxide that exhibits semiconductor properties. Let us call them semiconductors.

[0005] For example, as the oxide semiconductor, a transistor using zinc oxide or an In-Ga-Zn-based oxide is fabricated, and a technique of using the transistor as a switching element of a pixel of a display device or the like is disclosed (see Patent Document 1 and Patent Document 2).

[0006] By the way, it has been pointed out that hydrogen serves as a carrier source particularly in the oxide semiconductor. Therefore, measures are required to prevent hydrogen from being mixed during the formation of the oxide semiconductor, and by reducing the hydrogen in the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor, fluctuations in the threshold voltage are suppressed (see Patent Document 3).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, nitrogen serves as a carrier source in the same way as hydrogen. For this reason, when a large amount of nitrogen is contained in the film in contact with the oxide semiconductor film, fluctuations in the electrical characteristics of the transistor having the oxide semiconductor film occur, typically fluctuations in the threshold voltage. In addition, there is a problem that the electrical characteristics vary from transistor to transistor.

[0009] Therefore, one aspect of the present invention is a semiconductor device using a transistor having an oxide semiconductor. An object of the present invention is to suppress fluctuations in electrical characteristics and improve reliability. Another object of one aspect of the present invention is to provide a semiconductor device with reduced power consumption. Another object of one aspect of the present invention is to provide a novel semiconductor device or the like. Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. Other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc. Other problems will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract these other problems from the description of the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment. One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment. One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment. One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment. One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment. One aspect of the present invention includes a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film or the protective film has a region where the amount of gas released with a mass-to-charge ratio m / z = 17 is larger than the amount of nitrogen oxides released by heat treatment.

[0011] One aspect of the present invention includes a semiconductor device having a transistor including a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. One aspect of the present invention includes a semiconductor device having a transistor including a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. One aspect of the present invention includes a semiconductor device having a transistor including a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. One aspect of the present invention includes a semiconductor device having a transistor including a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. It is a device. A log-log graph showing the amount of change in the threshold voltage of a transistor with respect to stress time In the rough, the intervals of the logarithmic scales on the horizontal and vertical axes are equal, and the angle formed by the power-law approximation line of the absolute value of the amount of change in the threshold voltage and the straight line where the absolute value of the amount of change in the threshold voltage is 0 V is -3° or more and less than 20°, and the absolute value of the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.3 V. Note that the stress time refers to the time when a load such as voltage or temperature is applied to the transistor.

[0012] Also, one aspect of the present invention is a semiconductor device having a transistor including a gate electrode on an insulating surface, an oxide semiconductor film overlapping the gate electrode, a gate insulating film between the gate electrode and the oxide semiconductor film and in contact with the oxide semiconductor film, a protective film in contact with a surface of the oxide semiconductor film opposite to the surface in contact with the gate insulating film, and a pair of electrodes in contact with the oxide semiconductor film. In a graph showing the amount of change in the threshold voltage of the transistor with respect to stress time, the exponent of the power-law approximation line of the change value of the threshold voltage is -0.1 or more and 0.3 or less, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.3 V.

[0013] Note that the gate insulating film or the protective film has a region or a portion where the spin density measured by the electron spin resonance method (ESR) is less than 1×10 spins / cm 18 3 and preferably less than 1×10 17 spins / cm 3 and more than or equal to 1×10 18 spins / cm 3 and less than.

[0014] Also, the gate insulating film or the protective film has a g value of 2 in the electron spin resonance spectrum.​​​​​​​​​ A first signal with a value of 2.037 or more and 2.039 or less, a second signal with a g-value of 2.001 or more and 2.003 or less, and a third signal with a g-value of 1.964 or more and 1.966 or less are observed in a region or part. Also, the split widths of the first signal and the second signal, and the second signal and the third signal are each approximately 5 mT in the measurement of the X band .

[0015] In addition, a signal due to nitrogen oxide is observed in the gate insulating film or the protective film. The nitrogen oxide contains nitric oxide or nitrogen dioxide

[0016] There may be a protective film, an oxide semiconductor film, and a gate insulating film between the insulating surface and the gate electrode. Or, there may be a gate electrode and a gate insulating film between the insulating surface and the oxide semiconductor film .

[0017] A pair of electrodes may be provided between the oxide semiconductor film and the protective film. Or, a pair of electrodes may be provided between the oxide semiconductor film and the gate insulating film . [Advantages of the Invention]

[0018] According to one aspect of the present invention, fluctuations in the electrical characteristics of a transistor having an oxide semiconductor film can be suppressed while improving reliability. Or, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a novel semiconductor device or the like can be provided. Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects can be obtained from the description in the specification, drawings, claims, etc . ​​​​​It will become obvious by itself, and it is possible to extract effects other than these from the descriptions in the specification, drawings, claims, etc.

Brief Description of Drawings

[0019]

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Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the descriptions of the embodiments and examples shown below. Also in the embodiments and examples described below, for the same part or parts having the same function the same reference numerals or the same hatching patterns are commonly used among different drawings, and the repeated explanation thereof will be omitted.

[0021] In each of the figures described in this specification, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. is not limited thereto.

[0022] Also, the terms such as first, second, and third used in this specification are for avoiding confusion of components and are not numerically limiting. Therefore, for example, "the first" can be appropriately replaced with "the second" or "the third" and so on for explanation.

[0023] In addition, in this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, " perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0024] In addition, in this specification, when the crystal is trigonal or rhombohedral, it is represented as a hexagonal system. That's all.

[0025] Also, the functions of "source" and "drain" may be interchanged in cases where the direction of the current changes in the circuit operation. For this reason, in this specification, the terms "source" and "drain" are assumed to be interchangeable. That's all.

[0026] Also, voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, generally, the potential difference between the potential at a certain point and the reference potential (for example, the ground potential) is simply referred to as potential or voltage, and potential and voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, potential may be read as voltage or voltage may be read as potential. That's all.

[0027] Also, since the transistor having an oxide semiconductor film is an n-channel transistor, in this specification, when the gate voltage is 0V, a transistor in which it can be considered that no drain current is flowing is defined as a transistor having normally-off characteristics. Also, A transistor in which a drain current can be considered to flow when the gate voltage is 0V is defined as a transistor having normally-on characteristics.

[0028] Note that the channel length is, for example, in the top view of the transistor, the oxide semiconductor film (or the portion where current flows in the oxide semiconductor film when the transistor is in the on state) and the gate electrode overlap region, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where the channel is formed. Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in this specification, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0029] The channel width is, for example, the region where the oxide semiconductor film (or the portion where current flows in the oxide semiconductor film when the transistor is in the on state) and the gate electrode overlap, or the length of the portion where the source and the drain face each other in the region where the channel is formed. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

[0030] Note that depending on the structure of the transistor, in the region where the channel is actually formed, the The channel width (hereinafter referred to as the effective channel width) may be different from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may become non-ignorable . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the oxide semiconductor film may be larger than the ratio of the channel region formed on the top surface of the oxide semiconductor film . In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the oxide semiconductor film may be larger than the ratio of the channel region formed on the top surface of the oxide semiconductor film . In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view . By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the oxide semiconductor film is known. Therefore, when the shape of the oxide semiconductor film is not accurately known, it is difficult to accurately measure the effective channel width .

[0031] Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the oxide semiconductor film and the gate electrode overlap, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the oxide semiconductor film is known. Therefore, when the shape of the oxide semiconductor film is not accurately known, it is difficult to accurately measure the effective channel width . Therefore, when the shape of the oxide semiconductor film is not accurately known, it is difficult to accurately measure the effective channel width . is difficult

[0032] Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the oxide semiconductor film and the gate electrode overlap, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the oxide semiconductor film and the gate electrode overlap, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the oxide semiconductor film and the gate electrode overlap, may be referred to as the "surrounded channel width (SCW: Surrounded Channel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also nel Width)". Also, in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also in this specification, when simply described as the channel width, it may refer to the surrounded channel width or the apparent channel width. Also ​​​​​​In this specification, when simply described as channel width, it refers to the effective channel width. There is. Note that the channel length, channel width, effective channel width, apparent channel width, encircled channel width, etc. can be determined by obtaining a cross-sectional TEM image, etc. and analyzing the image. etc.

[0033] Note that when calculating the field-effect mobility of a transistor, the current value per channel width, etc., the encircled channel width may be used for the calculation. In that case, the value may be different from the case of calculating using the effective channel width.

[0034] (Embodiment 1) In this embodiment, a semiconductor device which is one aspect of the present invention, and a method for manufacturing the same will be described with reference to the drawings. The transistor 10 shown in this embodiment is a bottom-gate structure transistor.

[0035] (1. Structure of Transistor) FIGS. 1(A) to 1(C) show a top view and a cross-sectional view of the transistor 10 included in the semiconductor device. FIG. 1(A) is a top view of the transistor 10, and FIG. 1(B) is a cross-sectional view between the dashed-dotted line A - B in FIG. 1(A), and FIG. 1(C) is a cross-sectional view between the dashed-dotted line C - D in FIG. 1(A). That is. Note that in FIG. 1(A), for clarity, the substrate 11, the gate insulating film 15, the protective film 21, etc. are omitted.

[0036] The transistor 10 shown in FIGS. 1(A) to 1(C) includes a gate electrode 13 provided on the substrate 11, a gate insulating film 15 formed on the substrate 11 and the gate electrode 13, an oxide semiconductor film 17 overlapping the gate electrode 13 via the gate insulating film 15, and an oxide semiconductor film 17 ​ It has a pair of electrodes 19 and 20 that are in contact with Further, a protective film 21 is formed on the gate insulating film 15, the oxide semiconductor film 1

[0037] Note that the protective film 21 contacts the oxide semiconductor film 17 on the surface opposite to the surface where the gate insulating film 15 contacts. That is, the protective film 21 contacts the oxide semiconductor film 17 in the region opposite to the region where the channel is formed (hereinafter referred to as the back-channel region) in the oxide semiconductor film 17, and has a function of protecting the back-channel region of the oxide semiconductor film 17.

[0038] In this embodiment, at least one of the films in contact with the oxide semiconductor film 17, typically the gate insulating film 1 5 and the protective film 21, is an oxide insulating film, and the oxide insulating film contains nitrogen and has a small amount of defects.

[0039] Typical examples of the oxide insulating film that contains nitrogen and has a small amount of defects include a silicon oxynitride film and an aluminum oxynitride film. Note that the silicon oxynitride film and the aluminum oxynitride film refer to films having a higher oxygen content than nitrogen in terms of their composition, and the silicon nitride oxide film and the aluminum nitride oxide film refer to films having a higher nitrogen content than oxygen in terms of their composition.

[0040] The oxide insulating film that contains nitrogen and has a small amount of defects has a region or part where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the emission amount of nitrogen oxides (NO (where x is 0 or more and 2 or less, preferably 1 or more and 2 or less) released by heat treatment. Note that nitrogen x ​​​​​​​​​Typical examples of the oxide include nitrogen monoxide, nitrogen dioxide, etc. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 30 released by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. In this specification, the emission amount of the gas released by heat treatment is, for example, the emission amount by heat treatment when the surface temperature of the film is 50 °C or higher and 650 °C or lower, preferably 50 °C or higher and 550 °C or lower. An oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 30 released by heat treatment. than the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. than the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. than the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment. In this specification, the emission amount of the gas released by heat treatment is, for example, the emission amount by heat treatment when the surface temperature of the film is 50 °C or higher and 650 °C or lower, preferably 50 °C or higher and 550 °C or lower. 50 °C or higher and 650 °C or lower, preferably 50 °C or higher and 550 °C or lower. 50 °C or higher and 650 °C or lower, preferably 50 °C or higher and 550 °C or lower.

[0041] Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. The emission amount of the gas with a mass-to-charge ratio m / z = 30 released by heat treatment of an oxide insulating film containing nitrogen and having a small amount of defects is below the detection lower limit, and the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is 1 × 10 1 × 10 18 pieces / cm 3 5 × 10 19 pieces / cm 3 Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 released by heat treatment. The emission amount of the gas with a mass-to-charge ratio m / z = 46 released by heat treatment of an oxide insulating film containing nitrogen and having a small amount of defects is below the detection lower limit, and the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is 1 × 10 1 × 10 18 pieces / cm 35×10 or less above 19 per cm 3 and has a region or a portion having a value of 5×10 or less above. Alternatively, an oxide insulating film containing nitrogen and having a small amount of defects has a gas emission amount of a mass-to-charge ratio m / z = 30 below the detection limit, and a gas emission amount of a mass-to-charge ratio m / z = 46 is below the detection limit, and a gas emission amount of a mass-to-charge ratio m / z = 17 is 1×10 or more and 5×10 or less per cm in a region or a portion having a value of 5×10 or less above. 18 per cm 3 5×10 or less above 19 per cm 3 in a region or a portion having a value of 5×10 or less above.

[0042] Here, a typical example of the gas with a mass-to-charge ratio m / z = 30 is nitric oxide. Also, a typical example of the gas with a mass-to-charge ratio m / z = 17 is ammonia. Further, a typical example of the gas with a mass-to-charge ratio m / z = 46 is nitrogen dioxide. As an example of a method for measuring the gas emission amount by heat treatment, there is a temperature-programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Here, a typical example of the gas with a mass-to-charge ratio m / z = 17 is ammonia. Also, a typical example of the gas with a mass-to-charge ratio m / z = 46 is nitrogen dioxide. As an example of a method for measuring the gas emission amount by heat treatment, there is a temperature-programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Here, a typical example of the gas with a mass-to-charge ratio m / z = 46 is nitrogen dioxide. As an example of a method for measuring the gas emission amount by heat treatment, there is a temperature-programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Here, a typical example of the gas with a mass-to-charge ratio m / z = 46 is nitrogen dioxide. As an example of a method for measuring the gas emission amount by heat treatment, there is a temperature-programmed desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). Spectroscopy)).

[0043] Here, the method for measuring the gas emission amount in TDS analysis will be described. Here, an example of the gas is taken as molecule x, and the method for measuring the emission amount of molecule x will be described. Here, an example of the gas is taken as molecule x, and the method for measuring the emission amount of molecule x will be described.

[0044] The gas emission amount when performing TDS analysis is proportional to the integrated value of the spectrum obtained by the analysis. Therefore, the gas emission amount can be calculated from the ratio of the integrated value of the spectrum of the insulating film to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of a sample containing a predetermined atom. Therefore, the gas emission amount can be calculated from the ratio of the integrated value of the spectrum of the insulating film to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of a sample containing a predetermined atom. Therefore, the gas emission amount can be calculated from the ratio of the integrated value of the spectrum of the insulating film to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of a sample containing a predetermined atom. The reference value of the standard sample is the ratio of the atomic density to the integrated value of the spectrum of a sample containing a predetermined atom.

[0045] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density, which is a standard sample, and the TDS analysis results of the insulating film, the emission amount (N x ) of molecule x in the insulating film can be obtained by the following formula 1. Here, it is assumed that all of the spectra detected by the mass-to-charge ratio obtained by TDS analysis are derived from molecule x.

[0046]

Equation

[0047] N H2 is the value obtained by converting the hydrogen molecules released from the standard sample into density. S H2 is the integrated value of the spectrum when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is set as N H2 / S H2 . S x is the integrated value of the spectrum when the insulating film is subjected to TDS analysis. α x (x is the molecular species.) is a coefficient that affects the spectrum intensity in TDS analysis and varies depending on the type of molecule. For details of formula 1, refer to Japanese Patent Laid-Open No. 6-275697. Note that the emission amount of molecule x in the above insulating film is measured using the temperature-programmed desorption analysis device EMD-WA1000S / W manufactured by Denso Kagaku Co., Ltd., using a silicon wafer containing 9.62×10 16 atoms / cm 2 of hydrogen atoms as a standard sample.

[0048] Also, in the above formula 1, by substituting the integrated value of the spectrum when the emission amounts of nitric oxide, nitrogen dioxide, or ammonia are subjected to TDS analysis into S , the emission amounts of nitric oxide, nitrogen dioxide, or ammonia can be obtained. x

[0049] In the TDS analysis, the emission amount of the gas (nitric oxide) with a mass-to-charge ratio m / z = 30 The detection limit is 1×10 17 pieces / cm 3 , and a lower detection limit is 5×10 16 pieces / cm 3 , A lower detection limit is 4×10 16 pieces / cm 3 , and a lower detection limit is 1×10 16 pieces / cm 3 .

[0050] Also, in the TDS analysis, the emission amount of the gas (nitrogen dioxide) with a mass-to-charge ratio m / z = 46 The detection limit is 1×10 17 pieces / cm 3 , and a lower detection limit is 5×10 16 pieces / cm 3 , A lower detection limit is 4×10 16 pieces / cm 3 , and a lower detection limit is 1×10 16 pieces / cm 3 .

[0051] Also, in the TDS analysis, the emission amount of the gas (ammonia) with a mass-to-charge ratio m / z = 17 The detection limit is 5×10 17 pieces / cm 3 , and a lower detection limit is 1×10 17 pieces / cm 3 is .

[0052] In addition, when the sample contains water, the spectrum obtained by TDS analysis of the sample splits into fragments with mass-to-charge ratios 18, 17, and 16. The fragment pattern coefficient can be determined from the intensity ratio of each mass-to-charge ratio. For mass-to-charge ratios 18, 17, and 16 ​The fragment pattern coefficients are 100, 23, and 1, respectively. That is, in the spectrum of mass-to-charge ratio 1 7, the total intensity of the ammonia and water release amounts is observed. Therefore the ammonia release amount can be obtained by subtracting 0.23 times the release amount of the gas with a mass-to-charge ratio of m / z = 18 from the release amount of the gas with a mass-to-charge ratio of m / z = 17 in the TDS analysis . In this specification, the mass-to-charge ratio m / z = 17 is explained as the release amount of only ammonia excluding the water release amount .

[0053] Note that as the protective film 21, by using an oxide insulating film with a larger ammonia release amount than the nitrogen oxide release amount released by heat treatment, typically as the protective film 21, an oxide insulating film with a release amount of the gas with a mass-to-charge ratio of m / z = 17 of 1×10 or more 18 per cm 3 and 5×10 19 or less 3 per cm is used, in the heat treatment in the manufacturing process the reaction formulas (A-1) and (A-2) occur, and the nitrogen oxide is desorbed as nitrogen gas. As a result, the nitrogen concentration and the nitrogen oxide content of the protective film 21 can be reduced. In addition, it is possible to reduce the carrier traps at the interface between the gate insulating film 15 or the protective film 21 and the oxide semiconductor film 17. Also, it is possible to reduce the variation in the threshold voltage of the transistors included in the semiconductor device and reduce the variation in the electrical characteristics of the transistors .

[0054]

Chemical formula

[0055] ​​ [Chemical formula]

[0056] In addition, an oxide insulating film containing nitrogen and having a small amount of defects has, after heat treatment, a g value of 2.037 or more and 2.039 or less in the spectrum obtained by measurement with an ESR of 100 K or less, a first signal with a g value of 2.001 or more and 2.003 or less, and a g value of 1.964 or more and 1.966 or less of the third signal is observed. The split widths of the first signal and the second signal, and the split widths of the second signal and the third signal are about 5 mT in the X-band ESR measurement. Also, the first signal with a g value of 2.037 or more and 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less, and the total spin density of the third signal with a g value of 1.964 or more and 1.966 or less is less than 1×10 18 spins / cm 3 and typically is 1×10 17 spin s / cm 3 or more and less than 1×10 18 spins / cm 3 .

[0057] In addition, in the ESR spectrum at 100 K or less, the first signal with a g value of 2.037 or more and 2.039 or less , the second signal with a g value of 2.001 or more and 2.003 or less, and the g value of 1 .964 or more and 1.966 or less of the third signal correspond to signals caused by nitrogen oxides (NO x , where x is 0 or more and 2 or less, preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include , nitric oxide, nitrogen dioxide, etc. That is, the first with a g value of 2.037 or more and 2.039 or less The total spin density of the first signal with a g-value of 2.001 or more and 2.003 or less, the second signal with a g-value of 1.9 64 or more and 1.966 or less, the smaller the total spin density of the third signal, the lower the content of nitrogen oxides in the oxide insulating film. It can be said that the content of nitrogen oxides in the oxide insulating film is small.

[0058] Further, at least one of the gate insulating film 15 and the protective film 21 has a nitrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) of 6× 10 atoms / cm 20 atoms / cm 3 or less, which is preferable. As a result, in at least one of the gate insulating film 15 and the protective film 21, it becomes difficult to generate nitrogen oxides, and carrier traps at the interface between the gate insulating film 15 or the protective film 21 and the oxide semiconductor film 17 can be reduced. Further, it is possible to reduce the variation in the threshold voltage of the transistor included in the semiconductor device, and it is possible to reduce the variation in the electrical characteristics of the transistor.

[0059] In the transistor 10 having an oxide insulating film in which the gate insulating film 15 or the protective film 21 contains nitrogen and has a small amount of defects, a gate BT stress test is performed by applying a positive voltage or a negative voltage to the gate. The power approximation line L1 representing the absolute value (|ΔVth|) of the variation amount of the threshold voltage with respect to the test time (hereinafter also referred to as the stress time) before and after the BT stress test is shown in FIG. 2. In addition, when the test time (stress time) and the variation amount of the threshold voltage are plotted on a graph, the plotted values can be approximated by a power approximation line, and the power approximation line becomes a straight line on a log-log graph. The exponent of the power approximation line corresponds to the slope of the straight line in the log-log graph. ​Figure 2 is a double logarithmic graph. The horizontal axis represents the logarithm of the stress time, and the vertical axis represents the change in the threshold voltage. The logarithm of the absolute value of the momentum is represented. As for the conditions of the stress test, for example, when a display device is used as a semiconductor device, a maximum operating temperature of 60°C and a maximum drive voltage of 30V are applied, and conditions for applying stress for an arbitrary time, for example, 100 hours, can be used.

[0060] Here, the measurement method of the gate BT stress test will be described. First, the substrate temperature is constantly maintained at an arbitrary temperature (hereinafter referred to as the stress temperature), and the Vg-Id characteristics in the initial characteristics of the transistor are measured.

[0061] Next, while maintaining the substrate temperature at the stress temperature, a pair of electrodes that function as the source electrode and the drain electrode of the transistor are set to the same potential, and a potential different from that of the pair of electrodes is applied to the gate electrode for a certain period of time (hereinafter referred to as the stress time). Next, while maintaining the substrate temperature at the stress temperature, the Vg-Id characteristics of the transistor are measured. As a result, the difference in the threshold voltage and the shift value in the electrical characteristics before and after the gate BT stress test can be obtained as the amount of variation.

[0062] Note that a stress test in which a negative voltage is applied to the gate electrode is called a minus gate BT stress test (dark minus stress), and a stress test in which a positive voltage is applied is called a plus gate BT stress test (dark plus stress). Also, a stress test in which a negative voltage is applied to the gate electrode while irradiating light is called a photo minus gate BT stress test (photo minus stress), and a stress test in which a positive voltage is applied is called a photo plus gate BT stress test (photo plus stress). (photo plus stress). (photo plus stress). ​

[0063] In FIG. 2, the power approximation line L1 is a straight line on a double logarithmic graph, so the horizontal and vertical axes When the intervals between the graduations are equal, the power approximation line L 1 and the straight line when there is no change in threshold voltage with respect to stress time, i.e., as shown in FIG. The angle θ1 between the power function and the dashed line L2, whose exponent is 0, is within the range of θ2 and the stress |ΔVth| at 0.1 hour is less than 0.3 V, preferably less than 0.1 V θ2 is the range enclosed by the dashed line, and is typically set when |ΔVth| is 0.1V. The angle is 20° in the positive direction and 3° in the negative direction from the line at That is, the angle is -3° or more and less than 20°, and preferably 0° or more and less than 15°. The same interval means, for example, that the stress time on the horizontal axis is 10 times longer than the normal stress time, from 0.01 hours to 0 .1 hour interval and on the vertical axis, between 0.01V and 0.1V where ΔVth is 10 times The distance between the two points is equal. Also, the positive direction for θ2 is the counterclockwise direction. It is in the direction.

[0064] As in the case of the transistor 10 of this embodiment, the change in threshold voltage with respect to stress time The angle θ1 between the power approximation line L1, which represents the absolute value of the fluctuation (|ΔVth|), and the dashed line L2 is small. The smaller the transistor, the smaller the threshold voltage fluctuation due to aging, making it a highly reliable transistor. be.

[0065] In addition, in FIG. 2, if the horizontal axis is x and the vertical axis is y, the power approximation line L1 is expressed by the following formula 2: Here, b and C are constants, and b corresponds to the exponent of the power approximation line L1.

[0066]

number

[0067] In the transistor 10 shown in this embodiment, the exponent b of the power approximation line L1 is -0.1 or more and 0.3 or less, preferably 0 or more and 0.2 or less, and when the stress time is 0.1 hour, ΔVth is less than 0.3 V, preferably less than 0.1 V.

[0068] The smaller the exponent b of the power approximation line L1, the smaller the variation in the threshold voltage due to aging, and it is a highly reliable transistor. Also, the smaller ΔVth is when the stress time is 0.1 hour, the higher the reliability of the transistor at the initial stage of operation. As a result, the exponent b of the power approximation line L1 is -0.1 or more and 0.3 or less, preferably 0 or more and 0.2 or less, and ΔVth when the stress time is 0.1 hour is less than 0.3 V, preferably less than 0.1 V, and such a transistor has high reliability.

[0069] When at least one of the gate insulating film 15 and the protective film 21 in contact with the oxide semiconductor film 17 has a low nitrogen oxide content as described above, it is possible to reduce carrier traps at the interface between the gate insulating film 15 or the protective film 21 and the oxide semiconductor film 17. As a result, it is possible to reduce the variation in the threshold voltage of the transistors included in the semiconductor device, and it is possible to reduce the variation in the electrical characteristics of the transistors.

[0070] Details of other configurations of the transistor 10 will be described below.

[0071] There is no significant limitation on the material of the substrate 11, etc., but at least it can withstand subsequent heat treatment to a certain extent. ​​It is necessary to have heat resistance. As the substrate 11, for example, various substrates can be used to form transistors. The type of substrate is not limited to a specific one. As an example of such a substrate, there are a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a bonded film, paper containing a fibrous material, or a base film. As an example of a glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, bonded films, base films, etc. include the following. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), plastics typified by polyethersulfone (PES), or synthetic resins such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyester, polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, or papers. In particular, by manufacturing transistors using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., transistors with less variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured with such transistors, power consumption reduction of the circuit or high integration of the circuit can be achieved.

[0072] Further, a flexible substrate may be used as the substrate 11, and the transistor 10 may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 10. After partially or completely completing a semiconductor device on the release layer, it can be separated from the substrate 11 and transferred to another substrate. At this time, the transistor 10 can also be transferred to a substrate with poor heat resistance or a flexible substrate. Note that, for example, the above-described release layer may have a laminated structure of an inorganic film composed of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on the substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, there are a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a durable device, impart heat resistance, reduce weight, or make it thinner. Note that an underlayer insulating film may be provided between the substrate 11 and the gate electrode 13. Examples of the underlayer insulating film include silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, etc. Note that, as the underlayer insulating film, silicon nitride, gallium oxide, hafnium oxide, yttrium oxide, etc.

[0073]

[0074] ​​​​​​​​​​​​​By using tritium, aluminum oxide, etc., impurities, typically aluminum, are removed from the substrate 11. The diffusion of potassium metal, water, hydrogen, and the like into the oxide semiconductor film 17 can be suppressed.

[0075] The gate electrode 13 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or nickel. A metal element selected from the group consisting of nickel, iron, cobalt, and tungsten, or a mixture of the above metal elements. The metal element may be an alloy having the above-mentioned metal elements or an alloy combining the above-mentioned metal elements. In addition, the present invention uses a metal element selected from one or more of manganese and zirconium. The gate electrode 13 may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a single layer structure of a copper film containing manganese, A two-layer structure in which a titanium film is laminated on an aluminum film, and a two-layer structure in which a titanium film is laminated on a titanium nitride film A two-layer structure in which a tungsten film is laminated on a titanium nitride film, a tantalum nitride film or a nitride film Two-layer structure with tungsten film laminated on tungsten oxide film, copper film on manganese-containing copper film A two-layer structure in which a titanium film is laminated, an aluminum film is laminated on the titanium film, and then A three-layer structure in which a titanium film is formed on top of the copper film containing manganese, and a copper film is laminated on top of the copper film containing manganese. There are three-layer structures, such as a copper film containing manganese on top. One selected from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film made by combining a plurality of layers, or a nitride film may be used.

[0076] The gate electrode 13 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal element may also be used.

[0077] When the protective film 21 is made of an oxide insulating film containing nitrogen and having a small amount of defects, The insulating film 15 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. ZnO, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn-based metal oxides The oxide semiconductor film 17 may be formed as a single layer or a stacked layer. In order to improve the gate insulating film 15, at least the region in contact with the oxide semiconductor film 17 is is preferably formed using an oxide insulating film.

[0078] The gate insulating film 15 is an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating layer 14, oxygen can be diffused from the oxide semiconductor film 17 to the outside, and the oxide semiconductor can be prevented from being diffused from the outside. It is possible to prevent hydrogen, water, etc. from entering the membrane 17. Examples of insulating films having such a function include an aluminum oxide film, an aluminum oxynitride film, and a gallium oxide film. GaN film, gallium oxide nitride film, yttrium oxide film, yttrium oxide nitride film, hafnium oxide Examples of the oxide film include hafnium oxide nitride film.

[0079] The gate insulating film 15 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium minate (HfAl xO y N z ) By using high-k materials such as hafnium oxide and yttrium oxide, the gate leakage of the transistor can be reduced.

[0080] The thickness of the gate insulating film 15 is 5 nm or more and 400 nm or less, more preferably 10 nm or more 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

[0081] The oxide semiconductor film 17 is formed of a metal oxide film containing at least In or Zn, Typically, it is formed of an In-Ga oxide film, an In-Zn oxide film, an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), etc.

[0082] When the oxide semiconductor film 17 is an In-M-Zn oxide, when the sum of In and M is 1 00 atomic%, the atomic ratio of In to M is preferably more than 25 atom ic% and less than 75 atomic% of M, and more preferably more than 34 atomi c% of In and less than 66 atomic% of M.

[0083] The oxide semiconductor film 17 has an energy gap of 2 eV or more, preferably 2.5 eV or more , more preferably 3 eV or more. Thus, by using an oxide semiconductor with a wide energy gap, the off-current of the transistor 10 can be reduced.

[0084] The thickness of the oxide semiconductor film 17 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0085] When the oxide semiconductor film 17 is an In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce​ 、 or in the case of Nd), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide is preferably such that In ≧ M and Zn ≧ M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn = 1:1: 1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2 are preferable. Note that the atomic ratio of the oxide semiconductor film 17 to be formed includes, as an error, a plus or minus 40% variation in the atomic ratio of the metal elements contained in the above sputtering target.

[0086] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to the metal atom to form water and forms oxygen vacancies in the lattice from which oxygen has desorbed (or the portion from which oxygen has desorbed). When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Also, part of the hydrogen may bond with oxygen bonded to the metal atom to generate electrons, which are carriers . Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics .

[0087] For this reason, it is preferable that the oxide semiconductor film 17 has as little hydrogen as possible together with oxygen vacancies. Specifically, in the oxide semiconductor film 17, the hydrogen concentration obtained by secondary ion mass spectrometry (S IMS: Secondary Ion Mass Spectrometry) is 2 × 10 atoms / cm 20 or less, preferably 5 × 10 3 atoms / cm 19 or less, preferably 1 × 10 atoms / cm 3 or less, preferably 5 × 19 10 3 or less, preferably 5 × 1018 atoms / cm 3 Hereinafter, preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, still more preferably 1×10 16 at oms / cm 3 or less. As a result, the transistor 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage becomes positive.

[0088] Further, in the oxide semiconductor film 17, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases in the oxide semiconductor film 17 and it becomes n-type. Therefore, the concentration of silicon or carbon in the oxide semiconductor film 17 (the concentration obtained by secondary ion mass spectrometry) is set to 2×10 atoms / cm 18 or less, preferably 2×10 3 17 atoms / cm 3 or less. As a result, the transistor 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage becomes positive.

[0089] Further, in the oxide semiconductor film 17, the concentration of an alkali metal or an alkaline earth metal obtained by secondary ion mass spectrometry is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, the alkali metal or alkaline earth of the oxide semiconductor film 17 It is preferable to reduce the concentration of the metalloid. As a result, the transistor 10 has electrical characteristics (also referred to as normally-off characteristics) in which the threshold voltage becomes positive.

[0090] In addition, when nitrogen is contained in the oxide semiconductor film 17, electrons as carriers are generated, the carrier density increases, and it is likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5×10 18 atoms / cm 3 or less.

[0091] By reducing the impurities in the oxide semiconductor film 17, the carrier density of the oxide semiconductor film can be reduced. Therefore, the carrier density of the oxide semiconductor film 17 is 1×10 17 per cm 3 or less, preferably 1×10 15 per cm 3 or less, more preferably 1×10 13 per cm 3 or less, still more preferably 1×10 11 per cm 3 or less.

[0092] By using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor film 17, a transistor having more excellent electrical characteristics can be manufactured. Here, a low impurity concentration and a low defect level density (less oxygen deficiency) are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor that is high-purity intrinsic or substantially high-purity intrinsic is also called. Since a transistor using a conductor has few carrier generation sources, the carrier density may be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may have an electrical characteristic (also referred to as normally-off characteristic) in which the threshold voltage is positive. In addition, a transistor using an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic may have a low trap level density because the density of defect levels is low. Also, an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has an extremely small off-current, and when the voltage (drain voltage) between the source electrode and the drain electrode is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer, that is, 1 × 10 -13 A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may be a transistor with small fluctuations in electrical characteristics and high reliability. -13

[0093] In addition, the oxide semiconductor film 17 may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0094] Note that the oxide semiconductor film 17 may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film includes, for example, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, CAAC In the case of a single-layer structure having two or more of the regions of the C-OS region and the single-crystal structure region there is. Further, the mixed film has, for example, a laminated structure of two or more of the regions of the amorphous structure region, the microcrystalline structure region, the polycrystalline structure region, the CAAC-OS region, and the single-crystal structure region in some cases.

[0095] The pair of electrodes 19 and 20 are made of a single metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, iron, cobalt, silver, tantalum, or tungsten, or an alloy having this as a main component, and are used as a single-layer structure or a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper film containing manganese, a titanium film or a titanium nitride film, and an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and further a titanium film or a titanium nitride film is formed thereon a three-layer structure, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film, and further a molybdenum film or a molybdenum nitride film is formed thereon a three-layer structure, a copper film containing manganese is laminated with a copper film thereon, and further a copper film containing manganese is formed thereon a three-layer structure and the like. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0096] ​​​​​​​​​​In this embodiment, a pair of electrodes 19 and 20 are provided between the oxide semiconductor film 17 and the protective film 21. However, they may be provided between the gate insulating film 15 and the oxide semiconductor film 17.

[0097] When the gate insulating film 15 is formed of an oxide insulating film containing nitrogen and having a small amount of defects , the protective film 21 can be formed using silicon oxide, silicon oxynitride, Ga-Zn-based metal oxide, or the like.

[0098] Further, by providing an insulating film having a blocking effect on oxygen, hydrogen, water, etc. as the protective film 21 , it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 17 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 1 7. Examples of the insulating film having a blocking effect on oxygen, hydrogen, water, etc. include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, a silicon nitride film, and the like.

[0099] The protective film 21 may have a region with a thickness of 50 nm or more and 1000 nm or less, preferably 150 nm or more and 4 00 nm or less.

[0100] <2. Manufacturing method of transistor> Next, the manufacturing method of the transistor 10 shown in FIG. 1 will be described with reference to FIG. 3. Note that , in FIG. 3, the manufacturing method of the transistor 10 will be described using the cross-sectional view in the channel length direction shown by the dashed line A-B in FIG. 1(A) and the cross-sectional view in the channel width direction shown by the dashed line C-D.

[0101] The films (insulating films, oxide semiconductor films, metal oxide films, conductive films, etc.) constituting the transistor 10 can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD). Alternatively, it can be formed by a coating method or a printing method. Representative film-forming methods include sputtering and plasma-enhanced chemical vapor deposition (PECVD), but a thermal CVD method may also be used. Examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD (atomic layer deposition).

[0102] In the thermal CVD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and a raw material gas and an oxidizing agent are simultaneously fed into the chamber and reacted near or on the substrate to deposit a film on the substrate. Thus, since the thermal CVD method is a film-forming method that does not generate plasma, it has the advantage that defects are not generated due to plasma damage.

[0103] In the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, and raw material gases for the reaction are sequentially introduced into the chamber, and film formation is performed by repeating the order of gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of raw material gases are supplied to the chamber in order, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first raw material gas so that the plurality of types of raw material gases do not mix, and then the second raw material gas is introduced. When an inert gas is introduced simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when the second raw material gas is introduced. Also, instead of introducing an inert gas, after exhausting the first raw material gas by vacuum pumping, the second The raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first single atomic layer and reacts with the second raw material gas introduced later, so that the second single atomic layer is laminated on the first single atomic layer to form a thin film.

[0104] By repeating this gas introduction sequence multiple times while controlling it until the desired thickness is reached, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing fine transistors.

[0105] As shown in FIG. 3(A), a gate electrode 13 is formed on a substrate 11.

[0106] The method for forming the gate electrode 13 is shown below. First, a conductive film is formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, etc., and a mask is formed on the conductive film by a photolithography process. Next, a part of the conductive film is etched using the mask to form the gate electrode 13. After that, the mask is removed.

[0107] Note that the gate electrode 13 may be formed by an electroplating method, a printing method, an inkjet method, etc. instead of the above formation method.

[0108] In addition, a tungsten film can be formed as a conductive film by a film forming apparatus using ALD. In this case, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0109] ​​​​​​​​Here, a tungsten film having a thickness of 100 nm is formed by sputtering. A mask is formed by a photolithography process, and a tungsten film is formed using the mask. The gate electrode 13 is formed by dry etching.

[0110] Next, a gate insulating film 15 is formed on the substrate 11 and the gate electrode 13. An oxide semiconductor film 17 is formed on the gate electrode 13 in a region overlapping the gate electrode 13 .

[0111] The gate insulating film 15 is formed by sputtering, CVD, vacuum deposition, pulsed laser deposition, or the like. It is formed by the PLD method, thermal CVD method, etc.

[0112] When a silicon oxide film or a silicon oxynitride film is formed as the gate insulating film 15, As the source gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and fluorosilane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0113] In addition, when a gallium oxide film is formed as the gate insulating film 15, the MOCVD method is used. It can be formed.

[0114] In addition, the gate insulating film 15 is formed by a thermal CVD method such as MOCVD or ALD. To form a hafnium oxide film, a liquid containing a solvent and a hafnium precursor compound (haf Hafnium alkoxide solution, typically tetrakisdimethylamidohafnium (TDMAH Two types of gases are used: vaporized benzene (O3) as the raw material gas and ozone (O3) as the oxidizing agent. The chemical formula for tetrakisdimethylamidohafnium is Hf[N(CH3)2]4. Also, examples of other material liquids include tetrakis(ethylmethylamide)hafnium and the like.

[0115] Also, when forming an aluminum oxide film as the gate insulating film 15 using a thermal CVD method such as the MOCVD method or the ALD method, a raw material gas in which a solvent and a liquid containing an aluminum precursor compound ( such as trimethylaluminum TMA) is vaporized and two types of gases, H2O as an oxidizing agent, are used. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Also, examples of other material liquids include tris(dimethylamide)aluminum, triisobutyl aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0116] Also, when forming a silicon oxide film as the gate insulating film 15 using a thermal CVD method such as the MOCVD method or the ALD method, hexachlorodisilane is adsorbed on the film formation surface, chlorine contained in the adsorbed substance is removed, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0117] Here, a silicon oxynitride film is formed as the gate insulating film 15 by a plasma CVD method.

[0118] A method for forming the oxide semiconductor film 17 will be described below. An oxide semiconductor film is formed on the gate insulating film 15 by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, a thermal CVD method, or the like. Next, after forming a mask on the oxide semiconductor film by a photolithography process, a part of the oxide semiconductor film is etched using the mask. Then, as shown in FIG. 3(B), an oxide semiconductor film 17 is formed on the gate insulating film 15 so as to overlap a part of the gate electrode 13 and be element-isolated. After that, the mask is removed. Furthermore, by using a printing method for the oxide semiconductor film 17, the element-isolated oxide semiconductor film 17 can be directly formed.

[0119] Also, by using a printing method for the oxide semiconductor film 17, the element-isolated oxide semiconductor film 17 can be directly formed.

[0120] When forming an oxide semiconductor film by a sputtering method, a power supply device for generating plasma can be appropriately an RF power supply device, an AC power supply device, a DC power supply device, etc. Furthermore, for the sputtering gas, a noble gas (typically argon), oxygen gas, or a mixed gas of a noble gas and oxygen gas can be appropriately used. In the case of a mixed gas of a noble gas and oxygen gas, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0121] Also, the target may be appropriately selected according to the composition of the oxide semiconductor film to be formed. In addition, when forming an oxide semiconductor film, for example, when using a sputtering method, the substrate temperature is set to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 350°C or lower, and by forming the oxide semiconductor film, a CAAC-OS film can be formed. Furthermore, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0122] By suppressing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. .

[0123] In addition, when forming an oxide semiconductor film, for example, when using a sputtering method, the substrate temperature is 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 350°C or lower, and by forming the oxide semiconductor film, a CAAC-O S film can be formed.

[0124] In addition, in order to form a CAAC-OS film, it is preferable to apply the following conditions.

[0125] By suppressing the incorporation of impurities during film formation, it is possible to suppress the breakdown of the crystal state due to impurities. It is possible. For example, the impurity concentration (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber may be reduced. Also, the impurity concentration in the film formation gas may be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0126] Moreover, by increasing the oxygen ratio in the film formation gas and optimizing the power, plasma damage during film formation is preferably reduced. The oxygen ratio in the film formation gas is 30% by volume or more, preferably 100 % by volume.

[0127] As an example of the sputtering target, an In-Ga-Zn-based metal oxide target is shown below.

[0128] Also, after forming the oxide semiconductor film, a heat treatment may be performed to dehydrogenate or dehydrate the oxide semiconductor film. The temperature of the heat treatment is typically 150°C or higher and less than the substrate distortion point, preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower. .

[0129] The heat treatment is performed in an inert gas atmosphere containing a noble gas such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, after heating in an inert gas atmosphere, it may be heated in an oxygen atmosphere. Note that it is preferable that the above inert atmosphere and oxygen atmosphere do not contain hydrogen, water, etc. The treatment time is 3 minutes or more and 24 hours or less.

[0130] For the heat treatment, an electric furnace, an RTA apparatus, etc. can be used. By using an RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the distortion point of the substrate for a limited short time. Therefore, the heating treatment time can be shortened.

[0131] ​​ By forming a film while heating an oxide semiconductor film, and further after forming the oxide semiconductor film , by performing a heat treatment, in the oxide semiconductor film, the hydrogen concentration is 5×10 19 atoms / cm 3 or less, preferably 1×10 19 atoms / cm 3 or less, preferably 5×10 1 8 atoms / cm 3 or less, preferably 1×10 18 atoms / cm 3 or less, preferably is 5×10 17 atoms / cm 3 or less, preferably 1×10 16 atoms / cm 3 can be set to be less than or equal to the above value.

[0132] When forming an oxide semiconductor film, for example, an InGaZnO X (X>0) film using an ALD film forming apparatus, In(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form an InO 2 layer, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer , and then Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, these gases can be mixed to form a mixed compound layer such as an InGaO2 layer , an InZnO2 layer, a GaInO layer, a ZnInO layer, a GaZnO layer, etc. Note that instead of O3 gas, H2O gas bubbled with an inert gas such as Ar can be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3) 3 gas, In(C2H5)3 gas can be used. Also, instead of Ga(CH3)3 gas 3 gas, Ga(CH3)3 gas Alternatively, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0133] Here, after forming an oxide semiconductor film with a thickness of 35 nm by a sputtering method, a mask is formed on the oxide semiconductor film, and a part of the oxide semiconductor film is selectively etched. Next, after removing the mask, heat treatment is performed in a mixed gas atmosphere containing nitrogen and oxygen to form the oxide semiconductor film 17.

[0134] Note that the heat treatment is performed at a temperature higher than 350 °C and 650 °C or lower, preferably 450 °C or higher and 600 °C or lower, so that the CAAC conversion rate described later is 70% or higher and less than 100%, preferably 80% or higher and less than 100%, preferably 90% or higher and less than 100%, more preferably 95% or higher and 98% or lower, to obtain an oxide semiconductor film. Also, it is possible to obtain an oxide semiconductor film with a reduced content of hydrogen, water, etc. That is, an oxide semiconductor film with a low impurity concentration and a low defect level density can be formed.

[0135] Next, as shown in FIG. 3(C), a pair of electrodes 19 and 20 are formed.

[0136] The method for forming the pair of electrodes 19 and 20 is shown below. First, a conductive film is formed by a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. Next, a mask is formed on the conductive film by a photolithography process. Next, the conductive film is etched using the mask to form a pair of electrodes 19 and 20. After this, the mask is removed.

[0137] Here, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a thickness ​A titanium film having a thickness of 100 nm is then laminated on the titanium film by sputtering. A mask is formed by a photolithography process, and a tungsten film and an aluminum film are formed by using the mask. The aluminum film and the titanium film are dry etched to form a pair of electrodes 19 and 20 .

[0138] After the pair of electrodes 19 and 20 are formed, a heat treatment may be performed. The heat treatment may be performed under the same conditions as those of the heat treatment performed after the formation of the oxide semiconductor film 17. can.

[0139] After the pair of electrodes 19 and 20 are formed, a cleaning process is performed to remove etching residues. By carrying out this cleaning process, a short circuit between the pair of electrodes 19 and 20 is suppressed. The cleaning process can be carried out using TMAH (Tetramethylammonium hydroxide). Alkaline solutions such as hydrofluoric acid, oxalic acid, phosphoric acid, etc. This can be done using an acidic solution of, or water.

[0140] Next, a protective film 21 is formed on the oxide semiconductor film 17 and the pair of electrodes 19 and 20. The film 21 can be formed by a sputtering method, a CVD method, a vapor deposition method, or the like.

[0141] When forming an oxide insulating film containing nitrogen and having few defects as the protective film 21, the nitrogen As an example of an oxide insulating film that contains silicon and has few defects, a silicon oxynitride film is formed by CVD. In this case, the source gas is a deposition gas containing silicon. It is preferable to use a gas containing silicon and an oxidizing gas. Examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. There are nitrogen dioxide, nitrogen monoxide, etc.

[0142] Also, the oxidizing gas with respect to the depositing gas is made to be more than 20 times and less than 100 times, preferably 4 0 times or more and 80 times or less, and the pressure in the processing chamber is made to be less than 100 Pa, preferably 50 Pa or less By using a CVD method, an oxide insulating film containing nitrogen and having a small amount of defects can be formed This can be achieved.

[0143] Here, the temperature for holding the substrate 11 is set to 220°C, silane with a flow rate of 50 sccm and dinitrogen monoxide with a flow rate of 2000 sccm are used as source gases, the pressure in the processing chamber is set to 20 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz, 100 W (as the power density, it is 1. 6×10 -2 W / cm 2 ) and a plasma CVD method is used to form a silicon oxynitride film This is done.

[0144] Also, as the protective film 21, in the case of forming an oxide insulating film containing nitrogen and having a small amount of defects, in addition to the depositing gas containing silicon and the oxidizing gas as source gases, ammonia may be used. As a result, a film having a region with a large emission amount of a gas with a mass-to-charge ratio m / z = 17 (typically ammonia) can be formed. This is done.

[0145] For example, the temperature for holding the substrate 11 is set to 220°C, silane with a flow rate of 30 sccm, a flow rate of 4 000 sccm of dinitrogen monoxide, and ammonia with a flow rate of 100 sccm are used as source gases, the pressure in the processing chamber is set to 40 Pa, and the high-frequency power supplied to the parallel plate electrodes is 13.56 MHz and 150 W (as the power density, it is 2.4×10 -2 W / cm 2 ) and a plasma CVD method is It is used to form a silicon oxynitride film.

[0146] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and below the substrate distortion point, preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 450 °C or lower. By this heat treatment, it is possible to release water, hydrogen, etc. contained in the protective film 21.

[0147] Here, a heat treatment is performed at 350°C for 1 hour in a mixed gas atmosphere containing nitrogen and oxygen. .

[0148] Next, a heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and below the substrate distortion point, preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 450 °C or lower.

[0149] Through the above steps, a transistor with reduced threshold voltage variation can be fabricated. Also, a transistor with reduced electrical property variation can be fabricated.

[0150] <Modification Example 1> A modification of the transistor 10 shown in this embodiment will be described with reference to FIG. 4. This modification The transistor described in the example is an example where the gate insulating film or the protective film has a laminated structure. will be described.

[0151] In a transistor using an oxide semiconductor film, oxygen deficiency contained in the oxide semiconductor film leads to poor electrical properties of the transistor. For example, a transistor using an oxide semiconductor film containing oxygen deficiency in the film tends to have a threshold voltage that fluctuates in the negative direction and is prone to non-maryon characteristics. This is because charges are caused by oxygen deficiency contained in the oxide semiconductor.​ This is because it causes [the situation] and reduces the resistance.

[0152] In addition, when the oxide semiconductor film contains oxygen vacancies, with time-dependent changes and bias temperature stress tests (hereinafter also referred to as the BT (Bias-Temperature) stress test), there is a problem that the electrical characteristics of the transistor, typically the amount of variation in the threshold voltage, increases. There is.

[0153] Therefore, as part of the protective film, by providing an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition, a transistor with excellent electrical characteristics that suppresses the negative shift of the threshold voltage can be fabricated. Also, a highly reliable transistor with little variation in electrical characteristics due to time-dependent changes and photo-gate BT stress tests can be fabricated. can be.

[0154] The transistor 10a shown in FIG. 4(A) is characterized in that the protective film 21 has a multilayer structure. Specifically, the protective film 21 has an oxide insulating film 23, an oxide insulating film 25 containing more oxygen than oxygen satisfying the stoichiometric composition, and a nitride insulating film 27. The oxide insulating film 23 in contact with the oxide semiconductor film 17 is an oxide insulating film containing nitrogen and having a small amount of defects, which can be used for at least one of the gate insulating film 15 and the protective film 21 of the transistor 10. It is characterized by being.

[0155] The oxide insulating film 25 is formed using an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition desorbs a part of oxygen by heating. More oxygen than oxygen satisfying the stoichiometric composition The oxide insulating film containing oxygen is analyzed by TDS (thermal desorption spectrometry) to determine the amount of oxygen converted to oxygen atoms. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 at oms / cm 3 The oxide insulating film is as described above. The surface temperature should be in the range of 100°C to 700°C or 100°C to 500°C. preferable.

[0156] The oxide insulating film 25 has a thickness of 30 nm to 500 nm, preferably 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or more and 400 nm or less can be used.

[0157] The oxide insulating film 25 is placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180° C. or higher and 280° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber at 100 Pa or more and 250 Pa or less. More preferably, the pressure is set to 100 Pa or more and 200 Pa or less. .17W / cm 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 End 0.35W / cm 2 Under the following conditions of high frequency power supply, silicon oxide film or oxide A silicon nitride film is formed.

[0158] As the source gas of the oxide insulating film 25, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of deposition gases containing silicon include silane, disilane, Examples of oxidizing gases include trisilane, fluorinated silane, etc. Examples of oxidizing gases include oxygen, ozone, and nitrous oxide. There is nitrogen dioxide and the like.

[0159] As the film formation conditions of the oxide insulating film 25, by supplying the high-frequency wave power with the above power density in the processing chamber with the above pressure, the decomposition efficiency of the source gas in the plasma increases, the oxygen radicals increase, and the oxidation of the source gas proceeds. Therefore, the oxygen content in the oxide insulating film 25 becomes more than the stoichiometric composition. On the other hand, in the film formed at the above temperature, since the bonding force between silicon and oxygen is weak, a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result, an oxide insulating film can be formed that contains more oxygen than the oxygen that satisfies the stoichiometric composition and a part of the oxygen desorbs by heating. Furthermore, an oxide insulating film 23 is provided on the oxide semiconductor film 17. For this reason, in the formation process of the oxide insulating film 25, the oxide insulating film 23 serves as a protective film for the oxide semiconductor film 17. As a result, it is possible to form the oxide insulating film 25 using high-frequency power with a high power density while reducing the damage to the oxide semiconductor film 17. In addition, in the subsequent heat treatment process, a part of the oxygen contained in the oxide insulating film 25 can be moved to the oxide semiconductor film 17 to further reduce the amount of oxygen vacancies contained in the oxide semiconductor film 17. The nitride insulating film 27 uses at least a film having a blocking effect on hydrogen and oxygen. Furthermore, preferably, it has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the nitride insulating film 27, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 17 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 17. As a result of the weak bonding force between silicon and oxygen, a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result, an oxide insulating film can be formed that contains more oxygen than the oxygen that satisfies the stoichiometric composition and a part of the oxygen desorbs by heating. Furthermore, an oxide insulating film 23 is provided on the oxide semiconductor film 17. For this reason, in the formation process of the oxide insulating film 25, the oxide insulating film 23 serves as a protective film for the oxide semiconductor film 17. As a result, it is possible to form the oxide insulating film 25 using high-frequency power with a high power density while reducing the damage to the oxide semiconductor film 17. In addition, in the subsequent heat treatment process, a part of the oxygen contained in the oxide insulating film 25 can be moved to the oxide semiconductor film 17 to further reduce the amount of oxygen vacancies contained in the oxide semiconductor film 17. The nitride insulating film 27 uses at least a film having a blocking effect on hydrogen and oxygen. Furthermore, preferably, it has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the nitride insulating film 27, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 17 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 17.

[0160] The nitride insulating film 27 uses at least a film having a blocking effect on hydrogen and oxygen. Furthermore, preferably, it has a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. By providing the nitride insulating film 27, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 17 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 17. As a result, it is possible to form the oxide insulating film 25 using high-frequency power with a high power density while reducing the damage to the oxide semiconductor film 17. In addition, in the subsequent heat treatment process, a part of the oxygen contained in the oxide insulating film 25 can be moved to the oxide semiconductor film 17 to further reduce the amount of oxygen vacancies contained in the oxide semiconductor film 17.

[0161] As the nitride insulating film 27, a film having a thickness of 50 nm or more and 300 nm or less, preferably 100 n m or more and 200 nm or less, such as silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. is available.

[0162] Note that instead of the nitride insulating film 27, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. As the oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc., there are aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. is available.

[0163] The nitride insulating film 27 can be formed by using a sputtering method, a CVD method, etc.

[0164] When forming a silicon nitride film by plasma CVD as the nitride insulating film 27, a deposition gas containing silicon, nitrogen, and ammonia are used as source gases. By using a small amount of ammonia compared to nitrogen as the source gas, ammonia dissociates in the plasma, and active species are generated. The active species break the bonds between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bond between silicon and nitrogen is promoted, the bond between silicon and hydrogen is reduced, defects are reduced, and a dense silicon nitride film can be formed. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is large, the decomposition of the deposition gas containing silicon and nitrogen respectively does not proceed, the silicon and hydrogen bonds remain, defects increase, and a rough silicon nitride film is formed. For these reasons, a dense silicon nitride film with fewer silicon-hydrogen bonds and fewer defects can be formed. On the other hand, if the amount of ammonia in the source gas is large relative to nitrogen, the decomposition of the deposition gas containing silicon and nitrogen respectively does not proceed, the silicon and hydrogen bonds remain, resulting in an increase in defects and the formation of a rough silicon nitride film. For these reasons, ​​In the source gas, the flow rate ratio of nitrogen to ammonia is 5 or more and 50 or less, preferably 10 or more and 50 or less.

[0165] The transistor 10b shown in FIG. 4(B) has a gate insulating film 15 in which a nitride insulating film 29 and an oxide insulating film 31 containing nitrogen are laminated, and the oxide insulating film 31 in contact with the oxide semiconductor film 17 is an oxide insulating film containing nitrogen and having a small amount of defects.

[0166] As the nitride insulating film 29, it is preferable to use a film having a blocking effect on water, hydrogen, etc. Alternatively, as the nitride insulating film 29, it is preferable to use a film having a small amount of defects. Typical examples of the nitride insulating film 29 include silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc.

[0167] Note that by using a silicon nitride film for the nitride insulating film 29, the following effects can be obtained. The silicon nitride film has a higher relative dielectric constant than the silicon oxide film, and since the film thickness required to obtain the same capacitance is large, the gate insulating film 15 can be physically thickened. Therefore, a decrease in the breakdown voltage of the transistor 10b can be suppressed, and further, the breakdown voltage can be improved, and electrostatic breakdown of the semiconductor device can be suppressed.

[0168] In a transistor using an oxide semiconductor film, if there are trapping levels (also referred to as interface levels) in the gate insulating film 15, it causes fluctuations in the electrical characteristics of the transistor, typically fluctuations in the threshold voltage. As a result, there is a problem that the electrical characteristics vary from transistor to transistor. Therefore, by using a silicon nitride film with a small amount of defects for the nitride insulating film 29, the threshold Fluctuations in the threshold voltage and variations in the electrical characteristics of the transistor can be reduced.

[0169] Further, the nitride insulating film 29 may be formed in a laminated structure. For example, as the first silicon nitride film a silicon nitride film with a small amount of defects is used, and a silicon nitride film with a small amount of hydrogen molecule emission and ammonia molecule emission is provided as the second silicon nitride film on the first silicon nitride film. Thus, as the gate insulating film 15, a gate insulating film with a small amount of defects and a small amount of hydrogen molecule and ammonia molecule emission can be formed. As a result, the movement of hydrogen and nitrogen contained in the gate insulating film 15 to the oxide semiconductor film 17 can be suppressed.

[0170] Such a nitride insulating film 29 is preferably formed by laminating silicon nitride films using a two-step formation method. First, a first silicon nitride film with a small amount of defects is formed by plasma CVD using a mixed gas of silane, nitrogen, and ammonia as the source gas. By using the flow rate ratio of the source gas as in the nitride insulating film 27 described above, a silicon nitride film with a small amount of hydrogen molecule emission and ammonia molecule emission can be formed as the second silicon nitride film.

[0171] <Modification 2> A modification of the transistor 10 shown in this embodiment will be described with reference to FIG. 5. The transistor 10 shown in this embodiment was a channel etch type transistor, but the transistor 10c described in this modification is a channel protection type transistor.

[0172] The transistor 10c shown in FIG. 5(A) includes a gate electrode 13 provided on a substrate 11, ​​​​​​A gate insulating film 15 formed on a substrate 11 and a gate electrode 13, and an oxide semiconductor film 17 overlapping the gate electrode 13 with the gate insulating film 15 interposed therebetween, an insulating film 33 on the gate insulating film 15 and the oxide semiconductor film 17, and a pair of electrodes 19, 20 in contact with the oxide semiconductor film 17 at an opening of the insulating film 33. Specifically, the transistor 10d shown in FIG. 5(B) has an insulating film 35 formed on the oxide semiconductor film 17 and a pair of electrodes 19, 20 formed at ends of the insulating film 35 and in contact with the oxide semiconductor film 17. When forming the pair of electrodes 19, 20, a part of the oxide semiconductor film 17, typically the back channel region, is covered by the insulating films 33, 35. Therefore, the back channel region of the oxide semiconductor film 17 is not damaged by the etching for forming the pair of electrodes 19, 20. Furthermore, by using the insulating films 33, 35 as oxide insulating films containing nitrogen and having a small amount of defects, fluctuations in electrical characteristics can be suppressed, and a transistor with improved reliability can be fabricated.

[0173] Note that the transistor 10d shown in FIG. 5(B) has an insulating film 35 formed on the oxide semiconductor film 17 and a pair of electrodes 19, 20 formed at ends of the insulating film 35 and in contact with the oxide semiconductor film 17. When forming the pair of electrodes 19, 20, a part of the oxide semiconductor film 17, typically the back channel region, is covered by the insulating films 33, 35. Therefore, the back channel region of the oxide semiconductor film 17 is not damaged by the etching for forming the pair of electrodes 19, 20. Furthermore, by using the insulating films 33, 35 as oxide insulating films containing nitrogen and having a small amount of defects, fluctuations in electrical characteristics can be suppressed, and a transistor with improved reliability can be fabricated.

[0174] For the modified examples of the transistor 10 shown in this embodiment, they will be described with reference to FIG. 6. The transistor 10 shown in this embodiment was a transistor having one gate electrode, whereas the transistor 10e described in this modified example has two gate electrodes sandwiching an oxide semiconductor film. FIGS. 6(A) to 6(C) show a top view and a cross-sectional view of the transistor 10e included in the semiconductor device. FIG. 6(A) is a top view of the transistor 10e, and FIG. 6(B) is a cross-sectional view taken along line A-A' in FIG. 6(A). FIG. 6(C) is a cross-sectional view taken along line B-B' in FIG. 6(A). In FIGS. 6(A) to 6(C), reference numeral 11 denotes a substrate, reference numeral 13 denotes a gate electrode, reference numeral 15 denotes a gate insulating film, reference numeral 17 denotes an oxide semiconductor film, reference numeral 33 denotes an insulating film, reference numeral 35 denotes an insulating film, and reference numerals 19 and 20 denote a pair of electrodes. The transistor 10e has two gate electrodes 13a and 13b sandwiching the oxide semiconductor film 17.

[0175] <Modification Example 3> The modification example of the transistor 10 shown in this embodiment will be described with reference to FIG. 6. The transistor 10 shown in this embodiment was a transistor having one gate electrode, whereas the transistor 10e described in this modification example has two gate electrodes sandwiching an oxide semiconductor film. FIGS. 6(A) to 6(C) show a top view and a cross-sectional view of the transistor 10e included in the semiconductor device. FIG. 6(A) is a top view of the transistor 10e, and FIG. 6(B) is a cross-sectional view taken along line A-A' in FIG. 6(A). FIG. 6(C) is a cross-sectional view taken along line B-B' in FIG. 6(A).

[0176] In FIGS. 6(A) to 6(C), reference numeral 11 denotes a substrate, reference numeral 13 denotes a gate electrode, reference numeral 15 denotes a gate insulating film, reference numeral 17 denotes an oxide semiconductor film, reference numeral 33 denotes an insulating film, reference numeral 35 denotes an insulating film, and reference numerals 19 and 20 denote a pair of electrodes. FIG. 6(A) is a top view of the transistor 10e, and FIG. 6(B) is a cross-sectional view taken along line A-A' in FIG. 6(A). ) is a cross-sectional view between the dashed-dotted lines A - B, and FIG. 6(C) is a cross-sectional view between the dashed-dotted lines C - D in FIG. 6(A). In FIG. 6(A), for clarity, the substrate 11, the gate insulating film 15, the protective film 21, etc. are omitted.

[0177] The transistor 10e shown in FIGS. 6(B) and 6(C) is a channel etch type transistor, and includes a gate electrode 13 provided on the substrate 11, a gate insulating film 15 formed on the substrate 11 and the gate electrode 13, an oxide semiconductor film 17 overlapping the gate electrode 13 via the gate insulating film 15, and a pair of electrodes 19, 20 in contact with the oxide semiconductor film 17. Also, on the gate insulating film 15, the oxide semiconductor film 17, and the pair of electrodes 19, 20, there is a protective film 21 composed of an oxide insulating film 23, an oxide insulating film 25, and a nitride insulating film 27, and a gate electrode 37 formed on the protective film 21. The gate electrode 37 is connected to the gate electrode 13 at the openings 42, 43 provided in the gate insulating film 15 and the protective film 21. Here, as the gate insulating film 15, a nitride insulating film 29 and an oxide insulating film 31 are laminated. Also, as the protective film 21, an oxide insulating film 23, an oxide insulating film 25, and a nitride insulating film 27 are laminated. The gate insulating film 15 and the protective film 21 have a plurality of openings. Typically, as shown in FIG. 6(C), in the channel width direction, there are openings 42, 43 sandwiching the oxide semiconductor film 17. That is, the openings 42, 43 are provided outside the side surfaces of the oxide semiconductor film 17. At the openings 4 2, 43, the gate electrode 13 and the gate electrode 37 are connected. That is, in the channel width direction,

[0178] The gate insulating film 15 and the protective film 21 have a plurality of openings. Typically, as shown in FIG. 6(C), in the channel width direction, there are openings 42, 43 sandwiching the oxide semiconductor film 17. That is, as shown in FIG. 6(C), in the channel width direction, there are openings 42, 43 sandwiching the oxide semiconductor film 17. Namely, the openings 42, 43 are provided outside the side surfaces of the oxide semiconductor film 17. At the openings 4 2, 43, the gate electrode 13 and the gate electrode 37 are connected. That is, in the channel width direction, ​In the direction, the gate electrode 13 and the gate electrode 37 sandwich the oxide semiconductor film 17 with the gate insulating film 15 and the protective film 21 interposed therebetween. Also, in the channel width direction, the gate electrode 37 provided at the side surface of the oxide semiconductor film 17 and the openings 42 and 43 is positioned via the protective film 21 therein.

[0179] Note that, as shown in Fig. 6(C), in the channel width direction, the side surface of the oxide semiconductor film 17 and the gate electrode 37 face each other. Furthermore, in the channel width direction, the gate electrode 13 and the gate electrode 37 sandwich the oxide semiconductor film 17 with the gate insulating film 15 and the protective film 21, so that carriers flow not only at the interface between the gate insulating film 15 and the protective film 21 and the oxide semiconductor film 17 but also inside the oxide semiconductor film 17 in the oxide semiconductor film 17. As a result, the amount of carrier movement in the transistor 10e increases. Consequently, the on-current of the transistor 10 increases and the field-effect mobility becomes higher. Also, since the electric field of the gate electrode 37 affects the side surface of the oxide semiconductor film 17 or the end portion including the side surface and its vicinity, the generation of parasitic channels at the side surface or the end portion of the oxide semiconductor film 17 can be suppressed.

[0180] <Modification Example 4> A modification of the transistor 10 shown in the present embodiment will be described with reference to Figs. 7 and 8. The transistor 10 shown in the present embodiment has a single-layer oxide semiconductor film, whereas the transistors 10f and 10g described in this modification example have multilayer films.

[0181] Figs. 7(A) to 7(C) show a top view and a cross-sectional view of the transistor 10f included in the semiconductor device ​​​​​​The top view is shown. Fig. 7(A) is a top view of the transistor 10f, and Fig. 7(B) is a cross-sectional view taken along the dashed line A-B in Fig. 7(A ), and Fig. 7(C) is a cross-sectional view taken along the dashed line C-D in Fig. 7(A). In Fig. 7(A), for clarity, the substrate 11, the gate insulating film 15, the protective film 21, etc. are omitted. The transistor 10f shown in Fig. 7(A) has a multilayer film 45 overlapping the gate electrode 13 via the gate insulating film 15, and a pair of electrodes 19 and 20 in contact with the multilayer film 45. Also, a protective film 21 is formed over the gate insulating film 15, the multilayer film 45, and the pair of electrodes 19 and 20.

[0182] In the transistor 10f shown in Fig. 7(A), the multilayer film 45 has an oxide semiconductor film 17 and an oxide semiconductor film 46. That is, the multilayer film 45 has a two-layer structure. Also, a part of the oxide semiconductor film 17 functions as a channel region. Further, a protective film 21 is formed so as to be in contact with the multilayer film 45.

[0183] In the transistor 10f shown in this embodiment, the multilayer film 45 has an oxide semiconductor film 17 and an oxide semiconductor film 46. That is, the multilayer film 45 has a two-layer structure. Also, a part of the oxide semiconductor film 17 functions as a channel region. Further, a protective film 21 is formed so as to be in contact with the multilayer film 45. The oxide semiconductor film 46 is an oxide semiconductor film composed of one or more of the elements constituting the oxide semiconductor film 17. Therefore, interface scattering hardly occurs at the interface between the oxide semiconductor film 17 and the oxide semiconductor film 46. Accordingly, carrier movement is not inhibited at the interface, so that the field-effect mobility of the transistor is increased.

[0184] The oxide semiconductor film 46 is formed of a metal oxide containing at least In or Zn, and typically, an In-Ga oxide film, an In-Zn oxide film, an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), and is also thicker than the oxide semiconductor film 17.

[0185] The oxide semiconductor film 46 is formed of a metal oxide containing at least In or Zn, and typically, an In-Ga oxide film, an In-Zn oxide film, an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), and is also thicker than the oxide semiconductor film 17. ​​​​​​​​​​​The energy at the lower end of the conduction band is close to the vacuum level. Typically, the difference between the energy at the lower end of the conduction band of the oxide semiconductor film 46 and the energy at the lower end of the conduction band of the oxide semiconductor film 17 is 0. 05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide semiconductor film 46 and the electron affinity of the oxide semiconductor film 17 is 0.05 eV or more , 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. The oxide semiconductor film 46 preferably contains In because the carrier mobility (electron mobility) is increased. When the oxide semiconductor film 46 has Al, Ga, Y, Zr, La, Ce, or Nd in an atomic ratio higher than that of In, the following effects may be obtained. (1) The energy gap of the oxide semiconductor film

[0186] 46 is increased. (2) The electron affinity of the oxide semiconductor film 46 is decreased. (3) The diffusion of impurities from the outside is reduced. (4) Compared with the oxide semiconductor film 17 , the insulation property is increased. (5) Since Al, Ga, Y, Zr, La, Ce, or Nd is a metal element with a strong bonding force with oxygen, the generation of oxygen vacancies is less likely to occur.

[0187] When the oxide semiconductor film 46 is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, the atomic ratio of In and M is preferably such that In is less than 50 atomic %, M is more than 50 atomic%, and more preferably, In is less than 25 atomic %, and M is more than 75 atomic%.

[0188] %, M is more than 50 atomic%, and more preferably, In is less than 25 atomic %, and M is more than 75 atomic%. % or less, M is more than 75 atomic%.

[0189] In addition, when the oxide semiconductor film 17 and the oxide semiconductor film 46 are In-M-Zn oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd), compared with the oxide semiconductor film 17 the atomic ratio of M (Al, Ga, Y, Zr, La, Ce, or Nd ) contained in the oxide semiconductor film 46 is large, and typically, compared with the above atoms contained in the oxide semiconductor film 17 it is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more higher in atomic ratio.

[0190] In addition, when the oxide semiconductor film 17 and the oxide semiconductor film 46 are In-M-Zn oxide (M is Al l, Ga, Y, Zr, La, Ce, or Nd), for the oxide semiconductor film 46, In:M :Zn = x1:y1:z1 [atomic ratio], and for the oxide semiconductor film 17, In:M:Zn = x2: y2:z2 [atomic ratio], then y1 / x1 is larger than y2 / x2, and preferably, y1 / x1 is 1.5 times or more than y2 / x2. More preferably, y1 / x1 is more than 2 times larger than y2 / x2, and even more preferably, y1 / x1 is more than 3 times larger than y2 / x2. At this time, in the oxide semiconductor film, when y2 is equal to or more than x2, it is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor film.

[0191] When the oxide semiconductor film 17 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), in the target used to form the oxide semiconductor film 17 if the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1 、 x1 / y1 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less , it is preferably 1 or more and 6 or less. Note that setting z1 / y1 to be 1 or more and 6 or less makes it easier to form a CAAC-OS film as the oxide semiconductor film 17. Target Typical examples of the atomic ratio of metal elements are In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, etc.

[0192] When the oxide semiconductor film 46 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), in the target used to form the oxide semiconductor film 46 if the atomic ratio of metal elements is In:M:Zn = x2:y2:z2, then 、 x2 / y2 < x1 / y1, and z2 / y2 is 1 / 3 or more and 6 or less, preferably 1 or more and 6 or less as well. Note that setting z2 / y2 to be 1 or more and 6 or less makes it easier to form a CAAC-OS film as the oxide semiconductor film 46. Typical examples of the atomic ratio of metal elements in the target are In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, In:M:Zn = 1:3:8, In:M:Zn = 1:4:3, In:M:Z n = 1:4:4, In:M:Zn = 1:4:5, In:M:Zn = 1:4:6, In:M :Zn = 1:5:5, In:M:Zn = 1:5:6, etc.

[0193] Note that the atomic ratios of the oxide semiconductor film 17 and the oxide semiconductor film 46 each include a variation of plus or minus 40% of the above atomic ratio as an error.

[0194] The thickness of the oxide semiconductor film 46 is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less.

[0195] ​In addition, similar to the oxide semiconductor film 17, the oxide semiconductor film 46 may have, for example, a non-single crystal structure. This is good. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned -Crystalline Oxide Semiconductor) described later, a polycrystalline structure , the microcrystalline structure described later, or an amorphous structure.

[0196] The oxide semiconductor film 46 may have, for example, an amorphous structure. The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide semi conductor film having an amorphous structure has, for example, a complete amorphous structure and no crystal part.

[0197] Note that in the oxide semiconductor film 17 and the oxide semiconductor film 46, a mixed film having two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region may be formed. The mixed film may have, for example, a single-layer structure having two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Further, the mixed film may have, for example, a laminated structure having two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Here, the oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21. For this reason, even if a carrier trap is formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier trap is formed and the oxide semi

[0198] conductor film 17. As a result, electrons flowing through the oxide semiconductor film 17 are captured by the carrier trap, but there is a gap between the region where the carrier trap is formed and the oxide semiconductor film 17. As a result, even if a carrier trap is formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier trap is formed and the oxide semiconductor film 17. As a result, even if a carrier trap is formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier trap is formed and the oxide semiconductor film 17. As a result, even if a carrier trap is formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier trap is formed and the oxide semiconductor film 17. It is difficult to be captured by the rear trap and it is possible to increase the on-current of the transistor. At the same time, the field-effect mobility can be increased. Also, when electrons are captured by the carrier trap, the electrons act as negative fixed charges. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 17 and the region where the carrier trap is formed, it is possible to reduce the capture of electrons in the carrier trap, and it is possible to reduce the fluctuation of the threshold voltage.

[0199] In addition, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is difficult to form oxygen vacancies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 17.

[0200] Note that the oxide semiconductor film 17 and the oxide semiconductor film 46 are not simply laminated, but are fabricated so that a continuous junction (here, in particular, a structure in which the energy at the lower end of the conduction band changes continuously between the films) is formed. That is, a laminated structure is formed in which there are no impurities that form defect levels such as interface trap centers and recombination centers at the interface of each film. If impurities are mixed between the laminated oxide semiconductor film 17 and the oxide semiconductor film 46, the continuity of the energy band is lost, carriers are trapped at the interface, or recombine and disappear.

[0201] To form a continuous junction, a multi-chamber type film-forming apparatus equipped with a load lock chamber ​​​​​Each film is continuously laminated using a sputtering device without exposing it to the atmosphere. This is necessary. Each chamber in the sputtering device should be evacuated to a high vacuum (5 × 10 using an adsorption type vacuum exhaust pump such as a cryopump to remove impurities such as water that could become impurities for the oxide semiconductor film as much as possible. Pa to 1 × 10 -7 Pa (to about this level) is preferred. -4 Or, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas, especially gas containing carbon or hydrogen, from flowing back into the chamber from the exhaust system.

[0202] Note that instead of the multilayer film 45, a multilayer film 48 may be provided as in the transistor 10g shown in Fig. 7(D).

[0203] The multilayer film 48 has an oxide semiconductor film 47, an oxide semiconductor film 17, and an oxide semiconductor film 46 laminated in this order. That is, the multilayer film 48 has a three-layer structure. Also, the oxide semiconductor film 17 functions as a channel region.

[0204] Also, the gate insulating film 15 and the oxide semiconductor film 47 are in contact. That is, an oxide semiconductor film 47 is provided between the gate insulating film 15 and the oxide semiconductor film 17.

[0205] Also, the oxide semiconductor film 46 and the protective film 21 are in contact. That is, an oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21.

[0206] The oxide semiconductor film 47 can be appropriately formed using the same materials and formation methods as the oxide semiconductor film 46.

[0207] ​​​​​​​​The oxide semiconductor film 47 preferably has a smaller film thickness than the oxide semiconductor film 17. Oxide semi- By setting the thickness of the semiconductor film 47 to be 1 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less, it is possible to reduce the variation in the threshold voltage of the transistor.

[0208] In the transistor shown in this embodiment, an oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21. Therefore, even if carrier traps are formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier traps are formed and the oxide semiconductor film 17. As a result, electrons flowing through the oxide semiconductor film 17 are less likely to be captured by the carrier traps, the on-current of the transistor can be increased, and the field-effect mobility can be enhanced. Further, when electrons are captured by the carrier traps, the electrons act as negative fixed charges. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 17 and the region where the carrier traps are formed, it is possible to reduce the capture of electrons in the carrier traps and reduce the fluctuation of the threshold voltage. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Even if carrier traps are formed due to impurities and defects between the oxide semiconductor film 46 and the protective film 21, there is a gap between the region where the carrier traps are formed and the oxide semiconductor film 17. As a result, electrons flowing through the oxide semiconductor film 17 are less likely to be captured by the carrier traps, the on-current of the transistor can be increased, and the field-effect mobility can be enhanced. Further, when electrons are captured by the carrier traps, the electrons act as negative fixed charges. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 17 and the region where the carrier traps are formed, it is possible to reduce the capture of electrons in the carrier traps and reduce the fluctuation of the threshold voltage. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. Moreover, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17.

[0209] In addition, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. In addition, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. In addition, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17. In addition, since the oxide semiconductor film 46 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 17. Also, the oxide semiconductor film 46 is less likely to form oxygen deficiencies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen deficiency in the oxide semiconductor film 17.

[0210] Also, an oxide semiconductor film 47 is provided between the gate insulating film 15 and the oxide semiconductor film 17. and an oxide semiconductor film 46 is provided between the oxide semiconductor film 17 and the protective film 21. Therefore, the concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 47 and the oxide semiconductor film 17, the concentration of silicon or carbon in the oxide semiconductor film 17, or the concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 4 6 and the oxide semiconductor film 17 can be reduced. 6 and the oxide semiconductor film 17 can be reduced.

[0211] The transistor 10g having such a structure has extremely few defects in the multilayer film 48 including the oxide semiconductor film 17, so that the electrical characteristics of the transistor can be improved. Typically, an increase in the on-current and an improvement in the field-effect mobility are possible. Also, the variation in the threshold voltage in the gate BT stress test and the photo gate BT stress test, which are examples of the stress test, is small, and the reliability is high. In addition, the variation in the threshold voltage in the gate BT stress test and the photo gate BT stress test, which are examples of the stress test, is small, and the reliability is high. In addition, the variation in the threshold voltage in the gate BT stress test and the photo gate BT stress test, which are examples of the stress test, is small, and the reliability is high.

[0212] Note that a transistor 10h provided with a gate electrode 37 can be manufactured for the transistor 10f shown in FIG. 7(B) (see FIG. 7(E)). Alternatively, a transistor 10i provided with a gate electrode 37 can be manufactured for the transistor 10g shown in FIG. 7(D) ( see FIG. 7(F)). see FIG. 7(F)).

[0213] <Band structure of transistor> Next, the band structures of the multilayer film 45 provided in the transistor 10f shown in FIG. 7(A) and the multilayer film 48 provided in the transistor 10g shown in FIG. 7(D) will be described with reference to FIG. 8. Next, the band structures of the multilayer film 45 provided in the transistor 10f shown in FIG. 7(A) and the multilayer film 48 provided in the transistor 10g shown in FIG. 7(D) will be described with reference to FIG. 8.

[0214] Here, as an example, the oxide semiconductor film 17 has an energy gap of 3.15 eV. ​​​​Using a certain In-Ga-Zn oxide, an In-Ga-Zn oxide with an energy gap of 3 .5 eV is used as the oxide semiconductor film 46. The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300).

[0215] The energy differences between the vacuum levels and the upper valence band edges of the oxide semiconductor film 17 and the oxide semiconductor film 46 (also referred to as ionization potentials) are 8 eV and 8.2 eV, respectively. Note that the energy differences between the vacuum levels and the upper valence band edges can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultra violet Photoelectron Spectroscopy) apparatus (ULV AC-PHI VersaProbe).

[0216] Therefore, the energy differences between the vacuum levels and the lower conduction band edges of the oxide semiconductor film 17 and the oxide semiconductor film 46 (also referred to as electron affinities) are 4.85 eV and 4.7 eV, respectively.

[0217] FIG. 8(A) schematically shows a part of the band structure of the multilayer film 45 included in the transistor 10f. Here, the gate insulating film 15 and the protective film 21 are made of silicon oxide films, and the case where the multilayer film 45 is provided in contact with the silicon oxide film will be described. Note that EcI1 shown in FIG. 8(A) represents the energy of the lower conduction band edge of the silicon oxide film, EcS1 represents the energy of the lower conduction band edge of the oxide semiconductor film 17, EcS2 represents the energy of the lower conduction band edge of the oxide semiconductor film 46, and EcI2 represents the energy of the lower conduction band edge of the silicon oxide film. Also, E cI1 corresponds to the gate insulating film 15 shown in FIG. 7(B), and EcI2 corresponds to the protective film 21 shown in FIG. 7(B).

[0218] As shown in FIG. 8(A), in the oxide semiconductor film 17 and the oxide semiconductor film 46, the energy at the lower end of the conduction band changes smoothly without a barrier. In other words, it can also be said that it changes continuously. This is because the multilayer film 45 contains elements common to the oxide semiconductor film 17, and oxygen moves mutually between the oxide semiconductor film 17 and the oxide semiconductor film 46 to form a mixed layer. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined. As shown in FIG. 8(A), in the oxide semiconductor film 17 and the oxide semiconductor film 46, the energy at the lower end of the conduction band changes smoothly without a barrier. In other words, it can also be said that it changes continuously. This is because the multilayer film 45 contains elements common to the oxide semiconductor film 17, and oxygen moves mutually between the oxide semiconductor film 17 and the oxide semiconductor film 46 to form a mixed layer. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined.

[0219] As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined. As shown in FIG. 8(A), the oxide semiconductor film 17 of the multilayer film 45 becomes a well, and it can be seen that in the transistor using the multilayer film 45, the channel region is formed in the oxide semiconductor film 17. Since the energy at the lower end of the conduction band of the multilayer film 45 changes continuously, it can also be said that the oxide semiconductor film 17 and the oxide semiconductor film 46 are continuously joined.

[0220] As shown in FIG. 8(A), although trap levels due to impurities and defects may be formed near the interface between the oxide semiconductor film 46 and the protective film 21, by providing the oxide semiconductor film 46, the oxide semiconductor film 17 and the trap levels can be separated from each other. As shown in FIG. 8(A), although trap levels due to impurities and defects may be formed near the interface between the oxide semiconductor film 46 and the protective film 21, by providing the oxide semiconductor film 46, the oxide semiconductor film 17 and the trap levels can be separated from each other. As shown in FIG. 8(A), although trap levels due to impurities and defects may be formed near the interface between the oxide semiconductor film 46 and the protective film 21, by providing the oxide semiconductor film 46, the oxide semiconductor film 17 and the trap levels can be separated from each other. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable. However, when the energy difference between EcS1 and EcS2 is small, the electrons in the oxide semiconductor film 17 may reach the trap levels beyond the energy difference. When electrons are captured by the trap levels, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained, which is suitable.

[0221] FIG. 8B is a schematic diagram showing a part of the band structure of the multilayer film 45 of the transistor 10f. 8(A) is shown, which is a modified example of the band structure shown in FIG. When the protective film 21 is a silicon oxide film and the multilayer film 45 is provided in contact with the silicon oxide film, In addition, EcI1 shown in FIG. 8B is the energy of the bottom of the conduction band of the silicon oxide film. EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor film 17, and EcI2 represents The energy of the bottom of the conduction band of the silicon oxide film is shown in FIG. EcI2 corresponds to the gate insulating film 15, and EcI3 corresponds to the protective film 21 shown in FIG.

[0222] In the transistor shown in FIG. 7B, the multilayer film 45 is formed when the pair of electrodes 19 and 20 are formed. In some cases, the upper part of the oxide semiconductor film 46 is etched. The upper surface of the oxide semiconductor film 17 is in contact with the oxide semiconductor film 17 during the formation of the oxide semiconductor film 46. 46 mixed layers may form.

[0223] For example, the oxide semiconductor film 17 is an In- Ga-Zn oxide, or In-Ga-Z with In:Ga:Zn=3:1:2 [atomic ratio] n oxide as a sputtering target, and The semiconductor film 46 is an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2. , In-Ga-Zn oxide with In:Ga:Zn=1:3:4 [atomic ratio], or In: In-Ga-Zn oxide with an atomic ratio of Ga:Zn=1:3:6 was used as a sputtering target. In the case where the oxide semiconductor film is formed using the above-mentioned method, the oxide semiconductor film is more likely to be formed using the above-mentioned method than the oxide semiconductor film 17. Since the Ga content of the conductor film 46 is high, on the upper surface of the oxide semiconductor film 17, GaO x layers or mixed layers containing more Ga than the oxide semiconductor film 17 can be formed.

[0224] Therefore, even when the oxide semiconductor film 46 is etched, the Ec of EcS1 The energy of the lower end of the conduction band on the EcI2 side becomes higher, and it may be like the band structure shown in Fig. 8(B). There are cases.

[0225] When it becomes like the band structure shown in Fig. 8(B), when observing the cross section of the channel region, the multilayer film 45 may appear to be only the oxide semiconductor film 17. However, substantially, on the oxide semiconductor film 17, a mixed layer containing more Ga than the oxide semiconductor film 17 is formed, so the mixed layer can be regarded as the 1.5th layer. In addition, the mixed layer can be confirmed by analyzing the composition above the oxide semiconductor film 17, for example, by measuring the elements contained in the multilayer film 45 by EDX analysis or the like. For example, it can be confirmed by the fact that the composition above the oxide semiconductor film 17 has a higher Ga content than the composition in the oxide semiconductor film 17. That is, it can be confirmed by the fact that the composition above the oxide semiconductor film 17 has a higher Ga content than the composition in the oxide semiconductor film 17. For example, it can be confirmed by the fact that the composition above the oxide semiconductor film 17 has a higher Ga content than the composition in the oxide semiconductor film 17.

[0226] Fig. 8(C) schematically shows a part of the band structure of the multilayer film 48 of the transistor 10g. Here, the gate insulating film 15 and the protective film 21 are made of silicon oxide films, and the case where the multilayer film 48 is provided in contact with the silicon oxide film will be described. Note that EcI1 shown in Fig. 8(C) represents the energy of the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy of the lower end of the conduction band of the oxide semiconductor film 17, and EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor film 46. represents the energy of the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy of the lower end of the conduction band of the oxide semiconductor film 17, and EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor film 46. represents the energy of the lower end of the conduction band of the oxide semiconductor film 17, and EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor film 46. is shown, EcS3 represents the energy of the lower end of the conduction band of the oxide semiconductor film 47, and EcI2 represents the energy of the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the gate insulating film 15 shown in FIG. 7(D), and EcI2 corresponds to the protective film 21 shown in FIG. 7(D). As shown in FIG. 8(C), in the oxide semiconductor film 47, the oxide semiconductor film 17, and the oxide semiconductor film 46, the energy of the lower end of the conduction band changes smoothly without a barrier. In other words, it can be said that it changes continuously. This is because the multilayer film 48 contains elements common to the oxide semiconductor film 17, and oxygen moves mutually between the oxide semiconductor film 17 and the oxide semiconductor film 47, and between the oxide semiconductor film 17 and the oxide semiconductor film 46, so that a mixed layer is formed.

[0227] As shown in FIG. 8(C), in the oxide semiconductor film 47, the oxide semiconductor film 17, and the oxide semiconductor film 46, the energy of the lower end of the conduction band changes smoothly without a barrier. In other words, it can be said that it changes continuously. This is because the multilayer film 48 contains elements common to the oxide semiconductor film 17, and oxygen moves mutually between the oxide semiconductor film 17 and the oxide semiconductor film 47, and between the oxide semiconductor film 17 and the oxide semiconductor film 46, so that a mixed layer is formed.

[0228] From FIG. 8(C), it can be seen that the oxide semiconductor film 17 of the multilayer film 48 becomes a well, and in the transistor using the multilayer film 48, the channel region is formed in the oxide semiconductor film 17. Note that since the energy of the lower end of the conduction band of the multilayer film 48 changes continuously, it can also be said that the oxide semiconductor film 47, the oxide semiconductor film 17, and the oxide semiconductor film 46 are continuously joined.

[0229] Note that although trap levels may be formed due to impurities and defects in the vicinity of the interfaces between the oxide semiconductor film 17 and the protective film 21 and in the vicinity of the interfaces between the oxide semiconductor film 17 and the gate insulating film 15, as shown in FIG. 8(C), by providing the oxide semiconductor film 46 and the oxide semiconductor film 47, the oxide semiconductor film 17 and the region where the trap levels are formed are separated from each other. ​​​​​​​​​​​​​can be achieved. However, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are small, electrons in the oxide semiconductor film 17 may cross the energy difference and reach the trap level. When electrons are trapped at the trap level, negative fixed charges are generated on the surface of the oxide insulating film, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more, preferably 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, resulting in stable electrical characteristics, which is preferable. In addition, instead of the oxide semiconductor film 46, a metal oxide film formed of In-M oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd) can be used. However, in order to prevent the metal oxide film from functioning as part of the channel region, a material with a sufficiently low conductivity is used for the metal oxide film. Alternatively, for the metal oxide film, a material with an electron affinity (the energy difference between the vacuum level and the lower end of the conduction band) smaller than that of the oxide semiconductor film 17 and a conduction band

[0230] lower end energy having a difference (band offset) from the conduction band lower end energy of the oxide semiconductor film 17 is used. Also, in order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, a material in which the energy of the lower end of the conduction band of the metal oxide film is closer to the vacuum level by 0.2 eV or more, preferably 0.5 eV or more, than the energy of the lower end of the conduction band of the oxide semiconductor film 17 is preferably applied. Furthermore, by increasing the atomic ratio of the element M to In, the energy gap of the metal oxide film can be adjusted. from the oxide semiconductor film 17 and a conduction band lower end energy having a difference (band offset) from the conduction band lower end energy of the oxide semiconductor film 17 is used. Also, in order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, a material in which the energy of the lower end of the conduction band of the metal oxide film is closer to the vacuum level by 0.2 eV or more, preferably 0.5 eV or more, than the energy of the lower end of the conduction band of the oxide semiconductor film 17 is preferably applied. In addition, in order to suppress the occurrence of a difference in threshold voltage depending on the magnitude of the drain voltage, the energy of the lower end of the conduction band of the metal oxide film is preferably a material closer to the vacuum level by 0.2 eV or more, preferably 0.5 eV or more, than the energy of the lower end of the conduction band of the oxide semiconductor film 17. Moreover, by increasing the atomic ratio of the element M to In, the energy gap of the metal oxide film can be adjusted.

[0231] Moreover, by increasing the atomic ratio of the element M to In, the energy gap of the metal oxide film It is possible to increase the bandgap and decrease the electron affinity. For example, as the metal oxide film, when using a material composed of In-M oxide (M is Al, Ga, Y, Zr, La, Ce, or Nd), to form a conduction band band offset with the oxide semiconductor film 17 and suppress the formation of a channel in the metal oxide film, the metal oxide film, when In:M = x:y [atomic ratio], it is preferable that y / (x + y) is 0.75 or more and 1 or less, preferably 0.78 or more and 1 or less, more preferably 0.80 or more and 1 or less. However, even if elements other than indium, M, and oxygen, which are the main components, are mixed as impurities in the metal oxide film, the ratio of the impurities at that time is preferably 0.1% or less.

[0232] Also, when forming the metal oxide film by sputtering, by increasing the atomic ratio of element M to In, it is possible to reduce the number of particles during film formation. To reduce the number of particles, when In:M = x:y [atomic ratio], it is good that y / (x + y) is 0.90 or more, for example, 0.93. However, when forming the metal oxide film by sputtering, if the atomic ratio of M to In is too high, the insulation of the target becomes high, and film formation using DC discharge becomes difficult, and it becomes necessary to apply RF discharge. Therefore, in order to perform film formation using DC discharge that can handle a large-area substrate, it is good that y / (x + y) is 0.96 or less, preferably 0.95 or less, for example, 0.93. By applying a film formation method corresponding to a large-area substrate, the productivity of the semiconductor device can be increased.

[0233] Note that it is preferable that the metal oxide film does not contain a spinel-type crystal structure in the film. When the film of the oxide film contains a spinel-type crystal structure, the constituent elements of the pair of electrodes 19 and 20 may diffuse into the oxide semiconductor film 17 between the spinel-type crystal structure and other regions. For example, by applying In-M oxide as the metal oxide film and making the composition not contain divalent metal atoms (for example, zinc, etc.) as M, it is preferable because a metal oxide film not containing a spinel-type crystal structure can be formed. This is because, between the spinel-type crystal structure and other regions, the constituent elements of the pair of electrodes 19 and 20 may diffuse into the oxide semiconductor film 17. For example, by applying In-M oxide as the metal oxide film and making the composition not contain divalent metal atoms (for example, zinc, etc.) as M, a metal oxide film not containing a spinel-type crystal structure can be formed, which is preferable.

[0234] The film thickness of the metal oxide film is equal to or greater than the film thickness capable of suppressing the diffusion of the constituent elements of the pair of electrodes 19 and 20 into the oxide semiconductor film 17, and less than the film thickness capable of suppressing the supply of oxygen from the protective film 21 to the oxide semiconductor film 17. For example, when the film thickness of the metal oxide film is 10 nm or more, the diffusion of the constituent elements of the pair of electrodes 19 and 20 into the oxide semiconductor film 17 can be suppressed. Also, when the film thickness of the metal oxide film is 100 nm or less, oxygen can be effectively supplied from the protective film 21 to the oxide semiconductor film 17.

[0235] <Modification Example 5> A modification example of the transistor shown in this embodiment will be described with reference to FIG. 10. The transistor 10j shown in this modification example is characterized by having an oxide semiconductor film 17a and a pair of electrodes 19a and 20a formed using a multi-tone mask.

[0236] By using a multi-tone mask, it is possible to form a resist mask having a plurality of thicknesses. After forming the oxide semiconductor film 17a using the resist mask, by exposing the resist mask to oxygen plasma or the like, a part of the resist mask is removed to form a pair of electrodes. ​​​​​​​​​​It becomes a resist mask for this purpose. Therefore, the number of photolithography steps in the manufacturing process of the oxide semiconductor film 17a and the pair of electrodes 19 a, 20a can be reduced.

[0237] Note that by using a multi-tone mask, a part of the oxide semiconductor film 17a is exposed outside the pair of electrodes 19a, 20a in terms of planar shape.

[0238] Note that the configuration and method shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples.

[0239] <Modification Example 6> A modification example of the transistor shown in this embodiment will be described with reference to FIG. 9. The transistor 10k shown in this modification example has an organic insulating film 38 on the protective film 21.

[0240] As the organic insulating film 38, for example, an organic resin film such as polyimide, acrylic, polyamide, or epoxy can be used. The organic insulating film 38 preferably has a thickness of 500 nm or more and 10 μm or less.

[0241] Note that the organic insulating film 38 may be provided over the entire surface of the protective film 21. Alternatively, it may be separated for each transistor and provided so as to overlap the oxide semiconductor film 17 of each transistor. It is preferable that the organic insulating film 38 is formed separately because water from the outside does not diffuse into the semiconductor device through the organic insulating film 38.

[0242] Since the organic insulating film 38 has a thickness of 500 nm or more, the electric field generated by applying a negative voltage to the gate electrode 13 does not affect the surface of the organic insulating film 38, and the organic insulating film The surface of 38 is less likely to be positively charged. Also, even if positive charged particles contained in the air are adsorbed on the surface of the organic insulating film 38, since the organic insulating film 38 has a thickness of 500 nm or more, the electric field of the positive charged particles adsorbed on the surface of the organic insulating film 38 is less likely to affect the interface between the oxide semiconductor film 17 and the protective film 21. As a result, at the interface between the oxide semiconductor film 17 and the protective film 21, a substantially positive bias is not applied, and the change in the threshold voltage of the transistor is small. Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples. In addition, the electric field of the positive charged particles adsorbed on the surface of the organic insulating film 38 is less likely to reach the interface between the oxide semiconductor film 17 and the protective film 21 because the organic insulating film 38 is thick with a thickness of 500 nm or more. As a result, at the interface between the oxide semiconductor film 17 and the protective film 21, a substantially positive bias is not applied, and the change in the threshold voltage of the transistor is small. At the interface between the oxide semiconductor film 17 and the protective film 21, a substantially positive bias is not applied, and the change in the threshold voltage of the transistor is small. At the interface between the oxide semiconductor film 17 and the protective film 21, a substantially positive bias is not applied, and the change in the threshold voltage of the transistor is small.

[0243] Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples. Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples.

[0244] (Embodiment 2) In this embodiment, defects included in the oxide semiconductor film included in the transistor and the oxide insulating film in contact with the oxide semiconductor film will be described in relation to the deterioration of transistor characteristics. First, nitrogen oxides (hereinafter referred to as NO (x is 0 or more and 2 or less, preferably 1 or more and 2 or less)) included in the oxide insulating film in contact with the oxide semiconductor film will be described.

[0245] <1. NO x > First, nitrogen oxides (hereinafter referred to as NO (x is 0 or more and 2 or less, preferably 1 or more and 2 or less)) included in the oxide insulating film in contact with the oxide semiconductor film will be described. x First, nitrogen oxides (hereinafter referred to as NO (x is 0 or more and 2 or less, preferably 1 or more and 2 or less)) included in the oxide insulating film in contact with the oxide semiconductor film will be described.

[0246] <1-1. Transition level of NO in the oxide insulating film x > First, the transition level of point defects in a solid will be used for the description. The transition level is a concept for explaining the charged state of impurities or defects (hereinafter referred to as defect D) that form levels within the gap, and is calculated from the formation energy of the defect. That is, the transition level is a concept similar to the donor level or the acceptor level. First, the transition level of point defects in a solid will be used for the description. The transition level is a concept for explaining the charged state of impurities or defects (hereinafter referred to as defect D) that form levels within the gap, and is calculated from the formation energy of the defect. That is, the transition level is a concept similar to the donor level or the acceptor level. First, the transition level of point defects in a solid will be used for the description. The transition level is a concept for explaining the charged state of impurities or defects (hereinafter referred to as defect D) that form levels within the gap, and is calculated from the formation energy of the defect. That is, the transition level is a concept similar to the donor level or the acceptor level. First, the transition level of point defects in a solid will be used for the description. The transition level is a concept for explaining the charged state of impurities or defects (hereinafter referred to as defect D) that form levels within the gap, and is calculated from the formation energy of the defect. That is, the transition level is a concept similar to the donor level or the acceptor level.

[0247] The relationship between the formation energy and the transition level of the charge state of defect D will be described. Defect D has different formation energies depending on the charge state and also depends on the Fermi energy. The state where the defect releases one electron is denoted as D and the state where the defect captures one electron is denoted as D and the state where there is no electron movement is denoted as D + and the state where the defect captures one electron is denoted as D - and the state where there is no electron movement is denoted as D and the state where there is no electron movement is denoted as D 0 .

[0248] Defect D + , defect D 0 , defect D - The relationship between the formation energy and the transition level of each is shown in Fig. 11 (A). Also, in Fig. 11(B), for the case where defect D has an orbital with one electron occupied in the neutral state, the electron configurations of defect D , defect D + , defect D 0 , defect D - are shown respectively.

[0249] In Fig. 11(A), the dotted line represents the formation energy of defect D + , the solid line represents the formation energy of defect D 0 and the broken line represents the formation energy of defect D . The transition level represents the position of the Fermi level at which the formation energies of different charge states of defect D are equal. The position of the Fermi level at which the formation energies of defect D - become equal (i.e., the position of the intersection of the dotted line and the solid line) is denoted as ε( + / 0), and the position of the Fermi level at which the formation energies of defect D + and defect D 0 become equal (i.e., the position of the intersection of the solid line and the broken line) is denoted as ε(0 / -). Next, the transition of the energetically stable charge state of the defect when the Fermi level is changed . 0 and defect D - become equal (i.e., the position of the intersection of the solid line and the broken line) is denoted as ε(0 / -). .

[0250] Next, the transition of the energetically stable charge state of the defect when the Fermi level is changed The conceptual diagram is shown in Fig. 12. In Fig. 12, the two-dot chain line represents the Fermi level. Also, Fig. 12 In the left figure, the band diagrams in the cases where (1), (2), and (3) are each taken as the Fermi level are shown in the right figure of Fig. 12.

[0251] By knowing the transition levels of the solid, when the Fermi level is used as a parameter, it is possible to qualitatively grasp in what charged states the defects are energetically stable at each Fermi level. This can be done.

[0252] Next, as a representative example of the oxide insulating film in contact with the oxide semiconductor film, silicon oxynitride (SiO N) was used, and the defect levels in the silicon oxynitride and the ESR signals caused by the defect levels were verified by calculation. Specifically, for models in which NO2, N2O, NO, and N atoms were introduced into silicon dioxide (SiO2), by examining the transition levels of NO2, N2O, NO, and N atoms, it was verified whether NO2, N2O, NO, and N atoms could become electron traps in the transistor. For the calculation, SiO2 (c-SiO2) with a low-temperature quartz (α-quartz) crystal structure was used as a model. The crystal model of defect-free c-SiO2 is shown in Fig. 13. First, for a 72-atom model obtained by doubling the unit cell of c-SiO2 in all axial directions, structure optimization calculations were performed for the lattice constant and each atomic coordinate. For the calculation, the first-principles calculation software VASP (The Vienna Ab initio simulation package) was used. Also, the effect of the inner-shell electrons was Projector Augmente

[0253] ckage.

[0254] First, for a 72-atom model in which the unit cell of c-SiO2 was doubled in all axial directions, structure optimization calculations were performed for the lattice constant and each atomic coordinate. For the calculation, the first-principles calculation software VASP (The Vienna Ab initio simulation package) was used. For the calculation, the first-principles calculation software VASP (The Vienna Ab initio simulation package) was used. For the calculation, the first-principles calculation software VASP (The Vienna Ab initio simulation package) was used. ckage) was used. Also, the effect of the inner-shell electrons was Projector Augmente ​Calculated by the projector augmented wave (PAW) method, and the Heyd-Scuseria-Er nzerhof (HSE) DFT hybrid functional (HSE06) was used for the functional. The calculation conditions are shown below.

[0255]

Table 1

[0256] The band gap of the optimized c-SiO2 model was 8 .97 eV, which is close to the experimental value of 9.0 eV.

[0257] Subsequently, for each model in which NO2, N 2O, NO, or N atoms were introduced into the space (interstice) within the crystal structure of the above c-SiO2 model, structure optimization calculations were performed . Here, for each model, when the whole model is +1 valence (charge: +1), when the whole model is electrically neutral (0 valence) (charge: neutral), and when the whole model is -1 valence (charge: -1), optimization calculations were performed for each of the three cases. However, the charges imposed on the whole model were confirmed to be localized at the defects containing NO2, N2O, NO, and N atoms, respectively, in the ground state of electrons.

[0258] First, for the model in which NO2 was introduced into the interstice of the c-SiO2 model, the structure and the structural parameters of the NO2 molecule after the optimization calculation are shown in Fig. 14. In Fig. 14 , as a reference example, the structural parameters of the NO2 molecule in the gas phase are also appended.

[0259] Generally, a molecule that is not electrically neutral is often called a molecular ion, etc. However, here, since the molecule introduced into the interior of the crystal lattice is being discussed, unlike the gas phase, the valence of the molecule is not quantified ​​​​​ Since it is difficult, etc., for the sake of convenience, even for molecules that are not electrically neutral, they are also referred to as molecules. Let's call it.

[0260] From Figure 14, when the NO2 molecule is introduced, when the charge of the model is +1, the NO2 molecule is almost linear, and in the order of the charge of the model being neutral and -1, the O-N-O bond angle tends to decrease. This structural change of the NO2 molecule is almost the same as the change in the bond angle when changing the charge number of the isolated molecule in the gas phase. Therefore, most of the assumed charges are borne by the NO2 molecule , and it is inferred that the NO2 molecule in SiO2 exists in a state close to the isolated molecule. .

[0261] Subsequently, for the model in which N2O is introduced into the lattice space of the c-SiO2 model, the structure after the optimization calculation and the structural parameters of the N2O molecule are shown in Figure 15. In Figure 15, as a reference example, the structural parameters of the N2O molecule in the gas phase state are also appended.

[0262] From Figure 15, when the charge of the model is +1 and when it is neutral, the structure of the N2O molecule is almost the same linear structure. On the other hand, when the charge of the model is -1, the N2O molecule is bent and the N-O distance is extended compared to the other two conditions. This is considered to be because electrons have entered the LUMO level, which is the π orbital of the N2O molecule. *

[0263] Next, for the model in which NO is introduced into the lattice space of the c-SiO2 model, the structure after the optimization calculation is performed and the structural parameters of the NO molecule are shown in Figure 16.

[0264] From Figure 16, when the charge of the model is +1, the N-O distance is short, and conversely, when the charge of the model is -1 When this is the case, the N-O distance is long. This is because when the charge of the NO molecule in the gas phase is +1, 0, or -1, the bond order of the N-O bond is 3.0, 2.5, and 2.0 respectively, and it is speculated that this reflects that it is the largest when the charge is +1. From this, it is speculated that the NO molecule in SiO2 exists stably in a state close to an isolated molecule.

[0265] Finally, for the model in which an N atom is introduced between the lattices of the c-SiO2 model, the structure after the optimization calculation is shown in Fig. 17.

[0266] From Fig. 17, it was found that in any charge state, the N atom is more energetically stable when bonded to the atoms in SiO2 than when existing as an isolated atom between the lattices.

[0267] Subsequently, the transition level was calculated for each model.

[0268] Here, the transition level ε(q / q’) for transitioning between the state of charge q and the state of charge q’ in the model having a defect D in the structure can be calculated by the following Equation 3.

[0269]

Equation

[0270] Here, E tot (D q ) is the total energy of the model having the defect D with charge q, E tot ( bulk) is the total energy of the model without defects, n i is the number of atoms i contributing to the defect, μ i is the chemical potential of atom i, ε VBM is the energy at the upper end of the valence band in the model without defects, ΔV ​q is a correction term related to the electrostatic potential, E f is the Fermi energy .

[0271] The band diagram showing the transition levels obtained from the above formula is shown in FIG. 18. Note that as the oxide semiconductor film, a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 was used to form an oxide semiconductor film (hereinafter referred to as IGZO(111)). Also, in FIG. 18 in addition to the band diagrams of the above four models, the band diagram of IGZO(111) is also explicitly shown. Note that the unit of the numerical values in FIG. 18 is eV .

[0272] In FIG. 18, the values of each transition level are shown with the upper end of the valence band of SiO2 as the reference (0.0 eV) . Here, although the literature value was used as the electron affinity of SiO2, the positional relationship of each band when SiO2 and IGZO(111) are joined may actually be affected by the electron affinity of SiO2 .

[0273] Also, the transition level at which the charge of the model transitions from the +1 state to the 0 state is denoted as (+ / 0) , and the transition level at which the charge of the model transitions from the 0 state to the -1 state is denoted as (0 / -) .

[0274] In FIG. 18, in the model in which NO2 molecules are introduced into SiO2, two transition levels of (+ / 0) and (0 / -) exist at positions corresponding to within the band gap of IGZO(111) , suggesting that they may be involved in the trapping and detrapping of electrons. Also, in the models in which NO molecules are introduced into SiO2 and N atoms are introduced, in both cases, IGZO ​​A transition level of (+ / 0) exists at a position corresponding to within the bandgap of (111). One On the other hand, the transition levels of the model in which N2O molecules are introduced into SiO2 are all outside the bandgap of IGZO(11 1), and it is presumed that they stably exist as neutral molecules regardless of the position of the Fermi level.

[0275] From the above results, the interstitial molecules containing nitrogen that are involved in the electron trap / detrap, which is the cause of the positive shift of the threshold voltage of the transistor, are molecules having a transition level at a position higher than the conduction band within the bandgap of IGZO(111). Here, it is strongly suggested that the molecules having a transition level at a position higher than the conduction band within the bandgap of IGZO(1 11) are likely to be NO2 molecules or NO molecules, or both. 11) are likely to be NO2 molecules or NO molecules, or both.

[0276] <1-2. Verification of ESR signal> In response to the calculation results of the above transition levels, the ESR signal of NO2 molecules was obtained by calculation below. Also, the same verification was performed here for the model in which N atoms are substituted for O atoms in SiO2. Here, since there are 7 electrons in N atoms and 8 electrons in O atoms, the NO2 molecule has an open-shell structure. Therefore, since the neutral NO2 molecule has unpaired electrons, it can be measured by ESR. Also, when N atoms are substituted for O atoms in SiO2, there are only 2 Si atoms around the N atom, and since N has a dangling bond, it can be measured by ESR in the same way. Also, Here, since there are 7 electrons in N atoms and 8 electrons in O atoms, the NO2 molecule has an open-shell structure. Therefore, since the neutral NO2 molecule has unpaired electrons, it can be measured by ESR. Also, when N atoms are substituted for O atoms in SiO2, there are only 2 Si atoms around the N atom, and since N has a dangling bond, it can be measured by ESR in the same way. Also,

[0277] Since N has a nuclear spin of 1, Since N has a nuclear spin of 1, Since the neutral NO2 molecule has unpaired electrons, it can be measured by ESR. Also, when N atoms are substituted for O atoms in SiO2, there are only 2 Si atoms around the N atom, and since N has a dangling bond, it can be measured by ESR in the same way. Also, Since the neutral NO2 molecule has unpaired electrons, it can be measured by ESR. Also, when N atoms are substituted for O atoms in SiO2, there are only 2 Si atoms around the N atom, and since N has a dangling bond, it can be measured by ESR in the same way. Also, Since the neutral NO2 molecule has unpaired electrons, it can be measured by ESR. Also, when N atoms are substituted for O atoms in SiO2, there are only 2 Si atoms around the N atom, and since N has a dangling bond, it can be measured by ESR in the same way. Also, 14 Since N has a nuclear spin of 1, 14 N The peak of the ESR signal involved splits into three. At this time, the split width is the hyperfine coupling constant.

[0278] Therefore, whether the origin of the splitting of the ESR signal in the oxide insulating film into three is due to the NO2 molecule or due to the N atom substituting for the O atom in SiO2 was verified by calculation. When using the crystal structure of SiO2 as a model, the amount of calculation becomes enormous , so here, models of two types of cluster structures as shown in Fig. 19 were used, and after performing structure optimization on these , the g value and the hyperfine coupling constant were calculated. Fig. 19(A) is a model of a neutral NO2 molecule, and Fig. 19(B) is a cluster model having an Si-N-Si bond. In the model shown in Fig. 19(B), a cluster model in which the unbonded hands of the Si atom are terminated with H atoms was used. For the structure optimization of the model and the calculation of the g value and the hyperfine coupling constant of the structure-optimized model

[0279] , ADF (Amsterdam Density Functional software) was used. Also, for both the structure optimization of the model and the calculation of the g value and the hyperfine coupling constant of the structure-optimized model, "GGA:BP" was used as the functional, "QZ 4P" was used as the basis function, and "None" was used as the Core Type. Also, when calculating the g value and the hyperfine coupling constant, "Spin-Orbit" was considered as the relativistic effect, and "g & A-Tensor(full SO)" was selected as the calculation method of ESR / EP R. The calculation conditions are shown below.

[0280]

Table 2

[0281] As a result of the structure optimization, first, for the NO2 molecule shown in Fig. 19(A), the N-O bond length is 0 .1205 nm, and the O-N-O bond angle is 134.1°. This is close to the bond length of 0.1197 nm and bond angle of 134.3° which are the experimental values for the NO2 molecule . Also, for the Si-N-Si cluster model shown in Fig. 19(B), the Si-N bond length is 0. 172 nm, and the Si-N-Si bond angle is 138.3°. This is about the same as the Si-N bond length of 0.170 nm and Si-N-Si bond angle of 139.0° in the structure after performing the structure optimization calculation by substituting an N atom for an O atom in the SiO2 crystal by first-principles calculation . .

[0282] The calculated g values and hyperfine coupling constant values are shown below

[0283]

Table 3

[0284] As described above, the hyperfine coupling constant A corresponds to the split width of the peak of the ESR signal . From Table 3, the average value of the hyperfine coupling constant A for the NO2 molecule is approximately 5 mT. On the other hand , for the Si-N-Si cluster model, only Ax of the hyperfine coupling constant A takes a positive value , but the value is about 3 mT. The ESR spectra of NO 2 and Si-N-Si obtained from the g values and the hyperfine coupling constant A are shown in Fig. 20(A) and Fig. 20(B), respectively .

[0285] From this result, in the X-band ESR measurement, it has three signals and a hyperfine of about 5 mT ​​The ESR spectrum with a fine structure constant and a g-value of about 2 is likely to be caused by NO2 molecules in the SiO2 crystal. Among the three signals, the g-value of the central signal is about 2. Hereinafter, based on the above results, the mechanism of the phenomenon that the threshold voltage of the transistor shifts positively when the positive gate BT stress test (+GBT) is performed will be considered.

[0286] <1-3. Consideration of the Degradation Mechanism of Transistors> Using Fig. 21, the mechanism will be considered. Fig. 21 shows a structure in which a gate (GE), a gate insulating film (GI), an oxide semiconductor film (OS), and a silicon oxynitride film (SiON) are laminated in this order. Here, the case where the silicon oxynitride film SiON on the back channel side of the oxide semiconductor film (OS) contains nitrogen oxides will be described.

[0287] First, when a positive gate BT stress test (+GBT) is performed on the transistor, the electron density on the gate insulating film GI side and the silicon oxynitride film SiON side of the oxide semiconductor film OS increases. Note that the electron density on the silicon oxynitride film SiON side of the oxide semiconductor film OS is smaller than that on the gate insulating film GI side. When NO2 molecules or NO molecules contained in the silicon oxynitride film SiON diffuse to the interfaces between the gate insulating film GI and the oxide semiconductor film OS and between the oxide semiconductor film OS and the silicon oxynitride film SiON, the electrons on the gate insulating film GI side and the back channel side induced by the positive gate BT stress test (+GBT) are trapped. As a result, the trapped electrons are in the gate insulating film GI and the oxide semiconductor film OS.

[0288] stays near the interface between the oxide semiconductor film OS and the silicon oxynitride film SiON As a result, the threshold voltage of the transistor shifts in the positive direction.

[0289] That is, in the silicon oxynitride film in contact with the oxide semiconductor film, the lower the concentration of the contained nitrogen oxide the more the fluctuation of the threshold voltage of the transistor can be suppressed. Here, As the silicon oxynitride film in contact with the oxide semiconductor film, there are a protective film in contact with the back channel side, and a gate insulating film and the like. By providing a silicon oxynitride film with an extremely low nitrogen oxide content in contact with the oxide semiconductor film, a highly reliable transistor can be realized.

[0290] <2. V O H> Next, the H atom O located in the oxygen vacancy V (hereinafter referred to as V O H) will be described.

[0291] <2-1. Energy and stability between the forms of existence of H> First, the energy difference and stability of the forms of H existing in the oxide semiconductor film will be described using the results of calculations. Here, InGaZnO4 (hereinafter referred to as IGZ O(111)) was used as the oxide semiconductor film.

[0292] The structure used in the calculation was based on an 84-atom bulk model obtained by doubling the hexagonal unit cell of IGZO(111) in the a-axis and b-axis directions by a factor of 2 each.

[0293] In the bulk model, one O atom bonded to three In atoms and one Zn atom was replaced with H ​A model in which atoms were substituted was prepared (see Fig. 22(A)). Also, in Fig. 22(A), Fig. 22(B) shows a view of the ab-plane in the InO layer as seen from the c-axis. A region where one O atom bonded to three In atoms and one Zn atom was removed is denoted as oxygen vacancy V O and is indicated by a dashed line in Fig. 22( A) and Fig. 22(B). Also, the H atom located in the oxygen vacancy V O is denoted as V O H.

[0294] Also, in the bulk model, one O atom bonded to three In atoms and one Zn atom was removed to form an oxygen vacancy (V ). Near this V O , a model in which an H atom is bonded to an O atom bonded to one Ga O atom and two Zn atoms with respect to the ab-plane was prepared (see Fig. 22 (C)). Also, in Fig. 22(C), Fig. 22(D) shows a view of the ab-plane in the InO layer as seen from the c-axis. In Fig. 22(C) and Fig. 22(D), the oxygen vacancy V is indicated by a dashed line. Also, a model having an oxygen vacancy V and having an H atom bonded to an O atom bonded to one Ga O atom and two Zn atoms near the oxygen vacancy V is denoted as V O +H O and is denoted as such. O +H and is denoted as such.

[0295] For the above two models, optimization calculations were performed with the lattice constant fixed, and the total energy was calculated. Note that the smaller the value of the total energy, the more stable the structure can be said to be.

[0296] For the calculations, the first-principles calculation software VASP (The Vienna Ab init tio simulation package) was used. The calculation conditions are shown in Table 4.

[0297]

Table 4

[0298] The electronic state pseudopotential uses the potential generated by the PAW (Projector Augmented Wa ve) method, and the generalized function uses GGA / PBE (General ized-Gradient-Approximation / Perdew-Burke -Ernzerhof).

[0299] Also, the total energies of the two models calculated by the calculation are shown in Table 5.

[0300]

Table 5

[0301] From Table 5, the total energy of VH is 0.78 eV lower than that of V O H. Therefore, O VH is more stable than V V O H. Thus, it can be said that when an H atom approaches an oxygen deficiency (V O ), the H atom is more likely to be incorporated into the oxygen deficiency (V O ) than to bond with an O atom. O O O It is considered to be easy.

[0302] <2-2. Thermodynamic state of V O H Next, the results of evaluating the thermodynamic state of VH in which an H atom is incorporated into an oxygen deficiency (V O ) using electronic state calculations will be described. O O

[0303] The defect V contained in IGZO(111) OFor H, (V O H) + 、(V O H) - 、( V O H) 0 the formation energies of each were calculated. Note that (V O H) + indicates the state where one electron is emitted and (V O H) - indicates the state where one electron is captured, and (V O H) 0 indicates the state where there is no electron movement.

[0304] For the calculation, the first-principles calculation software VASP was used. The calculation conditions are shown in Table 6. Also 、the structure of the model used in the calculation is shown in Fig. 23. Note that the evaluation of the formation energy was calculated assuming the reaction shown in Equation 4. Also, for the calculation of the electronic state pseudopotential, the potential generated by the PAW method was used, and for the functional, the Heyd-Scuseria-Ernzerhof (HSE) DFT hybrid functional (HSE06) was used. Also, in the calculation of the formation energy of oxygen deficiency, the dilute limit of the oxygen deficiency concentration was assumed, and the energy was calculated by correcting for the excessive spread to the conduction band and valence electron band of electrons and holes. Also, taking the upper end of the valence electron band of the perfect crystal as the energy origin, the shift of the valence electron band due to the defect structure was corrected using the average electrostatic potential .

[0305]

Table 6

[0306]

Equation

[0307] The formation energy obtained in this calculation is shown in Fig. 24(A).

[0308] Fig. 24(A) shows the formation energies of (V O H) + , (V O H) - , and (V O H) 0 respectively. The horizontal axis is the Fermi level, and the vertical axis is the formation energy. The dotted line indicates the formation energy of (V O H) + , the solid line indicates the formation energy of (V O H) 0 , and the dashed line indicates the formation energy of (V O H) - . Also, the transition level ε(+ / -) at which the charge of V O H changes from (V O H) + to (V O H) 0

[0309] - is shown. Fig. 24(B) shows the thermodynamic transition level of V O H. From the calculation results, the energy gap of InGaZnO 4 was 2.739 eV. Also, assuming the energy of the valence band is 0 eV V, the transition level (ε(+ / -)) is 2.62 eV and exists just below the conduction band. From this, when the Fermi level exists within the energy gap, the charge state of V O H is always +1, and V O H is considered to be a donor. That is, it can be seen that when H atoms are incorporated into oxygen vacancies (V O ), IGZO(111) becomes n-type .

[0310] Next, the carrier (electron) density and the defect (VO (H) The results of evaluating the relationship of density are shown in Fig. 25. .

[0311] From Fig. 25, it can be seen that as the density of defect (V O H) increases, the carrier density increases. .

[0312] From the above, it was found that V O H in IGZO(111) acts as a donor. Also, it was found that when the density of V O H increases, IGZO(111) becomes n-type.

[0313] <3. Model for explaining the DOS in the oxide semiconductor film and the relationship between the elements that become DOS >] When the DOS (Density of States) exists inside the oxide semiconductor film and near the interface between the oxide semiconductor film and the outside, it becomes a factor for deteriorating the transistor having the oxide semiconductor film. The DOS inside the oxide semiconductor film and near its interface can be explained by the positions and bonding relationships of oxygen (O), oxygen deficiency (V ), hydrogen (H), and nitrogen oxide (NO O ). The following explains the outline of the model. x ). To impart stable electrical characteristics to the transistor, it is important to reduce the DOS (high-purity intrinsic conversion) inside the oxide semiconductor film and near its interface. To reduce the DOS,

[0314] it is necessary to reduce oxygen deficiency, hydrogen, and nitrogen oxide. The following explains the relationship between the DOS inside the oxide semiconductor film and near its interface and oxygen deficiency, hydrogen, and nitrogen oxide using a model. . .

[0315] ​FIG. 26 shows a band structure showing the DOS inside an oxide semiconductor film and in the vicinity of the interface therewith. In the following, the oxide semiconductor film is an oxide semiconductor film containing indium, gallium, and zinc ( The case where the substrate is an IGZO(111) will be described.

[0316] First, in general, there are two types of DOS: shallow level DOS In this specification, there are two types of DOS: deep level DOS and deep level DOS. The shallow level DOS is the energy at the bottom of the conduction band. This refers to the DOS between the energy (Ec) and the midgap. Therefore, for example, the shallow level DOS is the conduction band It is located near the lower energy limit. In this specification, the deep DOS (de The ep level DOS is the energy of the upper edge of the valence band (Ev) and the mid-gap Therefore, for example, a deep level DOS is a DOS between el DOS) is located closer to the midgap than the energy of the top of the valence band.

[0317] Shallow level DOS in oxide semiconductor films There are two types of DOS. The first type, shallow level DOS, is Near the surface of the oxide semiconductor film (at or near the interface with the insulating film (insulator)) The second shallow DOS. (shallow level DOS) is the DOS inside the oxide semiconductor film (bulk On the other hand, deep level DOS (deep level DOS) As the (OS), there is the DOS (bulk deep DOS) inside the oxide semiconductor film.

[0318] These DOSs may act as follows. First, the surface shallow DOS near the surface of the oxide semiconductor film is at a shallow position from the lower end of the conduction band. Therefore, in the surface shallow DOS, charge capture and disappearance can easily occur. On the other hand, the bulk shallow DOS inside the oxide semiconductor film is at a deeper position from the lower end of the conduction band compared with the surface shallow DOS near the surface of the oxide semiconductor film. For this reason, in the bulk shallow DOS, charge disappearance hardly occurs.

[0319] Hereinafter, the causative elements that create DOS in the oxide semiconductor film will be described.

[0320] For example, when forming a silicon oxide film on the oxide semiconductor film, indium contained in the oxide semiconductor film enters the silicon oxide film and substitutes for silicon, which may create a shallow-level DOS (shallow level DOS).

[0321] Also, for example, at the interface between the oxide semiconductor film and the silicon oxide film, the bond between indium and oxygen contained in the oxide semiconductor film is broken, and a bond between the oxygen and silicon occurs. This is due to the fact that the bond energy between silicon and oxygen is higher than the bond energy between indium and oxygen and the fact that silicon (tetravalent) has a higher valence than indium (trivalent). As a result, the oxygen contained in the oxide semiconductor film is taken away by silicon, and the site of the oxygen bonded to indium becomes oxygen-deficient. Also, this phenomenon occurs not only on the surface but also in the oxide semiconductor film. The same occurs even when silicon enters the oxide semiconductor film. These oxygen deficiencies form deep level DOS (deep level density of states).

[0322] Also, not only silicon but also other factors can break the bond between indium and oxygen. For example, in an oxide semiconductor film containing indium, gallium, and zinc, the bond between indium and oxygen is weaker and more likely to break than the bonds between gallium or zinc and oxygen. Therefore, for example, due to damage by plasma or damage by sputter particles, the bond between indium and oxygen can break and oxygen deficiencies can occur. These oxygen deficiencies form deep level DOS (deep level density of states).

[0323] These deep level DOS (deep level density of states) can capture holes, so they become hole traps (hole capture centers). That is, these oxygen deficiencies form bulk deep DOS inside the oxide semiconductor film. Oxygen deficiencies are a cause of forming bulk deep DOS and are an unstable factor for the oxide semiconductor film.

[0324] Also, the deep level DOS (deep level density of states) due to these oxygen deficiencies is, as will be described below, one of the factors for forming bulk shallow DOS inside the oxide semiconductor film.

[0325] Oxygen deficiencies in the oxide semiconductor film become metastable by capturing hydrogen. That is, the deep level DOS (deep level density of states) that can capture holes forms bulk shallow DOS when the oxygen deficiencies capture hydrogen and become metastable. becomes. As described in <V O thermodynamic state of H> shown in this embodiment, oxygen deficiency captures hydrogen and becomes neutral or positively charged. That is, the bulk shallow DOS inside the oxide semiconductor film is one of the V H releases electrons and becomes neutral or positively O charged, which affects the characteristics of the transistor. In addition, in order to prevent oxygen deficiency from having an adverse effect on the characteristics of the transistor,

[0326] it is important to reduce the density of oxygen deficiency. Therefore, by supplying excess oxygen to the oxide semiconductor film, that is, by filling oxygen deficiency with excess oxygen, the density of oxygen deficiency in the oxide semiconductor film can be reduced. That is, oxygen deficiency becomes stable when excess oxygen enters. For example, when excess oxygen is present in the oxide semiconductor film or in the insulating film near the interface of the oxide semiconductor film, the excess oxygen can fill the oxygen deficiency in the oxide semiconductor film, and the oxygen deficiency in the oxide semiconductor film can be effectively eliminated or reduced.

[0327]

[0328] Thus, oxygen deficiency becomes a metastable state or a stable state depending on either hydrogen or oxygen.

[0328] Also, as described in <Transition level of NO in the oxide insulating film> shown in this embodiment, x NO or NO2, which is NO, captures electrons contained in the oxide semiconductor film. As NO x is NO or NO2, it captures electrons contained in the oxide semiconductor film. NO x is one of the surface shallow DOS near the surface of the oxide semiconductor film. Therefore, in the insulating film provided near the interface of the oxide semiconductor film, NO NOx Its inclusion affects the characteristics of the transistor.

[0329] Note that NO x In order not to have an adverse effect on the characteristics of the transistor, the NO contained in the insulating film provided near the interface of the oxide semiconductor film x needs to be reduced. This is important.

[0330] <3-1. Hysteresis degradation model in the dark state of a transistor having an oxide semiconductor film model> Next, the degradation mechanism of a transistor having an oxide semiconductor film will be described. Oxidation A transistor having an oxide semiconductor film behaves differently when it is irradiated with light and when it is not irradiated with light. When irradiated with light, the DOS (bulk deep DOS) at a deep position inside the oxide semiconductor film may be greatly affected. When not irradiated with light, the DOS (surface shallow DOS) at a shallow position near the surface of the oxide semiconductor film (at or near the interface with the insulating film (Insulator)) may be involved. Therefore, first, the case where a transistor having an oxide semiconductor film is not irradiated with light (dark state) will be described. In the dark state, based on the relationship between the capture and release of charges by the DOS (surface shallow DOS) at a shallow position near the surface of the oxide semiconductor film (at or near the interface with the insulating film (Insulator)), the degradation mechanism of the transistor can be explained. Here, the gate insulating film is used as the insulating film provided near the interface of the oxide semiconductor film for explanation. tor) and its vicinity) w DOS) may be involved.

[0331] Therefore, first, the case where a transistor having an oxide semiconductor film is not irradiated with light (dark state) will be described. In the dark state, based on the relationship between the capture and release of charges by the DOS (surface shallow DOS) at a shallow position near the surface of the oxide semiconductor film (at or near the interface with the insulating film (Insulator)), the degradation mechanism of the transistor can be explained. Here, the gate insulating film is used as the insulating film provided near the interface of the oxide semiconductor film for explanation. state) will be described. In the dark state, based on the relationship between the capture and release of charges by the DOS (surface shallow DOS) at a shallow position near the surface of the oxide semiconductor film (at or near the interface with the insulating film (Insulator)), the degradation mechanism of the transistor can be explained. Here, the gate insulating film is used as the insulating film provided near the interface of the oxide semiconductor film for explanation. tor) and its vicinity) w DOS), the degradation mechanism of the transistor can be explained. Here, the gate insulating film is used as the insulating film provided near the interface of the oxide semiconductor film for explanation. Note that here, the gate insulating film is used as the insulating film provided near the interface of the oxide semiconductor film for explanation. membrane is used for explanation.

[0332] For a transistor having an oxide semiconductor film, the threshold voltage (Vth) when a gate BT (bias temperature) stress test is repeatedly performed in the dark state is shown in FIG. 27. From FIG. 27, when a positive gate BT stress test (+GBT) is performed, the threshold voltage changes in the positive direction. Next, when a negative gate BT stress test (-GBT) is performed, the threshold voltage changes in the negative direction and becomes a threshold voltage similar to the initial value. Thus, when the positive gate BT stress test and the negative gate BT stress test are alternately and repeatedly performed, the threshold voltage changes up and down (hysteresis occurs). That is, in a state where light is not irradiated, when the negative gate BT stress test and the positive gate BT stress test are repeatedly performed, the threshold voltage shifts repeatedly in the positive and negative directions, but as a whole, it is found that the change remains within a certain range.

[0333] Such a change in the threshold voltage of the transistor in the gate BT stress test in the dark state can be explained by the surface shallow DOS near the surface of the oxide semiconductor film. FIG. 28 shows the band structure including the oxide semiconductor film and the flowchart corresponding to the band structure. Before the application of the gate BT stress (the gate voltage (Vg) is 0), the surface shallow DOS near the surface

[0334] of the oxide semiconductor film has an energy higher than the Fermi level (Ef) and is electrically neutral because electrons are not trapped (step S101 in FIG. 28) since the energy is higher than the Fermi level (Ef) and electrons are not trapped, so it is electrically neutral (step S101 in FIG. 28) since the energy is higher than the Fermi level (Ef) and electrons are not trapped, so it is electrically neutral (step S101 in FIG. 28) )。The threshold voltage measured in step S101 is set as the initial value before the application of gate BT stress. Initial value.

[0335] Next, a positive gate BT stress test (dark state) is performed. By applying a positive gate voltage, the band of the conduction band bends, and the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy lower than the Fermi level. As a result, electrons are trapped in the surface shallow DOS near the surface of the oxide semiconductor film, and it becomes negatively charged (step S102 in FIG. 28). By applying a positive gate voltage, the band of the conduction band bends, and the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy lower than the Fermi level. As a result, electrons are trapped in the surface shallow DOS near the surface of the oxide semiconductor film, and it becomes negatively charged (step S102 in FIG. 28). allow DOS becomes an energy lower than the Fermi level. As a result, electrons are trapped in the surface shallow DOS near the surface of the oxide semiconductor film, and it becomes negatively charged (step S102 in FIG. 28). Electrons are trapped in the surface shallow DOS near the surface of the oxide semiconductor film, and it becomes negatively charged (step S102 in FIG. 28). charged (step S102 in FIG. 28).

[0336] Next, the stress is stopped and the gate voltage is set to 0. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. By setting the gate voltage to 0, the surface shallow DOS near the surface of the oxide semiconductor film becomes an energy higher than the Fermi level. However, it takes a long time for the electrons trapped in the surface shallow DOS near the surface of the oxide semiconductor film to be released. Therefore, the surface shallow DOS near the surface of the oxide semiconductor film remains negatively charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off. charged (step S103 in FIG. 28). At this time, in addition to the gate voltage, a negative voltage continues to be applied to the channel formation region of the transistor. Therefore, in order to turn on the transistor, a gate voltage higher than the initial value must be applied, and the threshold voltage changes in the positive direction. That is, there is a possibility that it becomes easier to be normally off.

[0337] Next, a negative gate BT stress test (dark state) is performed, and a negative gate voltage is applied. By applying a negative gate voltage, the band of the conduction band bends, and the oxide semiconductor By applying a negative gate voltage, the band of the conduction band bends, and the oxide semiconductor The surface shallow DOS near the surface of the body film becomes a higher energy. Therefore, the electrons captured by the surface shallow DOS near the surface of the oxide semiconductor film are emitted, and it becomes electrically neutral (step S104 in FIG. 28).

[0338] Next, the stress is stopped and the gate voltage is set to 0. At this time, since the surface shallow DOS near the surface of the oxide semiconductor film has already emitted electrons, it is electrically neutral (step S101). Therefore, the threshold voltage changes in the positive direction, and as a result, it returns to the initial value before the application of the gate BT stress. That is, in the dark state, when the negative gate BT stress test and the positive gate BT stress test are repeated, the threshold voltage repeatedly changes in the positive and negative directions. However, in the surface shallow DOS near the surface of the oxide semiconductor film, the electrons captured during the positive gate BT stress test are emitted during the negative gate BT stress test, so overall, it was found that the threshold voltage changes within a certain range.

[0339] As described above, the change in the threshold voltage of the transistor due to the gate BT stress test in the dark state can be explained by understanding the surface shallow DOS near the surface of the oxide semiconductor film.

[0340] <3-2. Degradation model of a transistor having an oxide semiconductor film in the bright state> Next, the mechanism of degradation when light is irradiated (bright state) will be described. In the bright state, the DOS (bulk deep DOS) at a deep position inside the oxide semiconductor film ​​​​​From the relationship between charge capture and release, the mechanism of transistor degradation will be explained. This can be done.

[0341] For a transistor having an oxide semiconductor film, the change in the threshold voltage (Vth) when the gate BT stress test is repeatedly performed in the bright state is shown in FIG. 29. From FIG. 29, the threshold voltage (Vth) changes in the negative direction from the initial value (Initial).

[0342] In FIG. 29, first, as the initial value of the threshold voltage, the result measured in the dark state without applying gate BT stress was plotted. Next, without applying gate BT stress, the threshold voltage was measured in the bright state. As a result, it was found that the threshold voltage in the bright state changed significantly in the negative direction compared to the threshold voltage in the dark state. This is because electrons and holes are generated by irradiating light, and it is considered that one factor is that the generated electrons are excited to the conduction band. That is, even when gate BT stress is not applied, due to the irradiation of light, the threshold voltage of the transistor having an oxide semiconductor film shifts in the negative direction, and it can be said that it becomes easier to be normally ionized. In this case, the larger the energy gap of the oxide semiconductor film, or the smaller the DOS within the gap, the fewer the excited electrons. Therefore, in such a case, the change in the threshold voltage due to only the irradiation of light becomes smaller.

[0343] Next, when the minus gate BT stress test (-GBT) is performed while irradiating light, the threshold voltage changes further in the negative direction.

[0344] ​​​​​​​After that, while irradiating with light, a positive gate BT stress test (+GBT) was performed. When this was done, the threshold voltage changed in the positive direction.

[0345] Furthermore, when repeating the negative gate BT stress test and the positive gate BT stress test while irradiating with light, the threshold voltage changed repeatedly in the positive and negative directions, and overall, it was found that it gradually changed in the negative direction. When the positive gate BT stress test and the negative gate BT stress test were repeatedly performed while irradiating with light, it was found that the threshold voltage of the transistor changed repeatedly in the positive and negative directions, and overall, it gradually changed in the negative direction. It was found that it gradually changed in the negative direction while repeatedly changing in the positive and negative directions.

[0346] In the gate BT stress test (repeated test of positive gate BT and negative gate BT) in the bright state shown above, the mechanism by which the threshold voltage of the transistor changes will be described using the band structures shown in FIGS. 30 and 31. In FIGS. 30 and 31, it will be described using the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). it will be described using the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film will be used for the description. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film will be used for the description. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film will be used for the description. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film will be used for the description. Note that the non-bridging oxygen hole trapping center (NBOHC1) is a non-bridging oxygen hole trapping center (NBOHC) located closer to the interface with the oxide semiconductor film (surface side) than the non-bridging oxygen hole trapping center (NBOHC2). is.

[0347] Before applying the gate BT stress and irradiating with light (the gate voltage (Vg) is 0), the bulk deep DOS inside the oxide semiconductor film has an energy lower than the Fermi level (Ef), and since holes are not trapped, it is electrically neutral (step S111 in FIG. 30). Before applying the gate BT stress and irradiating with light (the gate voltage (Vg) is 0), the bulk deep DOS inside the oxide semiconductor film has an energy lower than the Fermi level (Ef), and since holes are not trapped, it is electrically neutral (step S111 in FIG. 30). At this time, the threshold voltage measured in the dark state is set as the initial value in the dark state. At this time, the threshold voltage measured in the dark state is set as the initial value in the dark state.

[0348] Next, when irradiating the oxide semiconductor film with light without applying the gate BT stress, electrons and holes​ Holes are generated (step S112 in FIG. 30). The generated electrons are excited to the conduction band, and the threshold voltage is changed in the negative direction (electrons are omitted in the following steps for illustration). . Further, when holes are generated, the quasi-Fermi level (Efp) of the holes decreases. When the quasi- Fermi level (Efp) of the holes decreases, holes are trapped in the bulk deep D OS in the oxide semiconductor film (step S113 in FIG. 30). Therefore, when light is irradiated without applying gate BT stress, the threshold voltage changes in the negative direction compared to the dark state, and there is a possibility of becoming more easily normally ionized.

[0349] Next, when a negative gate BT stress test is performed while light is being irradiated, an electric field gradient is generated, and the holes trapped in the bulk deep DOS in the oxide semiconductor film are injected into the non-bridging oxygen hole trapping center (NBOHC1) in the gate insulating film (step S114 in FIG. 30). Further, due to the electric field, a part of the holes also moves to the non-bridging oxygen hole trapping center (NBOHC2) deeper inside the gate insulating film (step S115 in FIG. 31). The movement of holes from the non-bridging oxygen hole trapping center (NBOHC1) to the non-bridging oxygen hole trapping center (NBOH C2) in the gate insulating film progresses as the time for applying the electric field is longer. The holes in the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film act as positive fixed charges, changing the threshold voltage in the negative direction and making it more easily normally ionized.

[0350] Here, for ease of understanding, light irradiation and the negative gate BT stress test are shown in separate steps, but it should not be construed as being limited to this. For example, ​ Steps S112 to S115 may be considered to be steps occurring in parallel. I don't.

[0351] Next, a positive gate BT stress test is performed while the light is still irradiated. By applying a voltage to the bulk deep DOS inside the oxide semiconductor film, The trapped holes and the holes in the non-bridging oxygen hole traps (NBOHC1) in the gate insulating film As a result, the threshold voltage changes in the positive direction. However, the non-bridging oxygen hole traps (NBOHC2) in the gate insulating film are Since the location is deep inside the vein, the positive gate BT stress test was performed in the light state. Even if the non-bridging oxygen in the gate insulating film is In order to release the hole from the hole trapping center (NBOHC2), the non-bridging acid on the surface side must first be The non-bridged acid in the gate insulating film must move to the electron hole trap center (NBOHC1). Hole transfer from an oxygen hole trap (NBOHC2) to a non-bridging oxygen hole trap (NBOHC1) The shift of the charge occurs little by little depending on the time the electric field is applied. Therefore, the threshold voltage The amount of change in direction is also small, and it does not return to the initial value.

[0352] In addition, the non-bridging oxygen hole trap center (NBOHC1) in the gate insulating film and the oxide semiconductor film Hole exchange also occurs between the bulk deep DOS and the inner DOS. In the bulk deep DOS inside the semiconductor film, many holes are already trapped. Since the oxide semiconductor film and the gate insulating film are in a dummy state, the charge amount of the oxide semiconductor film and the gate insulating film as a whole is hardly reduced. There is a possibility.

[0353] Next, while the light is still being irradiated, a minus gate BT stress test is performed, and an electric field gradient is generated, and holes captured in the bulk deep DOS inside the oxide semiconductor film are injected into the non-bridging oxygen hole capture center (NBOHC1) in the gate insulating film. Also, due to the electric field holes are also partially injected into the non-bridging oxygen hole capture center (NBOHC2) deeper inside the gate insulating film (step S117 in FIG. 31). Note that the non-bridging oxygen hole capture center (NBOHC2) in the gate insulating film is in a state where the holes that entered in step S115 remain without being released. Therefore, by further injecting holes, the number of holes that act as fixed charges further increases. The threshold voltage changes further in the minus direction, making it easier to become more normally-on.

[0354] Next, while the light is still being irradiated, a plus gate BT stress test is performed. By applying a positive gate voltage, the holes captured in the bulk deep DOS inside the oxide semiconductor film, and the holes in the non-bridging oxygen hole capture center (NBOHC1) in the gate insulating film are released (step S118 in FIG. 31). As a result, the threshold voltage changes in the positive direction. However, the holes in the non-bridging oxygen hole capture center (NBOHC2) in the gate insulating film are hardly released. Therefore, the amount of change in the positive direction of the threshold voltage is also small, and it does not return all the way to the initial value.

[0355] As described above, in the bright state, by repeatedly performing the minus gate BT stress test and the plus gate BT stress test, the threshold voltage repeatedly changes in the positive and minus directions, and overall, it gradually changes in the minus direction. ​​​​​​​​​ is conceivable.

[0356] As described above, the change in the threshold voltage of the transistor in the gate BT stress test in the bright state can be explained by understanding the bulk deep DOS inside the oxide semiconductor film and the non-bridging oxygen hole trapping centers (NBOHC1 and NBOHC2) in the gate insulating film.

[0357] <3-3. Process model of dehydration, dehydrogenation, and oxygen addition of oxide semiconductor film > To impart stable electrical characteristics to the transistor, it is important to reduce the DOS (high-purity intrinsicization) inside the oxide semiconductor film and in the vicinity of its interface. Hereinafter, the process model of high-purity intrinsicization of the oxide semiconductor film will be described. Therefore, first, the dehydration and dehydrogenation of the oxide semiconductor film will be described, and then the oxygen addition by filling oxygen vacancies (V O ) will be described.

[0358] Before describing the process model of high-purity intrinsicization, it will be explained where oxygen vacancies in the oxide semiconductor film are likely to occur. In an oxide semiconductor film containing indium, gallium, and zinc, the bond between indium and oxygen is the most likely to break compared to the bond between gallium and oxygen and the bond between zinc and oxygen. Therefore, hereinafter, a model in which the bond between indium and oxygen breaks and oxygen vacancies are formed will be described.

[0359] When the bond between indium and oxygen breaks, oxygen desorbs, and the site of the oxygen that was bonded to indium becomes an oxygen vacancy. The oxygen vacancy is the DOS at a deep position in the oxide semiconductor film (deep ​​​​​​​​​​​​A level DOS is formed. Since the oxygen deficiency in the oxide semiconductor film is unstable, it is stabilized by capturing oxygen or hydrogen. Therefore, when there is hydrogen near the oxygen deficiency and the oxygen deficiency captures hydrogen, it becomes V O H. V O H forms a shallow level DOS of the oxide semiconductor film at a shallow position.

[0360] Next, when oxygen approaches the V O H in the oxide semiconductor film, the oxygen takes O hydrogen away from V H and desorbs hydrogen in the state of a hydroxyl group (OH) (see FIGS. 32(A) and 32(B). ) Oxygen approaches by moving through the oxide semiconductor film by heat treatment or the like.

[0361] Furthermore, when the desorbed hydroxyl group approaches the V O H of another oxide semiconductor film, it takes O hydrogen away from V H and further desorbs hydrogen in the state of a water molecule (H2O) (see FIGS. 32(C) and 32 (D).) As described above, one oxygen desorbs two hydrogens of the oxide semiconductor film. This is called dehydration and dehydrogenation of the oxide semiconductor film. By dehydration and dehydrogenation , the shallow level DOS of the oxide semiconductor film is reduced and the deep level DOS is formed.

[0362] Next, when oxygen approaches the oxygen deficiency in the oxide semiconductor film, the oxygen is captured by the oxygen deficiency and the oxygen deficiency disappears (see FIGS. 32(E) and 32(F).) This is called oxygen addition of the oxide semiconductor film. By oxygen addition, the deep level DOS (dee p level DOS) of the oxide semiconductor film can be reduced.

[0363] As described above, when dehydration, dehydrogenation, and oxygen addition of the oxide semiconductor film are performed, the shallow level DOS (shallow level DOS) and deep level DOS (deep level DOS) of the oxide semiconductor film can be reduced. This is called high-purity intrinsic conversion of the oxide semiconductor.

[0364] Note that the configurations and methods shown in this embodiment can be appropriately combined and used with the configurations and methods shown in other embodiments and examples.

[0365] (Embodiment 3) In this embodiment, the impurities contained in the oxide semiconductor film included in the transistor and the deterioration of the transistor characteristics will be described. Here, IGZO (11 1) is used as the oxide semiconductor film, and carbon is used as one of the impurities for explanation.

[0366] (1. Influence of Carbon in IGZO) Calculations of the electronic states were performed on a model in which C was introduced into IGZO (111).

[0367] For the calculations, the IGZO (111) crystal model (number of atoms: 112) shown in Fig. 33(A) was used.

[0368] Here, as models in which C was mixed into IGZO (111), models in which C was placed in each of the interstices (1) to (6) as shown in Fig. 33(A) and Table 7, a model in which one In was replaced with C, a model in which one Ga was replaced with C, a model in which one Zn was replaced with C, and a model in which one O was replaced with C were examined.

[0369] [Table 7]

[0370] <1-1. Model with C placed in the interstitial site> (1) For the models with C placed in the interstitial sites shown in (1) to (6), the total energy after structural optimization was compared to examine the stable arrangements. The calculation conditions are shown in Table 8. Since the generalized gradient approximation (GGA) is applied to the exchange-correlation functional, the band gap tends to be underestimated.

[0371]

Table 8

[0372] (1) The results of the structural optimization calculations for the models with C placed in the interstitial sites shown in (1) to (6) are shown in Table 9.

[0373]

Table 9

[0374] Although the interstitial site was selected as the initial position of C, after performing structural optimization, the models with C placed in the interstitial sites of (1), (3), , (4) had a (CO) O defect structure as shown in Fig. 33(C). Note that "(CO)" O means that O in the structure shown in Fig. 33(B) was replaced with CO as shown in Fig. 33(C). In the (CO) defect structure, C bonds with O. Also, C bonds with atoms M1 and M2. Further, O bonds with M3 and M4. Also, the models with C placed in the interstitial sites of (5) and (6) had a structure in which they bonded with the atoms in IGZO(111). Comparing the energies, the (CO) O defect structure has lower energy than the interstitial site. O defect structure As a result, the structure bonded to the atoms in IGZO(111) was found to be more stable.

[0375] Next, the structure of the model with the lowest energy and highest stability in this calculation (the model with C placed at (6)) is shown in Fig. 34(A), and the density of states is shown in Fig. 34(B). In Fig. 34(B), on the horizontal axis, the Fermi level E is set to 0 eV, with the density of states for up-spin shown in the upper half f and the density of states for down-spin shown in the lower half.

[0376] In the structure shown in Fig. 34(A), C is bonded to one In and two O atoms. In the model with Si, which is in the same group as C, placed between the lattice points, Si was only bonded to O. Referring to these results, it is speculated that the difference in the bonding states of Si and C is caused by the difference in ionic radius and electronegativity. Also, in Fig. 34(B), when the density of states between the lower end of the conduction band and the Fermi level E was integrated, the density of states corresponded to two electrons. f Since the Fermi level E is located two electron-vacuum level sides from the lower end of the conduction band, it is considered that by placing C between the lattice points, two electrons are released from C and IGZO(111) becomes n-type. f

[0377] <1-2. Model with a metal element replaced by C> Next, the optimal structure and density of states of the model with one In replaced by C are shown in Fig. 35. In Fig. 35(B), on the horizontal axis, the Fermi level E f is set to 0 eV.

[0378] In the structure shown in Fig. 35(A), C is bonded to three O atoms, forming a triangle with O at the vertices. It is located in the plane. Also, the schematic of the density of states shown in Fig. 35(B) is almost the same as that in the case without defects, but the Fermi level E is located one electron level closer to the vacuum level side than the bottom of the conduction band f . Therefore, by substituting In with C, one electron is emitted from C, and it is considered that IGZO(111) becomes n-type. This is considered to be due to the substitution of trivalent In with tetravalent C .

[0379] Next, the optimal structure and density of states of the model in which one Ga is replaced by C are shown in Fig. 36. Also, in Fig. 36(B), on the horizontal axis, the Fermi level E is set to 0 eV f .

[0380] In the structure shown in Fig. 36(A), C is bonded to four O atoms and is located almost at the center of the tetrahedron with O at the vertices . Also, the schematic of the density of states shown in Fig. 36(B) is almost the same as that in the case without defects, but the Fermi level E is located one electron level closer to the vacuum level side than the bottom of the conduction band f . Therefore, by substituting Ga with C, one electron is emitted from C, and it is considered that IGZO(111) becomes n-type. This is considered to be due to the substitution of trivalent Ga with tetravalent C .

[0381] Next, the optimal structure and density of states of the model in which one Zn is replaced by C are shown in Fig. 37. Also, in Fig. 37(B), on the horizontal axis, the Fermi level E is set to 0 eV f .

[0382] In the structure shown in Fig. 37(A), C is bonded to three O atoms and is located within the plane of the triangle with O at the vertices . Also, the schematic of the density of states shown in Fig. 37(B) is almost the same as that in the case without defects , but the Fermi level E f ​​is located two electrons away from the bottom of the conduction band toward the vacuum level. By replacing Zn with C, two electrons are released from C, and IGZO(111) becomes n This is thought to be due to the substitution of divalent Zn with tetravalent C.

[0383] <1-3. Model where O is replaced with C> Next, we considered whether C could be substituted for O. When one O is substituted for C, the O site becomes Considering the combination of metals that can be combined, there are four locations, so we created a substitution model for each. The structure was optimized by calculation. As a result, O bonded to two Ga atoms and one Zn atom was placed on C. The converted model was energetically stable.

[0384] IGZO(111) formed in an oxygen atmosphere contains a sufficient amount of O. To compare the energy required for C to substitute for O in IGZO(111), We consider models (1) and (2) in Table 10. Note that the following two models are mutually After matching the number of atoms to the total energy, the total energy was calculated.

[0385] [Table 10]

[0386] In order to investigate the stable configuration of C, we assumed IGZO(111) which contains a lot of oxygen. The total energy was calculated using a model that matches the model. The calculation results are shown in Table 11.

[0387] [Table 11]

[0388] In addition, model (1) in Table 10 shows that C exists as CO2 in IGZO(111). is the model to be considered. Also, the model in (2) of Table 10 is the model in which O of IGZO(111) is replaced by C replaced model.

[0389] As a result of the calculation, since the model of (1) was about 10.8 eV lower and more stable, it is considered that the model of (1) is more likely to occur than the model of (2 ) That is, it is considered that C is difficult to be replaced by O, and it is unstable for O to be replaced by C. As shown in Table 11, since C in IGZO(111) is more likely to occur due to lower energy in substitution with Ga than with O, it is considered that substitution with O is less likely to occur. In Table 11

[0390] 「IGZO:C 」 means that in InGaZnO4, an atom is replaced by C 」 means. 原子 」 means that an atom is replaced by C in InGaZnO4 」 means.

[0391] From the above results, it was found that when C is arranged in the interstices or C is replaced by a metal atom (In, Ga, Zn) 111), IGZO becomes n-type. Also, C in IGZO(1

[0392] 11) is considered to be stable especially when replaced by Ga. Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples.

[0393] (Embodiment 4) In this embodiment, a semiconductor device having a structure different from that of Embodiment 1 and a method for manufacturing the same will be described with reference to the drawings. The transistor 50 shown in this embodiment is different in that it is a transistor having a top gate structure as compared with the transistor 10 shown in Embodiment 1

[0394] ​​<1. Structure of Transistor> Figures 38(A) to 38(C) show a top view and cross-sectional views of the transistor 50. Fig. 3 8(A) is a top view of the transistor 50, and Fig. 38(B) is a cross-sectional view taken along the dashed line between points A and B in Fig. 38(A). Fig. 38(C) is a cross-sectional view taken along the dashed line C-D in Fig. 38(A). In Fig. 38(A), for clarity, the substrate 51, the protective film 53, the gate insulating film 5 9, the insulating film 63, etc. are omitted.

[0395] The transistor 50 shown in Fig. 38 includes an oxide semiconductor film 55 formed on the protective film 53, a pair of electrodes 57 and 58 in contact with the oxide semiconductor film 55, a gate insulating film 59 in contact with the oxide semiconductor film 55 and the pair of electrodes 57 and 58, and a gate electrode 61 overlapping the oxide semiconductor film 55 via the gate insulating film 59. Further, an insulating film 63 may be formed on the protective film 53, the pair of electrodes 57 and 58, the gate insulating film 59, and the gate electrode 61. In the present embodiment, at least one of the films in contact with the oxide semiconductor film 55, typically the protective film 53 and the gate insulating film 59, is an oxide insulating film containing nitrogen, and the oxide insulating film containing nitrogen is characterized by having a small defect amount.

[0396] Typical examples of the oxide insulating film containing nitrogen and having a small defect amount include a silicon oxynitride film,

[0397] an aluminum oxynitride film, etc. Note that the silicon oxynitride film and the aluminum oxynitride film refer to films having a higher oxygen content than nitrogen in terms of their composition, and the silicon nitride oxide film and the aluminum nitride oxide film refer to films having a higher nitrogen content than oxygen in terms of their composition.

[0398] ​​​​​​An oxide insulating film containing nitrogen and having a small amount of defects emits nitrogen oxides by heat treatment. (NO x , where x is 0 or more and 2 or less, preferably 1 or more and 2 or less), has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is large. Note that representative examples of nitrogen oxides include nitric oxide, nitrogen dioxide, etc. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 30 emitted by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is larger than the emission amount of the gas with a mass-to-charge ratio m / z = 46 emitted by heat treatment. Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is larger than the total emission amount of the gas with a mass-to-charge ratio m / z = 30 and the gas with a mass-to-charge ratio m / z = 46 emitted by heat treatment. Also, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 30 emitted by heat treatment is below the detection limit, and the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is 1×10 or more and 5×10 or less per cm . Or, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 46 emitted by heat treatment is below the detection limit and the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is 1×10

[0399] Also, an oxide insulating film containing nitrogen and having a small amount of defects has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 30 emitted by heat treatment is below the detection limit, and the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is 1×10 or more and 5×10 18 per cm 3 or less. Or, an oxide insulating film containing nitrogen and having a small amount of defects 19 has a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 46 emitted by heat treatment is below the detection limit 3 and the emission amount of the gas with a mass-to-charge ratio m / z = 17 emitted by heat treatment is 1×10 or more and 5×10 Yes, there is a region or portion where the emission amount of the gas with a mass-to-charge ratio m / z = 17 released by heat treatment is 1×10 18 pieces / cm 3 or more and 5×10 19 pieces / cm 3 or less. Or, an oxide insulating film containing nitrogen and having a small amount of defects has an emission amount of the gas with a mass-to-charge ratio m / z = 3 0 below the detection limit, an emission amount of the gas with a mass-to-charge ratio m / z = 4 6 below the detection limit, and an emission amount of the gas with a mass-to-charge ratio m / z = 1 7 is 1×10 or more and 5×10 18 pieces / cm 3 or less, and has a region 19 or portion. 3

[0400]

[0401] An oxide insulating film containing nitrogen and having a small amount of defects, after heat treatment, in the spectrum obtained by measuring with an ESR of 100 K or less has a first signal with a g value of 2.037 or more and 2.039 or less, a second signal with a g value of 2.001 or more and 2.003 or less, and a third signal with a g value of 1. 964 or more and 1.966 or less are observed. Also, the first signal with a g value of 2.037 or more 2.039 or less, the second signal with a g value of 2.001 or more and 2.003 or less signal, and the total spin density of the third signal with a g value of 1.964 or more and 1.966 or less is 1×10 or less, typically 1×10 18 spins / cm 3 ​17 spins / cm 3 is less than 1×10 18 spins / cm 3 .

[0402] In addition, in the ESR spectrum below 100K, the g value is 2.037 or more and 2.039 or less for the first signal, the g value is 2.001 or more and 2.003 or less for the second signal, and the g value is 1 .964 or more and 1.966 or less for the third signal, which corresponds to the signal caused by nitrogen oxides (NO x , where x is 0 or more and 2 or less , preferably 1 or more and 2 or less). Representative examples of nitrogen oxides include , nitric oxide, nitrogen dioxide, etc.

[0403] When at least one of the protective film 53 and the gate insulating film 59 in contact with the oxide semiconductor film 55 has a low content of nitrogen oxides as described above, it is possible to reduce carrier traps at the interface between the protective film 53 and the gate insulating film 59 and the oxide semiconductor film 55. As a result, it is possible to reduce fluctuations in the threshold voltage of the transistor included in the semiconductor device , and it is possible to reduce fluctuations in the electrical characteristics of the transistor.

[0404] In addition, at least one of the protective film 53 and the gate insulating film 59 preferably has a nitrogen concentration of 6×10 atoms / cm 20 or less as measured by SIMS. As a result, it is difficult for nitrogen oxides to be generated in at least one of the protective film 3 53 and the gate insulating film 59, and it is possible to reduce carrier traps at the interface between the protective film 53 or the gate insulating film 59 and the oxide semiconductor film 55. Also, the threshold voltage of the transistor included in the semiconductor device ​​​​It is possible to reduce the fluctuation of the low voltage, and thus the fluctuation of the electrical characteristics of the transistor is reduced. It is possible.

[0405] Other configuration details of transistor 50 are described below.

[0406] As the substrate 51, any of the substrates listed as the substrate 11 in the first embodiment can be used as appropriate.

[0407] When the gate insulating film 59 is formed of an oxide insulating film containing nitrogen and having few defects The protective film 53 is made of an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. Oxides containing more oxygen than meets the stoichiometric requirement can be formed. The insulating film can diffuse oxygen into the oxide semiconductor film by heat treatment. Representative examples of the film include silicon oxide film, silicon oxynitride film, silicon nitride oxide film, and gas oxide film. hafnium oxide film, yttrium oxide film, aluminum oxide film, aluminum oxynitride film Examples include minium membrane.

[0408] The protective film 53 has a thickness of 50 nm or more, preferably 200 nm or more and 3000 nm or less. The thickness of the protective film 53 is set to 300 nm or more and 1000 nm or less. It is possible to increase the amount of oxygen molecules released, and at the same time, the protective film 53 and the oxide film formed later can be prevented from being damaged. It is possible to reduce the interface state at the interface with the semiconductor film.

[0409] Here, "a part of the oxygen is released by heating" means that the amount of oxygen released is converted to oxygen atoms by TDS analysis. The amount of oxygen released is 1.0×10 18 atoms / cm 3 More than 3.0x1, preferably 0 20 atoms / cm 3This is the above. Note that during the above TDS analysis, the surface temperature of the membrane is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 500°C or lower. It is preferable.

[0410] The oxide semiconductor film 55 can be formed in the same manner as the oxide semiconductor film 17 shown in Embodiment 1. It can be done.

[0411] The pair of electrodes 57 and 58 can be formed in the same manner as the pair of electrodes 19 and 20 shown in Embodiment 1. It can be done.

[0412] In this embodiment, the pair of electrodes 57 and 58 are provided between the oxide semiconductor film 55 and the gate insulating film 59, but they may also be provided between the protective film 53 and the oxide semiconductor film 55.

[0413] When the protective film 53 is formed of an oxide insulating film containing nitrogen and having a small defect amount, the gate insulating film 59 can be, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a gallium oxide film, or a Ga-Z n-based metal oxide film, etc., and can be provided in a laminated or single-layer form. Note that in order to improve the interface characteristics with the oxide semiconductor film 55, at least the region in the gate insulating film 59 that contacts the oxide semiconductor film 55 is preferably formed of an oxide insulating film.

[0414] Also, by providing an insulating film having a blocking effect on oxygen, hydrogen, water, etc. as the gate insulating film 59, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 55 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 55. As the insulating film having a blocking effect on oxygen, hydrogen, water, etc., an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, etc. can be used. m films, gallium oxynitride films, yttrium oxide films, yttrium oxynitride films, hafnium oxide films, hafnium oxynitride films, and the like.

[0415] Also, as the gate insulating film 59, hafnium silicate (HfSiO x ), hafnium silicate (HfSi with nitrogen added x O y N z ), hafnium aluminate (HfAl with nitrogen added x O y N z ), high-k materials such as hafnium oxide and yttrium oxide can be used to reduce the gate leakage of the transistor. The gate insulating film 59 is, for example, 5 nm or more and 400 nm or less in thickness, more preferably 10 nm

[0416] or more and 300 nm or less, and still more preferably 15 nm or more and 100 nm or less. The gate electrode 61 can be formed in the same manner as the gate electrode 13 shown in Embodiment 1.

[0417] The insulating film 63 is made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum .

[0418] oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc., with a thickness of 30 nm or more and 500 nm or less, preferably 100 nm or more and 400 nm or less, and can be provided in a laminated or single-layer form. In addition, as the insulating film 63, like the protective film 53, an oxynitride insulating film containing more oxygen than the stoichiometric composition, and an insulating film having blocking properties for oxygen, hydrogen, water, etc. can be used.

[0419] ​​It may be a laminated structure of a film. As an insulating film having a blocking effect on oxygen, hydrogen, water, etc. are an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, a silicon nitride film, etc. As a result, in the heat treatment, oxygen is supplied to the oxide semiconductor film 55 through the gate insulating film 59 or / and the protective film 53, so that the interface level between the gate insulating film 59 or / and the protective film 53 and the oxide semiconductor film 55 can be reduced. In addition, the amount of oxygen deficiency contained in the oxide semiconductor film 55 can be reduced.

[0420] <2. Method for manufacturing a transistor> Next, the method for manufacturing a transistor shown in FIG. 38 will be described with reference to FIG. 39. Note that , in FIG. 39, a cross-sectional view in the channel length direction shown by the dashed line A-B in FIG. 38(A), and a cross-sectional view in the channel width direction shown by the dashed line C-D are used to describe the method for manufacturing the transistor 50.

[0421] As shown in FIG. 39(A), a protective film 53 is formed on the substrate 51. Next, an oxide semiconductor film 55 is formed on the protective film 53.

[0422] The protective film 53 is formed by a sputtering method, a CVD method, or the like.

[0423] When forming an oxide insulating film containing nitrogen and having a small amount of defects as the protective film 53, as an example of the oxide insulating film containing nitrogen and having a small amount of defects, a silicon oxynitride film can be formed by the CVD method. In this case, as the source gas, it is preferable to use a depositable gas containing silicon and an oxidizing gas. As a typical example of the depositable gas containing silicon and an oxidizing gas.​​​ There are silane, disilane, trisilane, silicon fluoride, etc. As the oxidizing gas, there are nitrous oxide, nitrogen dioxide, etc.

[0424] In addition, in the case of forming an oxide insulating film from which a part of oxygen desorbs by heating as the protective film 53, in the case of an oxide insulating film from which a part of oxygen desorbs by heating, it is preferably formed by a sputtering method using conditions with a high oxygen amount in the film-forming gas, and oxygen, or a mixed gas of oxygen and a rare gas, etc. can be used. Typically, it is preferable to set the oxygen concentration in the film-forming gas to 6% or more and 100% or less.

[0425] In addition, in the case of forming an oxide insulating film from which a part of oxygen desorbs by heating as the protective film 53, in the case of an oxide insulating film from which a part of oxygen desorbs by heating, after forming the oxide insulating film by the CVD method, by introducing oxygen into the oxide insulating film, the amount of oxygen desorbing by heating can be increased. As a method of introducing oxygen into the oxide insulating film, there are ion implantation method, ion doping method, plasma treatment, etc. In the present embodiment, since an oxide semiconductor film is not provided under the protective film 53, even if oxygen is introduced into the protective film 53, there is no damage to the oxide semiconductor film. Therefore, oxygen can be introduced into the protective film 53 in contact with the oxide semiconductor film without damaging the oxide semiconductor film.

[0426] In addition, when forming an oxide insulating film by the CVD method as the protective film 53, hydrogen or water derived from the source gas may be mixed into the oxide insulating film. Therefore, after forming the oxide insulating film by the CVD method, it is preferable to perform a heat treatment as dehydrogenation or dehydration.

[0427] The oxide semiconductor film 55 can be suitably formed in the same manner as the oxide semiconductor film 17 shown in Embodiment 1. It can be suitably used.

[0428] In addition, in order to enhance the orientation of the crystal portions included in the CAAC-OS film, it is preferable to improve the flatness of the surface of the protective film 53, which is the underlying insulating film of the oxide semiconductor film. Typically, the average surface roughness (Ra) of the protective film 53 can be 1 nm or less, 0.3 nm or less, or 0.1 nm or less. It can be achieved. As a planarization process for improving the flatness of the surface of the protective film 53, one or more of chemical mechanical polishing (CMP) treatment, dry etching treatment, and plasma treatment (so-called reverse sputtering) in which an inert gas such as argon gas is introduced into a vacuum chamber and an electric field is applied with the surface to be treated as the cathode to flatten the fine irregularities on the surface can be applied. It can be achieved.

[0429] As a planarization process for improving the flatness of the surface of the protective film 53, one or more of chemical mechanical polishing (CMP) treatment, dry etching treatment, and plasma treatment (so-called reverse sputtering) in which an inert gas such as argon gas is introduced into a vacuum chamber and an electric field is applied with the surface to be treated as the cathode to flatten the fine irregularities on the surface can be applied. ical Mechanical Polishing:CMP) treatment, dry etching treatment, and plasma treatment (so-called reverse sputtering) in which an inert gas such as argon gas is introduced into a vacuum chamber and an electric field is applied with the surface to be treated as the cathode to flatten the fine irregularities on the surface can be applied. treatment, and plasma treatment (so-called reverse sputtering) in which an inert gas such as argon gas is introduced into a vacuum chamber and an electric field is applied with the surface to be treated as the cathode to flatten the fine irregularities on the surface can be applied. treatment, and plasma treatment (so-called reverse sputtering) in which an inert gas such as argon gas is introduced into a vacuum chamber and an electric field is applied with the surface to be treated as the cathode to flatten the fine irregularities on the surface can be applied.

[0430] Next, as shown in FIG. 39(B), a pair of electrodes 57 and 58 are formed. The pair of electrodes 57 and 58 can be suitably formed in the same manner as the pair of electrodes 19 and 20 shown in Embodiment 1. Alternatively, the pair of electrodes 57 and 58 can be formed by a printing method or an inkjet method. It can be suitably used. It can be suitably used. It can be formed.

[0431] Next, as shown in FIG. 39(C), a gate insulating film 59 and a gate electrode 61 are formed. An insulating film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a conductive film is formed on the insulating film by a sputtering method, a CVD method, an evaporation method, etc. Next, a mask is formed on the conductive film by a photolithography process. Next, a part of the insulating film and the conductive film is etched using the mask. An insulating film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a conductive film is formed on the insulating film by a sputtering method, a CVD method, an evaporation method, etc. Next, a mask is formed on the conductive film by a photolithography process. Next, a part of the insulating film and the conductive film is etched using the mask. An insulating film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a conductive film is formed on the insulating film by a sputtering method, a CVD method, an evaporation method, etc. Next, a mask is formed on the conductive film by a photolithography process. Next, a part of the insulating film and the conductive film is etched using the mask. An insulating film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a conductive film is formed on the insulating film by a sputtering method, a CVD method, an evaporation method, etc. Next, a mask is formed on the conductive film by a photolithography process. Next, a part of the insulating film and the conductive film is etched using the mask. Etch and form the gate insulating film 59 and the gate electrode 61. After that, remove the mask. Do.

[0432] The film that becomes the gate insulating film 59 is formed by a sputtering method, a CVD method, an evaporation method, or the like. The film that becomes the gate electrode 61 is formed by a sputtering method, a CVD method, an evaporation method, or the like. Do.

[0433] In addition, when forming an oxide insulating film that contains nitrogen and has a small amount of defects as the film that becomes the gate insulating film 59, it can be formed by appropriately using the same conditions as the protective film 53. Do.

[0434] Next, as shown in Fig. 39(D), form an insulating film 63 on the substrate 51, the pair of electrodes 57, 58, the gate insulating film 5 9, and the gate electrode 61. The insulating film 63 can be formed by appropriately using a sputtering method, a CVD method, a printing method, a coating method, or the like. Do.

[0435] Next, similar to Embodiment 1, heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and lower than the substrate distortion point, preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower.

[0436] By the above steps, a transistor with reduced threshold voltage variation can be fabricated. Also, a transistor with reduced electrical property variation can be fabricated.

[0437] In addition, the configurations and methods shown in this embodiment can be appropriately combined and used with the configurations and methods shown in other embodiments and examples. Do.

[0438] <Modification 1> A modification of the transistor 50 shown in Embodiment 4 will be described with reference to Fig. 40. This The transistor described in the modification example will be described with respect to an example in which the gate insulating film or the protective film has a laminated structure. Hereinafter.

[0439] The transistor 50a shown in FIG. 40(A) is characterized in that the protective film 53 has a multilayer structure. Specifically, the protective film 53 is formed by laminating an oxide insulating film 65 and an oxide insulating film 67. The oxide insulating film 65 contains more oxygen than oxygen satisfying the stoichiometric composition, and the oxide insulating film 67 in contact with the oxide semiconductor film 55 can be used for at least one of the protective film 53 and the gate insulating film 59 of the transistor 50. It is an oxide insulating film containing nitrogen and having a small amount of defects.

[0440] The oxide insulating film 65 containing more oxygen than oxygen satisfying the stoichiometric composition has a thickness of 50 nm or more, preferably 200 nm or more and 3000 nm or less, more preferably 300 nm or more and 1000 nm or less. By increasing the thickness of the oxide insulating film 65 containing more oxygen than oxygen satisfying the stoichiometric composition, the amount of oxygen molecules released from the oxide insulating film 65 containing more oxygen than oxygen satisfying the stoichiometric composition can be increased, and the interface level at the interface between the oxide insulating film 67 and the oxide semiconductor film 55 can be reduced.

[0441] As a method for forming the oxide insulating film 65 containing more oxygen than oxygen satisfying the stoichiometric composition, an oxide insulating film in which a part of oxygen is desorbed by heating, as described for the protective film 53, can be appropriately used.

[0442] Further, for the oxide insulating film 67, the method for forming an oxide insulating film containing nitrogen and having a small amount of defects, which is listed for the protective film 53 and the gate insulating film 59 included in the transistor 50, is used. ​ can be done.

[0443] Note that the oxide insulating film 65 and the oxide A dielectric film 67 is formed, an oxide semiconductor film 55 is formed on the oxide dielectric film 67, and then, a heating process is performed. The heat treatment may be carried out to produce more oxygen than the oxygen required for the stoichiometric composition. Part of the oxygen contained in the oxide insulating film 65 containing oxygen is converted into As a result, the oxide insulating film 67 and the oxide semiconductor film 55 can be diffused in the vicinity of the interface. It is possible to reduce the interface state in the vicinity of the interface of the conductor film 55, and the change in the threshold voltage is This can reduce movement.

[0444] The temperature of the heat treatment is typically 150° C. or higher and lower than the substrate distortion point, preferably 250° C. or higher. The temperature is preferably 300° C. or higher and 450° C. or lower, and more preferably 300° C. or higher and 450° C. or lower.

[0445] Heat treatment is carried out using rare gases such as helium, neon, argon, xenon, krypton, etc., or The heating is performed in an inert gas atmosphere containing nitrogen, or after heating in an inert gas atmosphere, the heating is performed in an oxygen atmosphere. The inert atmosphere and oxygen atmosphere may contain hydrogen, water, etc. The treatment time is preferably from 3 minutes to 24 hours.

[0446] In a transistor 50b shown in FIG. 40B, the gate insulating film 59 is formed of an oxide insulating film 69 and A nitride insulating film 71 is laminated in this order, and the oxide insulating film 71 is in contact with the oxide semiconductor film 55. The insulating film 69 is characterized by containing nitrogen and having a small amount of defects.

[0447] The nitride insulating film 71 is the same as the nitride insulating film 29 shown in the first modification of the first embodiment. It is preferable to use a film. As a result, the gate insulating film 59 can be physically thickened. Therefore, a decrease in the breakdown voltage of the transistor 50b can be suppressed, and further, the breakdown voltage can be improved, thereby suppressing electrostatic breakdown of the semiconductor device.

[0448] <Modification 2> A modification of the transistor 50 shown in Embodiment 4 will be described with reference to FIG. 41. In this modification, a transistor having an oxide semiconductor film between a pair of electrodes and a gate insulating film will be described.

[0449] FIGS. 41(A) to 41(C) are a top view and cross-sectional views of a transistor 50c included in a semiconductor device according to an aspect of the present invention. FIG. 41(A) is a top view, FIG. 41(B) shows a schematic cross-sectional view taken along the dashed line A-B in FIG. 41(A), and FIG. 41(C) shows a schematic cross-sectional view taken along the dashed line C-D in FIG. 41(A). The transistor 50c shown in FIGS. 41(B) and 41(C) includes an oxide semiconductor film 73 formed on a protective film 53, an oxide semiconductor film 55 formed on the oxide semiconductor film 73, a pair of electrodes 57 and 58 in contact with the oxide semiconductor film 55 and the oxide semiconductor film 73, an oxide semiconductor film 75 in contact with the oxide semiconductor film 55 and the pair of electrodes 57 and 58, a gate insulating film 59 formed on the oxide semiconductor film 75, and a gate electrode 61 overlapping the oxide semiconductor film 55 with the gate insulating film 59 interposed therebetween. Further, an insulating film 63 may be formed on the protective film 53, the pair of electrodes 57 and 58, the oxide semiconductor film 75, the gate insulating film 59, and the gate electrode 61.

[0450]

[0451] In the transistor 50c, the protective film 53 has a convex portion, and a stacked oxide semiconductor film 73 and an oxide semiconductor film 55 are provided on the convex portion of the protective film 53.

[0452] As shown in FIG. 41(B), the oxide semiconductor film 75 is in contact with the upper surface of the oxide semiconductor film 55, and the upper surfaces and side surfaces of the pair of electrodes 57 and 58, and as shown in FIG. 41(C), the oxide semiconductor film 75 is in contact with the side surfaces of the convex portion of the protective film 53, the side surfaces and the upper surface of the oxide semiconductor film 73, the side surface and the upper surface of the oxide semiconductor film 55.

[0453] As shown in FIG. 41(C), in the channel width direction of the transistor 50c, the gate electrode 61 faces the upper surface and the side surface of the oxide semiconductor film 55 via the oxide semiconductor film 75 and the gate insulating film 59.

[0454] The gate electrode 61 electrically surrounds the oxide semiconductor film 55. With this structure, the on-current of the transistor 50c can be increased. Such a transistor structure is called a Surrounded Channel (S-Channel) structure. In the S- Channel structure, the current flows through the entire (bulk) oxide semiconductor film 55. Since the current flows inside the oxide semiconductor film 55, it is less affected by interface scattering, and thus a high on-current can be obtained. Note that increasing the thickness of the oxide semiconductor film 55 can improve the on-current.

[0455] Also, when miniaturizing the channel length and channel width of the transistor, if a pair of electrodes, an oxide semiconductor film, etc. are formed while retracting the resist mask, the ends of the pair of electrodes and the oxide semiconductor film may be rounded (have a curved surface). With such a configuration, the oxide semiconductor film ​​​​​​​The covering properties of the oxide semiconductor film 75 and the gate insulating film 59 formed on the conductor film 55 can be improved. Moreover, the electric field concentration that may occur at the ends of the pair of electrodes 57 and 58 can be alleviated. This can suppress the deterioration of the transistor.

[0456] In addition, by miniaturizing the transistor, the integration degree can be increased and the density can be made higher. For example, the channel length of the transistor is set to 100 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. And the channel width of the transistor is set to 100 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. Even when the channel width of the transistor according to one embodiment of the present invention is reduced as described above, by having an S-channel structure, the on-current can be increased. This can be achieved.

[0457] Note that for the oxide semiconductor film 73, the material of the oxide semiconductor film 46 shown in Modification Example 4 of Embodiment 1 can be appropriately used. Also, in FIG. 39(A), before forming the film that becomes the oxide semiconductor film 55, a film that becomes the oxide semiconductor film 73 is formed. Next, by processing the film that becomes the oxide semiconductor film 73 and the film that becomes the oxide semiconductor film 55, the oxide semiconductor film 73 and the oxide semiconductor film 55 can be formed.

[0458] For the oxide semiconductor film 75, the material of the oxide semiconductor film 47 shown in Modification Example 4 of Embodiment 1 can be appropriately used. Also, in FIG. 39(C), before forming the film that becomes the gate insulating film 59, a film that becomes the oxide semiconductor film 75 is formed. Next, the film that becomes the gate insulating film 59 and ​​​After forming the film to be the gate electrode 61, by processing them simultaneously, the oxide semiconductor film 75, the gate insulating film 59, and the gate electrode 61 can be formed. The oxide semiconductor film 75, the gate insulating film 59, and the gate electrode 61 can be formed.

[0459] Also, the oxide semiconductor film 73 may have a thickness such that the effect of suppressing the generation of interface levels of the oxide semiconductor film 55 is not lost. For example, the oxide semiconductor film 55 may have a region with a thickness greater than 1 times, preferably 2 times or more, more preferably 4 times or more, more preferably 6 times or more the thickness of the oxide semiconductor film 73. Note that this is not the case when it is not necessary to increase the on-current of the transistor. The oxide semiconductor film 73 may have a region with a thickness equal to or greater than the thickness of the oxide semiconductor film 55. more preferably 6 times or more the thickness of the oxide semiconductor film 73. Note that this is not the case when it is not necessary to increase the on-current of the transistor. The oxide semiconductor film 73 may have a region with a thickness equal to or greater than the thickness of the oxide semiconductor film 55. Also, the oxide semiconductor film 75 may have a region with a thickness such that the effect of suppressing the generation of interface levels of the oxide semiconductor film 55 is not lost, similar to the oxide semiconductor film 73. For example, it may have a region with a thickness equal to or less than that of the oxide semiconductor film 73. If the oxide semiconductor film 75 is thick, there is a risk that the electric field by the gate electrode 61 will not easily reach the oxide semiconductor film 55. Therefore, it is preferable to form the oxide semiconductor film 75 thin. For example, it may have a region thinner than the thickness of the oxide semiconductor film 55. Note that this is not limited to this. The thickness of the oxide semiconductor film 75

[0460] Also, the oxide semiconductor film 75 may have a region with a thickness such that the effect of suppressing the generation of interface levels of the oxide semiconductor film 55 is not lost, similar to the oxide semiconductor film 73. For example, it may have a region with a thickness equal to or less than that of the oxide semiconductor film 73. If the oxide semiconductor film 75 is thick, there is a risk that the electric field by the gate electrode 61 will not easily reach the oxide semiconductor film 55. it may have a region with a thickness equal to or less than that of the oxide semiconductor film 73. If the oxide semiconductor film 75 is thick, there is a risk that the electric field by the gate electrode 61 will not easily reach the oxide semiconductor film 55. Therefore, it is preferable to form the oxide semiconductor film 75 thin. For example, it may have a region thinner than the thickness of the oxide semiconductor film 55. Note that this is not limited to this. The thickness of the oxide semiconductor film 75 Therefore, it is preferable to form the oxide semiconductor film 75 thin. For example, it may have a region thinner than the thickness of the oxide semiconductor film 55. Note that this is not limited to this. The thickness of the oxide semiconductor film 75 Therefore, it is preferable to form the oxide semiconductor film 75 thin. For example, it may have a region thinner than the thickness of the oxide semiconductor film 55. Note that this is not limited to this. The thickness of the oxide semiconductor film 75 should be appropriately set according to the voltage for driving the transistor, considering the breakdown voltage of the gate insulating film 59. should be appropriately set according to the voltage for driving the transistor, considering the breakdown voltage of the gate insulating film 59.

[0461] To highly integrate a semiconductor device, miniaturization of transistors is essential. On the other hand, it is known that the electrical characteristics of transistors deteriorate due to miniaturization of transistors. When the channel width is reduced, the on-current decreases. When the channel width is reduced, the on-current decreases.

[0462] However, in the transistor according to one aspect of the present invention, as described above, an oxide semiconductor film 75 is formed so as to cover a region where a channel of 55 is formed, and the channel region is not in contact with the gate insulating film 59. Therefore, scattering of carriers occurring at the interface between the oxide semiconductor film 55 and the gate insulating film 59 can be suppressed, and the on-current of the transistor can be increased.

[0463] In addition, when the oxide semiconductor film is made intrinsic or substantially intrinsic, a decrease in the number of carriers contained in the oxide semiconductor film causes concern about a decrease in the field-effect mobility. However, in the transistor according to one aspect of the present invention, in addition to a gate electric field from the vertical direction being applied to the oxide semiconductor film 55, a gate electric field from the lateral direction is also applied. That is, a gate electric field is applied to the entire oxide semiconductor film 55, and the current flows through the bulk of the oxide semiconductor film. As a result, while suppressing fluctuations in electrical characteristics due to high-purity intrinsic conversion, it is possible to improve the field-effect mobility of the transistor. Furthermore, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface levels by forming the oxide semiconductor film 55 on the oxide semiconductor film 73, and being able to eliminate the influence of impurity mixing from above and below by providing the oxide semiconductor film 55 between the oxide semiconductor films 73 and 75. Therefore, the oxide semiconductor film 55 has a structure surrounded by the oxide semiconductor film 73 and the oxide semiconductor film 75 (and also a structure electrically surrounded by the gate electrode 61), and in addition to the improvement in the on-current of the transistor described above, it is possible to stabilize the threshold voltage.

[0464] ​​​​​​​​​​​Therefore, the current flowing between the source and drain when the gate voltage is 0V is This allows the power consumption to be reduced. Since the voltage is stabilized, the long-term reliability of the semiconductor device can be improved.

[0465] The structures and methods described in this embodiment may be used in conjunction with structures and methods described in other embodiments and examples. and the like.

[0466] (Embodiment 5) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0467] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), oxide semiconductors having an amorphous structure (hereinafter referred to as microcrystalline oxide semiconductors) and oxide semiconductors having an amorphous structure (hereinafter referred to as The oxide semiconductor film may be formed of at least one of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The insulating film may be made of an oxide semiconductor having a conductor and crystal grains.

[0468] Oxide semiconductors are classified into non-single-crystal oxide semiconductors and single-crystal oxide semiconductors. Alternatively, oxide semiconductors can be divided into crystalline oxide semiconductors and amorphous oxide semiconductors, for example. can be done.

[0469] As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligne d Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, and the like. Further, as the crystalline oxide semiconductor, there are single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and the like. Hereinafter, CAAC-OS, microcrystalline oxide semiconductors, and amorphous oxide semiconductors will be described.

[0470] First, CAAC-OS will be described. Hereinafter.

[0471] First, CAAC-OS will be described.

[0472] CAAC-OS is one of the oxide semiconductors having a plurality of crystal parts (also referred to as pellets) oriented in the c-axis direction. It is one of the semiconductor.

[0473] When CAAC-OS is observed by a transmission electron microscope (TEM: Transmission Elect ron Microscope), it is not possible to confirm a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary). Therefore, it can be said that CA AC-OS is less likely to cause a decrease in electron mobility due to grain boundaries. For example, as shown in Fig. 73(A), a high-resolution TEM image of the cross-section of CAAC-OS is observed from a direction substantially parallel to the sample surface. Here, the TEM image is observed using a spherical aberration corrector (Spherical A

[0474] berration Corrector) function. In addition, a high-resolution TEM image using the spherical aberration correction function is hereinafter particularly referred to as a Cs-corrected high-resolution TEM image . The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by a JEOL atomic resolution analytical electron microscope JEM-ARM200F or the like manufactured by JEOL Ltd. berration Corrector) function. Here, the high-resolution TEM image using the spherical aberration correction function is hereinafter particularly referred to as a Cs-corrected high-resolution TEM image . The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by a JEOL atomic resolution analytical electron microscope JEM-ARM200F or the like manufactured by JEOL Ltd. . The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by a JEOL atomic resolution analytical electron microscope JEM-ARM200F or the like manufactured by JEOL Ltd. . The acquisition of a Cs-corrected high-resolution TEM image can be performed, for example, by a JEOL atomic resolution analytical electron microscope JEM-ARM200F or the like manufactured by JEOL Ltd.

[0475] An enlarged Cs-corrected high-resolution TEM image of the region (1) in Fig. 73(A) is shown in Fig. 73(B). From Fig. 73(B), it can be confirmed that in the crystal part, metal atoms are arranged in layers. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed.) or the upper surface of the CAAC-OS film, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS.

[0476] In Fig. 73(B), CAAC-OS has a characteristic atomic arrangement. Fig. 73(C) shows the characteristic atomic arrangement indicated by auxiliary lines. From Fig. 73(B) and Fig. 73(C), it can be seen that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap formed by the inclination between pellets is about 0.8 nm. Therefore, the pellet can also be called a nanocrystal (nc).

[0477] Here, when schematically showing the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 from the Cs-corrected high-resolution TEM image, it has a structure like bricks or blocks stacked on top of each other (see Fig. 73(D)). The location where the inclination occurs between the pellets observed in Fig. 73(C) corresponds to the region 5161 shown in Fig. 73(D).

[0478] Also, for example, as shown in Fig. 74(A), a Cs-corrected high-resolution TEM image of the plane of CAAC- OS is observed from a direction substantially perpendicular to the sample surface. Enlarged Cs-corrected high-resolution TEM images of the region (1), region ( 2), and region (3) in Fig. 74(A) are shown in Fig. 74(B), Fig. 74(C), and Fig. 74(D), respectively. Fig. 74(B), Fig. 74(C), and Fig. 74(D​​​​​ ) From this, it can be confirmed that in the crystal part, the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is found in the arrangement of the metal atoms between different crystal parts.

[0479] Figure 70(A) is a high-resolution TEM image of the cross-section of CAAC-OS. Also, Figure 70(B ) is a high-resolution TEM image of the cross-section obtained by further magnifying Figure 70(A), and the atomic arrangement is highlighted for easy understanding.

[0480] Figure 70(C) is a local Fourier transform image of the region (diameter approximately 4 nm) surrounded by a circle between A-O-A' in Figure 70(A). From Figure 70(C), c-axis orientation can be confirmed in each region. Also, since the direction of the c-axis is different between A-O and O-A', it is suggested that they are different grains. Also, between A-O, it can be seen that the angle of the c-axis changes continuously little by little, such as 14.3°, 16. 6°, 26.4°. Similarly, between O-...

Claims

1. A light-emitting device having pixels and source signal lines, wherein each pixel includes a light-emitting element, a first transistor, a second transistor, and a third transistor, the first transistor having a first gate, the second transistor having a second gate and a third gate, the third transistor having a fourth gate, a channel formation region of the first transistor and a channel formation region of the second transistor being electrically connected in series between the source signal line and the fourth gate, either the source or the drain of the third transistor being electrically connected to the light-emitting element, either the second gate or the third gate being electrically connected to the first gate, a first gate electrode serving as the first gate being provided on an insulating surface, a gate insulating film being provided on the first gate electrode, a first oxide semiconductor film being provided on the gate insulating film, a pair of electrodes serving as a source electrode and a drain electrode being provided in contact with an upper surface of the first oxide semiconductor film, a protective film being provided in contact with upper surfaces of the first oxide semiconductor film, the source electrode, and the drain electrode, either the gate insulating film or the protective film being a silicon oxynitride film, when a stress time is 0.1 hour, a temperature is 60° C., +30 V is applied to the first gate electrode, and 0 V is applied to the pair of electrodes, in a graph in which the horizontal axis (x) indicates the logarithm of the stress time and the vertical axis (y) indicates the logarithm of the absolute value of the variation amount of the threshold voltage of the first transistor, an exponent of a power approximation line of the variation value of the threshold voltage is −0.1 or more and 0.3 or less, and the variation amount of the threshold voltage is less than 0.3 V. However, the power approximation line is represented by the following mathematical formula (1). Note that b and C are constants, and b is the exponent of the power approximation line. (Equation 1) y = Cx^b (1)

2. A light-emitting device having pixels and source signal lines, wherein each pixel includes a light-emitting element, a first transistor, a second transistor, and a third transistor, the first transistor having a first gate, the second transistor having a second gate and a third gate, the third transistor having a fourth gate and a fifth gate, ​ ​ The channel formation region of the first transistor and the channel formation region of the second transistor are electrically connected in series between the source signal line and the fourth gate. Either the source or the drain of the third transistor is electrically connected to the light-emitting element. Either one of the second gate and the third gate is electrically connected to the first gate. A first gate electrode that functions as the first gate is provided on the insulating surface. A gate insulating film is provided on the first gate electrode. A first oxide semiconductor film is provided on the gate insulating film. A pair of electrodes that function as a source electrode and a drain electrode are provided in contact with the upper surface of the first oxide semiconductor film. A protective film is provided in contact with the upper surface of the first oxide semiconductor film, the upper surface of the source electrode, and the upper surface of the drain electrode. One of the gate insulating film and the protective film is a silicon oxynitride film. When the stress time is 0.1 hour, the temperature is 60°C, +30 V is applied to the first gate electrode, and 0 V is applied to the pair of electrodes, in a graph where the horizontal axis (x) represents the logarithm of the stress time and the vertical axis (y) represents the logarithm of the absolute value of the variation amount of the threshold voltage of the first transistor, the exponent of the power approximation line of the variation value of the threshold voltage is -0.1 or more and 0.3 or less, and the variation amount of the threshold voltage is less than 0.3 V. However, the power approximation line is represented by the following mathematical formula (1). Note that b and C are constants, and b is the exponent of the power approximation line. (Equation 2) y = Cx^b (1)

3. A pixel, A source signal line, A power supply line, and a light-emitting device having the same. The pixel includes a light-emitting element, a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a first gate. The second transistor has a second gate and a third gate. The third transistor has a fourth gate. The fourth transistor has a fifth gate and a sixth gate. The channel formation region of the first transistor and the channel formation region of the second transistor are electrically connected in series between the source signal line and the fourth gate. The channel formation region of the third transistor and the channel formation region of the fourth transistor are electrically connected in series between the power supply line and the light-emitting element. Either one of the second gate and the third gate is electrically connected to the first gate, Either one of the fifth gate and the sixth gate is electrically connected to the fourth gate, A first gate electrode that functions as the first gate is provided on an insulating surface, A gate insulating film is provided on the first gate electrode, A first oxide semiconductor film is provided on the gate insulating film, A pair of electrodes that function as a source electrode and a drain electrode are provided in contact with the upper surface of the first oxide semiconductor film, A protective film is provided in contact with the upper surface of the first oxide semiconductor film, the upper surface of the source electrode, and the upper surface of the drain electrode, One of the gate insulating film and the protective film is a silicon oxynitride film, When the stress time is 0.1 hour, the temperature is 60 ° C., +30 V is applied to the first gate electrode, and 0 V is applied to the pair of electrodes, in a graph where the horizontal axis (x) represents the logarithm of the stress time and the vertical axis (y) represents the logarithm of the absolute value of the variation amount of the threshold voltage of the first transistor, the exponent of the power approximation line of the variation value of the threshold voltage is −0.1 or more and 0.3 or less, and the variation amount of the threshold voltage is less than 0.3 V. However, the power approximation line is represented by the following mathematical formula (1). Note that b and C are constants, and b is the exponent of the power approximation line. (Equation 3) y = Cx^b (1)

4. In any one of Claims 1 to 3, The pixel has a capacitance, One terminal of the capacitance is electrically connected to a fourth gate.

5. In any one of Claims 1 to 4, The second oxide semiconductor film includes the channel formation region of the second transistor, A light-emitting device having the second oxide semiconductor film between the second gate and the third gate.

Images