Semiconductor device

Abstract

To provide a storage device capable of suppressing power consumption, and to provide a semiconductor device using the same.SOLUTION: As a switching element for holding electric charges stored in a transistor that functions as a storage element, a transistor that uses an oxide semiconductor film as an active layer is provided on each memory cell of a storage device. The transistor used as the storage element comprises: a first gate electrode; a second gate electrode; a semiconductor film located between the first gate electrode and the second gate electrode; a first insulating film located between the first gate electrode and the semiconductor film; a second insulating film located between the second gate electrode and the semiconductor film; and a source electrode and a drain electrode contacted with the semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a non-volatile semiconductor memory device, and to a configuration and driving method of a memory cell for storing data. do. [Background technology]

[0002] Semiconductor memory devices (hereafter simply referred to as memory devices) include DRAM, which is classified as volatile memory. , SRAM, Mask ROM, EPROM, EEPROM, Flash, which are classified as non-volatile memory These include flash memory and ferroelectric memory, which are formed using single-crystal semiconductor substrates. Many of these memories are already in practical use. Among the above semiconductor memories, flash Memory allows data to be written and erased repeatedly, and can operate without a power supply. Since it is a non-volatile memory that can retain data, it is highly convenient and resistant to physical shock. Because of its strength, it is mainly used in portable storage media such as USB memory and memory cards, and is It is widely available in.

[0003] There are two types of flash memory: NAND type, which has a structure in which multiple memory cells are connected in series, and There are two types of NOR type, which has a structure in which multiple memory cells are connected in a matrix. Each flash memory has a transistor that functions as a memory element in each memory cell. The transistor that functions as this memory element is called a floating gate. The electrode for storing electric charges is provided between the gate electrode and the semiconductor film which is the active layer. Thus, data can be stored by accumulation of charge on the floating gate.

[0004] The following Patent Documents 1 and 2 disclose floating gates formed on a glass substrate. A thin film transistor having the same is described.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] By the way, in the case of a non-volatile memory, the absolute value of the voltage applied to the memory element when writing data tends to be generally larger than that of a volatile memory, around 20V. When repeatedly rewriting data in the case of a flash memory that can be performed, not only when writing data but also when erasing data, it is necessary to apply a large voltage to the transistor used as the memory element . Therefore, the power consumed during the operation of a flash memory, such as writing and erasing data, is high, and this is one of the factors that hinder the reduction of power consumption of electronic devices using a flash memory as a storage device. In particular, when using a flash memory in a portable electronic device such as a camera or a mobile phone, the high power consumption leads to the drawback of shortening the continuous use time. Moreover, although a flash memory is a non-volatile memory, data is lost due to leakage of minute charges. Therefore, it is said that the data retention period is currently about 5 to 10 years, and the realization of a flash memory capable of ensuring a longer retention period is desired.

[0007]

[0008] ​​​Furthermore, although the flash memory can repeatedly write and erase data, when accumulating charges in the floating gate, the gate insulating film is liable to deteriorate due to the tunneling current. Therefore, the number of times data can be rewritten in one memory element is limited to about several tens of thousands of times, and the realization of a flash memory that can withstand more rewrite times is desired. In view of the above problems, one object of the present invention is to provide a memory device capable of suppressing power consumption, and a semiconductor device using the memory device. Another object of the present invention is to provide a memory device capable of holding data for a longer period of time, and a semiconductor device using the memory device. Another object of the present invention is to provide a memory device capable of increasing the number of times data can be rewritten, and a semiconductor device using the memory device.

[0009]

Means for Solving the Problems

[0010] In one aspect of the present invention, a transistor having a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode is used as a memory element to constitute a non-volatile memory device. And in the above memory device, instead of injecting charges into the floating gate surrounded by the insulating film at a high voltage, the potential of the second gate electrode for controlling the threshold voltage of the transistor used as the memory element is controlled by a transistor with an extremely small off-current to write data. That is, the memory device according to one aspect of the present invention includes at least a transistor whose threshold voltage is controlled by a second gate electrode, a capacitive element for holding the potential of the second gate electrode, and a switching element for controlling the charge and discharge of the capacitive element. ​​​​It is characterized by being composed of a transistor used as a child.

[0011] The shift amount of the threshold voltage of the transistor used as a memory element is related to the potential of the second gate electrode. Height, more specifically, it is controlled by the potential difference between the source electrode and the second gate electrode. And The difference in the height of the threshold voltage, or the difference in the resistance value between the source electrode and the drain electrode due to the difference in the height of the threshold voltage, becomes the difference in the data stored in the memory element.

[0012] The transistor used as a memory element may be an insulated gate field effect transistor. Specifically, it has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

[0013] And the transistor used as a switching element includes a semiconductor material having a wider bandgap and a lower intrinsic carrier density than silicon in the channel formation region. By including such a semiconductor material in the channel formation region, a transistor with an extremely low off-current can be realized. Examples of such a semiconductor material include an oxide semiconductor, silicon carbide, and gallium nitride, which have a bandgap about three times that of silicon.

[0014] Note that the oxide semiconductor exhibits semiconductor characteristics that combine the high mobility obtained by microcrystalline silicon or polycrystalline silicon and the uniform device characteristics obtained by amorphous silicon. ​​​​​​​​​ is a metal oxide. And impurities such as moisture or hydrogen that act as electron donors The purified oxide semiconductor (purified OS) with reduced and highly purified impurities is of type i (intrinsic semiconductor) or extremely close to type i. The transistor using the above oxide semiconductor has the characteristic that the off-current is extremely low. Specifically, impurities such as moisture or hydrogen contained in the oxide semiconductor are removed, and the measured value of the hydrogen concentration in the oxide semiconductor by secondary ion mass spectrometry (SIMS) is 5×10 / cm or less, preferably 5×10 19 / cm 3 or less, more preferably 18 / cm 3 or less, even more preferably 5×10 17 / cm 3 or less, still more preferably 1×10 16 / cm 3 or less. Also, the carrier density of the oxide semiconductor film that can be measured by Hall effect measurement is 1×10 14 cm - 3 less than, preferably 1×10 12 cm -3 less than, even more preferably below the measurement limit of 1×1 0 11 cm -3 less than. That is, the carrier density of the oxide semiconductor film is extremely close to zero. Also, the bandgap is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. By using an oxide semiconductor film with sufficiently reduced impurity concentration such as moisture or hydrogen and highly purified, the off-current of the transistor can be reduced. eV or more. Here, the analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be mentioned. Oxide semiconductor film

[0015] Here, the analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be mentioned. Oxide Hydrogen concentration in semiconductor and conductive films is measured using SIMS. In principle, SIMS: It is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. It is known that the hydrogen concentration distribution in the film in the thickness direction is analyzed by SIMS. When analyzing the film, the values should be almost constant without extreme fluctuations within the range of the target film. The average value in the region where the value is obtained is adopted as the hydrogen concentration. When the thickness of the film is small, the hydrogen concentration in the adjacent film affects the film thickness, and a nearly constant value is obtained. In this case, the hydrogen concentration in the region where the film exists may not be found. The maximum or minimum value of the hydrogen concentration in the film is used. In the region, there are no mountain-shaped peaks having maximum values and no valley-shaped peaks having minimum values. If not, the value at the inflection point is used as the hydrogen concentration.

[0016] Note that moisture or hydrogen as an impurity is contained in the oxide semiconductor film formed by sputtering or the like. It has been found that water and hydrogen are contained in large amounts. Since water and hydrogen easily form donor levels, Therefore, the oxide semiconductor itself is treated as an impurity. In order to reduce impurities such as moisture or hydrogen in the conductive film, the oxide semiconductor film is Oxygen, oxygen, ultra-dry air (water content is 20 ppm or less, preferably 1 ppm or less, The gas is heated under an atmosphere of air (less than 10 ppb) or rare gas (argon, helium, etc.). Heat treatment is performed at 500°C to 850°C (or the strain point of the glass substrate). It is desirable to carry out the treatment at a temperature in the range of 550°C to 750°C. The heat treatment shall not exceed the heat-resistant temperature of the substrate to be used. Regarding the effect of desorption by heat treatment of moisture or hydrogen, it has been confirmed by TDS (Thermal Desorption Spectroscopy; temperature-programmed desorption gas analysis). Regarding the effect of desorption by heat treatment, it has been confirmed by TDS (Thermal Desorption Spectroscopy; temperature-programmed desorption gas analysis).

[0017] The heat treatment uses heat treatment in a furnace or the rapid thermal annealing method (RTA method). There are a method using a lamp light source and a method of moving a substrate in a heated gas for short-time heat treatment in the RTA method. When using the RTA method, the time required for heat treatment can be made shorter than 0.1 hour. Regarding the RTA method, there are a method using a lamp light source and a method of moving a substrate in a heated gas for short-time heat treatment. When using the RTA method, the time required for heat treatment can be made shorter than 0.1 hour. When using the RTA method, the time required for heat treatment can be made shorter than 0.1 hour.

[0018] Specifically, a transistor using an oxide semiconductor film purified to high purity by the above-described heat treatment as an active layer, for example, even if it is a device with a channel width W of 1×10 μm and a channel length L of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current (drain current when the voltage between the gate electrode and the source electrode is 0 V) 6 is below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 A or less. Thus, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, as a switching element for holding the charge of the holding capacitance, when measuring the off-current of the transistor from the transition of the charge amount per unit time of the holding capacitance using a transistor having a gate insulating film with a thickness of 100 nm and having an oxide semiconductor film purified to high purity, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is 10 zA / μm to 100 zA / μ A. -13 Regarding the above, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, as a switching element for holding the charge of the holding capacitance, when measuring the off-current of the transistor from the transition of the charge amount per unit time of the holding capacitance using a transistor having a gate insulating film with a thickness of 100 nm and having an oxide semiconductor film purified to high purity, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is 10 zA / μm to 100 zA / μ m. Regarding the above, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, as a switching element for holding the charge of the holding capacitance, when measuring the off-current of the transistor from the transition of the charge amount per unit time of the holding capacitance using a transistor having a gate insulating film with a thickness of 100 nm and having an oxide semiconductor film purified to high purity, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is 10 zA / μm to 100 zA / μ m. Regarding the above, it can be seen that the off-current density corresponding to the value obtained by dividing the off-current by the channel width of the transistor is 100 zA / μm or less. Also, as a switching element for holding the charge of the holding capacitance, when measuring the off-current of the transistor from the transition of the charge amount per unit time of the holding capacitance using a transistor having a gate insulating film with a thickness of 100 nm and having an oxide semiconductor film purified to high purity, when the voltage between the source electrode and the drain electrode of the transistor is 3 V, it is 10 zA / μm to 100 zA / μ m. ​​It has been found that a lower off-current of m can be obtained. Therefore, in one aspect of the present invention In the memory device according to the present invention, the off-current density of the transistor using the highly purified oxide semiconductor film as the active layer can be made 100 zA / μm or less, preferably 10 zA / μm or less, and more preferably 1 zA / μm or less. Therefore, the transistor using the highly purified oxide semiconductor film as the active layer has a significantly lower off-current when the voltage between the gate electrode and the source electrode is 0 or less than that of the transistor using crystalline silicon.

[0019] In addition, the transistor using the highly purified oxide semiconductor has almost no temperature dependence of the off-current. This is because impurities that act as electron donors (donors) in the oxide semiconductor are removed and the oxide semiconductor is highly purified, so that the conductivity type approaches the intrinsic type as much as possible, and the Fermi level is located at the center of the forbidden band. Also, this is because the energy gap of the oxide semiconductor is 3 eV or more and the thermally excited carriers are extremely few. Also the fact that the source electrode and the drain electrode are in a degenerate state is also a factor contributing to the absence of temperature dependence. The operation of the transistor is mostly due to the carriers injected from the degenerate source electrode into the oxide semiconductor and since there is no temperature dependence in the carrier density, it can be explained that there is no temperature dependence in the off-current.

[0020] Note that the oxide semiconductor is a quaternary metal oxide such as In-Sn-Ga-Zn-O-based oxide semiconductor or a ternary metal oxide such as In-Ga-Zn-O-based oxide semiconductor, In-Sn-Z n-O-based oxide semiconductor, In-Al-Zn-O-based oxide semiconductor, Sn-Ga-Zn-O-based ​​​​​Oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors, and binary metal oxides such as In-Zn-O based oxide semiconductors, Sn-Zn-O based oxide semiconductors, Al-Zn-O based oxide semiconductors, Zn-Mg-O based oxide semiconductors, Sn-Mg-O based oxide semiconductors, In-Mg-O based oxide semiconductors, In-Ga-O based oxide semiconductors, and In-O based oxide semiconductors, Sn-O based oxide semiconductors, Zn-O based oxide semiconductors, etc. can be used. In this specification, for example, an In-Sn-Ga-Zn-O based oxide semiconductor means a metal oxide containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn), and its stoichiometric composition ratio is not particularly limited. Further, the above oxide semiconductors may contain silicon. Alternatively, the oxide semiconductor can be represented by the chemical formula InMO3(ZnO) (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co.

Advantages of the Invention

[0021] By using the transistor with low off-current as a switching element for holding the charge stored in the memory element, leakage of charge from the memory element can be prevented. Therefore, a memory device capable of retaining data for a long period of time and a semiconductor device using the memory device can be provided. m (m>0). Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. By using the transistor with low off-current as a switching element for holding the charge stored in the memory element, leakage of charge from the memory element can be prevented. Therefore, a memory device capable of retaining data for a long period of time and a semiconductor device using the memory device can be provided. Also, the voltage required for writing and reading data to the memory element is almost determined by the operating voltage of the transistor that functions as a switching element. Therefore, compared with conventional flash memories,

Advantages of the Invention

[0022] By using the transistor with low off-current as a switching element for holding the charge stored in the memory element, leakage of charge from the memory element can be prevented. Therefore, a memory device capable of retaining data for a long period of time and a semiconductor device using the memory device can be provided. Also, the voltage required for writing and reading data to the memory element is almost determined by the operating voltage of the transistor that functions as a switching element. Therefore, compared with conventional flash memories, By using the transistor with low off-current as a switching element for holding the charge stored in the memory element, leakage of charge from the memory element can be prevented. Therefore, a memory device capable of retaining data for a long period of time and a semiconductor device using the memory device can be provided. Also, the voltage required for writing and reading data to the memory element is almost determined by the operating voltage of the transistor that functions as a switching element. Therefore, compared with conventional flash memories,

[0023] Also, the voltage required for writing and reading data to the memory element is almost determined by the operating voltage of the transistor that functions as a switching element. Therefore, compared with conventional flash memories, the voltage required for writing and reading data to the memory element is almost determined by the operating voltage of the transistor that functions as a switching element. Therefore, compared with conventional flash memories, A memory device capable of significantly reducing the operating voltage and suppressing power consumption, and a semiconductor device using the memory device can be provided.

[0024] In addition, deterioration of the gate insulating film due to tunneling current can be suppressed compared to conventional flash, so a memory device capable of increasing the number of data rewrite times, and a semiconductor device using the memory device can be provided.

Brief Description of the Drawings

[0025]

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Mode for Carrying Out the Invention

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and its form and details can be variously changed without departing from the spirit and scope of the present invention, which is easily understood by those skilled in the art. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0027] Note that all semiconductor devices that can use a memory device, such as integrated circuits such as microprocessors and image processing circuits, RF tags, memory media, and semiconductor display devices, are included in the scope of the present invention. In addition, semiconductor display devices include liquid crystal display devices, light-emitting devices having a light-emitting element such as an organic light-emitting element (OLED) provided in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission Display), etc., semiconductor and so on. A semiconductor display device having a circuit element using a body film in a pixel portion or a driving circuit is within the scope thereof. It is included in.

[0028] (Embodiment 1) FIG. 1(A) shows an example of a circuit diagram of a memory cell corresponding to the minimum unit of the memory device of the present invention. The memory cell 100 shown in FIG. 1(A) includes a transistor 101 that functions as a memory element and a transistor 102 that functions as a switching element and can control the supply of potential to the second gate electrode of the transistor 101. Further, the memory cell 100 may be provided with a capacitor element 103 for holding the potential of the second gate electrode of the transistor 101. It may be provided.

[0029] Note that the memory cell 100 may further include other circuit elements such as a diode, a resistance element, and an inductor, if necessary.

[0030] The transistor 101 that functions as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film. The various operations of the memory device can be controlled by the potentials applied to the first gate electrode, the second gate electrode, the source electrode, and the drain electrode of the transistor 101. second insulating film, and a source electrode and a drain electrode in contact with the semiconductor film. The potentials applied to the first gate electrode, the second gate electrode, the source electrode, and the drain electrode of the transistor 101 can control various operations of the memory device.

[0031] The transistor 102 that functions as a switching element includes a semiconductor material having a wider bandgap than silicon and a lower intrinsic carrier density than silicon in a channel formation region. is. By using such a semiconductor material in the channel formation region of the transistor 102, the off-current can be sufficiently reduced.

[0032] As an example of a semiconductor material having a wider bandgap and a lower intrinsic carrier density than a silicon semiconductor, compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), oxide semiconductors such as metal oxides such as zinc oxide (ZnO), etc. can be applied. Among these, the oxide semiconductor can be manufactured by a sputtering method or a wet method (such as a printing method), and has the advantage of excellent mass productivity. Also, the process temperature of silicon carbide is about 1500 °C, and the process temperature of gallium nitride is about 1100 °C, but the film formation temperature of the oxide semiconductor is as low as 300 to 500 °C (below the glass transition temperature, at most about 700 °C), and it is possible to form a film on an inexpensive and easily available glass substrate. Also, on an integrated circuit using a semiconductor material that does not have resistance to heat treatment at a high temperature of 1500 °C to 2000 °C, it is also possible to stack semiconductor elements made of an oxide semiconductor. Also, it is possible to cope with an increase in the size of the substrate. Therefore, among the above-mentioned wide-gap semiconductors, the oxide semiconductor in particular has the merit of high mass productivity. Also, even when trying to obtain a crystalline oxide semiconductor in order to improve the performance of the transistor (for example, the field-effect mobility), a crystalline oxide semiconductor can be easily obtained by heat treatment at 450 °C to 800 °C. In the following description, the case of using an oxide semiconductor having the above advantages as the semiconductor film of the second transistor 102 is taken as an example.

[0033]

[0034] ​​​Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. When the memory cell 100 has a plurality of transistors that function as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in a combination of series and parallel. Note that the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural. Note that in FIG. 1(A), the memory cell 100 is shown with only one transistor 102 that functions as a switching element, but the present invention is not limited to this configuration. In one aspect of the present invention, at least one transistor that functions as a switching element may be provided for each memory cell, and the number of the above transistors may be plural.

[0035] Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor. Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor. Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor. Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor. Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor. Note that the state where transistors are connected in series means that only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. Also, the state where transistors are connected in parallel means that the source electrode of the first transistor is connected to the source electrode of the second transistor, and the drain electrode of the first transistor is connected to the drain electrode of the second transistor.

[0036] Also, unlike the transistor 101 that functions as a memory element, the transistor 102 that functions as a switching element may have a gate electrode that exists only on one side of the active layer. However, the present invention is not limited to this configuration, and the transistor that functions as a switching element may also have a pair of gate electrodes that sandwich the active layer, similar to the transistor that functions as a memory element. Also, unlike the transistor 101 that functions as a memory element, the transistor 102 that functions as a switching element may have a gate electrode that exists only on one side of the active layer. However, the present invention is not limited to this configuration, and the transistor that functions as a switching element may also have a pair of gate electrodes that sandwich the active layer, similar to the transistor that functions as a memory element. Also, unlike the transistor 101 that functions as a memory element, the transistor 102 that functions as a switching element may have a gate electrode that exists only on one side of the active layer. However, the present invention is not limited to this configuration, and the transistor that functions as a switching element may also have a pair of gate electrodes that sandwich the active layer, similar to the transistor that functions as a memory element. Also, unlike the transistor 101 that functions as a memory element, the transistor 102 that functions as a switching element may have a gate electrode that exists only on one side of the active layer. However, the present invention is not limited to this configuration, and the transistor that functions as a switching element may also have a pair of gate electrodes that sandwich the active layer, similar to the transistor that functions as a memory element. Also, unlike the transistor 101 that functions as a memory element, the transistor 102 that functions as a switching element may have a gate electrode that exists only on one side of the active layer. However, the present invention is not limited to this configuration, and the transistor that functions as a switching element may also have a pair of gate electrodes that sandwich the active layer, similar to the transistor that functions as a memory element.

[0037] Also, in one aspect of the present invention, at least the transistor 102 that functions as a switching element may have the above-described wide-gap semiconductor material in the active layer. Therefore, an oxide semiconductor film may be used for the active layer of the transistor 101 that functions as a memory element. Alternatively, a semiconductor such as amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium other than the oxide semiconductor may be used for the active layer of the transistor 101 that functions as a memory element. However, by using an oxide semiconductor film for the active layers of all the transistors in the memory cell 100, the process can be simplified.

[0038] Next, the connection relationships of the transistor 101, the transistor 102, and the capacitor element 103 in the memory cell 100 shown in FIG. 1(A) will be described.

[0039] The gate electrode of the transistor 102 is connected to the write word line WL. And either one of the source electrode and the drain electrode of the transistor 102 is connected to the input data line Din, and the other is connected to the second gate electrode of the transistor 101. The first gate electrode of the transistor 101 is connected to the read word line RL. And either one of the source electrode and the drain electrode of the transistor 101 is connected to the output data line Dout, and the other is connected to a power supply line to which a fixed potential such as ground is applied.

[0040] Also, one of the pair of electrodes of the capacitor element 103 is connected to the second gate electrode of the transistor 101, and the other is connected to a power supply line to which a fixed potential such as ground is applied. ​​​​​​​​​

[0041] In this specification, "connection" means electrical connection, corresponding to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the "connected state" does not necessarily refer to a directly continuous state, but also includes an indirectly connected state through circuit elements such as wiring, resistors, diodes, and transistors, as long as current, voltage, or potential can be supplied or transmitted. Moreover, even if components that are independent on a circuit diagram are connected, in reality, for example, when a part of the wiring also functions as an electrode, there may be a case where a single conductive film has the functions of multiple components. In this specification, "connection" includes such a case where a single conductive film has the functions of multiple components within its scope. In addition, the source electrode and drain electrode of a transistor change their names depending on the polarity of the transistor and the potential difference applied to each electrode. Generally, in an n-channel type transistor, the electrode to which a lower potential is applied is called the source electrode, and the electrode to which a higher potential is applied is called the drain electrode. Also, in a p-channel type transistor, the electrode to which a lower potential is applied is called the drain electrode, and the electrode to which a higher potential is applied is called the source electrode. In this specification, for convenience, when explaining the connection relationship of a transistor, it is assumed that the source electrode and drain electrode are fixed, but in reality, the names of the source electrode and drain electrode change according to the above potential relationship.

[0042]

[0043]

[0044] ​​​​​​​​​​​​​​Note that in FIG. 1(A), the transistor 102 has a gate electrode only on one side of the active layer. This shows the case where the transistor 102 has a pair of gate electrodes sandwiching the active layer. When the transistor 102 has a pair of gate electrodes sandwiching the active layer, one of the gate electrodes is connected to the write word line WL, and the other gate electrode may be in a floating state electrically insulated, or may be in a state where a potential is given from elsewhere. In the latter case, the same height of potential may be given to the pair of electrodes, or a fixed potential such as ground may be given only to the other gate electrode. By controlling the height of the potential given to the other gate electrode, the threshold voltage of the transistor 102 can be controlled.

[0045] Next, FIG. 1(B) shows an example of a cross-sectional view of the memory cell 100 having the circuit configuration shown in FIG. 1(A). The memory cell shown in FIG. 1(B) has a transistor 101 that functions as a memory element and a transistor 102 that functions as a switching element, formed on a substrate 110 having an insulating surface. Specifically, the transistor 101 has, on a substrate 110 having an insulating surface, a first gate electrode 121, an insulating film 112 on the first gate electrode 121, and an oxide semiconductor film 123 that functions as an active layer and overlaps the first gate electrode 121 with the insulating film 112 interposed therebetween, a source electrode 124 and a drain electrode 125 on the oxide semiconductor film 123, an insulating film 116 on the oxide semiconductor film 123, the source electrode 124, and the drain electrode 125, and a second gate electrode 126 that overlaps the oxide semiconductor film 123 on the insulating film 116. Also, an insulating film 117 is formed on the second

[0046] gate electrode 126, and the transistor 101 is an insulating film 117. 117 may be included as a component.

[0047] Further, the transistor 102 includes a gate electrode 111, an insulating film 112 on the gate electrode 111, and an oxide semiconductor film 113 that functions as an active layer and overlaps the gate electrode 111 with the insulating film 112 interposed therebetween, and a source electrode 114 and a drain electrode 115 on the oxide semiconductor film 113. An insulating film 116 is formed on the oxide semiconductor film 113, the source electrode 114, and the drain electrode 115, and the transistor 102 may include the insulating film 116 as a component.

[0048] Further, the capacitor element 103 is formed in a region where the source electrode 124 of the transistor 101 and the second gate electrode 126 overlap with the insulating film 116 interposed therebetween.

[0049] Next, with reference to FIG. 2, the operation of the transistor functioning as a memory element will be described by taking the case where the transistor 101 is an n-channel type and handles binary data as an example. Note that FIG. 2(A) shows a circuit diagram of the transistor 101, and the potentials of the respective electrodes of the transistor 101 are denoted with the potential of the first gate electrode being Vcg, the potential of the second gate electrode being Vbg, the potential of the source electrode being Vs, and the potential of the drain electrode being Vd.

[0050] First, the operation of the transistor 101 during data writing will be described. During writing, a voltage equal to or lower than the threshold voltage Vth0 is applied between the first gate electrode and the source electrode of the transistor 101. Note that the threshold voltage Vth0 is the second ​​​​​​​​​​​​Transistor 10 when the potential Vbg of the gate electrode is equal to the potential Vgnd of the ground corresponds to the threshold voltage of 1. Specifically, the relationship between the potential of the first gate electrode and the source electrode during writing is Vcg - Vs ≤ Vth0. Therefore, transistor 101 is off during writing and the drain electrode is in a high-impedance state.

[0051] Then, during data writing, the potential Vbg of the second gate electrode is controlled in height according to the value of the data to be written. When handling binary data, the second gate electrode is either given a high potential Vdd or a low potential Vss. The relationship between each potential is represented by Vdd > Vss ≥ Vgnd. For example, when the potential Vbg of the second gate electrode is set to the low potential Vss = Vgnd, the threshold voltage of transistor 101 remains Vth0 . On the other hand, when the potential Vbg of the second gate electrode is set to the high potential Vdd, the threshold voltage of the transistor shifts to the negative side and becomes Vth1.

[0052] In this embodiment, the case where the low potential Vss = Vgnd during writing has been described as an example , but the low potential Vss does not necessarily have to be equal to the potential Vgnd of the ground . For example, Vdd > Vss > Vgnd may be used. However, in this case, the shift amount of the threshold voltage should be smaller than the shift amount of the threshold voltage when the potential Vbg of the second gate electrode is set to the high potential Vdd .

[0053] Next, the operation of transistor 101 during data holding will be described. During holding , transistor 102 functioning as a switching element is off. As described above ​Since the sea urchin transistor 102 has an extremely low off-current, the potential Vbg of the second gate electrode holds the height set during writing.

[0054] Next, the operation of the transistor 101 during data reading will be described. During reading, a voltage higher than the threshold voltage Vth1 and lower than Vth0 is applied between the first gate electrode and the source electrode of the transistor 101.

[0055] And when the threshold voltage of the transistor 101 was set to Vth1 during the immediately preceding data writing, since the voltage between the first gate electrode and the source electrode becomes higher than the threshold voltage Vth1, the transistor 101 turns on, and the resistance value between the source electrode and the drain electrode decreases. Therefore, the potential Vs of the source electrode is applied to the drain electrode. On the other hand, when the threshold voltage of the transistor 101 was set to Vth0 during the immediately preceding data writing, even if the voltage between the first gate electrode and the source electrode becomes higher than Vth1, if it is lower than the threshold voltage Vth0, the transistor 101 remains off. Therefore, the resistance value between the source electrode and the drain electrode is high, and the potential Vd of the drain electrode remains in a high-impedance state.

[0056] Therefore, the potential Vd of the drain electrode is linked to the height of the potential applied to the second gate electrode during the immediately preceding data writing. Fig. 2(B) shows the relationship between the potential Vcg of the first gate electrode and the drain current Id of the transistor 101 during reading. Line 130 shows the relationship between the potential Vcg and the drain when the threshold voltage is set to Vth1. shows the relationship of the current Id, and line 131 is when the threshold voltage is set to Vth0 , showing the relationship between the potential Vcg and the drain current Id. As shown in Fig. 2(B), when the voltage between the first gate electrode and the source electrode is set to a potential Vread that is higher than the threshold voltage Vth1 and lower than the threshold voltage Vth0 , from lines 130 and 131, the drain current Id1 obtained when the threshold voltage is Vth1 is higher than the drain current Id0 obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current Id or the potential Vd of the drain electrode , the value of the written data can be grasped. Note that in this embodiment, the case where the voltage between the first gate electrode and the source electrode is higher than the threshold voltage Vth1 and lower than the threshold voltage Vth0 during reading has been described, but

[0057] the present invention is not limited to this configuration. The voltage between the first gate electrode and the source electrode during reading does not necessarily have to be equal to or lower than the threshold voltage Vth0. For example, when writing data immediately before, if the threshold voltage of transistor 101 is set to Vth1 , during reading, if the voltage between the first gate electrode and the source electrode is higher than the threshold voltage Vth0 , transistor 101 turns on, and the resistance value between the source electrode and the drain electrode decreases. Let the resistance value between the source electrode and the drain electrode at this time be Rds0. On the other hand, when writing data immediately before, if the threshold voltage of transistor 101 is set to Vth0 , during reading, if the voltage between the first gate electrode and the source electrode is higher than the threshold voltage Vth0 , transistor 101 turns on, and the resistance value between the source electrode and the drain electrode decreases. Let the resistance value between the source electrode and the drain electrode at this time be Rds0. On the other hand, when writing data immediately before, if the threshold voltage of transistor 101 is set to Vth0 , during reading, if the voltage between the first gate electrode and the source electrode is higher than the threshold voltage Vth0 , transistor 101 turns on, and the resistance value between the source electrode and the drain electrode decreases. Let the resistance value between the source electrode and the drain electrode at this time be Rds0. On the other hand, when writing data immediately before, if the threshold voltage of transistor 101 is set to Vth0 , during reading, if the voltage between the first gate electrode and the source electrode is higher than the threshold voltage Vth0 , transistor 101 turns on, and the resistance value between the source electrode and the drain electrode decreases. Let the resistance value between the source electrode and the drain electrode at this time be Rds0. On the other hand, when writing data immediately before, if the threshold voltage of transistor 101 is set to Vth0 The resistance value between the electrodes decreases. At this time, the resistance value between the source electrode and the drain electrode is defined as Rds1 And at least when the threshold voltage is set to Vth1, by operating the transistor 101 in the saturation region, the transistor 101 during reading can have a difference such that the resistance value between the source electrode and the drain electrode is Rds0 < Rds1 regardless of whether the threshold voltage is set to either Vth1 or Vth0. Specifically when the voltage between the first gate electrode and the source electrode is Vgs and the voltage between the source electrode and the drain electrode is Vds, in the range where |Vds| > |Vgs - Vth0| is satisfied, the transistor 101 may be operated. By making the resistance value between the source electrode and the drain electrode have a difference such that Rds0 < Rds1, even when the voltage between the first gate electrode and the source electrode during reading is higher than the threshold voltage Vth0, the potential Vd of the drain electrode can be made to be linked to the height of the potential applied to the second gate electrode during the writing of the immediately preceding data. For example, as shown in Fig. 2(B), when the voltage between the first gate electrode and the source electrode is set to a potential Vread' higher than the threshold voltage Vth0, from line 130 and line 131, the drain current Id1' obtained when the threshold voltage is Vth1 becomes higher than the drain current Id0' obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current Id or the potential Vd of the drain electrode, the value of the written data can be grasped. Next, the operation of the transistor 101 during data erasure will be described. During erasure the transistor 101, similar to during data writing, has the first gate electrode and the source electrode, and the drain current Id1' obtained when the threshold voltage is Vth1 becomes higher than the drain current Id0' obtained when the threshold voltage is Vth0. Therefore, by reading the value of the drain current Id or the potential Vd of the drain electrode, the value of the written data can be grasped. Therefore, by reading the value of the drain current Id or the potential Vd of the drain electrode, the value of the written data can be grasped. can be grasped.

[0058] Next, the operation of the transistor 101 during data erasure will be described. During erasure the transistor 101, similar to during data writing, has the first gate electrode and the source A voltage equal to or lower than the threshold voltage Vth1 is applied between the source electrodes. Specifically, The relationship between the potential of the first gate electrode and the source electrode during erasure is Vcg - Vs ≤ Vth1 Thus, the transistor 101 is off during erasure, and the drain electrode is in a high impedance state. And during data erasure, the potential Vbg of the second gate electrode is set to a fixed potential such as ground, and the threshold voltage of the transistor 101 is V th0.

[0059] Note that in this embodiment, a method for driving a memory device that erases written data has been described However, the present invention is not limited to this configuration. One advantage of the memory device according to an aspect of the present invention is that it does not require an erasure operation unlike a conventional flash memory. Therefore , for example, it is also possible to write another data so as to overwrite the previously written data .

[0060] Note that in the case of a general flash memory, during data writing, the floating gate that accumulates charges is in an insulated state covered with an insulating film. Therefore, in order to accumulate charges on the floating gate using the tunneling effect, it is necessary to apply a voltage as high as about 20 V to the memory element. However, in one aspect of the present invention, data writing and reading can be performed by a transistor using a highly purified oxide semiconductor film as the active layer of the transistor. Therefore, the voltage required during the operation of the memory device is about several volts, and the power consumption can be significantly reduced. Note that the transistor used as the memory element of the flash memory and the transistor used as the memory element of the memory device according to one aspect of the present invention are used as Since the transistors are different in structure and driving method, it is difficult to accurately grasp the difference in power consumption during operation from the potentials applied to the respective electrodes of the memory element. However, for example, if we focus only on the power consumption during data writing and compare it, in the memory device according to one aspect of the present invention, when a voltage of 5V is applied between the second gate electrode and the source electrode, sufficient data can be written. On the other hand, in a normal flash memory, in order to write data by accumulating charges on the floating gate, a voltage of at least about 16V is required between the gate electrode and the source electrode. The power consumed in the transistor corresponds to the square of the gate voltage of the transistor divided by the load resistance of the transistor. Therefore, it can be seen that the power consumption of the memory device according to one aspect of the present invention is about 10% of the power consumption of a normal flash memory. Thus, from the comparison of the power consumption during writing, it can be seen that the power consumption during operation can be significantly reduced. Note that in a semiconductor device using a general flash memory, since the voltage (operating voltage) required during the operation of the flash memory is large, usually, a boosting circuit or the like is used to boost the voltage applied to the flash memory. However, in the memory device according to one aspect of the present invention, since the operating voltage of the memory device can be kept small, the power consumption can be reduced. Therefore, the burden on external circuits such as the boosting circuit related to the operation of the memory device in the semiconductor device can be reduced, and accordingly, the function of the external circuit can be extended, etc., to realize the high functionality of the semiconductor device.

[0061] In addition, since the operating voltage of the memory device can be kept small, the range of the operating voltage can be covered. Since the voltage required during the operation of the flash memory is large, usually, a boosting circuit or the like is used to boost the voltage applied to the flash memory. However, in the memory device according to one aspect of the present invention, since the operating voltage of the memory device can be suppressed to be small, the power consumption can be reduced. Therefore, the burden on external circuits such as the boosting circuit related to the operation of the memory device in the semiconductor device can be reduced, and accordingly, the function of the external circuit can be extended, etc., to realize the high functionality of the semiconductor device. That is, the burden on external circuits such as the boosting circuit related to the operation of the memory device in the semiconductor device can be reduced, and the functionality of the external circuit can be enhanced, etc., to realize the high functionality of the semiconductor device. Since redundant circuit design is not required, the integration degree of the integrated circuit used in the semiconductor device can be increased, and the semiconductor device can be made highly functional. Moreover, in this embodiment, the driving method in the case of handling binary digital data has been described.

[0062] In the storage device of the present invention, it is also possible to handle multi-valued data of three or more values. When handling multi-valued data of three or more values, at the time of writing data, the height of the potential Vbg of the second gate electrode can be selected from three or more. Since the value of the threshold voltage is controlled by the potential Vbg of the second gate electrode, according to the above configuration, the height of the threshold voltage can be set to three or more levels according to the height of the potential Vbg of the set second gate electrode. Then, using the difference generated in the drain current due to the difference in the height of the threshold voltage, or the difference generated in the resistance value between the source electrode and the drain electrode due to the difference in the height of the threshold voltage, it is possible to read multi-valued data. As another method, according to each level of the height of the threshold voltage, voltages slightly higher than each level are prepared in advance, the prepared voltages are applied to the first gate electrode, and reading is performed for each level of the height of the threshold voltage. For example, when reading 4-valued data, four voltages (Vread0, Vread1, Vread2, Vread3) slightly higher than each level of the four-level threshold voltage (Vth0, Vth1, Vth2, Vth3) are prepared in advance, and by using the four voltages to perform four readings, 4-valued data can be read. With the above configuration, it is possible to increase the storage capacity of the storage device while suppressing the area.

[0063] With the above configuration, it is possible to increase the storage capacity of the storage device while suppressing the area.

[0063] Since the difference in threshold voltage becomes small, if there is a minute off-current, the potential of the second gate electrode changes, making it difficult to maintain the accuracy of data and tending to further shorten the holding period. However, in one aspect of the present invention, since a transistor with a significantly reduced off-current by using a highly purified oxide semiconductor film is used as a switching element, the effect of preventing off-current is higher than that of a silicon-based transistor. Therefore, it is possible to suppress the shortening of the holding period associated with multi-valuing. Also, in FIG. 1(B), the case where the transistor 102 functioning as a switching element is a bottom gate type having an oxide semiconductor film 113 on the gate electrode 111 is illustrated, but the transistor 102 is not limited to the bottom gate type. The transistor 102 only needs to use an oxide semiconductor film as an active layer. For example, it may be a top gate type having a gate electrode on the oxide semiconductor film. Also, the transistor 102 is not limited to the top contact type in which the source electrode 114 and the drain electrode 115 are formed on the oxide semiconductor film 113, and may be a bottom contact type in which the oxide semiconductor film 113 is formed on the source electrode 114 and the drain electrode 115. Also, the transistor 102 is a channel etch type in which the film thickness of the oxide semiconductor film 113 overlapping the insulating film 116 between the source electrode 114 and the drain electrode 115 is thinner than other portions, but the present invention is not limited to this configuration. In order to prevent damage due to plasma during etching for forming the source electrode 114 and the drain electrode 115 and film reduction due to etching, etc., a channel protection film is provided on the oxide semiconductor film 113 between the source electrode 114 and the drain electrode 115.

[0064] In FIG. 1(B), the case where the transistor 102 functioning as a switching element is a bottom gate type having an oxide semiconductor film 113 on the gate electrode 111 is illustrated, but the transistor 102 is not limited to the bottom gate type. The transistor 102 only needs to use an oxide semiconductor film as an active layer. For example, it may be a top gate type having a gate electrode on the oxide semiconductor film. Also, the transistor 102 is not limited to the top contact type in which the source electrode 114 and the drain electrode 115 are formed on the oxide semiconductor film 113, and may be a bottom contact type in which the oxide semiconductor film 113 is formed on the source electrode 114 and the drain electrode 115. The transistor 102 only needs to use an oxide semiconductor film as an active layer. For example, it may be a top gate type having a gate electrode on the oxide semiconductor film. Also, the transistor 102 is not limited to the top contact type in which the source electrode 114 and the drain electrode 115 are formed on the oxide semiconductor film 113, and may be a bottom contact type in which the oxide semiconductor film 113 is formed on the source electrode 114 and the drain electrode 115. The transistor 102 is not limited to the top contact type in which the source electrode 114 and the drain electrode 115 are formed on the oxide semiconductor film 113, and may be a bottom contact type in which the oxide semiconductor film 113 is formed on the source electrode 114 and the drain electrode 115. Also, the transistor 102 is a channel etch type in which the film thickness of the oxide semiconductor film 113 overlapping the insulating film 116 between the source electrode 114 and the drain electrode 115 is thinner than other portions, but the present invention is not limited to this configuration. The transistor 102 is a channel etch type in which the film thickness of the oxide semiconductor film 113 overlapping the insulating film 116 between the source electrode 114 and the drain electrode 115 is thinner than other portions, but the present invention is not limited to this configuration. In order to prevent damage due to plasma during etching for forming the source electrode 114 and the drain electrode 115 and film reduction due to etching, etc., a channel protection film is provided on the oxide semiconductor film 113 between the source electrode 114 and the drain electrode 115. The transistor 102 is a channel etch type in which the film thickness of the oxide semiconductor film 113 overlapping the insulating film 116 between the source electrode 114 and the drain electrode 115 is thinner than other portions, but the present invention is not limited to this configuration. In order to prevent damage due to plasma during etching for forming the source electrode 114 and the drain electrode 115 and film reduction due to etching, etc., a channel protection film is provided on the oxide semiconductor film 113 between the source electrode 114 and the drain electrode 115. In order to prevent damage due to plasma during etching for forming the source electrode 114 and the drain electrode 115 and film reduction due to etching, etc., a channel protection film is provided on the oxide semiconductor film 113 between the source electrode 114 and the drain electrode 115. In order to prevent damage due to plasma during etching for forming the source electrode 114 and the drain electrode 115 and film reduction due to etching, etc., a channel protection film is provided on the oxide semiconductor film 113 between the source electrode 114 and the drain electrode 115. It may be of the channel protection type.

[0065] FIG. 3(A) shows an example of a cross-sectional view of the memory cell 100 having the circuit configuration shown in FIG. 1(A). is shown. The memory cell shown in FIG. 3(A) includes a channel protection type transistor 101 that functions as a memory element and a channel protection type transistor 10 2 that functions as a switching element, which are formed on a substrate 140 having an insulating surface. Specifically, the transistor 101 includes, on the substrate 140 having an insulating surface, a first gate electrode

[0066] 151, an insulating film 142 on the first gate electrode 151, an oxide semiconductor film 153 that functions as an active layer and overlaps the first gate electrode 151 with the insulating film 142 interposed therebetween, a channel protection film 157 that overlaps the gate electrode 151 on the oxide semiconductor film 153, a source electrode 154 and a drain electrode 155 on the oxide semiconductor film 153, an insulating film 146 on the oxide semiconductor film 153, the channel protection film 157, the source electrode 154 and the drain electrode 155, and a second gate electrode 156 that overlaps the oxide semiconductor film 153 on the insulating film 146. Further, an insulating film 147 is formed on the second gate electrode 156, and the transistor 101 may include the insulating film 147 as a component.

[0067] Also, the transistor 102 includes, on the substrate 140 having an insulating surface, a gate electrode 141, an insulating film 142 on the gate electrode 141, an oxide semiconductor film 143 that functions as an active layer and overlaps the gate electrode 141 with the insulating film 142 interposed therebetween, a channel protection film 148 on the oxide semiconductor film 143, a source electrode 144 and a drain electrode 145 on the oxide semiconductor film 143 ​It has an oxide semiconductor film 143, a channel protection film 148, a source electrode 144, and An insulating film 146 is formed on the drain electrode 145, and the transistor 102 may include the insulating film 146 as a component.

[0068] Also, the capacitor element 103 is formed in a region where the source electrode 154 of the transistor 101 and the second gate electrode 156 overlap with the insulating film 146 interposed therebetween.

[0069] The channel protection film 157 and the channel protection film 148 can be formed by a chemical vapor deposition method such as plasma CVD or thermal CVD, or a sputtering method. Also, for the channel protection film 157 and the channel protection film 148, it is desirable to use an inorganic material containing oxygen (such as silicon oxide, silicon oxynitride, nitrogen silicon oxide, etc.). By using an inorganic material containing oxygen for the channel protection film 15 7 and the channel protection film 148, even if oxygen deficiency occurs due to a heat treatment for reducing moisture or hydrogen in the oxide semiconductor film 153 and the oxide semiconductor film 14 3, oxygen can be supplied to at least the regions of the oxide semiconductor film 153 and the oxide semiconductor film 143 that are in contact with the channel protection film 157 and the channel protection film 148 respectively, and the oxygen deficiency serving as a donor can be reduced to satisfy the stoichiometric composition ratio. Therefore, the channel formation region can be made i-type or substantially i-type, the variation in the electrical characteristics of the transistor due to oxygen deficiency can be reduced, and the improvement of the electrical characteristics can be realized. The channel formation region refers to a region of the semiconductor film that overlaps with the gate electrode with the gate insulating film interposed therebetween. In the case of a transistor used as a memory element, among the semiconductor films,

[0070] Note that the channel formation region corresponds to a region of the semiconductor film that overlaps with the gate electrode with the gate insulating film interposed therebetween. In the case of a transistor used as a memory element, among the semiconductor films, Between the source electrode and the drain electrode, with a gate insulating film interposed therebetween, a first gate electrode corresponds to a region overlapping with the second gate electrode.

[0071] Next, FIG. 3(B) shows an example of a cross-sectional view of the memory cell 100 having the circuit configuration shown in FIG. 1(A). The memory cell shown in FIG. 3(B) includes a bottom contact type transistor 101 that functions as a storage element, and a bottom contact type transistor 102 that functions as a switching element, which are formed on a substrate 160 having an insulating surface.

[0072] Specifically, the transistor 101 includes, on the substrate 160 having an insulating surface, a first gate electrode 171, an insulating film 162 on the first gate electrode 171, a source electrode 1 74 and a drain electrode 175 on the insulating film 162, and an active layer that overlaps with the first gate electrode 171 with the insulating film 162 interposed therebetween and is in contact with the source electrode 174 and the drain electrode 175, an oxide semiconductor film 173 that functions as an active layer, an insulating film 166 on the oxide semiconductor film 173, the source electrode 174, and the drain electrode 175, and a second gate electrode 176 that overlaps with the oxide semiconductor film 173 on the insulating film 166. Also, an insulating film 167 is formed on the second gate electrode 176, and the transistor 101 may include the insulating film 167 as a component.

[0073] Also, the transistor 102 includes, on the substrate 160 having an insulating surface, a gate electrode 161, an insulating film 162 on the gate electrode 161, a source electrode 164 and a drain electrode 165 on the insulating film 162, and overlaps with the gate electrode 161 with the insulating film 162 interposed therebetween, and the source electrode ​​The oxide semiconductor film 163, which functions as an active layer, is in contact with the source electrode 164 and the drain electrode 165. It has the oxide semiconductor film 163, the source electrode 164, and the drain electrode 165. An insulating film 166 is formed on the oxide semiconductor film 163, the source electrode 164, and the drain electrode 165, and the transistor 102 may include the insulating film 166 as a component.

[0074] Also, the capacitor element 103 is formed in a region where the source electrode 174 of the transistor 101 and the second gate electrode 176 overlap with the insulating film 166 interposed therebetween.

[0075] Also, in FIGS. 1(A), 3(A), and 3(B), the case where an oxide semiconductor film is used for the active layer of the transistor 101 functioning as a memory element is illustrated. However, as described above, in the active layer of the transistor 101, a semiconductor such as amorphous, microcrystalline, polycrystalline, or single-crystalline silicon or germanium other than the oxide semiconductor may be used.

[0076] FIG. 4(A) shows a cross-sectional view of the memory cell 100 as an example when a semiconductor film containing silicon is used for the active layer of the transistor 101 functioning as a memory element. The memory cell shown in FIG. 4(A) has a transistor 101 functioning as a memory element and a transistor 102 functioning as a switching element formed on a substrate 200 having an insulating surface.

[0077] Specifically, the transistor 102 has a gate electrode 211, an insulating film 230 on the gate electrode 211, an oxide semiconductor film 213 functioning as an active layer that overlaps with the gate electrode 211 with the insulating film 230 interposed therebetween, and a source electrode on the oxide semiconductor film 213. - It has a source electrode 214 and a drain electrode 215. An oxide semiconductor film 213, source An insulating film 231 is formed on the electrode 214 and the drain electrode 215, and the transistor 102 may include the insulating film 231 as a component.

[0078] Also, the transistor 101 is formed on an insulating film 231 formed on a substrate 200 having an insulating surface On it, a first gate electrode 221, an insulating film 212 on the first gate electrode 221, and an insulating film A semiconductor film 223 that functions as an active layer using silicon and overlaps the first gate electrode 221 with the insulating film 212 interposed therebetween And a source electrode 224 and a drain electrode 225 on the semiconductor film 223 And an insulating film 216 on the semiconductor film 223, the source electrode 224, and the drain electrode 225, and a second gate electrode 226 that overlaps the semiconductor film 223 on the insulating film 216 It has. Also, an insulating film 217 is formed on the second gate electrode 226, and the transistor 101 may include the insulating film 217 as a component.

[0079] Also, the capacitor element 103 is formed in a region where the drain electrode 225 of the transistor 101 and the second gate electrode 226 overlap with the insulating film 216 interposed therebetween.

[0080] Next, FIG. 4(B) shows, as an example, a cross-sectional view of the memory cell 100 when a semiconductor film containing silicon is used for the active layer of the transistor 101 that functions as a memory element. FIG. 4 (B) shows a memory cell including a transistor 101 that functions as a memory element and a transistor 102 that functions as a switching element, which are formed on a substrate 270 having an insulating surface. (B)

[0081] ​​Specifically, the transistor 102 has a gate electrode 244 formed on an insulating film 247 on a substrate 270. The electrode 241, the insulating film 260 on the gate electrode 241, and the gate insulating film 260 sandwiched between the gate An oxide semiconductor film 243 that overlaps with the electrode 241 and functions as an active layer, and an oxide semiconductor film 2 The source electrode 244 or the drain electrode 245 is disposed on the oxide semiconductor film 2. 43, an insulating film 261 is formed on the source electrode 244 and the drain electrode 245; The transistor 102 may include an insulating film 261 as a component.

[0082] The transistor 101 also includes a first gate electrode 251 and a first gate The insulating film 242 is disposed on the first gate electrode 251, and the insulating film 242 is disposed between the first gate electrode 251 and the second gate electrode 251. A semiconductor film 253 that functions as an active layer using silicon is overlapped with the semiconductor film 253. A source electrode 254, a drain electrode 255, and a semiconductor film 253, a source electrode 254 and a drain electrode 255 are formed. The insulating film 246 on the inner electrode 255 overlaps with the semiconductor film 253 on the insulating film 246. The second gate electrode 256 has an insulating layer. A film 247 is formed, and the transistor 101 includes the insulating film 247 as a component. is also good.

[0083] The capacitor 103 is connected to the drain electrode 255 of the transistor 101 and the second gate electrode The electrode 256 is formed in an overlapping region with the insulating film 246 sandwiched therebetween.

[0084] Note that the transistors 101 shown in FIGS. 4A and 4B are both bottom-gate transistors. However, it may be a top gate type or a bottom contact type. That's fine. And although the transistor 101 is of the channel-etch type, it may be of the channel-protection type. Also, the transistor 102 shown in FIGS. 4(A) and 4(B) is exemplified as being of the bottom-gate type in both cases, but it may be of the top-gate type or the bottom contact type. And the transistor 102 is of the channel-etch type but may be of the channel-protection type.

[0085] (Embodiment 2) In this embodiment, a configuration of a storage device having a plurality of memory cells and an example of its driving method will be described.

[0086] FIG. 5 shows, as an example, a circuit diagram of a cell array of a NOR-type storage device in which a plurality of memory cells 300 are connected in a matrix. Regarding the configuration of each memory cell 300 included in the storage device shown in FIG. 5, the content described for the configuration of the memory cell 100 in Embodiment 1 can be referred to. Specifically, the memory cell 300 includes a transistor 301 that functions as a storage element and a transistor 302 that functions as a switching element capable of controlling the supply of potential to the second gate electrode of the transistor 301. Also, the memory cell 300 may be provided with a capacitor element 303 for holding the potential of the second gate electrode of the transistor 301. The memory cell 300 may further include other circuit elements such as a diode, a resistor element, an inductor, etc., as necessary.

[0087] In the cell array shown in FIG. 5, a plurality of input data lines Din, a plurality of output data lines Dou

[0088] and Various wirings such as a plurality of write word lines WL and a plurality of read word lines RL are provided. A signal or a power supply potential from a drive circuit of the cell array is supplied to each memory cell 300 via these wirings. Therefore, the number of the wirings can be determined by the number and arrangement of the memory cells 300. Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example. And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1. And for the transistor 301, either one of the source electrode and the drain electrode is connected to the output data line Dout1, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied.

[0089] Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example. And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1. And for the transistor 301, either one of the source electrode and the drain electrode is connected to the output data line Dout1, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied. Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example.

[0090] And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1. And for the transistor 301, either one of the source electrode and the drain electrode is connected to the output data line Dout1, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied. Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example. And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1. And for the transistor 301, either one of the source electrode and the drain electrode is connected to the output data line Dout1, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied. Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example. And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1. And for the transistor 301, either one of the source electrode and the drain electrode is connected to the output data line Dout1, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied. Specifically, in the case of the cell array shown in FIG. 5, memory cells of 3 rows × 3 columns are connected in a matrix, and at least input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, and read word lines RL1 to RL3 are arranged in the cell array as an example. And regarding the connection structure between the above wirings and the circuit elements in the memory cell 300, one of the memory cells 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1 will be taken as an example and described. The gate electrode of the transistor 302 is connected to the write word line WL1. And for the transistor 302, either one of the source electrode and the drain electrode is connected to the input data line Din1, and the other is connected to the second gate electrode of the transistor 301.

[0091] Also, one of the pair of electrodes of the capacitive element 303 is connected to the second gate electrode of the transistor 301, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied. is connected.

[0092] Also, FIG. 6 shows, as an example, a circuit diagram of a cell array of a NAND-type storage device in which a plurality of memory cells 300 are connected in series. The configuration of each memory cell included in the storage device shown in FIG. 6 is the same as that in FIG. 5, and in the first embodiment, the description of the configuration of the memory cell 100 can be referred to. For the cell array shown in FIG. 6, a case where cell arrays in which three memory cells are connected in series are arranged in three columns

[0093] is illustrated. Specifically, a cell array having 3×3 memory cells, input data lines Din1 to Din3, output data lines Dout1 to Dout3, write word lines WL1 to WL3, read word lines RL1 to RL3, selection signal lines SEL1 to SEL2, and the power supply line 304 are arranged in the cell array. Signals or power supply potentials from the drive circuit of the cell array are supplied to each memory cell via these wirings. Therefore, the number of the above wirings can be determined by the number of memory cells 300.

[0094] Next, the connection structure between the above wirings and the circuit elements in the memory cell 300 will be described. For example, considering the memory cell 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1 , and the read word line RL1, the gate electrode of the transistor 302 is connected to the write word line WL1. And the transistor is connected to the read word line RL1, and the source electrode of the transistor 302 is connected to the output data line Dout1. Of the source electrode and the drain electrode of the transistor 302, one is connected to the input data line D in1, and the other is connected to the second gate electrode of the transistor 301. Also, the first gate electrode of the transistor 301 is connected to the read word line RL1 and. And the transistor 301 is between the output data line Dout1 and the power supply line 304 to which a fixed potential such as ground is applied, in series between adjacent memory cells connected.

[0095] Also, one of the pair of electrodes of the capacitor element 303 is connected to the second gate electrode of the transistor 301, and the other is connected to the power supply line 304 to which a fixed potential such as ground is applied and.

[0096] Next, taking the cell array shown in FIG. 6 as an example, the operation of the memory device according to one aspect of the present invention will be described using FIG. 21. FIG. 21 is a timing chart showing the time change of the potential of the signal input to each wiring, and the transistors 301 and 302 are n-channel type, and the case of handling binary data is illustrated.

[0097] First, the operation of the memory device during data writing will be described. At the time of writing , when a signal having a pulse is input to the write word line WL1, the potential of the pulse , specifically, a high-level potential, is applied to the gate electrode of the transistor 302. And the transistor 302 whose gate electrode is connected to the write word line WL1 becomes fully on. On the other hand, a low-level potential is input to the read word line RL1 , and a low-level potential is applied to the first gate electrode of the transistor 301. And​​ The transistor 301, to which the first gate electrode is connected to the read word line RL1, all turn off.

[0098] Then, signals containing data as information are sequentially input to the input data lines Din1 to Din3. In FIG. 21, signals having a high-level potential are input to the input data line Din1 and the input data line Din3, and a signal having a low-level potential is input to the input data line Din2, which is illustrated as an example. The potential levels of the signals input to the input data lines Din1 to Din3 naturally vary depending on the content of the data.

[0099] The potentials input to the input data lines Din1 to Din3 are applied to the second gate electrode of the transistor 301 via the on transistor 302. Then, according to the potential of the second gate electrode, the shift amount of the threshold voltage of the transistor 301 is determined. Specifically, since signals having a high-level potential are input to the input data line Din1 and the input data line Din3, in the memory cell 300 connected to the input data line Din1 and the memory cell 300 connected to the input data line Din3, the potential of the second gate electrode of the transistor 301 is at a high level. That is, in the memory cell 300, the transistor 301 functioning as a memory element operates according to line 130 in FIG. 2. On the other hand, since a signal having a low-level potential is input to the input data line Din2, in the memory cell 300 connected to the input data line Din2, the potential of the second gate electrode of the transistor 301 is at a low level. That is, in the memory cell 300, the transistor 301 functioning as a memory element operates according to line 130 in FIG. 2. , in the memory cell 300, the transistor 301 that functions as a memory element operates according to line 131 in FIG. 2 and operates according to line 131 in FIG. 2

[0100] When the input of a signal with a pulse to the write word line WL1 ends, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, a signal with a pulse is input to the write word line WL2 and the write word line WL3 in sequence, and in the memory cell having the write word line WL2 and the memory cell having the write word line WL3, the above-described operations are repeated in the same manner. When the input of a signal with a pulse to the write word line WL1 ends, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, a signal with a pulse is input to the write word line WL2 and the write word line WL3 in sequence, and in the memory cell having the write word line WL2 and the memory cell having the write word line WL3, the above-described operations are repeated in the same manner. Then, a signal with a pulse is input to the write word line WL2 and the write word line WL3 in sequence, and in the memory cell having the write word line WL2 and the memory cell having the write word line WL3, the above-described operations are repeated in the same manner. 3 are repeated in the same manner.

[0101] Next, the operation of the memory device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode holds the level set during writing. Also, all the read word lines RL1 to RL3 are given a low-level potential. Next, the operation of the memory device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential. Next, the operation of the memory device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode holds the level set during writing. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode holds the level set during writing. Also, all the read word lines RL1 to RL3 are given a low-level potential. Also, all the read word lines RL1 to RL3 are given a low-level potential.

[0102] In the timing chart of FIG. 21, a holding period is provided to explain the operation of holding data. However, in the actual operation of the memory, the holding period does not have to be provided. In the timing chart of FIG. 21, a holding period is provided to explain the operation of holding data. However, in the actual operation of the memory, the holding period does not have to be provided.

[0103] Next, the operation of the memory device during data reading will be described. During reading, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential, in the same manner as during holding. Next, the operation of the memory device during data reading will be described. During reading, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential, in the same manner as during holding. Next, the operation of the memory device during data reading will be described. During reading, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 is turned off, specifically, a low-level potential, in the same manner as during holding.

[0104] In a NAND-type memory device, a fixed potential such as an output data line and ground is provided Between the power supply lines, adjacent memory cells are connected in series. For a certain memory When it is desired to read the data of a cell, by controlling the memory cell connected to the same output data line as the said memory cell, Whether the output data line to which the said memory cell is connected conducts with a power supply line to which a fixed potential such as ground is provided, The stored binary value can be distinguished.

[0105] Specifically, focusing on the memory cell 300 connected to the input data line Din1, the output data line Dout1, the write word line WL1, and the read word line RL1, consider the case of reading the high-level data stored in the said memory cell 300. When selecting the output data line Dout1 to which the said memory cell 300 is connected, Set SEL1 And SEL2 to a high-level potential, and turn on the transistor 320 connected to SEL1 and The transistor 321 connected to SEL2. Then, the read word line RL1 connected to the first gate electrode of the transistor 301 in the said memory cell 300 is set to Low level. Further, apply a high-level potential to the read word lines RL2 to RL3, And turn on each transistor 301 connected to the read word lines RL2 to RL3. The transistor 301 of the said memory cell 300 has high-level data written to the second gate electrode. That is, according to the operation of the transistor 301 that functions as a memory element shown in FIG. 2, the threshold voltage is shifted to the negative side and becomes Vth1. Therefore, Thus, transistor 301 is on. Therefore, all the transistors connected to the output data line Dout1 are on, and the output data line Dout1 is connected to the power supply line supplied with ground and becomes approximately the same potential as ground. Next, focusing on the memory cell 300 connected to the input data line Din2, the output data line Dout2, the write word line WL 1, and the read word line RL1, consider the case of reading the low-level data stored in the memory cell 300. To select the output data line D

[0106] out2, set SEL1 and SEL2 to a high-level potential, and turn on the transistor 320 connected to SEL1 and the transistor 321 connected to SEL2. Then, set the read word line RL1 connected to the first gate electrode of the transistor 301 in the memory cell 300 to a low level. Furthermore, apply a high-level potential to the read word lines RL 2 to RL3 to turn on each transistor 301 connected to the read word lines RL2 to RL3. The transistor 301 of the memory cell 300 has low-level data written to the second gate electrode. That is, according to the operation of the transistor 301 that functions as a memory element shown in FIG. 2, the threshold voltage does not shift and is V th0. Therefore, the transistor 301 is off. Therefore, the output data line Dout2 is not connected to the power supply line supplied with ground and becomes a high impedance state.

[0107] Note that a read circuit is connected to the end of each output data line Dout, and the output signal of the read circuit becomes the actual output of the memory.

[0108] In this embodiment, when reading data, the output data line is selected by using two selection signal lines, SEL1 and SEL2, and transistors each having a gate electrode connected to each signal line as an example. The selection of the output data line when reading data is such that conduction and non-conduction between the output data line and the read circuit connected thereto can be selected. Therefore, at least one selection signal line and a transistor connected to the selection signal line are sufficient.

[0109] In this embodiment, the driving method of sequentially performing the operations of writing, holding, and reading in a plurality of memory cells has been described, but the present invention is not limited to this configuration. The above operations may be performed only in the memory cells of the designated address .

[0110] Also, in the case of the cell array shown in FIG. 6, an example is shown where four wirings, an input data line Din, an output data line Dout, a write word line WL, and a read word line RL, are connected to each memory cell . However, in the memory device of the present invention, the number of wirings connected to each memory cell is not limited to this. Signals for controlling the switching of transistor 301, signals for controlling the switching of transistor 302, and signals for supplying a potential to the second gate electrode of transistor 301 can be supplied to memory cell 300 . In addition, the number and connection structure of the wirings may be appropriately determined so that the drain current of transistor 301 or the resistance value between the source electrode and the drain electrode can send the potential included as information to the drive circuit .

[0111] In the timing chart shown in FIG. 21, the hatched portions of the output data lines Dout1, Dou t2 and Dout3 represent a state where the data is uncertain. Also, the rising edges of each signal are vertically raised, and the falling edges of each signal are vertically lowered. However, since each actual signal is affected by factors such as the load of the signal line and noise, it is easily understood by those skilled in the art that the waveforms of each signal are dulled.

[0112] Next, taking the cell array shown in FIG. 5 as an example, the operation of the memory device according to one aspect of the present invention will be described with reference to FIG. 7. FIG. 7 is a timing chart showing the time change of the potential of the signals input to each wiring, and illustrates a case where the transistors 301 and 302 are n-channel type and handle binary data.

[0113] First, the operation of the memory device during data writing will be described. At the time of writing, when a signal having a pulse is input to the write word line WL1, the potential of the pulse, specifically the high-level potential, is applied to the gate electrode, so that all the transistors 302 whose gate electrodes are connected to the write word line WL1 are turned on. On the other hand, a signal having a potential lower than Vth1 in FIG. 2 showing the operation of the transistor functioning as a memory element is input to the read word line RL1, and all the transistors 301 whose first gate electrodes are connected to the read word line RL1 maintain off state.

[0114] Then, signals containing data as information are sequentially input to the input data lines Din1 to Din3. In FIG. 7, high-level potentials are applied to all of the input data lines Although it illustrates the case where a signal is being input, the levels of the signals input to the input data lines Din1 to Din3 naturally differ depending on the content of the data. Also, when dealing with binary data, the potential of the signals input to the input data lines Din1 to Din3 only needs to be binary at potentials corresponding to the power supply voltage (for example, Vdd and Vss). However, when dealing with multi-valued data of three or more values, the number of potential levels can be determined according to the radix used for the data being handled. When dealing with binary data, the potential of the signals input to the input data lines Din1 to Din3 only needs to be binary at potentials corresponding to the power supply voltage (for example, Vdd and Vss). However, when dealing with multi-valued data of three or more values, the number of potential levels can be determined according to the radix used for the data being handled. naturally differ depending on the content of the data. Also, when dealing with binary data, the potential of the signals input to the input data lines Din1 to Din3 only needs to be binary at potentials corresponding to the power supply voltage (for example, Vdd and Vss). However, when dealing with multi-valued data of three or more values, the number of potential levels can be determined according to the radix used for the data being handled. naturally differ depending on the content of the data. Also, when dealing with binary data, the potential of the signals input to the input data lines Din1 to Din3 only needs to be binary at potentials corresponding to the power supply voltage (for example, Vdd and Vss). However, when dealing with multi-valued data of three or more values, the number of potential levels can be determined according to the radix used for the data being handled. naturally differ depending on the content of the data. Also, when dealing with binary data, the potential of the signals input to the input data lines Din1 to Din3 only needs to be binary at potentials corresponding to the power supply voltage (for example, Vdd and Vss). However, when dealing with multi-valued data of three or more values, the number of potential levels can be determined according to the radix used for the data being handled.

[0115] The potential input to the input data lines Din1 to Din3 is applied to the second gate electrode of the transistor 301 through the turned-on transistor 302. Then, according to the potential of the second gate electrode, the shift amount of the threshold voltage of the transistor 301 is determined. The potential input to the input data lines Din1 to Din3 is applied to the second gate electrode of the transistor 301 through the turned-on transistor 302. Then, according to the potential of the second gate electrode, the shift amount of the threshold voltage of the transistor 301 is determined. The potential input to the input data lines Din1 to Din3 is applied to the second gate electrode of the transistor 301 through the turned-on transistor 302. Then, according to the potential of the second gate electrode, the shift amount of the threshold voltage of the transistor 301 is determined.

[0116] When the input of the signal having a pulse to the write word line WL1 is completed, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, signals having pulses are input to the write word line WL2 and the write word line WL3 in order, and the above-described operation is repeated similarly in the memory cell having the write word line WL2 and the memory cell having the write word line WL3. When the input of the signal having a pulse to the write word line WL1 is completed, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, signals having pulses are input to the write word line WL2 and the write word line WL3 in order, and the above-described operation is repeated similarly in the memory cell having the write word line WL2 and the memory cell having the write word line WL3. When the input of the signal having a pulse to the write word line WL1 is completed, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, signals having pulses are input to the write word line WL2 and the write word line WL3 in order, and the above-described operation is repeated similarly in the memory cell having the write word line WL2 and the memory cell having the write word line WL3. When the input of the signal having a pulse to the write word line WL1 is completed, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, signals having pulses are input to the write word line WL2 and the write word line WL3 in order, and the above-described operation is repeated similarly in the memory cell having the write word line WL2 and the memory cell having the write word line WL3. When the input of the signal having a pulse to the write word line WL1 is completed, all the transistors 302 whose gate electrodes are connected to the write word line WL1 turn off. Then, signals having pulses are input to the write word line WL2 and the write word line WL3 in order, and the above-described operation is repeated similarly in the memory cell having the write word line WL2 and the memory cell having the write word line WL3.

[0117] Next, the operation of the storage device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 turns off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode is set during writing. Next, the operation of the storage device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 turns off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode is set during writing. Next, the operation of the storage device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 turns off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode is set during writing. Next, the operation of the storage device during data holding will be described. During holding, all the write word lines WL1 to WL3 are given a potential at which the transistor 302 turns off, specifically, a low-level potential. Since the off-current of the transistor 302 is extremely low as described above, the potential of the second gate electrode is set during writing. maintains the level. Also, for all the read word lines RL1 to RL3, a potential at which the transistor 301 turns off, specifically, a potential lower than Vth1 in FIG. 2 showing the operation of the transistor functioning as a memory element, is applied.

[0118] In the timing chart of FIG. 7, a holding period is provided to explain the operation of holding data. However, in the actual operation of the memory, it is not necessary to provide a holding period.

[0119] Next, the operation of the memory device during data readout will be described. During readout, for all the write word lines WL1 to WL3, a potential at which the transistor 302 turns off, specifically, a low-level potential, is applied as in the holding state.

[0120] On the other hand, during readout, a signal having a pulse is sequentially input to the read word lines RL1 to RL3. Specifically, first, when a signal having a pulse is input to the read word line RL1, a potential of the pulse, specifically, a potential higher than Vth1 and lower than Vth0 in FIG. 2 showing the operation of the transistor functioning as a memory element, or a potential higher than Vth0, is applied to the first gate electrode of the transistor 301. In the transistor 301, when a potential higher than Vth1 and lower than Vth0 in FIG. 2 showing the operation of the transistor functioning as a memory element, or a potential higher than Vth0, is applied to the first gate electrode, the drain current or the resistance value between the source electrode and the drain electrode is determined according to the threshold voltage set during the previous write operation.

[0121] ​​​​​​​​​Then, the drain current of transistor 301, or the resistance between the source electrode and the drain electrode The value is the potential included as information, that is, the potential of the electrode among the source electrode and the drain electrode of transistor 301 that is connected to the output data lines Dout1 to Dout3 is supplied to the drive circuit via the output data lines Dout1 to Dout3.

[0122] Note that the potential supplied to the output data lines Dout1 to Dout3 is determined according to the data written in the memory cell. Therefore, ideally, if the same value of data is stored in a plurality of memory cells, the same level of potential should be supplied to all the output data lines connected to the memory cell. However, in reality, due to variations in the characteristics of transistor 301 or transistor 302 among the memory cells, even if the data that should be read out are all the same value, variations occur in the potential supplied to the output data lines, and there may be a width in its distribution. Therefore, even if there are some variations in the potential supplied to the output data lines Dout1 to Dout3, a readout circuit that forms a signal whose width and waveform are processed according to the desired specifications, including the data read out from the above potential as information, is provided in the memory device as a drive circuit.

[0123] Fig. 9 shows an example of the readout circuit in a circuit diagram. The readout circuit shown in Fig. 9 includes transistors 310_1 to 310_3 that function as switching elements for controlling the input of the potential of the output data lines Dout1 to Dout3 to the readout circuit, and transistors that function as resistors It has transistors 311_1 to 311_3. Also, the read circuit shown in FIG. 9 has operational amplifiers 312_1 to 312_3.

[0124] Specifically, for transistors 311_1 to 311_3, their gate electrodes and drain electrodes are respectively connected, and a high-level power supply voltage Vdd is applied to the gate electrodes and drain electrodes. Also, the source electrodes of transistors 311_1 to 311_3 are connected to the non-inverting input terminals (+) of operational amplifiers 312_1 to 312_3. Thus, transistors 311_1 to 311_3 function as resistors connected between the node to which the power supply potential Vdd is applied and the non-inverting input terminals (+) of operational amplifiers 312_1 to 312_3. In FIG. 9, a transistor with its gate electrode and drain electrode connected is used as a resistor, but the present invention is not limited to this, and any element that functions as a resistor can be substituted.

[0125] Also, transistors 310_1 to 310_3 that function as switching elements have their gate electrodes connected to bit lines BL1 to BL3 respectively. Then, according to the potentials of bit lines BL1 to BL3, the connection between output data lines Dout1 to Dout3 and the source electrodes of transistors 311_1 to 311_3 is controlled.

[0126] For example, when transistor 310_1 is turned on, transistor 301 in memory cell 300 and transistor 311_1 in the read circuit are connected in series, so the potential Vdata at the subsequent node becomes the non-inverting input of operational amplifiers 312_1 to 312_3. ​​​​​​​​​​​​​​It will be applied to the terminal (+). And the level of the potential Vdata is determined according to the ratio of the resistance value between the source electrode and the drain electrode of transistor 3 01 and the resistance value between the source electrode and the drain electrode of transistor 311_1. Therefore, the value of the read data is reflected in the level of the potential Vdata.

[0127] On the other hand, the reference potential Vref is applied to the inverting input terminals (-) of operational amplifiers 312_1 to 312_3. And depending on whether the potential Vdata applied to the non-inverting input terminal (+) is higher or lower than the reference potential Vref, the level of the potential Vout at the output terminal can be made different, whereby a signal indirectly containing data as information can be obtained.

[0128] Note that even for memory cells storing the same value of data, due to the variation in characteristics between the memory cells, there is also variation in the level of the read potential Vdata, and it may have a certain width in its distribution. Therefore, the level of the reference potential Vref is determined in consideration of the variation in the potential Vdata of the nodes in order to accurately read the value of the data.

[0129] Also, in FIG. 9, one operational amplifier is used for each output data line for reading data, but the number of operational amplifiers is not limited to this. When handling data with n values (n is a natural number of 2 or more), the number of operational amplifiers used for each output data line is set to (n - 1).

[0130] Next, the operation of the storage device during data erasure will be described. During erasure, similar to the data writing operation, a signal with a pulse is input to the write word line WL1. ​​​​​​​​​​​and the potential of the pulse, specifically the high-level potential, is applied to the gate electrode, whereby for the transistors 302 each having a gate electrode connected to the write word line WL1, all turn on. On the other hand, a signal having a potential lower than Vth1 in FIG. 2 showing the operation of the transistor functioning as a memory element is input to the read word line RL1, and the transistors 301 each having a first gate electrode connected to the read word line RL1 all maintain the off state.

[0131] Then, a fixed potential such as ground is applied to the input data lines Din1 to Din3. In FIG. 7, the case where signals having a low-level potential are input to all of the input data lines Din1 to Din3 is illustrated. The low-level fixed potential input to the input data lines Din1 to Din3 is applied to the second gate electrode of the transistor 301 via the on transistor 302. Then, according to the potential of the second gate electrode, the value of the threshold voltage of the transistor 301 is reset.

[0132] When the input of the signal having a pulse to the write word line WL1 ends, all of the transistors 302 each having a gate electrode connected to the write word line WL1 turn off. Then, signals having a pulse are sequentially input to the write word line WL2 and the write word line WL3, and in the memory cells having the write word line WL2 and the memory cells having the write word line WL3, the above-described operations are similarly repeated.

[0133] In the timing chart of FIG. 7, an erasure period is provided to explain the operation of erasing data. ​​​​​​​However, in the actual operation of the memory, it is not necessary to provide an erasure period. In this case, it is only necessary to write another data so as to overwrite the previously written data. The fact that it is not necessary to provide an erasure period is one of the advantages of the memory device according to one aspect of the present invention.

[0134] Also, in this embodiment, the driving method of sequentially performing the write, hold, read, and erase operations in a plurality of memory cells has been described. However, the present invention is not limited to this configuration. The above operations may be performed only in the memory cells of the specified address.

[0135] Also, in the case of the cell array shown in FIG. 5, the case where four wirings of an input data line Din, an output data line Dout, a write word line WL, and a read word line RL are connected to each memory cell is illustrated. However, in the memory device of the present invention, the number of wirings connected to each memory cell is not limited to this. A signal for controlling the switching of the transistor 301, a signal for controlling the switching of the transistor 302, and a signal for supplying a potential to the second gate electrode of the transistor 3 01 can be supplied to the memory cell 300. In addition, the drain current of the transistor 301 or the resistance value between the source electrode and the drain electrode can be sent to the drive circuit as the potential included as information. The number of wirings and the connection structure may be appropriately determined. For controlling the switching of the transistor 301, a signal for controlling the switching of the transistor 302, and a signal for supplying a potential to the second gate electrode of the transistor 301, a signal for supplying a potential to the second gate electrode of the transistor 301, the drain current of the transistor 301, or the resistance value between the source electrode and the drain electrode can be sent to the drive circuit as the potential included as information. The number of wirings and the connection structure may be appropriately determined. can be sent to the drive circuit as the potential included as information. The number of wirings and the connection structure may be appropriately determined.

[0136] Next, taking the memory device using the cell array shown in FIG. 5 as an example, the configuration of the drive circuit of the memory device according to one aspect of the present invention will be described.

[0137] ​​FIG. 8 shows, as an example, the configuration of a memory device according to an aspect of the present invention in a block diagram. Note that In the block diagram shown in FIG. 8, the circuits in the memory device are classified by function and shown as independent blocks from each other. However, in an actual circuit, it is difficult to completely separate the circuits by function, and one circuit may be related to multiple functions.

[0138] The memory device shown in FIG. 8 has a cell array 500 in which a plurality of memory cells are connected in a matrix and a drive circuit 501 that controls the driving of the cell array 500. The drive circuit 501 includes a read circuit 502 that generates a signal including data read from the cell array 500 as information, a word line drive circuit 503 that selects the memory cells included in the cell array 500 row by row, a data line drive circuit 504 that controls writing or erasing of data in the selected memory cells, and a control circuit 505 that selects the operations of the read circuit 502, the word line drive circuit 503, and the data line drive circuit 504. The word line drive circuit 503 includes a word line decoder 506. The data line drive circuit 504 includes a data line decoder 508 and a data line selector 509.

[0139] Note that the memory device according to an aspect of the present invention only needs to include at least the cell array 500 in its configuration. The memory device according to an aspect of the present invention includes, in its scope, a cell array and a memory module in a state where part or all of a drive circuit is connected to the cell array. The memory module may be in a so-called packaged state in which connection terminals that can be mounted on a printed wiring board or the like are provided and are protected with resin or the like.

[0140] In addition, all or part of the drive circuit 501 may be formed on the same substrate as the cell array 500, or may be formed on a substrate different from the cell array 500. When all or part of the drive circuit 501 and the cell array 500 are formed on different substrates, they can be connected via an FPC (Flexible Printed Circuit) or the like. In this case, part of the drive circuit 501 may be connected to the FPC using the COF (Chip On Film) method. Also, all or part of the drive circuit 501 may be connected to the cell array 500 using the COG (Chip On Glass) method. By forming both the cell array 500 and the drive circuit 501 on the same substrate, the number of components of the external circuit connected to the storage device can be reduced, thus reducing costs

[0141] through the reduction of the assembly process and the inspection process. Also, the number of contacts at the connection part between the storage device and the external circuit can be reduced, preventing a decrease in yield due to connection failures and preventing a decrease in reliability due to the low mechanical strength at the connection points. Also, only circuits such as the word line drive circuit 503 and the data line selector 509, whose drive frequencies are relatively lower than those of other circuits, can be formed on the same substrate as the cell array 500. In this way, by partially forming the drive circuit 501 on the same substrate as the cell array 500, certain advantages can be enjoyed, such as avoiding a decrease in yield due to the above-mentioned connection failures and a decrease in mechanical strength at the connection points, and cost reduction through the reduction of the assembly process and the inspection process. In addition, compared with the case where the cell array 500 and the drive circuit 501 are all formed on a single substrate, the performance of a circuit with a high drive frequency can be further enhanced.

[0142] When a signal AD including an address (Ax, Ay) as information is input to the storage device, the control circuit 505 sends the address Ax, which is information regarding the column direction of the address, to the data line drive circuit 504 and sends the address Ay, which is information regarding the row direction of the address, to the word line drive circuit 503. Also, the control circuit 505 sends the signal DAT, which includes the data input to the storage device as information, to the data line drive circuit 504.

[0143] The selection of an operation, such as writing data, reading data, or erasing data, is selected by signals such as RE (Read enable), WE (Write enable), EE (Erase enable), etc., supplied to the control circuit 505. Note that when a plurality of cell arrays 500 are provided in the storage device, a signal CE (Chip enable) for selecting a cell array may be input to the control circuit 505. When the write operation is selected by the signal WE, in accordance with an instruction from the control circuit 505, a signal having a pulse is input to the write word line WL corresponding to the address Ay by the word line decoder 506 included in the word line drive circuit 503. On the other hand, when the write operation is selected by the signal WE, in the data line drive circuit 504, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is given to the data line selector 509. In the data line selector 509,

[0144] When the write operation is selected by the signal WE, in accordance with an instruction from the control circuit 505, a signal having a pulse is input to the write word line WL corresponding to the address Ay by the word line decoder 506 included in the word line drive circuit 503. On the other hand, when the write operation is selected by the signal WE, in the data line drive circuit 504, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is given to the data line selector 509. In the data line selector 509, When the write operation is selected by the signal WE, in accordance with an instruction from the control circuit 505, in the data line drive circuit 504, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is given to the data line selector 509. In the data line selector 509, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is given to the data line selector 509. In the data line selector 509, According to the signal from the data line decoder 508, sample the signal DATA containing data as information, and input the sampled signal to the input data line Din corresponding to the address Ax.

[0145] When the read operation is selected by the signal RE, according to the instruction from the control circuit 505, a signal having a pulse is input to the read word line RL corresponding to the address Ay by the word line decoder 506 of the word line driving circuit 503. On the other hand, when the read operation is selected by the signal RE, according to the instruction from the control circuit 505, in the read circuit 502, by controlling the potential of the bit line BL corresponding to the address Ax, the transistor among the transistors 310_1 to 310_3 corresponding to the address Ax is turned on. Then, the data stored in the memory cell of the address is read from the potential of the output data line Dout corresponding to the corresponding address Ax, and a signal containing the data as information is generated

[0146] When the erase operation is selected by the signal EE, according to the instruction from the control circuit 505, a signal having a pulse is input to the write word line WL of the corresponding address Ay by the word line decoder 506 of the word line driving circuit 503. On the other hand, when the erase operation is selected by the signal EE, according to the instruction from the control circuit 505, in the data line driving circuit 50 4, a signal for controlling the operation of the data line selector 509 from the data line decoder 508 is given to the data line selector 509. In the data line selector 509, according to the signal from the data line decoder 508, a signal for erasing data is sent to the corresponding address ​​​​​​​​​​​Input it to the input data line Din of S Ax.

[0147] In the memory device shown in FIG. 8, the word line drive circuit 503 controls both the input of a signal to the write word line W L and the input of a signal to the read word line RL. However , the present invention is not limited to this configuration. A drive circuit that controls the input of a signal to the write word line WL and a drive circuit that controls the input of a signal to the read word line RL may be provided in the memory device respectively.

[0148] This embodiment can be implemented in appropriate combination with the above embodiment.

[0149] (Embodiment 3) Taking a bottom gate type transistor with a channel etch structure as an example, a method for manufacturing a memory device according to an aspect of the present invention will be described. In this embodiment, a transistor that functions as a memory element and a transistor that functions as a switching element both use an oxide semiconductor film as an active layer, and this will be described as an example.

[0150] As shown in FIG. 10(A), gate electrodes 401 and 402 are formed on a substrate 400.

[0151] There is no significant limitation on the substrate that can be used as the substrate 400 having an insulating surface, but at least it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. For example , a glass substrate manufactured by the fusion method or the float method can be used. When the temperature of the subsequent heat treatment is high for the glass substrate, a glass substrate having a strain point of 730 °C or higher is preferably used. In addition, for the glass substrate, for example, aluminosilicate glass, aluminoborosilicate Glass materials such as acid glass and barium borosilicate glass are used. Generally, , by including more barium oxide (BaO) compared to boron oxide, a more practical heat-resistant glass can be obtained. Therefore, it is preferable to use a glass substrate containing more BaO than B2O3.

[0152] Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Additionally, crystallized glass or the like can be used. A substrate with an insulating film provided on the surface of a metal substrate such as a stainless steel alloy may also be used.

[0153] Also, a substrate made of a flexible synthetic resin such as plastic generally has a low heat-resistant temperature, but can be used as substrate 400 if it can withstand the processing temperature in the subsequent manufacturing process. Examples of plastic substrates include polyesters typified by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, and acrylic resin.

[0154] An insulating film serving as an underlayer film may be formed between substrate 400, gate electrode 401, and gate electrode 402. Examples of the underlayer film include a silicon oxide film, a silicon oxynitride film, and a silicon nitride film. Any one of a film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used singly or in multiple layers. In particular, a highly barrier insulating film, such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc., is used for the base film to prevent impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals and heavy metals contained in the substrate 400 from entering into the oxide semiconductor film, the gate insulating film, or the interface and its vicinity between the oxide semiconductor film and other insulating films.

[0155] In this specification, an oxynitride refers to a substance with a higher oxygen content than nitrogen in its composition, and a nitride oxide refers to a substance with a higher nitrogen content than oxygen in its composition.

[0156] The materials for the gate electrodes 401 and 402 can be metal materials such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc., conductive films using these metal materials as the main components, or nitrides of these metals, which can be used singly or in layers. If it can withstand the temperature of the heat treatment performed in subsequent processes, aluminum or copper can also be used as the above metal materials. Aluminum or copper is preferably used in combination with a high-melting point metal material to avoid problems of heat resistance and corrosiveness. Examples of high-melting point metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc.

[0157] For example, as the gate electrodes 401 and 402 having a two-layer laminated structure, aluminum A two-layer laminated structure with a molybdenum film laminated on a um film, a molybdenum film laminated on a copper film A two-layer structure, a two-layer structure with a titanium nitride film or a tantalum nitride film laminated on a copper film, or It is preferable to form a two-layer structure in which a titanium nitride film and a molybdenum film are laminated. A gate electrode 401 and a gate electrode 402 having a three-layer laminated structure are preferably made of an aluminum film, an alloy film of aluminum and silicon, an alloy film of aluminum and titanium, or an alloy film of aluminum and neodymium as an intermediate layer, and a tungsten film, a tungsten nitride film, a titanium nitride film, or a titanium film as upper and lower layers. Also, by using a transparent oxide conductive film such as an indium oxide film, an indium tin oxide alloy film, an indium zinc oxide alloy film, a zinc oxide film, a zinc aluminum oxide film, a zinc aluminum nitride film, or a zinc gallium oxide film for the gate electrode 401 and the gate electrode 402, the aperture ratio of the pixel portion can be improved.

[0158] The film thickness of the gate electrode 401 and the gate electrode 402 is 10 nm to 400 nm, preferably 10 0 nm to 200 nm. In this embodiment, after forming a conductive film for the gate electrode with a thickness of 150 nm by sputtering using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching, thereby forming the gate electrode 401 and the gate electrode 402. It is preferable that the end of the formed gate electrode has a tapered shape because the covering property of the gate insulating film laminated thereon is improved. In addition, a resist mask may be formed by an inkjet method. When a resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0159] The film thickness of the gate electrode 401 and the gate electrode 402 is 10 nm to 400 nm, preferably 10 0 nm to 200 nm. In this embodiment, a conductive film for the gate electrode with a thickness of 150 nm is formed by sputtering using a tungsten target, and then the conductive film is processed (patterned) into a desired shape by etching, thereby forming the gate electrode 401 and the gate electrode 402. Note that it is preferable that the end of the formed gate electrode has a tapered shape because the covering property of the gate insulating film laminated thereon is improved. In addition, a resist mask may be formed by an inkjet method. When a resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced. When the end of the formed gate electrode has a tapered shape, it is preferable because the covering property of the gate insulating film laminated thereon is improved. In addition, a resist mask may be formed by an inkjet method. Forming a resist mask by an inkjet method does not use a photomask, so the manufacturing cost can be reduced. It is also possible to form a resist mask by an inkjet method. When a resist mask is formed by an inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0160] Next, a gate insulating film 403 is formed on the gate electrodes 401 and 402. The gate insulating film 403 can be formed by using a plasma CVD method, a sputtering method, etc., as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, an aluminum nitride oxide film, a hafnium oxide film, or a tantalum oxide film. It is desirable that the gate insulating film 403 contains as few impurities such as moisture and hydrogen as possible. When forming a silicon oxide film by a sputtering method, a silicon target or a quartz target is used as a target, and oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0161] By removing impurities, a type-i or substantially type-i oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to interface levels and interface charges. Therefore, the interface between the highly purified oxide semiconductor and the gate insulating film 403 is important. For this reason, the gate insulating film (GI) in contact with the highly purified oxide semiconductor is required to have high quality.

[0162] For example, high-density plasma CVD using microwaves (2.45 GHz) is preferable because it can form a dense and high breakdown voltage high-quality insulating film. Since the highly purified oxide semiconductor and the high-quality gate insulating film are in close contact, the interface level can be reduced and the interface characteristics can be made good.

[0163] Of course, as long as a high-quality insulating film can be formed as the gate insulating film, sputtering Other film formation methods such as a thermal oxidation method or a plasma CVD method can be applied. Further, the film quality of the gate insulating film and the interface characteristics between the gate insulating film and the oxide semiconductor can be improved by heat treatment after film formation It may be an insulating film. In any case, it goes without saying that the film quality as the gate insulating film is good. As long as the interface state density between the gate insulating film and the oxide semiconductor can be reduced and a good interface can be formed

[0164] A gate insulating film 403 having a structure in which an insulating film using a material with high barrier properties and an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio are laminated may be formed. In this case, the insulating film such as a silicon oxide film or a silicon oxynitride film is formed between the insulating film with high barrier properties and the oxide semiconductor film. Examples of the insulating film with high barrier properties include a silicon nitride film, a silicon oxynitride film By using an insulating film with high barrier properties, impurities in the atmosphere such as moisture or hydrogen, or impurities such as alkali metals or heavy metals contained in the substrate can be prevented from entering the oxide semiconductor film, the gate insulating film 403, or the interface between the oxide semiconductor film and other insulating films and the vicinity thereof. Further, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen content ratio in contact with the oxide semiconductor film, it is possible to prevent the insulating film with high barrier properties from directly contacting the oxide semiconductor film

[0165] For example, a silicon nitride film (SiN (y>0)) with a film thickness of 50 nm or more and 200 nm or less is formed as the first gate insulating film by sputtering, and a silicon oxide film (SiO y (y>0)) with a film thickness of 5 nm or more and 300 nm or less is formed as the second gate insulating film on the first gate insulating film ​​​​​​​​​​​x (x > 0)) can be laminated to form a gate insulating film 403 with a film thickness of 100 nm. The film thickness of the gate insulating film 403 can be appropriately set according to the characteristics required for the transistor, and can be about 350 nm to 400 nm.

[0166] In this embodiment, on a silicon nitride film with a film thickness of 50 nm formed by sputtering, a silicon oxide film with a film thickness of 100 nm formed by sputtering is laminated to form a gate insulating film 40 3.

[0167] In addition, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the gate insulating film 403, as a pre-treatment for film formation, the substrate 400 on which the gate electrodes 401 and gate electrode 402 are formed is pre-heated in the pre-heating chamber of the sputtering apparatus, and the moisture or water adsorbed on the substrate 400, such as impurities, are desorbed and exhausted. The pre-heating temperature is preferably 100 °C or higher and 400 °C or lower, preferably 150 °C or higher and 300 °C or lower. The exhaust means provided in the pre-heating chamber is preferably a cryopump. This pre-heating process can be omitted if necessary.

[0168] Next, an oxide semiconductor film 40 with a film thickness of 2 nm or more and 200 nm or less, preferably a film thickness of 3 nm or more and 50 nm or less, and more preferably a film thickness of 3 nm or more and 20 nm or less is formed on the gate insulating film 403. The oxide semiconductor film 404 is formed by sputtering using an oxide semiconductor as a target. In addition, the oxide semiconductor film 404 can be formed by sputtering in a rare gas (e.g., argon) atmosphere, in an oxygen atmosphere, or in a mixed atmosphere of a rare gas (e.g., argon) and oxygen. ​​

[0169] Before forming the oxide semiconductor film 404 by sputtering, argon gas is introduced to perform reverse sputtering to generate plasma, and remove the dust adhering to the surface of the gate insulating film 403 which is preferable. Reverse sputtering is a method of forming plasma on the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere . Further, it may be performed in an atmosphere in which oxygen, hydrogen, nitrous oxide, etc. are added to the argon atmosphere. Further, it may be performed in an atmosphere in which chlorine, carbon tetrafluoride, etc. are added to the argon atmosphere.

[0170] As the oxide semiconductor film 404, the oxide semiconductors as described above can be used.

[0171] In this embodiment, an In-Ga-Zn-O-based non-single crystal film with a film thickness of 30 nm obtained by a sputtering method using an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc) is used as the oxide semiconductor film 404. As the above target, for example, an oxide semiconductor target having a composition ratio of the atomic ratio of each metal of In:Ga:Zn = 1:1:0.5, In:Ga:Zn = 1:1 :1, or In:Ga:Zn = 1:1:2 can be used. Further, when using the sputtering method, film formation may be performed using a target containing 2% by weight or more and 1 0% by weight or less of SiO2. Further, the filling rate of the oxide semiconductor target containing In, Ga, and Zn is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide semiconductor target with a high filling rate, the formed oxide semiconductor film becomes a dense film. ​​​​

[0172] A substrate is held in a processing chamber maintained under a reduced pressure state, and while removing residual moisture in the processing chamber, hydrogen and sputter gas from which moisture has been removed is introduced, and an oxide semiconductor film 404 is formed on a substrate 400 using a metal oxide as a target. During film formation, the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor film can be reduced. In addition, damage due to sputtering can be reduced. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Further, as an exhaust means, a turbo pump with a cold trap added thereto may be used. The film formation chamber evacuated using a cryopump is, for example, evacuated of compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well), and thus the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0173] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, a DC power source is 0.5 kW, and the conditions under an oxygen (oxygen flow ratio 100%) atmosphere are applied. Note that when a pulsed DC power source is used, dust called particles generated during film formation can be reduced, and the film thickness distribution becomes uniform, which is preferable. The oxide semiconductor film is preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, and the thickness may be appropriately selected according to the material.

[0174] Note that the oxide semiconductor film 404 should contain as little hydrogen, hydroxyl groups, and moisture as possible. Therefore, as a pretreatment for film formation, the substrate 400 on which the gate insulating film 403 is formed is preheated in the preheating chamber of the sputtering apparatus, and it is preferable to desorb and exhaust impurities such as moisture or hydrogen adsorbed on the substrate 400. The preheating temperature is preferably 100°C or higher and 40 0°C or lower, more preferably 150°C or higher and 300°C or lower. The exhaust means provided in the preheating chamber is preferably a cryopump. Note that this preheating process can also be omitted. In addition, this preheating can be similarly performed on the substrate 400 on which the source electrodes 407 and drain electrodes 40 8, source electrodes 409 and drain electrodes 410 are formed before the formation of the insulating film 411. It is also possible.

[0175] There are an RF sputtering method that uses a high-frequency power source as a sputtering power source and a D C sputtering method in the sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulsewise. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0176] In addition, there is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and deposit different material films in the same chamber, or can simultaneously discharge a plurality of types of materials in the same chamber to form a film.

[0177] In addition, there are sputtering apparatuses that use a magnetron sputtering method equipped with a magnet mechanism inside the chamber, and ECR sp uttering apparatuses that use plasma generated using microwaves without using glow discharge.

[0178] In addition, as a film formation method using a sputtering method, there is a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0179] The gate insulating film 403 and the oxide semiconductor film 404 may be continuously formed without exposing them to the atmosphere. By continuously forming the film without exposing it to the atmosphere, the interface is not contaminated by atmospheric components such as water and hydrocarbons and impurity elements floating in the atmosphere, and each laminated interface can be formed, so that variations in transistor characteristics can be reduced.

[0180] Next, as shown in FIG. 10(B), the oxide semiconductor film 404 is processed (patterned) into a desired shape by etching or the like, and island-shaped oxide semiconductor films 405 and 406 are formed on the gate insulating film 403 at positions overlapping with the gate electrode 401 and the gate electrode 402. respectively.

[0181] A resist mask for forming the island-shaped oxide semiconductor films 405 and 406 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photo mask is not used, the manufacturing cost can be reduced.

[0182] Also, when forming a contact hole in the gate insulating film 403, the process can be performed when forming the island-shaped oxide semiconductor films 405 and 406.

[0183] Note that etching for forming the island-shaped oxide semiconductor films 405 and 406 It may be dry etching, wet etching, or both. For the etching gas used in dry etching, a gas containing chlorine (chlorine-based gas, such as chlorine ( Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.) is preferred. Also, a gas containing fluorine (fluorine-based gas, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon ( Ar) to these gases, etc. can be used. As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that the desired processing shape can be etched. ) As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO-07N (manufactured by Kanto Chemical Co., Inc.) can be used. Also,

[0184] After wet etching, the etching solution is removed by washing together with the etched material. The waste liquid of the etching solution containing the removed material can be purified and the contained material can be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor film from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced. ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately adjusted so that the desired processing shape can be etched.

[0185]

[0186] Before forming the conductive film in the next process, reverse sputtering is performed to remove resist residues and the like adhering to the surfaces of the island-shaped oxide semiconductor film 405, oxide semiconductor film 406, and gate insulating film 403. It is preferable to remove them.

[0187] Next, heat treatment is performed on the oxide semiconductor film 405 and the oxide semiconductor film 406 in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a noble gas (argon, helium, etc.). By performing heat treatment on the oxide semiconductor film 405 and the oxide semiconductor film 406, moisture or hydrogen in the oxide semiconductor film 40 5 and the oxide semiconductor film 406 can be desorbed. Specifically, heat treatment may be performed at 300°C or higher and 850°C or lower (or a temperature equal to or lower than the strain point of the glass substrate), preferably 550 °C or higher and 750°C or lower. For example, it may be performed at about 600°C for 3 minutes or more and 6 minutes or less. If the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so treatment can be performed even at a temperature exceeding the strain point of the glass substrate. Alternatively, heat treatment may be performed for about 1 hour in a state where the substrate temperature has reached 450°C. In this embodiment, an electric furnace, which is one of the heat treatment apparatuses, is used to perform heat treatment on the oxide semiconductor film 405 and the oxide semiconductor film 406 for 6 minutes in a nitrogen atmosphere in a state where the substrate temperature has reached 600°C. After the above heat treatment, in order to prevent re-mixing of moisture or hydrogen,

[0188] the oxide semiconductor film 405 and the oxide semiconductor film 406 are not allowed to come into contact with the atmosphere. Note that the heat treatment apparatus is not limited to an electric furnace, and heat conduction or heat from a heating element such as a resistance heating element can be used.

[0189] is used. ​It may be provided with an apparatus for heating an object to be processed by radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus for heating an object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus for performing heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or a non-reactive gas such as nitrogen that does not react with the object to be processed by heat treatment is used. For example, as the heat treatment, GRTA may be performed by moving a substrate into an inert gas heated to a high temperature of 650 °C to 700 °C, heating for several minutes, and then moving the substrate out of the inert gas heated to a high temperature. Using GRTA enables high-temperature heat treatment in a short time. In heat treatment, it is preferable that nitrogen or an inert gas such as helium, neon, or argon does not contain moisture or hydrogen. Alternatively, the purity of nitrogen or an inert gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). If impurities such as moisture or hydrogen are added to the oxide semiconductor, at 85 °C, 2 × 10

[0190]

[0191]

[0192] 6 V ​​​​​​​​​​In a 12-hour gate bias-thermal stress test (BT test) at / cm, the bond between the impurity and the main component of the oxide semiconductor is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated unpaired bond induces a drift in the threshold voltage (Vth). However, as described above, by improving the interface characteristics between the gate insulating film and the oxide semiconductor film and removing impurities in the oxide semiconductor film, especially moisture or hydrogen as much as possible, a stable transistor can be obtained even for the BT test. By the above process, the concentration of hydrogen in the oxide semiconductor film can be reduced and purified, thereby stabilizing the oxide semiconductor film. Also, by heat treatment below the glass transition temperature, an oxide semiconductor film with an extremely low carrier density and a wide bandgap can be formed. Therefore, transistors can be manufactured using a large-area substrate, thereby improving mass productivity. Also, by using the oxide semiconductor film with the reduced and purified hydrogen concentration, a transistor with high breakdown voltage, low short-channel effect, and high on-off ratio can be manufactured. When heating the oxide semiconductor film, depending on the material of the oxide semiconductor film and the heating conditions, plate-like crystals may be formed on its upper surface. The plate-like crystals are preferably single crystals with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film. Also, even if it is not a single crystal, in the channel formation region, the ab planes of each crystal coincide, or the a-axis or b-axis all coincide, and it is preferably a polycrystal with a c-axis orientation substantially perpendicular to the surface of the oxide semiconductor film.

[0193]

[0194] ​​​​​​​​​​​​​​That is, when there are irregularities on the underlying surface of the oxide semiconductor film, the plate-like crystals become polycrystals.

[0195] Next, as shown in FIG. 10(C), on the gate insulating film 403, the oxide semiconductor film 405, and the oxide semiconductor film 406, after forming a conductive film that will become the source electrode and the drain electrode (including wirings formed in the same layer), by patterning the conductive film, a source electrode 407 and a drain electrode 408 are formed on the oxide semiconductor film 405, and a source electrode 409 and a drain electrode 410 are formed on the oxide semiconductor film 406, respectively. The conductive film may be formed by sputtering or vacuum evaporation. As materials for the conductive film that will become the source electrode and the drain electrode (including wirings formed in the same layer), elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W, alloys containing the above-described elements as components, or alloy films combining the above-described elements can be mentioned. Also, a configuration in which a high melting point metal film such as Cr, Ta, Ti, Mo, or W is laminated on the lower side or the upper side of a metal film such as Al or Cu may be used. Moreover, it is possible to improve the heat resistance by using an Al material to which elements for preventing the generation of hillocks and whiskers occurring in the Al film, such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, and Y, are added.

[0196] In addition, the conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a Ti film is laminated, an aluminum film is further laminated on the Ti film, and a Ti film is formed on the aluminum film can be mentioned.

[0197] ​​​​​​​Also, the conductive film serving as the source electrode and the drain electrode (including the wiring formed in the same layer) may be formed of a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide alloy (In2O3―SnO2, abbreviated as ITO), indium zinc oxide alloy (In2O3―ZnO), or a material obtained by adding silicon or silicon oxide to the metal oxide material can be used.

[0198] When performing heat treatment after forming the conductive film, it is preferable to endow the conductive film with heat resistance that can withstand this heat treatment.

[0199] Then, a resist mask is formed on the conductive film, and selective etching is performed to form the source electrode 4 07 and the drain electrode 408, and the source electrode 409 and the drain electrode 410. After that, the resist mask is removed.

[0200] For the exposure during the formation of the resist mask in the photolithography process, ultraviolet light, KrF laser light or ArF laser light is used. The channel length L of the transistor formed later is determined by the distance between the lower ends of the adjacent source electrodes and the lower ends of the drain electrodes on the oxide semiconductor film 405 and the oxide semiconductor film 406. When performing exposure with a channel length L of less than 25 nm in the photolithography process during the formation of the resist mask, extreme ultraviolet light with a wavelength as short as several nm to several tens of nm is used for exposure. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the transistor formed later to be 10 nm or more and 1000 nm or less, and the circuit This allows for faster operation and, because the off-current is extremely small, it also reduces power consumption. This can be done.

[0201] Note that the oxide semiconductor film 405 and the oxide semiconductor film 406 are formed during etching of the conductive film. The materials and etching conditions are appropriately adjusted so that as little as possible is removed.

[0202] In this embodiment, a titanium film is used as the conductive film, and a solution containing ammonia and hydrogen peroxide (a The conductive film is wet-etched using ammonia peroxide to form the source electrode 407 and A source electrode 409 and a drain electrode 410 are formed on the gate electrode 402. The solution containing ammonium peroxide is specifically 31% by weight of hydrogen peroxide and 28% by weight of ammonium peroxide. Use an aqueous solution of monium oxide and water in a volume ratio of 5:2:2. Alternatively, use chlorine (Cl2 The conductive film may be dry-etched using a gas containing boron chloride (BCl3) or the like. stomach.

[0203] By the above patterning, a source electrode 407, a drain electrode 408, and a source electrode 409 are formed. When forming the island-shaped oxide semiconductor film 405, the oxide semiconductor The exposed portion of the film 406 is partially etched to form a groove (recess). In addition, a source electrode 407 and a drain electrode 408, and a source electrode 409 and a drain electrode A resist mask for forming the inner electrode 410 may be formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used, so the manufacturing process is This reduces manufacturing costs.

[0204] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a halftone mask that gives multi-level intensity to incident light may be used to perform an etching process. The resist mask formed using the halftone mask has a shape with a plurality of film thicknesses, and the shape can be further deformed by performing etching, so it can be used in a plurality of etching processes for processing different patterns. Therefore, using a single halftone mask, resist masks corresponding to at least two or more different patterns can be formed. Thus, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, enabling simplification of the process.

[0205] Next, plasma treatment using a gas such as N2O, N2, or Ar is performed. This plasma treatment removes adsorbed water and the like adhering to the surface of the exposed oxide semiconductor film. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0206] Note that after the plasma treatment, as shown in FIG. 10(D), an insulating film 411 is formed so as to cover the source electrode 407 and the drain electrode 408, the source electrode 409 and the drain electrode 410, the oxide semiconductor film 405, and the oxide semiconductor film 406. The insulating film 411 desirably contains as few impurities as possible, such as moisture and hydrogen, and may be a single-layer insulating film or may be composed of a plurality of laminated insulating films. If hydrogen is contained in the insulating film 411, the hydrogen may penetrate into the oxide semiconductor film, or the hydrogen may extract oxygen in the oxide semiconductor film, resulting in a decrease in the resistance of the back channel portion of the oxide semiconductor film (n-type conversion) and the possible formation of a parasitic channel. Therefore, the insulating film 411 should be a film that contains as little hydrogen as possible ​​​​It is important not to use hydrogen in the film formation method. For the insulating film 411, it is desirable to use a material with high barrier properties. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen content ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor films 405 and 406. Then, an insulating film with a low nitrogen content ratio is sandwiched between them, and an insulating film with high barrier properties is formed so as to overlap the source electrodes 407 and 408, the source electrodes 409 and 410, and the oxide semiconductor films 405 and 406. By using an insulating film with high barrier properties, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor films 405 and 406, the gate insulating film 403, or the interface between the oxide semiconductor films 405 and 406 and other insulating films and the vicinity thereof. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. It is desirable to use a material with high barrier properties. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film can be used. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen content ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor films 405 and 406. When using a plurality of laminated insulating films, an insulating film such as a silicon oxide film or a silicon oxynitride film with a lower nitrogen content ratio than the above-mentioned insulating film with high barrier properties is formed on the side closer to the oxide semiconductor films 405 and 406. Then, an insulating film with a low nitrogen content ratio is sandwiched between them, and an insulating film with high barrier properties is formed so as to overlap the source electrodes 407 and 408, the source electrodes 409 and 410, and the oxide semiconductor films 405 and 406. Then, an insulating film with a low nitrogen content ratio is sandwiched between them, and an insulating film with high barrier properties is formed so as to overlap the source electrodes 407 and 408, the source electrodes 409 and 410, and the oxide semiconductor films 405 and 406. By using an insulating film with high barrier properties, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor films 405 and 406, the gate insulating film 403, or the interface between the oxide semiconductor films 405 and 406 and other insulating films and the vicinity thereof. By using an insulating film with high barrier properties, it is possible to prevent impurities such as moisture or hydrogen from entering the oxide semiconductor films 405 and 406, the gate insulating film 403, or the interface between the oxide semiconductor films 405 and 406 and other insulating films and the vicinity thereof. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406. Also, by forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low nitrogen ratio so as to contact the oxide semiconductor films 405 and 406, it is possible to prevent the insulating film using a material with high barrier properties from directly contacting the oxide semiconductor films 405 and 406.

[0207] In this embodiment, the insulating film 411 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C. In this embodiment, the insulating film 411 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. In this embodiment, the insulating film 411 having a structure in which a silicon nitride film with a thickness of 100 nm formed by sputtering is laminated on a silicon oxide film with a thickness of 200 nm formed by sputtering is formed. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is 100 °C.

[0208] Note that after forming the insulating film 411, a heat treatment may be performed. The heat treatment is preferably performed in an atmosphere of nitrogen, oxygen , ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium), preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher and 350°C or lower. In the present embodiment form, for example, a heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Alternatively, before forming the source electrode 407 and the drain electrode 408, and the source electrode 409 and the drain electrode 410, a rapid thermal annealing (RTA) treatment similar to the previous heat treatment performed on the oxide semiconductor film may be performed for a short time at a high temperature. Even if oxygen deficiency has occurred in the oxide semiconductor film 405 and the oxide semiconductor film 406 due to the previous heat treatment performed on the oxide semiconductor film, after the exposed region of the oxide semiconductor film 405 provided between the source electrode 40 7 and the drain electrode 408 is provided in contact with the oxygen-containing insulating film 411, or after the exposed region of the oxide semiconductor film 406 provided between the source electrode 409 and the drain electrode 41 0 is provided in contact with the oxygen-containing insulating film 411, by performing a heat treatment, oxygen is supplied to the oxide semiconductor film 405 and the oxide semiconductor film 406. Therefore, by supplying oxygen to the regions of the oxide semiconductor film 405 and the oxide semiconductor film 406 that are in contact with the insulating film 411, oxygen deficiencies serving as donors can be reduced, and a structure that satisfies the stoichiometric composition ratio can be achieved. As a result, the oxide semiconductor film 405 and the oxide semiconductor film 406 can be made i-type or substantially i-type, and the electrical characteristics of the transistor can be improved and the variation in the electrical characteristics can be reduced. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 411. Other than that, as long as it is after the formation of the insulating film 411, it is not particularly limited. By reducing the oxygen deficiency serving as a donor, a structure that satisfies the stoichiometric composition ratio can be achieved. As a result, the oxide semiconductor film 405 and the oxide semiconductor film 406 can be made i-type or substantially i-type, and the electrical characteristics of the transistor can be improved and the variation in the electrical characteristics can be reduced. The timing for performing this heat treatment is not particularly limited as long as it is after the formation of the insulating film 411. Heat treatment in the process, for example, heat treatment during resin film formation or heat treatment for reducing the resistance of a transparent conductive film, can also serve as the above heat treatment, so that the number of steps can be increased without increasing the number of steps, and the oxide semiconductor film 405 and the oxide semiconductor film 406 can be made into i-type or substantially i-type. This can be achieved.

[0209] FIG. 11(A) shows a top view of the memory device after the process shown in FIG. 10(D) is completed. Note that the cross-sectional view along the dashed line A1-A2 in FIG. 11(A) corresponds to FIG. 10(D).

[0210] Next, a contact hole 412 is formed in the insulating film 411 by etching or the like to expose a part of the drain electrode 408. Then, as shown in FIG. 10(E), after forming a conductive film on the insulating film 411, the conductive film is patterned to form a back gate electrode 413 at a position overlapping the oxide semiconductor film 406. Then, an insulating film 414 is formed so as to cover the back gate electrode 413. The back gate electrode 413 is connected to the drain electrode 408 at the contact hole 412. The back gate electrode 413 can be formed using the same material and structure as the gate electrode 401, the gate electrode 402, or the source electrode 407 and the drain electrode 408, the source electrode 409 and the drain electrode 410. The thickness of the back gate electrode 413 is 10 nm to 400 nm, preferably 100 nm to 20 0 nm. In this embodiment, after forming a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are laminated, a resist mask is formed by photolithography or the like, and unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning ). It is possible to form the back gate electrode 413 using the same material and structure as the gate electrode 401, the gate electrode 402, or the source electrode 407 and the drain electrode 408, the source electrode 409 and the drain electrode 410.

[0211] The film thickness of the back gate electrode 413 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, after forming a conductive film having a structure in which a titanium film, an aluminum film, and a titanium film are laminated, a resist mask is formed by photolithography or the like, and unnecessary portions are removed by etching to process the conductive film into a desired shape (patterning ). Then, unnecessary parts are removed by etching to process the conductive film into a desired shape (patterning).​ By performing (g), the back gate electrode 413 is formed.

[0212] The insulating film 414 is desirably made of a material with high barrier properties that can prevent moisture, hydrogen, etc. in the atmosphere from affecting the characteristics of the transistor. For example, as the insulating film with high barrier properties, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film, etc. can be formed in a single layer or laminated by a plasma CVD method or a sputtering method, etc. To obtain the effect of the barrier property, the insulating film 414 is preferably formed with a film thickness of, for example, 15 nm to 400 nm.

[0213] In this embodiment, an insulating film with a thickness of 300 nm is formed by the plasma CVD method. The film formation conditions are that the flow rate of the silane gas is 4 sccm, the flow rate of dinitrogen monoxide (N2O) is 800 sccm, and the substrate temperature is 400 °C.

[0214] Through the above steps, the transistor 420 that functions as a switching element, the transistor 421 that functions as a memory element, and the capacitor element 430 are formed. FIG. 11(B) shows a top view of the memory cell shown in FIG. 10(E). FIG. 10(E) corresponds to a cross-sectional view taken along the broken line A1 - A2 in FIG. 11(B).

[0215] The transistor 420 has a gate electrode 401 formed on a substrate 400 having an insulating surface, a gate insulating film 403 on the gate electrode 401, an oxide semiconductor film 405 overlapping the gate electrode 401 on the gate insulating film 403, and a pair of source electrodes 407 or drain electrodes 408 formed on the oxide semiconductor film 405. Further, the transistor 4 It is also acceptable to include the insulating film 411 formed on the oxide semiconductor film 405 in its components. The transistor 420 shown in Fig. 10(E) has a channel etch structure in which a part of the oxide semiconductor film 405 is etched between the source electrode 407 and the drain electrode 40 8. There is.

[0216] Note that although the transistor 420 has been described using a single-gate structure transistor, if necessary, by having a plurality of gate electrodes 401 electrically connected, a multi-gate structure transistor having a plurality of channel formation regions can also be formed.

[0217] Also, the transistor 421 includes a gate electrode 4 02 formed on a substrate 400 having an insulating surface, a gate insulating film 403 on the gate electrode 402, and a gate electrode 402 on the gate insulating film 403 overlapping oxide semiconductor film 406, a pair of source electrodes 409 or drain electrodes 410 formed on the oxide semiconductor film 406, an insulating film 411 formed on the oxide semiconductor film 406, the source electrode 409, the drain electrode 410, and a back gate electrode 4 13 overlapping the oxide semiconductor film 406 and the gate electrode 402 on the insulating film 411. Further, the transistor 421 may include an insulating film 414 formed on the back gate electrode 413 in its components. The transistor 4 shown in Fig. 10(E) 21 has a channel etch structure in which a part of the oxide semiconductor film 406 is etched between the source electrode 409 and the drain electrode 410.

[0218] Note that although the transistor 421 has been described using a single-gate structure transistor, if necessary, ​​​​Optionally, a plurality of electrically connected gate electrodes 402 may be provided to form a channel. A transistor having a multi-gate structure having a plurality of regions can also be formed.

[0219] The capacitor 430 is connected between the source electrode 409 and the back gate electrode of the transistor 421. 413 are formed in a region where they overlap with each other with the insulating film 411 therebetween.

[0220] The gate electrode 402 of the transistor 421 is controlled to output data. The operation of the memory element, such as writing, reading, retaining, and erasing, can be selected. The back gate electrode 413 functions as a first electrode. In this way, the threshold voltage of the transistor 421 used as a memory element can be controlled. In this embodiment, the transistor used as a memory element is In the transistor 421, the gate electrode 402 formed before the oxide semiconductor film 406 is The back gate electrode 413 formed after the first electrode and the oxide semiconductor film 406 is connected to the second electrode. Although illustrated with a memory cell used as a pole, the invention is not limited to this configuration. For example, in the transistor 421 used as a memory element, The gate electrode 402 formed on the oxide semiconductor film 406 is a second electrode. It is also possible to operate the back gate electrode 413 as the first electrode. In this case, the gate electrode 402 is provided instead of the back gate electrode 413 of the transistor 420. A connection is made to the drain electrode 408 .

[0221] In addition, in FIG. 11B, the back gate electrode 413 covers the entire oxide semiconductor film 406. Although the case where [it is] is exemplified, the present invention is not limited to this configuration. The back gate electrode 41 3 only needs to overlap at least a part of the channel formation region of the oxide semiconductor film 406 is sufficient.

[0222] Note that the band gap of the oxide semiconductor is 3.0 to 3.5 eV. On the other hand, silicon carbide has a band gap of 3.26 eV, and gallium nitride has a band gap of 3.39 eV, both of which have a band gap about three times that of silicon. Therefore, these compound semiconductors such as silicon carbide and gallium nitride are common with the oxide semiconductor in terms of being wide-gap semiconductors, and the characteristic of having a large band gap is advantageous for improving the breakdown voltage of the transistor, reducing power loss, etc. Next, how removing impurities such as moisture or hydrogen contained in the oxide semiconductor film as much as possible and purifying the oxide semiconductor film affects the characteristics of the transistor will be described below.

[0223] Next, how removing impurities such as moisture or hydrogen contained in the oxide semiconductor film as much as possible and purifying the oxide semiconductor film affects the characteristics of the transistor will be described below. and purifying the oxide semiconductor film as much as possible affects the characteristics of the transistor will be described below. affects the characteristics of the transistor will be described below.

[0224] FIG. 12 shows a longitudinal sectional view of an inverted staggered type transistor using an oxide semiconductor. A gate insulating film (GI) is provided on a gate electrode (GE), and an oxide semiconductor film (OS) is provided via the gate insulating film. A source electrode (S) and a drain electrode (D) are provided on the oxide semiconductor film, and an insulating film is provided so as to cover the source electrode (S) and the drain electrode (D). An oxide semiconductor film (OS) is provided via a gate insulating film (GI) on a gate electrode (GE), and a source electrode (S) and a drain electrode (D) are provided on the oxide semiconductor film, and an insulating film is provided so as to cover the source electrode (S) and the drain electrode (D). and a source electrode (S) and a drain electrode (D) are provided thereon, and an insulating film is provided so as to cover the source electrode (S) and the drain electrode (D). An insulating film is provided so as to cover the source electrode (S) and the drain electrode (D).

[0225] FIG. 13 shows an energy band diagram (schematic diagram) on A-A' shown in FIG. 12. Also in FIG. 13, black circles (●) indicate electrons, and white circles (○) indicate holes, each of which is a charge It has -q and +q. After applying a positive voltage (VD>0) to the drain electrode (D), The dashed line indicates the case where no voltage is applied to the gate electrode (GE) (VG = 0), and the solid line indicates the case where a positive voltage (VG>0) is applied to the gate electrode (G E). When no voltage is applied to the gate electrode (GE), due to the high potential barrier, carriers (electrons) are not injected from the source electrode (S) into the oxide semiconductor film (OS) side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate electrode (GE), the potential barrier decreases, showing an on state where current flows .

[0226] Figure 14 is an energy band diagram (schematic diagram) on B - B' in Figure 12. Figure 14(A) shows the state where a positive potential (VG>0) is applied to the gate electrode (GE), indicating an on state where carriers (electrons) flow between the source electrode (S) and the drain electrode (D). Also, Figure 14(B) shows the state where a negative potential (VG<0) is applied to the gate electrode (GE) , indicating the off state (where minority carriers do not flow).

[0227] Figure 15 shows the relationship between the vacuum level, the work function of the metal (φ M ), and the electron affinity (χ) of the oxide semiconductor .

[0228] At room temperature, electrons in the metal are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are generally n - type. In that case, the Fermi level (Ef) is away from the intrinsic Fermi level (Ei) located at the center of the bandgap and is located closer to the conduction band (Ec) . It is known that a part of hydrogen in the oxide semiconductor becomes a donor, which is one of the factors for the n - type conversion of the oxide semiconductor. Also, oxygen deficiency is one of the factors for n - type conversion .​ is known.

[0229] On the other hand, one aspect of the present invention is to remove hydrogen, which is an n-type impurity, from the oxide semiconductor to purify it to a high purity so that impurities other than the main component of the oxide semiconductor are not contained as much as possible, and to remove oxygen vacancies, thereby bringing the oxide semiconductor as close as possible to an intrinsic state. That is, instead of doping impurities to make the oxide semiconductor an i-type, by removing impurities such as moisture or hydrogen and oxygen vacancies as much as possible and purifying to a high purity, an i-type (intrinsic semiconductor) or an oxide semiconductor as close as possible to an i-type (intrinsic semiconductor) is obtained. With the above configuration, as shown by the arrow, the Fermi level (Ef) can approach the same level as the intrinsic Fermi level (Ei) as close as possible. can approach.

[0230] The band gap (Eg) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4.3 V. The work function of titanium (Ti) constituting the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0231] At this time, electrons move to the lowest energy-stable part on the oxide semiconductor side at the interface between the gate insulating film and the highly purified oxide semiconductor, as shown in FIG. 14(A).

[0232] Also, in FIG. 14(B), when a negative potential is applied to the gate electrode (GE), since the number of minority carriers which are holes is substantially zero, the current becomes a value close to zero as much as possible.

[0233] Next, the intrinsic carrier density in the oxide semiconductor was calculated. In-Ga-Zn-O-based oxide The band gap of the semiconductor is 3.05 eV, and the intrinsic carrier density was calculated based on this value The energy distribution f(E) of electrons in a solid is known to follow the Fermi-Dirac statistics shown by the following equation.

[0234]

Eq.

[0235] In a normal semiconductor where the carrier density is not extremely high (non-degenerate), the following relational expression holds .

[0236]

Eq.

[0237] Therefore, the Fermi-Dirac distribution in Equation (1) is approximated by the Boltzmann distribution equation shown by the following equation .

[0238]

Eq.

[0239] Using Equation (3), the intrinsic carrier density (n i ) of the semiconductor is calculated to obtain the following equation.

[0240]

Eq.

[0241] Then, the effective density of states (Nc , Nv) and the band gap (Eg) values of Si and In-Ga-Zn-O-based oxide semiconductors were substituted into Equation (4) to calculate the intrinsic carrier density. The results are shown in Table 1.

[0242]

Table 1

[0243] The In-Ga-Zn-O-based oxide semiconductor has an extremely low intrinsic carrier density compared to Si. This can be understood. When 3.05 eV is selected as the bandgap of the In-Ga-Zn-O-based oxide semiconductor, assuming that the Fermi-Dirac distribution law is approximately correct for the intrinsic carrier density in both Si and the In-Ga-Zn-O-based oxide semiconductor, it can be said that the carrier density of the former is about 10 times greater than that of the latter. 17 Next, a method for measuring the off-current of a transistor having a highly purified oxide semiconductor film and the results thereof will be described.

[0244] The results will be described.

[0245] Fig. 18 shows the configuration of the measurement circuit used in the actual measurement. The measurement circuit shown in Fig. 18 uses a transistor having a highly purified oxide semiconductor film as a switching element for holding the charge of the holding capacitor, and measures the off-current of the above-described transistor from the change in the amount of charge per unit time of the holding capacitor. Specifically, the measurement circuit shown in Fig. 18 has a configuration in which three measurement systems 801-

[0246] 1 to measurement system 801-3 for measuring the off-current are connected in parallel. And measurement systems 801- 1 to measurement system 801-3 each have a capacitor element 802 and a transistor 803 to be measured. Furthermore, measurement systems 801-1 to measurement system 801-3 each have transistors 804 to transistor 806.

[0247] ​​In each measurement system, the gate electrode of transistor 803 is connected to the node to which the potential Vgb is applied. Also, the source electrode of transistor 803 is connected to the node to which the potential Vb is applied, and the drain electrode is connected to node A. Also, the gate electrode of transistor 804 is connected to the node to which the potential Vga is applied. Also, the trans istor 804 has its source electrode connected to node A and its drain electrode connected to the node to which the potential Va is applied. Also, the gate electrode and the drain electrode of transistor 805 are connected to the node to which the potential Va is applied. Also, the gate electrode of transistor 806 is connected to node A, and transistor 806 has its source electrode connected to the node to which the potential Vb is applied. Then, the source electrode of transistor 805 and the drain electrode of transistor 806 are connected, and the potentials of these two electrodes are output from each measurement system as potential Vout1 ~ potential Vout3. The pair of electrodes of capacitive element 802 is such that one is connected to node A and the other is connected to the node to which the potential Vb is applied. Also, in this embodiment, the transistor 803 to be measured uses an oxide semiconductor film with a high-purity film thickness of 30 nm and a gate insulating film with a film thickness of 100 nm. And the channel formation region of transistor 803 has a channel length L = 10 μm and a channel width W = 50 μ m. Also, the capacitance values of the capacitive elements 802 in each measurement system are 100 fF, 1 pF, and 3 pF, respectively.

[0248] Before measurement, initialization is performed. First, the potential Vgb is set such that transistor 803 is turned on. m. Also, the capacitance values of the capacitive elements 802 in each measurement system are 100 fF, 1 pF, and 3 pF, respectively.

[0249] Before measurement, initialization is performed. First, the potential Vgb is set such that transistor 803 is turned on. Set it to the height. As a result, the transistor 803 turns on, and the potential V b, that is, the low-level potential VSS is applied to node A. Then, by setting the potential Vgb to a height such that the transistor 803 turns off, the transistor 803 is turned off. Next, set the potential Vga to a height such that the transistor 804 turns on. As a result of this, the potential Va, that is, the high-level potential VDD, is applied to node A, and between the pair of electrodes of the capacitive element 8 02, the potential difference between the low-level potential VSS and the high-level potential VDD is applied. Then, by setting the height of the potential Vga to a height such that the transistor 804 turns off , the transistor 804 turns off and node A becomes a floating state.

[0250] Next, move on to the measurement operation. When performing the measurement, set the potential Va and the potential Vb to heights such that charge flows into or out of node A. In this embodiment , the potential Va and the potential Vb are set to the low-level potential VSS. Note that at the timing of measuring the potential Vout , the potential Va is temporarily set to the high-level potential VDD, but otherwise the potential Va and the potential Vb are maintained at the low-level potential VSS.

[0251] Since a minute off-current flows through the transistor 803, the amount of charge held in node A varies with the passage of time. And as the amount of charge held in node A varies, the potential of node A varies, so the potentials Vout1 to Vout3 change in height according to the value of the off-current of the transistor 803.

[0252] Specifically, in this measurement, the potential VDD was set to 5V and the potential VSS was set to 0V. And during the measurement the potential Va was basically set to the potential VSS, and every 10 to 300 seconds, for a period of 100 mse c, the potential Va was set to the potential VDD, and the potentials Vout1 to Vout3 were measured .

[0253] Figure 19 shows the relationship between the elapsed time Time related to the above current measurement and the potential Vout. From about 90 seconds, the state of the potential change can be confirmed.

[0254] In advance, by obtaining the relationship between the potential V A of node A and the potential Vout, it is possible to obtain the potential Vo ut and then obtain the potential V A of node A. Generally, the potential V A of node A can be expressed as a function of the potential Vout as shown in the following equation.

[0255]

Equation

[0256] Also, the charge Q A of node A is expressed as follows using the potential V A of node A, the capacitance C A connected to node A, and a constant (const). Here, the capacitance C connected to node A A is the sum of the capacitance value of the capacitance element 802 and other capacitances (such as the input capacitance of the circuit composed of the transistors 805 and 80 6).

[0257]

Equation

[0258] The current I of node A is the time derivative of the charge flowing into node A (or the charge flowing out of node A). Therefore, the current I of node A is expressed as follows. Thus, the current I of node A can be obtained from the capacitance C connected to node A

[0259] [Number]

[0260] and the potentials Vout1 to Vout3. A As described above, the current I of node A can be obtained. FIG. 20 shows the off-current calculated by the above measurement. The Δt used for calculating the current I flowing through the transistor 803 was set to about 30000 sec. Note that FIG. 20 shows the relationship between the source

[0261] electrode-drain electrode voltage V and the off-current I. From FIG. 20, it can be seen that the off-current is about 40 zA / μm under the condition that the source electrode-drain electrode voltage is 4V.

[0262] Thus, by purifying the oxide semiconductor film so that impurities such as moisture or hydrogen other than the main component of the oxide semiconductor are not contained as much as possible, the operation of the transistor can be improved.

[0263] This embodiment can be implemented in appropriate combination with the above embodiment.

[0264] (Embodiment 4) In this embodiment, an example of a belt-shaped storage medium, which is one of the semiconductor devices using the storage device according to one aspect of the present invention, will be described.

[0265] FIG. 16(A) shows, as an example, the configuration of the storage medium according to one aspect of the present invention. FIG. 16(​​​​​​ The storage medium shown in A) is a storage device 701 according to one embodiment of the present invention, a drive device, and a storage medium. A connector 702 for electrical connection and a connector 703 for various signals input and output via the connector 702 , an interface 703 that processes signals according to the specifications, and an interface 704 that processes signals according to the operating state of the storage medium, etc. Therefore, the light emitting diode 704 is turned on, and the memory device 701, the interface 703, the light emitting diode 704 ... A controller that controls the operation of various circuits and semiconductor elements in the storage medium, such as a photodiode 704. A roller 705 is mounted on a printed wiring board 706. In addition, a controller A quartz crystal used to generate a clock signal to control the operation of the 705, memory A regulator for controlling the level of the power supply voltage in the medium may be provided. stomach.

[0266] The printed wiring board 706 shown in FIG. 16(A) is provided with a connector 7 as shown in FIG. The cover 707 is made of resin or the like so that the 02 and the light emitting diode 704 are partially exposed. It is also possible to provide protection by doing so.

[0267] The memory device 701 according to one embodiment of the present invention is capable of suppressing power consumption during operation. This allows for lower power consumption of the storage medium using the storage device 701, and ultimately reduces the power consumption of the storage medium. It is possible to reduce the power consumption of a driving device connected to the driving device. The storage device 701 is capable of storing data for a long period of time and is also capable of writing data. Since the number of times the data can be changed can be increased, the reliability of the storage medium can be improved. It is possible to retain data for a long period of time and increase the number of times data can be rewritten. This loosens the constraints on the operating conditions of the storage media, making it possible to increase the versatility of the storage media. It is.

[0268] This embodiment can be implemented in appropriate combination with the above embodiment.

Example

[0269] By using the semiconductor device according to one aspect of the present invention, it is possible to provide an electronic device with high reliability, low power consumption, and high-speed driving. Especially in the case of portable electronic devices where it is difficult to constantly receive power supply, by adding the semiconductor device with low power consumption according to one aspect of the present invention to its components, merits such as a longer continuous usage time can be obtained. It is possible to provide an electronic device with low power consumption, and high-speed driving. Especially in the case of portable electronic devices where it is difficult to constantly receive power supply, by adding the semiconductor device with low power consumption according to one aspect of the present invention to its components, merits such as a longer continuous usage time can be obtained. In the case of portable electronic devices where it is difficult to constantly receive power supply, by adding the semiconductor device with low power consumption according to one aspect of the present invention to its components, merits such as a longer continuous usage time can be obtained. By adding the semiconductor device with low power consumption according to one aspect of the present invention to its components, merits such as a longer continuous usage time can be obtained. It can be obtained.

[0270] Also, in the semiconductor device of the present invention, since the temperature of the heat treatment in the manufacturing process can be suppressed, even on a flexible synthetic resin substrate such as plastic that has inferior heat resistance to glass, it is possible to fabricate transistors with excellent characteristics and high reliability. Therefore, by using the manufacturing method according to one aspect of the present invention, it is possible to provide a highly reliable, lightweight, and flexible semiconductor device. Examples of plastic substrates include polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. Also, in the semiconductor device of the present invention, since the temperature of the heat treatment in the manufacturing process can be suppressed, even on a flexible synthetic resin substrate such as plastic that has inferior heat resistance to glass, it is possible to fabricate transistors with excellent characteristics and high reliability. Therefore, by using the manufacturing method according to one aspect of the present invention, it is possible to provide a highly reliable, lightweight, and flexible semiconductor device. Therefore, by using the manufacturing method according to one aspect of the present invention, it is possible to provide a highly reliable, lightweight, and flexible semiconductor device. As plastic substrates, polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like can be mentioned. Examples of plastic substrates include polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. I), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. Examples of plastic substrates include polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like. Examples of plastic substrates include polyesters represented by polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), polyetheretherketone (PEEK), polysulfone (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide, acrylonitrile-butadiene-styrene resin, polyvinyl chloride, polypropylene, polyvinyl acetate, acrylic resin, and the like.

[0271] A semiconductor device according to an aspect of the present invention can be used in a display device, a notebook personal computer, an image playback device having a recording medium (typically a device having a display capable of playing a recording medium such as a DVD: Digital Versatile Disc and displaying its image). In addition, as electronic devices in which a semiconductor device according to an aspect of the present invention can be used, there are a mobile phone, a portable game machine, a portable information terminal, an electronic book, a video camera, a digital still camera, a goggle type display (head-mounted display), a navigation system, an audio playback device (car audio, digital audio player, etc.), a copying machine, a facsimile machine, a printer, a printer multifunction device, an automated teller machine (ATM), a vending machine, and the like. Specific examples of these electronic devices are shown in FIG. 17.

[0272] FIG. 17(A) shows a portable game machine, which has a housing 7031, a housing 7032, a display unit 7033, a display unit 7034, a microphone 7035, a speaker 7036, operation keys 7037, a start button 7038, and the like. A semiconductor device according to an aspect of the present invention can be used in an integrated circuit for controlling the drive of a portable game machine. By using a semiconductor device according to an aspect of the present invention in an integrated circuit for controlling the drive of a portable game machine, a highly reliable portable game machine, a portable game machine with low power consumption, a portable game machine with high-speed drive, and a high-performance portable game machine can be provided. Note that the portable game machine shown in FIG. 17(A) has two display units 7033 and 7034, but the number of display units included in the portable game machine is not limited to this.

[0273] ​​​​​​​​​​​​​​​​FIG. 17(B) is a mobile phone, which includes a housing 7041, a display unit 7042, a voice input unit 7043, a voice output unit 7044, operation keys 7045, a light receiving unit 7046, etc. By converting the light received by the light receiving unit 7046 into an electrical signal, an external image can be captured. A semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of a mobile phone. By using the semiconductor device according to one aspect of the present invention for an integrated circuit for controlling the driving of a mobile phone, a mobile phone with high reliability, a mobile phone with low power consumption, a mobile phone with high-speed driving, and a

[0274] high-function mobile phone can be provided.

[0274] FIG. 17(C) is a portable information terminal, which includes a housing 7051, a display unit 7052, operation keys 7053, etc. In the portable information terminal shown in FIG. 17(C), a modem may be built in the housing 7051. A semiconductor device according to one aspect of the present invention can be used for an integrated circuit for controlling the driving of a portable information terminal. By using the semiconductor device according to one aspect of the present invention for an integrated circuit for controlling the driving of a portable information terminal, a portable information terminal with high

[0275] reliability, a portable information terminal with low power consumption, a portable information terminal

[0275] with high-speed driving, and a high-function portable information terminal can be provided. This embodiment can be implemented in appropriate combination with the above-described embodiments.

Description of Reference Numerals

[0276] 100 Memory cell 101 Transistor 102 Transistor 103 Capacitor element 110 Substrate 111 Gate electrode 112 Insulating film 113 Oxide semiconductor film 114 Source electrode 115 Drain electrode 116 Insulating film 117 Insulating film 121 Gate electrode 123 Oxide semiconductor film 124 Source electrode 125 Drain electrode 126 Gate electrode 130 Line 131 Line 140 Substrate 141 Gate electrode 142 Insulating film 143 Oxide semiconductor film 144 Source electrode 145 Drain electrode 146 Insulating film 147 Insulating film 148 Channel protection film 151 Gate electrode 153 Oxide semiconductor film 154 Source electrode 155 Drain electrode 156 Gate electrode 157 Channel protection film 160 Substrate 161 Gate electrode 162 Insulating film 163 Oxide semiconductor film 164 Source electrode 165 Drain electrode 166 Insulating film 167 Insulating film 171 Gate electrode 173 Oxide semiconductor film 174 Source electrode 175 Drain electrode 176 Gate electrode 200 Substrate 208 Oxide semiconductor film 211 Gate electrode 212 Insulating film 213 Oxide semiconductor film 214 Source electrode 215 Drain electrode 216 Insulating film 217 Insulating film 221 Gate electrode 223 Semiconductor film 224 Source electrode 225 Drain electrode 226 Gate electrode 230 Insulating film 231 Insulating film 241 Gate electrode 242 Insulating film 243 Oxide semiconductor film 244 Source electrode 245 Drain electrode 246 Insulating film 247 Insulating film 251 Gate electrode 253 Semiconductor film 254 Source electrode 255 Drain electrode 256 Gate electrode 260 Insulating film 261 Insulating film 270 Substrate 300 Memory cell 301 Transistor 302 Transistor 303 Capacitor element 304 Power supply line 310_1 Transistor 310_2 Transistor 310_3 Transistor 311_1 Transistor 311_2 Transistor 311_3 Transistor 312_1 Operational amplifier 312_2 Operational amplifier 312_3 Operational amplifier 320 Transistor 321 Transistor 400 Substrate 401 Gate electrode 402 Gate electrode 403 Gate insulating film 404 Oxide semiconductor film 405 Oxide semiconductor film 406 Oxide semiconductor film 407 Source electrode 408 Drain electrode 409 Source electrode 410 Drain electrode 411 Insulating film 412 Contact hole 413 Back gate electrode 414 Insulating film 420 Transistor 421 Transistor 430 Capacitor element 500 Cell array 501 Driving circuit 502 Readout circuit 503 Word line driving circuit 504 Data line driving circuit 505 Control circuit 506 Decoder for word line 508 Decoder for data line 509 Selector for data line 701 Memory device 702 Connector 703 Interface 704 Light emitting diode 705 Controller 706 Printed wiring board 707 Cover material 801-1 Measuring system 801-2 Measuring system 801-3 Measuring system 802 Capacitor element 803 Transistor 804 Transistor 805 Transistor 806 Transistor 7031 Housing 7032 Housing 7033 Display unit 7034 Display unit 7035 Microphone 7036 Speaker 7037 Operation key 7038 Stylus 7041 Housing 7042 Display Unit 7043 Voice Input Unit 7044 Voice Output Unit 7045 Operation Key 7046 Light Receiving Unit 7051 Housing 7052 Display Unit 7053 Operation Key

Claims

1. A first transistor having a channel formation region including an oxide semiconductor, a second transistor having a channel formation region including an oxide semiconductor, and a capacitor element, wherein the first transistor has a first oxide semiconductor layer, a first conductive layer having a region located below the first oxide semiconductor layer and functioning as a first gate electrode, a second conductive layer having a region located above the first oxide semiconductor layer and functioning as a second gate electrode, a third conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode, and a fourth conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode, the second conductive layer is electrically connected to a fifth conductive layer having a region functioning as one of the source electrode and the drain electrode of the second transistor, in the channel length direction of the first transistor, the second conductive layer has a region having a length greater than the length of the first oxide semiconductor layer, the third conductive layer has a first region overlapping the first oxide semiconductor layer and a second region not overlapping the first oxide semiconductor layer, the second conductive layer has a third region overlapping the second region, the second region functions as a first electrode of the capacitor element, and the third region functions as a second electrode of the capacitor element, a semiconductor device.

2. A first transistor having a channel formation region including an oxide semiconductor, a second transistor having a channel formation region including an oxide semiconductor, and a capacitor element, wherein the first transistor has a first oxide semiconductor layer, a first conductive layer having a region located below the first oxide semiconductor layer and functioning as a first gate electrode, a second conductive layer having a region located above the first oxide semiconductor layer and functioning as a second gate electrode, a third conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and functioning as one of a source electrode and a drain electrode, and a fourth conductive layer having a region in contact with the upper surface of the first oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode, The second conductive layer is electrically connected to a fifth conductive layer having a region that functions as one of the source electrode and the drain electrode of the second transistor. In the channel length direction of the first transistor, the second conductive layer has a region having a length greater than the length of the first oxide semiconductor layer. The third conductive layer has a first region overlapping the first oxide semiconductor layer and a second region not overlapping the first oxide semiconductor layer. The second conductive layer has a third region overlapping the second region. The second region functions as the first electrode of the capacitor element. The third region functions as the second electrode of the capacitor element. In the channel length direction of the first transistor, the second region has a region having a length greater than the length of the first region, a semiconductor device.

3. In claim 1 or 2, A semiconductor device in which the channel formation region of the first transistor and the channel formation region of the second transistor have an oxide semiconductor containing In, Ga, and Zn.

4. In any one of claims 1 to 3. A semiconductor device in which data having three or more values is supplied to a sixth conductive layer having a region that functions as the other of the source electrode and the drain electrode of the second transistor.

5. In any one of claims 1 to 3. A semiconductor device in which a signal is supplied to a sixth conductive layer having a region that functions as the other of the source electrode and the drain electrode of the second transistor.

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