Method and apparatus for digitally controlling the ion energy distribution in a plasma

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generating a waveform for plasma processing of a substrate in a processing chamber.Embodiments of the present disclosure include an apparatus and method for generating a pseudo-staircase voltage waveform, including coupling a first voltage supply to an output node during a first stage of generating the waveform, coupling a first capacitor between the output node and an electrical ground node during a second stage of generating the waveform, and coupling the first capacitor and a second capacitor in a series path between the output node and an electrical ground node during a third stage of generating the waveform.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. In particular, embodiments of the present disclosure relate to plasma processing systems used to process substrates.

Background Art

[0002]

[0002] Reliably generating high aspect ratio features is one of the important technical challenges for next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process. In that case, plasma is generated within a processing chamber, ions from the plasma are accelerated toward the surface of the substrate, and openings are formed in a material layer disposed below a mask layer formed on the surface of the substrate.

[0003]

[0003] In a typical plasma-assisted etching process, a substrate is disposed on a substrate support disposed within a processing chamber, plasma is generated above the substrate, and ions are accelerated from the plasma across a plasma sheath (i.e., a region depleted of electrons generated between the plasma and the surface of the substrate) toward the substrate.

[0004]

[0004] Conventional radio frequency (RF) plasma-assisted etching processes simply supply a sine wave including an RF signal to one or more of the electrodes within a plasma processing chamber and cannot adequately or desirably control sheath characteristics and the generated ion energy, which has been found to lead to undesirable plasma processing results. Undesirable processing results can include excessive sputtering of the mask layer and the occurrence of sidewall defects within high aspect ratio features.

[0005]

[0005] Accordingly, there is a need in the art for plasma processing and biasing methods that can provide desired plasma-assisted etching process results.

Summary of the Invention

[0006]

[0006] Multiple embodiments provided in this specification generally include an apparatus, a plasma processing system, and a method for generating a waveform (e.g., a pseudo-staircase voltage waveform) for plasma processing a substrate within a processing chamber.

[0007]

[0007] Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage source, a first switch coupled between the first voltage source and the output node of the waveform generator, a second switch, and a capacitor array. In that case, the second switch is coupled between the output node and the capacitor array. The capacitor array includes a first capacitor coupled to the second switch, a third switch coupled between the first capacitor and the electrical ground node, a second capacitor selectively coupled to a node between the first capacitor and the third switch, and a fourth switch coupled between the second capacitor and the electrical ground node.

[0008]

[0008] Some embodiments are directed to a method for waveform generation. The method generally includes coupling a first voltage source to an output node during a first stage of generating a waveform, coupling a first capacitor between the output node and the electrical ground node during a second stage of generating a waveform, and coupling the first capacitor and the second capacitor in series between the output node and the electrical ground node during a third stage of generating a waveform.

[0009]

[0009] Some embodiments are directed to an apparatus for waveform generation. The apparatus generally includes a memory and one or more processors coupled to the memory. The memory and the one or more processors are configured to execute coupling a first voltage source to an output node during a first stage of generating a waveform, coupling a first capacitor between the output node and the electrical ground node during a second stage of generating a waveform, and coupling the first capacitor and the second capacitor in series between the output node and the electrical ground node during a third stage of generating a waveform.

[0010]

[0010] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, can be provided by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate exemplary embodiments and should not be considered as limiting the scope of the present disclosure, and other equally valid embodiments may be acceptable.

Brief Description of the Drawings

[0011]

Figure 1

[0011] It is a schematic cross-sectional view of a processing system according to one or more embodiments configured to implement the methods described herein.

Figure 2A

[0012] It shows a voltage waveform that can be applied to the electrodes of a processing chamber according to one or more embodiments.

Figure 2B

[0013] It shows a voltage waveform established on a substrate due to the voltage waveform applied to the electrodes of the processing chamber.

Figure 3A

[0014] It shows a typical ion energy distribution (IED) when using an excitation waveform of a single frequency.

Figure 3B

[0015] It is a graph showing an IED function (IEDF) according to certain aspects of the present disclosure.

Figure 4

[0016] It shows a pseudo-step voltage waveform generated using a waveform generator according to certain embodiments of the present disclosure.

Figure 5

[0017] It shows an exemplary embodiment of a waveform generator for digital control of IED according to certain aspects of the present disclosure.

Figure 6

[0018] It is a timing diagram showing the state of the switches of the waveform generator of FIG. 5 according to certain aspects of the present disclosure.

Figure 7

[0019] A process flow diagram showing a method for waveform generation according to certain aspects of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0020] As technology nodes progress towards 2nm, the fabrication of smaller features with higher aspect ratios requires atomic precision for plasma processing. In etching processes where plasma ions play a major role, ion energy control is difficult for the semiconductor device industry. Conventional radio frequency (RF) bias techniques use sinusoidal waves to excite the plasma and accelerate the ions that interact with the surface of the substrate.

[0013]

[0021] Some embodiments of the present disclosure generally relate to techniques for generating a pseudo-staircase voltage waveform for controlling the ion energy distribution (IED) in a plasma. For example, the techniques described herein may enable digital control of the IED. In that case, a network of capacitors (e.g., external to an integrated circuit), switches, and a direct current (DC) power supply is used to generate a pseudo-staircase voltage waveform and maintain a negative voltage on an electrode (such as an electrode within an electrostatic chuck) within a plasma processing system. This is when the substrate disposed on the electrode is being discharged by a positive ion current from the plasma. The process of maintaining a constant negative voltage on the electrode while the substrate is being discharged by a positive ion current is called current compensation. This technique may provide precise control of the IED by generating multiple ion energy peaks via digital commands from a process chamber controller.

[0014]

[0022] The techniques described herein offer several advantages over conventional methods for ion energy control. For example, while some conventional methods enable the generation of a single energy peak, the techniques described herein can generate multiple ion energy peaks that can be adjusted to meet specifications. Further, while some conventional methods use an external current source to perform current compensation, several embodiments of the present disclosure perform current compensation without using an external current source, reducing the hardware area consumption. The techniques described herein may also enable the etching of different materials with higher selectivity and the deposition of films with improved film characteristics. Additionally, the techniques described herein can generate a substrate bias in a processing chamber with poor return of high-frequency (RF) current by operating in a periodic transient regime.

[0015] Multiple embodiments of a plasma processing system

[0023] FIG. 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plurality of plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as reactive ion etching (RIE) plasma processing. However, note that the plurality of embodiments described herein may also be used with a processing system configured to be used in other plasma-assisted processes, such as a plasma deposition process, e.g., a plasma enhanced chemical vapor deposition (PECVD) process, a plasma physical vapor deposition (PEPVD) process, a plasma atomic layer deposition (PEALD) process, a plasma treatment process, or a plasma-based ion implantation process (e.g., a plasma doping (PLAD) process).

[0016]

[0024] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP). In that case, the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within the processing space 129. The upper electrode also faces a lower electrode (e.g., substrate support assembly 136) disposed within the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes and supplies an RF signal configured to ignite and maintain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and is disposed within the processing region therebetween. Typically, the other of the upper or lower electrodes is coupled to ground or a second RF power source. One or more components of the substrate support assembly 136, such as the support base 107, are electrically coupled to the plasma generator assembly 163. The plasma generator assembly 163 includes the RF generator 118, and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, a support assembly 136, and a system controller 126.

[0017]

[0025] The processing chamber 100 typically includes a chamber body 113. The chamber body 113 includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124. Together, they define the processing space 129. The one or more sidewalls 122 and the chamber base 124 are generally sized and shaped from a material configured to form a structural support for the elements of the processing chamber 100 and to withstand the pressures and additional energies applied thereto. On the other hand, the plasma 101 is generated within a reduced pressure environment maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more sidewalls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0018]

[0026] The gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases from a process gas source 119 in fluid communication with the processing space 129 to the processing space 129. The substrate 103 is loaded into and removed from the processing space 129 through an opening (not shown) within one of the one or more sidewalls 122. The opening is sealed by a slit valve (not shown) during plasma processing of the substrate 103.

[0019]

[0027] The system controller 126, also referred to herein as the process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence (including the substrate biasing method described herein) used to process the substrate 103. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the processing chamber and associated sub-processors. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuitry 135 is conventionally coupled to the CPU 133 and includes cache, clock circuitry, input / output subsystems, power supplies, etc., and combinations thereof. Software instruction commands (programs) and data may be encoded to instruct the processor within the CPU 133 and stored in the memory 134. Software programs (or computer instruction commands) readable by the CPU 133 within the system controller 126 specify which operations are executable by the components within the processing system 10.

[0020]

[0028] Typically, the program is readable by the CPU 133 within the system controller 126 and includes code. When executed by the processor (CPU 133), the code performs operations related to the plasma processing scheme described herein. The program may include instruction commands. The instruction commands are used to control various hardware and electrical components within the processing system 10. Thereby, various process operations and various process sequences used to implement the methods described herein are performed. In one embodiment, the program includes instruction commands used to perform one or more of the operations described below in relation to FIGS. 4-7.

[0021]

[0029] The processing system may include a plasma generator assembly 163, a first PV source assembly 196 for establishing a first pulse voltage (PV) waveform at the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at the edge control electrode 115. The first PV waveform or the second PV waveform may be generated using a waveform generator as described in more detail herein with respect to FIGS. 4, 5, and 6. In some embodiments, the plasma generator assembly 163 supplies an RF signal to the support base 107 (e.g., an electrode or a cathode). The support base 107 may be used to generate (maintain and / or ignite) the plasma 101 within the processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency of 1 MHz or more, or about 2 MHz or more, such as about 13.56 MHz or more.

[0022]

[0030] As described above, in some embodiments, the plasma generator assembly 163 includes the RF generator 118 and the RF generator assembly 160 and is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially constant sinusoidal waveform frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107 disposed proximate to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain a processing plasma 101 of a processing gas disposed within the processing space 129.

[0023]

[0031] In some embodiments, the support base 107 is an RF electrode electrically coupled to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are disposed within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator PG1 within the PV waveform generator 150 and thus blocks the flow of current to the RF matching circuit 162 and the RF generator 118.

[0024]

[0032] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and sustain the processing plasma 101 using the processing gas disposed within the processing space 129 and the electric field generated by the RF power (RF signal) supplied by the RF generator 118 to the support base 107. The processing space 129 is fluidly coupled to one or more dedicated vacuum pumps via the vacuum outlet 120. The one or more dedicated vacuum pumps maintain the processing space 129 at a near-atmospheric pressure state and exhaust the processing gas and / or other gases from the processing space 129. In some embodiments, the substrate support assembly 136 disposed within the processing space 129 is disposed on a support shaft 138 that is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 disposed within the substrate support 105 relative to the support base 107.

[0025]

[0033] As briefly described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, as further described below. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is inserted between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and is disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0026]

[0034] Typically, the substrate support 105 is formed of a dielectric material (e.g., a bulk sintered ceramic material such as a corrosion-resistant metal oxide material or a metal nitride material), which is, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In multiple embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded within the dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 within the processing region above the bias electrode 104 are identified and / or monitored by measuring the RF waveform established at the bias electrode 104.

[0027]

[0035] In one configuration, the bias electrode 104 is a chucking pole used to fix (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 relative to the processing plasma 101 using one or more of the pulse voltage bias schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components such as one or more metal meshes, foils, plates, or combinations thereof.

[0028]

[0036] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116. The clamping network 116 uses an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable) to provide a clamping voltage, such as a static DC voltage between approximately -5000V and approximately 5000V, to the bias electrode 104. As further described below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor, also referred to herein as blocking capacitor C5. The blocking capacitor C5 is disposed between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0029]

[0037] The substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is disposed at a distance from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit substrate, the edge control electrode 115 is annular, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments as shown in FIG. 1, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed at a distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 that is similar to the bias electrode 104. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed on or within the region of the quartz tube 110. The quartz tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN, etc.).

[0030]

[0038] The edge control electrode 115 can be biased using a PV waveform generator different from the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased using the PV waveform generator 150 that is also used to bias the bias electrode 104. This is by splitting a portion of the power to the edge control electrode 115. In one configuration, the first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, and the second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115.

[0031]

[0039] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to the optional filter assembly 151 and the bias electrode 104. In the following description, the power supply line 157 of the first PV source assembly 196 used mainly to couple the PV waveform generator 150 to the bias electrode 104 will be described. However, the voltage supply line 158 of the second PV source assembly 197 that couples the PV waveform generator 150 to the edge control electrode 115 will include the same or similar components. The (one or more) electrical conductors in the various portions of the voltage supply line 157 include the following. That is, (a) one or a combination of coaxial cables such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated wire for a high voltage corona resistant circuit, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). The optional filter assembly 151 includes one or more electrical elements configured to substantially prevent the current generated by the output of the RF generator 118 from flowing through the power supply line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, and thus blocks the flow of current to the PV waveform generator 150.

[0032]

[0040] The second PV source assembly 197 includes a clamping network 116. Thereby, the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamping network 116 coupled within the first PV source assembly 196. Applying similarly configured PV waveforms and clamping voltages to the bias electrode 104 and the edge control electrode 115 helps to improve the uniformity of the plasma across the surface of the substrate being processed, and thus the results of the plasma processing process can be improved.

[0033]

[0041] In some embodiments, the processing chamber 100 further includes a quartz tube 110 or a collar. They at least partially circumscribe a portion of the substrate support assembly 136 to prevent the substrate support 105 and / or the support base 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz tube 110, the insulator plate 111, and the ground plate 112 are circumscribed by the liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma from being generated in the space below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0034]

[0042] FIG. 2A shows a voltage waveform that can be established at the electrodes of the processing chamber. FIG. 2B shows an example of different types of voltage waveforms 225 and 230 established at the substrate due to different voltage waveforms similar to the voltage waveform shown in FIG. 2A established separately at the electrodes (e.g., bias electrode 104) within the processing chamber. The waveforms include two stages, namely the ion current stage 205 and the sheath collapse stage 210, as illustrated. At the start of the ion current stage 205, a drop in the substrate voltage creates a high-voltage sheath above the substrate and accelerates positive ions towards the substrate. The positive ions that strike the surface of the substrate during the ion current stage 205 deposit positive charge on the substrate surface, which, if uncompensated, gradually increases the substrate voltage in the positive direction during the ion current stage 205, as shown by the voltage waveform 225 in FIG. 2B. However, the uncontrolled accumulation of positive charge on the substrate surface undesirably gradually discharges the sheath and the chuck capacitor, slowly reducing the sheath voltage drop and bringing the substrate potential closer to zero, as illustrated by the voltage waveform 225. The accumulation of positive charge results in a voltage drop (i.e., the voltage becomes less negative) within the voltage waveform established at the substrate surface (FIG. 2B). However, as shown in FIG. 2A, the voltage waveform established at the electrode with a negative slope during the ion current stage 205 can be generated to establish a square-shaped region (e.g., a slope close to zero) with respect to the substrate voltage waveform to be established, as shown by the voltage waveform 230 in FIG. 2B. Implementing the slope within the waveform established at the electrode during the ion current stage 205 can be referred to as current compensation. The voltage difference between the start and the end of the ion current stage 205 determines the width of the ion energy distribution function (IEDF). The larger the voltage difference, the wider the IEDF width. To achieve ions of a single energy and a narrower IEDF width, an operation is performed using current compensation to flatten the substrate voltage waveform during the ion current stage 205.

[0035] Generation techniques for waveform generation

[0043] Some embodiments of the present disclosure generally relate to techniques for generating a pseudo-step voltage waveform for controlling the ion energy distribution (IED) in a plasma. For example, this technique may include using a network of external storage capacitors and switches that are charged and discharged in a periodic transient mode to achieve a desired pulse waveform that generates a desired IED at the surface of a substrate.

[0036]

[0044] FIG. 3A shows a typical IED when using a single high-frequency (RF) frequency excitation waveform. As shown, the IED has a bimodal shape with a high-energy peak 306, a low-energy peak 302, and ions of intermediate energy (e.g., associated with the intermediate energy region 304). When viewed from the side of a plasma etching process, only the ions at or near the high-energy peak have the energy and directionality to overcome the ion generation charging effect occurring within the material being etched and reach the bottom of the feature to enable an etching reaction. Ions with intermediate energy are not beneficial to the etching process. This is because such ions are non-directional and tend to collide with the sidewalls of the feature, often resulting in an undesirable IED that induces a bow-shaped profile of the feature. Low-energy ions are important for the etching process as they clean the mask surface, maintain the shape of the mask layer, and prevent clogging of the holes. Some embodiments of the present disclosure provide techniques that enable the manipulation of the IED from a broad IED to a narrow IED (gathered around any desired value).

[0037]

[0045] Figure 3B is a graph showing an IED function (IEDF) according to certain aspects of the present disclosure. The IEDF includes multiple high energy peaks such as a first energy peak 301, a second energy peak 303, and a third energy peak 305. As shown, the energy associated with the first energy peak 301 is slightly lower than the energy associated with the second energy peak 303, and the energy associated with the second energy peak 303 is slightly lower than the energy associated with the third energy peak 305. The narrow energy distribution and multiple IED peaks can be useful in forming features on the surface of a substrate with desired atomic precision. Ions associated with the third energy peak 305 (or high energy peak) are generally configured to reach the bottom of the highly etched aspect ratio features and have the energy and directionality to enable an etching reaction. When viewed from the side of the plasma etching process, ions at or near the high energy peak are also generally configured to have the energy and directionality to overcome the ion generation charging effect that occurs within the material being etched. The first energy peak 301 (low energy peak) and / or the second energy peak 303 can be generated such that they do not have enough energy to reach the bottom of the feature during etching. However, the low and intermediate energies can still be useful in the etching process because these ion energies are important for the etching process as they clean the mask, maintain the shape of the mask layer, and prevent clogging of the holes.

[0038]

[0046] The IED can be affected based on the operation / closure of different switches of the waveform generator (e.g., the second switch (S2) 512, the seventh switch (S7) 524, and / or the eighth switch (S8) 526 of the waveform generator 500, which will be described in more detail with respect to FIG. 5). The techniques described herein enable control of each switch and control of the closure duration of each switch, affecting the IED. By controlling the switches, the IED shown in FIG. 3B can be implemented using the pseudo-stair voltage waveform 400, as described in more detail herein.

[0039]

[0047] FIG. 4 shows a pseudo-stair voltage waveform 400 generated using a waveform generator (e.g., the waveform generator 500 shown in FIG. 5) according to certain embodiments of the present disclosure. In some embodiments, the waveform generator 500 forms at least a portion of the pulse waveform generator 150 of the first PV source assembly 196, and / or the waveform generator 500 forms at least a portion of the pulse waveform generator 150 of the second PV source assembly 197. The pseudo-stair voltage waveform 400 is applied to bias the wafer to implement a particular IED. The pulse repetition frequency of the pseudo-stair voltage waveform 400 can vary between several tens of kHz to several hundreds of kHz, e.g., between 50 kHz and 800 kHz, e.g., between 100 kHz and 400 kHz. The pseudo-stair voltage waveform 400 can be divided into a plurality of steps of various durations in one waveform cycle.

[0040]

[0048] As shown, the pseudo-stair voltage waveform 400 includes waveform regions 401 and 405. The waveform region 401 (e.g., corresponding to the sheath collapse stage 210 of FIG. 2) includes a direct current (DC) signal, and the waveform region 405 (e.g., corresponding to the ion current stage 205 of FIG. 2) includes a voltage pseudo-stair that can be used for ion current compensation.

[0041]

[0049] During the middle of a part of the waveform region 401 within the pulse waveform cycle, the plasma bulk electrons are attracted to the surface of the substrate (for example, the substrate support surface 105A of the substrate 103 in FIG. 1). This is due to the rising edge 402 of the pseudo-step voltage waveform 400. And a positive voltage (V positve ) is established at the electrode. The substrate surface and the electrode (for example, the bias electrode 104 in FIG. 1) form a capacitive element (for example, an electrostatic chuck capacitor (C esc ). At this stage, an equal amount of positive charge at the electrode (compared to the negative charge of the substrate, for example) cancels out the electric field generated by the accumulation of electrons provided by the bulk plasma.

[0042]

[0050] At the falling edge 403 of the pseudo-step voltage waveform 400, the ions are neutralized by the electrons. This is due to the application of the pseudo-step voltage waveform 400 to the electrode. A negative voltage (-V0) is established at the electrode, and a negative DC sheath potential is established at the substrate surface. This is the origin of the higher energy peak (for example, the third energy peak 305 of the IEDF in FIG. 3B). The DC sheath potential, or the higher ion energy, can be approximated using the voltage drop (ΔV) at the falling edge 403 (for example, V positive +V0), and the ratio between C esc and the sheath capacitance (C sheath ). That is, V dc =-(V positive +V0)C esc / (C esc +C sheath ) Therefore, the waveform region 401 helps to maintain the plasma in the chamber and establish the DC sheath potential of the higher energy peak.

[0043]

[0051] When incident ions neutralize electrons on the substrate surface and positive charges accumulate on the substrate surface, in the absence of means for ion compensation (also called current compensation), the DC sheath potential decreases. As a result, the ions incident on the substrate surface become not of a single energy due to the change in the DC sheath potential. As an effort to compensate for the collection of positive charges on the substrate during the ion current stage seen within the waveform region 405, in some embodiments, a voltage pseudo-step is applied to the electrode to compensate for the change in the sheath potential, thereby maintaining a constant sheath potential V dc (single energy peak). In some embodiments, the voltage pseudo-step applied to the electrode in the waveform region 405 is divided into a plurality of sub-steps, and each sub-step has a duration Δt that is constant or can be varied between sub-steps.

[0044]

[0052] In a first sub-step 406 having a duration Δt, the total amount of positive charge ΔQ = I ion ×Δt accumulates on the substrate surface. Here, the ion current (I ion ) can be calculated as I sheath = C ion dV / dt based on the time derivative of the electrode voltage (V) and the sheath capacitance (C sheath ), and thus the DC sheath potential decreases by ΔQ / C sheath . To compensate for this change in the DC sheath potential, a voltage drop at the falling edge 407 of the pseudo-step voltage waveform 400 is applied (for example, as will be described in more detail with respect to FIG. 5, electrons are supplied to the electrode from a network of capacitors of the capacitor array based on the closing of the switch). The amount of the voltage drop applied during one or more of the sub-steps of the voltage pseudo-step can be determined from the known or measured ion current I ion generated during plasma processing. Thereby, the voltage pseudo-step tends to follow the desired ion compensation curve 413.

[0045]

[0053] In the second sub-step 408, a voltage of -2V0 is applied to the electrode. The voltage drop (e.g., associated with the falling edge 409) can be implemented by applying the voltage at the end of the second sub-step 408. In one embodiment, the voltage drop applied at the falling edge 409 has the same magnitude as the voltage drop applied at the falling edge 407, as described in more detail herein with respect to FIG. 5. After the falling edge 409, the third sub-step 410 begins. During that time, a voltage of -3V0 is applied to the substrate.

[0046]

[0054] During the falling edge 407 and the falling edge 409, the electrons supplied to the electrode (from one or more of the capacitors in the capacitor array) cancel out the electric field generated by the incident ions, thereby maintaining the DC sheath potential. As a result, a digital (depending on the switch state) cluster of ion energies near -(V positive + V0) volts is generated. One example shown in FIG. 4 includes three sub-steps 406, 408, 410 within the waveform region 405, but it should be noted that any number of sub-steps may be implemented within the waveform region 405.

[0047]

[0055] FIG. 5 shows an exemplary embodiment of a waveform generator 500 according to certain embodiments of the present disclosure. In some embodiments, the waveform generator 500 is configured to generate a pseudo-staircase voltage waveform 400 (of FIG. 4). The waveform 400 can be established at an electrode (e.g., the bias electrode 104 of FIG. 1) or a support base (the support base 107 of FIG. 1). The waveform generator 500 can be used to implement one or more of the waveform generation assemblies 150 described above with respect to FIG. 1.

[0048]

[0056] The waveform generator 500 includes voltage power supplies such as a first voltage supply 502 (e.g., a positive DC voltage source) and a second voltage supply 504 (e.g., a negative DC voltage source).

[0049]

[0057] The waveform generator 500 further includes capacitors (also referred to as pulse capacitance elements), such as a first capacitor (C1) 506, a second capacitor (C2) 508, and a third capacitor (C3) 510. The first capacitor 506, the second capacitor 508, and the third capacitor 510 can act as voltage storage elements that can be charged using a charging circuit.

[0050]

[0058] The waveform generator 500 further includes switches (e.g., transistors), such as a first switch (S1) 512, a second switch (S2) 514, a third switch (S3) 516, a fourth switch (S4) 518, a fifth switch (S5) 520, a sixth switch (S6) 522, a seventh switch (S7) 524, an eighth switch (S8) 526, and a ninth switch (S9) 528. The switch may be a power transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)). The switch may be a high voltage solid state relay. The switches can be used to select a current path (also referred to as an output current path) for the waveform generator 500.

[0051]

[0059] In certain embodiments, the first switch 512, the fifth switch 520, the sixth switch 522, and the ninth switch 528 operate in the same manner. For example, as will be described in more detail with respect to FIG. 6, the first switch 512, the fifth switch 520, the sixth switch 522, and the ninth switch 528 are opened and closed simultaneously.

[0052]

[0060] The first switch 512 is coupled between the first voltage supply source 502 and the output node 534. The second switch 514 is coupled between the output node 534 and the capacitor array. The capacitor array includes at least a first capacitor 506 and a second capacitor 508. The first capacitor 506 is coupled to the second switch 514. The second capacitor 508 is selectively coupled to a node 517 between the first capacitor 506 and the third switch 516. The third switch 516 is coupled between the first capacitor 506 and the electrical ground node. The fourth switch 518 is coupled between the second capacitor 508 and the electrical ground node.

[0053]

[0061] The capacitor array is connected to a charging circuit. The charging circuit includes a second voltage supply source 504 selectively coupled to each of the first capacitor 506 and the second capacitor 508. The charging circuit further includes a fifth switch 520 coupled between the second voltage supply source 504 and the first capacitor 506, and a sixth switch 522 coupled between the fifth switch 520 and the second capacitor 508. The seventh switch 524 is coupled to a node 517 between the first capacitor 506 and the third switch 516, and a node 519 between the second capacitor 508 and the sixth switch 522. The third capacitor 510 is selectively coupled to a node 521 between the second capacitor 508 and the fourth switch 518. The eighth switch 526 is coupled to a node 521 between the second capacitor 508 and the fourth switch 518, and a node 523 between the third capacitor 510 and the ninth switch 528.

[0054]

[0062] The waveform generator 500 is coupled to the plasma processing chamber via the output node 534. The plasma processing chamber has a floating capacitor (C stray ) 530 and an electrostatic chuck capacitor (C esc)It includes 532. The floating capacitor 530 represents the capacitance (capacitance) between the plasma processing chamber and the electrical ground node. As described above, the electrostatic chuck capacitor 532 represents the capacitance between the electrode (for example, the bias electrode 104 in FIG. 1) and the substrate surface (for example, the substrate support surface 105A in FIG. 1). The electrostatic chuck capacitor 532 is connected between the output node (U out )534 and the plasma load 536 (which may be the plasma generated in the plasma processing chamber). The plasma load 536 is represented by the sheath capacitor (C shealth )538 (representing the ion compensation current and the plasma sheath) and the plasma resistance element (R plasma )540. The plasma resistance element (R plasma )540 is coupled to ground through one or more chamber components such as the chamber lid.

[0055]

[0063] FIG. 5 shows a configuration including two voltage sources, three capacitors, and nine switches used to generate a voltage pseudo-step, but this configuration is not intended to limit the scope of the disclosure provided herein. This is because the waveform generator 500 may include a greater or lesser number of voltage sources, capacitors, and switches connected within a similar configuration for generating a voltage pseudo-step. As will be further described below, the opening and closing timing of the various switches can be controlled by commands sent from a controller (for example, the system controller 126 in FIG. 1). This can affect the IED. The operation of the waveform generator 500 for generating the pseudo-step voltage waveform 400 shown in FIG. 4 will be described in more detail with respect to FIG. 6.

[0056]

[0064] Figure 6 is a timing diagram 600 showing the state of a switch according to certain embodiments of the present disclosure. The following description mainly discloses a switch timing process executed in a system including a waveform generator (e.g., waveform generator 500 of FIG. 5) for generating a pulse voltage waveform (e.g., pseudo-stair voltage waveform 400 of FIG. 4), but this configuration is not intended to limit the scope of the disclosure provided herein.

[0057]

[0065] In the first stage (P1) of a waveform cycle (e.g., a cycle of the pseudo-stair voltage waveform 400), based on a command from the controller, the first switch 512 (S1), the fifth switch 520 (S5), the sixth switch 522 (S6), and the ninth switch 528 (S9) are closed. The second switch 514 (S2) is opened. The third switch 516 (S3) and the fourth switch 518 (S4) are closed.

[0058]

[0066] During the first stage (P1), the positive DC voltage (V positive ) from the first voltage supply 502 charges the floating capacitor 530 and the electrostatic chuck capacitor 532 (formed by the wafer surface and the electrodes). Further, during the first stage (P1), switches 516, 518, 520, 522, and 528 are closed. Thus, the negative DC voltage (-V0) from the second voltage supply 504 charges the first capacitor 506 (C1), the second capacitor 508 (C2), and the third capacitor 510 (C3) to -V0.

[0059]

[0067] In the second stage (P2) of the waveform cycle, based on a command from the controller, the first switch 512 (S1), the fifth switch 520 (S5), the sixth switch 522 (S6), and the ninth switch 528 (S9) are opened. The second switch 514 (S2) and the third switch 516 (S3) are closed. The seventh switch 524 (S7), the fourth switch 518 (S4), and the eighth switch 526 (S8) are opened. Accordingly, the first capacitor 506 (C1) (e.g., charged to -V0) is coupled to the output node 534, applying a negative voltage -V0 to the output node 534.

[0060]

[0068] During the second stage (P2), at the falling edge of the pulse step from V positive to -V0 (e.g., the falling edge 403 of the pseudo-staircase voltage waveform 400), ions are neutralized by plasma bulk electrons from the first capacitor 506. A negative voltage -V0 is established at the electrode (e.g., the non-plasma facing surface of the electrostatic chuck capacitor 532), and a negative DC sheath potential is established at the wafer surface. As the incident ions neutralize the plasma bulk electrons on the wafer surface, the DC sheath potential decreases in the absence of means for current compensation. Accordingly, the energy of the ions incident on the wafer surface will change over time due to the DC sheath potential (i.e., the droop of the pulsed waveform).

[0061]

[0069] To perform current compensation, the pseudo-step voltage waveform 400 is generated by applying different magnitudes of negative voltage to the output node 534. For example, in the third stage (P3) of the waveform cycle, based on a command from the controller, the second switch 514 (S2) remains closed. The first switch 512 (S1), the fifth switch 520 (S5), the sixth switch 522 (S6), and the ninth switch 528 (S9) are opened. The third switch 516 (S3) and the eighth switch 526 (S8) are opened. The seventh switch 524 (S7) and the fourth switch 518 (S4) are closed. During the third stage, the negative voltage from the first capacitor 506 (C1) and the second capacitor 508 (C2) is applied to the electrodes (e.g., applied to the output node 534). In other words, by closing the seventh switch 524 (S7) and the fourth switch 518 (S4), the first capacitor 506 (C1) and the second capacitor 508 (C2) (both charged to -V0) are arranged in series. Therefore, the sum of the voltages of the capacitors 506, 508 (e.g., -2V0) is applied to the output node 534.

[0062]

[0070] In the fourth stage (P4) of the waveform cycle, based on a command from the controller, the second switch 514 (S2) remains closed. The first switch 512 (S1), the fifth switch 520 (S5), the sixth switch 522 (S6), and the ninth switch 528 (S9) remain open. The third switch 516 (S3) remains open. The fourth switch 518 (S4) is opened. The seventh switch 524 (S7) and the eighth switch 526 (S8) are closed. During the fourth stage, a negative voltage (-V0) (e.g., the most negative part of the pseudo-step function ramp and the transient voltage) from each of the first capacitor 506 (C1), the second capacitor 508 (C2), and the third capacitor 510 (C3) is applied to the output node 534. In other words, during the fourth stage (P4), by closing the seventh switch 524 (S7) and the eighth switch 526 (S8) and opening the fourth switch 518 (S4), the capacitors 506, 508, 510 (each charged to -V0) are arranged in series. Thus, the sum of the voltages of the capacitors 506, 508, 510 (e.g., -3V0) is applied to the output node 534.

[0063]

[0071] After the fourth stage of the waveform cycle, the waveform cycle may be repeated. The application of the multiple stages and cycles of the pseudo-step voltage waveform 400 exposes the non-plasma facing surface of the electrostatic chuck capacitor 532 to an effective lamp, and some instances of DC bias may be created while the plasma facing surface of the electrostatic chuck capacitor 532 is receiving an ion discharge current. These DC biases are caused by the closing of the switches as described, and generate different energy peaks (as shown in FIG. 3B) to control the IEDs in the plasma.

[0064]

[0072] In certain embodiments, the first capacitor 506 (C1), the second capacitor 508 (C2), and the third capacitor 510 (C3) may be charged to a specific voltage using the second voltage source 504 according to the waveform to be implemented (e.g., the pseudo-stair voltage waveform 400). In some embodiments, the first capacitor 506 (C1), the second capacitor 508 (C2), and the third capacitor 510 (C3) may be charged to higher or lower voltages to implement various voltage levels for waveforms suitable for various embodiments.

[0065]

[0073] In certain embodiments, as described herein, when the electrostatic chuck capacitor 532 is constantly discharged by the positive ion current from the plasma load 536, the waveform generator 500 maintains the desired negative voltage on the upper surface of the electrostatic chuck capacitor 532. For example, the waveform generator 500 uses the charge stored in the first capacitor 506 (C1), the second capacitor 508 (C2), and / or the third capacitor 510 (C3) to maintain the negative charge of the electrostatic chuck capacitor 532 by constantly operating in a transient period.

[0066]

[0074] The instantaneous voltage across the electrostatic chuck capacitor 532 may not change under transient conditions, but by applying the negative voltage from the first capacitor 506 (C1), the second capacitor 508 (C2), and / or the third capacitor 510 (C3) on the non-plasma facing surface of the electrostatic chuck capacitor 532 alone or in combination over a certain period of time, a pseudo-stair voltage waveform 400 established at the electrodes and the substrate will be generated. The number of steps (and the duration) of the pseudo-stair voltage waveform 400 can vary according to the number of capacitors used in the waveform generator 500, the timing of the switches, and / or the number of voltage sources. Based on the constant application of the negative voltage on the non-plasma facing surface of the electrostatic chuck capacitor 532, the desired negative voltage of the electrostatic chuck capacitor 532 (i.e., the DC bias of the plasma facing surface of the electrostatic chuck capacitor 532) is maintained.

[0067]

[0075] FIG. 7 is a process flow diagram showing a method 700 for waveform generation. Method 700 may be executed by a waveform generation system including a waveform generator (e.g., waveform generator 500 of FIG. 5) and / or a system controller (e.g., system controller 126 of FIG. 1).

[0068]

[0076] In activity 702, during a first stage of generating a waveform (e.g., the pseudo-staircase voltage waveform 400 of FIG. 4), the waveform generation system couples a first voltage source (e.g., the first voltage source 502 of FIG. 5) to an output node (e.g., output node 534). The output node may be coupled to an electrode disposed within a processing chamber (e.g., processing chamber 100 of FIG. 1). For example, the output node may be coupled to bias electrode 104 or support base 107. The first voltage source outputs a positive DC voltage (e.g., V positive ) to the output node.

[0069]

[0077] During the first stage, a first capacitor (e.g., the first capacitor 506 of FIG. 1) and a second capacitor (e.g., the second capacitor 508 of FIG. 1) are charged. For example, the first capacitor and the second capacitor are coupled to a second voltage source (e.g., the second voltage source 504 of FIG. 5). The second voltage source charges the first capacitor and the second capacitor to a desired voltage (e.g., each to a negative voltage -V0).

[0070]

[0078] In activity 704, during a second stage of generating the waveform, the waveform generation system couples the first capacitor between the output node and an electrical ground node. During the second stage, a negative voltage (e.g., -V0) is provided to the output node from the first capacitor.

[0071]

[0079] In activity 706, during the third stage of generating the waveform, the waveform generation system couples the first capacitor and the second capacitor in series between the output node and the electrical ground node. During the third stage, a negative voltage (e.g., -2V0) is provided to the output node from the first capacitor and the second capacitor. After the third stage of the waveform cycle, the waveform cycle may be repeated.

[0072]

[0080] Optionally, in activity 708, during the fourth stage of generating the waveform, the waveform generation system couples the first capacitor, the second capacitor, and the third capacitor in series between the output node and the electrical ground node. During the fourth stage, a negative voltage (e.g., -3V0) is provided to the output node from the first capacitor, the second capacitor, and the third capacitor. After the fourth stage of the waveform cycle, the waveform cycle may be repeated.

[0073]

[0081] The term "coupled" is used herein to refer to a direct or indirect connection between two objects. For example, if object A physically contacts object B and object B physically contacts object C, objects A and C may be considered to be coupled to each other even if objects A and C do not directly physically contact each other. For example, a first object may be coupled to a second object even if the first object does not directly physically contact the second object.

[0074]

[0082] Although the foregoing has been directed to multiple embodiments of the present disclosure, other and further multiple embodiments of the present disclosure may be devised without departing from its basic scope, which is defined by the following claims.

Claims

1. A waveform generator for plasma processing a substrate in a processing chamber, comprising: a first voltage supply; a first switch coupled between the first voltage supply and the output node of the waveform generator; a second switch; and a capacitor array, wherein the second switch is coupled between the output node and the capacitor array, and the capacitor array comprises: a first capacitor coupled to the second switch; a third switch coupled between the first capacitor and an electrical ground node; a second capacitor selectively coupled between the first capacitor and the third switch; and a fourth switch coupled between the second capacitor and the electrical ground node, the waveform generator.

2. The waveform generator according to claim 1, further comprising a charging circuit coupled to the capacitor array.

3. The waveform generator according to claim 2, wherein the charging circuit comprises a second voltage supply selectively coupled to each of the first capacitor and the second capacitor.

4. The waveform generator according to claim 3, wherein the charging circuit further comprises: a fifth switch coupled between the second voltage supply and the first capacitor; and a sixth switch coupled between the fifth switch and the second capacitor.

5. The waveform generator according to claim 4, wherein the charging circuit further comprises a seventh switch coupled to a node between the first capacitor and the third switch and a node between the second capacitor and the sixth switch.

6. The waveform generator according to claim 4, wherein the second voltage supply is selectively coupled to a third capacitor.

7. The waveform generator according to claim 6, wherein the charging circuit further comprises: a ninth switch coupled between the sixth switch and the third capacitor; and an eighth switch coupled to a node between the second capacitor and the fourth switch and a node between the third capacitor and the ninth switch.

8. The waveform generator according to claim 3, wherein each of the first voltage supply and the second voltage supply includes a direct current (DC) voltage source.

9. The waveform generator according to claim 1, wherein each of the first switch, the second switch, the third switch, and the fourth switch includes a transistor.

10. ​ ​ ​ ​ ​ ​ ​ ​ The output node of the waveform generator is coupled to a processing chamber, the waveform generator according to claim 1. **Claim 11** A method for a waveform generator for plasma processing a substrate in a processing chamber, comprising: During a first stage of generating a waveform, coupling a first voltage source to an output node; During a second stage of generating the waveform, coupling a first capacitor between the output node and an electrical ground node; and During a third stage of generating the waveform, coupling the first capacitor and a second capacitor in series between the output node and the electrical ground node. **Claim 12** The method of claim 11, further comprising charging the first capacitor and the second capacitor during the first stage. **Claim 13** The method of claim 12, wherein charging the first capacitor and the second capacitor includes coupling a second voltage source to the first capacitor and the second capacitor. **Claim 14** The method of claim 11, further comprising providing a negative voltage stored in the first capacitor to the output node during the second stage. **Claim 15** The method of claim 11, further comprising providing a negative voltage to the output node, the negative voltage being a sum of voltages stored in the first capacitor and the second capacitor. **Claim 16** A memory, and An apparatus for waveform generation for plasma processing a substrate in a processing chamber, comprising one or more processors coupled to the memory, the memory and the one or more processors being configured to: During a first stage of generating a waveform, couple a first voltage source to an output node; During a second stage of generating the waveform, couple a first capacitor between the output node and an electrical ground node; and During a third stage of generating the waveform, couple the first capacitor and a second capacitor in series between the output node and the electrical ground node. **Claim 17** The apparatus of claim 16, wherein the memory and the one or more processors are further configured to charge the first capacitor and the second capacitor during the first stage. **Claim 18** Charging the first capacitor and the second capacitor includes coupling a second voltage supply to the first capacitor and the second capacitor, the apparatus of claim 17. **Claim 19** The memory and the one or more processors are further configured to provide a negative voltage stored in the first capacitor to the output node during the second stage, the apparatus of claim 16. **Claim 20** The memory and the one or more processors are further configured to provide a negative voltage to the output node, the negative voltage being the sum of the voltages stored in the first capacitor and the second capacitor, the apparatus of claim 16.

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