Reducing gate-induced drain leakage in the word lines of a DRAM

Abstract

To provide dynamic random-access memory cells with buried word lines having reduced gate induced drain leakage.SOLUTION: A memory device 100 comprises two work-function metal layers 112, 116. An insulating layer 120 is deposited on a second work-function metal layer 116, and has a top surface 122 substantially coplanar with a substrate surface 103. The second work-function metal layer 116 of the memory device has a lower work function than a first work-function layer. The low work-function metal layer reduces gate-induced drain leakage current losses.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. In particular, embodiments of the present disclosure provide a dynamic random access memory cell with an embedded word line having reduced gate-induced drain leakage.

Background Art

[0002]

[0002] Electronic devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard disk drives use memory devices that provide significant data storage performance while consuming low power. There are two main types of random access memory cells suitable for use in electronic devices, namely, dynamic and static. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but may require periodic reprogramming or "refreshing" to maintain this voltage beyond a very short period. Static random access memory (SRAM) is so named because they do not require periodic refreshing.

[0003]

[0003] DRAM memory circuits are manufactured by replicating millions of identical circuit elements known as DRAM cells on a single semiconductor wafer. Each DRAM cell is an addressable location capable of storing 1 bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components. That is, a field effect transistor (FET) and a capacitor.

[0004]

[0004] The manufacture of DRAM cells involves fabricating a transistor, a capacitor, and three contacts. Each of the three is for a bit line, a word line, and a reference voltage. The manufacture of DRAM is a highly competitive business. In order to enable more memory to be packed onto a single memory chip, there is an ongoing need to reduce the size of individual cells, and in particular, to increase the memory cell density to a density exceeding 256 megabits. The limitations on reducing the cell size are the passage of both active and passive word lines through the cell, the size of the cell capacitor, and the compatibility of the array device with non-array devices.

[0005]

[0005] Conventionally, the word lines of DRAM have used a high work function material as the gate electrode to reduce channel impurities. An important leakage component in DRAM devices is gate-induced drain leakage (GIDL). It is caused by trap assisted band-to-band tunneling at the surface of the drain of the transistor where the gate overlaps the drain. During fabrication, interface states are generated within the substrate. These surface states increase the generation rate of electron-hole pairs and enhance GIDL. The high work function material used in the word lines of DRAM may increase gate-induced drain leakage near the source / drain area due to band-to-band tunneling. Therefore, there is a need for a DRAM cell that can maintain a low resistance while also maintaining a low gate-induced drain leakage.

Summary of the Invention

[0006]

[0006] Embodiments of the present disclosure are directed to a memory device and a method of forming a memory device. In one or more embodiments, the memory device is a substrate in which a plurality of trenches extend from a substrate surface into the substrate by a depth, each trench including a bottom and sidewalls, a gate oxide layer on the bottom and sidewalls of the trench, a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer and having an upper surface within the depth of the trench, and a second work function metal layer on the recessed metal layer.

[0007]

[0007] In one or more embodiments, a method of forming a memory device includes providing a substrate having a plurality of trenches, depositing a conformal gate oxide layer on the substrate, forming a metal layer on the gate oxide layer, recessing the metal layer to form a recessed metal layer, and depositing a second work function metal layer on the recessed metal layer.

[0008]

[0008] In one or more embodiments, a memory cell includes a recessed access device and a word line electrically connected to the recessed access device, the word line including a substrate in which a plurality of trenches extend from a substrate surface into the substrate by a depth, each trench including a bottom and sidewalls, a gate oxide layer on the bottom and sidewalls of the trench, a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer and having an upper surface within the depth of the trench, and a second work function metal layer on the recessed metal layer.

[0009]

[0009] To enable a detailed understanding of the features of the present disclosure described above, a more specific description of the present disclosure briefly summarized above is obtained by referring to the embodiments, and some embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure, and the present disclosure may admit other equally effective embodiments. In the embodiments described herein, the accompanying drawings are used for description by way of illustration rather than limitation, and similar elements are denoted by similar reference numerals in the drawings.

Brief Description of the Drawings

[0010]

Figure 1

[0010] A circuit diagram of a DRAM cell block according to the prior art is shown.

Figure 2

[0011] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 3

[0012] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 4

[0013] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 5

[0014] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 6

[0015] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 7

[0016] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 8

[0017] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Figure 9

[0018] A cross-sectional view of a device according to one or more embodiments of the present disclosure is shown.

Modes for Carrying Out the Invention

[0011]

[0019] Before some exemplary embodiments of the present disclosure are described, it should be understood that the present disclosure is not limited to the details of the configurations or processing steps presented in the following description. The present disclosure can have other embodiments and can be implemented or executed in various ways.

[0012]

[0020] As used in this specification and the appended claims, terms such as "precursor", "reactant", "reactive gas", etc. are used interchangeably to refer to any gas species that can react with the substrate surface.

[0013]

[0021] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores data bits by storing (or not for zero) a packet of charge on a capacitor, the charge of which is gated onto the capacitor via an access transistor, and detecting the voltage perturbation caused by turning on the same transistor and dumping the charge packet onto the interconnect line of the transistor output. Thus, a single DRAM cell is fabricated from one transistor and one capacitor. As shown in FIG. 1, a DRAM device is formed from an array of DRAM cells. The columns on the access transistors are linked by word lines 52a, 52b, and the transistor input / outputs are linked by bit lines 54a, 54b, 54c. Historically, DRAM capacitors have evolved to a 3D structure, branching from flat polysilicon oxide substrate plate capacitors to "stack" capacitors having both plates on the substrate and "trench" capacitors using etched cavities in the substrate as a common plate.

[0014]

[0022] Conventionally, DRAM cells have placed a high work function metal structure within an embedded word line structure. In a DRAM device, bit lines are formed within a metal level placed on a substrate, while word lines are formed at a polysilicon gate level on the surface of the substrate. In an embedded word line (bWL), the word line is embedded beneath the surface of the semiconductor substrate using a metal as the gate electrode.

[0015]

[0023] In one or more embodiments, a memory device, such as a DRAM cell, is provided that uses a low work function material on a high work function material. Such a memory device advantageously maintains low resistance while also maintaining low gate induced drain leakage (GIDL). An embedded word line cell array transistor has a word line embedded beneath the surface of the semiconductor substrate using a metal as the gate electrode.

[0016]

[0024] In this specification, exemplary embodiments are described with reference to cross-sectional views that are schematic diagrams of exemplary embodiments (and intermediate structures). Thus, for example, variations from the shape of the figures as a result of manufacturing techniques and / or tolerances are expected. Thus, exemplary embodiments should not be construed as limited to the specific shapes of the regions shown herein, but may include, for example, variations in the shapes resulting from manufacturing. For example, an implanted region illustrated as rectangular may typically have rounded or curved features, and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, an embedded region formed by implantation may result in some implantation within the region between the embedded region and the surface where implantation occurs through it. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to represent the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0017]

[0025] FIGS. 2 to 9 are cross-sectional views showing a memory device 100 according to one or more embodiments. Referring to FIG. 2, the substrate 102 is formed to have a plurality of trenches 104 that form recessed channels. The trenches have a bottom 106 and sidewalls 108. The plurality of trenches 104 may be formed to have a width within a range of about 10 nm to about 100 nm, including about 10 nm to about 80 nm, about 10 nm to about 70 nm, about 10 nm to about 60 nm, about 10 nm to about 50 nm, or about 10 nm to about 40 nm, but are not limited thereto. As will be appreciated by those skilled in the art, the width of the plurality of trenches 104 is defined by the distance W1 from one sidewall 108 to the other sidewall 108. As will be appreciated by those skilled in the art, the depth of the plurality of trenches 104 is defined by the distance D1 from the substrate surface 103 to the bottom 106 of the plurality of trenches 104.

[0018]

[0026] As used herein, the term "substrate" refers to any substrate or the surface of a material formed on a substrate where film processing is performed during manufacturing. For example, the substrate surface on which processing can be performed may include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., depending on the application, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate as will be disclosed in more detail below. The term "substrate surface" is intended to include such a lower layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019]

[0027] To form the plurality of trenches 104, a buffer insulating layer (e.g., a silicon oxide layer, not shown) may be formed on the substrate surface 103 and / or a hard mask layer (e.g., a nitride layer, not shown) may be formed. Such techniques are well known to those skilled in the art and thus will not be described.

[0020]

[0028] Referring to FIG. 3, a gate oxide layer 110 is conformally deposited on the substrate 102, on the substrate surface 103, and along the sidewalls 108 and bottom 106 of the plurality of trenches 104. In one or more embodiments, the gate oxide layer 110 includes one or more of silicon oxynitride (SiON), silicon oxide, or a high-k material. The term "silicon oxide" may be used to describe the gate oxide layer 110, but those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" may be used to describe a material having silicon and oxygen in any suitable stoichiometric ratio. The same is true for other materials recited in the present disclosure, such as silicon nitride, silicon oxynitride, tungsten oxide, zirconium oxide, aluminum oxide, hafnium oxide, etc.

[0021]

[0029] In one or more embodiments, the term "high-k" refers to a material having a high dielectric constant (e.g., as compared to silicon dioxide). In one or more embodiments, the high-k material is selected from one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), or zirconium silicon oxide (ZrSiO).

[0022]

[0030] In the above embodiments, the gate oxide layer 110 has a thickness in the range from about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0023]

[0031] Referring to FIGS. 4 and 5, a metal layer 113 is formed on the gate oxide layer 110. In one or more embodiments, the metal layer 113 is formed by depositing a conformal first work function metal layer 112 (see FIG. 4) on the conformal gate oxide layer 110 and then depositing a bulk metal layer 114 (see FIG. 5) on the first work function metal layer 112. The bulk metal layer 114 is deposited using any one of several methods well known to those skilled in the art, including chemical vapor deposition, physical vapor deposition, or atomic layer deposition, but is not limited thereto.

[0024]

[0032] As used herein, "atomic layer deposition" or "cyclical deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is individually exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay such that each compound can adhere and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be exposed to the substrate sequentially. In spatial ALD, various portions of the substrate surface or the material on the substrate surface are exposed to two or more reactive compounds simultaneously such that any given point on the substrate is not substantially exposed to two or more reactive compounds at the same time. As used in this specification and the appended claims, the term "substantially" in this regard means that there is a possibility that a small portion of the substrate may be simultaneously exposed to multiple reactive gases for diffusion, and the simultaneous exposure is not intended, as would be understood by those skilled in the art.

[0025]

[0033] In one aspect of the time-domain ALD process, after a first reactive gas (i.e., a first precursor or compound A, such as an aluminum precursor) enters (pulses) into the reaction zone, it is delayed for a first time. Next, after a second precursor or compound B (e.g., an oxidizing agent) enters (pulses) into the reaction zone, it is delayed for a second time. During each time delay, a purge gas such as argon is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds enter (are pulsed) alternately until a desired film or film thickness is formed on the substrate surface. In any scenario, the ALD process of pulsing compound A, the purge gas, compound B, and the purge gas is a cycle. The cycle may start with either compound A or compound B and can continue through each sequence of the cycle until a film of a predetermined thickness is obtained.

[0026]

[0034] In one embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied to the reaction zone simultaneously but are separated by a curtain of inert gas and / or a curtain of vacuum. The substrate is moved relative to the gas supply device. Thereby, any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0027]

[0035] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to a precursor and / or a co-reagent simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to either flowing simultaneously or having most of the exposure of the precursors overlap.

[0028]

[0036] Plasma enhanced chemical vapor deposition (PECVD) is widely known for depositing thin films due to its cost efficiency and versatility of film properties. In PECVD, for example, a hydrocarbon source such as vapor of a gas-phase hydrocarbon or a liquid-phase hydrocarbon entrained in a carrier gas is introduced into the PECVD chamber. A plasma initiation gas, usually helium, is also introduced into the chamber. Then, a plasma is initiated in the chamber to generate excited CH radicals. The excited CH radicals chemically bond to the surface of a substrate positioned in the chamber and form a desired film thereon. Embodiments described herein with reference to PECVD may be implemented using any suitable thin film deposition system. Any apparatus described herein is exemplary and should not be understood or construed as limiting the scope of the embodiments described herein.

[0029]

[0037] As used herein, the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) with respect to the vacuum level. In one or more embodiments, the first work function metal layer has a work function of 4.3 eV or more. In one embodiment, the first work function metal layer has a work function of 4.5 eV or more. In other embodiments, the first work function metal layer has a work function of 4.3 eV or more, including 4.4 eV or more, 4.5 eV or more, 4.6 eV or more, 4.7 eV or more, 4.8 eV or more, 4.9 eV or more, 5.0 eV or more, 5.1 eV or more, or 5.2 eV or more.

[0030]

[0038] In one or more embodiments, the first work function metal layer includes a metal nitride. In one or more embodiments, the first work function metal layer includes one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN. In one or more embodiments, the first work function metal layer is selected from the group consisting of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, WN / TiN, and combinations thereof. In one or more embodiments, the first work function metal layer includes titanium nitride. In one or more embodiments, the first work function metal layer may also be referred to as a high / medium work function metal layer.

[0031]

[0039] In one or more embodiments, the first work function metal layer 112 has a thickness in the range of about 1 nm to about 5 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, or about 5 nm.

[0032]

[0040] In one or more embodiments, the bulk metal layer 114 is also known as a word line. Referring to FIG. 6, the bulk metal layer 114 (i.e., the word line) is embedded (recessed) by chemical mechanical polishing (CMP) and etched back. Thereby, the bulk metal layer 114 and the first work function metal layer 112 do not protrude beyond the substrate surface 103 (e.g., thereby, the bulk metal layer 114 is completely embedded within the substrate 102).

[0033]

[0041] In the above embodiments, the embedded word line 115 (i.e., the recessed bulk metal layer 115) may be formed by forming a word line layer 114 (i.e., the bulk metal layer 114) on the substrate 102 so as to fill the trench 104. Then, the word line layer 114 may be polished using a chemical mechanical polishing (CMP) method and etched back using a dry etching process to expose the substrate surface 103. The embedded word line 115 may be formed by using a partial etching process to recess the embedded word line 114 into the substrate 102. As shown in FIG. 6, the first work function metal layer 112 is placed at the same height as the embedded word line 115. The upper surfaces 117 of the embedded word line 115 and the first work function metal layer 112 are at a recessed depth or distance D2 from the substrate surface 103 within the plurality of trenches 104. In one or more embodiments, the embedded word line 115 has an upper surface 117 within the depth D1 of the trench 104. Thus, in one or more embodiments, D2 is less than D1.

[0034]

[0042] In one or more embodiments, the bulk metal layer 114 (i.e., the word line) includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the bulk metal layer 114 includes tungsten (W). In other embodiments, the bulk metal layer 114 includes ruthenium (Ru). In one or more embodiments, the embedded word line 115 (i.e., the recessed bulk metal layer 115) includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the embedded word line 115 includes tungsten (W). In other embodiments, the embedded word line 115 includes ruthenium (Ru).

[0035]

[0043] Referring to FIG. 7, in one or more embodiments, a second work function metal layer 116 is deposited on the substrate 102 over the recessed bulk metal layer 115 (i.e., over the embedded word line). Referring to FIG. 8, the second work function metal layer 116 is then polished using a chemical mechanical polishing (CMP) process and etched back to expose the substrate surface 103. The upper surface 118 of the second work function metal layer 116 is at a distance D3 from the substrate surface 103 within a plurality of trenches 104. In one or more embodiments, the second work function metal layer 116 has an upper surface 118 within the depth D1 of the trench 104. Thus, in one or more embodiments, D3 is less than D1.

[0036]

[0044] In one or more embodiments, the second work function metal layer 116 has a work function less than that of the first work function metal layer. In one or more embodiments, the second work function metal layer 116 has a work function of less than about 4.3 eV. In one embodiment, the second work function metal layer 116 has a work function of 4.2 eV or less. In one embodiment, the work function of the second work function metal layer 116 is about 4.25 eV or less, about 4.2 eV or less, about 4.15 eV or less, about 4.1 eV or less, about 4.05 eV or less, about 4 eV or less, about 3.5 eV or less, or about 3.0 eV or less.

[0037]

[0045] In the above embodiments, the second work function metal layer 116 may also be referred to as a low work function metal layer. Resistance is a property of a material that quantifies how strongly the material resists the flow of electric current. A low resistance indicates that the material allows the flow of electric current quite readily. A material with a high resistance does not readily allow the flow of electric current. As used herein, the term "material with a high resistance" refers to a material or substance having a resistance greater than about 500 μΩcm. In one or more embodiments, the first work function metal layer 116 has a resistance of less than about 500 μΩcm, including less than about 400 μΩcm, less than about 300 μΩcm, less than about 200 μΩcm, or about 100 μΩcm. In one or more specific embodiments, the second work function metal layer 116 is substantially free of polysilicon and / or doped polysilicon. As used herein, the term "substantially free of" means that there is less than 5% polysilicon and / or doped polysilicon, including less than 4%, less than 3%, less than 2%, less than 1%, or less than 0.5% polysilicon and / or doped polysilicon present within the second work function metal layer 116. As used herein, the term "polysilicon" or "poly-Si" refers to polycrystalline silicon.

[0038]

[0046] In one or more embodiments, the second work function metal layer 116 includes a metal carbide or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). As used herein, the term "metal carbide" refers to a composite material composed of carbon and a metal having generally a less negative charge. As used herein, the term "metal silicide" refers to a composite material composed of silicon and a metal having generally a less positive charge. As will be recognized by one of ordinary skill in the art, the metal silicide, which is a composite material, is distinguished from polysilicon and doped polysilicon.

[0039]

[0047] In other embodiments, the second work function metal layer 116 comprises a metal carbide or metal silicide having one or more metals selected from gallium (Ga), indium (In), or thallium (Tl). In one or more embodiments, the second work function metal layer 116 comprises aluminum carbide or aluminum silicide. In one or more embodiments, the second work function metal layer 116 comprises gallium carbide or gallium silicide. In one or more embodiments, the second work function metal layer 116 comprises indium carbide or indium silicide. In one or more embodiments, the second work function metal layer 116 comprises thallium carbide or thallium silicide. In one or more embodiments, the second work function metal layer 116 comprises one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). In other embodiments, the second work function metal layer 116 comprises one or more metals selected from gallium (Ga), indium (In), or thallium (Tl). In one or more embodiments, the second work function metal layer 116 comprises aluminum. In one or more embodiments, the second work function metal layer 116 comprises gallium. In one or more embodiments, the second work function metal layer 116 comprises indium. In one or more embodiments, the second work function metal layer 116 comprises thallium.

[0040]

[0048] In one or more embodiments, the second work function metal layer 116 has a thickness T1 in the range of about 10 nm to about 50 nm, including about 10 nm, about 15 nm, about 20 nm, about 25 nm, about 30 nm, about 35 nm, about 40 nm, about 45 nm, or about 50 nm.

[0041]

[0049] Referring to FIG. 9, an insulating layer 120 is deposited on the second work function metal layer 116. In one or more embodiments, the insulating layer has an upper surface 122 that is substantially coplanar with the substrate surface 103.

[0042]

[0050] In the above-described embodiments, the insulating layer 120 includes a dielectric material. As used herein, the term "dielectric" refers to an electrically insulating material that can be polarized by an applied electric field. In one or more embodiments, the dielectric material includes, but is not limited to, oxides (e.g., SiO2, Al2O3), nitrides (e.g., Si3N4). In one or more embodiments, the dielectric material includes silicon nitride (Si3N4). In certain embodiments, the composition of the insulating layer is non-stoichiometric with respect to the ideal molecular formula. For example, in certain embodiments, the dielectric material includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), oxynitrides (e.g., silicon oxynitride (SiON)), oxycarbides (e.g., silicon oxycarbide (SiOC)), and oxynitrocarbides (e.g., silicon oxycarbonitride (SiNCO)).

[0043]

[0051] One or more embodiments are directed to a memory cell. In one or more embodiments, the memory cell includes a recess access device and a word line electrically connected to the recess access device, the word line including a substrate having a plurality of trenches extending from the substrate surface into the substrate by a depth, each trench including a bottom and sidewalls, a gate oxide layer on the bottom and sidewalls of the trench, a recessed metal layer on the gate oxide layer, the recessed metal layer including a first work function metal layer and a bulk metal layer and having an upper surface within the depth of the trench, and a second work function metal layer on the recessed metal layer.

[0044]

[0052] Spatial relative terms such as "lower", "below", "underside", "upper", "above", "upside" may be used herein to facilitate description of the relationship of one element or feature to another (one or more) element or (one or more) features as shown in the drawings. It should be understood that spatial relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawing is turned over, an element described as "below" or "lower" than another element or feature will be oriented "above" the other element or feature. Thus, the exemplary term "lower" can encompass both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0045]

[0053] In the context of describing the materials and methods described herein (in particular, in the context of the following claims), the use of the terms "a", "an", and "the" and similar indicators is to be construed as covering both the singular and the plural, unless the contrary is indicated herein or is clearly contradicted by the context. The recitation of a range of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless the contrary is indicated herein or is otherwise clearly contradicted by the context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and does not limit the scope unless otherwise claimed. Words in the specification should not be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods.

[0046]

[0054] References to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" throughout this specification mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or traits may be combined in any suitable manner.

[0047] Although the disclosure of this specification has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the present disclosure without departing from the spirit and scope of the invention. Therefore, the present invention is intended to cover modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A substrate in which a plurality of trenches extend from the substrate surface into the substrate by a depth, each trench including a bottom and sidewalls, the substrate, A gate oxide layer on the bottom and the sidewalls of the trench, An embedded metal layer on the gate oxide layer, comprising a first work function metal layer containing a material having a work function of 4.3 eV or more and a bulk metal layer, having an upper surface within the range of the depth of the trench, and the upper surface of the first work function metal layer and the upper surface of the bulk metal layer being at the same depth from the substrate surface, the embedded metal layer, and A second work function metal layer deposited on the first work function metal layer and the bulk metal layer and containing a material having a work function of less than 4.3 eV, the second work function metal layer including a metal carbide having one or more metals selected from gallium (Ga), indium (In), or thallium (Tl), or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl) A memory device comprising.

2. The memory device according to claim 1, wherein the first work function metal layer is formed on the gate oxide layer on the sidewalls and the bottom of the plurality of trenches, and the bulk metal layer is formed on the first work function metal layer.

3. The memory device according to claim 1, wherein the first work function metal layer contains a metal nitride.

4. The memory device according to claim 1, wherein the first work function metal layer contains one or more of titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), molybdenum nitride (MoN), TaN / TiN, or WN / TiN.

5. The memory device according to claim 1, wherein the bulk metal layer contains one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh).

6. The memory device according to claim 1, wherein the second work function metal layer has an upper surface within the range of the depth of the plurality of trenches.

7. The memory device according to claim 6, further comprising an insulating layer on the second work function metal layer in the plurality of trenches, the insulating layer having an upper surface substantially coplanar with the substrate surface.

8. A method of forming a memory device, comprising: providing a substrate having a plurality of trenches; depositing a conformal gate oxide layer on the substrate; forming a metal layer on the conformal gate oxide layer, including depositing a conformal first work function metal layer on the conformal gate oxide layer and depositing a bulk metal layer on the conformal first work function metal layer; recessing the metal layer to form a recessed metal layer, wherein the conformal first work function metal layer and the bulk metal layer are recessed to the same depth from the substrate surface; and depositing a second work function metal layer on the conformal first work function metal layer and the bulk metal layer, the second work function metal layer including a metal carbide having one or more metals selected from gallium (Ga), indium (In), or thallium (Tl), or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl). including wherein the conformal first work function metal layer includes a material having a work function of 4.3 eV or more, and the second work function metal layer includes a material having a work function of less than 4.3 eV.

9. The method according to claim 8, wherein recessing the metal layer moves the upper surface of the conformal first work function metal layer and the upper surface of the bulk metal layer to the recess depth in the plurality of trenches.

10. The method according to claim 8, wherein the second work function metal layer has a thickness in the range of 10 nm to 50 nm.

11. The method according to claim 8, wherein the gate oxide layer includes one or more of silicon oxynitride (SiON), silicon oxide (SiO), or a high-k material.

12. The method according to claim 8, further comprising etching the second work function metal layer.

13. The method according to claim 12, further comprising depositing an insulating layer on the second work function metal layer.

14. A memory cell, comprising Recessed access device, and a word line electrically connected to the recessed access device, wherein the word line includes a substrate in which a plurality of trenches extend from the substrate surface into the substrate by a depth, each trench including a bottom and side walls; a gate oxide layer on the bottom and the side walls of the trench; a recessed metal layer on the gate oxide layer, including a first work function metal layer and a bulk metal layer, having an upper surface within the range of the depth of the trench, and the upper surface of the first work function metal layer and the upper surface of the bulk metal layer being at the same depth from the substrate surface; and a second work function metal layer deposited on the first work function metal layer and the bulk metal layer, the second work function metal layer including a metal carbide having one or more metals selected from gallium (Ga), indium (In), or thallium (Tl), or a metal silicide having one or more metals selected from aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), wherein the first work function metal layer includes a material having a work function of 4.3 eV or more, and the second work function metal layer includes a material having a work function of less than 4.3 eV, a memory cell.

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