Multilayer electronic component

Abstract

To achieve a multilayer electronic component that can achieve desired characteristics by reducing electromagnetic coupling between two inductors.SOLUTION: An electronic component 1 includes a common port 2, a signal port 4, a first inductor L24, a second inductor L25, and a stack 50. The first inductor L24 has a first end and a second end. The second end of the first inductor L24 is connected to one end of the second inductor L25. A first inductor conductor L24c constituting the first inductor L24 is wound about an axis A1 extending in a first direction. A second inductor conductor L25c constituting the second inductor L25 is wound about an axis A2 extending in a second direction intersecting the first direction.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present invention relates to a multilayer electronic component including two inductors.

Background Art

[0002] In small mobile communication devices, a configuration is widely used in which an antenna commonly used in a plurality of applications having different systems and usage frequency bands is provided, and a plurality of signals transmitted and received by this antenna are separated using a diplexer.

[0003] Generally, a diplexer that separates a first signal having a frequency within a first frequency band and a second signal having a frequency within a second frequency band higher than the first frequency band includes a common port, a first signal port, a second signal port, a first filter provided in a first signal path from the common port to the first signal port, and a second filter provided in a second signal path from the common port to the second signal port. As the first and second filters, for example, an LC resonator configured using an inductor and a capacitor is used.

[0004] As a diplexer, as disclosed in Patent Document 1, a device using a laminate including a plurality of laminated dielectric layers is known. Further, as an inductor used in an LC resonator, as disclosed in Patent Document 1, an inductor configured using an inductor electrode extending in the short side direction of the laminate and two via hole conductors extending in the lamination direction of the laminate is known.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In recent years, miniaturization and space saving of small mobile communication devices have been demanded in the market, and miniaturization of the diplexer used in such communication devices has also been required. When the LC resonator constituting the filter includes two inductors, if the diplexer is miniaturized, the electromagnetic coupling between the two inductors may become too strong. As a result, it may not be possible to achieve the desired characteristics.

[0007] Patent Document 1 discloses a method of weakening the electromagnetic coupling between two inductors by shifting two inductors, each constituted by an inductor electrode and two via hole conductors, in the longitudinal direction on the upper surface of the diplexer. However, when the diplexer is miniaturized, the space for shifting the two inductors also becomes smaller. Patent The method described in Document 1 has a problem that in the miniaturized diplexer, the electromagnetic coupling between the two inductors cannot be sufficiently weakened.

[0008] The above problem is not limited to the diplexer, but applies to all multilayer electronic components including two inductors that can be electromagnetically coupled.

[0009] The present invention has been made in view of such problems, and an object thereof is to provide a multilayer electronic component in which the electromagnetic coupling between two inductors is suppressed so that desired characteristics can be realized.

Means for Solving the Problems

[0010] The multilayer electronic component of the present invention includes a first port, a second port through which a signal input to the first port passes, a first inductor and a second inductor provided between the first port and the second port in terms of circuit configuration, a plurality of stacked dielectric layers and a plurality of conductors, and a laminate for integrating the first port, the second port, the first inductor and the second inductor. The first inductor has a first end closest to the first port in terms of circuit configuration and a second end opposite to the first end. The second end of the first inductor is connected to one end of the second inductor.

[0011] The laminate includes a first inductor conductor forming a first inductor and a second inductor conductor forming a second inductor. The first inductor conductor is wound around an axis extending in a first direction. The second inductor conductor is wound around an axis extending in a second direction intersecting the first direction.

[0012] In the laminated electronic component of the present invention, the first direction and the second direction may be orthogonal to each other. In this case, one of the first direction and the second direction may be parallel to the lamination direction of the plurality of dielectric layers.

[0013] Further, in the laminated electronic component of the present invention, the first inductor and the second inductor may be provided in series in a path connecting the first port and the second port.

[0014] Further, the laminated electronic component of the present invention may further include a first resonator provided between the first port and the second port in terms of circuit configuration. The first inductor and the second inductor may be included in the first resonator. In this case, the laminated electronic component may further include a third port and a second resonator provided between the first port and the third port in terms of circuit configuration.

[0015] Further, when the laminated electronic component of the present invention includes a third port, one of the second port and the third port may be a first signal port that selectively passes a first signal having a frequency within a first passband, and the other of the second port and the third port may be a second signal port that selectively passes a second signal having a frequency within a second passband lower than the first passband. Also, the second port may be the first signal port, and the third port may be the second signal port.

[0016] In addition, when the multilayer electronic component of the present invention includes a second resonator, the laminate may further include a conductor for the second resonator that constitutes the second resonator. In this case, one of the first inductor conductor and the second inductor conductor may be a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers, and the other of the first inductor conductor and the second inductor conductor may be a vertical inductor conductor wound around an axis extending in a direction perpendicular to the stacking direction of the plurality of dielectric layers. The vertical inductor conductor may be disposed at a position farther from the conductor for the second resonator than the horizontal inductor conductor.

[0017] In addition, when the multilayer electronic component of the present invention includes a second resonator, the laminate may have a bottom surface and an upper surface located at both ends in the stacking direction of the plurality of dielectric layers, and four side surfaces connecting the bottom surface and the upper surface. The shape of each of the bottom surface and the upper surface may be a rectangular shape that is long in one direction. The four side surfaces may include a first side surface and a second side surface located at both ends in the longitudinal direction of the rectangular shape. In this case, one of the first inductor conductor and the second inductor conductor may be a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers, and the other of the first inductor conductor and the second inductor conductor may be a vertical inductor conductor wound around an axis extending in a direction perpendicular to the stacking direction of the plurality of dielectric layers. The vertical inductor conductor may be disposed at a position closer to the first side surface than the second side surface. The distance from the vertical inductor conductor to the first side surface may be smaller than the distance from the horizontal inductor conductor to the first side surface.

Advantages of the Invention

[0018] In the multilayer electronic component of the present invention, the first inductor conductor constituting the first inductor is wound around an axis extending in the first direction, and the second inductor conductor constituting the second inductor is wound around an axis extending in a second direction intersecting the first direction. Thus, according to the present invention, there is an effect that it is possible to realize a multilayer electronic component capable of suppressing electromagnetic field coupling between the first inductor and the second inductor and realizing desired characteristics.

Brief Description of the Drawings

[0019]

Figure 1

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Figure 14

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Figure 17

Embodiments for Carrying Out the Invention

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, with reference to FIG. 1, an outline of the configuration of a multilayer electronic component (hereinafter simply referred to as an electronic component) 1 according to one embodiment of the present invention will be described. The electronic component 1 according to the present embodiment includes at least a first port, a second port, a first inductor, and a second inductor. The second port is a port that allows a signal input to the first port to pass through. The first and second inductors are provided between the first port and the second port in terms of circuit configuration. In this application, the expression "in terms of circuit configuration" is used to refer to the arrangement on the circuit diagram rather than the arrangement in the physical configuration.

[0021] FIG. 1 shows, as an example of an electronic component 1 including a first port, a second port, a first inductor, and a second inductor, a diplexer. The diplexer includes a first filter that selectively passes a first signal having a frequency within a first passband, and a second filter that selectively passes a second signal having a frequency within a second passband lower than the first passband.

[0022] The electronic component 1 further includes a third port. One of the second port and the third port is a first signal port that selectively passes a first signal having a frequency within the first passband, and the other of the second port and the third port is a second signal port that selectively passes a second signal having a frequency within the second passband. In particular, in the present embodiment, the electronic component 1 includes a common port 2 as the first port, a signal port 4 as the second port, and a signal port 3 as the third port. The signal port 4 corresponds to the first signal port. The signal port 3 corresponds to the second signal port.

[0023] The electronic component 1 further includes a resonator 10 provided between the common port 2 and the signal port 3 in terms of circuit configuration, and a resonator 20 provided between the common port 2 and the signal port 4 in terms of circuit configuration.

[0024] Next, with reference to FIG. 1, an example of the configuration of the resonators 10 and 20 will be described. The resonator 10 includes a port 11 connected to the common port 2, a port 12 connected to the signal port 3, a path 13 connecting the port 11 and the port 12, inductors L11, L12, L13, and capacitors C11, C12, C13. The inductors L11 and L12 are provided in series in the path 13. The path 13 is a part of the path connecting the common port 2 and the signal port 3.

[0025] One end of the inductor L11 is connected to the port 11. One end of the inductor L12 is connected to the other end of the inductor L11. The other end of the inductor L12 is connected to the port 12.

[0026] One end of capacitor C11 is connected to one end of inductor L12. One end of capacitor C12 is connected to the other end of inductor L12. Inductor L13 connects the other ends of capacitors C11 and C12 to ground. Capacitor C13 is connected in parallel to inductor L12.

[0027] Resonator 20 includes port 21 connected to common port 2, port 22 connected to signal port 4, path 23 connecting port 21 and port 22, and LC circuits 24, 25, 26 provided between port 21 and port 22 in terms of circuit configuration.

[0028] LC circuit 24 includes inductor L21 and capacitors C21, C22. One end of inductor L21 is connected to port 21. Capacitor C21 is connected in parallel to inductor L21. One end of capacitor C22 is connected to the other end of inductor L21. The other end of capacitor C22 is connected to ground.

[0029] LC circuit 25 includes inductors L22, L23 and capacitors C23, C24, C25, C26, C27, C28, C29, C30. One end of capacitor C23 is connected to the other end of inductor L21 of LC circuit 24. One end of capacitor C24 is connected to the other end of capacitor C23. One end of capacitor C25 is connected to the other end of capacitor C24. One end of capacitor C26 is connected to the other end of capacitor C25.

[0030] One end of capacitor C27 is connected to one end of capacitor C23. One end of capacitor C28 is connected to the other end of capacitor C27. The other end of capacitor C28 is connected to the other end of capacitor C26.

[0031] One end of capacitor C29 is connected to the connection point of capacitors C23 and C24. The other end of capacitor C29 is connected to the connection point of capacitors C26 and C28. One end of inductor L22 is connected to the connection point of capacitors C23 and C24. The other end of inductor L22 is connected to ground.

[0032] One end of capacitor C30 is connected to the connection point of capacitors C23 and C27. The other end of capacitor C30 is connected to the connection point of capacitors C25 and C26. One end of inductor L23 is connected to the connection point of capacitors C25 and C26. The other end of inductor L23 is connected to ground.

[0033] LC circuit 26 includes inductors L24, L25 and capacitors C31, C32, C33, C34. Inductors L24 and L25 are provided in series on path 23. Path 23 is part of the path connecting common port 2 and signal port 4.

[0034] One end of inductor L24 is connected to the other end of capacitor C26 of LC circuit 25. One end of inductor L25 is connected to the other end of inductor L24. The other end of inductor L25 is connected to port 22.

[0035] One end of capacitor C31 is connected to one end of inductor L24. One end of capacitor C32 is connected to one end of inductor L25. The other ends of capacitors C31 and C32 are connected to ground. Capacitor C33 is connected in parallel with inductor L24. Capacitor C34 is connected in parallel with inductor L25.

[0036] The first signal with a frequency within the first passband selectively passes through path 23 of resonator 20. The second signal with a frequency within the second passband selectively passes through path 13 of resonator 10. In this way, electronic component 1 separates the first signal and the second signal.

[0037] Next, referring to FIG. 2, other configurations of electronic component 1 will be described. FIG. 2 is a perspective view showing the appearance of electronic component 1.

[0038] Electronic component 1 further includes a laminate 50 including a plurality of stacked dielectric layers and a plurality of conductors. Laminate 50 is for integrating the first port, the second port, the third port, the first inductor, and the second inductor. In particular, in this embodiment, laminate 50 integrates common port 2, signal ports 3, 4, and resonators 10, 20. Resonators 10, 20 are configured using a plurality of conductors.

[0039] Laminate 50 has a bottom surface 50A and a top surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the top surface 50B. Side surfaces 50C, 50D face opposite sides, and side surfaces 50E, 50F also face opposite sides. Side surfaces 50C to 50F are perpendicular to the top surface 50B and the bottom surface 50A.

[0040] Here, as shown in FIG. 2, the X direction, the Y direction, and the Z direction are defined. The X direction, the Y direction, and the Z direction are orthogonal to each other. In this embodiment, a direction parallel to the stacking direction T is defined as the Z direction. Also, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction.

[0041] As shown in FIG. 2, the bottom surface 50A is located at the -Z direction end of the laminate 50. The top surface 50B is located at the Z direction end of the laminate 50. The shape of each of the bottom surface 50A and the top surface 50B is a rectangular shape that is long in the X direction. The side surface 50C is located at the -X direction end of the laminate 50. The side surface 50D is located at the X direction end of the laminate 50. The side surface 50E is located at the -Y direction end of the laminate 50. The side surface 50F is located at the Y direction end of the laminate 50.

[0042] The electronic component 1 further includes terminals 111, 112, 113, 114, 115, and 116 provided on the bottom surface 50A of the laminate 50. The terminals 114, 111, and 113 are arranged in this order in the X direction at a position closer to the side surface 50E than to the side surface 50F. The terminals 116, 112, and 115 are arranged in this order in the X direction at a position closer to the side surface 50F than to the side surface 50E.

[0043] The terminal 112 corresponds to the common port 2, the terminal 113 corresponds to the signal port 3, and the terminal 114 corresponds to the signal port 4. Therefore, the common port 2 and the signal ports 3 and 4 are provided on the bottom surface 50A of the laminate 50. Each of the terminals 111, 115, and 116 is connected to the ground.

[0044] Next, with reference to FIGS. 3 to 13, an example of a plurality of dielectric layers and a plurality of conductors constituting the laminate 50 will be described. In this example, the laminate 50 has 31 stacked dielectric layers. Hereinafter, these 31 dielectric layers will be referred to as the first to 31st dielectric layers in order from the bottom. Also, the first to 31st dielectric layers are represented by reference numerals 51 to 81.

[0045] In FIGS. 3 to 11, the plurality of circles represent a plurality of through holes. A plurality of through holes are formed in each of the dielectric layers 51 to 79. The plurality of through holes are each formed by filling a conductor paste into a hole for the through hole. Each of the plurality of through holes is connected to a conductor layer or another through hole.

[0046] FIG. 3(a) shows the pattern formation surface of the first dielectric layer 51. Terminals 111 to 116 are formed on the pattern formation surface of the dielectric layer 51.

[0047] FIG. 3(b) shows the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern formation surface of the dielectric layer 52.

[0048] FIG. 3(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, 533, and 534 are formed on the pattern formation surface of the dielectric layer 53.

[0049] FIG. 4(a) shows the pattern formation surface of the fourth dielectric layer 54. Conductor layers 541, 542, 543, 544, 545, and 546 are formed on the pattern formation surface of the dielectric layer 54. The conductor layer 545 is connected to the conductor layer 544.

[0050] FIG. 4(b) shows the pattern formation surface of the fifth dielectric layer 55. Conductor layers 551, 552, 553, 554, 555, 556, and 557 are formed on the pattern formation surface of the dielectric layer 55. The conductor layer 553 is connected to the conductor layer 552. The conductor layers 555 and 556 are connected to the conductor layer 554.

[0051] FIG. 4(c) shows the pattern formation surface of the sixth dielectric layer 56. Conductor layers 561, 562, 563, 564, and 565 are formed on the pattern formation surface of the dielectric layer 56.

[0052] FIG. 5(a) shows the pattern formation surface of the seventh dielectric layer 57. Conductor layers 571, 572, 573, 574, 575, and 576 are formed on the pattern formation surface of the dielectric layer 57. The conductor layer 574 is connected to the conductor layer 573. The conductor layer 576 is connected to the conductor layer 575.

[0053] FIG. 5(b) shows the pattern formation surfaces of the eighth and ninth dielectric layers 58 and 59. No conductor layer is formed on the pattern formation surfaces of the dielectric layers 58 and 59.

[0054] FIG. 5(c) shows the pattern formation surface of the tenth dielectric layer 60. Conductor layers 601 and 602 are formed on the pattern formation surface of the dielectric layer 60. Further, in FIG. 5(c), reference numerals 60T1, 60T2, 60T3, and 60T4 denote through holes for inductors formed in the dielectric layer 60.

[0055] FIG. 6(a) shows the pattern formation surface of the eleventh dielectric layer 61. Conductor layers 611 and 612 are formed on the pattern formation surface of the dielectric layer 61. Further, in FIG. 6(a), reference numerals 61T1, 61T2, 61T3, and 61T4 denote through holes for inductors formed in the dielectric layer 61.

[0056] FIG. 6(b) shows the pattern formation surface of the twelfth dielectric layer 62. Conductor layers 621 and 622 are formed on the pattern formation surface of the dielectric layer 62. Further, in FIG. 6(b), reference numerals 62T1, 62T2, 62T3, and 62T4 denote through holes for inductors formed in the dielectric layer 62.

[0057] FIG. 6(c) shows the pattern formation surface of the thirteenth dielectric layer 63. Conductor layers 631, 632, and 633 are formed on the pattern formation surface of the dielectric layer 63. Further, in FIG. 6(c), reference numerals 63T1, 63T2, 63T3, and 63T4 denote through holes for inductors formed in the dielectric layer 63.

[0058] FIG. 7(a) shows the pattern formation surface of the fourteenth dielectric layer 64. Conductor layers 641, 642, and 643 are formed on the pattern formation surface of the dielectric layer 64. Further, in FIG. 7(a), reference numerals 64T1, 64T2, 64T3, and 64T4 denote through holes for inductors formed in the dielectric layer 64.

[0059] Figure 7(b) shows the pattern formation surface of the 15th dielectric layer 65. Conductor layers 651, 652, and 653 are formed on the pattern formation surface of the dielectric layer 65. Also, in Figure 7(b), reference numerals 65T1, 65T2, 65T3, and 65T4 indicate through holes for inductors formed in the dielectric layer 65.

[0060] Figure 7(c) shows the pattern formation surface of the 16th dielectric layer 66. Conductor layers 661, 662, and 663 are formed on the pattern formation surface of the dielectric layer 66. Also, in Figure 7(c), reference numerals 66T1, 66T2, 66T3, and 66T4 indicate through holes for inductors formed in the dielectric layer 66.

[0061] Figure 8(a) shows the pattern formation surface of the 17th dielectric layer 67. Conductor layers 671, 672, and 673 are formed on the pattern formation surface of the dielectric layer 67. Also, in Figure 8(a), reference numerals 67T1, 67T2, 67T3, and 67T4 indicate through holes for inductors formed in the dielectric layer 67.

[0062] Figure 8(b) shows the pattern formation surface of the 18th dielectric layer 68. Conductor layers 681, 682, and 683 are formed on the pattern formation surface of the dielectric layer 68. Also, in Figure 8(b), reference numerals 68T1, 68T2, 68T3, and 68T4 indicate through holes for inductors formed in the dielectric layer 68.

[0063] Figure 8(c) shows the pattern formation surfaces of the 19th and 20th dielectric layers 69 and 70. No conductor layers are formed on the pattern formation surfaces of the dielectric layers 69 and 70. Also, in Figure 8(c), reference numerals 69T1, 69T2, 69T3, and 69T4 indicate through holes for inductors formed in the dielectric layers 69 and 70.

[0064] Figure 9(a) shows the pattern formation surface of the 21st dielectric layer 71. Conductor layers 711 and 712 are formed on the pattern formation surface of the dielectric layer 71.

[0065] Figure 9(b) shows the pattern formation surface of the 22nd dielectric layer 72. No conductor layer is formed on the pattern formation surface of the dielectric layer 72.

[0066] Figure 9(c) shows the pattern formation surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, and 734 are formed on the pattern formation surface of the dielectric layer 73.

[0067] Figure 10(a) shows the pattern formation surface of the 24th dielectric layer 74. Conductor layers 741, 742, 743, and 744 are formed on the pattern formation surface of the dielectric layer 74.

[0068] Figure 10(b) shows the pattern formation surface of the 25th dielectric layer 75. Conductor layers 751, 752, and 753 are formed on the pattern formation surface of the dielectric layer 75.

[0069] Figure 10(c) shows the pattern formation surface of the 26th dielectric layer 76. Conductor layers 761, 762, and 763 are formed on the pattern formation surface of the dielectric layer 76.

[0070] Figure 11(a) shows the pattern formation surface of the 27th dielectric layer 77. Conductor layers 771, 772, and 773 are formed on the pattern formation surface of the dielectric layer 77.

[0071] Figure 11(b) shows the pattern formation surface of the 28th dielectric layer 78. Conductor layers 781, 782, and 783 are formed on the pattern formation surface of the dielectric layer 78.

[0072] Figure 11(c) shows the pattern formation surface of the 29th dielectric layer 79. Conductor layers 791, 792, and 793 are formed on the pattern formation surface of the dielectric layer 79.

[0073] Figure 12(a) shows the pattern formation surface of the 30th dielectric layer 80. Conductor layers 801, 802, and 803 are formed on the pattern formation surface of the dielectric layer 80.

[0074] FIG. 12(b) shows the pattern formation surface of the 31st dielectric layer 81. A mark 811 made of a conductor layer is formed on the pattern formation surface of the dielectric layer 81.

[0075] The laminate 50 shown in FIG. 2 is configured by laminating the 1st to 31st dielectric layers 51 to 81 such that the pattern formation surface of the 1st dielectric layer 51 becomes the bottom surface 50A of the laminate 50, and the surface on the opposite side of the pattern formation surface of the 31st dielectric layer 81 becomes the top surface 50B of the laminate 50.

[0076] Each of the plurality of through holes shown in FIGS. 3 to 11 is connected to a conductor layer overlapping in the stacking direction T or another through hole overlapping in the stacking direction T when the 1st to 29th dielectric layers 51 to 79 are laminated. Among the plurality of through holes shown in FIGS. 3 to 11, the through holes located within the terminal or the conductor layer are connected to that terminal or that conductor layer.

[0077] FIG. 13 shows the inside of the laminate 50 configured by laminating the 1st to 31st dielectric layers 51 to 81. As shown in FIG. 13, inside the laminate 50, the plurality of conductor layers and the plurality of through holes shown in FIGS. 3 to 12 are laminated. Note that in FIG. 13, the mark 811 is omitted. Also, in FIG. 13, for ease of understanding, the dimensions of the laminate 50 in the stacking direction T are drawn larger than the actual ones.

[0078] Hereinafter, the correspondence between the components of the circuit of the electronic component 1 shown in FIG. 1 and the components inside the laminate 50 shown in FIGS. 3 to 12 will be described. First, the components of the resonator 10 will be described. The inductor L11 is composed of the conductor layers 731, 741, 751, 761, 771, 781, 791, 801 shown in FIGS. 9(c) to 12(a) and a plurality of through holes connected to these conductor layers.

[0079] The inductor L12 is composed of conductor layers 611, 621, 631, 641, 651, 661, 671, 681 shown in FIGS. 6(a) to 8(b) and a plurality of through holes connected to these conductor layers.

[0080] The inductor L13 is composed of the conductor layer 521 shown in FIG. 3(b).

[0081] The capacitor C11 is composed of conductor layers 531, 541, 551, 561 shown in FIGS. 3(c) to 4(c) and dielectric layers 53 to 55 between these conductor layers.

[0082] The capacitor C12 is composed of conductor layers 531, 542, 551 shown in FIGS. 3(c) to 4(b) and dielectric layers 53, 54 between these conductor layers.

[0083] The capacitor C13 is composed of conductor layers 561, 571 shown in FIGS. 4(c) and 5(a) and dielectric layer 56 between these conductor layers.

[0084] Next, the components of the LC circuit 24 of the resonator 20 will be described. The inductor L21 is composed of conductor layers 612, 622, 632, 642, 652, 662, 672, 682 shown in FIGS. 6(a) to 8(b) and a plurality of through holes connected to these conductor layers.

[0085] The capacitor C21 is composed of terminal 112 and conductor layer 543 shown in FIGS. 3(a) and 4(a), terminal 112 and conductor layer 543 and and dielectric layers 51 to 53 therebetween.

[0086] The capacitor C22 is composed of terminal 116 and conductor layer 532 shown in FIGS. 3(a) and 3(c), terminal 116 and conductor layer 532 and and dielectric layers 51, 52 therebetween.

[0087] Next, the components of the LC circuit 25 of the resonator 20 will be described. The inductor L22 is composed of the conductor layers 732, 742, 752, 762, 772, 782, 792, 802 shown in FIGS. 9(c) to 12(a) and a plurality of through holes connected to these conductor layers.

[0088] The inductor L23 is composed of the conductor layers 733, 743, 753, 763, 773, 783, 793, 803 shown in FIGS. 9(c) to 12(a) and a plurality of through holes connected to these conductor layers.

[0089] The capacitor C23 is composed of the conductor layers 543, 552, 562 shown in FIGS. 4(a) to 4(c) and the dielectric layers 54, 55 between these conductor layers.

[0090] The capacitor C24 is composed of the conductor layers 553, 563 shown in FIGS. 4(b) and 4(c) and the dielectric layer 55 between these conductor layers.

[0091] The capacitor C25 is composed of the conductor layers 554, 563 shown in FIGS. 4(b) and 4(c) and the dielectric layer 55 between these conductor layers.

[0092] The capacitor C26 is composed of the conductor layers 544, 555, 564 shown in FIGS. 4(a) to 4(c) and the dielectric layers 54, 55 between these conductor layers.

[0093] The capacitor C27 is composed of the conductor layers 562, 573 shown in FIGS. 4(c) and 5(a) and the dielectric layer 56 between these conductor layers.

[0094] The capacitor C28 is composed of the conductor layers 564, 574 shown in FIGS. 4(c) and 5(a) and the dielectric layer 56 between these conductor layers.

[0095] Capacitor C29 is composed of conductor layers 545 and 553 shown in FIGS. 4(a) and 4(b), and dielectric layer 54 between these conductor layers.

[0096] Capacitor C30 is composed of conductor layers 532 and 556 shown in FIGS. 3(c) and 4(b), and dielectric layers 53 and 54 between these conductor layers.

[0097] Next, the components of LC circuit 26 of resonator 20 will be described. Inductor L24 is composed of conductor layers 633, 643, 653, 663, 673, and 683 shown in FIGS. 6(c) to 8(b), and a plurality of through-holes connected to these conductor layers.

[0098] Inductor L25 is composed of conductor layers 601, 711, and 712 shown in FIGS. 5(c) and 9(a), and through-holes 60T1 to 60T4, 61T1 to 61T4, 62T1 to 62T4, 63T1 to 63T4, 64T1 to 64T4, 65T1 to 65T4, 66T1 to 66T4, 67T1 to 67T4, 68T1 to 68T4, 69T1 to 69T4 shown in FIGS. 5(c) to 9(a).

[0099] Through-holes 60T1, 61T1, 62T1, 63T1, 64T1, 65T1, 66T1, 67T1, 68T1, 69T1 are connected in series. Through-holes 60T2, 61T2, 62T2, 63T2, 64T2, 65T2, 66T2, 67T2, 68T2, 69T2 are connected in series. Through-holes 60T3, 61T3, 62T3, 63T3, 64T3, 65T3, 66T3, 67T3, 68T3, 69T3 are connected in series. Through-holes 60T4, 61T4, 62T4, 63T4, 64T4, 65T4, 66T4, 67T4, 68T4, 69T4 are connected in series.

[0100] The through-hole 69T1 formed in the dielectric layer 70 is connected to the vicinity of one end of the conductor layer 711. The through-hole 69T2 formed in the dielectric layer 70 is connected to the vicinity of the other end of the conductor layer 711. The through-hole 60T2 formed in the dielectric layer 60 is connected to the vicinity of one end of the conductor layer 601. The through-hole 60T3 formed in the dielectric layer 60 is connected to the vicinity of the other end of the conductor layer 601. The through-hole 69T3 formed in the dielectric layer 70 is connected to the vicinity of one end of the conductor layer 712. The through-hole 69T4 formed in the dielectric layer 70 is connected to the vicinity of the other end of the conductor layer 712.

[0101] The capacitor C31 is composed of the conductor layers 533 and 544 shown in FIGS. 3(c) and 4(a), and the dielectric layer 53 between these conductor layers.

[0102] The capacitor C32 is composed of the conductor layers 522 and 534 shown in FIGS. 3(b) and 3(c), and the dielectric layer 52 between these conductor layers.

[0103] The capacitor C33 is composed of the conductor layers 564 and 575 shown in FIGS. 4(c) and 5(a), and the dielectric layer 56 between these conductor layers.

[0104] The capacitor C34 is composed of the conductor layers 534, 546, 557, 565, and 576 shown in FIGS. 3(c) to 5(a), and the dielectric layers 53 to 56 between these conductor layers.

[0105] Next, with reference to FIGS. 1, 13, and 14, the structural features of the electronic component 1 according to the present embodiment will be described. FIG. 14 is a cross-sectional view showing a part inside the laminate 50 shown in FIG. 13. In the present embodiment, the inductor L24 of the LC circuit 26 of the resonator 20 corresponds to the first inductor, and the inductor L25 of the LC circuit 26 of the resonator 20 corresponds to the second inductor.

[0106] Hereinafter, the inductor L24 is also referred to as the first inductor L24, and the inductor L25 is also referred to as the second inductor L25. As shown in FIG. 1, the first inductor L24 and the second inductor L25 are included in the resonator 20 and are provided in series in the path 23 of the resonator 20. The path 23 is a part of the path connecting the common port 2 (the first port) and the signal port 4 (the second port). The first inductor L24 has a first end closest to the common port 2 (the first port) in terms of circuit configuration and a second end on the side opposite to the first end. The second end of the first inductor L24 is connected to one end of the second inductor L25.

[0107] The laminate 50 includes a first inductor conductor L24c constituting the first inductor L24 and a second inductor conductor L25c constituting the second inductor L25. The first inductor conductor L24c is a conductor structure composed of conductor layers 633, 643, 653, 663, 673, 683 and a plurality of through holes connected to these conductor layers. The second inductor conductor L25c is a conductor structure composed of conductor layers 601, 711, 712 and through holes 60T1 to 60T4, 61T1 to 61T4, 62T1 to 62T4, 63T1 to 63T4, 64T1 to 64T4, 65T1 to 65T4, 66T1 to 66T4, 67T1 to 67T4, 68T1 to 68T4, 69T1 to 69T4. In FIG. 14, the first and second inductor conductors L24c, L25c are shown using solid lines and dashed lines.

[0108] The reference sign A1 in FIG. 14 indicates an axis passing through the space surrounded by the conductor layers 633, 643, 653, 663, 673, 683. The first inductor conductor L24c is wound around the axis A1 extending in the first direction.

[0109] Reference numeral A2 in FIG. 14 indicates an axis passing through a space surrounded by conductor layers 601, 711, 712 and through holes 60T1 to 60T4, 61T1 to 61T4, 62T1 to 62T4, 63T1 to 63T4, 64T1 to 64T4, 65T1 to 65T4, 66T1 to 66T4, 67T1 to 67T4, 68T1 to 68T4, 69T1 to 69T4. The second inductor conductor L25c is wound around axis A2 extending in a second direction intersecting the first direction.

[0110] In the present embodiment, the first direction and the second direction are orthogonal to each other. Also, one of the first direction and the second direction is parallel to the stacking direction T. In the present embodiment, the first direction is a direction parallel to the Z direction and parallel to the stacking direction T. Axis A1 extends in a direction parallel to the stacking direction T. Also, the second direction is a direction parallel to the X direction. Axis A2 extends in a direction orthogonal to the stacking direction T.

[0111] Here, an inductor conductor wound around an axis extending in a direction parallel to the stacking direction T is referred to as a horizontal inductor conductor, and an inductor conductor wound around an axis extending in a direction orthogonal to the stacking direction T is referred to as a vertical inductor conductor. In the present embodiment, the first inductor conductor L24c is a horizontal inductor conductor, and the second inductor conductor L25c is a vertical inductor conductor.

[0112] As described above, the shape of each of the bottom surface 50A and the top surface 50B of the laminate 50 is a rectangular shape long in the X direction. Among the four side surfaces 50C, 50D, 50E, 50F of the laminate 50, the side surfaces 50C, 50D are located at both ends in the longitudinal direction of the rectangular shape. As shown in FIG. 14, the second inductor conductor L25c, which is a vertical inductor conductor, is disposed closer to the side surface 50C than to the side surface 50D. The distance from the second inductor conductor L25c to the side surface 50C is smaller than the distance from the first inductor conductor L24c, which is a horizontal inductor conductor, to the side surface 50C.

[0113] The laminate 50 further includes a resonator conductor that constitutes the resonator 10. The resonator conductor is a conductor structure including a plurality of conductor layers that constitute each of the inductors L11 to L13 and the capacitors C11 to C13, and a plurality of through holes connected to the plurality of conductor layers. In FIG. 14, among the resonator conductors, the plurality of conductor layers that constitute the inductors L11 to L13 are shown using broken lines. The resonator conductor is disposed at a position closer to the side surface 50D than the side surface 50C. Therefore, the second inductor conductor L25c, which is a vertical inductor conductor, is disposed at a position farther from the resonator conductor than the first inductor conductor L24c, which is a horizontal inductor conductor. Also, the second inductor conductor L25c is disposed at a position farther from the plurality of conductor layers that constitute the inductors L11 to L13 than the first inductor conductor L24c.

[0114] Next, an example of the characteristics of the electronic component 1 according to the present embodiment will be shown. FIG. 15 is a characteristic diagram showing an example of the passing attenuation characteristic and the reflection attenuation characteristic of the electronic component 1. In FIG. 15, the curve marked with reference numeral 91 shows the passing attenuation characteristic of the second filter constituted by the resonator 10 provided between the common port 2 and the signal port 3. Also, the curve marked with reference numeral 92 shows the passing attenuation characteristic of the first filter constituted by the resonator 20 provided between the common port 2 and the signal port 4. Also, the curve marked with reference numeral 93 shows the reflection attenuation characteristic at the common port 2.

[0115] FIG. 16 is a characteristic diagram showing the insertion loss of the first filter. FIG. 17 is a characteristic diagram showing the reflection loss of the first filter. In FIG. 16, the horizontal axis represents the frequency, and the vertical axis represents the insertion loss. In FIG. 17, the horizontal axis represents the frequency, and the vertical axis represents the reflection loss.

[0116] Next, the operation and effects of the electronic component 1 according to the present embodiment will be described. As described above, in the present embodiment, the second end of the first inductor L24 is connected to one end of the second inductor L25. When the electronic component 1 is miniaturized, the distance between two inductors that are close to each other in the circuit configuration, such as the first and second inductors L24 and L25, becomes smaller, and the electromagnetic field coupling between the two inductors becomes stronger. In particular, when two inductor conductors constituting two inductors, like those described in Patent Document 1, are both wound around an axis extending in the same direction and are arranged such that one of the two inductor conductors overlaps the other when viewed from the axial direction, the electromagnetic field coupling between the two inductors tends to become stronger.

[0117] In contrast, in the present embodiment, the first inductor conductor L24c constituting the first inductor L24 is wound around an axis A1 extending in the first direction, and the second inductor conductor L25c constituting the second inductor L25 is wound around an axis A2 extending in a second direction intersecting the first direction. Thus, according to the present embodiment, compared with the above case, the electromagnetic field coupling between the first inductor L24 and the second inductor L25 can be suppressed. Thereby, according to the present embodiment, while miniaturizing the electronic component 1, desired characteristics can be realized. Specifically, as shown in FIG. 15, the attenuation in the passband can be increased in a frequency band (about 3 GHz to about 8 GHz) higher than the first passband.

[0118] Also, in the present embodiment, the first direction and the second direction are orthogonal to each other. Thus, according to the present embodiment, the electromagnetic field coupling between the first inductor L24 and the second inductor L25 can be further suppressed.

[0119] Incidentally, the vertical inductor conductor is more likely to be electromagnetically coupled to other conductors arranged in a direction orthogonal to the stacking direction T than the horizontal inductor conductor. In the present embodiment, the first inductor conductor L24c is a horizontal inductor conductor, and the second inductor conductor L25c is a vertical inductor conductor. The first and second inductor conductors L24c and L25c are arranged in the above-described positional relationship with respect to the side surface 50C. Thus, according to the present embodiment, when the distance from the second inductor conductor L25c to the side surface 50C is larger than the distance from the first inductor conductor L24c to the side surface 50C, the distance from other conductors arranged on the side surface 50D side can be increased. As a result, according to the present embodiment, it is possible to suppress the second inductor conductor L25c from being electromagnetically coupled to other conductors arranged on the side surface 50D side.

[0120] Further, the electronic component 1 according to the present embodiment is a diplexer including a resonator 10 provided between a common port 2 and a signal port 3, and a resonator 20 provided between the common port 2 and the signal port 4 The first and second inductors L24 and L25 are included in the resonator 20. The first and second inductor conductors L24c and L25c are arranged in the above-described positional relationship with respect to the resonator conductors constituting the resonator 10. Thus, according to the present embodiment, it is possible to prevent the isolation characteristics between the signal port 3 and the signal port 4 from deteriorating due to the second inductor conductor L25c included in the resonator 20 being electromagnetically coupled to the resonator conductors constituting the resonator 10.

[0121] Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the electronic component of the present invention may be an electronic component including only the resonator 20 as a circuit component, or may be an electronic component including only the LC circuit 26 as a circuit component. The electronic component including only the resonator 20 functions as a band-pass filter. The electronic component including only the LC circuit 26 functions as a low-pass filter.

[0122] In addition, the first and second inductor conductors of the present invention can also be applied to two inductors other than inductors L24 and L25 as long as the requirement that the second end of the first inductor is connected to one end of the second inductor is satisfied. Specifically, the first and second inductor conductors of the present invention can also be applied to inductors L11 and L12 of resonator 10 and inductors L22 and L23 of LC circuit 25 of resonator 20. Both the pair of inductors L11 and L12 and the pair of inductors L22 and L23 satisfy the requirement that the second end of the first inductor is connected to one end of the second inductor.

[0123] Also, the second end of the first inductor may be directly connected to one end of the second inductor or may be indirectly connected.

[0124] Also, contrary to the embodiment, the first inductor conductor constituting the first inductor L24 may be a vertical inductor conductor, and the second inductor L25 conductor constituting the second inductor may be a horizontal inductor conductor.

Description of Reference Numerals

[0125] 1... electronic component, 2... common port, 3, 4... signal ports, 10, 20... resonators, 24 - 26... LC circuits, 50... laminate, 50A... bottom surface, 50B... top surface, 50C - 50F... side surfaces, 51 - 81... dielectric layers, L24... first inductor, L25... second inductor.

Claims

1. A first port, a second port that allows a signal input to the first port to pass through, a first inductor and a second inductor provided between the first port and the second port in terms of circuit configuration, including a plurality of stacked dielectric layers and a plurality of conductors, and comprising a laminate for integrating the first port, the second port, the first inductor, and the second inductor, the first inductor has a first end closest to the first port in terms of circuit configuration and a second end opposite to the first end, the second end of the first inductor is directly connected to one end of the second inductor in terms of circuit configuration, the laminate includes a first inductor conductor constituting the first inductor and a second inductor conductor constituting the second inductor, the first inductor conductor is wound around an axis extending in a first direction, the second inductor conductor is wound around an axis extending in a second direction intersecting the first direction, the first direction and the second direction are orthogonal to each other, a stacked electronic component as described above, characterized in that one of the first direction and the second direction is parallel to the stacking direction of the plurality of dielectric layers.

2. The stacked electronic component according to Claim 1, wherein the first inductor and the second inductor are provided in series in a path connecting the first port and the second port.

3. Furthermore, it comprises a first resonator provided between the first port and the second port in terms of circuit configuration, The stacked electronic component according to Claim 1 or 2, wherein the first inductor and the second inductor are included in the first resonator.

4. Furthermore, it comprises a third port, The stacked electronic component according to Claim 3, characterized in that it further comprises a second resonator provided between the first port and the third port in terms of circuit configuration.

5. One of the second port and the third port is a first signal port that selectively passes a first signal having a frequency within a first passband, The stacked electronic component according to Claim 4, characterized in that the other of the second port and the third port is a second signal port that selectively passes a second signal having a frequency within a second passband lower than the first passband.

6. The second port is the first signal port, The stacked electronic component according to claim 5, wherein the third port is the second signal port.

7. The laminate further includes a second resonator conductor that constitutes the second resonator. One of the first inductor conductor and the second inductor conductor is a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The other of the first inductor conductor and the second inductor conductor is a vertical inductor conductor wound around an axis extending in a direction perpendicular to the stacking direction of the plurality of dielectric layers. The stacked electronic component according to any one of claims 4 to 6, wherein the vertical inductor conductor is disposed at a position farther from the second resonator conductor than the horizontal inductor conductor.

8. The laminate has a bottom surface and an upper surface located at both ends in the stacking direction of the plurality of dielectric layers, and four side surfaces connecting the bottom surface and the upper surface. Each of the bottom surface and the upper surface has a rectangular shape that is long in one direction. The four side surfaces include a first side surface and a second side surface located at both ends in the longitudinal direction of the rectangular shape. One of the first inductor conductor and the second inductor conductor is a horizontal inductor conductor wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The other of the first inductor conductor and the second inductor conductor is a vertical inductor conductor wound around an axis extending in a direction perpendicular to the stacking direction of the plurality of dielectric layers. The vertical inductor conductor is disposed closer to the first side surface than the second side surface. The stacked electronic component according to any one of claims 4 to 6, wherein the distance from the vertical inductor conductor to the first side surface is smaller than the distance from the horizontal inductor conductor to the first side surface.

9. The stacked electronic component according to any one of claims 1 to 8, wherein the first inductor conductor and the second inductor conductor are adjacent to each other in the second direction.

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