Semiconductor memory device

Abstract

To provide a semiconductor storage device which can be high integrated.SOLUTION: A semiconductor storage device (a memory die) comprises a first chip CM and a second chip CP, which are adhered via a plurality of adhesion electrodes MB and DB. The first chip comprises a semiconductor substrate 200. The second chip comprises: a plurality of first conductive layers 110; a plurality of semiconductive layers 120 opposite to the plurality of first conductive layers; a first wiring layer M0 containing a plurality of bit lines BL; a second wiring layer M1 containing a plurality of wires; and a third wiring layer containing a plurality of first adhesion electrodes PI1. Each of the plurality of wirings in the second wiring layer is provided to a region overlapping one of the plurality of bit lines in view of a first direction, and comprises: a first part that is electrically connected to one of the plurality of bit lines; and a second part that is provided to a region overlapping one of the plurality of first adhesion electrodes in view of the first direction, and is connected to the one of the plurality of first adhesion electrodes.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] A semiconductor memory device including a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layer is known. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer such as silicon nitride (SiN) or a conductive charge storage layer such as a floating gate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of high integration.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment includes a first chip and a second chip bonded via a plurality of bonding electrodes. The first chip includes a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate. The second chip includes a plurality of first conductive layers, a plurality of semiconductor layers, a first wiring layer, a second wiring layer, and a second chip bonding electrode layer. The plurality of first conductive layers are arranged in a first direction intersecting the surface of the semiconductor substrate. The plurality of semiconductor layers extend in the first direction and face the plurality of first conductive layers. The first wiring layer is provided between the plurality of semiconductor layers and the first chip and includes a plurality of bit lines electrically connected to the plurality of semiconductor layers. The second wiring layer is provided between the first wiring layer and the first chip and includes a plurality of wirings. The third wiring layer is provided between the second wiring layer and the first chip and includes a plurality of first bonding electrodes which are a part of the plurality of bonding electrodes. The plurality of bit lines extend in a second direction intersecting the first direction and are arranged in a third direction intersecting the first direction and the second direction. Each of the plurality of wirings in the second wiring layer includes a first portion and a second portion. The first portion is provided in a region overlapping one of the plurality of bit lines when viewed from the first direction, extends in the second direction, and is electrically connected to one of the plurality of bit lines. The second portion is provided in a region overlapping one of the plurality of first bonding electrodes when viewed from the first direction and is connected to one of the plurality of first bonding electrodes. At least a part of the plurality of wirings in the second wiring layer each includes a third portion. The third portion extends in the third direction and is connected to one end portion in the second direction of the first portion and one end portion in the second direction of the second portion.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Next, the semiconductor memory device according to the embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations etc. may be omitted. Further, the same reference numerals are given to common parts in a plurality of embodiments, and the description may be omitted.

[0008] Also, in this specification, when referring to a "semiconductor memory device", it may mean a memory die, or may mean a memory system including a controller die such as a memory chip, a memory card, an SSD (Solid State Drive), etc. Further, it may mean a configuration including a host computer such as a smartphone, a tablet terminal, a personal computer, etc.

[0009] Also, in this specification, when it is said that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Also, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0011] Also, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, for example, this circuit or the like includes a transistor or the like, this transistor or the like is provided in the current path between the two wirings, and this may mean that this transistor or the like is in an ON state.

[0012] Also, in this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] Also, in this specification, a direction along a predetermined plane may be called the first direction, a direction intersecting the first direction along this predetermined plane may be called the second direction, and a direction intersecting this predetermined plane may be called the third direction. These first direction, second direction, and third direction may or may not correspond to any of the X direction, Y direction, and Z direction.

[0014] Also, in this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called upper, and the direction approaching the substrate along the Z direction is called lower. Also, when referring to the lower surface or lower end of a certain configuration, it means the surface or end on the substrate side of this configuration, and when referring to the upper surface or upper end, it means the surface or end on the side opposite to the substrate of this configuration. Also, a surface intersecting the X direction or Y direction is called a side surface or the like.

[0015] In addition, in this specification, when referring to the "width", "length", "thickness", etc. of a structure, member, etc. in a predetermined direction, it may mean the width, length, thickness, etc. in a cross-section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), or the like.

[0016] [First Embodiment] [Circuit Configuration of Memory Die MD] FIG. 1 is a schematic circuit diagram showing a partial configuration of a memory die MD. As shown in FIG. 1, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. As shown in FIG. 1, the memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string units SU. Each of these plurality of string units SU includes a plurality of memory strings MS. One end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. Also, the other end of each of these plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0017] The memory string MS includes a drain-side selection transistor STD, a plurality of memory cells MC (memory transistors), and a source-side selection transistor STS. The drain-side selection transistor STD, the plurality of memory cells MC, and the source-side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may be simply referred to as selection transistors (STD, STS).

[0018] The memory cell MC is a field-effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multiple bits of data. Note that word lines WL are respectively connected to the gate electrodes of multiple memory cells MC corresponding to one memory string MS. These word lines WL are commonly connected to all the memory strings MS in one memory block BLK.

[0019] The selection transistor (STD, STS) is a field-effect transistor. The selection transistor (STD, STS) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. Selection gate lines (SGD, SGS) are respectively connected to the gate electrodes of the selection transistors (STD, STS). One drain-side selection gate line SGD is commonly connected to all the memory strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all the memory strings MS in one memory block BLK.

[0020] FIG. 2 is a schematic circuit diagram showing a partial configuration of the peripheral circuit PC. The peripheral circuit PC includes, for example, a row control circuit RowC as shown in FIG. 2. The row control circuit RowC includes a plurality of block decoding units blkd and a block decoder BLKD.

[0021] The plurality of block decoding units blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. The block decoding unit blkd includes a plurality of transistors T BLK . The plurality of transistors T BLK correspond to the plurality of word lines WL in the memory block BLK. The transistor T BLK is, for example, a field-effect NMOS transistor. The transistor TBLK The drain electrode of BLK transistor T is connected to the word line WL. The source electrode of transistor T BLK is connected to the wiring CG. The wiring CG is connected to all block decoding units blkd in the row control circuit RowC. The gate electrode of transistor T BLK is connected to the signal supply line BLKSEL. A plurality of signal supply lines BLKSEL are provided corresponding to all block decoding units blkd. Also, the signal supply line BLKSEL is connected to all transistors T

[0022] in the block decoding unit blkd.

[0023] The block decoder BLKD decodes the block address during a read operation or a write operation. Also, according to the decoded block address, one of the plurality of signal supply lines BLKSEL is set to the "H" state, and the remaining signal supply lines BLKSEL are set to the "L" state.

[0024] The switch transistors BLS, BLBIAS are, for example, field effect type NMOS transistors. The drain electrodes of the switch transistors BLS, BLBIAS are connected to the bit line BL. The source electrode of the switch transistor BLS is connected to the sense amplifier circuit SADL. The source electrode of the switch transistor BLBIAS is connected to a voltage supply line (not shown).

[0025] The sense amplifier circuit SADL includes a sense circuit, a latch circuit, and a voltage transfer circuit. The sense circuit includes a sense transistor and a data wiring. The gate electrode of the sense transistor is electrically connected to the bit line BL. The drain electrode of the sense transistor is connected to the data wiring. The sense transistor turns on according to the voltage or current of the bit line BL. The data wiring is charged or discharged according to the ON / OFF state of the sense transistor. The latch circuit latches "1" or "0" data according to the voltage of the data wiring. The voltage transfer circuit connects the bit line BL to one of two voltage supply lines according to the data latched by the latch circuit.

[0026] The latch circuit XDL is electrically connected to the data wiring in the sense amplifier circuit SADL via the wiring DBUS. The data included in the latch circuit XDL is sequentially transferred to the sense amplifier circuit SADL or an input / output control circuit (not shown). [Structure of Memory Die MD] FIG. 4 is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the present embodiment. As shown in FIG. 4, the memory die MD includes a chip C on the memory cell array MCA side M and a chip C on the peripheral circuit PC side P and includes them.

[0027] Chip C M has a plurality of external pad electrodes P connectable to bonding wires (not shown) on its upper surface X . Also, a plurality of bonding electrodes P M are provided on the lower surface of the chip C I1 . Also, a plurality of bonding electrodes P P are provided on the upper surface of the chip C I2 . Hereinafter, for the chip C M , the surface on which the plurality of bonding electrodes P I1 are provided is called the front surface, and the surface on which the plurality of external pad electrodes P X are provided is called the back surface. Also, for the chip C P , the plurality of bonding electrodes P I2The surface on which it is provided is called the front surface, and the surface on the opposite side of the front surface is called the back surface. In the illustrated example, chip C P 's front surface is provided above the back surface of chip C P , and the back surface of chip C M is provided above the front surface of chip C M .

[0028] Chip C M and chip C P are arranged such that the front surface of chip C M faces the front surface of chip C P . A plurality of bonding electrodes P I1 are provided corresponding to the plurality of bonding electrodes P I2 respectively, and are arranged at positions where they can be bonded to the plurality of bonding electrodes P I2 . The bonding electrode P I1 and the bonding electrode P I2 function as bonding electrodes for bonding chip C M and chip C P and electrically connecting them.

[0029] In addition, in the example of FIG. 4, the corner portions a1, a2, a3, a4 of chip C M respectively correspond to the corner portions b1, b2, b3, b4 of chip C P .

[0030] FIG. 5 is a schematic bottom view showing a configuration example of chip C M . In FIG. 5, some configurations such as the bonding electrode P I1 are omitted. FIGS. 6 and 7 are schematic cross-sectional views showing some configurations of the memory die MD. FIG. 8 is a schematic bottom view showing some configurations of chip C M . FIG. 9 is a schematic cross-sectional view showing some configurations of chip C M . Although FIG. 9 shows a YZ cross-section, the same structure as FIG. 9 is observed even when observing a cross-section other than the YZ cross-section along the central axis of the semiconductor layer 120 (for example, an XZ cross-section). FIG. 10 is a schematic plan view showing a configuration example of chip C P . In FIG. 10, the bonding electrode P I2Some components such as etc. are omitted. FIG. 11 is a schematic plan view showing an enlarged part of FIG. 10. FIGS. 12 and 13 are schematic plan views showing an enlarged part of FIG. 11.

[0031] [Chip C M 's structure] In the example of FIG. 5, chip C M comprises four memory planes MP arranged in the X direction. Further, each of these four memory planes MP comprises a plurality of memory blocks BLK arranged in the Y direction. Also, in the example of FIG. 5, the plurality of memory blocks BLK each comprise a hook-up region R provided at both ends in the X direction HU and a memory hole region R provided between them MH . Also, chip C M comprises a peripheral region R provided on one end side in the Y direction relative to the four memory planes MP P .

[0032] In addition, in the illustrated example, the hook-up region R HU is provided at both ends in the X direction of the memory plane MP. However, such a configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the hook-up region R HU may be provided at one end in the X direction instead of both ends in the X direction of the memory plane MP. Also, the hook-up region R HU may be provided at the central position or a position near the center in the X direction of the memory plane MP.

[0033] Chip C M comprises, for example, as shown in FIG. 6, a substrate layer L SB and a memory cell array layer L SB provided below the substrate layer L MCA and a via contact electrode layer CH provided below the memory cell array layer L MCA and a plurality of wiring layers M0, M1 provided below the via contact electrode layer CH, and a chip bonding electrode layer MB provided below the wiring layers M0, M1.

[0034] [Chip CM substrate layer L SB structure] For example, as shown in FIG. 6, the substrate layer L SB is provided with a conductive layer 100 provided on the upper surface of the memory cell array layer L MCA an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0035] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) into which an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B) is implanted, or may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0036] The conductive layer 100 functions as part of the source line SL (FIG. 1). Four conductive layers 100 are provided corresponding to the four memory planes MP (FIG. 5). Regions VZ not including the conductive layer 100 are provided at the ends of the memory plane MP in the X and Y directions.

[0037] The insulating layer 101 includes, for example, silicon oxide (SiO2) or the like.

[0038] The back surface wiring layer MA includes a plurality of wirings ma. These plurality of wirings ma may include, for example, aluminum (Al) or the like.

[0039] Some of the plurality of wirings ma function as part of the source line SL (FIG. 1). Four such wirings ma are provided corresponding to the four memory planes MP (FIG. 5). Each of these wirings ma is electrically connected to the conductive layer 100.

[0040] Also, some of the plurality of wirings ma function as external pad electrodes P X and are provided in the peripheral region R P and are provided in the region VZ that does not include the conductive layer 100 in the memory cell array layer L MCAIt is connected to the via contact electrode CC in the [chip C]. Also, a part of the wiring ma is exposed to the outside of the memory die MD through the opening TV provided in the insulating layer 102.

[0041] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide, for example.

[0042] [Memory cell array layer L of chip C M of MCA memory hole region R MH in the structure of As described with reference to FIG. 5, the memory cell array layer L MCA is provided with a plurality of memory blocks BLK arranged in the Y direction. As shown in FIG. 6, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks BLK in the Y direction.

[0043] The memory block BLK includes, for example, as shown in FIG. 6, a plurality of conductive layers 110 arranged in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Also, as shown in FIG. 9, a gate insulating film 130 is provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

[0044] The conductive layer 110 has a substantially plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) and molybdenum (Mo), for example. Also, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 made of silicon oxide (SiO2) or the like is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0045] Among the plurality of conductive layers 110, one or more conductive layers 110 located at the uppermost layer function as the gate electrode of the source-side selection transistor STS (FIG. 1) and the source-side selection gate line SGS (see FIG. 6). These plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0046] Further, a plurality of conductive layers 110 located below the above function as gate electrodes of memory cells MC (FIG. 1) and word lines WL. Each of the plurality of conductive layers 110 is electrically independent for each memory block BLK.

[0047] In addition, one or more conductive layers 110 located below the above function as the gate electrode of the drain side select transistor STD and the drain side select gate line SGD. For example, as shown in FIG. 8, the width Y SGD is the width Y in the Y direction of the conductive layer 110 functioning as the word line WL. WL In addition, an insulating layer SHE such as silicon oxide (SiO2) is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0048] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions, for example, as shown in FIG. 8. Each of the semiconductor layers 120 functions as a channel region of a plurality of memory cells MC and select transistors (STD, STS) included in one memory string MS (FIG. 1). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si) or the like. The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. The outer peripheral surface of the semiconductor layer 120 is surrounded by a plurality of conductive layers 110, and faces these plurality of conductive layers 110.

[0049] Moreover, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see FIG. 6). This impurity region contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0050] In addition, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL through a via contact electrode ch and a via contact electrode Vy. This impurity region contains an N-type impurity such as phosphorus (P).

[0051] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120, as shown in FIG. 8, for example. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 9, for example. The tunnel insulating film 131 and the block insulating film 133 contain, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or the like. The charge storage film 132 contains a film capable of storing charges, such as silicon nitride (SiN), for example. The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0052] Note that FIG. 9 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities, for example.

[0053] [Structure in the hook-up region R of the memory cell array layer L of chip C M of chip C MCA of the memory cell array layer L HU in the hook-up region R] As shown in FIG. 7, a plurality of via contact electrodes CC are provided in the hook-up region R. Each of these plurality of via contact electrodes CC extends in the Z direction and is connected to the conductive layer 110 at the upper end. HU

[0054] [Structure in the peripheral region R of the memory cell array layer L of chip C M of chip C MCA of the memory cell array layer L P in the peripheral region R] In the peripheral region R P a plurality of via contact electrodes CC are provided corresponding to the external pad electrode P, as shown in FIG. 6, for example. Each of these plurality of via contact electrodes CC is connected to the external pad electrode P at the upper end. X X

[0055] ​​​ [Structure of via contact electrode layer CH] A plurality of via contact electrodes ch included in the via contact electrode layer CH are electrically connected to at least one of, for example, the configuration in the memory cell array layer L MCA and the configuration in the chip C P

[0056] The via contact electrode layer CH includes a plurality of via contact electrodes ch as a plurality of wirings. These plurality of via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrode ch is provided corresponding to a plurality of semiconductor layers 120 and is connected to the lower ends of the plurality of semiconductor layers 120.

[0057] [Chip C M structure of wiring layers M0, M1] A plurality of wirings included in the wiring layers M0 and M1 are electrically connected to at least one of, for example, the configuration in the memory cell array layer L MCA and the configuration in the chip C P

[0058] The wiring layer M0 includes a plurality of wirings m0. These plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Note that a part of the plurality of wirings m0 functions as bit lines BL. The bit lines BL are arranged in the X direction and extend in the Y direction as shown in FIG. 8, for example.

[0059] The wiring layer M1 includes a plurality of wirings m1 as shown in FIG. 6, for example. These plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Note that the wiring pattern in the wiring layer M1 will be described later.

[0060] [Structure of chip bonding electrode layer MB] A plurality of wirings included in the chip bonding electrode layer MB are, for example, the configuration in the memory cell array layer L MCA and the configuration in the chip C​​P is electrically connected to at least one of the components therein.

[0061] The chip bonding electrode layer MB includes a plurality of bonding electrodes P I1 . These plurality of bonding electrodes P I1 may include, for example, a barrier conductive film p such as titanium nitride (TiN), I1B and a metal film p such as copper (Cu), I1M and may include a laminated film thereof.

[0062] [Structure of chip C P Chip C P has, for example, as shown in FIG. 10, four peripheral circuit regions R arranged in the X direction corresponding to the memory plane MP. PC These four peripheral circuit regions R PC each have a solder control circuit region R provided at both ends in the X direction. RC Also, between these two solder control circuit regions R RC two block decoder regions R arranged in the X direction are provided. BD Also, between these two block decoder regions R BD four column control circuit regions R arranged in the X and Y directions are provided. CC Also, although not shown, circuits are also arranged in other regions in the peripheral circuit region R. PC Also, in the region of chip C P opposite to the peripheral region R P a circuit region R is provided. C

[0063] The solder control circuit region R RC is provided with a plurality of block decode units blkd described with reference to FIG. 2. The block decoder region R BD is provided with a block decoder BLKD described with reference to FIG. 2. The column control circuit region R CC is provided with a column control circuit ColC described with reference to FIG. 3. The circuit region R CAn input / output circuit (not shown) is provided. This input / output circuit is connected to an external pad electrode P via via contact electrodes CC etc. described with reference to FIG. 6. X is connected.

[0064] Also, in FIG. 10, a region overlapping with the hookup region R HU (FIG. 5) when viewed from the Z direction is indicated by a dotted line. In the example of FIG. 10, the memory hole region R MH is divided into four regions R MHU in the X direction. The widths of these four regions R MHU in the X direction may all be the same or may not be the same. For example, the widths of the first and fourth regions R MHU counting from the negative side in the X direction may be larger than the widths of the other regions R MHU in the X direction.

[0065] In the example of FIG. 10, a part of the row control circuit region R RC is provided in a region overlapping with the hookup region R HU (FIG. 5) when viewed from the Z direction. Also, a part of the row control circuit region R RC is provided in a region overlapping with the memory hole region R MH (FIG. 5) when viewed from the Z direction. Also, in the example of FIG. 10, the width of the row control circuit region R RC in the X direction is larger than the width of the hookup region R HU (FIG. 5) in the X direction.

[0066] Also, in the example of FIG. 10, the central position of the column control circuit region R CC in the X direction coincides with the boundary between the first and second regions R MHU counting from the negative side in the X direction, or the boundary between the third and fourth regions R MHU counting from the negative side in the X direction. Note that the central position of the column control circuit region R CC in the X direction does not have to coincide with the boundary between the first and second regions R MHU counting from the negative side in the X direction, or the boundary between the third and fourth regions R MHU counting from the negative side in the X direction.

[0067] Column control circuit area R CC As shown in FIG. 11, consists of two regions R arranged in the Y direction CC1 and two regions R arranged in the Y direction provided between them CC2 and a region R provided between them CC3 and includes them.

[0068] Region R CC1 consists of four regions R arranged in the Y direction CC11 These four regions R CC11 each consist of two regions R arranged in the Y direction CC111 and four regions R arranged in the Y direction provided between them CC112 and includes them. Region R CC111 is provided with a plurality of sense amplifier circuits SADL described with reference to FIG. 3. Region R CC112 is provided with a plurality of switch transistors BLS, BLBIAS described with reference to FIG. 3. In the following description, one region R CC111 and two regions R corresponding thereto CC112 and the region including them may be referred to as region R CC110 and may be called.

[0069] Region R CC110 As shown in FIG. 12, consists of a plurality of (four in the illustrated example) regions R arranged in the X direction CC113 These plurality of regions R CC113 each include a part of region R CC111 and a part of region R CC112 and includes them. In region R CC113 in the part corresponding to region R CC111 two sense amplifier circuits SADL (FIG. 3) arranged in the X direction are provided. In region R CC113 in the part corresponding to region R CC112 a set of switch transistors BLS (FIG. 3), BLBIAS (FIG. 3) are provided.

[0070] In addition, FIG. 13 illustrates a plurality of transistors Tr provided in region R CC110 and includes them.

[0071] For example, in region R CC111 a plurality of transistors Tr that constitute the sense amplifier circuit SADL are provided. That is, FIG. 13 illustrates a plurality of semiconductor substrate regions 200S arranged in the X direction and extending in the Y direction, and a plurality of electrodes gc arranged in the Y direction and extending in the X direction. At the intersection of these plurality of semiconductor substrate regions 200S and the plurality of electrodes gc, transistors Tr that constitute the sense amplifier circuit SADL are provided respectively. The plurality of transistors Tr that constitute one sense amplifier circuit SADL are arranged in the Y direction.

[0072] Also, in two regions R arranged in the Y direction CC112 a plurality of transistors Tr that constitute the switch transistors BLS and BLBIAS are provided. That is, FIG. 13 illustrates a plurality of semiconductor substrate regions 200S arranged in the X direction and extending in the Y direction, and a plurality of electrodes gc arranged in the Y direction and extending in the X direction. At the intersection of these plurality of semiconductor substrate regions 200S and the plurality of electrodes gc, transistors Tr that constitute the switch transistors BLS and BLBIAS are provided respectively. In the illustrated example, two switch transistors BLS are arranged in the Y direction, and between these two switch transistors BLS, two switch transistors BLBIAS arranged in the Y direction are provided.

[0073] A via contact electrode electrically connected to the sense amplifier circuit SADL is provided in the source region of the switch transistor BLS. The source regions of the two switch transistors BLBIAS arranged in the Y direction are provided in a common region in the semiconductor substrate region 200S. In this region, a via contact electrode electrically connected to a voltage supply line to which an erase voltage V ERA is supplied during the erase operation is provided. The drain regions of the two switch transistors BLS and BLBIAS arranged in the Y direction are provided in a common region in the semiconductor substrate region 200S. In this region, a via contact electrode electrically connected to the bit line BL is provided.

[0074] Region RCC2 As shown in FIG. 11, it includes eight regions R arranged in the Y direction. CC21 These eight regions R CC21 are each provided with a plurality of latch circuits XDL (FIG. 3) arranged in the X direction. The number of latch circuits XDL arranged in the X direction in one region R CC21 is the same as the number of sense amplifier circuits SADL arranged in the X direction in one region R. For example, as illustrated in FIG. 12, when eight sense amplifier circuits SADL arranged in the X direction are provided in one region R CC111 eight latch circuits XDL arranged in the X direction are provided in one region R. CC111 In addition, in the present embodiment, as shown in FIG. 12, a plurality of wiring lines DBUS are provided corresponding to the plurality of sense amplifier circuits SADL arranged in the X direction. These plurality of wiring lines DBUS each extend in the Y direction as shown in FIG. 11 and are commonly connected to eight sense amplifier circuits SADL arranged in the Y direction and eight latch circuits XDL arranged in the Y direction. Note that only a part of the plurality of DBUS is illustrated in FIG. 11. CC21

[0075]

[0076] In region R CC3 as shown in FIG. 11, a circuit YCOM for controlling the sense amplifier circuit SADL, latch circuit XDL, etc. described with reference to FIG. 3 is provided.

[0077] In addition, chip C P for example, as shown in FIG. 6, includes a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 provided above the electrode layer GC, and a chip bonding electrode layer DB provided above the wiring layers D0, D1, D2, D3, D4.

[0078] [Structure of the semiconductor substrate 200 of chip C P The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, there are provided, for example, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S where the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region 200I. A part of the P-type well region 200P is provided in the semiconductor substrate region 200S, and a part of the P-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as a channel region of a plurality of transistors Tr constituting the peripheral circuit PC and a part such as one electrode of a plurality of capacitors.

[0079] [Structure of the electrode layer GC of chip C P On the upper surface of the semiconductor substrate 200, an electrode layer GC is provided via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Also, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are each connected to a via contact electrode CS.

[0080] The N-type well region 200N of the semiconductor substrate 200, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as a channel region of a plurality of transistors Tr constituting the peripheral circuit PC and one electrode of a plurality of capacitors.

[0081] The plurality of electrodes gc included in the electrode layer GC each function as a gate electrode of a plurality of transistors Tr constituting the peripheral circuit PC and the other electrode of a plurality of capacitors.

[0082] ​The via contact electrode CS extends in the Z direction and is connected to the upper surface of the semiconductor substrate 200 or the electrode gc at the lower end. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0083] [Chip C P structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in FIG. 6, a plurality of wirings included in D0, D1, D2, D3, D4 are electrically connected to at least one of the configuration in the memory cell array layer L MCA and the configuration in the chip C P .

[0084] The wiring layers D0, D1, D2 each include a plurality of wirings d0, d1, d2. These plurality of wirings d0, d1, d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0085] The wiring layers D3, D4 each include a plurality of wirings d3, d4. These plurality of wirings d3, d4 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0086] [Structure of chip bonding electrode layer DB] A plurality of wirings included in the chip bonding electrode layer DB are electrically connected to at least one of the configuration in the memory cell array layer L MCA and the configuration in the chip C P .

[0087] The chip bonding electrode layer DB includes a plurality of bonding electrodes P I2 These plurality of bonding electrodes P I2is, for example, a barrier conductive film p such as a laminated film of titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), etc. I2B and a metal film p such as copper (Cu), etc. I2M may include a laminated film or the like.

[0088] In addition, for the bonding electrode P I1 and the bonding electrode P I2 copper (Cu) or the like is used for the metal film p I1M ,p I2M When used, the metal film p I1M and the metal film p I2M are integrated, making it difficult to confirm their mutual boundaries. However, due to misalignment during bonding, the bonding electrode P I1 and the bonding electrode P I2 The distortion of the shape bonded together, the barrier conductive film p I1B ,p I2B The bonding structure can be confirmed due to misalignment (occurrence of discontinuous portions on the side surface). Also, when the bonding electrode P I1 and the bonding electrode P I2 are formed by the damascene method, each side surface has a tapered shape. Therefore, the shape of the cross-section along the Z direction at the portion where the bonding electrode P I1 and the bonding electrode P I2 are bonded together is not a straight side wall but a non-rectangular shape. Also, when the bonding electrode P I1 and the bonding electrode P I2 are bonded together, the bottom surface, side surface, and top surface of each Cu forming them are covered with a barrier metal. In contrast, in a general wiring layer using Cu, an insulating layer (such as SiN or SiCN, etc.) having an anti-oxidation function of Cu is provided on the top surface of Cu, and no barrier metal is provided. Therefore, even if there is no misalignment during bonding, it is possible to distinguish from a general wiring layer.

[0089] [Wiring pattern in wiring layer M1] As described with reference to FIG. 2 and the like, each word line WL is connected to a transistor T BLK Here, since a relatively large voltage may be supplied to the word line WL, the transistor T BLKAs for this, a high breakdown voltage transistor is used. Here, the high breakdown voltage transistor may become relatively large. From this relationship, the area of the row control circuit region R described with reference to FIG. 10 RC may become relatively large.

[0090] Here, when the area of the row control circuit region R RC is larger than the area of the hook-up region R HU it is conceivable to provide a part of the row control circuit region R RC in a region overlapping the hook-up region R when viewed from the Z direction, and to provide the remaining part in a region not overlapping the memory plane MP when viewed from the Z direction. However, in this case, the total area of the peripheral circuit region R HU may become larger than the area of the memory plane MP, and the circuit area of the memory die MD may increase. PC Therefore, in the present embodiment, as described with reference to FIG. 10, a part of the row control circuit region R

[0091] is provided in a region overlapping the hook-up region R when viewed from the Z direction, and the remaining part is provided in a region overlapping the memory hole region R RC when viewed from the Z direction. HU when viewed from the Z direction. MH When such a structure is adopted, some bit lines BL are provided at positions overlapping the row control circuit region R

[0092] instead of the column control circuit region R CC when viewed from the Z direction. RC or the block decoder region R BD Therefore, in the present embodiment, a wiring m1a extending in the X direction as shown in FIG. 15 is provided in the wiring layer M1, and the bit line BL and the configuration in the column control circuit region R

[0093] are electrically connected via this wiring m1a. According to such a configuration, the row control circuit region R CC in the RCIt becomes possible to provide a semiconductor memory device capable of high integration by suppressing an increase in the circuit area of the memory die MD accompanying an increase in the area of

[0094] Hereinafter, the wiring pattern in the wiring layer M1 will be described.

[0095] FIG. 14 is a schematic plan view for explaining the wiring pattern in the wiring layer M1. FIG. 14 shows the configuration in the wiring layer M1 and the chip C P in the chip C are shown superimposed. FIG. 15 is a schematic bottom view for explaining the wiring pattern in the wiring layer M1. FIG. 15 shows the configuration in the wiring layer M1 and the configuration in the wiring layer M0 superimposed. FIGS. 16 and 17 are schematic plan views for explaining the wiring pattern in the wiring layer M1. FIG. 16 shows the configuration in the wiring layer M1 and the chip C P in the chip C are shown superimposed. FIG. 17 shows the configuration of the region corresponding to FIG. 16. However, in FIG. 17, the wiring m1a is omitted. FIG. 18 is a schematic bottom view for explaining the wiring m1a. FIG. 19 is a schematic bottom view for explaining the wiring m1b. FIG. 20 is a schematic bottom view for explaining the wiring pattern in the wiring layer M1.

[0096] In the memory hole region R of the wiring layer M1 MH as shown in FIG. 15, a plurality of wiring groups Gm1 are provided. As shown in FIG. 14 for example, the wiring group Gm1 is provided corresponding to a plurality of regions R CC110 arranged in the Y direction, and are arranged in the Y direction with the same pitch as these plurality of regions R CC110 . Further, each of the wiring groups Gm1 is provided within one of the plurality of regions R MHU described with reference to FIG. 10.

[0097] As shown in FIG. 15 for example, each of the wiring groups Gm1 includes a plurality of (eight in the example of FIG. 15) wirings m1a. The wiring m1a is a part of the plurality of wirings m1 described with reference to FIGS. 6, 7, etc.

[0098] As shown in FIG. 18, the wiring m1a includes a portion 151 provided at a position overlapping the bit line BL when viewed from the Z direction, a portion 152 provided at a position overlapping the bonding electrode P I1 when viewed from the Z direction, and a portion 153 connected to these portions 151 and 152.

[0099] The portion 151 extends in the Y direction. As shown in FIG. 6, the upper surface of the portion 151 is connected to two via contact electrodes V1 arranged in the Y direction. These two via contact electrodes V1 are connected to the lower surface of the bit line BL. Also, as shown in FIG. 18, the length of these two via contact electrodes V1 in the Y direction is larger than the length of these two via contact electrodes V1 in the X direction. Also, the length of the portion 151 in the Y direction is larger than the total Y length of these two via contact electrodes V1. Also, the length of the portion 151 in the X direction is larger than the length of these two via contact electrodes V1 in the X direction. The portion 151 covers the entire lower surface of these two via contact electrodes V1.

[0100] In the illustrated example, two via contact electrodes V1 are provided corresponding to one portion 151, but such a configuration is merely an example. For example, one via contact electrode V1 may be provided corresponding to one portion 151, or three or more via contact electrodes V1 may be provided corresponding to one portion 151.

[0101] Here, the bit lines BL are arranged in the X direction over the entire memory hole region R MH The portion 151 is also provided over the entire memory hole region R corresponding to these plurality of bit lines BL MH as a whole.

[0102] Of the wiring groups Gm1 illustrated in FIG. 15, one (wiring group Gm1a) contains a portion 151 provided at a position overlapping with the 16n + 12th (n is an integer of 0 or more) bit line BL counted from the negative side in the X direction. Also, a portion 151 contained in one (wiring group Gm1b) of the wiring groups Gm1 illustrated in FIG. 15 is provided at a position overlapping with the 16n + 13th bit line BL counted from the negative side in the X direction. Similarly hereinafter, a portion 151 contained in one of the 16 wiring groups Gm1 arranged in the Y direction is provided at a position overlapping with the 16n + mth (m is an integer from 1 to 16) bit line BL counted from the negative side in the X direction.

[0103] As shown in FIG. 18, the portion 152 is formed in a substantially rectangular shape. As shown in FIG. 6, the lower surface of the portion 152 is connected to the bonding electrode P I1 . As shown in FIG. 18, the length of the portion 152 in the Y direction is larger than the length of the bonding electrode P I1 in the Y direction. Also, the length of the portion 152 in the X direction is larger than the length of the bonding electrode P I1 in the X direction. The portion 152 covers the entire upper surface of the bonding electrode P I1 .

[0104] The bonding electrode P I1 is arranged in the X direction and the Y direction over the entire column control circuit region R CC described with reference to FIG. 10. The portion 152 is also provided over the entire column control circuit region R I1 corresponding to these plurality of bonding electrodes P CC .

[0105] FIGS. 16 and 17 illustrate a plurality of regions R CC113 . As shown in FIGS. 16 and 17, the portion 152 contained in the wiring group Gm1a is provided at a position overlapping with the first region R CC113 counted from the positive side in the Y direction among the four regions R CC113 arranged in the Y direction, when viewed from the Z direction. Also, the portion 152 contained in the wiring group Gm1b is provided at a position overlapping with the four regions R CC113Among them, the second region R counted from the positive side in the Y direction CC113 is provided at a position overlapping when viewed from the Z direction. Similarly, hereinafter, a portion 152 included in one of a plurality of wiring groups Gm1 arranged in the Y direction is provided at a position overlapping with one of a plurality of regions R CC113 arranged in the Y direction when viewed from the Z direction.

[0106] Also, in the example of FIG. 16, the positions in the X direction of the plurality of portions 152 included in each wiring group Gm1 are all different. Also, the plurality of regions R CC113 are each provided at a position overlapping with two portions 152 when viewed from the Z direction. These two portions 152 are electrically connected to two sense amplifier circuits SADL (see FIG. 12) included in the corresponding region R CC113 respectively.

[0107] As shown in FIG. 18, the portion 153 extends in the X direction. One end portion of the portion 153 in the X direction is connected to one end portion of the portion 151 in the Y direction (in the illustrated example, the end portion on the negative side in the Y direction). The other end portion of the portion 153 in the X direction is connected to one end portion of the portion 152 in the Y direction (in the illustrated example, the end portion on the positive side in the Y direction). Note that the central position of the portion 153 in the Y direction is between the central position of the portion 151 in the Y direction and the central position of the portion 152 in the Y direction.

[0108] As shown in FIG. 20, when focusing on eight wirings m1a included in one wiring group Gm1, the portions 153 are arranged in the Y direction at a predetermined pitch. Also, the pitch P 151 in the X direction of the portion 151 is larger than the pitch P 152 in the X direction of the portion 152. Therefore, when focusing on the eight wirings m1a included in one wiring group Gm1, the lengths X 153 in the X direction of the portions 153 of these eight wirings m1a are all different. In the example of FIG. 16, among these eight wirings m1a, the length X 153 in the X direction of the portion 153 is smaller for those provided on the positive side in the Y direction, and the length X 153is large.

[0109] As described with reference to FIG. 10, the plurality of wiring groups Gm1 are provided within one range of the plurality of regions R arranged in the X direction. For example, the wiring m1a having the maximum length in the X direction is connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. MHU of which one range is provided. For example, the wiring m1a having the maximum length in the X direction is connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. MHU and the bonding electrode P provided near the end in the X direction of the column control circuit region R. CC connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. I1 connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. 153 of which one range is provided. For example, the wiring m1a having the maximum length in the X direction is connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. MHU connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. CC connected to the bit line BL provided near the end in the X direction of the region R, and the bonding electrode P provided near the end in the X direction of the column control circuit region R. Therefore, the maximum value of the length X in the X direction of the portion 153 may substantially coincide with, for example, the distance X in the X direction from the end in the X direction of the region R to the end in the X direction of the column control circuit region R (FIG. 10). The maximum value of the length X is at least smaller than the length in the X direction of the region R. EE (FIG. 10) and may substantially coincide. The maximum value of the length X 153 is at least smaller than the length in the X direction of the region R. MHU is at least smaller than the length in the X direction of the region R.

[0110] Note that some of the eight wirings included in some of the wiring groups Gm1 may be wiring m1b as illustrated in FIG. 19 instead of wiring m1a. The wiring m1b is basically configured in the same manner as the wiring m1a. However, the wiring m1b does not include the portion 153. In the wiring m1b, one end in the Y direction of the portion 151 is connected to the portion 152.

[0111] For example, in a region near the center in the X direction of the column control circuit region R, the bit line BL and the bonding electrode P electrically connected to the bit line BL may overlap when viewed from the Z direction. The wiring m1b, rather than the wiring m1a, is connected to such a bit line BL. CC For example, in a region near the center in the X direction of the column control circuit region R, the bit line BL and the bonding electrode P electrically connected to the bit line BL may overlap when viewed from the Z direction. The wiring m1b, rather than the wiring m1a, is connected to such a bit line BL. I1 connected to the bit line BL may overlap when viewed from the Z direction. The wiring m1b, rather than the wiring m1a, is connected to such a bit line BL.

[0112] Next, with reference to FIG. 20, the pitch P in the Y direction of the bonding electrode P I1 will be described. PI1 will be described.

[0113] The pitch P in the Y direction of the bonding electrode P I1 in the Y direction of the bonding electrode PPI1 is the width Y in the Y direction of the wiring group Gm1 Gm1 and the minimum distance Y allowed as the distance between two wiring groups Gm1 arranged in the Y direction S It is conceivable that the sum is equal to or greater than the above value.

[0114] Also, the width Y in the Y direction of the wiring group Gm1 Gm1 can be shown as follows. In the illustrated example, the wiring group Gm1 includes eight wirings m1a arranged in the Y direction. The width Y Gm1 is the width Y in the Y direction of the portion 151 of the one provided on the most positive side in the Y direction among these eight wirings m1a 151 including. Also, the width Y Gm1 is the width Y in the Y direction of the portion 152 of the one provided on the most negative side in the Y direction among these eight wirings m1a 152 including. Also, the width Y Gm1 includes the widths in the Y direction of the other six portions 153. Also, the width Y Gm1 includes the distances between these eight wirings m1a. Therefore, for example, if the total width of the widths in the Y direction of the six portions 153 and the distances between the eight wirings m1a is Y LS then the width Y in the Y direction of the wiring group Gm1 Gm1 is the width Y 151 and the width Y 152 and the width Y LS It can be shown as the sum value of.

[0115] From the above, the pitch P in the Y direction of the bonding electrode P I1 can be equal to or greater than the sum of the width Y PI1 and the width Y 151 and the width Y 152 and the minimum distance Y LS and. S It is possible that the sum is equal to or greater than the above value.

[0116] [Second Embodiment] Figs. 21 to 25 are schematic plan views showing a part of the configuration of a semiconductor memory device according to the second embodiment. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0117] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0118] However, as described with reference to FIG. 14, in the semiconductor memory device according to the first embodiment, a plurality of wiring groups Gm1 are arranged in the Y direction at the same pitch as the region R CC110 and one wiring group Gm1 is provided corresponding to one region R CC110 .

[0119] On the other hand, as shown in FIG. 21, in the semiconductor memory device according to the second embodiment, a plurality of wiring groups Gm2 are arranged in the Y direction at a pitch smaller than that of the region R CC110 and a plurality of (four in the illustrated example) wiring groups Gm2 are provided corresponding to one region R CC110 .

[0120] The wiring group Gm2 includes a plurality of wirings m1a, similar to the wiring group Gm1. Note that a part of the plurality of wirings included in some of the wiring groups Gm2 may be the wiring m1b as exemplified in FIG. 19 instead of the wiring m1a. In FIG. 21, the region where four wiring groups Gm2 are provided is shown as the region R Gm2 .

[0121] Also, in the example of FIG. 22, a plurality of (four in the illustrated example) portions 152 included in a plurality of (four in the illustrated example) wiring groups Gm2 are respectively provided at positions overlapping with the (2n + 1)-th (n is an integer of 0 or more) region R CC113 when counted from the negative X direction. Further, no portion 152 is provided at a position overlapping with the (2n + 2)-th region R CC113 when viewed from the Z direction. The four portions 152 overlapping with the (2n + 1)-th region R CC113 are electrically connected to the four sense amplifier circuits SADL (see FIG. 12) included in the (2n + 1)-th region R CC113 and the (2n + 2)-th region R CC113 , respectively.

[0122] The portions 152 of the plurality of wirings m1a illustrated in FIG. 22 are each connected to transistors Tr etc. in the corresponding region R via the wirings d0 to d3 described with reference to FIGS. 6 and 7. CC113 in the column control circuit region R

[0123] FIG. 23 illustrates the configuration in the wiring layer D4. The wiring layer D4 illustrated in FIG. 23 includes wirings d4a and d4b. The wirings d4a and d4b are part of the plurality of wirings d4 described with reference to FIGS. 6, 7, etc.

[0124] The wiring d4a is formed in a substantially rectangular shape. The upper surface of the wiring d4a is connected to the bonding electrode P I2 The length of the wiring d4a in the Y direction is larger than the length of the bonding electrode P I2 in the Y direction. Also, the length of the wiring d4a in the X direction is larger than the length of the bonding electrode P I2 in the X direction. The wiring d4a covers the entire lower surface of the bonding electrode P I2

[0125] The wiring d4b is provided between two wirings d4a having different positions in the X direction and extends in the Y direction. In the example of FIG. 23, three wirings d4b are provided between two wirings d4a arranged in the X direction.

[0126] According to such a configuration, for example, as shown in FIG. 24, the wiring d4 can electrically connect the configuration in the column control circuit region R CC and the configuration arranged outside thereof. Also, the wiring d4 can electrically connect the configuration provided on the positive side in the Y direction from the column control circuit region R CC and the configuration provided on the negative side in the Y direction from the column control circuit region R CC via the column control circuit region R CC

[0127] Note that in FIG. 22, the plurality of portions 152 included in the plurality of wiring groups Gm2 are each in the (2n + 1)-th region R counted from the negative side in the X direction CC113 ​​An example where they are provided at overlapping positions when viewed from the Z direction was shown. However, such a configuration is merely an example. For example, a plurality of portions 152 included in the plurality of wiring groups Gm2 are each in the (4n + 1)-th region R counted from the negative X direction CC113 may be provided at overlapping positions when viewed from the Z direction. In such a case, as shown in FIG. 25 for example, more wirings d4b can be provided between two wirings d4a arranged in the X direction.

[0128] [Third Embodiment] FIG. 26 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the third embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

[0129] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0130] However, the semiconductor memory device according to the third embodiment includes a column control circuit region R CC instead of a column control circuit region R CC ′. As shown in FIG. 26, the column control circuit region R CC ′ includes two regions R CC1 ′ arranged in the Y direction and a region R CC3 provided therebetween.

[0131] The region R CC1 ′ includes eight regions R CC11 ′ arranged in the X direction and the Y direction. These eight regions R CC11 ′ each include two regions R CC21 arranged in the Y direction, two regions R CC111 arranged in the Y direction and provided therebetween, and four regions R CC112 arranged in the Y direction and provided therebetween.

[0132] Here, in addition to the configuration in the region R CC11 ′ described with reference to FIG. 11, the region R CC11 also includes a region R CC21is included. Therefore, in region R CC11 ´, the width in the Y direction is larger than the width in the Y direction of region R CC11 . According to such a configuration, compared with the first embodiment, it is possible to increase the number of wirings m1a and m1b included in the wiring group Gm1.

[0133] [Fourth Embodiment] FIG. 27 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the fourth embodiment. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted.

[0134] The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0135] However, as described with reference to FIG. 10, in the first embodiment, in the peripheral circuit region R PC , four column control circuit regions R CC arranged in the X direction and the Y direction are provided. Further, in the peripheral circuit region R PC , a region R MH obtained by dividing the memory hole region R MHU into four in the X direction is provided, and the central position in the X direction of the column control circuit region R CC coincides with the boundary between the first and second regions R MHU counted from the negative side in the X direction, or the boundary between the third and fourth regions R MHU counted from the negative side in the X direction.

[0136] However, such a configuration is merely an example. For example, in one peripheral circuit region R PC , if the number of column control circuit regions R CC arranged in the Y direction is a (a is an integer of 1 or more), and in one peripheral circuit region R PC , if the number of column control circuit regions R CC arranged in the X direction is b (b is an integer of 1 or more), a and b can be adjusted as appropriate. Further, for example, in the peripheral circuit region R PC , a memory hole region R MHis divided into 2b in the X direction. MHU It is also possible to provide these 2b regions R MHU The widths in the X direction of the column control circuit region R may or may not be the same. CC The center position in the X direction of the area R is the 2n+1th and 2n+2nd (n is an integer between 0 and b-1) areas R, counting from the negative side of the X direction. MHU It may or may not coincide with the boundary of

[0137] For example, in the example of FIG. 27, a is 2 and b is 3. Therefore, in the peripheral circuit region R PC In the X-direction and Y-direction, six column control circuit regions R CC In addition, the peripheral circuit region R PC , memory hole region R MH is divided into 6 regions in the X direction. MHU In addition, the column control circuit region R CC The center position in the X direction of the first and second regions R MHU The boundary of the third and fourth area R counting from the negative X-axis MHU or the 5th and 6th regions R counting from the negative X-axis MHU The column control circuit region R CC The center position in the X direction of the first and second regions R MHU The boundary of the third and fourth area R counting from the negative X-axis MHU or the 5th and 6th regions R counting from the negative X-axis MHU It does not have to coincide with the boundary of

[0138] [Fifth embodiment] 28 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to the fifth embodiment. In the following description, the same reference numerals are used to designate the same parts as in the first embodiment, and description thereof will be omitted.

[0139] As described with reference to FIG. 27, one peripheral circuit region R PCIn this case, the number a of column control circuit regions R arranged in the Y direction CC and the number b of column control circuit regions R arranged in the X direction CC can be adjusted as appropriate. For example, in the example of FIG. 28, a is 2 and b is 1. Incidentally, in other respects, the semiconductor memory device according to the fifth embodiment is configured in the same manner as the semiconductor memory device according to the first embodiment.

[0140] [Sixth Embodiment] FIG. 29 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the sixth embodiment. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0141] As described with reference to FIGS. 27 and 28, in one peripheral circuit region R PC the number a of column control circuit regions R arranged in the Y direction CC and the number b of column control circuit regions R arranged in the X direction CC can be adjusted as appropriate. For example, in the example of FIG. 29, a is 1 and b is 1.

[0142] Incidentally, in the first embodiment, as described with reference to FIG. 5, on the chip C M four memory planes MP arranged in the X direction are provided. Also, as described with reference to FIG. 10, on the chip C P four peripheral circuit regions R arranged in the X direction corresponding to these four memory planes MP PC are provided.

[0143] On the other hand, in the sixth embodiment, on the chip C M a total of 16 memory planes MP arranged in 4 in the X direction and 4 in the Y direction are provided. Also, as shown in FIG. 29, on the chip C P corresponding to these 16 memory planes MP, a total of 16 peripheral circuit regions R arranged in 4 in the Y direction and 4 in the Y direction PC are provided.

[0144] In other respects, the semiconductor memory device according to the sixth embodiment is configured in the same manner as the semiconductor memory device according to the first embodiment.

[0145] [Seventh Embodiment] FIG. 30 is a schematic bottom view showing a part of the configuration of the semiconductor memory device according to the seventh embodiment. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0146] The semiconductor memory device according to the seventh embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0147] However, as shown in FIG. 30, in the seventh embodiment, a wiring group Gm3 is provided between a plurality of wiring groups Gm1 arranged in the Y direction. The wiring group Gm3 includes a plurality of wirings m1c arranged in the Y direction. The wiring m1c extends in the X direction. The wiring m1c is a part of the plurality of wirings m1 described with reference to FIGS. 6, 7, etc. The wiring m1c may be, for example, the wiring CG described with reference to FIG. 2, or may be a wiring electrically connected to the select gate lines (SGD, SGS). Further, the wiring m1c may be, for example, the signal supply line BLKSEL described with reference to FIG. 2, or may be a signal supply line that supplies an inverted signal of the signal supply line BLKSEL. Further, the wiring m1c may be other wirings.

[0148] Next, the pitch P I1 in the Y direction of the bonding electrode P PI1 will be described.

[0149] In the example of FIG. 30, the pitch P I1 in the Y direction of the bonding electrode P PI1 is considered to be equal to or greater than the sum of twice the width Y Gm1 in the Y direction of the wiring group Gm1, the width Y Gm3 in the Y direction of the wiring group Gm3, and the minimum distance Y S2 allowed as the distance between the wiring group Gm1 and the wiring group Gm3.

[0150] Width Y of wiring group Gm1 in the Y direction Gm1 As described above, width Y 151 and width Y 152 and width Y LS can be shown as the total value thereof.

[0151] Therefore, in the example of FIG. 30, pitch P I1 of bonding electrode P in the Y direction PI1 is made to be equal to or greater than the total value of width Y 151 and width Y 152 and width Y LS and width Y Gm3 and twice the minimum distance Y S2

[0152] In addition, width Y Gm3 of wiring group Gm3 in the Y direction can be shown as the total width of the widths of a plurality of wirings m1c in the Y direction included in wiring group Gm3 and the distances between these plurality of wirings m1c.

[0153] [Eighth Embodiment] FIG. 31 is a schematic bottom view showing a partial configuration of a semiconductor memory device according to the eighth embodiment. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted.

[0154] The semiconductor memory device according to the eighth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0155] However, as shown in FIG. 31, in the eighth embodiment, column control circuit region R CC (FIG. 10) and row control circuit region R RC ​A wiring group Gm4 is provided in the region between it and (FIG. 10). The wiring group Gm4 includes a plurality of wirings m1d. In the illustrated example, the wirings m1d are arranged in the Y direction and extend in the X direction. The wiring m1d is a part of the plurality of wirings m1 described with reference to FIGS. 6, 7, etc. The wiring m1d may be, for example, the wiring CG described with reference to FIG. 2, or may be a wiring electrically connected to the selection gate lines (SGD, SGS). Further, the wiring m1d may be, for example, the signal supply line BLKSEL described with reference to FIG. 2, or may be a signal supply line that supplies the inverted signal of the signal supply line BLKSEL. Further, the wiring m1d may be other wirings.

[0156] [Embodiment 9] FIG. 32 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the ninth embodiment. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted. In FIG. 12, the region R CC113 is illustrated as a vertically long region (a shape in which the length in the Y direction is longer than the length in the X direction). On the other hand, in FIG. 32, for the convenience of illustration, the region R CC113 is illustrated as a horizontally long region (a shape in which the length in the X direction is longer than the length in the Y direction). However, the region R CC113 shown in FIG. 12 and the region R CC113 shown in FIG. 32 mean the same configuration.

[0157] The column control circuit region R illustrated in FIG. 11 CC includes two regions R CC1 arranged in the Y direction, two regions R CC2 arranged in the Y direction provided between them, and a region R CC3 provided between them. Further, the column control circuit region R CC ' illustrated in FIG. 26 includes two regions R CC1 ' arranged in the Y direction and a region R CC3 provided between them.

[0158] However, such a configuration is merely an example, and the column control circuit regions R CC , RCC The arrangement of each region in ´ can be adjusted as appropriate.

[0159] For example, the column control circuit region R CC may include, as shown in FIG. 32, two regions R arranged in the Y direction CC1 and two regions R arranged in the Y direction provided on the negative side in the Y direction relative to this CC2 and a region R provided on the negative side in the Y direction relative to this. CC3 Although not shown, the column control circuit region R CC ´ may include two regions R arranged in the Y direction CC1 ´ and a region R provided on the negative side in the Y direction relative to this. CC3

[0160] In addition, FIG. 32 illustrates 64 sense amplifier circuits SADL<0> to SADL<63> as sense amplifier circuits SADL. In the illustrated example, 16 sense amplifier circuits SADL<16n> to SADL<16n + 15> (n is an integer of 0 or more) are arranged in 4 columns from the negative side in the Y direction to the positive side in the Y direction. The sense amplifier circuits SADL<0> to SADL<63> are electrically connected to the first to 64th bit lines BL counted from the negative side in the X direction, respectively.

[0161] FIG. 32 also illustrates 64 latch circuits XDL<0> to XDL<63> as latch circuits XDL. In the illustrated example, 16 latch circuits XDL<16n> to XDL<16n + 15> are arranged in 4 columns from the negative side in the Y direction to the positive side in the Y direction. These 64 latch circuits are provided corresponding to the 64 sense amplifier circuits SADL<0> to SADL<63>, respectively.

[0162] FIG. 32 also illustrates 8 wirings DBUS extending in the Y direction. These 8 wirings DBUS are connected to 8 sense amplifier circuits SADL<8m> to SADL<8m + 7> (m is an integer of 0 or more) arranged in the Y direction and 8 latch circuits XDL<8m> to XDL<8m + 7> arranged in the Y direction, respectively. ​

[0163] [Embodiment 10] FIG. 33 is a schematic plan view showing a partial configuration of the semiconductor memory device according to the tenth embodiment. FIG. 34 is a schematic plan view showing a part of another configuration example of the semiconductor memory device according to the tenth embodiment. In the following description, the same reference numerals are given to the same parts as in the first embodiment, and the description thereof is omitted. Note that, also in FIGS. 33 and 34, the region R CC113 is illustrated as a horizontally long region. However, the region R CC113 shown in FIG. 12 and the region R CC113 shown in FIGS. 33 and 34 have the same configuration.

[0164] In the column control circuit region R CC exemplified in FIG. 11, 16 sense amplifier circuits SADL are arranged in the Y direction. Also, similarly, in the column control circuit region R CC ' exemplified in FIG. 26 and the column control circuit region R CC exemplified in FIG. 32, 16 sense amplifier circuits SADL are arranged in the Y direction.

[0165] However, such a configuration is merely an example, and the number of sense amplifier circuits SADL arranged in the Y direction in the column control circuit regions R CC , R CC ' can be adjusted as appropriate.

[0166] For example, as exemplified in FIG. 33, in the column control circuit region R CC , 12 sense amplifier circuits SADL may be arranged in the Y direction. Also, as exemplified in FIG. 34, similarly, in the column control circuit region R CC exemplified in FIG. 11, 12 sense amplifier circuits SADL may be arranged in the Y direction. Also, although not shown, similarly, in the column control circuit region R CC ' exemplified in FIG. 26, 12 sense amplifier circuits SADL may be arranged in the Y direction.

[0167] Also, in FIG. 33, 48 sense amplifier circuits SADL<0> to SADL<47> are illustrated as the sense amplifier circuit SADL. In the illustrated example, 12 sense amplifier circuits SADL are arranged in the Y direction over 4 columns. In columns other than the third column counted from the negative side in the X direction, the sense amplifier circuits SADL<12n1> to SADL<12n1 + 11> (n1 is 0, 1, or 3) are arranged from the negative side to the positive side in the Y direction. Also, in the third column counted from the negative side in the X direction, the sense amplifier circuits SADL<32> to SADL<35>, SADL<24> to SADL<31> are arranged from the negative side to the positive side in the Y direction.

[0168] Further, in FIG. 33, 48 latch circuits XDL<0> to XDL<47> are illustrated as the latch circuit XDL. In the illustrated example, 12 latch circuits XDL are arranged in the Y direction over 4 columns. In columns other than the third column counted from the negative side in the X direction, the latch circuits XDL<12n1> to XDL<12n1 + 11> are arranged from the negative side to the positive side in the Y direction. Also, in the third column counted from the negative side in the X direction, the latch circuits XDL<32> to XDL<35>, XDL<24> to XDL<31> are arranged from the negative side to the positive side in the Y direction.

[0169] In addition, FIG. 33 illustrates six wiring DBUSs. Four of these six wiring DBUSs extend in the Y direction and are respectively connected to eight sense amplifier circuits SADL<8m1> to SADL<8m1+7> arranged in the Y direction (m1 is 0, 2, 3, or 5) and eight latch circuits XDL<8m1> to XDL<8m1+7> arranged in the Y direction. Further, each of the remaining two of these six wiring DBUSs has two portions extending in the Y direction. One of these two portions is connected to four sense amplifier circuits SADL<8m2> to SADL<8m2+3> arranged in the Y direction (m2 is 1 or 4) and four latch circuits XDL<8m2> to XDL<8m2+3> arranged in the Y direction. The other of these two portions is connected to four sense amplifier circuits SADL<12> to SADL<15> arranged in the Y direction and four latch circuits XDL<12> to XDL<15> arranged in the Y direction, or is connected to four sense amplifier circuits SADL<44> to SADL<47> arranged in the Y direction and four latch circuits XDL<44> to XDL<47> arranged in the Y direction.

[0170] [Embodiment 11] FIG. 35 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to the 11th embodiment. FIG. 36 is a schematic plan view showing a part of another configuration example of the semiconductor memory device according to the 11th embodiment. In the following description, the same reference numerals are given to the same parts as those in the 1st embodiment, and the description thereof is omitted. In FIGS. 35 and 36 as well, the region R CC113 is illustrated as a horizontally long region. However, the region R shown in FIG. 12 CC113 and the region R shown in FIGS. 35 and 36 CC113 mean the same configuration.

[0171] As described with reference to FIGS. 33 and 34, the number of sense amplifier circuits SADL arranged in the Y direction in the column control circuit regions R CC , R CC ´ can be adjusted as appropriate.

[0172] For example, as illustrated in FIG. 35, in the column control circuit region RCC In this case, eight sense amplifier circuits SADL may be arranged in the Y direction. Also, as illustrated in FIG. 36, in the column control circuit region R illustrated in FIG. 11 CC Similarly, in this case, eight sense amplifier circuits SADL may be arranged in the Y direction. Also, although not illustrated, in the column control circuit region R illustrated in FIG. 26 CC Similarly, in this case, eight sense amplifier circuits SADL may be arranged in the Y direction.

[0173] Note that FIG. 35 illustrates 32 sense amplifier circuits SADL<0> to SADL<31> as the sense amplifier circuits SADL. In the illustrated example, eight sense amplifier circuits SADL<8n> to SADL<8n + 7> are arranged in four columns from the negative side in the Y direction to the positive side in the Y direction.

[0174] Also, FIG. 35 illustrates 32 latch circuits XDL<0> to XDL<31> as the latch circuits XDL. In the illustrated example, eight latch circuits XDL<8n> to XDL<8n + 7> are arranged in four columns from the negative side in the Y direction to the positive side in the Y direction.

[0175] Also, FIG. 35 illustrates four wirings DBUS. These four wirings DBUS are each connected to eight sense amplifier circuits SADL<8m> to SADL<8m + 7> arranged in the Y direction and eight latch circuits XDL<8m> to XDL<8m + 7> arranged in the Y direction.

[0176] [Embodiment 12] FIG. 37 is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the 12th embodiment. FIG. 38 is a schematic plan view showing a part of another configuration example of the semiconductor memory device according to the 12th embodiment. In the following description, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted. Note that also in FIGS. 37 and 38, the region R CC113 is illustrated as a horizontally long region. However, the region R shown in FIG. 12 CC113 and the regions R shown in FIGS. 37 and 38 CC113means the same configuration.

[0177] The column control circuit region R illustrated in FIGS. 11 and 32 to 36 CC , and the column control circuit region R illustrated in FIG. 26 CC ´, the number of sense amplifier circuits SADL arranged in the X direction is equal to the number of latch circuits XDL arranged in the X direction.

[0178] However, such a configuration is merely an example, and in the column control circuit regions R CC ,R CC ´, the number of sense amplifier circuits SADL arranged in the X direction and the number of latch circuits XDL arranged in the X direction may be different.

[0179] For example, FIGS. 37 and 38 illustrate a total of 48 sense amplifier circuits SADL<0> to SADL<47> arranged in 12 rows in the Y direction and 4 columns in the X direction. Also, FIGS. 37 and 38 illustrate a total of 48 latch circuits XDL<0> to XDL<47> arranged in 16 rows in the Y direction and 3 columns in the X direction.

[0180] Note that FIG. 37 illustrates six wiring lines DBUS. Each of these six wiring lines DBUS is connected to eight sense amplifier circuits SADL<8m> to SADL<8m + 7> and eight latch circuits XDL<8m> to XDL<8m + 7>.

[0181] [Embodiment 13] FIGS. 39 and 40 are schematic bottom views showing a part of the configuration of the semiconductor memory device according to the 13th embodiment. FIG. 40 illustrates the configuration of the region corresponding to FIG. 39. However, in FIG. 40, the bit lines BL are omitted. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0182] In the example of FIG. 15, the positions of the portions 151 of the plurality of wirings m1a included in each wiring group Gm1 in the X direction are equally spaced in the X direction. However, such a configuration is merely an example, and the positions of the portions 151 of the plurality of wirings m1a included in each wiring group Gm1 in the X direction do not have to be equally spaced.

[0183] For example, when adopting the column control circuit region R CC described with reference to FIG. 33, the sense amplifier circuit SADL<4> is arranged in the X direction in parallel with the sense amplifier circuits SADL<16>, SADL<24>, and SADL<40>. Further, in the column control circuit region R CC when the number of sense amplifier circuits SADL arranged in the X direction is 49 or more, the sense amplifier circuit SADL<4> is arranged in the X direction in parallel with the sense amplifier circuits SADL<48n + 4>, SADL<48n + 16>, SADL<48n + 24n>, and SADL<48n + 40>.

[0184] FIG. 39 shows an example of a wiring group Gm1 corresponding to the sense amplifier circuits SADL<48n + 4>, SADL<48n + 16>, SADL<48n + 24n>, and SADL<48n + 40>. The wiring group Gm1 illustrated in FIG. 39 includes 12 wirings m1a.

[0185] In FIG. 39, bit lines BL are arranged at equal intervals in the X direction. Also, two bit lines BL corresponding to sense amplifier circuits SADL<48n + 4> and SADL<48n + 16> and two portions 151 connected thereto are separated by 12 pitches between the bit lines BL. Also, two bit lines BL corresponding to sense amplifier circuits SADL<48n + 16> and SADL<48n + 24> and two portions 151 connected thereto are separated by 8 pitches between the bit lines BL. Also, two bit lines BL corresponding to sense amplifier circuits SADL<48n + 24> and SADL<48n + 40> and two portions 151 connected thereto are separated by 16 pitches between the bit lines BL. Also, two bit lines BL corresponding to sense amplifier circuits SADL<48n + 40> and SADL<48n + 52> and two portions 151 connected thereto are separated by 12 pitches between the bit lines BL.

[0186] The average value of the pitches in the X direction of the portions 151 of the plurality of wirings m1a included in the wiring group Gm1 illustrated in FIG. 39 is 12 pitches between the bit lines BL. This is larger than the pitch P in the X direction of the portions 152 of the plurality of wirings m1a included in the wiring group Gm1 illustrated in FIG. 39 152 (FIG. 40).

[0187] [Other Embodiments] The semiconductor memory devices according to the first to thirteenth embodiments have been described above. However, the configurations described above are merely examples, and the specific configurations can be adjusted as appropriate.

[0188] For example, in the column control circuit region R illustrated in FIG. 32 CC sixteen sense amplifier circuits SADL<16n> to SADL<16n + 15> arranged from the negative side in the Y direction to the positive side in the Y direction are each connected to sixteen bit lines BL arranged continuously from the negative side in the X direction to the positive side in the X direction. However, such a configuration is merely an example, and the correspondence between the bit lines BL and the sense amplifier circuits SADL can be adjusted as appropriate.

[0189] For example, the column control circuit region R illustrated in FIG. 32 CC In this case, eight sense amplifier circuits SADL and eight latch circuits XDL are connected to a single common wiring DBUS. However, such a configuration is merely an example, and the number of sense amplifier circuits SADL and latch circuits XDL connected to a single DBUS can be adjusted as appropriate.

[0190] Also, in the above embodiments, an example of applying to a NAND flash memory has been described. However, the technology described in this specification is applicable to configurations other than NAND flash memories, such as, for example, three-dimensional NOR flash memories. Further, the technology described in this specification is applicable to configurations other than flash memories, such as, for example, three-dimensional DRAMs.

[0191] [Example of DRAM] FIG. 41 is a schematic block diagram showing a configuration example of DRAM1. FIG. 42 is a schematic circuit diagram showing a configuration example of the memory cell array 11 of DRAM1.

[0192] As shown in FIG. 41, DRAM1 includes a memory cell array 11, an input / output circuit 20, a word line driver 30 (denoted as WLD in FIG. 41), a row decoder 34, a read / write amplifier 43, a command decoder 51, a sense unit 60, a column decoder 61, a command address input circuit 70, a clock input circuit 81, an internal clock generation circuit 82, and a voltage generation circuit 90.

[0193] Also, DRAM1 includes a plurality of external terminals such as clock terminals CK, / CK, command / address terminal CAT, data terminal DQT, data mask terminal DMT, and power supply terminals VPP, VDD, VSS, VDDQ, VSSQ.

[0194] The memory cell array 11 includes a plurality of memory layers ML D as shown in FIG. 42. These plurality of memory layers ML D are arranged in a direction perpendicular to the substrate. Also, these plurality of memory layers ML DEach includes bit lines BL D and bit lines BL D connected to a plurality of transistors Tr D and a plurality of capacitors Cap connected to these plurality of transistors Tr D and a plate line PL commonly connected to these plurality of capacitors Cap. The source electrode of transistor Tr D is connected to bit line BL D The drain electrode of transistor Tr D is connected to capacitor Cap. The gate electrode of transistor Tr D is connected to word line WL D Also, word line WL D and plate line PL are each connected to transistors Tr D in a plurality of memory layers ML D respectively.

[0195] When a low-level or high-level voltage is applied to word line WL D and a low-level or high-level voltage is applied to bit line BL, transistor Tr D becomes on or off. As a result, charge is accumulated in capacitor Cap or the accumulated charge is discharged.

[0196] In DRAM1, data is held in association with the charge stored in capacitor Cap. Also, in DRAM1, in order to maintain the charge stored in capacitor Cap, a process of periodically refreshing the charge of capacitor Cap is performed by a refresh circuit. In FIG. 41, for convenience of explanation, the refresh circuit and the like are omitted.

[0197] In the plurality of memory cells in memory cell array 11 (in DRAM1, transistors Tr DA memory address is associated with each combination of the transistor Tr and the capacitor Cap. Among the plurality of external terminals, the command / address terminal CAT (FIG. 41) receives a memory address from an external device such as a memory controller. The memory address received by the command / address terminal CAT is transmitted to the command address input circuit 70. When the command address input circuit 70 receives a memory address, it transmits the decoded row address XADD to the row decoder 34 and the decoded column address YADD to the column decoder 61.

[0198] Also, the command / address terminal CAT receives a command from an external device such as a memory controller. The command received by the command / address terminal CAT is transmitted to the command address input circuit 70. When the command address input circuit 70 receives a command, it transmits the received command as an internal command signal ICMD to the command decoder 51.

[0199] The command decoder 51 includes a circuit that decodes the internal command ICMD and generates a signal for executing the internal command. The command decoder 51 transmits, for example, an activated command ACT and a refresh command AREF to the row decoder 34. The row decoder 34 selects the word line WL D according to the command ACT and the refresh command AREF received from the command decoder 51. The row decoder 34 transmits a signal indicating the selected word line WL D to the word line driver 30.

[0200] The word line driver 30 is connected to the word line WL D (FIG. 42). The word line driver 30 receives a signal from the row decoder 34 and applies a low-level or high-level voltage to the word line WL D indicated by that signal.

[0201] Also, the command decoder 51 transmits, for example, a read / write command R / W to the column decoder 61. The column decoder 61 selects bit lines BL (FIG. 42) according to the read / write command R / W received from the command decoder 51. The column decoder 61 transmits a signal indicating the selected bit line BL to the sense unit 60.

[0202] The sense unit 60 is connected to the bit lines BL. The sense unit 60 receives a signal from the column decoder 61 and applies a low-level or high-level voltage to the bit lines BL indicated by the signal.

[0203] When reading data, a memory address is received together with a read command by the command / address terminal CAT. Thereby, data is read from the memory cells MC in the memory cell array 11 specified by the memory address. The read data is output externally from the data terminal DQT via the sense unit 60, the read / write amplifier 43, and the input / output circuit 20.

[0204] When writing data, a memory address is received together with a write command by the command / address terminal CAT, and the data terminal DQT receives the write data. Also, if necessary, the data mask terminal DMT receives a data mask. The write data is transmitted to the memory cell array 11 via the input / output circuit 20, the read / write amplifier 43, and the sense unit 60. Thereby, the write data is written to the memory cells specified by the memory address.

[0205] The read / write amplifier 43 includes various latch circuits that temporarily hold the read data and the write data.

[0206] The voltage generation circuit 90 is connected to the power supply terminals VPP, VDD, and VSS. The voltage generation circuit 90 is supplied with power supply voltages from the power supply terminals VPP, VDD, and VSS, and generates various internal voltages VOD, VARY, and VPERI based on these power supply voltages. The internal voltages VOD and VARY are mainly used in the sense unit 60, and the internal voltage VPERI is used in other peripheral circuits.

[0207] Also, the input / output circuit 20 is connected to the power supply terminals VDDQ and VSSQ. Dedicated power supply voltages are supplied to the power supply terminals VDDQ and VSSQ so that power supply noise generated in the input / output circuit 20 does not propagate to other circuit blocks. Note that the power supply voltages supplied to the power supply terminals VDDQ and VSSQ may be the same as the power supply voltages supplied to the power supply terminals VDD and VSS.

[0208] Complementary external clock signals are input to the clock terminals CK and / CK. The external clock signals are supplied to the internal clock generation circuit 82. The internal clock generation circuit 82 generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to the internal clock generation circuit 82 and the command decoder 51.

[0209] When the internal clock generation circuit 82 is enabled by the clock enable from the command address input circuit 70, it generates various internal clock signals LCLK. The internal clock signals LCLK are used to measure the timings of various internal operations. For example, the internal clock signal LCLK is output to the input / output circuit 20. The input / output circuit 20 transmits and receives data from the data terminal DQT based on the input internal clock signal LCLK.

[0210] FIG. 43 is a schematic circuit diagram showing a memory cell array 11' according to another configuration example of the DRAM1.

[0211] As shown in FIG. 43, the memory cell array 11' includes a plurality of memory layers ML D '. These plurality of memory layers ML D´ are arranged in a direction perpendicular to the substrate. Further, these plurality of memory layers ML D ´ each include a word line WL D ´ and a word line WL D ´ connected to a plurality of transistors Tr D ´ and these plurality of transistors Tr D ´ are connected to a plurality of capacitors Cap and a plate line PL commonly connected to these plurality of capacitors Cap. The source electrode of the transistor Tr D ´ is connected to the bit line BL D ´. The drain electrode of the transistor Tr D ´ is connected to the capacitor Cap. The gate electrode of the transistor Tr D ´ is connected to the word line WL D . Also, the bit line BL D ´ and the plate line PL are each connected to the transistors Tr D ´ in the plurality of memory layers ML D ´.

[0212] Even in such a configuration, with an increase in the number of the memory layers ML D , there is a risk that the area of the peripheral circuit increases on a semiconductor substrate (not shown). Also, for such a configuration as well, the technology described in this specification can be applied.

[0213] [Others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0214] 110... Conductive layer, 120... Semiconductor layer, 130... Gate insulating film, 151, 152, 153... Portions, 200... Semiconductor substrate, C M , C P ... Chip, Tr... Transistor, BL... Bit line, WL... Word line, MC... Memory cell, M0, M1, D0, D1, D2, D3, D4... Wiring layers, MB, DB... Chip bonding electrode layers, Gm1... Wiring group, m1, m1a, m1b... Wires, P I1 , P I2 ... Bonding electrode.

Claims

1. A semiconductor memory device comprising a first chip and a second chip bonded via a plurality of bonding electrodes, wherein the first chip comprises a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate, and the second chip comprises a plurality of first conductive layers arranged in a first direction intersecting the surface of the semiconductor substrate, a plurality of semiconductor layers extending in the first direction and facing the plurality of first conductive layers, a first wiring layer provided between the plurality of semiconductor layers and the first chip and including a plurality of bit lines electrically connected to the plurality of semiconductor layers, a second wiring layer provided between the first wiring layer and the first chip and including a plurality of wirings, and a second chip bonding electrode layer provided between the second wiring layer and the first chip and including a plurality of first bonding electrodes which are a part of the plurality of bonding electrodes, wherein the plurality of bit lines extend in a second direction intersecting the first direction and are arranged in a third direction intersecting the first direction and the second direction, each of the plurality of wirings in the second wiring layer is provided in a region overlapping one of the plurality of bit lines when viewed from the first direction, has a first portion extending in the second direction and electrically connected to the one of the plurality of bit lines, and is provided in a region overlapping one of the plurality of first bonding electrodes when viewed from the first direction and has a second portion connected to the one of the plurality of first bonding electrodes, and at least a part of the plurality of wirings in the second wiring layer each extends in the third direction and has a third portion connected to one end portion in the second direction of the first portion and one end portion in the second direction of the second portion.

2. The semiconductor memory device according to claim 1, wherein in some of the wirings in the second wiring layer, one end portion in the second direction of the first portion is connected to the second portion.

3. A semiconductor memory device comprising a first chip and a second chip bonded via a plurality of bonding electrodes, wherein the first chip comprises a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate, and the second chip comprises a plurality of first conductive layers arranged in a first direction intersecting the surface of the semiconductor substrate, a plurality of semiconductor layers extending in the first direction and facing the plurality of first conductive layers, a first wiring layer provided between the plurality of semiconductor layers and the first chip and including a plurality of bit lines electrically connected to the plurality of semiconductor layers, and a second wiring layer provided between the first wiring layer and the first chip and including a plurality of wiring groups. ​ ​ ​ ​ ​ ​ A second chip bonding electrode layer provided between the second wiring layer and the first chip and including a plurality of first bonding electrodes that are a part of the plurality of bonding electrodes and comprising The plurality of bit lines extend in a second direction intersecting the first direction and are arranged in a third direction intersecting the first direction and the second direction. Each of the plurality of wiring groups in the second wiring layer includes a plurality of wirings. Each of the plurality of wirings is provided in a region overlapping one of the plurality of bit lines when viewed from the first direction, extends in the second direction, and has a first portion electrically connected to the one of the plurality of bit lines; and a second portion provided in a region overlapping one of the plurality of first bonding electrodes when viewed from the first direction and connected to the one of the plurality of first bonding electrodes and comprising At least a part of the plurality of wirings each extends in the third direction and has a third portion connected to one end portion of the first portion in the second direction and one end portion of the second portion in the second direction. A semiconductor memory device comprising.

4. In a part of the wirings in the second wiring layer, one end portion of the first portion in the second direction is connected to the second portion. The semiconductor memory device according to claim 3.

5. One of the plurality of wiring groups is defined as a first wiring group, The pitch in the third direction of the first portions of the plurality of wirings included in the first wiring group is defined as a first pitch, When the pitch in the third direction of the second portions of the plurality of wirings included in the first wiring group is defined as a second pitch, The first pitch is larger than the second pitch. The semiconductor memory device according to claim 3 or 4.

6. One of the plurality of wiring groups is defined as a first wiring group, Another one of the plurality of wiring groups, which is adjacent to the first wiring group in the second direction, is defined as a second wiring group, When a plurality of first bonding electrodes arranged in the second direction corresponding to the plurality of wiring groups arranged in the second direction among the plurality of first bonding electrodes are defined as a plurality of second bonding electrodes, The pitch in the second direction of the plurality of second bonding electrodes is equal to or greater than the sum of the width of the first wiring group in the second direction and the distance in the second direction between the first wiring group and the second wiring group. The semiconductor memory device according to any one of claims 3 to 5.

7. The width of the first wiring group in the second direction is The width in the second direction of the first portion of the first wiring, which is one of the plurality of wirings included in the first wiring group, The width in the second direction of the second portion of the second wiring, which is another one of the plurality of wirings included in the first wiring group, The total value of the widths in the second direction of the third portions of the plurality of third wirings, which are the plurality of wirings included in the first wiring group excluding the first wiring and the second wiring, The total value of the distances in the second direction between the plurality of wirings included in the first wiring group is the total value of The semiconductor memory device according to claim 6.

8. The second chip includes a memory plane, The first chip includes a circuit region provided in a region overlapping the memory plane when viewed from the first direction, The circuit region Two first circuit regions arranged in the third direction, One or a plurality of second circuit regions provided between the two first circuit regions and arranged in a number of a (a is an integer of 1 or more) in the second direction and in a number of b (b is an integer of 1 or more) in the third direction are provided Each of the two first circuit regions includes a plurality of first transistors electrically connected to at least a part of the plurality of first conductive layers, Each of the one or a plurality of second circuit regions includes a plurality of second transistors electrically connected to a part of the plurality of bit lines The semiconductor memory device according to any one of claims 3 to 7.

9. The memory plane A first region provided with the plurality of semiconductor layers, A second region including a plurality of first via contact electrodes connected to the plurality of first conductive layers are provided, A part of the first circuit region is provided in a region overlapping the second region when viewed from the first direction, Another part of the first circuit region is provided in a region overlapping the first region when viewed from the first direction The semiconductor memory device according to claim 8.

10. When the first region is divided into 2b regions in the third direction and these 2b regions are defined as third regions, Each of the plurality of wiring groups is provided within the range of any one of these 2b third regions The semiconductor memory device according to claim 9.

11. When the first region is divided into 2b regions in the third direction and these 2b regions are defined as third regions, The maximum length in the third direction of the plurality of wirings included in the plurality of wiring groups is smaller than the width in the third direction of these 2b third regions The semiconductor memory device according to claim 9 or 10.

12. Said b is an integer of 3 or more. The semiconductor memory device according to any one of Claims 8 to 11.

13. The second circuit region includes n sense amplifier circuits arranged in the second direction. When the second circuit region is divided into n regions in the second direction, and these n regions are defined as fourth regions, each of the plurality of wiring groups is provided within the range of any one of these n fourth regions. The semiconductor memory device according to any one of Claims 8 to 12.

14. The number of the plurality of wiring groups arranged in the second direction is n. The semiconductor memory device according to Claim 13.

15. The number of the plurality of wiring groups arranged in the second direction is an integral multiple of n. The semiconductor memory device according to Claim 13.

16. The circuit region includes a third circuit region provided between the first circuit region and the second circuit region. The third circuit region outputs signals to a plurality of signal lines connected to the gate electrodes of the plurality of first transistors. The semiconductor memory device according to any one of Claims 8 to 15.

17. It includes a second via contact electrode provided between the first wiring layer and the second wiring layer. One end portion of the second via contact electrode in the first direction is connected to one of the plurality of bit lines. The other end portion of the second via contact electrode in the first direction is connected to the first portion of one of the plurality of wirings. The semiconductor memory device according to any one of Claims 1 to 16.

18. The length of the second via contact electrode in the second direction is greater than the length of the second via contact electrode in the third direction. The semiconductor memory device according to Claim 17.

19. One end portion of one of the plurality of first bonding electrodes in the first direction is connected to the second portion of one of the plurality of wirings. The semiconductor memory device according to any one of Claims 1 to 18.

20. The first chip includes a third wiring layer provided between the semiconductor substrate and the second chip, and a first chip bonding electrode layer provided between the third wiring layer and the second chip and including a plurality of third bonding electrodes which are a part of the plurality of bonding electrodes. The third wiring layer includes a fourth wiring connected to one end portion of one of the plurality of third bonding electrodes in the first direction and connected to one of the plurality of bit lines through the one of the plurality of third bonding electrodes. Connected to one end portion in the other one of the first directions among the plurality of third bonding electrodes, connected to the other one of the plurality of bit lines through the other one of the plurality of third bonding electrodes, a fifth wiring whose position in the third direction is different from that of the fourth wiring, A sixth wiring provided between the fourth wiring and the fifth wiring and extending in the second direction The semiconductor memory device according to any one of claims 1 to 19, comprising

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