Protection Circuit and Semiconductor Device

Abstract

To improve the operation reliability.SOLUTION: A protection circuit according to an embodiment includes first to third power source lines, a first resistor, a first capacitor, a first transistor, and first to third inverters. The first resistor is connected between the first power source line and a first node. The first capacitor is connected between the first node and the third power source line. The first transistor is connected between the second power source line and the third power source line. The first inverter includes a first power source end connected to the second power source line, a second power source end connected to the third power source line, and an input end connected to the first node. The second inverter includes a first power source end connected to the second power source line, a second power source end connected to the third power source line, and an input end connected to an output end of the first inverter. The third inverter includes a first power source end connected to the second power source line, a second power source end connected to the third power source line, an input end connected to an output end of the second inverter, and an output end connected to a gate of the first transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a protection circuit and a semiconductor device.

Background Art

[0002] A protection circuit against ESD (Electro Static Discharge) is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the operation reliability.

Means for Solving the Problems

[0005] The protection circuit according to the embodiment includes a first power line, a second power line, a third power line, a first resistor, a first capacitor, a first transistor, a first inverter, a second inverter, and a third inverter. The first resistor is connected between the first power line and the first node. The first capacitor is connected between the first node and the third power line. The first transistor is connected between the second power line and the third power line. The first inverter has a first power supply terminal connected to the second power line, a second power supply terminal connected to the third power line, and an input terminal connected to the first node. The second inverter has a first power supply terminal connected to the second power line, a second power supply terminal connected to the third power line, and an input terminal connected to the output terminal of the first inverter. The third inverter has a first power supply terminal connected to the second power line, a second power supply terminal connected to the third power line, an input terminal connected to the output terminal of the second inverter, and an output terminal connected to the gate of the first transistor.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the description, components having substantially the same function and configuration are denoted by the same reference numerals. Also, the embodiments shown below illustrate the technical idea. The embodiments do not specify the material, shape, structure, arrangement, etc. of the components. The embodiments can be variously modified.

[0008] [Embodiment] The protection circuit according to the embodiment will be described.

[0009] [1] Configuration [1-1] Overall Configuration of Semiconductor Device 1 FIG. 1 is a circuit diagram for explaining a configuration example of a semiconductor device 1 including a protection circuit 10 according to an embodiment. The semiconductor device 1 is a device that performs various operations using electric power supplied from the outside. The semiconductor device 1 is, for example, an IC (Integrated Circuit) chip.

[0010] The semiconductor device 1 includes power supply lines PL1, PL2, and PL3, terminals T1, T2, and T3, a protection circuit 10, a regulator circuit 11, and a functional circuit 12.

[0011] Each of the power supply lines PL1, PL2, and PL3 is a wiring. Each of the power supply lines PL1, PL2, and PL3 is used to supply a power supply voltage to each circuit included in the semiconductor device 1.

[0012] Each of the terminals T1, T2, and T3 is a power supply terminal of the semiconductor device 1. Terminal T1 is connected to the power supply line PL1. For example, a power supply voltage VDDH is applied to terminal T1. The power supply voltage VDDH is, for example, 5V. Terminal T2 is connected to the power supply line PL2. For example, a power supply voltage VDDL lower than the power supply voltage VDDH is output from terminal T2. The power supply voltage VDDL is, for example, 1.5V. Terminal T3 is connected to the power supply line PL3. Terminal T3 is grounded to a voltage lower than the power supply voltages VDDH and VDDL (for example, 0V).

[0013] The protection circuit 10 protects the circuits connected to the power supply lines PL1 and PL2 from ESD. The protection circuit 10 is connected to the power supply lines PL1, PL2, and PL3.

[0014] The regulator circuit 11 generates a power supply voltage VDDL lower than the power supply voltage VDDH from the power supply voltage VDDH applied to the power supply line PL1 and outputs it to the power supply line PL2. The regulator circuit 11 is connected to the power supply lines PL1 and PL2.

[0015] The functional circuit 12 is a circuit that realizes various operations executed by the semiconductor device 1. The functional circuit 12 is connected to the power supply lines PL1, PL2, and PL3.

[0016] [1-2] Configuration of the protection circuit 10 Continuing to refer to FIG. 1, the configuration of the protection circuit 10 will be described.

[0017] The protection circuit 10 includes a resistor R1, a capacitor C1, inverters INV1 to INV6, transistors M1 and M2, and a diode DI1.

[0018] One end of resistor R1 is connected to power line PL1. The other end of resistor R1 is connected to node N1. One electrode of capacitor C1 is connected to node N1. The other electrode of capacitor C1 is connected to power line PL3.

[0019] When the voltage of power line PL1 changes, the voltage at node N1 changes with a delay corresponding to the RC time constant. The RC time constant is determined by the resistance value of resistor R1 and the capacitance value of capacitor C1. In the embodiment, the resistance value of resistor R1 and the capacitance value of capacitor C1 are set such that the RC time constant is much longer than the time of the instantaneous current inflow caused by ESD. In other words, while the instantaneous current inflow due to ESD is occurring, the voltage at node N1 is kept substantially constant.

[0020] Inverter INV1 inverts the logic level at node N1 and outputs it to inverter INV2. The positive power supply terminal of inverter INV1 is connected to power line PL1. The negative power supply terminal of inverter INV1 is connected to power line PL3. Inverter INV2 inverts the logic level received from inverter INV1 and outputs it to inverter INV3. The positive power supply terminal of inverter INV2 is connected to power line PL1. The negative power supply terminal of inverter INV2 is connected to power line PL3. Inverter INV3 inverts the logic level received from inverter INV2 and outputs it to the gate of transistor M1. The positive power supply terminal of inverter INV3 is connected to power line PL1. The negative power supply terminal of inverter INV3 is connected to power line PL3.

[0021] Each of inverters INV1 to INV3 is composed of transistors with a breakdown voltage that can operate at power supply voltage VDDH. Hereinafter, a transistor with a breakdown voltage that can operate at power supply voltage VDDH is referred to as a high breakdown voltage transistor.

[0022] Transistor M1 is an N-type MOSFET. The drain of transistor M1 is connected to power line PL1. The source of transistor M1 is connected to power line PL3.

[0023] Inverter INV4 inverts the logic level of node N1 and outputs it to inverter INV5. The positive power supply terminal of inverter INV4 is connected to power supply line PL2. The negative power supply terminal of inverter INV4 is connected to power supply line PL3. Inverter INV5 inverts the logic level received from inverter INV4 and outputs it to inverter INV6. The positive power supply terminal of inverter INV5 is connected to power supply line PL2. The negative power supply terminal of inverter INV5 is connected to power supply line PL3. Inverter INV6 inverts the logic level received from inverter INV5 and outputs it to the gate of transistor M2. The positive power supply terminal of inverter INV6 is connected to power supply line PL2. The negative power supply terminal of inverter INV6 is connected to power supply line PL3.

[0024] Inverter INV4 is composed of high-voltage transistors. Each of inverters INV5 and INV6 is composed of transistors with a breakdown voltage that cannot operate at power supply voltage VDDH but can operate at power supply voltage VDDL. Hereinafter, a transistor with a breakdown voltage that cannot operate at power supply voltage VDDH but can operate at power supply voltage VDDL is called a low-voltage transistor. The high-voltage transistor and the low-voltage transistor differ in at least one of the gate length and the thickness of the gate oxide film. The high-voltage transistor has a longer gate length, or a thicker gate oxide film, or a longer gate length and a thicker gate oxide film than the low-voltage transistor.

[0025] Transistor M2 is an N-type MOSFET. The drain of transistor M2 is connected to power supply line PL2. The source of transistor M2 is connected to power supply line PL3.

[0026] The anode of diode DI1 is connected to power supply line PL2. The cathode of diode DI1 is connected to power supply line PL1.

[0027] In the embodiment, each of the inverters INV1 to INV3 and the inverters INV4 to INV6 operates with a voltage of 1 / 2 of the power supply voltage as the threshold voltage of the logic level. The threshold voltage of the logic level is the voltage used as a threshold when determining whether the logic level of a node is at the "H" level or the "L" level. For example, when the power supply voltage is 5V, the threshold voltage of the logic level is 2.5V. 3V is determined as the "H" level, and 2V is determined as the "L" level. Also, when the power supply voltage rises, the threshold voltage of the logic level also rises. For example, when the power supply voltage is 10V, the threshold voltage of the logic level is 5V. In this specification, in a state where the power supply voltage is approximately 0V or in a state where the power supply voltage is low and the circuit does not operate normally, the logic level is not defined.

[0028] [2] Operation The protection circuit 10 according to the embodiment performs different operations according to conditions. In this specification, the operation of the protection circuit 10 will be described by taking two conditions, namely, the device test and the system test, as examples. The device test and the system test are tests in which ESD is applied to the object to be tested using a test device. The device test uses a single device as the object to be tested. The system test uses a system to which a power supply voltage is applied and which is operating as the object to be tested. Hereinafter, the ESD applied in the device test is referred to as device ESD, and the ESD applied in the system test is referred to as system ESD.

[0029] [2-1] Operation of the protection circuit 10 in the device test First, with reference to FIGS. 2 and 3, the operation of the protection circuit 10 according to the embodiment in a device test will be described. FIG. 2 is a circuit diagram for explaining the operation in a device test of a semiconductor device including the protection circuit according to the embodiment. FIG. 3 is a table for explaining the operation in a device test of the protection circuit according to the embodiment. As shown in FIG. 2, one end of the device test apparatus TD1 is connected to the terminal T1 via the switch SW1. The other end of the device test apparatus TD1 is connected to the terminal T3 and grounded. The device test apparatus TD1 can apply a device ESD to a device connected to the device test apparatus TD1.

[0030] In a device test, the device test apparatus TD1 applies a device ESD to the semiconductor device 1. The device test is, for example, an HBM (Human Body Model) test, an MM (Machine Model) test, a CDM (Charged Device Model) test, or the like. The state before the device test apparatus TD1 applies a device ESD to the semiconductor device 1 is defined as the first state, and the state in which the device ESD is being applied is defined as the second state, and they will be described in order.

[0031] (First state: State before applying device ESD) In the first state, the switch SW1 disconnects the device test apparatus TD1 from the terminal T1. The semiconductor device 1 is not supplied with a power supply voltage and is sufficiently discharged. The voltage of the power supply line PL1 is 0V. The voltage of the power supply line PL2 is 0V. The voltage of the node N1 is 0V because the capacitor C1 is sufficiently discharged. The logic levels of the node N1 determined by the inverter INV1 and the logic level of the node N1 determined by the inverter INV4 are not defined because the inverters INV1 to INV6 are not operating. The transistors M1 and M2 are in an off state because no power supply voltage is supplied.

[0032] (Second state: State in which device ESD is being applied) In the second state, switch SW1 connects device test apparatus TD1 and terminal T1. Then, device test apparatus TD1 applies the current of device ESD to terminal T1. Since current is input via terminal T1, the voltage of power line PL1 rises. In the second state, the voltage of power line PL1 is controlled to a clamp voltage on the high voltage side, for example, 9V or less, by the function of this ESD protection circuit. The clamp voltage on the high voltage side is determined so as not to damage the high voltage operation circuit of functional circuit 12.

[0033] Although the voltage of power line PL1 has risen due to ESD, since it is not a normal power supply sequence, the operation of regulator circuit 11 is indeterminate. The voltage of power line PL2 is also controlled to a clamp voltage on the low voltage side, for example, 3V or less, by the function of this ESD protection circuit. The clamp voltage on the low voltage side is determined so as not to damage the low voltage operation circuit of functional circuit 12.

[0034] The RC time constant determined by the resistance value of resistor R1 and the capacitance value of capacitor C1 is sufficiently larger than the time during which the power supply voltage is boosted by a high-speed surge current such as ESD. Therefore, the voltage of node N1 is maintained at 0V during ESD surge application. The threshold voltage of the logic level of inverter INV1 is about 1 / 2 of the clamp voltage of power line PL1 during ESD application. Thus, inverter INV1 determines that the voltage of node N1, which is 0V, is at the "L" level. The threshold voltage of the logic level of inverter INV4 is about 1 / 2 of the clamp voltage of power line PL2 during ESD application. Thus, inverter INV4 determines that the voltage of node N1, which is 0V, is at the "L" level.

[0035] Inverter INV1 outputs an "H" level to inverter INV2. Inverter INV2 inverts the received "H" level and outputs an "L" level to inverter INV3. Inverter INV3 inverts the received "L" level and outputs an "H" level to the gate of transistor M1. Since an "H" level is applied to the gate of transistor M1, it turns on. The turned-on transistor M1 discharges power line PL1.

[0036] Inverter INV4 outputs an “H” level to inverter INV5. Inverter INV5 inverts the received “H” level and outputs an “L” level to inverter INV6. Inverter INV6 inverts the received “L” level and outputs an “H” level to the gate of transistor M2. Since an “H” level is applied to the gate of transistor M2, it turns on. When transistor M2 is turned on, power line PL2 is discharged.

[0037] In this way, when device ESD is applied to semiconductor device 1, transistors M1 and M2 turn on, and protection circuit 10 can protect functional circuit 12 from high voltage.

[0038] [2-2] Operation of Protection Circuit 10 in System Test Subsequently, with reference to FIGS. 4 and 5, the operation of protection circuit 10 according to the embodiment in a system test will be described. FIG. 4 is a circuit diagram for explaining the operation in a system test of a semiconductor device including the protection circuit according to the embodiment. FIG. 5 is a table for explaining the operation in a system test of the protection circuit according to the embodiment.

[0039] As shown in FIG. 4, system SYS includes semiconductor device 1 and external protection device PD. External protection device PD turns on when the voltage difference across both ends exceeds threshold voltage Vpd and functions as a current path to protect semiconductor device 1 from high voltage due to system-level ESD. Threshold voltage Vpd is, for example, 12V. One end of external protection device PD is connected to terminal T1. The other end of external protection device PD is connected to terminal T3.

[0040] The positive output of the power supply PS is connected to terminal T1. The negative output of the power supply PS is connected to and grounded at terminal T3. The power supply PS supplies the power supply voltage VDDH to the system SYS. The power supply voltage VDDH is 5V. Also, one end of the system test device TD2 is connected to terminal T1 via the switch SW2. The other end of the system test device TD2 is connected to terminal T3. The system test device TD2 can apply system ESD to the system connected to the system test device TD2.

[0041] In the system test, the system test device TD2 applies system ESD to the system SYS to which the power supply voltage is supplied. The system test is a test defined, for example, in IEC61000-4-2. The state before the system test device TD2 applies system ESD is defined as the first state, and the state when the system test device TD2 is applying system ESD is defined as the second state, and will be described in order.

[0042] (First state: State before applying system ESD) In the first state, the switch SW2 disconnects the system test device TD2 from terminal T1. The system SYS is supplied with 5V, which is the power supply voltage VDDH, from the power supply PS and is operating. The voltage of the power supply line PL1 is 5V.

[0043] The regulator circuit 11 generates 1.5V, which is the power supply voltage VDDL, from the voltage of 5V on the power supply line PL1 and outputs it to the power supply line PL2. The voltage of the power supply line PL2 is 1.5V.

[0044] The capacitor C1 is charged with 5V on the power supply line PL1 via the resistor R1. Therefore, the voltage of the node N1 is 5V. The logic level threshold voltage of the inverter INV1 is 2.5V, which is higher than half of the voltage of 5V on the power supply line PL1. Therefore, the inverter INV1 determines that the voltage of the node N1 is at the "H" level. The logic level threshold voltage of the inverter INV4 is 0.75V, which is higher than half of the voltage of 1.5V on the power supply line PL2. Therefore, the inverter INV4 determines that the voltage of the node N1 is at the "H" level.

[0045] Inverter INV1 outputs an "L" level to inverter INV2. Inverter INV2 inverts the received "L" level and outputs an "H" level to inverter INV3. Inverter INV3 inverts the received "H" level and outputs an "L" level to the gate of transistor M1. Since an "L" level is applied to the gate of transistor M1, it turns off.

[0046] Inverter INV4 outputs an "L" level to inverter INV5. Inverter INV5 inverts the received "L" level and outputs an "H" level to inverter INV6. Inverter INV6 inverts the received "H" level and outputs an "L" level to the gate of transistor M2. Since an "L" level is applied to the gate of transistor M2, it turns off.

[0047] In this way, in the first state where the system test device TD2 is disconnected, the system SYS operates using 5V which is the power supply voltage VDDH. In the first state, transistors M1 and M2 are in the off state.

[0048] (Second state: State where system ESD is applied) In the second state, switch SW2 connects the system test device TD2 and terminal T1. Then, the system test device TD2 applies the current of the system ESD to terminal T1. Since current is input via terminal T1, the voltage of the power supply line PL1 rises. In the second state, the state where the voltage of the power supply line PL1 has risen to 11V will be described.

[0049] Even when the voltage of the power supply line PL1 rises, the output voltage of the regulator circuit 11 does not change. The regulator circuit 11 outputs a voltage of 1.5V to the power supply line PL2. The voltage of the power supply line PL2 is 1.5V.

[0050] The RC time constant determined by the resistance value of resistor R1 and the capacitance value of capacitor C1 is much larger than the time during which the power supply voltage is boosted by a high-speed surge current such as a system ESD. Therefore, the voltage at node N1 maintains the voltage of 5V before the ESD surge application during the ESD surge application. The threshold voltage of the logic level of inverter INV1 is 5.5V, which is higher than half of the voltage of 11V on power supply line PL1. Thus, inverter INV1 determines the voltage of 5V at node N1 as the "L" level. The threshold voltage of the logic level of inverter INV4 is 0.75V, which is higher than half of the voltage of 1.5V on power supply line PL2. Thus, inverter INV4 determines the voltage of 5V at node N1 as the "H" level.

[0051] Inverter INV1 outputs an "H" level to inverter INV2. Inverter INV2 inverts the received "H" level and outputs an "L" level to inverter INV3. Inverter INV3 inverts the received "L" level and outputs an "H" level to the gate of transistor M1. Since an "H" level is applied to the gate of transistor M1, it turns on. The power supply line PL1 is discharged by the turned-on transistor M1.

[0052] Inverter INV4 outputs an "L" level to inverter INV5. Inverter INV5 inverts the received "L" level and outputs an "H" level to inverter INV6. Inverter INV6 inverts the received "H" level and outputs an "L" level to the gate of transistor M2. Since an "L" level is applied to the gate of transistor M2, it turns off.

[0053] In this way, when a system ESD is applied to system SYS and the voltage of power supply line PL1 rises to 11V, which is greater than twice the power supply voltage VDDH of 5V, transistor M1 turns on and transistor M2 maintains the off state.

[0054] Furthermore, when more time elapses from the second state, the voltage of the power line PL1 rises to 12V, and the external protection device PD is turned on. The semiconductor device 1 is protected from the high voltage due to system ESD by the turned-on external protection device PD.

[0055] [3] Effect According to the protection circuit 10 according to the embodiment described above, the operation reliability can be improved. Hereinafter, the detailed effects of the protection circuit 10 according to the embodiment will be described.

[0056] ESD may be applied to the semiconductor device both in the state of the device alone and in the state where the device is incorporated into the system and operating. Therefore, in order to protect the device from device ESD, a protection circuit is provided inside the device. Also, in order to protect the system from system ESD, an external protection device is provided in the system separately from the protection circuit inside the device. It is preferable that the protection circuit inside the device does not operate when system ESD is applied.

[0057] In the protection circuit 10 according to the embodiment, the inverters INV4 to INV6 that control the transistor M2 are connected to the power line PL2 and operate using the power supply voltage VDDL. The power supply voltage VDDL is a voltage generated by the regulator circuit 11. Therefore, even when system ESD is applied and the voltage of the power line PL1 rises, the power supply voltage VDDL does not rise. Thus, the inverter INV4 that operates using the power supply voltage VDDL has a logic level threshold voltage that does not rise under the influence of system ESD.

[0058] As a result, when a system ESD is applied, the protection circuit 10 according to the embodiment can determine that the inverter INV4 sets the node N1 to the "H" level without being affected by the voltage rise of the power line PL1. Therefore, when a system ESD is applied, the protection circuit 10 according to the embodiment can maintain the transistor M2 in the off state. By maintaining the transistor M2 in the off state, fluctuations in the power supply voltage VDDL can be suppressed, and the operational reliability can be improved.

[0059] [4]Modifications and the like In the embodiment, the case where the terminal T2 connected to the power line PL2 is provided has been described as an example, but the terminal T2 may be omitted.

[0060] In this specification, "connected" indicates being electrically connected, and for example, does not exclude having another element in between. Also, "being electrically connected" may be via an insulator as long as it can operate in the same manner as being electrically connected. Further, in the specification, the "on state" indicates that a voltage equal to or higher than the threshold voltage of the corresponding transistor is applied to the gate of the transistor. The "off state" indicates that a voltage lower than the threshold voltage of the corresponding transistor is applied to the gate of the transistor, and does not exclude the flow of a minute current such as the leakage current of the transistor.

[0061] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0062] 1…Semiconductor device, 10…Protection circuit, 11…Regulator circuit, 12…Functional circuit, T1~T3…Terminals, PL1~PL3…Power supply lines, R1…Resistor, C1…Capacitor, INV1~INV6…Inverters, M1,M2…Transistors, DI1…Diode, SYS…System, PD…External protection device, PS…Power supply, SW1,SW2…Switches, TD1…Device test apparatus, TD2…System test apparatus.

Claims

1. a first power line, a second power line, a third power line, a first resistor connected between the first power line and a first node, a first capacitor connected between the first node and the third power line, a first transistor connected between the second power line and the third power line, a first inverter having a first power terminal connected to the second power line, a second power terminal connected to the third power line, and an input terminal connected to the first node, a second inverter having a first power terminal connected to the second power line, a second power terminal connected to the third power line, and an input terminal connected to an output terminal of the first inverter, and a third inverter having a first power terminal connected to the second power line, a second power terminal connected to the third power line, an input terminal connected to an output terminal of the second inverter, and an output terminal connected to a gate of the first transistor A protection circuit comprising:

2. a first voltage is applied to the first power line, a second voltage lower than the first voltage is applied to the second power line, and a third voltage lower than both the first voltage and the second voltage is applied to the third power line, The protection circuit according to claim 1.

3. a second transistor connected between the first power line and the third power line, a fourth inverter having a first power terminal connected to the first power line, a second power terminal connected to the third power line, and an input terminal connected to the first node, a fifth inverter having a first power terminal connected to the first power line, a second power terminal connected to the third power line, and an input terminal connected to an output terminal of the fourth inverter, and a sixth inverter having a first power terminal connected to the first power line, a second power terminal connected to the third power line, an input terminal connected to an output terminal of the fifth inverter, and an output terminal connected to a gate of the second transistor The protection circuit according to claim 1, further comprising:

4. The protection circuit according to claim 1, wherein a thickness of a gate oxide film of a transistor included in the first inverter is thicker than a thickness of a gate oxide film of a transistor included in the second inverter.

5. The protection circuit according to claim 1, wherein a gate length of a transistor included in the first inverter is longer than a gate length of a transistor included in the second inverter.

6. The protection circuit according to claim 1, further comprising a diode having an anode connected to the second power line and a cathode connected to the first power line.

7. The protection circuit according to claim 2, a regulator circuit connected to the first power line and the second power line and outputting the second voltage to the second power line A semiconductor device comprising:

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