Method for forming a contact structure and semiconductor device thereof

Abstract

Disclosed are embodiments of a method for forming a contact structure and a semiconductor device thereof. In one example, the semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion that are in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method for forming a contact structure and a semiconductor device thereof.

Background Art

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become difficult and costly. As a result, the memory density for planar memory cells approaches the upper limit.

[0003] 3D memory architectures are capable of addressing the limitations of the density of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0004] Embodiments of a method for forming a contact structure and a semiconductor device thereof are disclosed herein.

[0005] In one example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

[0006] In another example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. The contact structure also includes that the lower surface of the first contact portion contacts the upper surface of the second contact portion at a contact interface where the lower surface of the first contact portion is below the upper surface of the conductive layer.

[0007] In yet another example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of a base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact portion extends from a second surface of the base structure into the base structure.

[0008] The accompanying drawings are incorporated herein and form a part of the specification. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and also enable those skilled in the art to make and use the present disclosure.

Brief Description of the Drawings

[0009]

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DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] Although specific configurations and arrangements are being discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can also be used in various other applications.

[0012] Note that references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0013] Generally, technical terms can be understood at least in part from their usage in context. For example, as used herein, the term "one or more" can be used, at least in part depending on the context, in the singular sense to describe any feature, structure, or characteristic, or in the plural sense to describe a combination of features, structures, or characteristics. Similarly, terms such as "a", "an", or "the", although repeated, can be understood, at least in part depending on the context, to convey either a singular usage or a plural usage. Additionally, it can be understood that the term "based on" is not necessarily intended to convey an exclusive set of factors, but instead, although repeated, can, at least in part depending on the context, allow for the possibility of the existence of additional factors that are not necessarily explicitly recited.

[0014] The meanings of "on", "above", and "over" in the present disclosure should be construed in the broadest manner, where "on" not only means "directly on" something, but also includes meaning "on" something with intervening features or layers therebetween, and "above" or "over" not only mean "above" or "over" something, but can also include meaning that it is "above" or "over" something (i.e., directly on top of something) without intervening features or layers therebetween, which should be readily understood.

[0015] Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," and "upper," may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for the purpose of facilitating the description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. The substrate itself may be patterned. The material added on the substrate may or may not be patterned. Moreover, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made from a non-conductive material such as glass, plastic, or a sapphire wafer.

[0017] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend across the entirety of a structure below or above it, or can have an extent smaller than the extent of the structure below or above it. Further, a layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes (or at the upper and lower surfaces) between the upper and lower surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductors and contact layers (interconnect lines and / or vertical interconnect access (VIA) contacts are formed therein) and one or more dielectric layers.

[0018] As used herein, the term "nominal / nominally" refers to the desired (or target) value of a characteristic or parameter related to a component or process operation that is set during the design phase of a product or process, along with a range of values above and / or below the desired value. The range of values can be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that can vary based on a particular technology node associated with the semiconductor device in question. Based on the particular technology node, the term "about" can indicate, for example, a value of a given quantity that varies within 10 - 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, a staircase structure refers to a set of surfaces, the set of surfaces including at least two horizontal surfaces (e.g., along the x-y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along the z-axis), each horizontal surface being adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and also being adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A "step" or "stair" refers to a vertical shift in height of a set of adjacent surfaces. In the present disclosure, the terms "stair" and "step" refer to one level of the staircase structure and are used interchangeably. In the present disclosure, the horizontal direction can refer to a direction (e.g., the x direction or the y direction) parallel to the upper surface of a substrate (e.g., a substrate providing a fabrication platform for forming a structure on the substrate), and the vertical direction can refer to a direction (e.g., the z direction) perpendicular to the upper surface of the structure.

[0020] As used herein, the term "3D NAND memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings" such as NAND memory strings) on a substrate that are laterally oriented such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0021] In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of a channel structure (e.g., known as sidewall selective epitaxial growth (SEG)). Compared to another type of semiconductor plug (e.g., bottom SEG) formed at the lower end of the channel structure, the formation of sidewall SEG avoids etching of the memory film and semiconductor channel on the lower surface of the channel hole (also known as "SONO" punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices with advanced technologies such as having 96 or more levels with a multi-deck architecture. Moreover, the sidewall SEG structure can be combined with a backside process to form source contacts from the backside of the substrate, avoid leakage current and parasitic capacitance between the front-side source contacts and word lines, and increase the effective device area.

[0022] Peripheral contacts (e.g., through-silicon contact (TSV)) formed in the peripheral region to facilitate electrical contact between the memory cells and the peripheral circuits can also be formed using a backside process in these 3D NAND memory devices. However, due to the increasing levels of 3D NAND memory devices, the fabrication of peripheral contacts faces difficulties. For example, the formation of peripheral contacts using a backside process often includes a two-step etching process (e.g., a first etching process to form a first opening above the substrate for a first contact portion, and a second etching process to form a second opening from the backside for a second contact portion). A conductive material is often deposited to fill the second opening, and a dielectric spacer is often deposited into the second opening before forming the second contact portion. The two-step etching and deposition process can be undesirably long and complex.

[0023] Figure 1 illustrates a cross-sectional view of an existing contact structure in a semiconductor device 100. The semiconductor device 100 includes a base structure 104, an insulating structure 118 on the base structure 104, and a memory stack 106 on the base structure 104 and within the insulating structure 118. The base structure 104 includes an insulating layer 102 and a polysilicon layer 108 on the insulating layer 102. The memory stack 106 has a multi-level staircase structure and includes a plurality of alternating conductor layers 110 and dielectric layers 112. The semiconductor device 100 also includes a plurality of channel structures (not shown in Figure 1), which extend into the polysilicon layer 108 and are electrically connected to the polysilicon layer 108. The intersections of the channel structures and the conductor layers 110 form a plurality of memory cells. The semiconductor device 100 further includes a source contact 126, which extends into the insulating layer 102 and the polysilicon layer 108. The source contact 126 is in contact with the polysilicon layer 108 and is electrically connected to the channel structures for applying a source voltage. The semiconductor device 100 also includes a word line contact 114, which extends into the insulating structure 118 and is in contact with the conductor layers 110 of each level.

[0024] The semiconductor device 100 also includes a spacer 120 in the polysilicon layer 108 and a peripheral contact 116, which extends into the insulating structure 118, the spacer 120, and the insulating layer 102. The peripheral contact 116 includes a first contact portion 116-1 that extends into the insulating structure 118 and a second contact portion 116-2 that extends into the base structure 104. The first and second contact portions 116-1 and 116-2 are jointly connected to each other away from the memory stack 106. The second contact portion 116-2 and the source contact 126 are formed by a backside process. The spacer 120 insulates the second contact portion 116-2 from the polysilicon layer 108.

[0025] To form the spacer 120 and the second contact portion 116-2, after the first contact portion 116-1 is formed, a hole is formed by removing a portion of the base structure 104 from the back side (e.g., the lower surface). The hole extends into the insulating layer 102 and the polysilicon layer 108 until it contacts the first contact portion 116-1. Then, a dielectric material is deposited into the hole. After a recess etch to remove a portion of the dielectric material to expose the first contact portion 116-1, a conductive material is deposited on the dielectric layer to fill the hole and form the second contact portion 116-2. The portion of the dielectric material in the polysilicon layer 108 forms the spacer 120. Often, to ensure that the second contact portion 116-2 can form a desirable contact with the first contact portion 116-1, the hole is over-etched into the insulating structure 118. The upper surface of the hole (i.e., the upper surface of the second contact portion 116-2) is often not flat and, for example, is often not in the same plane as the upper surface of the polysilicon layer 108. For example, a protruding structure can be formed on the upper surface of the second contact portion 116-2 as shown in FIG. 1. As described above, the formation of the peripheral contact 116 (especially the second contact portion 116-2) can be long and complex. Existing fabrication processes for forming peripheral contacts (e.g., TSVs) need to be improved.

[0026] Various embodiments according to the present disclosure provide improved semiconductor devices and methods of fabricating the same. According to the disclosed fabrication method, in order to form a contact structure, a spacer structure is formed on the front side of a base structure. The spacer structure can be formed by an etching process, followed by a deposition process to fill an opening structure formed by the etching process. The etching process and the deposition process can be performed separately, but they can be incorporated into the current process flow without additional fabrication steps. For example, the etching process can be performed in any suitable etching / patterning process for forming another structure in the semiconductor device before the formation of the first contact portion, and the deposition process can be any suitable deposition process for forming another structure in the semiconductor device before the formation of the first contact portion. In some embodiments, the etching process is performed using a zero mask, which is used to pattern a structure in the substrate before any structure is formed on the base structure. In some embodiments, the etching process is the same patterning process for patterning a structure (e.g., a bottom-select-gate cut structure in a memory stack) on the base structure. In some embodiments, the deposition process can be the same deposition process for forming an insulating structure in which a memory stack is positioned. Thus, the fabrication process can be simplified.

[0027] The spacer structure can be formed from a trench structure or from holes in a polysilicon layer. The second contact portion is positioned within the spacer structure and is insulated from the polysilicon layer. In some embodiments, forming the spacer structure from holes in a conductive layer enables the lower surface of the first contact portion to be closer to the insulating layer, reduces the etching required to form the holes for forming the second conductor portion, and further simplifies the fabrication process.

[0028] FIG. 2A illustrates a cross-sectional view of an exemplary contact structure within semiconductor device 200 according to some embodiments. FIG. 2B illustrates a top view of the contact structure within semiconductor device 200 according to some embodiments. For ease of illustration, FIGS. 2A and 2B are described together.

[0029] As shown in FIG. 2A, the semiconductor device 200 includes a base structure 204, an insulating structure 218 on the base structure 204, and a contact structure 216 extending into the insulating structure 218 and the base structure 204. Also, the semiconductor device 200 can include a substrate, and the base structure 204 is positioned on the substrate. In some embodiments, the semiconductor device 200 includes a memory stack 206 on the base structure 204 and within the insulating structure 218. The semiconductor device 200 can include a word line contact 214, which is within the insulating structure 218, in contact with the memory stack 206, and electrically connected to the memory stack 206. In some embodiments, the semiconductor device 200 includes a source contact structure 226, which is in contact with the base structure 204 and electrically connected to the base structure 204. In some embodiments, the contact structure 216 is positioned in a peripheral region of the semiconductor device 200. The memory stack 206 can be positioned in a core region and / or a staircase region of the semiconductor device 200. By way of example, in the present disclosure, the semiconductor device is represented by a 3D NAND memory device, and the contact structure (e.g., 216) is described as a peripheral contact within the 3D NAND memory device. In some embodiments, the contact structure 216 electrically connects a peripheral circuit and a contact pad (not shown) on the opposite side of the base structure 204 of the semiconductor device 200, such that the peripheral circuit can be electrically connected to an external circuit through the contact pad. In some embodiments, the contact structure 216 is electrically connected to a peripheral circuit and the source contact structure 226 on the opposite side of the base structure 204 of the semiconductor device 200, such that the peripheral circuit is electrically connected to the source contact structure 226 and can control the operation of the source of the 3D NAND memory device.It should be understood that the structures, and fabrication methods for forming these contact structures, can likewise be used to form contact structures within any other suitable structure / device.

[0030] The substrate of semiconductor device 200 can comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In some embodiments, the substrate is a thinned substrate (e.g., a semiconductor layer), which has been thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. In some embodiments, the substrate has been removed and is not included within semiconductor device 200. Note that x, y, and z axes are included in the figures of the present disclosure to further illustrate the spatial relationships of the components within the semiconductor device. By way of example, the substrate of semiconductor device 200 includes two lateral surfaces (e.g., an upper surface and a lower surface) that extend laterally in the x and y directions (i.e., horizontally). The z direction represents a direction perpendicular to the x-y plane (i.e., the plane formed by the x and y directions). As used herein, whether one component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) of a semiconductor device (e.g., semiconductor device 200) is determined in the z direction (i.e., the vertical direction) with respect to the substrate of the semiconductor device when the substrate is positioned within the lowest plane of the semiconductor device in the z direction. The same concepts for explaining spatial relationships are applied throughout the present disclosure.

[0031] In some embodiments, semiconductor device 200 is part of a non-monolithic 3D NAND memory device, where components are formed separately on different substrates and then bonded in a face-to-face manner, a face-to-back manner, or a back-to-back manner. Any suitable digital, analog, and / or mixed-signal peripheral circuits (not shown) such as those used to facilitate the operation of semiconductor device 200 can be formed on a separate peripheral device substrate different from the memory array substrate on which the components shown in FIG. 2A are formed. The memory array substrate can be removed from semiconductor device 200, as will be described in detail below, and it should be understood that the peripheral device substrate can become the substrate of semiconductor device 200. Depending on the manner in which the peripheral device substrate and the memory array device substrate are bonded, it should be further understood that the memory array device (e.g., as shown in FIG. 2A) can be in its original position within semiconductor device 200 or can be inverted upside down. For ease of reference, FIG. 2A shows the state of semiconductor device 200 where the memory array device is in its original position (i.e., not inverted upside down). However, in some examples, it should be understood that the memory array devices shown in FIG. 2A can be inverted upside down within semiconductor device 200 and their relative positions can be changed accordingly. The same concepts for explaining spatial relationships apply throughout the present disclosure.

[0032] As shown in FIG. 2A, the base structure 204 can include an insulating layer 202 and a polysilicon layer 208 on the insulating layer 202. Optionally, the base structure 204 can include a stop layer 224 between the insulating layer 202 and the polysilicon layer 208. The insulating layer 202 can include one or more interlayer dielectric (ILD) layers (also known as "inter-metal dielectric (IMD) layers"), and interconnect lines and via contacts can be formed therein. The ILD layers of the insulating layer 202 can include a dielectric material, which can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the insulating layer 202 includes silicon oxide. The stop layer 224, if any, can be disposed directly on the insulating layer 202. The stop layer 224 can be a single-layer structure or a multi-layer structure. In some embodiments, the stop layer 224 is a single-layer structure and includes a high dielectric constant (high-k) dielectric layer. In some embodiments, the stop layer 224 is a double-layer structure and includes a first stop layer on a second stop layer. The first stop layer can include silicon nitride, and the second stop layer can include a high-k dielectric. The high-k dielectric layer can include, for example, aluminum oxide, hafnium oxide, zirconium oxide, or titanium oxide. In one example, the stop layer 224 can include aluminum oxide. As will be described in detail below, since the function of the stop layer 224 is to stop the etching of the channel holes, it should be understood that the stop layer 224 can include any other suitable material having a relatively high etching selectivity (e.g., greater than about 5) with respect to the materials in the layers thereon. In some embodiments, in addition to functioning as an etching stop layer, the stop layer 224 also functions as a backside substrate thinning stop layer.

[0033] The polysilicon layer 208 can be disposed directly on the stop layer 224. In some embodiments, a pad oxide layer (e.g., a silicon oxide layer) is disposed between the stop layer 224 and the polysilicon layer 208 to relieve the stress between the polysilicon layer 208 and the stop layer 224 (e.g., an aluminum oxide layer). The polysilicon layer 208, according to some embodiments, includes an N-type doped polysilicon layer. That is, the polysilicon layer 208 can be doped with any suitable N-type dopant (such as phosphorus (P), arsenic (Ar), or antimony (Sb), etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. The polysilicon layer 208 can include a polysilicon sub-layer 208-1 between the upper surface and the lower surface of the polysilicon layer 108 and can be conductively connected to the semiconductor channel of the 3D NAND memory string and the source contact structure of the semiconductor device 200. As will be described in detail below, due to the diffusion process, the polysilicon layer 208 can have a suitable uniform doping concentration profile in the vertical direction. The sub-layer 208-1 of the polysilicon layer 208 can have the same polysilicon material as the rest of the polysilicon layer 208, and the doping concentration can be uniform in the polysilicon layer 208 after diffusion, so it should be understood that the sub-layer 208-1 may not be distinguishable from the rest of the polysilicon layer 208 in the semiconductor device 200. Nevertheless, the sub-layer 208-1 refers to a part of the polysilicon layer 208 that is in contact with the semiconductor channel instead of the memory film in the lower part of the channel structure.

[0034] FIG. 2A shows that, as described above, the polysilicon layer 208 is above the stop layer 224, but it should be understood that the stop layer 224 may be above the polysilicon layer 208 in some examples. The reason is that the memory array devices shown in FIG. 2A can be inverted upside down, and their relative positions within the semiconductor device 200 can be changed accordingly. In some embodiments, the memory array devices shown in FIG. 2A are inverted upside down (at the top) within the semiconductor device 200 and are coupled to the peripheral devices (at the bottom), such that the stop layer 224 is above the polysilicon layer 208. In the present disclosure, the polysilicon layer 208 is described as a conductive layer for facilitating the electrical connection between the source contact of the semiconductor device 200 and the memory stack 206, but in various embodiments, any other suitable conductive material may also be formed between the memory stack 206 and the insulating layer 202 to perform a similar / same function as the polysilicon layer 208.

[0035] The memory stack 206 can include a plurality of alternating conductor layers 210 and dielectric layers 212 on the polysilicon layer 208. The conductor layers 210 and dielectric layers 212 in the memory stack 206 can be alternating in the vertical direction. In other words, except for those at the top or bottom of the memory stack 206, each conductor layer 210 can be adjacent to two dielectric layers 212 on both sides, and each dielectric layer 212 can be adjacent to two conductor layers 210 on both sides. The conductor layer 210 can include a conductive material, which includes, but is not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductor layer 210 can include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductor layer 210 can extend horizontally as a word line and end in one or more staircase structures of the memory stack 206. The dielectric layer 212 can include a dielectric material, which includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The memory stack 206 can have a staircase structure, and the staircase structure includes a plurality of steps (for example, extending horizontally along the x / y direction). Each step can include one or more pairs of conductor layers 210 and dielectric layers 212 (referred to as conductor / dielectric layer pairs). The word line contact 214 (extending into the insulating structure 218) can be in contact with and conductively connected to the upper conductor layer 210 of each step, as shown in FIG. 2A. The word line contact 214 can include a conductive material, which includes, but is not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. The insulating structure 218 can include a dielectric material, which includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0036] In some embodiments, semiconductor device 200 is a 3D NAND memory device and includes a plurality of memory cells formed within memory stack 206. The memory cells can be formed by intersections of 3D NAND memory strings within memory stack 206 and conductor layer 210. FIG. 6 illustrates a cross-sectional view of a channel structure within memory stack 206.

[0037] As shown in FIG. 6, channel structure 612 extends vertically through memory stack 206 and polysilicon layer 208 and terminates (if any) at stop layer 224. That is, channel structure 612 can include two portions, namely, a lower portion surrounded by polysilicon layer 208 (i.e., below the interface between polysilicon layer 208 and memory stack 206), and an upper portion surrounded by memory stack 206 (i.e., above the interface between polysilicon layer 208 and memory stack 206). As used herein, the "upper portion / end" of a component (e.g., channel structure 612) is the portion / end that is farther away from the substrate in the z-direction when the substrate is positioned within the lowest plane of semiconductor device 200, and the "lower portion / end" of a component (e.g., channel structure 612) is the portion / end that is closer to the substrate in the z-direction. In some embodiments, each channel structure 612 does not extend further beyond stop layer 224 because etching of the channel holes is stopped by stop layer 224. For example, the lower end of channel structure 612 can be nominally coplanar with the upper surface of stop layer 224.

[0038] The channel structure 612 can include a channel hole filled with a semiconductor material (e.g., as semiconductor channel 616) and a dielectric material (e.g., as memory film 614). In some embodiments, the semiconductor channel 616 includes silicon (e.g., amorphous silicon, polysilicon, or single crystal silicon, etc.). In one example, the semiconductor channel 616 includes polysilicon. In some embodiments, the memory film 614 is a composite layer including a tunneling layer, a storage layer (also known as a "charge trap layer"), and a blocking layer. The remaining space of the channel hole can be partially or completely filled by a capping layer 618 including a dielectric material (e.g., silicon oxide, etc.) and / or an air gap. The channel structure 612 can have a cylinder shape (e.g., pillar shape). According to some embodiments, the capping layer 618, the semiconductor channel 616, the tunneling layer, the storage layer, and the blocking layer of the memory film 614 are arranged in this order radially from the center towards the outer surface of the pillar. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 614 can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). In some embodiments, the channel structure 612 further includes a channel plug 620 at the upper part of the upper side of the channel structure 612. The channel plug 620 can include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 620 functions as the drain of a NAND memory string.

[0039] As shown in FIG. 6, according to some embodiments, a portion of the semiconductor channel 616 along the sidewall of the channel structure 612 (e.g., in the lower portion of the channel structure 612) is in contact with the polysilicon sublayer 208-1. That is, the memory film 614 is separated at the lower portion of the channel structure 612 that abuts the sublayer 208-1 of the polysilicon layer 208, and according to some embodiments, exposes the semiconductor channel 616 to contact the surrounding polysilicon sublayer 208-1. As a result, the polysilicon sublayer 208-1 surrounding and in contact with the semiconductor channel 616 can act as the "sidewall SEG" of the channel structure 612. In some embodiments, the source contact structure 226 is in contact with the polysilicon layer 208 and is electrically connected to the semiconductor channel 616 through the polysilicon layer 208.

[0040] As shown in FIG. 6, in some embodiments, semiconductor device 200 further includes insulating spacers 622 that extend vertically through alternating conductor layers 210 and dielectric layers 212 of memory stack 206. In some embodiments, insulating spacers 622 extend into polysilicon layer 208 and terminate in polysilicon sublayer 208-1, according to some embodiments. In some embodiments, the lower end of each insulating spacer 622 is nominally coplanar with the upper surface of polysilicon sublayer 208-1. Also, each insulating spacer 622 can extend laterally to separate channel structure 612 into a plurality of blocks. Unlike slit structures in some 3D NAND memory devices, insulating spacers 622 do not, according to some embodiments, contain any contacts therein (i.e., do not function as source contacts). In some embodiments, each insulating spacer 622 includes an opening (e.g., a slit) filled with one or more dielectric materials (including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof). In one example, each insulating spacer 622 can be filled with silicon oxide as insulator core 626 and a high-k dielectric connected to the gate dielectric layer.

[0041] The source contact structure 226 extends vertically from the opposite side (i.e., the back side) of the polysilicon layer 208 with respect to the stop layer 224 through the insulating layer 202 and the stop layer 224 (if any) and can be in contact with the polysilicon layer 208. It should be understood that the depth to which the source contact structure 226 extends into the polysilicon layer 208 can vary in different examples. The source contact structure 226 can electrically connect the source of the NAND memory string of the semiconductor device 200 to the peripheral device through the polysilicon layer 208 from the back side of the memory array substrate (removed), and thus, in this specification, it can also be referred to as "back side source pickup" as well. The source contact structure 226 can include any suitable type of contact. In some embodiments, the source contact structure 226 includes via contacts. In some embodiments, the source contact structure 226 includes laterally extending wall-shaped contacts. The source contact structure 226 can include one or more conductive layers (e.g., a metal layer, e.g., tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al), or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)), etc.).

[0042] Referring back to FIGS. 2A and 2B, the contact structure 216 can extend into the insulating structure 218 and the base structure 204 and can be conductively connected to any peripheral circuitry for the operation of the memory cell. In some embodiments, the contact structure 216 extends through the polysilicon layer 208 and the insulating layer 202. The contact structure 216 can include a first contact portion 216-1 that extends into the insulating structure 218 and a second contact portion 216-2 that extends into the base structure 204 (e.g., the polysilicon layer 208 and the insulating layer 202, and the stop layer 224 if any). The first and second contact portions 216-1 and 216-2 can be in contact with each other at a contact interface and can be conductively connected to each other. Also, the semiconductor device 200 can include a spacer structure 220 that is within the polysilicon layer 208, surrounds the second contact portion 216-2, and insulates the second contact portion 216-2 from the polysilicon layer 208.

[0043] In some embodiments, as shown in Figure 2B, the lateral cross-sectional area of the second contact portion 216-2 is greater than or equal to the lateral cross-sectional area of the first contact portion 216-1, and the first contact portion 216-1 is completely overlapped with the second contact portion 216-2. The lateral cross-sections of the first and second contact portions 216-1 and 216-2 can each have any suitable shape (e.g., an elliptical shape, a square shape, a rectangular shape, and a circular shape, etc.). For example, the lateral cross-sections of the first and second contact portions 216-1 and 216-2 can be nominally circular and square, respectively. The upper surface of the second contact portion 216-2 can be sufficiently flat, for example, at the same level as (in the same plane as) the upper surface of the polysilicon layer 208. The contact interface between the first contact portion 216-1 and the second contact portion 216-2 can be in the same plane as (or at least nominally in the same plane as) the upper surface of the polysilicon layer 208. That is, the lower surface of the first contact portion 216-1 and the upper surface of the second contact portion 216-2 can each be in the same plane as (or at least nominally in the same plane as) the upper surface of the polysilicon layer 208. In some embodiments, the first and second contact portions 216-1 and 216-2 can be made of tungsten, cobalt, copper, or aluminum, and / or silicide, respectively.

[0044] The spacer structure 220 is within the polysilicon layer 208, in contact with the second contact portion 216-2, capable of surrounding the second contact portion 216-2, and configured such that the second contact portion 216-2 (or the contact structure 216) is insulated from the polysilicon layer 208. The lateral dimensions of the spacer structure 220 (e.g., in the x-y plane) can be large enough to insulate the second contact portion 216-2 from the polysilicon layer 208 in all directions. The upper surface of the spacer structure 220 in contact with the insulating structure 218 can be coplanar with the upper surface of the polysilicon layer 208. The lower surface of the spacer structure 220 can be in contact with the insulating layer 202 (or the stop layer 224 if present), such that the second contact portion 216-2 is completely insulated from the polysilicon layer 208. In various embodiments, the lower surface of the spacer structure 220 can be at the same level as or below the lower surface of the polysilicon layer 208. For example, the lower surface of the spacer structure 220 can be within the stop layer 224 or within the insulating layer 202. In some embodiments, the spacer structure 220 includes a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof). It should be understood that if the spacer structure 220 includes the same material as the insulating structure 218 and / or the spacer structure 220, the upper and / or lower surfaces of the spacer structure 220 may not be distinguishable.

[0045] FIG. 3A illustrates a cross-sectional view of another exemplary contact structure in a semiconductor device 300 according to some embodiments. FIG. 3B illustrates a top view of the contact structure in the semiconductor device 300 according to some embodiments. For ease of illustration, FIGS. 3A and 3B are described together, and details of other same structures in both semiconductor devices 200 and 300 are not repeated for ease of explanation.

[0046] As shown in FIG. 3A, the semiconductor device 300 includes a contact structure 316 and a spacer structure 320. The contact structure 316 can include a first contact portion 316-1 and a second contact portion 316-2, which are in contact with each other and are electrically connected to each other. The contact structure 316 can extend through the spacer structure 320 such that the spacer structure 320 insulates the contact structure 316 from the polysilicon layer 208. Unlike the contact structure 216, the contact interface between the first contact portion 316-1 and the second contact portion 316-2 can be below the upper surface of the polysilicon layer 208. For example, the contact interface (e.g., the lower surface of the first contact portion 316-1 and the upper surface of the second contact portion 316-2) can be between the upper surface and the lower surface of the polysilicon layer 208. In some embodiments, the contact interface can be coplanar (or at least nominally coplanar) with the lower surface of the polysilicon layer 208. That is, the first contact portion 316-1 can extend into (e.g., through) the polysilicon layer 208. Accordingly, the second contact portion 316-2 can have a reduced thickness within the spacer structure 320.

[0047] Unlike the spacer structure 220, the spacer structure 320 surrounds at least a portion of the first contact portion 316-1 such that the first contact portion 316-1 is insulated from the polysilicon layer 208. When the contact interface between the first contact portion 316-1 and the second contact portion 316-2 is between the upper surface and the lower surface of the polysilicon layer 208, the spacer structure 320 can also insulate a portion of the second contact portion 316-2 from the polysilicon layer 208. In some embodiments, as shown in FIG. 3B, the lateral cross-sectional area of the second contact portion 316-2 is greater than or equal to the lateral cross-sectional area of the first contact portion 316-1, and the first contact portion 316-1 is completely overlapped with the second contact portion 316-2. The materials and shapes of the first contact portion 316-1, the second contact portion 316-2, and the spacer structure 320 can be the same as or similar to those of the first contact portion 216-1, the second contact portion 216-2, and the spacer structure 220, respectively, and a detailed description will not be repeated here.

[0048] FIGS. 4A to 4D illustrate a manufacturing process for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of a method 700 for forming a semiconductor device according to some embodiments of the present disclosure. The examples of semiconductor devices shown in FIGS. 4A to 4D and FIG. 7 include the semiconductor devices shown in FIGS. 2A and 2B. FIGS. 4A to 4D and FIG. 7 are described together. It should be understood that the operations shown in method 700 are not exhaustive and that other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously or in an order different from that shown in FIG. 7.

[0049] Referring to FIG. 7, method 700 begins at operations 702 and 704, where a trench structure is formed in a base structure and a spacer structure is formed in the trench structure. FIG. 4A illustrates the corresponding structures.

[0050] As shown in FIG. 4A, at the beginning of the fabrication process, a trench structure can be formed in base structure 404. The shape and depth of the trench structure can correspond to those of the subsequently formed spacer structure. Base structure 404 can include a polysilicon layer 408 on a stop layer 424, and stop layer 424 is further on an insulating layer 402. Polysilicon layer 408 can include a sacrificial sublayer, and the sacrificial sublayer is then used to form a polysilicon sublayer in polysilicon layer 408. Detailed descriptions of polysilicon layer 408, stop layer 424, and insulating layer 402 can be referred to the descriptions of polysilicon layer 208, stop layer 224, and insulating layer 202, and will not be repeated here.

[0051] The trench structure can surround an area (e.g., polysilicon layer 408) in the peripheral region of base structure 404 such that the surrounded area (e.g., in polysilicon layer 408) can be insulated from the portion of polysilicon layer 408 outside the trench structure. In some embodiments, the trench structure can extend from the upper surface of polysilicon layer 408 to at least the lower surface of polysilicon layer 408. For example, the lower surface of the trench structure can stop on or in stop layer 424. In some embodiments, the lower surface of polysilicon layer 408 stops at stop layer 424. The thickness / depth of the trench structure can be at least the thickness of polysilicon layer 408 along the z direction. The trench structure can be formed by any suitable patterning process (e.g., dry etching and / or wet etching, etc.) following a photolithography process.

[0052] The base structure 404 can be formed on one side (e.g., the first side) of the substrate. The substrate can be a silicon substrate or a carrier substrate made of any suitable material (e.g., to name a few, semiconductor, glass, sapphire, plastic, etc.). In some embodiments, the insulating layer 402 includes a dielectric material (e.g., silicon oxide, etc.). In some embodiments, the stop layer 424 includes a high-k dielectric material (e.g., aluminum oxide, etc.). In some embodiments, the polysilicon layer 408 includes polysilicon having a uniform doping profile. In some embodiments, the insulating layer 402, the stop layer 424, and the polysilicon layer 408 are sequentially formed on the substrate by any suitable film deposition method (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless deposition, and combinations thereof, etc.). Thereafter, the substrate can be removed or thinned to form various structures (e.g., contact vias, etc.). In some embodiments, the substrate is removed or thinned at an appropriate time during the manufacturing process such that contact vias can be formed from the lower surface of the base structure 404.

[0053] A dielectric stack (which may subsequently form a memory stack) can be formed on a base structure 404 on a substrate. The dielectric stack can include a plurality of alternating sacrificial layers and dielectric layers. In some embodiments, the dielectric stack (having a plurality of pairs of sacrificial layers and dielectric layers) is formed on a polysilicon layer 408. The alternating sacrificial layers and dielectric layers can be alternately deposited on the polysilicon layer 408 to form the dielectric stack. In some embodiments, each dielectric layer includes a layer of silicon oxide and each sacrificial layer includes a layer of silicon nitride. In some embodiments, a pad oxide layer (e.g., a silicon oxide layer (not shown)) is formed between the polysilicon layer 408 and the dielectric stack. An insulating structure 418 (having a suitable dielectric material such as silicon oxide) can be deposited on the dielectric stack and the base structure 404 at an appropriate time during the fabrication process such that the dielectric stack is positioned within the insulating structure 418. The dielectric stack, the insulating structure 418, and the pad oxide layer (if any) can be formed by one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof).

[0054] Before the first contact portion of the contact structure is formed, the trench structure can be formed in the peripheral region of the semiconductor device at any suitable time during the manufacturing process. In some embodiments, the trench structure is formed by patterning a base structure 404 (e.g., a polysilicon layer 408) using a "zero mask", which is used to pattern the base structure 404 before any structure is formed thereon. In some embodiments, the trench structure is formed by patterning a dielectric stack to form a bottom-select-gate cut structure, for example, after one or more pairs of sacrificial layers and dielectric layers are formed on the base structure 404. Thus, the pattern for forming the trench structure can be incorporated into an existing patterning mask, and the etching of the base structure 404 for forming the trench structure can be carried out together with other existing etching operations, reducing the total number of etching operations. In various embodiments, the trench structure can also be formed by a separate patterning / etching process or simultaneously with other suitable structures, depending on the manufacturing process.

[0055] The spacer structure 420 can be formed within the trench structure. A dielectric material (e.g., silicon oxide) can be deposited to fill the trench structure and form the spacer structure 420. The dielectric material can be deposited by any suitable film deposition method (e.g., CVD, PVD, ALD, and combinations thereof, etc.), and can be deposited at any suitable time during the fabrication process, before the first contact portion of the contact structure is formed. In some embodiments, the spacer structure 420 can be formed by the same deposition process that forms the insulating structure 418, after the formation of the dielectric stack. In some embodiments, the spacer structure 420 can be formed by the same deposition process that forms the bottom - select - gate cut structure within the dielectric stack, after one or more pairs of sacrificial layers and dielectric layers are formed on the base structure 404 and before the entire dielectric stack is formed. In various embodiments, the spacer structure 420 can also be formed by a separate deposition process, depending on the fabrication process, or can be filled with a dielectric material simultaneously with other suitable structures.

[0056] Before the formation of the contact structure, other structures (not shown in FIGS. 4A-4D) can be formed within the semiconductor device (e.g., a dielectric stack). In some embodiments, a channel structure is formed that extends vertically through the polysilicon layer 408 and terminates at the stop layer 424 of the dielectric stack. In some embodiments, to form the channel structure, a channel hole (e.g., an opening) is formed that extends vertically through the dielectric stack and the polysilicon layer 408, and a memory film (e.g., a blocking layer, a storage layer, and a tunneling layer) and a semiconductor channel are sequentially formed along the sidewalls of the channel hole. The deposition of the films and layers within the channel hole can include ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a channel plug is formed in contact with the semiconductor channel above the semiconductor channel. In some embodiments, the fabrication process for forming the channel hole includes a wet etching process and / or a dry etching process (e.g., deep ion reactive etching (DRIE), etc.). According to some embodiments, the etching of the channel hole continues until it is stopped by the stop layer 424 due to the etching selectivity between the materials of the stop layer 424 and the polysilicon layer 408.

[0057] To conductively connect the polysilicon layer 408 and the channel structure, a polysilicon sublayer 408-1 (which is in contact with and conductively connected to the semiconductor channel) is formed within the polysilicon layer 408. In some embodiments, the lower portion of the memory film is removed so that the memory film is in a detached state. The polysilicon sublayer 408-1 in contact with the semiconductor channel can be formed by replacing a sacrificial sublayer with a polysilicon sublayer. The formation of the polysilicon sublayer 408-1 can include suitable dry etching and / or wet etching processes, CVD, PVD, ALD, and combinations thereof. Insulating spacers (which divide the memory cell into a plurality of blocks) can also be formed. The formation of the insulating spacers can include suitable dry etching and / or wet etching processes, CVD, PVD, ALD, and combinations thereof. A gate exchange process can be performed to replace the sacrificial layer in the dielectric stack and form a plurality of conductor layers. A memory stack 406 (having a plurality of alternately arranged conductor layers 410 and dielectric layers 412) can be formed on the polysilicon layer 408. The gate exchange process can include suitable isotropic etching processes, CVD, PVD, ALD, and combinations thereof. The channel structure (extending through the memory stack 406) can be in contact with and conductively connected to the polysilicon layer 408 through the semiconductor channel. In some embodiments, the memory stack 406 can be repeatedly patterned to form a stepped structure, which includes a plurality of steps extending laterally (e.g., along the x / y direction). The patterning process of the memory stack 406 can include a repetitive photolithography process and recess etching (e.g., an isotropic etching process).

[0058] Referring back to FIG. 7, method 700 proceeds to operation 706, where a first contact portion is formed on the upper surface of the base structure and surrounded by a spacer structure. FIG. 4B illustrates the corresponding structure.

[0059] As shown in FIG. 4B, the first contact portion 416-1 can be formed in the insulating structure 418 and landed on the upper surface of the base structure 404. The lower surface of the first contact portion 416-1 can be within an enclosed area in the polysilicon layer 408 defined by the spacer structure 420, and in the lateral direction, the first contact portion 416-1 is surrounded by the spacer structure 420. In some embodiments, the lower surface of the first contact portion 416-1 extends below the upper surface of the polysilicon layer 408. In some embodiments, the first contact portion 416-1 is formed by the same process that forms the word line contact 414, and the word line contacts 414 land on each respective step and form a conductive connection with the conductor layer 410 in the step. The first contact portion 416-1 and the word line contact 414 can each include a suitable conductive material (such as tungsten, etc.).

[0060] The formation of the first contact portion 416-1 and the word line contact 414 can include a patterning process followed by a suitable film deposition process. The patterning process can remove a portion of the insulating structure 418 and form openings corresponding to the locations and positions of the first contact portion 416-1 and the word line contact 414. In some embodiments, the opening for the first contact portion 416-1 extends into the insulating structure 418 and exposes the enclosed area in the polysilicon layer 408. In some embodiments, the opening for the word line contact 414 extends into the insulating structure 418 and exposes the conductor layer 410 in the corresponding step. The deposition of the conductive material can include CVD, PVD, ALD, electroplating, electroless plating, and combinations thereof.

[0061] Referring back to FIG. 7, method 700 proceeds to operation 708, where a hole is formed that extends from the lower surface of the base structure to the first contact portion, and the hole is surrounded by a spacer structure. FIG. 4C illustrates the corresponding structure.

[0062] As shown in FIG. 4C, a hole 415 can be formed that extends from the lower surface of the base structure 404 to the first contact portion 416-1. The hole 415 can be surrounded by a spacer structure 420. A portion of the base structure 404 (i.e., a portion of the insulating layer 402, the stop layer 424, and the polysilicon layer 408) can be removed to form the hole 415, and the hole 415 extends from the lower surface of the base structure 404 (e.g., the lower surface of the insulating layer 402) to the first contact portion 416-1. The hole 415 is in contact with the first contact portion 416-1 and can expose the first contact portion 416-1. As shown in FIG. 4C, the portion of the hole 415 in the polysilicon layer 408 can be positioned within the enclosed area defined by the spacer structure 420. The lateral dimension of the hole 415 can be large enough to be in complete contact with the first contact portion 416-1 and can also be small enough not to exceed the enclosed area surrounded by the spacer structure 420. In some embodiments, the hole 415 is isolated from the polysilicon layer 408 outside the spacer structure 420. In some embodiments, the lateral dimension of the hole 415 can be less than or equal to the lateral dimension of the enclosed area.

[0063] In some embodiments, another hole 425 for forming a source contact structure can be formed in the same patterning process for forming the hole 415. The hole 425 can extend from the lower surface of the base structure 404 (e.g., the insulating layer 402) to the polysilicon layer 408. The patterning process can include a suitable etching process (e.g., a dry etching process and / or a wet etching process).

[0064] In various embodiments, the substrate (on which the base structure 404 is formed) is removed before the formation of the holes 415. The substrate can be removed at any suitable time during the fabrication process by a grinding process, CMP, recess etching, or a combination thereof. In some embodiments, the lower surface of the base structure 404 is the lower surface of the insulating layer 402.

[0065] Referring back to FIG. 7, method 700 proceeds to operation 710, where a second contact portion is formed in the holes in contact with the first contact portion. FIG. 4D illustrates the corresponding structure.

[0066] As shown in FIG. 4D, the second contact portion 416-2 can be formed in the holes 415 in contact with the first contact portion 416-1. A conductive material (such as tungsten, etc.) can be deposited to fill the holes 415 and other holes 425. Any suitable film deposition method can be implemented to deposit the conductive material. For example, the deposition method can include CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some embodiments, the source contact structure 426 can be formed by the same deposition process that forms the second contact portion 416-2. A contact structure 416 (having first and second contact portions 416-1 and 416-2 in contact with each other) is formed and can extend through the insulating structure 418 and the base structure 404 (such as the spacer structure 420) to connect to the peripheral circuits of the semiconductor device. On the one hand, the source contact structure 426 can be formed in contact with the polysilicon layer 408 and conductively connected to the polysilicon layer 408 and into the base structure 404. Then, the channel structure can be conductively connected to the source through the polysilicon layer 408 and the source contact structure 426.

[0067] Figures 5A-5D illustrate a fabrication process for forming a semiconductor device according to some embodiments of the present disclosure. FIG. 8 illustrates a flowchart of a method 800 for forming a semiconductor device according to some embodiments of the present disclosure. Examples of the semiconductor devices shown in FIGS. 5A-5D and FIG. 8 include the semiconductor devices shown in FIGS. 3A and 3B. FIGS. 5A-5D and FIG. 8 are described together. It should be understood that the operations shown in method 800 are not exhaustive and that other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously or in an order different from that shown in FIG. 8. For ease of illustration, parts in FIGS. 5A-5D similar to those in FIGS. 4A-4D are shown using the same numbers, and detailed descriptions of these parts are not repeated here.

[0068] Referring to FIG. 8, method 800 begins at operations 802 and 804, where a first hole is formed in a base structure and a well structure is formed in the first hole. FIG. 5A illustrates the corresponding structure.

[0069] As shown in FIG. 5A, at the beginning of the fabrication process, a first hole may be formed in the base structure 404. The shape and depth of the first hole can correspond to those of the spacer structure to be formed later. In some embodiments, the lower surface of the first hole can expose the stop layer 424. In some embodiments, the depth of the first hole can be greater than or equal to the thickness of the polysilicon layer 408 such that the spacer structure to be formed later can insulate the contact structure from the polysilicon layer 408. The first hole can be formed at any suitable time during the fabrication process, either together with other structures or in a separate process. A suitable etching process (e.g., wet etching and / or dry etching) can be implemented as a patterning process to form the first hole. A detailed description of the location and timing for forming the first hole can be referred to that of the trench structure described in FIGS. 4A-4D and will not be repeated here.

[0070] A well structure 519 can be formed in the base structure 404 by filling the first hole with a dielectric material. The lower surface of the well structure 519 can be in contact with the stop layer 424. In some embodiments, the lower surface of the well structure 519 can be on or below the upper surface of the stop layer 424. The upper surface of the well structure 519 can be defined as a surface that is coplanar with the upper surface of the polysilicon layer 408 for ease of illustration. In some embodiments, the dielectric material includes silicon oxide and can be formed by a suitable film deposition method (e.g., CVD, PVD, ALD, or a combination thereof, etc.). A detailed description of the location and timing for forming the well structure 519 can be referred to that of the spacer structure 420 described in FIGS. 4A-4D and will not be repeated here.

[0071] Referring back to FIG. 8, method 800 proceeds to operation 806, where a first contact portion is formed within the well structure. FIG. 5B illustrates the corresponding structure.

[0072] As shown in FIG. 5B, a first contact portion 516-1 can be formed within the well structure 519. The first contact portion 516-1 can be formed within the insulating structure 418 and land on the lower surface of the well structure 519. The first contact portion 516-1 can be surrounded by the well structure 519. In some embodiments, the first contact portion 516-1 is formed by the same process that forms the word line contact 414, and the word line contacts 414 land on top of each stage and form a conductive connection with the conductor layer 410 within the stage. The first contact portion 516-1 and the word line contact 414 can each include a suitable conductive material (e.g., tungsten, etc.). In some embodiments, the lower surface of the first contact portion 516-1 does not reach the lower surface of the well structure 519 but is below the upper surface of the polysilicon layer 408, such that etching from the lower surface of the base structure 404 can be reduced when the second contact portion is formed. That is, the second hole for forming the second contact portion need not reach from the lower surface of the base structure 404 (i.e., the insulating layer 402) to the upper surface of the polysilicon layer 408.

[0073] The formation of the first contact portion 516-1 and the word line contact 414 can include an appropriate film deposition process followed by a patterning process. The patterning process can remove a portion of the insulating structure 418 at a desired depth and form openings corresponding to the locations and positions of the first contact portion 516-1 and the word line contact 414. In some embodiments, the opening for the first contact portion 516-1 extends into the insulating structure 418, exposing an enclosed area within the polysilicon layer 408. In some embodiments, the opening for the word line contact 414 extends into the insulating structure 418, exposing the conductor layer 410 in the corresponding stage. Deposition of the conductive material can include CVD, PVD, ALD, electroplating, electroless plating, and combinations thereof.

[0074] Referring back to FIG. 8, method 800 proceeds to operation 808, where a second hole is formed that extends from the lower surface of the base structure to the first contact portion. A spacer structure is formed. FIG. 5C illustrates the corresponding structure.

[0075] As shown in FIG. 5C, a second hole 515 may be formed that extends from the lower surface of the base structure 404 to the first contact portion 516-1. A spacer structure 520 may be formed from the remaining portion of the well structure 519. The second hole 515 may be surrounded by the spacer structure 520 in the polysilicon layer 408. A portion of the base structure 404 (i.e., a portion of the insulating layer 402, the stop layer 424, and the polysilicon layer 408 (if any)) may be removed to form the second hole 515, and the second hole 515 extends from the lower surface of the base structure 404 (e.g., the lower surface of the insulating layer 402) to the first contact portion 516-1. The second hole 515 is in contact with the first contact portion 516-1 and can expose the first contact portion 516-1. In various embodiments, the upper surface of the second hole 515 is in the same plane as or above the upper surface of the stop layer 424, and sufficient contact between the first contact portion 516-1 and the second hole 515 (or the second contact portion formed later) can be ensured. As shown in FIG. 5C, the lateral dimension of the hole 415 can be large enough to be in complete contact with the first contact portion 516-1, and can also be small enough not to exceed the spacer structure 420. In some embodiments, the second hole 515 is isolated from the polysilicon layer 408 outside the spacer structure 520. In some embodiments, the lateral dimension of the second hole 515 can be less than or equal to the lateral dimension of the well structure 519 (or the spacer structure 520). In some embodiments, another hole 425 for forming the source contact structure 426 can be formed in the same patterning process for forming the hole 415. The patterning process can include a suitable etching process (e.g., a dry etching process and / or a wet etching process).

[0076] Referring back to FIG. 8, method 800 proceeds to operation 810, where a second contact portion is formed in the second hole in contact with the first contact portion. FIG. 5D illustrates the corresponding structure.

[0077] As shown in FIG. 5D, a second contact portion 516-2 can be formed in the second hole 515 in contact with the first contact portion 516-1. A conductive material (e.g., tungsten, etc.) can be deposited to fill the second hole 515 and other holes 425. Any suitable film deposition method can be implemented to deposit the conductive material. For example, the deposition method can include CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. In some embodiments, the source contact structure 426 can be formed by the same deposition process that forms the second contact portion 516-2. A contact structure 516 (having first and second contact portions 516-1 and 516-2 in contact with each other) is formed and can extend through the insulating structure 418 and the base structure 404 (e.g., spacer structure 520) to connect to the peripheral circuit of the semiconductor device. The lower surface of the first conductor portion 516-1 can be below the upper surface of the spacer structure 520. The upper surface of the second conductor portion 516-2 can be a flat / same-level surface.

[0078] Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an insulating layer, a conductive layer on the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. The upper surface of the second contact portion is in the same plane as the upper surface of the conductive layer.

[0079] In some embodiments, the conductive layer includes polysilicon.

[0080] In some embodiments, the lateral cross-sectional area of the second contact portion is greater than or equal to that of the first contact portion.

[0081] In some embodiments, the semiconductor device further includes a memory stack including conductive layers and dielectric layers arranged alternately on the conductive layer and away from the contact structure. In some embodiments, the semiconductor device is also within the memory stack and includes a channel structure entering the conductive layer. The channel structure includes a semiconductor channel. The lower portion of the semiconductor channel is in contact with the conductive layer. The second contact structure extends vertically in the insulating layer and is in contact with the conductive layer.

[0082] In some embodiments, the channel structure further includes a memory layer, the memory layer being in contact with and surrounding the semiconductor channel. In some embodiments, the lower portion of the memory layer is separated to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

[0083] In some embodiments, the spacer structure includes a dielectric material.

[0084] In some embodiments, the first contact structure electrically connects the peripheral circuit and the contact pad on the opposite side of the insulating layer and the conductive layer.

[0085] In some embodiments, the first contact structure is electrically connected to the second contact structure.

[0086] Embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure within the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure within the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. The contact structure also includes that the lower surface of the first contact portion contacts the upper surface of the second contact portion at a contact interface where the lower surface of the first contact portion is below the upper surface of the conductive layer.

[0087] In some embodiments, the contact interface is coplanar with the lower surface of the conductive layer.

[0088] In some embodiments, the conductive layer includes polysilicon.

[0089] In some embodiments, the lateral cross-sectional area of the second contact portion is greater than or equal to the lateral cross-sectional area of the first contact portion.

[0090] In some embodiments, the semiconductor device further includes a memory stack including alternating conductive layers and dielectric layers over the conductive layer and spaced apart from the contact structure, and a channel structure within the memory stack and extending into the conductive layer. The channel structure includes a semiconductor channel. A lower portion of the semiconductor channel is in contact with the conductive layer. A second contact structure extends vertically within the insulating layer and is in contact with the conductive layer.

[0091] In some embodiments, the channel structure further includes a memory layer in contact with and surrounding the semiconductor channel. In some embodiments, a lower portion of the memory layer is separated to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer.

[0092] In some embodiments, the spacer structure includes a dielectric material.

[0093] In some embodiments, the first contact structure electrically connects the peripheral circuit and the contact pad on the opposite side of the insulating layer and the conductive layer.

[0094] In some embodiments, the first contact structure is electrically connected to the second contact structure.

[0095] Embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes forming a spacer structure from a first surface of a base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact portion extends from a second surface of the base structure into the base structure.

[0096] In some embodiments, the step of forming the spacer structure includes removing a portion of the base structure on the first surface and forming an opening structure extending from the first surface into the base structure. In some embodiments, the step of forming the spacer structure includes filling the opening structure with an insulating material.

[0097] In some embodiments, the lower surface of the opening structure is between the first surface and the second surface of the base structure.

[0098] In some embodiments, the base structure includes an insulating layer and a conductive layer on the insulating layer. In some embodiments, the step of forming the opening structure includes forming a trench structure in the conductive layer and forming a first portion of the conductive layer surrounded by the trench structure and a second portion of the conductive layer outside the trench structure.

[0099] In some embodiments, the first portion of the conductive layer is isolated from the second portion of the conductive layer by a trench structure, and the lower surface of the trench structure is in contact with an insulating layer.

[0100] In some embodiments, the step of forming a first contact portion surrounded by a spacer structure includes forming a first contact portion that is in contact with the first portion of the conductive layer and is surrounded by an insulating material.

[0101] In some embodiments, the step of forming a second contact portion includes forming a hole that extends from the second surface of the base structure into the base structure and is in contact with the first contact portion. The hole is insulated from the second portion of the conductive layer by a spacer structure. In some embodiments, the step of forming a second contact portion includes filling the hole with a conductive material.

[0102] In some embodiments, the base structure includes an insulating layer and a conductive layer on the insulating layer. In some embodiments, the step of forming an opening structure includes forming a hole in the conductive layer, and the lower surface of the hole is in contact with the insulating layer.

[0103] In some embodiments, the step of forming a first contact portion surrounded by a spacer structure includes forming a first contact portion that extends into an insulating material. The lower surface of the first contact portion is below the upper surface of the spacer structure.

[0104] In some embodiments, the lower surface of the first contact portion is in contact with the insulating layer.

[0105] In some embodiments, the step of forming the second contact portion includes forming another hole that extends from the second surface of the base structure into the base structure and is in contact with the first contact portion. The hole is insulated from the conductive layer by an insulating material. In some embodiments, the step of forming the second contact portion includes filling the hole with a conductive material.

[0106] In some embodiments, the base structure includes an insulating layer, an etching stop layer on the insulating layer, and a conductive layer on the etching stop layer. In some embodiments, the step of forming the opening structure includes removing a portion of the conductive layer until the lower surface of the opening structure stops on the etching stop layer.

[0107] In some embodiments, the method further includes forming a memory stack on the base structure away from the contact structure. The insulating material is deposited before the formation of the memory stack.

[0108] In some embodiments, the method further includes forming a memory stack on the base structure away from the contact structure. The insulating material is deposited after the formation of the memory stack.

[0109] In some embodiments, the method further includes forming a channel structure including a semiconductor channel in the memory stack. The lower portion of the semiconductor channel is in contact with the conductive layer. In some embodiments, the method further includes forming a contact structure that extends from the second surface of the base structure into the base structure and is in contact with the conductive layer. The contact structure is formed by the same process as forming the second contact portion.

[0110] Accordingly, the foregoing description of certain embodiments will disclose the general nature of the present disclosure such that others can, by applying knowledge within the scope of those skilled in the art, readily modify and / or adapt such specific embodiments for various applications without departing from the general concepts of the present disclosure and without undue experimentation. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein. The phraseology or terminology herein is for the purpose of description and not of limitation, and it is to be understood that the terminology or phraseology herein is to be so construed as to be understandable by those of ordinary skill in the art in light of the teachings and guidance.

[0111] Embodiments of the present disclosure have been described above with the aid of functional building blocks that illustrate the implementation of specific functions and their relationships. The boundaries of these functional building blocks are arbitrarily defined herein for the sake of convenience of description. Alternative boundaries may be defined as long as the specific functions and their relationships are appropriately implemented.

[0112] The summary and abstract sections may describe one or more (but not all) exemplary embodiments contemplated by the inventors of the present disclosure and are, therefore, not intended to limit the present disclosure and the appended claims in any way.

[0113] The breadth and scope of the present disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the following claims and their equivalents.

Description of Reference Numerals

[0114] 100 Semiconductor device 102 Insulating layer 104 Base structure 106 Memory stack 108 Polysilicon layer 110 Conductor layer 112 Dielectric layer 114 Word line contact 116 Peripheral contact 116-1 First contact portion 116-2 Second contact portion 118 Insulating structure 120 Spacer 126 Source contact 200 Semiconductor device 202 Insulating layer 204 Base structure 206 Memory stack 208 Polysilicon layer 208-1 Polysilicon sublayer 210 Conductor layer 212 Dielectric layer 214 Word line contact 216 Contact structure 216-1 First contact portion 216-2 Second contact portion 218 Insulating structure 220 Spacer structure 224 Stop layer 226 Source contact structure 300 Semiconductor device 316 Contact structure 316-1 First contact portion 316-2 Second contact portion 320 Spacer structure 402 Insulating layer 404 Base structure 406 Memory stack 408 Polysilicon layer 408-1 Polysilicon sublayer 410 Conductor layer 412 Dielectric layer 414 Word line contact 415 Hole portion 416 Contact structure 416-1 First contact portion 416-2 Second contact portion 418 Insulating structure 420 Spacer structure 424 Stop layer 425 Another hole portion 426 Source contact structure 515 Second hole portion 516-1 First contact portion 516-2 Second contact portion 519 Well structure 520 Spacer structure 612 Channel structure 614 Memory film 616 Semiconductor channel 618 Capping layer 620 Channel plug 622 Insulating spacer 626 Insulator core

Claims

1. An insulating layer, a conductive layer on the insulating layer, an insulating structure on the conductive layer, a spacer structure within the conductive layer and in contact with the insulating layer, a first contact structure within the spacer structure and extending vertically through the insulating layer, the conductive layer, and the insulating structure, comprising: the first contact structure includes a first contact portion and a second contact portion in contact with each other, an upper surface of the second contact portion is coplanar with an upper surface of the conductive layer, the second contact portion penetrates the insulating layer, the conductive layer includes polysilicon, a semiconductor device.

2. The semiconductor device according to claim 1, wherein a lateral cross-sectional area of the second contact portion is greater than or equal to a lateral cross-sectional area of the first contact portion.

3. A memory stack including alternating conductive layers and dielectric layers on the conductive layer and spaced apart from the contact structure, a channel structure within the memory stack and entering the conductive layer, the channel structure including a semiconductor channel, a lower portion of the semiconductor channel being in contact with the conductive layer, a second contact structure extending vertically within the insulating layer and in contact with the conductive layer, further comprising the semiconductor device according to claim 1.

4. The channel structure further includes a memory layer, the memory layer being in contact with and surrounding the semiconductor channel, a lower portion of the memory layer is separated to expose the semiconductor channel such that the semiconductor channel is in contact with the conductive layer, the semiconductor device according to claim 3.

5. The semiconductor device according to claim 1, wherein the spacer structure includes a dielectric material.

6. The semiconductor device according to claim 1, wherein the first contact structure electrically connects a peripheral circuit and a contact pad on an opposite side of the insulating layer and the conductive layer.

7. The semiconductor device according to claim 3, wherein the first contact structure is electrically connected to the second contact structure.

8. An insulating layer, a conductive layer on the insulating layer, an insulating structure on the conductive layer, a spacer structure within the conductive layer and in contact with the insulating layer, Inside the spacer structure, a first contact structure extending vertically through the insulating layer, the conductive layer, and the insulating structure including The first contact structure includes a first contact portion and a second contact portion that are in contact with each other. The lower surface of the first contact portion is in contact with the upper surface of the second contact portion at a contact interface that is below the upper surface of the conductive layer. The second contact portion penetrates the insulating layer. The conductive layer includes polysilicon, a semiconductor device.

9. The semiconductor device according to claim 8, wherein the contact interface is on the same plane as the lower surface of the conductive layer.

10. The semiconductor device according to claim 8, wherein the conductive layer includes polysilicon.

11. The semiconductor device according to claim 8, wherein the lateral cross-sectional area of the second contact portion is equal to or greater than the lateral cross-sectional area of the first contact portion.

12. On the conductive layer and away from the contact structure, a memory stack including alternating conductive layers and dielectric layers, Inside the memory stack, a channel structure entering the conductive layer, including a semiconductor channel, wherein a lower portion of the semiconductor channel is in contact with the conductive layer, the channel structure, A second contact structure extending vertically in the insulating layer and in contact with the conductive layer The semiconductor device according to claim 8, further comprising.

13. The channel structure further includes a memory layer, the memory layer is in contact with the semiconductor channel and surrounds the semiconductor channel, The lower portion of the memory layer is separated so as to expose the semiconductor channel, and the semiconductor channel is in a state of being in contact with the conductive layer. The semiconductor device according to claim 12.

14. A method for forming a semiconductor device, comprising: Providing a base structure including an insulating layer and a conductive layer; Forming a spacer structure from a first surface of the base structure into the base structure; Forming an insulating structure on the base structure; Forming a first contact that extends vertically through the insulating layer, the conductive layer, and the insulating structure and is surrounded by the spacer structure, the step including forming a first contact portion and forming a second contact portion; comprising; the second contact portion extends from a second surface of the base structure into the base structure; the conductive layer includes polysilicon, a method.

15. The step of forming the spacer structure includes: removing a portion of the base structure on the first surface to form an opening structure that extends from the first surface into the base structure; filling the opening structure with an insulating material; The method according to claim 14, comprising.

16. The method according to claim 15, wherein a lower surface of the opening structure is between the first surface and the second surface of the base structure.

17. The step of forming the second contact portion includes: forming a hole that extends from the second surface of the base structure into the base structure and is in contact with the first contact portion, the hole being insulated from the second portion of the conductive layer by the spacer structure; filling the hole with a conductive material; The method according to claim 14, comprising.

18. The step of forming the second contact portion includes: forming another hole that extends from the second surface of the base structure into the base structure and is in contact with the first contact portion, the hole being insulated from the conductive layer by the insulating material; filling the hole with a conductive material; The method according to claim 15, comprising.

19. The base structure includes an etching stop layer between the insulating layer and the conductive layer; The step of forming the opening structure includes removing a portion of the conductive layer until a lower surface of the opening structure stops on the etching stop layer. The method according to claim 15.

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