Semiconductor device

Abstract

To provide a transistor having good electrical characteristics and high reliability; and provide a display device using the transistor.SOLUTION: A bottom-gate transistor using an oxide semiconductor in a channel region comprises an active layer using an oxide semiconductor layer dehydrated or dehydrogenated by a heat treatment, in which the active layer is formed by a first region in a fine-crystallized surface layer part and a second region in the other part. With use of the oxide semiconductor layer having such composition, a change to an n type and generation of a parasitic channel which are caused by re-entry of moisture from the surface layer part or oxygen desorption can be inhibited, and contact resistance between a source electrode and a drain electrode can be reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a transistor using an oxide semiconductor and a display device using the transistor.

Background Art

[0002] In recent years, a technique for forming a transistor using a semiconductor thin film (having a thickness of several nm or more and several hundred nm or less) formed on a substrate having an insulating surface has attracted attention. Transistors are widely applied to electronic devices such as ICs and electro-optical devices, and in particular, development has been urgently required as a switching element for image display devices. Metal oxides exist in various forms and are used in various applications. Indium oxide is a well-known material and is used as a light-transmissive electrode material required for liquid crystal displays and the like. Among metal oxides, some exhibit semiconductor characteristics. Examples of metal oxides exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Transistors using such metal oxides exhibiting semiconductor characteristics in the channel formation region are already known (Patent Document 1 and Patent Document 2).

[0003]

[0004]

[0005]

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] In a display device or the like, a pixel portion (also referred to as a pixel circuit) and a drive circuit portion are formed on the same substrate. In this case, the transistor used in the pixel portion is required to have excellent switching characteristics, for example, a large on-off ratio. The transistor used in the drive circuit is required to operate at high speed.

[0007] In particular, as the pixel density of the display device is higher, the writing time of the display image becomes shorter. Therefore, the transistor used in the drive circuit preferably operates at high speed.

[0008] One aspect of the invention disclosed in this specification relates to a transistor and a display device that solve the above problems.

MEANS FOR SOLVING THE PROBLEMS

MEANS FOR SOLVING THE PROBLEMS

[0009] One aspect of the invention disclosed in this specification is that in an oxide semiconductor layer forming a channel region, its surface layer portion has a crystal region composed of a microcrystalline layer, and the other portions are amorphous, an amorphous mixture of amorphous and microcrystalline with microcrystals scattered in the region, or the whole is a group of microcrystals formed transistor. Further, a display device in which a drive circuit portion and a pixel portion including the transistor are formed on the same substrate.

[0010] One aspect of the invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer and an oxide semiconductor layer on the gate insulating layer, and a source electrode layer and a drain electrode layer overlapping with a part of the oxide semiconductor layer on the gate insulating layer and an oxide insulating layer in contact with the oxide semiconductor layer. , the oxide semiconductor layer is formed of a first region in the surface layer portion and a second region in other portions. It is a transistor characterized by this.

[0011] Note that the ordinal numbers attached as first and second are used for convenience and do not indicate the process order or the stacking order. Also, it does not indicate a unique name as a matter for specifying the invention in this specification. It does not indicate a unique name as a matter for specifying the invention in this specification.

[0012] Another aspect of the invention disclosed in this specification is a transistor having a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, an oxide semiconductor layer overlapping a part of the source electrode layer and the drain electrode layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed of a first region in the surface layer portion and a second region in other portions. It is a transistor characterized by this. The first region of the oxide semiconductor layer is formed of microcrystals with a c-axis orientation perpendicular to the film surface. The second region of the oxide semiconductor layer is an amorphous, a mixture of amorphous and microcrystals with microcrystals scattered in the amorphous region, or is entirely formed of microcrystals.

[0013] The first region of the above oxide semiconductor layer is formed of microcrystals with a c-axis orientation perpendicular to the film surface.

[0014] The second region of the oxide semiconductor layer is an amorphous, a mixture of amorphous and microcrystals with microcrystals scattered in the amorphous region, or is entirely formed of microcrystals.

[0015] The oxide semiconductor layer is one that has been subjected to a high-temperature short-time dehydration or dehydrogenation treatment by an RTA method or the like. By this heating process, the surface layer portion of the oxide semiconductor layer comes to have a crystalline region composed of microcrystals, and the other portions are an amorphous, a mixture of amorphous and microcrystals with microcrystals scattered in the amorphous region, or entirely become a group of microcrystals. The surface layer portion of the oxide semiconductor layer comes to have a crystalline region composed of microcrystals, and the other portions are an amorphous, a mixture of amorphous and microcrystals with microcrystals scattered in the amorphous region, or entirely become a group of microcrystals.

[0016] ​​​​​​By using an oxide semiconductor layer having such a structure, re-invasion of moisture from the surface layer portion and deterioration of electrical characteristics due to n-type formation caused by desorption of oxygen can be prevented. Further, the surface layer portion of the oxide semiconductor layer is on the back channel side and has a crystal region composed of microcrystals, thereby suppressing the generation of parasitic channels. Further, in the channel etch type structure, having a crystal region can reduce the contact resistance between the surface layer portion with improved conductivity and the source electrode and the drain electrode. Also, by using the transistor which is one aspect of the present invention, a drive circuit portion and a pixel portion are formed on the same substrate, and a display device can be manufactured using a liquid crystal element, a light emitting element, an electrophoretic element, or the like. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, an oxide semiconductor layer overlapping a part of the source electrode layer and the drain electrode layer on the gate insulating layer, and an oxide in contact with the oxide semiconductor layer. Also, by using the transistor which is one aspect of the present invention, a drive circuit portion and a pixel portion are formed on the same substrate, and a display device can be manufactured using a liquid crystal element, a light emitting element, an electrophoretic element, or the like. By using an oxide semiconductor layer having such a structure, re-invasion of moisture from the surface layer portion and deterioration of electrical characteristics due to n-type formation caused by desorption of oxygen can be prevented. Further, the surface layer portion of the oxide semiconductor layer is on the back channel side and has a crystal region composed of microcrystals, thereby suppressing the generation of parasitic channels. Further, in the channel etch type structure, having a crystal region can reduce the contact resistance between the surface layer portion with improved conductivity and the source electrode and the drain electrode.

[0017] Also, by using the transistor which is one aspect of the present invention, a drive circuit portion and a pixel portion are formed on the same substrate, and a display device can be manufactured using a liquid crystal element, a light emitting element, an electrophoretic element, or the like. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Also, by using the transistor which is one aspect of the present invention, a drive circuit portion and a pixel portion are formed on the same substrate, and a display device can be manufactured using a liquid crystal element, a light emitting element, an electrophoretic element, or the like.

[0018] Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this.

[0019] Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. Further, another aspect of the present invention disclosed in this specification has a pixel portion and a drive circuit portion having a transistor on the same substrate. The transistor has a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer overlapping a part of the oxide semiconductor layer on the gate insulating layer, and an oxide insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer is formed in a first region of the surface layer portion and a second region of the other portion, and is a display device characterized by this. It has an oxide insulating layer, and the oxide semiconductor layer has a first region in the surface layer portion and a second region formed in the other portion, and is a display device characterized by this.

[0020] The first region of the oxide semiconductor layer is formed of microcrystals with a c-axis orientation perpendicular to the film surface and the second region is amorphous, a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region or is entirely formed of microcrystals.

Advantages of the Invention

[0021] In a transistor using an oxide semiconductor layer, by configuring the surface layer portion of the oxide semiconductor layer to have a crystalline region and the other portion to be amorphous, a mixture of amorphous and microcrystals, or entirely microcrystalline, a transistor and a display device with good electrical characteristics and high reliability can be manufactured.

Brief Description of the Drawings

[0022]

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Mode for Carrying Out the Invention

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same part or parts having the same function, and the repeated description thereof will be omitted.

[0024] (Embodiment 1) In this embodiment, the structure of the transistor will be described with reference to FIG. 1.

[0025] FIG. 1(A) is a cross-sectional view of a channel etch type transistor, and its plan view is shown in FIG. 4(A ). FIG. 1(A) is a cross-sectional view taken along line A1-A2 in FIG. 4(A).

[0026] The transistor shown in FIG. 1 includes a gate electrode layer 101, a gate insulating layer 102, on a substrate 100, An oxide semiconductor layer 103 having a crystal region 106 in a surface layer portion, a source electrode layer 105a, and a drain electrode layer 105b are included. Further, an oxide insulating layer 107 is provided on the oxide semiconductor layer 10 3 having a crystal region 106 in the surface layer portion, the source electrode layer 105a, and the drain electrode layer 105b. are provided.

[0027] In FIG. 1(A), as a normal channel etch type transistor, a structure in which a part of the oxide semiconductor layer is etched between the source electrode layer 10 5a and the drain electrode layer 105b is shown. However, as shown in FIG. 1(B), a structure may be adopted in which the oxide semiconductor layer is not etched and the crystal region in the surface layer portion remains. region remains. is left.

[0028] The gate electrode layer 101 can be formed as a single layer or a laminate using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components. When a low-resistance metal material such as aluminum or copper is used for the electrode layer it is preferably used in combination with a high melting point metal material due to problems of heat resistance and corrosion resistance. As the high melting point metal materials, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used. For example, when using a low-resistance metal material such as aluminum or copper for the electrode layer it is advisable to use it in combination with a high melting point metal material due to heat resistance and corrosion problems. As the high melting point metal materials, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used. can be used.

[0029] Further, for the purpose of improving the aperture ratio of the pixel portion, a transparent oxide conductive layer such as indium oxide, an indium oxide tin oxide alloy, an indium oxide zinc oxide alloy, zinc oxide, zinc oxide aluminum nium, aluminum zinc oxynitride, or gallium zinc oxide can be used for the gate electrode layer 101. oxide layer, zinc oxide aluminum nitride, or gallium zinc oxide can also be used. layer can also be used.

[0030] For the gate insulating layer 102, a single-layer film or a laminated film such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, tantalum oxide, etc. can be used. These can be formed by methods such as CVD method or sputtering method.

[0031] Also, for the oxide semiconductor film, a thin film represented by InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, there are Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Among the oxide semiconductor films with the structure represented by InMO3(ZnO) m (m>0), the oxide semiconductor with a structure containing Ga as M is called an In-Ga-Zn-O-based oxide semiconductor, and its thin film is also called an In-Ga-Zn-O-based film.

[0032] The oxide semiconductor layer 103 is formed using the sputtering method. The film thickness is 10 nm or more and 300 nm or less, preferably 20 nm or more and 100 nm or less. However, when the structure is such that a part of the oxide semiconductor layer 103 is etched as shown in Fig. 1(A), at the completion of the device, it will have a region thinner than the above film thickness.

[0033] The oxide semiconductor layer 103 is used after being subjected to a high-temperature short-time dehydration or dehydrogenation treatment by an RTA method or the like. The dehydration or dehydrogenation treatment is performed using a high-temperature gas (an inert gas such as nitrogen or a rare gas) or light at 500°C or more and 750°C or less (or a temperature below the strain point of the glass substrate ) for about 1 minute or more and 10 minutes or less, preferably about 3 minutes or more and 6 minutes or less at 650°C. ) for about 1 minute or more and 10 minutes or less, preferably about 3 minutes or more and 6 minutes or less at 650°C. It can be carried out by TA (Rapid Thermal Anneal) treatment. RTA method By using this method, dehydration or dehydrogenation can be performed in a short time, so that it can be processed even at a temperature exceeding the strain point of the glass substrate.

[0034] The oxide semiconductor layer 103 is an amorphous layer having many unbonded hands at the stage of film formation. However, by performing a heating process as the dehydration or dehydrogenation treatment, unbonded hands in the vicinity can be bonded to each other to form an ordered amorphous structure. Further, as the ordering develops, it becomes a mixture of amorphous and microcrystals with microcrystals scattered in the amorphous region, or the whole is formed of a microcrystal group. Here, the particle size of the microcrystals is a so-called nanocrystal of 1 nm or more and 20 nm or less, and is generally smaller than the size of microcrystal grains called microcrystals.

[0035] In addition, in the surface layer portion of the oxide semiconductor layer 103 which is the crystal region 106, it is preferable that a microcrystalline layer with a c-axis orientation is formed in the direction perpendicular to the layer surface. In this case, the crystal has a major axis in the c-axis direction, and the minor axis direction is 1 nm or more and 20 nm or less.

[0036] Since the surface layer portion of the oxide semiconductor layer having such a configuration has a dense crystal region composed of microcrystals, it is possible to prevent deterioration of electrical characteristics due to re-invasion of moisture from the surface layer portion or n-type formation due to desorption of oxygen. Further, the surface layer portion of the oxide semiconductor layer is on the back channel side, and prevention of n-type formation is also effective in suppressing parasitic channels. In addition, by having a crystal region, the contact resistance between the surface layer portion with improved conductivity and the source electrode layer 105a or the drain electrode layer 105b can be reduced.

[0037] Here, the In-Ga-Zn-O film varies in the crystal structure that is easy to grow depending on the oxide semiconductor film-forming target used. For example, when using an oxide semiconductor film-forming target containing In, Ga, and Zn with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 to form an In-Ga-Zn-O film and crystallize it through a heating process, a hexagonal layered compound-type crystal structure is likely to form, in which one or two oxide layers containing Ga and Zn are mixed between the In oxide layers. Also, when forming a film using a target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:2 and crystallizing it through a heating process, the oxide layer containing Ga and Zn sandwiched between the In oxide layers is likely to be two layers. The stable crystal structure is the one with two oxide layers containing Ga and Zn in the latter case, and crystal growth is also likely to occur. When forming a film using a target with a molar ratio of In2O3:Ga 2O3:ZnO = 1:1:2 and crystallizing it through a heating process, crystals connecting from the surface layer to the gate insulating film interface may be formed. Note that the molar ratio may be equivalently referred to as the atomic ratio. As shown in Fig. 10(A), depending on the order of the process, a crystal region may not be formed on the side surface portion of the oxide semiconductor layer 103, and the crystal region 106 is formed only in the upper layer portion excluding the side surface portion. However, the area ratio of the side surface portion is small, and the above-described effects are maintained even in this case. The source electrode layer 105a and the drain electrode layer 105b have a three-layer structure composed of the first conductive layers 112a, 112b,

[0038] the second conductive layers 113a, 113b, and the third conductive layers 114a, 114b. As these materials, the same materials as those of the gate electrode layer 101 described above are used. For this reason, even when the side surface portion of the oxide semiconductor layer 103 is not a crystal region, the above-described effects are maintained.

[0039] The source electrode layer 105a and the drain electrode layer 105b have a three-layer structure composed of the first conductive layers 112a, 112b, the second conductive layers 113a, 113b, and the third conductive layers 114a, 114b. As these materials, the same materials as those of the gate electrode layer 101 described above are used. It is possible.

[0040] Also, by using the aforementioned oxide conductive layer having translucency as the source electrode layer 1 05a and the drain electrode layer 105b, the translucency of the pixel portion can be improved and the aperture ratio can also be increased.

[0041] Also, by forming the aforementioned oxide conductive layer between each of the aforementioned metal film and the oxide semiconductor layer that become the source electrode layer 105a and the drain electrode layer 105b, the contact resistance can be reduced. It is also possible.

[0042] On the oxide semiconductor layer 103, the source electrode layer 105a, and the drain electrode layer 105b, there is an oxide insulating layer 107 that functions as a channel protection layer. For the oxide insulating layer, an inorganic insulating film using sputtering is used, typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film or an aluminum oxynitride film, etc. is used.

[0043] Also, the constituent materials of each part are the same, and a bottom contact structure transistor as shown in Fig. 10(B) can also be formed.

[0044] The transistor shown in Fig. 10(B) has a gate electrode layer 101, a gate insulating layer 102, a source electrode layer 105a, a drain electrode layer 105b, and an oxide semiconductor layer 103 including a crystal region 106 in the surface layer portion on a substrate 100. Also, an oxide insulating layer 107 is provided on the gate insulating layer 102, the source electrode layer 105a and the drain electrode layer 105b, and the oxide semiconductor layer 103.

[0045] Also in this structure, the oxide semiconductor layer 103 is amorphous, with microcrystals scattered in the amorphous region. ​​​​It is a mixture of amorphous and microcrystalline, or entirely composed of a microcrystalline group, and only its surface layer has a crystal region 106 composed of a microcrystalline layer. By using such an oxide semiconductor layer it is possible to prevent deterioration of electrical characteristics due to n-type formation caused by re-invasion of moisture from the surface layer and desorption of oxygen, similar to the channel etch type. Also, the surface layer of the oxide semiconductor layer is the back channel side, and having a crystal region composed of a microcrystalline layer can suppress the generation of parasitic channels.

[0046] By adopting the above configuration, a highly reliable transistor with improved electrical characteristics can be provided.

[0047] In this embodiment, an example of a channel etch type transistor is shown, but a channel protection type transistor can also be used. Also, a bottom contact type transistor having an oxide semiconductor layer overlapping on the source electrode layer and the drain electrode layer can be used.

[0048] Note that the configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used.

[0049] (Embodiment 2) In this embodiment, taking the manufacturing process of a display device including the channel etch type transistor shown in Embodiment 1 as an example, it will be described with reference to FIGS. 2 to 9. FIGS. 2 and 3 are cross-sectional views, FIGS. 4 to 7 are plan views, and the lines A1 - A2 and B1 - B2 in FIGS. 4 to 7 correspond to the cross-sectional views A1 - A2 and B1 - B2 in FIGS. 2 and 3.

[0050] First, prepare a substrate 100. The substrate 100 may be an alkali-free glass substrate, an aluminoborosilicate glass substrate, or an aluminosilicate glass substrate, etc., which is made by the fusion method or the float method. In addition to these, a ceramic substrate, or a plastic substrate having heat resistance sufficient to withstand the processing temperature of this manufacturing process can be used. Further, a substrate having an insulating film provided on the surface of any metal substrate such as a stainless steel alloy may be applied. Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, an insulating film may be formed as an underlayer film on the substrate 100. As the underlayer film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used. These can be formed by the CVD method, the sputtering method, or the like. When a substrate containing mobile ions such as a glass substrate is used as the substrate 100, by using a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film as the underlayer film, it is possible to prevent mobile ions from entering the semiconductor layer. Next, a conductive film for forming a gate wiring including a gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire surface of the substrate 100 by the sputtering method or the vacuum evaporation method. Next, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the wiring and the electrodes (the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121). At this time, a film is formed over the gate electrode layer 101.

[0051] First, prepare a substrate 100. The substrate 100 may be an alkali-free glass substrate, an aluminoborosilicate glass substrate, or an aluminosilicate glass substrate, etc., which is made by the fusion method or the float method. In addition to these, a ceramic substrate, or a plastic substrate having heat resistance sufficient to withstand the processing temperature of this manufacturing process can be used. Further, a substrate having an insulating film provided on the surface of any metal substrate such as a stainless steel alloy may be applied. Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used.

[0052] In addition, an insulating film may be formed as an underlayer film on the substrate 100. As the underlayer film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used. These can be formed by the CVD method, the sputtering method, or the like. When a substrate containing mobile ions such as a glass substrate is used as the substrate 100, by using a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film as the underlayer film, it is possible to prevent mobile ions from entering the semiconductor layer. Next, a conductive film for forming a gate wiring including a gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire surface of the substrate 100 by the sputtering method or the vacuum evaporation method. Next, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the wiring and the electrodes (the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121). At this time, a film is formed over the gate electrode layer 101. First, prepare a substrate 100. The substrate 100 may be an alkali-free glass substrate, an aluminoborosilicate glass substrate, or an aluminosilicate glass substrate, etc., which is made by the fusion method or the float method. In addition to these, a ceramic substrate, or a plastic substrate having heat resistance sufficient to withstand the processing temperature of this manufacturing process can be used. Further, a substrate having an insulating film provided on the surface of any metal substrate such as a stainless steel alloy may be applied. Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, an insulating film may be formed as an underlayer film on the substrate 100. As the underlayer film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used. These can be formed by the CVD method, the sputtering method, or the like. When a substrate containing mobile ions such as a glass substrate is used as the substrate 100, by using a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film as the underlayer film, it is possible to prevent mobile ions from entering the semiconductor layer.

[0053] Next, a conductive film for forming a gate wiring including a gate electrode layer 101, a capacitor wiring 108, and a first terminal 121 is formed over the entire surface of the substrate 100 by the sputtering method or the vacuum evaporation method. Next, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching to form the wiring and the electrodes (the gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121). At this time, a film is formed over the gate electrode layer 101. First, prepare a substrate 100. The substrate 100 may be an alkali-free glass substrate, an aluminoborosilicate glass substrate, or an aluminosilicate glass substrate, etc., which is made by the fusion method or the float method. In addition to these, a ceramic substrate, or a plastic substrate having heat resistance sufficient to withstand the processing temperature of this manufacturing process can be used. Further, a substrate having an insulating film provided on the surface of any metal substrate such as a stainless steel alloy may be applied. Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. In addition, an insulating film may be formed as an underlayer film on the substrate 100. As the underlayer film, a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be used. These can be formed by the CVD method, the sputtering method, or the like. When a substrate containing mobile ions such as a glass substrate is used as the substrate 100, by using a film containing nitrogen such as a silicon nitride film or a silicon nitride oxide film as the underlayer film, it is possible to prevent mobile ions from entering the semiconductor layer. To prevent the film from being segmented, the edge of the gate electrode layer 101 is preferably etched to have a tapered shape. The cross-sectional view at this stage is shown in Fig. 2(A). Note that the plan view at this stage corresponds to Fig. 4(B). The gate wiring including the gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion can be formed in a single layer or a stacked layer using a metal material such as aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or an alloy material mainly composed of these metal materials, or a nitride containing these metal materials as components. When a low-resistance metal material such as aluminum or copper is used for the electrode layer, it is preferably used in combination with a high-melting-point metal material due to problems of heat resistance and corrosion resistance. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used. For example, as the stacked structure of the gate electrode layer 101, a two-layer stacked structure in which molybdenum is stacked on aluminum, a two-layer structure in which molybdenum is stacked on copper, a two-layer structure in which titanium nitride or tantalum nitride is stacked on copper, or a two-layer structure in which titanium nitride and molybdenum are stacked is preferable. As the three-layer stacked structure, a structure in which aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as the intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as the upper and lower layers is preferable.

[0054] At this time, an oxide conductive layer having translucency is used for some electrode layers and wiring layers to improve the aperture ratio. aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium and other metal materials, or alloy materials mainly composed of these metal materials, or nitrides containing these metal materials as components can be used to form a single layer or a stack. When a low-resistance metal material such as aluminum or copper is used for the electrode layer, it is advisable to use it in combination with a high-melting-point metal material due to heat resistance and corrosion problems. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, etc. can be used.

[0055] For example, as the stacked structure of the gate electrode layer 101, a two-layer stacked structure in which molybdenum is stacked on aluminum, a two-layer structure in which molybdenum is stacked on copper, a two-layer structure in which titanium nitride or tantalum nitride is stacked on copper, or a two-layer structure in which titanium nitride and molybdenum are stacked is preferable. For the three-layer stacked structure, a structure in which aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as the intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as the upper and lower layers is preferable. or a two-layer structure in which titanium nitride and molybdenum are stacked is preferable. As the three-layer stacked structure, aluminum, an alloy of aluminum and silicon, an alloy of aluminum and titanium, or an alloy of aluminum and neodymium is used as the intermediate layer, and tungsten, tungsten nitride, titanium nitride, or titanium is used as the upper and lower layers to form a stacked structure is preferable.

[0056] At this time, an oxide conductive layer having translucency is used for some electrode layers and wiring layers to improve the aperture ratio. ​​​It is also possible. For example, indium oxide, indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide, aluminum zinc oxynitride aluminum, or zinc gallium oxide, etc. can be used.

[0057] Next, a gate insulating layer 102 is formed on the gate electrode layer 101. The gate insulating layer 102 has a film thickness of 50 nm or more and 250 nm or less, and is formed by a CVD method, a sputtering method, or the like.

[0058] For example, as the gate insulating layer 102, a silicon oxide film with a film thickness of 100 nm is formed by a sputtering method. Of course, the gate insulating layer 102 is not limited to a silicon oxide film, and may be formed as a single layer or a laminated structure made of an oxynitride silicon film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, a tantalum oxide film, or other insulating films, and formed from these materials.

[0059] Also, as the gate insulating layer 102, it is also possible to form a silicon oxide layer by a CVD method using an organic silane gas. As the organic silane gas, ethyl silicate (TEOS), te tramethylsilane (TMS), tetramethylcyclotetrasiloxane (TMCTS), o ctamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS ), triethoxysilane (TRIES), tris(dimethylamino)silane (TDMAS), etc. silicon-containing compounds can be used.

[0060] Also, as the gate insulating layer 102, oxides, nitrides, oxynitrides, or nitroxides of aluminum, yttrium, or hafnium can be used. Also, their compounds ​​A compound containing at least two kinds of substances may be used.

[0061] In this specification, an oxynitride is an oxynitride having a composition in which the number of oxygen atoms is greater than the number of nitrogen atoms. Nitride oxide refers to a substance in which the number of nitrogen atoms exceeds the number of oxygen atoms. For example, a silicon oxynitride film is a material that contains more nitrogen atoms than silicon. The number of oxygen atoms is larger than that of the ion-exchanged nuclei, and the Rutherford BBS method ackscattering spectrometry and hydrogen forward scattering spectrometry (HFS) When measured using Hydrogen Forward Scattering (Hydrogen Forward Scattering) The concentration range is 50 atomic % to 70 atomic % for oxygen, and 0.5 atomic % to 15 atomic % for nitrogen. % or less, silicon is 25 atomic % to 35 atomic %, hydrogen is 0.1 atomic % to 10 atomic % % or less. The composition of the silicon oxide nitride film is as follows: There are more nitrogen atoms than oxygen atoms, and when measured using RBS and HFS, the concentration range As the atomic percentage, oxygen is 5 atomic percent or more and 30 atomic percent or less, nitrogen is 20 atomic percent or more and 55 atomic percent or less, and silicon is The content of carbon is between 25 atomic % and 35 atomic % and the content of hydrogen is between 10 atomic % and 30 atomic %. However, the total number of atoms constituting silicon oxynitride or silicon nitride oxide is When the atomic percentage of is 100, the content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges. This is to be included.

[0062] Note that before an oxide semiconductor film for forming the oxide semiconductor layer 103 is formed, an argon gas is Reverse sputtering is performed by introducing gas to generate plasma, and the It is preferable to remove the dust that is on the substrate. A method of applying a voltage using a power source to form plasma near a substrate to modify the surface. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, the process may be carried out in an atmosphere in which oxygen, N2O, etc. are added to the argon atmosphere. Also, the process may be carried out in an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere. After the reverse sputtering process, without exposing to the atmosphere, by forming an oxide semiconductor film, it is possible to prevent dust and moisture from adhering to the interface between the gate insulating layer 102 and the oxide semiconductor layer 103.

[0063] Next, an oxide semiconductor film having a film thickness of 5 nm or more and 200 nm or less, preferably 10 nm or more and 40 nm or less, is formed on the gate insulating layer 102.

[0064] As the oxide semiconductor film, an In-Sn-Ga-Zn-O film which is a quaternary metal oxide film, an In-Ga-Zn-O film which is a ternary metal oxide film, an In-Sn-Zn-O film, an In-Al-Zn-O film, a Sn-Ga-Zn-O film, an Al-Ga-Zn-O film, a Sn-Al-Zn-O system, or a binary metal oxide film such as an In-Zn-O film, a Sn-Zn-O film, an Al-Zn-O film, a Zn-Mg-O film, a Sn-Mg-O film, an In-Mg-O film, an In-O film, a Sn-O film, a Zn-O film, etc. can be used. Also, the above oxide semiconductor film may contain SiO2.

[0065] Here, a target for forming an oxide semiconductor containing In, Ga, and Zn (molar ratio of In2O3:Ga2O3:ZnO = 1:1:1, or In2O3:Ga2O3:ZnO = 1:1:2) is used, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, ​​​​​​​​​​​A film is formed under an atmosphere of a direct current (DC) power supply of 0.5 kW and oxygen (oxygen flow rate ratio: 100%). Note that , when using a pulsed DC power supply, dust can be reduced and the film thickness distribution can be easily made uniform. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based oxide semiconductor film with a thickness of 30 nm is formed by sputtering using a target for In-Ga-Zn-O film formation. .

[0066] Sputtering methods include an RF sputtering method using a high-frequency power supply for the sputtering power supply, a DC sputtering method using a DC power supply, and a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a film having electrical conductivity such as a metal film. .

[0067] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and form different material films in the same chamber, or can simultaneously form multiple types of materials in the same chamber.

[0068] There is also a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber, or an ECR sputtering apparatus using plasma generated using microwaves without using glow discharge.

[0069] In addition, as a film formation method using sputtering, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation. .

[0070] Next, a second photolithography process is performed to form a resist mask, and the In-Ga-Z n-O film is etched. Organic acids such as citric acid and oxalic acid can be used as an etchant. Here, ITO07N (manufactured by Kanto Chemical Co., Inc.) was used For wet etching, unnecessary portions are removed to form the In-Ga-Zn-O film into an island shape and the oxide semiconductor layer 103 is formed. By tapering the end portion of the oxide semiconductor layer 103 etching, disconnection of the wiring due to the step shape can be prevented. Note that the etching here is not limited to wet etching, and dry etching may be used .

[0071] Next, dehydration or dehydrogenation of the oxide semiconductor layer is performed. The first heat treatment for performing this dehydration or dehydrogenation is carried out by using a high-temperature gas (an inert gas such as nitrogen or a rare gas) or light at 5 00 °C or higher and 750 °C or lower (or a temperature equal to or lower than the strain point of the glass substrate) for 1 minute or more and 10 minutes or less, preferably by RTA (Rapid Thermal Anneal) treatment at 650 °C for 3 minutes or more and 6 minutes or less . By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so that processing can be performed even at a temperature exceeding the strain point of the glass substrate . A cross-sectional view at this stage is shown in Fig. 2(B), and a plan view is shown in Fig. 5. Note that the heat treatment is not limited to this timing, and it may be performed multiple times before and after the photolithography process or the film formation process .

[0072] Here, the surface layer portion of the oxide semiconductor layer 103 is crystallized by the first heat treatment and has a crystal region 106 composed of microcrystals . Also, other regions of the oxide semiconductor layer 103 ​The region is either amorphous or a mixture of amorphous and microcrystals with microcrystals dispersed in the amorphous region, or it entirely becomes a group of microcrystals. Note that the crystal region 106 is part of the oxide semiconductor layer 103, and hereinafter, the notation of the oxide semiconductor layer 103 shall include the crystal region 106.

[0073] In this specification, heat treatment in an inert gas atmosphere such as nitrogen or a rare gas is referred to as heat treatment for dehydration or dehydrogenation. In this specification, dehydrogenation does not solely refer to the elimination as H2 by this heat treatment. Rather, for the sake of convenience, it includes dehydration or dehydrogenation including the elimination of H, OH, etc. It is important that the oxide semiconductor layer subjected to dehydration or dehydrogenation does not come into contact with the atmosphere and

[0074] is not re - mixed with water or hydrogen. After performing dehydration or dehydrogenation to make the oxide semiconductor layer n - type (n, n, etc.), that is, to lower the resistance, and then making it i - type to have a high resistance, a transistor using the oxide semiconductor layer has a positive threshold voltage value (Vth) and exhibits so - called normally - off characteristics. For a transistor used in a - display device, it is preferable that the threshold voltage is a positive value as close as possible to 0V. In an active - matrix + type display device, the electrical characteristics of the transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, the threshold voltage of the transistor is important. If the threshold voltage value of the transistor is negative, a current flows between the source electrode and the drain electrode even when the gate voltage is 0V, resulting in so - called normally - on characteristics, and it becomes difficult to control the circuit composed of such transistors. The electrical characteristics of the transistors constituting the circuit are important, and these electrical characteristics affect the performance of the display device. In particular, the threshold voltage of the transistor is important. If the threshold voltage value of the transistor is negative, a current flows between the source electrode and the drain electrode even when the gate voltage It becomes difficult. Also, even if the threshold voltage value is positive, if the absolute value thereof is high for a transistor there may be a case where the driving voltage is insufficient and the switching operation itself cannot be performed. In the case of an n-channel type transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied as the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state, is not suitable as a transistor used in a circuit.

[0075] When cooling from the temperature at which dehydration or dehydrogenation is performed, the atmosphere may be switched to an atmosphere different from the atmosphere during the temperature increase or heat treatment. For example, without exposing the inside of the same furnace to the atmosphere after dehydration or dehydrogenation, the inside of the furnace can be filled with high-purity oxygen gas, N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) for cooling.

[0076] In the first heat treatment, it is preferable that the atmosphere does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0077] When the heat treatment is performed in the above-described inert gas atmosphere, the oxide semiconductor layer becomes oxygen-deficient type and is n-type (n - + ​​​​​​​​​​​​​By forming an oxide insulating layer in contact with the layer, the oxide semiconductor layer is made in an oxygen-excess state, which can be said to cause i-type conversion, that is, high resistance conversion. As a result, a transistor with good electrical characteristics and high reliability can be fabricated. Moreover, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, a part of the oxide semiconductor layer may crystallize. After the first heat treatment, it becomes an oxygen-deficient type and the oxide semiconductor layer 103 has a lower resistance. After the first heat treatment, the carrier concentration increases compared to the oxide semiconductor film immediately after film formation, preferably having a carrier concentration of 1×10 / cm

[0078] or more. In addition, the first heat treatment of the oxide semiconductor layer can also be performed on the oxide semiconductor film before processing it into an island-shaped oxide semiconductor layer. In that case, a second photolithography step is performed after the first heat treatment. In this case, a crystal region is not formed in a part of the island-shaped oxide semiconductor layer 103, and the crystal region 106 is formed only in the upper layer part excluding the side surface part (see Fig. 10(A). 18 / cm 3 Then, a third photolithography step is performed to form a resist mask, and unnecessary parts are removed by etching to form a contact hole reaching a wiring or an electrode layer made of the same material as the gate electrode layer 101. This contact hole is provided to be continuous with a conductive film to be formed later and the above-mentioned wiring, etc.

[0079] Next, as a conductive layer on the oxide semiconductor layer 103 and the gate insulating layer 102, the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114 are formed by sputtering or vacuum evaporation. ).

[0080]

[0081] ​​​​​​​​​​ The cross-sectional view at this stage is shown in Fig. 2(C).

[0082] As the materials for the first conductive layer 112, the second conductive layer 113, and the third conductive layer 114, the same materials as those of the gate electrode layer 101 described above can be used. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used.

[0083] Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used. Here, titanium, which is a heat-resistant conductive material, is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113. By adopting such a configuration, while taking advantage of the low resistivity of aluminum, the generation of hillocks can be reduced. In this embodiment, a three-layer conductive layer is used, but it is not limited thereto, and a single-layer structure, a two-layer structure, or a structure of four or more layers may be used. For example, a single-layer structure of titanium may be used, or a laminated structure with aluminum containing silicon may be used.

[0084] Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6. Next, a fourth photolithography process is performed to form a resist mask 131, and unnecessary portions are removed by etching to form a source electrode layer 105a, a drain electrode layer 105b, an oxide semiconductor layer 103, and a connection electrode 120. As the etching method at this time, wet etching or dry etching is used. For example, when titanium is used for the first conductive layer 112 and the third conductive layer 114, and an aluminum alloy containing neodymium is used for the second conductive layer 113, wet etching can be performed using hydrogen peroxide water or heated hydrochloric acid as an etchant. In this etching process, a part of the oxide semiconductor layer 103 is etched, and an oxide semiconductor layer 103 having a thin region in thickness is formed between the source electrode layer 105a and the drain electrode layer 105b. The cross-sectional view at this stage is shown in Fig. 3(A), and the plan view is shown in Fig. 6.

[0085] At this time, if etching is performed under the condition that the etching selectivity between the first conductive layer 112 and the third conductive layer 114 and the oxide semiconductor layer 103 is sufficient, a transistor structure in which the crystal region of the surface layer portion as shown in FIG. 1(B) remains is obtained. Also, the etching of the first conductive layer 112, the second conductive layer 113, the third conductive layer 114, and the oxide semiconductor layer 103 can all be etched by using hydrogen peroxide water or heated hydrochloric acid. Therefore, steps such as steps do not occur at the ends of the source electrode layer 105a or the drain electrode layer 105b and the oxide semiconductor layer 103. Further, since wet etching is used, the etching is performed isotropically, and the ends of the source electrode layer 105a and the drain electrode layer 105b retreat from the resist mask 131. Through the above steps, a transistor 170 having the oxide semiconductor layer 103 and the crystal region 106 as a channel formation region can be manufactured.

[0086]

[0087] Here, by using the above-described oxide conductive layer having translucency in the same manner as the gate electrode layer 101 for the source electrode layer 105a and the drain electrode layer 105b, the translucency of the pixel portion can be improved, and the aperture ratio can be increased.

[0088]

[0089] Also, in this fourth photolithography process, the second terminal 122, which is made of the same material as the source electrode layer 105a and the drain electrode layer 105b, is left at the terminal portion. Note that the second terminal 1 ​​​​​​​​​​​​​​ 22 is a source wiring (a source wiring including a source electrode layer 105a or a drain electrode layer 105b). The power supply is electrically connected to the power supply line.

[0090] In addition, in the terminal portion, the connection electrode 120 is connected to a contact formed in the gate insulating layer 102. It is directly connected to the first terminal 121 of the terminal portion through a hole. However, the source wiring or drain wiring of the transistor of the driving circuit is formed through the same process as described above. The gate electrode is directly connected to the gate wiring.

[0091] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a photomask, the number of resist masks can be reduced, simplifying the process and This also reduces costs.

[0092] Next, the resist mask 131 is removed, and the oxide insulating layer 107 covering the transistor 170 is removed. The oxide insulating layer 107 can be formed using a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like. For example, a tantalum oxide film, a tantalum oxide film, or the like can be used.

[0093] In this embodiment, a silicon oxide film is deposited as the oxide insulating layer by a sputtering method. The substrate temperature during the process may be set to room temperature or higher and 300° C. or lower. In this embodiment, the substrate temperature is set to 100° C. Here, as a method to prevent impurities such as water and hydrogen from being mixed in during film formation, Pre-bake at a temperature between 50℃ and 350℃ for between 2 and 10 minutes, and then avoid exposure to air. It is desirable to form an oxide insulating layer without causing any damage to the silicon oxide film. The film is heated under a rare gas (typically argon) atmosphere, under oxygen atmosphere, or under a rare gas (typically It can be carried out in a mixed atmosphere of argon and oxygen. Also, as the target, , a silicon oxide target or a silicon target can be used. For example, using a silicon target , silicon oxide can be formed by sputtering in an oxygen and rare gas atmosphere. For the oxide insulating layer formed in contact with the low-resistance oxide semiconductor layer, it is preferable to use an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, and OH ions, and blocks the intrusion of these from the outside. -

[0094] In this embodiment, a silicon target with a purity of 6N and columnar polycrystalline B-doped (resistance value 0 .01 Ω·cm) is used, the distance between the substrate and the target (T-S distance) is 89 mm, the pressure is 0.4 Pa, a DC power supply of 6 kW, and film formation is performed by pulsed DC sputtering in an oxygen (oxygen flow ratio 100%) atmosphere. The film thickness is 300 nm.

[0095] Next, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is performed in an inert gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is performed in a nitrogen atmosphere. Or, an RTA treatment with high temperature and short time may be performed in the same manner as the first heat treatment. In the second heat treatment, since the oxide insulating layer 107 is heated in contact with the oxide semiconductor layer 103, oxygen is supplied from the oxide insulating layer 107 to the oxide semiconductor layer 10 3 which became n-type and had its resistance reduced in the first heat treatment, resulting in an oxygen-excess state, and the oxide semiconductor layer 1 03 can be made i-type (high resistance).

[0096] In this embodiment, the second heat treatment is performed after forming the silicon oxide film, but the timing of the heat treatment G is not limited to immediately after the formation of the silicon oxide film, and there is no problem as long as it is after the formation of the silicon oxide film. Yes.

[0097] Also, in the case of using a heat-resistant material for the source electrode layer 105a and the drain electrode layer 105b, a process using the first heat treatment conditions can be performed at the timing of the second heat treatment. In this case, the heat treatment can also be performed only once after the formation of the silicon oxide film.

[0098] Next, a fifth photolithography process is performed to form a resist mask, and contact holes 125 reaching the drain electrode layer 105b are formed by etching the oxide insulating layer 107. Also, contact holes 127 reaching the second terminal 122 and contact holes 126 reaching the connection electrode 120 are also formed by the etching here. The cross-sectional view at this stage is shown in FIG. 3(B). Shown in FIG. 3(B).

[0099] Next, after removing the resist mask, a transparent conductive film is formed. As the transparent conductive film, materials such as indium oxide (In2O3) and indium tin oxide alloy (In2O3 - SnO2, hereinafter abbreviated as ITO) can be used, and it can be formed by sputtering or vacuum evaporation. The etching treatment of such materials is performed using a hydrochloric acid-based solution. However, since ITO is likely to generate etching residues, indium zinc oxide alloy (In2O3 - ZnO, hereinafter abbreviated as IZO) may be used to improve the etching processability.

[0100] Next, a sixth photolithography process is performed to form a resist mask, and unnecessary portions of the transparent conductive film are removed by etching to form the pixel electrode layer 110. Here, at the capacitance portion With the gate insulating layer 102 and the oxide insulating layer 107 as dielectrics, a holding capacitor is formed by the capacitor wiring 108 and the pixel electrode layer 110.

[0101] Also, in this sixth photolithography process and etching process, transparent conductive layers 128 and 129 are formed above the first terminal 121 and the second terminal 122, respectively. The transparent conductive layers 128 and 129 serve as electrodes or wirings used for connection with the FPC. The transparent conductive layer 128 connected to the first terminal 121 functions as an input terminal of the gate wiring and becomes a terminal electrode for connection. Further, the transparent conductive layer 129 formed on the second terminal 122 becomes a terminal electrode for connection that functions as an input terminal of the source wiring.

[0102] Next, the resist mask is removed. The cross-sectional view at this stage is shown in FIG. 3(C), and the plan view is shown in FIG. 7.

[0103] Also, FIGS. 8(A1) and 8(A2) respectively show a plan view and a cross-sectional view of the gate wiring terminal portion at this stage. FIG. 8(A1) corresponds to a cross-sectional view taken along line C1 - C2 in FIG. 8(A2). In FIG. 8(A1), the transparent conductive layer 155 formed on the protective insulating film 154 and the connection electrode 153 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 8(A1), the first terminal 151 formed of the same material as the gate wiring and the connection electrode 153 formed of the same material as the source wiring overlap via the gate insulating layer 152, and a part is in direct contact and electrically conductive. Further, the connection electrode 153 and the transparent conductive layer 155 are in direct contact and electrically conductive through a contact hole provided in the protective insulating film 154.

[0104] Also, FIGS. 8(B1) and 8(B2) show a plan view and a cross-sectional view of the source wiring terminal portion, respectively. FIG. 8(B1) corresponds to a cross-sectional view taken along line D1-D2 in FIG. 8(B2). In FIG. 8(B1), the transparent conductive layer 155 formed on the protective insulating film 154 and the connection electrode 150 is a terminal electrode for connection that functions as an input terminal. Also, in FIG. 8(B1), the second terminal 156 formed of the same material as the gate wiring overlaps with the connection electrode 150 electrically connected to the source wiring via the gate insulating layer 152. The second terminal 156 is not electrically connected to the connection electrode 150. If the second terminal 156 is set to a potential different from that of the connection electrode 150, for example, floating, GND, 0V, etc., a capacitor for noise countermeasure or a capacitor for electrostatic countermeasure can be formed. Also, the connection electrode 150 is electrically connected to the transparent conductive layer 155 through a contact hole provided in the protective insulating film 154.

[0105] A plurality of gate wirings, source wirings, and capacitor wirings are provided according to the pixel density. Also, in the terminal portion, a plurality of first terminals at the same potential as the gate wiring, second terminals at the same potential as the source wiring, third terminals at the same potential as the capacitor wiring, etc. are arranged side by side. The number of each terminal can be set to an arbitrary number, and the implementer can appropriately determine it.

[0106] In this way, by using six photolithography processes, the channel etch type transistor 170 and the holding capacitor portion can be completed. By configuring the pixel portions arranged in a matrix with these, one substrate for manufacturing an active matrix type display device can be fabricated. It can be set as such. In this specification, for convenience, such a substrate is referred to as an active matrix substrate. is called.

[0107] When manufacturing an active matrix type liquid crystal display device, a liquid crystal layer is provided between the active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode that is electrically connected to the counter electrode provided on the counter substrate is provided on the active matrix substrate, and a fourth terminal that is electrically connected to the common electrode is provided at the terminal portion. This fourth terminal is a terminal for setting the common electrode to a fixed potential, such as GND, 0V, etc.

[0108] Also, this embodiment is not limited to the pixel configuration of FIG. 7. A plan view of another pixel configuration example is shown in FIG. 9 In FIG. 9, there is an example in which a capacitance wiring is not provided, and a holding capacitance is formed by overlapping pixel electrodes via the gate wiring, the protective insulating film and the gate insulating layer of adjacent pixels. In this case, the capacitance wiring and the third terminal connected to the capacitance wiring can be omitted. Note that in FIG. 9, the same reference numerals are used for the same parts as in FIG. 7.

[0109] In an active matrix type liquid crystal display device, an image is formed by driving liquid crystal elements arranged in a matrix. Specifically, a voltage is applied between the pixel electrode and the counter electrode included in the selected liquid crystal element, whereby optical modulation of the liquid crystal layer is performed, and this optical modulation is recognized by the observer as an image.

[0110] In the video display of a liquid crystal display device, there is a problem that afterimages occur because the response of the liquid crystal molecules themselves is slow. In order to reduce such afterimages, so-called performing all-black display every other frame ​​​​​There is a driving technique called black insertion.

[0111] In addition, the response speed is improved by increasing the normal vertical sync frequency by 1.5 times, preferably by more than twice as much. and selecting a gray scale to be written for each of the divided fields in each frame. There is also a driving technology called double speed driving.

[0112] In addition, multiple LED (light emitting diode) light sources or multiple EL light sources are used as backlights. Each light source constituting the surface light source is independently controlled within one frame period. There is also a driving technology for intermittent lighting. For example, when using LEDs, a single white LED is used. LEDs of three or more colors can be used. Therefore, the timing of LED emission can be adjusted to match the switching timing of the optical modulation of the liquid crystal layer. They can also be synchronized. This driving technology allows LEDs to be partially turned off, In particular, in the case of video display in which the proportion of the black display area occupying the entire screen is high, the power consumption reduction effect is The results can be seen.

[0113] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0114] In addition, when manufacturing a light-emitting display device, an electrode (also called a cathode) on the low power supply potential side of a light-emitting element is ) is set to GND, 0V, etc., so the cathode is connected to the terminal at a low power supply potential, e.g. For example, a fourth terminal is provided for setting the voltage to GND, 0V, etc. When manufacturing a pixel, a power supply line is provided in addition to the source line and gate line. The slave portion is provided with a fifth terminal that is electrically connected to the power supply line.

[0115] In this embodiment, the manufacturing method will be described by taking a channel-etch type transistor as an example. However, by changing the order of the steps, it is also possible to manufacture a transistor having a bottom contact structure.

[0116] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the transistors in the pixel portion on the same substrate with respect to the gate line or the source line. The protection circuit is preferably configured by using a non-linear element using an oxide semiconductor layer.

[0117] Through the above steps, it is possible to provide a transistor having good electrical characteristics and high reliability and a display device using the transistor.

[0118] Note that the configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0119] (Embodiment 3) In this embodiment, an example of operating a part of a driving circuit and a pixel portion configured by transistors manufactured on the same substrate will be described.

[0120] In this embodiment, a pixel portion and a driving circuit portion are formed on the same substrate by using the method for manufacturing a transistor according to Embodiment 1. Note that the transistor shown in Embodiment 1 is an n-channel type transistor, and the driving circuit portion is limited to a part of the circuit that can be configured only by n-channel type transistors.

[0121] An example of a block diagram of an active matrix type display device is shown in FIG. 14(A). ​​​​​​​​On the substrate 5300, a pixel section 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, and a signal line driving circuit 5304 are arranged. In the pixel section 5301, a plurality of signal lines extend from the signal line driving circuit 5304 and are arranged, and a plurality of scanning lines extend from the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 and are arranged. In the intersection area of the scanning line and the signal line, pixels each having a display element are arranged in a matrix. Further, the substrate 5300 of the display device is connected to a timing control circuit 5305 (also referred to as a controller or a control IC) via a connection section such as an FPC (Flexible Printed Circuit). The first scanning line driving circuit 5302, the second scanning line driving circuit 5303, and the signal line driving circuit 5304 shown in FIG. 14(A) are formed on the same substrate 5300 as the pixel section 5301. Therefore, the number of components such as driving circuits provided externally is reduced, so that cost reduction can be achieved. Also, the connection section (such as an FPC) between the substrate 5300 and an external driving circuit can be reduced, so that reliability and yield can be improved. The timing control circuit 5305 supplies a start signal for the first scanning line driving circuit (GSP1) (the start signal is also referred to as a start pulse), a clock signal for the scanning line driving circuit (GCK1), etc. to the first scanning line driving circuit 5302. Also, for the second scanning line driving circuit 5303, a start signal for the second scanning line driving circuit (GSP2), a clock signal for the scanning line driving circuit (GCK2), etc. are supplied.

[0122]

[0123]

[0124] Also, for the signal line driving circuit 5304, a start signal for the signal line driving circuit (SSP), a clock signal for the signal line driving circuit (SCK), video signal data (DATA) (also simply referred to as a video signal), a latch signal (LAT), etc. are to be supplied. Note that each clock signal may be a plurality of clock signals with a phase shift, or may be supplied together with a signal obtained by inverting the clock signal (CK B). Note that one of the first scanning line driving circuit 5302 and the second scanning line driving circuit 5303 can be omitted.

[0125] In FIG. 14(B), a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driving circuit 5304 is formed on a substrate different from the pixel portion 5301. With this configuration, even when using a transistor with a relatively small field effect mobility, a part of the driving circuit can be configured on the same substrate as the pixel portion. Therefore, cost reduction and yield improvement can be achieved.

[0126] Next, an example of the configuration and operation of a signal line driving circuit composed of n-channel transistors will be described with reference to FIGS. 15(A) and 15(B).

[0127] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). Also, the switching circuits 5602_1 to 5602_N are each composed of transistors 5603_1 to 5603_k (k is a natural number). Here, the transistors The transistors 5603_1 to 5603_k are n-channel transistors.

[0128] Regarding the connection relationship of the signal line driving circuit, the switching circuit 5602_1 will be described as an example. The first terminals of the transistors 5603_1 to 5603_k are respectively connected to the wirings 5604_1 to 5 604_k. The second terminals of the transistors 5603_1 to 5603_k are respectively connected to the signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are connected to the wiring 5605_1.

[0129] The shift register 5601 outputs signals of the H level (also called the H signal , the high power supply potential level) to the wirings 5605_1 to 5605_N in sequence, and has the function of selecting the switching circuits 5602_1 to 56 02_N in sequence.

[0130] The switching circuit 5602_1 has the function of controlling the conduction state (conduction between the first terminal and the second terminal) between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, the function of controlling whether to supply the potentials of the wirings 5604_ 1 to 5604_k to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has the function as a selector. Also, the transistors 5603_1 to 5603_k each have the function of controlling the conduction state between the wirings 5604_1 to 5604_k and the signal lines S1 to Sk, that is, the function of supplying the potentials of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. In this way, the transistors 5603_1 to 5603_k each have the function as a switch. ~5603_k each have the function as a switch.

[0131] Note that video signal data (DATA) is respectively provided to the wirings 5604_1 to 5604_k. is input. The data (DATA) for the video signal is often an analog log signal corresponding to the image information or the image signal.

[0132] Next, the operation of the signal line driving circuit in Fig. 15(A) will be described with reference to the timing chart in Fig. 15(B). Fig. 15(B) shows an example of signals Sout_1 to Sout_N and signals Vdata_1 to Vdata_k. The signals Sout_1 to Sout_N are each an example of the output signals of the shift register 5601, and the signals Vdata_1 to Vdata _k are each an example of the signals input to the wirings 5604_1 to 5604_k. Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is divided into periods T1 to TN as an example. The periods T1 to TN are each a period for writing the video signal data (DATA) to the pixels belonging to the selected row. There is. In the periods T1 to TN, the shift register 5601 outputs H-level signals to the wirings 560 5_1 to 5605_N in order. For example, in period T1, the shift register 5

[0133] 601 outputs a high-level signal to the wiring 5605_1. At this time, the transistors 5 603_1 to 5603_k turn on, and the wirings 5604_1 to 5604_k and the signal lines S

[0134] 1 to Sk become conductive. Then, Data is applied to the wirings 5604_1 to 5604_k. For example, in period T1, the shift register 5 601 outputs a high-level signal to the wiring 5605_1. At this time, the transistors 5 603_1 to 5603_k turn on, and the wirings 5604_1 to 5604_k and the signal lines S 1 to Sk become conductive. And, to the wirings 5604_1 to 5604_k, Data (S1) to Data(Sk) are input. Data(S1) to Data(Sk) are each written, via transistors 5603_1 to 5603_k, to the pixels belonging to the selected row, specifically, to the pixels in the first column to the k-th column. Thus, in periods T1 to TN, video signal data (DATA) is written, column by column in order, to the pixels belonging to the selected row.

[0135] As described above, by writing the video signal data (DATA) to the pixels column by column, the number of video signal data (DATA) or the number of wirings can be reduced. Therefore, the number of connections to the external circuit can be reduced. Also, by writing the video signal to the pixels column by column, the writing time can be lengthened, and insufficient writing of the video signal can be prevented.

[0136] Note that as the shift register 5601 and the switching circuit 5602, a circuit composed of the transistors shown in Embodiment 1 or 2 can be used. In this case, all the transistors of the shift register 5601 can be composed of unipolar transistors.

[0137] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter, a buffer, etc. In the scanning line driving circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the pixels for one line's worth ofThe gate electrode of the transistor is connected. And the transistors of the pixels for one line must be turned on all at once, so a buffer capable of passing a large current is used.

[0138] A form of the shift register used in part of the scanning line driving circuit and / or the signal line driving circuit will be described with reference to FIGS. 16 and 17.

[0139] The shift register has first to Nth pulse output circuits 10_1 to 10_N ( N is a natural number of 3 or more) (see FIG. 16(A)). The first pulse output circuits 10_1 to 10_N of the shift register are supplied with a first clock signal CK1 from a first wiring 11, a second clock signal CK2 from a second wiring 12, a third clock signal CK3 from a third wiring 13, and a fourth clock signal CK4 from a fourth wiring 14.

[0140] Also, in the first pulse output circuit 10_1, a start pulse SP1 (first start pulse) from a fifth wiring 15 is input. Also, in the nth pulse output circuit 10_n (n is a natural number of 2 or more and N or less) from the second stage onward, a signal (referred to as a previous stage signal OUT(n - 1)) from the pulse output circuit of the previous stage is input.

[0141] Also, a signal from the third pulse output circuit 10_3 two stages later is input to the first pulse output circuit 10_1. Similarly, or in the nth pulse output circuit 10_n from the second stage onward, a signal (referred to as a subsequent stage signal OUT(n + 2)) from the (n + 2)th pulse output circuit two stages later is input.

[0142] ​​​​​​​​Therefore, from each stage of the pulse output circuit, a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the subsequent stage and / or the preceding stage of the pulse output circuit, and a second output signal (OUT(1) to OUT(N)) for input to another circuit or the like are output. As shown in FIG. 16(A), since the subsequent stage signal OUT(n + 2) is not input to the two stages at the final stage of the shift register, as an example, a separate second start pulse SP2 and a third start pulse SP3 may be respectively input.

[0143] The clock signal (CK) is a signal that repeats between the H level and the L level (also referred to as the L signal, low power supply potential level) at regular intervals. Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially delayed by 1 / 4 cycle. In the present embodiment, the first clock signal (CK1) to the fourth clock signal (CK4) are used to control the driving of the pulse output circuit and the like. The clock signal may also be referred to as GCK or SCK depending on the input driving circuit, but here it will be described as CK.

[0144] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are electrically connected to any one of the first wiring 11 to the fourth wiring 14. For example, in FIG. 16(A), in the first pulse output circuit 10_1, the first input terminal 21 is electrically connected to the first wiring 11, the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is electrically connected to the third wiring 13. Also, in the second pulse output circuit 10_2, the first input terminal 21 is electrically connected to the second wiring 12, the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. ​​​​​​​​​​​​​​​is electrically connected to the wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14 are connected.

[0145] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, and a fifth input terminal 25, a first output terminal 26, and a second output terminal 27 (see Fig. 16(B)). See).

[0146] In the first pulse output circuit 10_1, a first clock signal CK 1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third input A third clock signal CK3 is input to the terminal 23, a start pulse is input to the fourth input terminal 24 is input, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, and a first output signal OUT(1)(SR) is output from the first output terminal 2 6, and a second output signal OUT(1) is output from the second output terminal 27 will be output.

[0147] In addition, in the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N, in addition to the three-terminal transistor A four-terminal transistor 28 (see Fig. 16(C)) can be used In this specification, when a transistor has two gate electrodes via a semiconductor layer The gate electrode below the semiconductor layer is also called the lower gate electrode, and the gate electrode above the semiconductor layer Is also called the upper gate electrode. The transistor 28 is input to the lower gate electrode The first control signal G1 and the second control signal G2 input to the upper gate electrode is an element that can perform electrical control between the In terminal and the Out terminal.

[0148] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a transistor, the manufacturing process may cause the threshold voltage to shift to the negative side or the positive side. Therefore in a transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, a configuration capable of controlling the threshold voltage is preferable. In the transistor 28 shown in FIG. 16(C), gate electrodes are provided via gate insulating layers above and below the channel formation region, and by controlling the potential of the upper and / or lower gate electrodes, the threshold voltage can be controlled to a desired value.

[0149] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG. 16(D).

[0150] The pulse output circuit shown in FIG. 16(D) includes first transistors 31 to thirteenth transistors 43. In addition to the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the second output terminal 27 described above, a power supply line 51 to which a first high power supply potential VDD is supplied, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied are provided, and signals or power supply potentials are supplied to the first transistors 31 to thirteenth transistors 43 connected thereto.

[0151] Here, the magnitude relationship of the power supply potentials of the respective power supply lines in FIG. 16(D) is such that the first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC is a potential higher than the third power supply potential VSS. The first clock signal (CK1) to the fourth clock signal (CK4) are ​​​​​​​​​​, a signal that repeats the H level and the L level at regular intervals. For example, when at the H level, it is V DD, and when at the L level, it is VSS.

[0152] Note that by making the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, without affecting the operation, the potential applied to the gate electrode of the transistor can be kept low, which can reduce the shift of the threshold value of the transistor and suppress degradation.

[0153] Also, as shown in FIG. 16(D), among the first transistor 31 to the thirteenth transistor 43, it is preferable to use the four-terminal transistor 28 shown in FIG. 16(C) for the first transistor 31, the sixth transistor 36 to the ninth transistor 39.

[0154] For the first transistor 31, the sixth transistor 36 to the ninth transistor 39, it is required to switch the potential of the node to which one of the electrodes serving as the source or drain is connected according to the control signal of the gate electrode. Also, it is preferable that the transistor has a fast response (steep rise of the on-current) to the control signal input to the gate electrode, so as to further reduce the malfunction of the pulse output circuit. Therefore, by using a four-terminal transistor, the threshold voltage can be controlled, and a pulse output circuit with less malfunction can be obtained. In FIG. 16(D), the first control signal G1 and the second control signal G2 are the same control signal, but a configuration in which different control signals are input may also be used.

[0155] In FIG. 16(D), for the first transistor 31, the first terminal is electrically connected to the power supply line 51 Continuing, the second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode (the lower gate electrode and the upper gate electrode) is electrically connected to the fourth input terminal 24 and is.

[0156] The second transistor 32 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the first terminal of the ninth transistor 39, and its gate electrode electrically connected to the gate electrode of the fourth transistor 3 4.

[0157] The third transistor 33 has its first terminal electrically connected to the first input terminal 21 and its second terminal electrically connected to the first output terminal 26.

[0158] The fourth transistor 34 has its first terminal electrically connected to the power supply line 53 and its second terminal electrically connected to the first output terminal 26.

[0159] The fifth transistor 35 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode electrically connected to the fourth input terminal 24.

[0160] The sixth transistor 36 has its first terminal electrically connected to the power supply line 52, its second terminal electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34, and its gate electrode (the lower gate electrode and the upper gate electrode) electrically connected to the fifth input terminal 25 and is.

[0161] The seventh transistor 37 has its first terminal electrically connected to the power supply line 52 and its second terminal electrically connected to the eighth ​​is electrically connected to the second terminal of the transistor 38, and the gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the third input terminal 23.

[0162] The eighth transistor 38 has its first terminal electrically connected to the gate electrode of the second transistor 32 and the fourth transistor 34, and the gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the second input terminal 22.

[0163] The ninth transistor 39 has its first terminal electrically connected to the second terminal of the first transistor 31 and the second transistor 32, its second terminal electrically connected to the gate electrode of the third transistor 33 and the tenth transistor 40, and the gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 52.

[0164] The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, its second terminal electrically connected to the second output terminal 27, and the gate electrode electrically connected to the second terminal of the ninth transistor 39.

[0165] The eleventh transistor 41 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and the gate electrode electrically connected to the gate electrodes of the second transistor 32 and the fourth transistor 34.

[0166] The twelfth transistor 42 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the second output terminal 27, and the gate electrode electrically connected to the is electrically connected to the pole (lower gate electrode and upper gate electrode).

[0167] The 13th transistor 43 has its first terminal electrically connected to the power supply line 53, its second terminal electrically connected to the first output terminal 26, and its gate electrode electrically connected to the gate electrode of the 7th transistor 37 (lower gate electrode and upper gate electrode). is electrically connected to the pole (lower gate electrode and upper gate electrode).

[0168] In FIG. 16(D), the connection point of the gate electrode of the 3rd transistor 33, the gate electrode of the 10th transistor 40, and the second terminal of the 9th transistor 39 is defined as node A. Also, the connection point of the gate electrode of the 2nd transistor 32, the gate electrode of the 4th transistor 34, the second terminal of the 5th transistor 35, the second terminal of the 6th transistor 36, the first terminal of the 8th transistor 38, and the gate electrode of the 11th transistor 41 is defined as node B (see FIG. 17(A)).

[0169] In FIG. 17(A), when the pulse output circuit described in FIG. 16(D) is applied to the first pulse output circuit 10_ 1, the signals input or output to / from the first input terminal 21 to the fifth input terminal 25, the first output terminal 26 and the second output terminal 27 are shown.

[0170] Specifically, a first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, a third clock signal CK3 is input to the third input terminal 23, a start pulse (SP1) is input to the fourth input terminal 24, a subsequent stage signal OUT(3) is input to the fifth input terminal 25, a first output signal OUT(1)(SR) is output from the first output terminal 26, and a second output signal OUT( (2) is output from the second output terminal 27​​​​​​ 1) is output.

[0171] Note that a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between a drain region and a source region, and can conduct current through the drain region, the channel region, and the source region. Here, since the source and the drain change depending on the structure and operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the regions functioning as the source and the drain may not be called the source or the drain. As an example of that case, each may be denoted as the first terminal and the second terminal. Note that in FIG. 17(A), a capacitive element may be separately provided for performing a bootstrap operation by making node A in a floating state. Also, a capacitive element having one electrode electrically connected to node B may be separately provided to hold the potential of node B. Here, a timing chart of a shift register including a plurality of pulse output circuits shown in FIG. 17(A) is shown in FIG. 17(B). Note that when the shift register is a scanning line driving circuit, period 61 in FIG. 17(B) is a vertical blanking period, and period 62 corresponds to a gate selection period. Note that as shown in FIG. 17(A), by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, the following advantages exist before and after the bootstrap operation.

[0172]

[0173]

[0174]

[0175] ​​​​​​​​​​​​​When there is no ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, when the potential of node A rises due to the boost strap operation, the potential of the source which is the second terminal of the first transistor 31 rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the boost strap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed. Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted. When there is no ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, when the potential of node A rises due to the boost strap operation, the potential of the source which is the second terminal of the first transistor 31 rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the boost strap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed. Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal.

[0176] Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the boost strap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed. Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted. When there is no ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, when the potential of node A rises due to the boost strap operation, the potential of the source which is the second terminal of the first transistor 31 rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor. Therefore, by providing the ninth transistor 39 to which the second power supply potential VCC is applied to the gate electrode, although the potential of node A rises due to the boost strap operation, it is possible to prevent the potential of the second terminal of the first transistor 31 from rising. That is, by providing the ninth transistor 39, the value of the negative bias voltage applied between the gate and the source of the first transistor 31 can be reduced. Therefore, with the circuit configuration of this embodiment, the negative bias voltage applied between the gate and the source of the first transistor 31 can also be reduced, so that deterioration of the first transistor 31 due to stress can be suppressed. Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted. When there is no ninth transistor 39 to which a second power supply potential VCC is applied to the gate electrode, when the potential of node A rises due to the boost strap operation, the potential of the source which is the second terminal of the first transistor 31 rises and becomes larger than the first power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, a large bias voltage is applied between the gate and the source and between the gate and the drain, so that a large stress is applied, which may cause deterioration of the transistor.

[0177] Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted. Note that in the case of a shift register including a plurality of pulse output circuits in this embodiment, in a signal line driving circuit having more stages than the scanning line driving circuit, the ninth transistor 39 may be omitted. Note that the ninth transistor 39 may be provided so as to be connected between the second terminal of the first transistor 31 and the gate of the third transistor 33 via the first terminal and the second terminal. There is an advantage that the number of transistors can be reduced.

[0178] Note that, as the semiconductor layer of the first transistor 31 to the thirteenth transistor 43, an oxide semiconductor is used, whereby the off-current of the transistor can be reduced, and the on-current and the field-effect mobility can be increased. Therefore, the degree of deterioration can be reduced, so that malfunction within the circuit is reduced. Further, a transistor using an oxide semiconductor has a smaller degree of deterioration of the transistor due to application of a high potential to the gate electrode than a transistor using amorphous silicon. Therefore, the same operation can be obtained even if the first power supply potential VDD is supplied to the power supply line that supplies the second power supply potential VCC, and since the number of power supply lines routed between circuits

[0179] Note that, for the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37, the clock signal supplied by the third input terminal 23, and for the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38, the clock signal supplied by the second input terminal 22, the same operation is achieved even if the connection relationship is interchanged so that the clock signal supplied by the second input terminal 22 to the gate electrode (lower gate electrode and upper gate electrode) of the seventh transistor 37, and the clock signal supplied by the third input terminal 23 to the gate electrode (lower gate electrode and upper gate electrode) of the eighth transistor 38.

[0180] Note that, in the shift register shown in Fig. 17(A), the seventh transistor 37 and the eighth From the state where both transistors 38 are on, the seventh transistor 37 is turned off, the eighth transistor 38 is turned on, then the seventh transistor 37 is turned off, and the eighth transistor 38 is turned off. By doing so, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 occurs twice due to the potential drop of the gate electrode of the seventh transistor 37 and the potential drop of the gate electrode of the eighth transistor 38. It will occur.

[0181] On the other hand, in the shift register shown in Fig. 17(A), from the state where both the seventh transistor 37 and the eighth transistor 38 are on, the seventh transistor 37 is on, the eighth transistor 38 is off, then the seventh transistor 37 is off, and the eighth transistor 38 is off. By doing so, the potential drop of node B caused by the potential drop of the second input terminal 22 and the third input terminal 23 can be reduced once by the potential drop of the gate electrode of the eighth transistor 38. Therefore, it is preferable to have a connection relationship in which the clock signal CK3 is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and the clock signal CK2 is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. This is because the number of fluctuations in the potential of node B is reduced and noise can be reduced.

[0182] Therefore, it is preferable that the clock signal CK3 is supplied from the third input terminal 23 to the gate electrode (the lower gate electrode and the upper gate electrode) of the seventh transistor 37, and the clock signal CK2 is supplied from the second input terminal 22 to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. Because the number of fluctuations in the potential of node B is reduced and noise can be reduced. In this way, the period of holding the potentials of the first output terminal 26 and the second output terminal 27 at the L level to the gate electrode (the lower gate electrode and the upper gate electrode) of the eighth transistor 38. is preferably set so that the clock signal CK2 is supplied from the second input terminal 22. This is because the number of fluctuations in the potential of node B is reduced and noise can be reduced. is reduced, and noise can be reduced.

[0183] Thus, the period during which the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level By configuring the signal of level H to be periodically supplied to node B, malfunction of the pulse output circuit can be suppressed.

[0184] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0185] (Embodiment 4) In this embodiment, a display device having a display function formed by using the transistors shown in Embodiments 1 and 2 in a pixel portion and a driving circuit will be described.

[0186] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Also, a display medium such as electronic ink, whose contrast changes by an electric action, can be used.

[0187] Note that the display device in this specification refers to an image display device, a display device, or a light source (including an illumination device). Also, a connector, for example, an FPC (Flexible Printed Circuit) or a module to which a TAB (Tape Automated Bonding) tape is attached, a module in which a printed wiring board is provided at the tip of the TAB tape, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG (Chip On Glass) method is also included in the display device.

[0188] In this embodiment, the appearance and cross-section of a liquid crystal display panel corresponding to one form of the display device will be described , with reference to FIG. 20. FIGS. 20(A1) and (A2) are top views of the liquid crystal display panel , and FIG. 20(B) corresponds to a cross-sectional view taken along M-N of FIGS. 20(A1) and (A2). The liquid crystal display panel has a structure in which liquid crystal elements 4013 are sealed with a sealing material 4005 between a first substrate 4001 on which transistors 4010 and 4011 including an oxide semiconductor layer are formed and a second substrate 4006 .

[0189] A pixel portion 4002 provided on the first substrate 4001 and a scanning line driving circuit 4004 are surrounded by the sealing material 4005. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006 . Also, a signal line driving circuit 4003 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001 .

[0190] Note that the connection method of the separately formed driving circuit is not particularly limited, and methods such as the COG method, the wire bonding method, or the TAB method can be used. FIG. 20(A1) is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 20(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method .

[0191] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 are In FIG. 20B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistor 4010. An insulating layer 4020 is provided on the 011 .

[0192] The transistors 4010 and 4011 each include the oxide semiconductor layer described in Embodiments 1 and 2. In this embodiment, a highly reliable transistor including a The transistors 4010 and 4011 are n-channel transistors.

[0193] The oxide semiconductor layer of the transistor 4011 for the driver circuit is formed over the insulating layer 4044. A conductive layer 4040 is provided in a position overlapping the panel formation region. The conductive layer 4040 is oxidized. By providing the MOSFET in a position overlapping the channel formation region of the semiconductor layer, In addition, the amount of change in the threshold voltage of the transistor 4011 can be reduced. The second gate electrode 4040 is set to the same potential as the gate electrode layer of the transistor 4011. The conductive layer 4040 can function as a gate electrode of the transistor 4011. The conductive layer 4040 may be given a potential different from that of the ground electrode layer. It may be 0V or may be in a floating state.

[0194] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 400. 6. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4008. The overlapping portion corresponds to the liquid crystal element 4013. Note that an insulating layer 4032 and 4033 which function as alignment films are provided on the pixel electrode layer 4030 and the counter electrode layer 4031 respectively. Although not shown in the figure, the color filter may be provided on either side of the first substrate 4001 or the second substrate 4006. As the first substrate 4001 and the second substrate 4006, glass, ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used. Furthermore, columnar spacers 4035 are provided to control the thickness (cell gap) of the liquid crystal layer 4008. The spacer 4035 is obtained by selectively etching an insulating film. Note that the shape of the spacer is not limited to columnar, and for example, spherical spacers can also be used.

[0195] In addition, the counter electrode layer 4031 is electrically connected to a common potential line provided on the same substrate as the transistor 4010. Using a common connection portion, the counter electrode layer 4031 and the common potential line can be electrically connected through conductive particles disposed between the pair of substrates. Note that the conductive particles are contained in the sealing material 4005. Moreover, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases.

[0196]

[0197]

[0198] ​​​​​​​​​​​​​ Yes, when the cholesteric liquid crystal is heated, just before the transition from the cholesteric phase to the isotropic phase appears. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range . A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μsec or more and 1 00 μsec or less, and since it is optically isotropic, alignment treatment is not required and the viewing angle dependence is small. When using the blue phase, not limited to the configuration of FIG. 20, a so-called horizontal electric field mode structure in which an electrode layer corresponding to the counter electrode layer 4031 is formed on the same substrate side as the pixel electrode layer 4030 may be used. Note that, although this embodiment is an example of a transmissive liquid crystal display device, it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0199] In addition, this embodiment is an example of a transmissive liquid crystal display device, but it can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0200] Further, in the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and an example is shown in which a colored layer and an electrode layer used for the display element are provided in this order. However, the polarizing plate may be provided inside the substrate. Also, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and may be appropriately set according to the materials and manufacturing process conditions of the polarizing plate and the colored layer. Further, a light-shielding film that functions as a black matrix may be provided. Note that a light-shielding film that functions as a black matrix may be provided.

[0201] Further, in this embodiment, in order to reduce surface irregularities caused by the transistor and improve reliability, the transistor is covered with an insulating layer (insulating layer 4020, insul ating layer 4021) that functions as a protective film or a planarizing insulating film. The protective film is an organic substance or gold floating in the air . It is for preventing the intrusion of contaminating impurities such as foreign substances and water vapor, and a dense film is preferable. The protective film can be formed as a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon oxynitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film by using a sputtering method. In this embodiment, an example of forming the protective film by a sputtering method is shown, but it is not particularly limited and other methods may be used.

[0202] In this embodiment, an insulating layer 4020 having a laminated structure is formed as the protective film. Here, as the first layer of the insulating layer 4020, a silicon oxide film is formed by using a sputtering method. When a silicon oxide film is used as the protective film, it is effective in preventing hillocks in the aluminum films used as the source electrode layer and the drain electrode layer.

[0203] Also, as the second layer of the protective film, a silicon nitride film is formed by using a sputtering method. When a silicon nitride film is used as the protective film, it is possible to suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change of the electrical characteristics of the transistor.

[0204] Note that, after forming the protective film, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed.

[0205] Also, an insulating layer 4021 is formed as a planarization insulating film. For the insulating layer 4021, heat-resistant organic materials such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass etc. can be used. Note that a plurality of insulating films formed of these materials may be laminated to form the insulating layer 4021. to form the insulating layer 4021.

[0206] Note that the siloxane-based resin is a resin containing an Si—O—Si bond formed using a siloxane-based material as a starting material. Organic groups (for example, an alkyl group or an aryl group) or a fluoro group may be used as a substituent of the siloxane-based resin. Further, the organic group may have a fluoro group. Note that the siloxane-based resin is a resin containing an Si—O—Si bond formed using a siloxane-based material as a starting material. Organic groups (for example, an alkyl group or an aryl group) or a fluoro group may be used as a substituent of the siloxane-based resin. Further, the organic group may have a fluoro group. to form the insulating layer 4021. to form the insulating layer 4021.

[0207] The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced. The method for forming the insulating layer 4021 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. When the insulating layer 4021 is formed of a liquid material, annealing (300°C or higher and 400°C or lower) of the oxide semiconductor layer may be performed simultaneously in the baking step. By combining the baking step of the insulating layer 4021 and the annealing of the oxide semiconductor layer, the number of steps can be reduced.

[0208] For the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, etc. can be used. For the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, etc. can be used. For the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, etc. can be used. For the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, etc. can be used. For the pixel electrode layer 4030 and the counter electrode layer 4031, a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, etc. can be used.

[0209] Further, the pixel electrode layer 4030 and the counter electrode layer 4031 are formed of a conductive polymer (also referred to as a conductive polymer). It can be formed using a conductive composition containing (hereinafter referred to as). Formed using a conductive composition The pixel electrode thus obtained preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 7 0% or more at a wavelength of 550 nm. Further, the resistivity of the conductive polymer contained in the conductive composition is Preferably 0.1 Ω·cm or less.

[0210] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example Polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or Its derivatives, or copolymers of two or more of these can be mentioned.

[0211] In addition, various signals and potentials supplied to the separately formed signal line drive circuit 4003, the scan line drive circuit 4004 or the pixel portion 4 002 are supplied via the FPC 4018.

[0212] In this embodiment, the connection terminal electrode 4015 is formed of the same conductive film as the pixel electrode layer 40 30 of the liquid crystal element 4013, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011.

[0213] The connection terminal electrode 4015 is electrically connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019.

[0214] Also, in FIG. 20, an example in which the signal line drive circuit 4003 is mounted on the first substrate 4001 is shown. However, this embodiment is not limited to this configuration, and only a part of the scan line drive circuit, the signal line drive circuit, or only a part of the scan line drive circuit may be mounted.

[0215] FIG. 21 shows an example of a liquid crystal display module using the substrate 2600 on which the transistors shown in Embodiments 1 and 2 are formed. It shows an example of constructing a liquid crystal display module.

[0216] FIG. 21 is an example of a liquid crystal display module, in which a substrate 2600 and a counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including transistors and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB system, coloring layers corresponding to each of the colors red, green, and blue are provided corresponding to each pixel. Outside the substrate 2600 and the counter substrate 2601 polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the substrate 2600 by a flexible wiring board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer in a state of having.

[0217] In the liquid crystal display module, there are TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liq n-Plane-Switching) mode, FFS (Fringe Field S witching) mode, MVA (Multi-domain Vertical A lignment) mode, PVA (Patterned Vertical Alig nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liq uid Crystal) mode, AFLC (AntiFerroelectric L iquid Crystal) mode, etc. can be used.

[0218] As described above, a highly reliable liquid crystal display panel can be configured.

[0219] Note that the configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. It is assumed that it can be used.

[0220] (Embodiment 5) In this embodiment, an example of an electronic paper is shown as a display device to which the transistors shown in Embodiments 1 and 2 are applied. An example of an electronic paper is shown.

[0221] FIG. 13 shows an active matrix type electronic paper as an example of a display device. As the transistor 581 used in the display device, the transistors shown in Embodiments 1 and 2 can be applied. It can be applied.

[0222] The electronic paper in FIG. 13 is an example of a display device using a twist ball display method. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer, generating a potential difference between the first electrode layer and the second electrode layer, and controlling the orientation of the spherical particles. It is a method of performing display by controlling the orientation of the spherical particles.

[0223] The transistor 581 is a transistor having a bottom gate structure, and a source electrode layer or a drain electrode layer is electrically connected to the first electrode layer 587 through openings formed in the insulating layers 585, 584, and 583. Between the first electrode layer 587 and the second electrode layer 588, there is , a black region 590a, a white region 590b, and a cavity 594 filled with a liquid A spherical particle 589 including them is provided, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin (see Fig. 13). In the present embodiment, the first electrode layer 587 corresponds to the pixel electrode , and the second electrode layer 588 corresponds to the common electrode. The second electrode layer 588 is electrically connected to a common potential line provided on the same substrate as the transistor 581.

[0224] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules having a diameter of 10 μm or more and 200 μm or less, in which positively charged white fine particles and negatively charged black fine particles are encapsulated, are used. The microcapsules provided between the first electrode layer and the second electrode layer are such that when an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions to each other, and white or black can be displayed. A display element applying this principle is an electrophoretic display element, and a device using the electrophoretic display element is generally called an electronic paper. Since the electrophoretic display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, and also the power consumption is small, and the display portion can be recognized even in a dim place. Also, even when power is not supplied to the display portion, since it is possible to hold an image once displayed, when the display device with a display function (also referred to as a semiconductor device or a semiconductor device including a display device) is separated from a radio wave transmission source even in such a case, it is possible to save the displayed image.

[0225] Note that the configuration shown in the present embodiment can be used in appropriate combination with the configuration shown in other embodiments. ​

[0226] (Embodiment 6) In this embodiment, a light-emitting display device using the transistors shown in Embodiments 1 and 2 will be described as an example of the display device. As the display element included in the display device, a light-emitting element using electroluminescence will be described here. The light-emitting element using electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element. When a voltage is applied to the organic EL element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0227] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element structure. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission using inner-shell electron transition of metal ions. Here, an organic EL element will be described as the light-emitting element. FIG. 18 shows a digital clock display device using the organic EL element as the light-emitting element.

[0228] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element structure. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and its light-emitting mechanism is localized light emission using inner-shell electron transition of metal ions. Here, an organic EL element will be described as the light-emitting element. FIG. 18 shows a digital clock display device using the organic EL element as the light-emitting element. Here, an organic EL element will be described as the light-emitting element. FIG. 18 shows a digital clock

[0229] Here, an organic EL element will be described as the light-emitting element. FIG. 18 shows a digital clock This is a diagram showing an example of a pixel configuration to which intermediate gradation driving can be applied.

[0230] The configuration and operation of a pixel to which digital time gradation driving can be applied will be described. Here shows an example in which two n-channel type transistors using an oxide semiconductor layer as a channel formation region, as shown in Embodiments 1 and 2, are used in one pixel.

[0231] Pixel 6400 has a switching transistor 6401, a driving transistor 6402, a light emitting element 6404, and a capacitive element 6403. The switching transistor 64 01 has its gate connected to the scanning line 6406, its first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and its second electrode (the other of the source electrode and the drain electrode) connected to the gate of the driving transistor 6402. The driving transistor 6402 has its gate connected to the power supply line 6407 via the capacitive element 6403, its first electrode connected to the power supply line 64 07, and its second electrode connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate. Note that a low power supply potential is set for the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a potential lower than the high power supply potential set for the power supply line 6407, and for example, GND, 0V, etc. may be set as the low power supply potential. By applying the potential difference between this high power supply potential and the low power supply potential to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light, the

[0232] potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 to cause a current to flow through the light emitting element 6404 and make the light emitting element 6404 emit light. Therefore, the Set each potential so that the potential difference becomes equal to or higher than the voltage required for the light emission of the light-emitting element 6404. Do.

[0233] Note that the capacitor element 6403 can also be omitted by substituting for the gate capacitance of the driving transistor 6402. Regarding the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode. Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or fully off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. To operate the driving transistor 6402 in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405.

[0234] Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or fully off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. To operate the driving transistor 6402 in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. That is, the driving transistor 6402 operates in the linear region. Since the driving transistor 6402 operates in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or fully off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. (Power supply line voltage + Vth of the driving transistor 6402) or higher voltage is applied.

[0235] Also, when performing analog gradation driving instead of digital time gradation driving, the same pixel configuration as in FIG. 18 can be used by changing the signal input. When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light-emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Note that by inputting a video signal such that the driving transistor 6402 operates in the saturation region, current can flow through the light-emitting element 6404.

[0236] When performing analog gradation driving, a voltage equal to or higher than the forward voltage of the light-emitting element 6404 + the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. The forward voltage of the light-emitting element 6404 refers to the voltage when a desired luminance is set, and includes at least the forward threshold voltage. Here, in the case of the voltage input voltage driving method, a video signal that causes the driving transistor 6402 to be in one of two states, either fully on or fully off, is input to the gate of the driving transistor 6402. That is, the driving transistor 6402 operates in the linear region. To operate the driving transistor 6402 in the linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage equal to or higher than (the power supply line voltage + the Vth of the driving transistor 6402) is applied to the signal line 6405. To operate the switch 6402 in the saturation region, the potential of the power supply line 6407 is made higher than the gate potential of the driving transistor 6402. By using an analog video signal, a current corresponding to the video signal can be passed through the light-emitting element 6404, and analog gradation driving can be performed.

[0237] Note that the pixel configuration shown in FIG. 18 is not limited to this. For example, a new switch, resistor element, capacitor element, transistor, or logic circuit, etc. may be added to the pixel shown in FIG. 18. .

[0238] Next, the configuration of the light-emitting element will be described with reference to FIG. 19. Here, the case where the driving transistor is of the n-type will be taken as an example to describe the cross-sectional structure of the pixel. In FIGS. 19(A), (B) , (C), the transistors 7001, 7011, 7021 used in the display device can be the transistors described in Embodiments 1 and 2.

[0239] For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. For example, there are an upper surface emission structure that extracts light from the surface opposite to the substrate on which the transistor is formed, and a lower surface emission structure that extracts light from the surface on the substrate side . There is also a light-emitting element having a double-sided emission structure combining them, and the pixel configuration of the present invention can be used for light-emitting elements of any emission structure. The light-emitting element with the lower surface emission structure will be described with reference to FIG. 19(A).

[0240] A cross-sectional view of the pixel when the transistor 7011 is of the n-type and the light emitted from the light-emitting element 7012 is emitted to the first electrode 701

[0241] 3 side is shown. In FIG. 19(A), the transistor 7011 On a light-transmissive conductive layer 7017 electrically connected to a drain electrode layer, a first electrode 7013 of a light-emitting element 7012 is formed, and an EL layer 7014 and a second electrode 7015 are sequentially laminated on the first electrode 7013.

[0242] As the light-transmissive conductive layer 7017, an indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmissive conductive films can be used.

[0243] Also, various materials can be used for the first electrode 7013 of the light-emitting element. For example, when the first electrode 7013 is used as a cathode, materials with a relatively small work function, such as alkali metals (Li, Cs, etc.), alkaline earth metals (Mg, Ca, Sr, etc.), alloys containing alkali metals or alkaline earth metals (Mg:Ag, Al:Li, etc.), or rare earth metals such as Yb and Er are preferred. In FIG. 19(A), the film thickness of the first electrode 7013 is set to a level that allows light to pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm is used as the first electrode 7013.

[0244] Note that after laminating and forming a light-transmissive conductive film and an aluminum film, they may be selectively etched to form the light-transmissive conductive layer 7017 and the first electrode 7013. In this case, etching can be performed using the same resist mask.

[0245] Also, the peripheral portion of the first electrode 7013 is covered with a partition wall 7019. The It is formed using an organic resin film such as a polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. When a photosensitive resin material is used as the partition wall 7019, the process of forming a resist mask can be omitted.

[0246] In addition, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 may include at least a light-emitting layer, and is not limited to a single layer, and may be composed of a stack of multiple layers. When the EL layer 7014 is composed of multiple layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the first electrode 7013 that functions as a cathode. Note that it is not necessary to provide all the layers other than the light-emitting layer among these.

[0247] In addition, it is not limited to the above stacking order. The first electrode 7013 may function as an anode, and a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order on the first electrode 7013. However, it is better to stack an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the first electrode 7013 that functions as a cathode, which can suppress the voltage rise of the drive circuit unit and reduce the power consumption.

[0248] In addition, various materials can be used as the second electrode 7015 formed on the EL layer 7014. For example, when the second electrode 7015 is used as an anode, materials with a relatively large work function, such as ZrN, Ti, W, Ni, Pt, Cr, etc., or transparent conductive materials such as ITO, IZO, ZnO are preferable. Also, as the shielding film 7016 on the second electrode 7015, a metal that blocks light, a metal that reflects light, or the like is used. In this embodiment, the second ​​​​​​​​​​​​​Use an ITO film as the electrode 7015 and a Ti film as the shielding film 7016.

[0249] The region where the first electrode 7013, the EL layer 7014, and the second electrode 7015 are laminated corresponds to the light-emitting element 7012. In the case of the element structure shown in Fig. 19(A), the light-emitting element 7012 emits light that is emitted toward the first electrode 7013 side as indicated by the arrow.

[0250] In Fig. 19(A), the light emitted from the light-emitting element 7012 passes through the color filter layer 7033, passes through the insulating layer 7032, the oxide insulating layer 7031, the gate insulating layer 7030, and the substrate 7010 and is emitted.

[0251] The color filter layer 7033 can be formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using photolithography technology, or the like.

[0252] In addition, the color filter layer 7033 is covered with an overcoat layer 7034 and a protective insulating layer 7035 In Fig. 19(A), the overcoat layer 7034 is shown with a thin film thickness, but it also has a function of flattening the unevenness caused by the color filter layer 7033. Note that the overcoat layer 7034 can be formed of a resin material such as an acrylic resin.

[0253] In addition, the contact holes that reach the drain electrode layer formed in the protective insulating layer 7035, the overcoat layer 7034, the color filter layer 7033, the insulating layer 7032, and the oxide insulating layer 7031 are arranged at positions overlapping the partition wall 7019.

[0254] Next, a light-emitting element having a double-sided emission structure will be described with reference to Fig. 19(B).

[0255] In FIG. 19(B), a light-transmitting conductive layer electrically connected to the drain electrode layer of the transistor 7021 has, on it, a first electrode 7023, an EL layer 7024, , and a second electrode 7025 included in the light-emitting element 7022 laminated in this order.

[0256] As the light-transmitting conductive layer 7027, a light-transmitting conductive film such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used. In addition, various materials can be used for the first electrode 7023. For example, when the first electrode 7 023 is used as a cathode, materials with a relatively small work function, such as alkali metals (Li, Cs, etc.), alkaline earth metals (Mg, Ca, Sr, etc.), alloys containing alkali metals or alkaline earth metals (Mg:Ag, Al:Li, etc.), or rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as a cathode, and its film thickness is set to a degree that allows light to pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a thickness of 20 nm is used as the first electrode 7023.

[0257] After laminating and forming the light-transmitting conductive film and the aluminum film, they may be selectively etched to form the light-transmitting conductive layer 7027 and the first electrode 7023. In this case, etching can be performed using the same resist mask.

[0258]

[0259] ​​​​​​​​​The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. When a photosensitive resin material is used for the partition wall 7029, a resist mask is used. Therefore, the step of forming a mask can be omitted.

[0260] The EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 is at least As long as it includes a light-emitting layer, it is not limited to a single layer and may be composed of a laminate of multiple layers. When the electrode 7024 is made of multiple layers, the electrode 7024 is placed on the first electrode 7023 which acts as a cathode. The electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are laminated in this order. Of these layers, it is not necessary to provide all layers other than the light-emitting layer.

[0261] In addition, the stacking order is not limited to the above. The first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order. The first electrode 7023 functions as a cathode, and an electron injection layer and an electron The voltage of the drive circuit is reduced by stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order. This can suppress the rise in temperature and reduce power consumption.

[0262] In addition, the second electrode 7025 formed on the EL layer 7024 can be made of various materials. For example, when the second electrode 7025 is used as an anode, the work function is relatively It is preferable to use a transparent conductive material such as ITO, IZO, or ZnO. In this embodiment, the second electrode 7025 is used as an anode, and the second electrode 7025 is made of a material containing silicon oxide. An ITO film is formed.

[0263] The region where the first electrode 7023, the EL layer 7024, and the second electrode 7025 are laminated is corresponding to the light-emitting element 7022. In the case of the element structure shown in FIG. 19(B), the light-emitting element 7022 emits light to both the second electrode 7025 side and the first electrode 7023 side as indicated by the arrows. Both are emitted.

[0264] In addition, in FIG. 19(B), one of the lights emitted from the light-emitting element 7022 to the first electrode 7023 side passes through the color filter layer 7043, and is emitted through the insulating layer 7042, the oxide insulating layer 704 1, the first gate insulating layer 7040, and the substrate 7020.

[0265] The color filter layer 7043 can be formed by a droplet discharge method such as an inkjet method, a printing method, an etching method using a photolithography graphy technique, or the like.

[0266] In addition, the color filter layer 7043 is covered with an overcoat layer 7044 and a protective insulating layer 7045. It is covered.

[0267] In addition, the contacts reaching the drain electrode layer formed on the protective insulating layer 7045, the overcoat layer 7044, the color filter layer 7043, the insulating layer 7042, and the oxide insulating layer 7041 holes are arranged at positions overlapping the partition wall 7029. However, when using a light-emitting element with a double-sided emission structure and making both display surfaces full-color displays,

[0268] since the light from the second electrode 7025 side does not pass through the color filter layer 7043, it is preferable to provide a sealing substrate with a separate color filter layer above the second electrode 7025. filter layer above the second electrode 7025.

[0269] Next, the light-emitting element with the top surface injection structure will be described with reference to Fig. 19(C).

[0270] In Fig. 19(C), the first electrode 7003 of the light-emitting element 7002 electrically connected to the drain electrode layer of the transistor 7001 is formed, and the EL layer 7004 and the second electrode 7005 are sequentially laminated on the first electrode 7003.

[0271]

[0272]

[0273]

[0274] ​​​​​​​​​​​​​​​​Further, it is not limited to the above stacking order, and a hole injection layer may be formed on the first electrode 7003 used as an anode. A hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer may be stacked in this order.

[0275] In this embodiment, on a stacked film formed by stacking a titanium film, an aluminum film, and a titanium film in this order, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer are stacked in this order, and a stack of an Mg:Ag alloy thin film and ITO is formed thereon.

[0276] However, when the transistor 7001 is of the n-type, stacking an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer in this order on the first electrode 7003 can suppress the voltage rise in the driving circuit and reduce the power consumption.

[0277] The second electrode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide added with silicon oxide, or the like may be used as the light-transmitting conductive film.

[0278] The region where the first electrode 7003, the EL layer 7004, and the second electrode 7005 are stacked corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 19(C), the light emitted from the light-emitting element 7002 is emitted toward the second electrode 7005 as indicated by the arrow.

[0279] Further, the drain electrode layer of the transistor 7001 is an oxide insulating layer 7051, a protective insulating layer 7 It is electrically connected to the first electrode 7003 through the contact hole provided in the 052 and the insulating layer 7055. Electrically connect.

[0280] The planarization insulating layer 7053 can use resin materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above resin materials, low dielectric constant materials ( low-k materials), siloxane-based resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can be used. Note that the planarization insulating layer 7053 may be formed by laminating a plurality of insulating films formed of these materials. The method for forming the planarization insulating layer 7053 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. not particularly limited, and depending on the material, sputtering, SOG, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. can be used.

[0281] Also, a partition wall 7009 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition wall 7009 is formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane. When a photosensitive resin material is used as the partition wall 7009, the step of forming a resist mask can be omitted. When a photosensitive resin material is used as the partition wall 7009, the step of forming a resist mask can be omitted.

[0282] Also, when performing full-color display in the structure of FIG. 19(C), for example, the light-emitting element 70 02 is a green light-emitting element, one adjacent light-emitting element is a red light-emitting element, and the other adjacent light-emitting element is a blue light-emitting element. In addition to these three types of light-emitting elements, a light-emitting display device capable of full-color display using four types of light-emitting elements including a white element may be manufactured.

[0283] Also, all of the plurality of light-emitting elements to be arranged are white light-emitting elements, and a sealing substrate having a color filter or the like is arranged above the light-emitting element 7002, and a light-emitting display device capable of full-color display may be manufactured. A material that exhibits single-color light emission such as white is formed, and full-color display can be performed by combining a color filter and a color conversion layer.

[0284] Of course, single-color light emission display may be performed. For example, an illumination device may be formed using white light emission, or an area color type light-emitting device may be formed using single-color light emission.

[0285] Also, if necessary, an optical film such as a polarizing film such as a circular polarizing plate may be provided.

[0286] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic E L element as the light-emitting element.

[0287] In addition, an example in which a transistor that controls the driving of the light-emitting element is electrically connected to the light-emitting element has been shown, but a configuration in which a current control transistor is connected between the transistor and the light-emitting element may also be used.

[0288] Note that the display device shown in this embodiment is not limited to the configuration shown in FIG. 19, and various modifications based on the technical idea of the present invention are possible.

[0289] Next, the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the display device to which the transistors shown in Embodiments 1 and 2 are applied will be described with reference to FIG. 22. FIG. 22 shows the transistors and light-emitting elements formed on the first substrate between the first substrate and the second substrate . is a top view of a panel sealed with a sealing material, and FIG. 22(B) corresponds to the cross-sectional view taken along the line H-I in FIG. 22(A). -I.

[0290] A pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b provided on a first substrate 4501 are surrounded by a sealing material 4505. Also, a second substrate 4506 is provided over the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b. Thus, the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b are sealed together with a filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it is preferably packaged (enclosed) with a highly airtight and low outgassing protective film (such as a bonding film, an ultraviolet curable resin film, etc.) or a cover material so as not to be exposed to the outside air. Further, the pixel portion 4502, signal line driving circuits 4503a, 4503b, and scanning line driving circuits 4504a, 4504b provided on the first substrate 4501 have a plurality of transistors. In FIG. 22(B), the transistor 4510 included in the pixel portion 4502 and the transistor 4509 included in the signal line driving circuit 4503a are illustrated. To the transistors 4509 and 4510, the transistors shown in highly reliable Embodiments 1 and 2 including an In-Ga-Zn-O-based film as an oxide semiconductor layer can be applied. In this embodiment, the transistors 4509 and 4510 are n-channel transistors.

[0291]

[0292] ​​​​​​​​​​​​​

[0293] On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state. On the insulating layer 4544, at a position overlapping with the channel formation region of the oxide semiconductor layer of the transistor 4509 for the drive circuit, a conductive layer 4540 is provided. By providing the conductive layer 4540 at a position overlapping with the channel formation region of the oxide semiconductor layer, the change amount of the threshold voltage of the transistor 4509 before and after the BT test can be reduced. Also, by setting the conductive layer 4540 to the same potential as the gate electrode layer of the transistor 4509, it can also function as a second gate electrode layer. Further, a potential different from the gate electrode layer of the transistor 4509 may be applied to the conductive layer 4540. Also, the potential of the conductive layer 4540 may be GND, 0V, or in a floating state.

[0294] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like. Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. Note that the configuration of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but it is not limited to the configuration shown in this embodiment. The configuration of the light-emitting element 4511 can be appropriately changed according to the direction of the light extracted from the light-emitting element 4511 and the like.

[0295] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. The partition wall 4520 is preferably formed on the first electrode layer 4517 using a photosensitive material so that the side wall has an inclined surface with a curvature. The partition wall 4520 is preferably formed on the first electrode layer 4517 using a photosensitive material so that the side wall has an inclined surface with a curvature.

[0296] The electroluminescent layer 4512 is not limited to a single layer and may be composed of a stack of multiple layers.

[0297] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon oxide nitride film, a DLC film, etc.

[0298] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0299] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source and drain electrode layers in the second transistor 10 are formed from the same conductive film as those in the second transistor 10.

[0300] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0301] The substrate located in the direction in which light is extracted from the light emitting element 4511 must have light transmitting properties. In that case, glass plates, plastic plates, polyester films or acrylics A light-transmitting material such as a film is used.

[0302] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used .

[0303] Also, if necessary, an optical film such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element . Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection .

[0304] The signal line driving circuits 4503a and 4503b and the scanning line driving circuits 4504a and 4504b may be those in which a driving circuit formed of a separately formed single-crystalline semiconductor or polycrystalline semiconductor is mounted . Further, only the signal line driving circuit, only the scanning line driving circuit, or only a part of them may be separately formed and mounted, and this embodiment is not limited to the configuration shown in FIG. 22 .

[0305] Through the above steps, a highly reliable light-emitting display device (display panel) can be configured

[0306] Note that the configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments .

[0307] (Embodiment 7) The display device to which the transistors shown in Embodiments 1 and 2 are applied can be used for an electronic paper . The electronic paper can be used in electronic devices in any field as long as it can display information . For example, using the electronic paper, electronic books (e-books), posters , in-vehicle advertisements in vehicles such as trains, and displays on various cards such as credit cards, etc It can be applied. An example of an electronic device is shown in FIGS. 11 and 12.

[0308] FIG. 11(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper print, the advertisement is replaced manually, but if electronic paper is used, the advertisement display can be changed in a short time. Note that the poster 2631 may be configured to be able to wirelessly transmit and receive information.

[0309] Also, FIG. 11(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper print, the advertisement is replaced manually, but if electronic paper is used, the advertisement display can be changed in a short time without much labor. Also, a stable image can be obtained without the display being disrupted. Note that the in-vehicle advertisement may be configured to be able to wirelessly transmit and receive information.

[0310] Also, FIG. 12 shows an example of an e-book. For example, the e-book 2700 is composed of two housings, a housing 27 01 and a housing 2703. The housing 2701 and the housing 270 3 are integrated by a shaft portion 2711, and can perform an opening and closing operation around the shaft portion 2711. With such a configuration, it becomes possible to operate in a form similar to browsing a paper book.

[0311] A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portion 2705 and the display portion 2707 may be configured to display a continuous screen, or may be configured to display different screens. With a configuration of displaying different screens, for example, a text is displayed on the right display portion (display portion 2705 in FIG. 12), and the left display portion (display portion 2707 in FIG. 12) may display an image or the like. An image can be displayed on the display unit 2707 (shown in FIG. 12).

[0312] Also, FIG. 12 shows an example in which the housing 2701 is provided with an operation unit or the like. For example, in the housing 2 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. are provided. . Pages can be sent by the operation keys 2723. Note that a key board, a pointing device, etc. may be provided on the same surface as the display unit of the housing. Also, a configuration in which external connection terminals (terminals connectable to various cables such as earphone terminals, USB terminals, or an AC adapter and a USB cable), a recording medium insertion part, etc. are provided on the back surface or side surface of the housing may be adopted. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0313]

[0314] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0315] (Embodiment 8) The display device using the transistors shown in Embodiments 1 and 2 can be applied to various electronic devices (including gaming machines). Examples of electronic devices include a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (mobile phone, mobile phone), etc. (also referred to as a telephone device), a portable game machine, a portable information terminal, an audio playback device, a pachinko machine, etc. Examples include large game machines.

[0316] FIG. 23(A) shows an example of a television device. The television device 9600 has a display unit 9603 incorporated in a housing 9601. The display unit 9603 can display video. Here, a configuration is shown in which the housing 9601 is supported by a stand 9605.

[0317] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control operation device 9610. The operation keys 9609 provided on the remote control operation device 9610 can be used to switch channels and adjust the volume, and can also be used to operate the video displayed on the display unit 9603. Further, the remote control operation device 9610 may be configured to include a display unit 9607 for displaying information output from the remote control operation device 9610.

[0318] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and can further be connected to a communication network by wire or wirelessly via the modem to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers) information communication.

[0319] FIG. 23(B) shows an example of a digital photo frame. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 970 3 can display various images, such as images taken with a digital camera, etc. By displaying the data, it can function in the same way as a normal photo frame.

[0320] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (such as USB terminals, various cable connection terminals like USB cables), a recording medium insertion part, etc. It is configured to be composed of these. These configurations may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because it improves the design. For example, an image data memory storing image data taken with a digital camera can be inserted into the recording medium insertion part of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

[0321] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0322] FIG. 24(A) shows a portable game machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected in an openable and closable manner by a connecting part 9893. A display unit 9882 is incorporated in the casing 9881, and a display unit 9883 is incorporated in the casing 9891. Also, the portable game machine shown in FIG. 24(A) also includes, among other things, a speaker part 9884, a recording medium insertion part 988 6, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration ​​9889) that includes a function to measure motion, odor, or infrared rays, a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the display device according to the present invention is included, and other auxiliary equipment is appropriately provided. The portable game machine shown in FIG. 24(A) can read and write programs recorded on a recording medium. It has the function of reading the RAM or data and displaying it on the display, and wireless communication with other portable gaming machines. The portable gaming machine shown in FIG. 24(A) has a function of sharing information. The functions are not limited to these, and may have a variety of functions.

[0323] FIG. 24(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and it is sufficient that the display device according to the present invention is included. can be appropriately provided.

[0324] FIG. 25A shows an example of a mobile phone. The mobile phone 1000 has a housing 1001. In addition to the display unit 1002, the operation buttons 1003, the external connection port 1004, It is equipped with a speaker 1005, a microphone 1006, etc.

[0325] The mobile phone 1000 shown in FIG. 25A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making calls and sending and receiving e-mails can be performed by using the display unit 1002. It can be performed by touching with a finger or the like.

[0326] There are mainly three modes on the screen of the display unit 1002. The first is the display mode mainly for displaying images. The second is the input mode mainly for inputting information such as characters. The third is the display + input mode in which the two modes of the display mode and the input mode are mixed. For example, when making a phone call or creating an email, the display unit 1002 may be set to the character input mode mainly for character input, and an input operation for the characters displayed on the screen may be performed.

[0327] For example, when making a phone call or creating an email, set the display unit 1002 to the character input mode mainly for character input, and perform an input operation on the characters displayed on the screen. For example, when making a phone call or creating an email, set the display unit 1002 to the character input mode mainly for character input, and perform an input operation on the characters displayed on the screen.

[0328] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched. Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched. Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0329] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode. Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode. Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode. Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0330] Also, in the input mode, when the signal detected by the optical sensor of the display unit 1002 is detected and there is no touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode. Also, in the input mode, when the signal detected by the optical sensor of the display unit 1002 is detected and there is no touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode. Also, in the input mode, when the signal detected by the optical sensor of the display unit 1002 is detected and there is no touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0331] The display unit 1002 can also function as an image sensor. For example, the display unit 10 By touching 02 with the palm or fingers and imaging palm prints, fingerprints, etc., personal authentication can be performed. In addition, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used in the display unit, it is also possible to image finger veins, palm veins, etc.

[0332] Figure 25(B) is also an example of a mobile phone. The mobile phone in Figure 25(B) includes a display device 9410 including a housing 9411, a display unit 9412, and operation buttons 9413, and a housing 9401 with operation buttons 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and a light-emitting unit 9406 that emits light when there is an incoming call, and has a communication device 9400. The display device 9410 having a display function is detachable in two directions of the arrow from the communication device 9400 having a telephone function. Therefore, it is possible to attach the short axes of the display device 9410 and the communication device 9400 to each other, or attach the long axes of the display device 9410 and the communication device 9400 to each other. Also, when only the display function is required, the display device 9410 can be removed from the communication device 9400, and the display device 9 410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each has a rechargeable battery.

[0333] Note that the configurations shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0334] (Embodiment 9) When an oxide semiconductor layer contacts a metal layer or an oxide insulating layer, a phenomenon occurs in which oxygen moves. In this embodiment, regarding the difference between the case where the oxide semiconductor layer is amorphous and the case where it is crystalline, the above ​​​​​​Explain the results of scientific calculations on phenomena.

[0335] FIG. 33 illustrates a structure of a transistor according to one embodiment of the present invention, in which an oxide semiconductor layer and a source A state in which the metal layer that will become the electrode and drain electrode, the oxide semiconductor layer, and the oxide insulating layer are in contact with each other. The arrows in the figure indicate the direction of the contact or heating state. Each indicates the direction of oxygen movement.

[0336] When oxygen vacancies occur in an i-type oxide semiconductor layer, the layer exhibits n-type conductivity. The oxide semiconductor layer, which is n-type due to vacancies, becomes i-type when oxygen is supplied in excess. In actual device processes, this effect is utilized, and the metals that become the source and drain electrodes are In the oxide semiconductor layer in contact with the metal layer, oxygen is attracted to the metal side, and part of the contact area (film If the thickness is too thin, oxygen vacancies occur throughout the entire thickness, causing the layer to become n-type and providing good contact with the metal layer. In addition, the oxide semiconductor layer in contact with the oxide insulating layer can be formed by removing the oxide from the oxide insulating layer. When oxygen is supplied, a part of the contact area (or the entire thickness direction if the film is thin) becomes oxygen-excessive. This makes the region i-type and functions as a channel formation region of the transistor.

[0337] In one embodiment of the present invention, a metal layer which is to be an oxide semiconductor layer and a source electrode and a drain electrode is provided. A crystalline region of the oxide semiconductor is formed in the region where the oxide semiconductor layer and the oxide insulating layer contact each other. Therefore, the region in contact with the metal layer or the oxide insulating layer is an amorphous oxide semiconductor. The oxygen transport patterns were verified by scientific calculations to see how they differed from those in the case of a layer.

[0338] The model used for the scientific calculations is a rectangular parallelepiped of In-Ga-Zn-O system amorphous and crystalline structure. Calculation using a material with a 10% oxygen deficiency in the area on one side in the longitudinal direction (see Fig. 34). It compares the oxygen distribution after 10 nsec under the acceleration condition of 650°C. Each of these conditions is shown in Table 1 and Table 2.

[0339]

Table 1

[0340]

Table 2

[0341] As the calculation results, the oxygen distribution when using amorphous is shown in Fig. 35(A), and the oxygen distribution when using crystal is shown in Fig. 35(B). The dotted line is the initial (Initial), and the solid line is the result (after 10 n sec). It can be seen that oxygen is moving regardless of whether it is amorphous or crystal from the change in the distribution.

[0342] The increase rate of oxygen atoms before and after the calculation in the region with oxygen deficiency was 15.9% for amorphous and 11.3% for crystal. That is, oxygen moves more easily in amorphous than in crystal, and the result is that it is easier to fill the oxygen deficiency. That is, oxygen moves relatively less easily in crystal than in amorphous.

[0343] Therefore, even in the structure in which the oxide semiconductor layer in one aspect of the present invention has a crystal region, it was confirmed that oxygen moves in the same manner as when the oxide semiconductor layer is amorphous. Also, since oxygen moves relatively less easily in crystal than in amorphous, it was confirmed that there is an effect of suppressing the desorption of oxygen from the oxide semiconductor layer.

[0344] ​​​​​​​Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so. EXAMPLES

[0345] In this embodiment, an oxide semiconductor film was dehydrated or dehydrogenated at high temperature for a short time by an RTA method. The state of the material was analyzed using TEM analysis, TEM-EDX analysis, X-ray diffraction, and SIMS analysis. The results of the analysis will be explained below.

[0346] The sample used for the analysis was an oxide of In2O3:Ga2O3:ZnO=1:1:1 (molar ratio). Using a compound semiconductor film deposition target, an In-Ga-Zn The sample was also heated at 650°C for 6 minutes in a nitrogen gas atmosphere using an RTA device. For comparison, sample A was heated at 450°C in a nitrogen gas atmosphere using an electric furnace for 1 Sample B was heated for 1 h, and sample C was not heated (as-depo). did.

[0347] First, to examine the crystalline state of each sample, a high-resolution transmission electron microscope (Hitachi The cross section was observed at an accelerating voltage of 300 kV using a TEM (H9000-NAR, manufactured by Eppendorf). Figure 26 shows cross-sectional photographs of sample A, Figure 27 shows cross-sectional photographs of sample B, and Figure 28 shows cross-sectional photographs of sample C. In this figure, (A) is a low-magnification photograph (2 million times), and (B) is a high-magnification photograph (4 million times).

[0348] Specimen A, which was heated at 650°C for 6 minutes by the RTA method shown in Figure 26, has the following characteristics in its cross section: A continuous lattice image was observed in the surface layer. In particular, in the high-magnification photograph of Figure 26(B), the area enclosed in a white frame A clear lattice image was observed in the region, suggesting the presence of aligned microcrystals. In the case of heating for a short time of about 6 minutes at 650 °C by the RTA method, the surface layer part of the In-Ga-Zn-O film becomes crystallized and has a crystal region. Except for the surface layer part in other regions, a continuous and clear lattice image is not observed, and microcrystalline particles are confirmed to float in some amorphous regions. The particle size of the microcrystals was 2 nm or more and 4 nm or less, which is a so-called nanocrystal.

[0349] On the other hand, from the cross-sectional photographs of FIG. 27 (sample B) and FIG. 28 (sample C), a clear lattice image is not observed in any region in the film thickness direction, and it is confirmed that it is amorphous.

[0350] FIGS. 29 (A) and (B) show enlarged photographs of the surface layer part of sample A heated at 650 °C for 6 minutes by the RTA method and an electron beam diffraction pattern of the crystal region. In the enlarged photograph of the surface layer part (FIG. 29 (A) ), arrows 1 to 5 indicating the direction in which the lattice images are arranged are shown, and it can be seen that crystals grow in a direction perpendicular to the surface of the film. The electron beam diffraction pattern shown in FIG. 29 (B) is the one observed at the position of arrow number 3, and an orientation in the c-axis direction is confirmed. Further, as a result of comparing this electron beam diffraction pattern with known lattice constants, it was found that the crystal structure is In2Ga2ZnO7 (see FIG. 36).

[0351] FIG. 30 shows the results of TEM-EDX (energy dispersive X-ray spectroscopy) analysis of the cross-section of the surface layer part of sample A. Although a raw material target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 was used , the composition ratio of the surface layer part is such that Zn is 0.3 or more and 0.4 or less with respect to In or Ga being 1, indicating that Zn is slightly deficient.

[0352] ​​​Next, the results of analyzing the crystal state of the same three types of samples by X-ray diffraction are shown in Fig. 31. In the chart of each sample, the peak observed at 2θ = 30 to 36° is information derived from the In-G a-Zn-O-based material, and since it is broad, it reflects an amorphous state. However, for sample A heated at 650 °C for 6 minutes by the RTA method, the peak position is on the lower angle side than that of sample B and sample C, suggesting the presence of diffraction peaks obtained from the (009) plane and (101) plane, which exhibit the strongest diffraction intensity in the In-Ga-Zn-O-based crystalline material. Therefore, it was confirmed that sample A also has a crystal region in the X-ray diffraction method.

[0353] Next, the SIM S (secondary ion mass spectrometry) analysis results for the hydrogen concentration, carbon concentration, and nitrogen concentration in the films of sample A and sample C are shown in Fig. 32. The horizontal axis indicates the depth from the sample surface and the position of the depth 0 nm at the left end corresponds to the outermost surface of the sample (the outermost surface of the oxide semiconductor layer), and the analysis is performed from the surface side.

[0354] Fig. 32(A) shows the hydrogen concentration profile. From the profile of sample A, it was found that the hydrogen concentration decreased by more than one order of magnitude compared to the profile of sample C, and it was confirmed that dehydration or dehydrogenation was effectively performed by heating at 650 °C for 6 minutes by the RTA method. The profiles of sample A and sample C were quantified using a standard sample fabricated with the same In-Ga- Zn-O-based oxide semiconductor layer as the sample.

[0355] Note that, due to its principle, it is known that it is difficult to accurately obtain data in the vicinity of the sample surface and at the interface of a laminated film with different materials in SIMS analysis. In this analysis, the accurate concentration in the film ​​In order to obtain accurate data, the profile was taken from a depth of 15 nm to 35 nm of the film thickness of about 40 nm. The files were the subject of evaluation.

[0356] From the profile of sample C, it was found that hydrogen was approximately 3× 10 20 atoms / cm 3 That's about 5 x 10 20 atoms / cm 3 The average hydrogen concentration is as follows: Approximately 4 x 10 degrees 20 atoms / cm 3 It can be seen that the proton of sample A is included. From the file, it was found that the average hydrogen concentration in the oxide semiconductor layer was reduced to about 2 × 10 by dehydrogenation. 19 at oms / cm 3 It can be seen that the noise level has been reduced to .

[0357] Fig. 32(B) shows the carbon concentration profile, and Fig. 32(C) shows the nitrogen concentration profile. Unlike the hydrogen concentration profile, no clear difference was observed between sample A and sample C. The RTA method was used to measure the desorption or incorporation of carbon and nitrogen components by heating at 650°C for 6 minutes. In addition, the secondary ion intensity of "H" + "O" is shown in Figure 38, and the secondary ion intensity of "H" + "O" is shown in Figure 39. The results show the secondary ion intensity of "H2" + "O". Both are samples treated at high temperatures. The strength of the SiO2 is low, and even when heated at 650°C for 6 minutes using the RTA method, there is no desorption of moisture or OH. was found to be carried out efficiently.

[0358] From the above analysis results, it was found that the sample heated to 650℃ for 6 minutes by RTA method had the following characteristics: It was confirmed that a crystalline region existed in the layer. It was confirmed that the noise level could be reduced to 10 or less. EXAMPLES

[0359] In this embodiment, the results of the -BT test on the transistor fabricated in Embodiment 1 will be described.

[0360] One of the methods for examining the reliability of a transistor is the bias - thermal stress test (hereinafter, referred to as the BT test). The BT test is a type of accelerated test and can evaluate the characteristic changes of a transistor caused by long - term use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT test becomes an important index for examining reliability. The smaller the amount of change in the threshold voltage before and after the BT test, the higher the reliability of the transistor can be said.

[0361] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is maintained constant, the source and drain of the transistor are set to the same potential, and a potential different from that of the source and drain is applied to the gate for a certain period of time. The substrate temperature may be appropriately set according to the test purpose. Also when the potential applied to the gate is higher than the potentials of the source and drain, it is called the +BT test, and when the potential applied to the gate is lower than the potentials of the source and drain, it is called the -BT test.

[0362] The test intensity of the BT test can be determined by the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film is determined by dividing the potential difference between the gate and the source and drain by the film thickness of the gate insulating film. For example, if it is desired to set the electric field strength applied to a gate insulating film with a thickness of 100 nm to 2 MV / cm, the potential difference may be set to 20 V.

[0363] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge within the electrostatic field at a certain point. However, in general, the potential difference between the potential at a certain point and the reference potential (e.g., ground potential) is simply referred to as potential or voltage, and potential and voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, potential may be read as voltage, or voltage may be read as potential. For this reason, in this specification, unless otherwise specified, potential may be read as voltage, or voltage may be read as potential.

[0364] - The BT test was conducted with a substrate temperature of 150°C, an electric field strength applied to the gate insulating film of 2 MV / cm, and an application time of 1 hour. First, to measure the initial characteristics of the transistor to be subjected to the -BT test, the substrate temperature was set to 40°C, the source-drain voltage (hereinafter also referred to as drain voltage or Vd) was set to 1 V,

[0365] and the source-gate voltage (hereinafter also referred to as gate voltage or Vg) was changed from -20 V to +20 V. The change characteristics of the source-drain current (hereinafter also referred to as drain current or Id), that is, the Vg-Id characteristics when Vd is 1 V, were measured. Here, the substrate temperature is set to 40°C as a measure to prevent moisture absorption on the sample surface, but if there are no particular problems, the measurement may be performed with the substrate temperature at room temperature ( 25°C). Next, with Vd set to 10 V, the same measurement was performed to measure the Vg-Id characteristics when Vd is 10 V. Then, after raising the substrate temperature to 150°C, the voltages of the source and drain of the transistor were measured. Here, the substrate temperature is set to 40°C as a measure to prevent moisture absorption on the sample surface, but if there are no particular problems, the measurement may be performed with the substrate temperature at room temperature ( 25°C).

[0366] Next, with Vd set to 10 V, the same measurement was performed to measure the Vg-Id characteristics when Vd is 10 V. Then, after raising the substrate temperature to 150°C, the voltages of the source and drain of the transistor

[0367] were measured. The electric field strength applied to the gate insulating film was then set to 2 MV / cm. A voltage was applied to the gate. Here, the thickness of the gate insulating film of the transistor is 100 nm. Therefore, -20V was applied to the gate and held there for 1 hour. Although the time is set to 1 hour, the time may be changed depending on the purpose.

[0368] Next, while keeping the voltage applied to the gate, source, and drain, the substrate temperature was lowered to 40°C. If the voltage application is stopped before the substrate temperature drops completely, the residual heat -The voltage should not be applied because the damage done to the transistor during the BT test would be repaired. After the substrate temperature reaches 40°C, the voltage application is stopped. Strictly speaking, the temperature drop time must be added to the application time, but in practice, the temperature rise to 40°C in a few minutes. Since this was considered to be within the margin of error, the temperature drop time was added to the application time. do not have.

[0369] Next, under the same conditions as the measurement of the initial characteristics, the Vg-Id characteristics were measured when Vd was 1 V and 10 V. The Vg-Id characteristics after the -BT test were obtained.

[0370] FIG. 37(A) shows the Vg-Id characteristics of the transistor before and after the -BT test. The horizontal axis of (A) is the gate voltage (Vg), and the vertical axis is the drain current (Id) versus gate voltage. is shown on a logarithmic scale.

[0371] FIG. 37B is an enlarged view of the portion 900 shown in FIG. 37A. The initial characteristic 901 is , Vg-Id characteristics of the transistor before the -BT test when Vd is 1V. 1 shows the Vg-Id characteristics of the transistor before the -BT test when Vd is 10V. Also, -BT902 shows the Vg-Id characteristics of the transistor after the -BT test when Vd is 1V, and -BT912 shows the Vg-Id characteristics of the transistor after the -BT test when Vd is 10V.

[0372] From FIG. 37, it can be seen that -BT902 and -BT912 are slightly shifted in the positive direction as a whole compared to the initial characteristics 901 and initial characteristics 911. However, the shift amount is only slightly less than 0.5V, and it was confirmed that the transistor fabricated in Embodiment 1 is a highly reliable transistor in the -BT test.

Explanation of Symbols

[0373] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input Terminal 22 Input Terminal 23 Input Terminal 24 Input Terminal 25 Input Terminal 26 Output Terminal 27 Output Terminal 28 Transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor ​​​51 Power cord 52 Power cord 53 Power cord 61 Period 62 Period 100 Substrate 101 Gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 106 Crystal region 107 Oxide insulating layer 108 Capacitor wiring 110 Pixel electrode layer 112 Conductive layer 113 Conductive layer 114 Conductive layer 120 Connection electrode 121 Terminal 122 Terminal 125 Contact hole 126 Contact hole 127 Contact hole 128 Transparent conductive layer 129 Transparent conductive layer 131 Resist mask 150 Connection electrode 151 Terminal 152 Gate insulating layer 153 Connection electrode 154 Protective insulating film 155 Transparent conductive layer 156 Terminal 170 Transistor 581 Transistor 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 900 Site 901 Initial characteristics 902 -BT 911 Initial characteristics 912 -BT 1000 Mobile phone 1001 Housing 1002 Display unit 1003 Operation button 1004 External connection port 1005 Speaker 1006 Microphone 105a Source electrode layer 105b Drain electrode layer 112a Conductive layer 113a Conductive layer 114a Conductive layer 2600 Substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Coloring layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2631 Poster 2632 In-vehicle advertisement 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft portion 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4040 Conductive layer 4044 Insulating layer 4501 Substrate 4502 Pixel portion 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Partition wall 4540 Conductive layer 4544 Insulating layer 5300 Substrate 5301 Pixel portion 5302 Scanning line drive circuit 5303 Scanning line drive circuit 5304 Signal line drive circuit 5305 Timing control circuit 5601 Shift register 5602 Switching circuit 5603 Transistor 5604 Wiring 5605 Wiring 590a Black region 590b White region 6400 Pixel 6401 Switching transistor 6402 Driving transistor 6403 Capacitive element 6404 Light-emitting element 6405 Signal line 6406 Scanning line 6407 Power supply line 6408 Common electrode 7001 Transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Partition wall 7010 Substrate 7011 Transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding film 7017 Transparent conductive layer 7019 Partition wall 7020 Substrate 7021 Transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7026 Electrode 7027 Transparent conductive layer 7029 Partition wall 7030 Gate insulating layer 7031 Oxide insulating layer 7032 Insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulating layer 7040 Gate insulating layer 7041 Oxide insulating layer 7042 Insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulating layer 7051 Oxide insulating layer 7052 Protective insulating layer 7053 Planarizing insulating layer 7055 Insulating layer 9400 Communication device 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting part 9410 Display device 9411 Housing 9412 Display part 9413 Operation button 9600 Television device 9601 Housing 9603 Display part 9605 Stand 9607 Display part 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display part 9881 Housing 9882 Display part 9883 Display part 9884 Speaker part 9885 Operation key 9886 Recording medium insertion part 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED lamp 9891 Housing 9893 Connecting part 9900 Slot machine 9901 Housing 9903 Display part 4503a Signal line drive circuit 4503b Signal line drive circuit 4504a Scanning line drive circuit 4504b Scanning line drive circuit 4518a FPC 4518b FPC

Claims

1. A transistor having a channel formation region in an oxide semiconductor layer, wherein the oxide semiconductor layer has a surface layer portion having an uneven surface and has a crystal region in the surface layer portion, wherein the oxide semiconductor layer has microcrystals c-axis oriented with respect to the uneven surface, wherein the oxide semiconductor layer has a quaternary metal oxide film, a ternary metal oxide film, or a binary metal oxide film, a semiconductor device.

2. A transistor having a channel formation region in an oxide semiconductor layer, wherein the oxide semiconductor layer has a first region and a second region, wherein a direction perpendicular to the surface of the oxide semiconductor layer in the first region is a first direction, wherein a direction perpendicular to the surface of the oxide semiconductor layer in the second region is a second direction, wherein the first direction is different from the second direction, wherein the first region has first microcrystals c-axis oriented in the first direction, wherein the second region has second microcrystals c-axis oriented in the second direction, a semiconductor device.

3. A transistor having a channel formation region in an oxide semiconductor layer, wherein the oxide semiconductor layer, has a first region having first microcrystals c-axis oriented in a direction perpendicular to the surface of the oxide semiconductor layer in a surface layer portion, and has a second region having second microcrystals in a region other than the surface layer portion, wherein a crystal state of the second region is different from a crystal state of the first region, a semiconductor device.

4. In Claim 2 or Claim 3, wherein the oxide semiconductor layer has a quaternary metal oxide film, a ternary metal oxide film, or a binary metal oxide film, a semiconductor device.

5. In Claim 1 or Claim 4, wherein the quaternary metal oxide film is an In—Sn—Ga—Zn—O film, wherein the ternary metal oxide film is an In—Ga—Zn—O film, an In—Sn—Zn—O film, an In—Al—Zn—O film, a Sn—Ga—Zn—O film, an Al—Ga—Zn—O film, or a Sn—Al—Zn—O system, wherein the binary metal oxide film is an In—Zn—O film, a Sn—Zn—O film, an Al—Zn—O film, a Zn—Mg—O film, a Sn—Mg—O film, or an In—Mg—O film, a semiconductor device.

6. In any one of Claims 2 to 4, wherein the first microcrystals have a particle size of 1 nm or more and 20 nm or less, a semiconductor device.

7. In any one of Claims 1 to 6, having a first electrode and a second electrode, The first electrode has a region in contact with the lower surface of the oxide semiconductor layer. The second electrode has a region in contact with the lower surface of the oxide semiconductor layer. A semiconductor device.

Images