Semiconductor device and method of manufacturing the same

Abstract

Aspects of the present disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a first die, the first die including a first contact structure formed on a front surface of the first die. The semiconductor device includes a first semiconductor structure and a first pad structure disposed on a rear surface of the first die. The first semiconductor structure is conductively connected to the first contact structure from the rear surface of the first die, and the first pad structure is conductively coupled to the first semiconductor structure. An end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. The first die and the second die can be bonded face-to-face.

Description

Technical Field

[0001] This application describes embodiments generally related to semiconductor devices.

Background Art

[0002] Generally, semiconductor devices (e.g., semiconductor chips) communicate with the outside world via various input / output (I / O) pad structures such as signaling pad structures and power / ground (P / G) pad structures. In some examples, a semiconductor chip can include multiple metal layers formed over a circuit on a substrate. One or more of the metal layers are used to form pad structures that are conductively coupled to the circuit above the substrate. The pad structures can be formed to facilitate the attachment of bonding wires that can conductively couple the pad structures to external components such as power, ground, other semiconductor chips, and metal lines on a printed circuit board (PCB).

Summary of the Invention

[0003] Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a first die, and the first die includes a first contact structure formed on a surface of the first die. The semiconductor device includes a first semiconductor structure disposed on a back surface of the first die and conductively connected to the first contact structure from the back surface of the first die. The semiconductor device further includes a first pad structure disposed on the back surface of the first die and conductively coupled to the first semiconductor structure.

[0004] In one embodiment, an end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure.

[0005] In one embodiment, the semiconductor device includes a second semiconductor structure disposed on the back surface of the first die. The second semiconductor structure is conductively connected to the second contact structure from the back surface of the first die. The second pad structure in the semiconductor device is disposed on the back surface of the first die and is conductively coupled to the second semiconductor structure. The semiconductor device further includes a first insulating structure disposed between the first pad structure and the second pad structure, electrically insulating the first pad structure from the second pad structure.

[0006] In one example, the semiconductor device further includes a second insulating structure disposed between the first semiconductor structure and the second semiconductor structure, electrically insulating the first semiconductor structure from the second semiconductor structure.

[0007] In one embodiment, the first semiconductor structure includes a doped semiconductor material, and the first pad structure includes a metal material. In one example, the doped semiconductor material is polysilicon.

[0008] In one embodiment, the first die includes a core region including a vertical memory cell string, a staircase region for connecting to the gates of the memory cells in the vertical memory cell string, and a contact region including a first contact structure. The core region, the staircase region, and the contact region are electrically insulated by respective insulating structures of an insulating layer disposed on the back surface of the first die.

[0009] In one example, the pad structure is disposed on the back surface of the first die and is conductively connected to the vertical memory cell string in the core region through a semiconductor structure disposed between the pad structure and the vertical memory cell string.

[0010] In one example, the semiconductor device further includes a second die having a peripheral circuit for a vertical memory cell string on the surface of the second die. The first die and the second die are joined face to face.

[0011] In one example, the first contact structure on the first die is electrically coupled to the input / output circuit on the second die through a bonding structure.

[0012] Aspects of the present disclosure provide a method of manufacturing a semiconductor device. The method includes forming, on a back surface of a first die, a first semiconductor structure that is conductively connected to a first contact structure from the back surface of the first die, and forming, on the back surface of the first die, a first pad structure that is conductively connected to the first semiconductor structure. The first die includes a first substrate and a first contact structure formed on a surface of the first die.

[0013] In one embodiment, the method further includes bonding the first die and a second die face to face. The method includes removing the first substrate from the back surface of the first die, and an end of the first contact structure on the back surface of the first die is exposed. The end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure.

[0014] In one embodiment, forming the first semiconductor structure includes forming a semiconductor layer on an end of the first contact structure on the back surface of the first die, and forming the semiconductor structure by removing a first portion of the semiconductor layer. The first hole is formed to separate a semiconductor structure including the first semiconductor structure and a second semiconductor structure. Forming the first semiconductor structure further includes depositing an insulating layer on the semiconductor structure and in the first hole. A portion of the insulating layer in the first hole forms a second insulating structure. One of the second insulating structures is disposed between the first semiconductor structure and the second semiconductor structure and electrically insulates the first semiconductor structure and the second semiconductor structure. The first die is separated into a core region including a vertical memory cell string, a staircase region for connecting to a gate of a memory cell in the vertical memory cell string, and a contact region including the first contact structure. The core region, the staircase region, and the contact region are electrically insulated by two second insulating structures.

[0015] Forming the first pad structure includes removing a second portion of the insulating layer to form a second hole above each of the semiconductor structures and forming a pad structure in the second hole above each of the semiconductor structures. The pad structure including the first pad structure is electrically insulated by a first insulating structure of the insulating layer.

[0016] In one example, forming the semiconductor layer includes depositing a doped semiconductor material that is conductive to form the semiconductor layer, and the first semiconductor structure includes the doped semiconductor material. In one example, the doped semiconductor material is polysilicon.

[0017] In one example, one of the pad structures is within the core region and is conductively connected to a vertical memory cell string within the core region via a semiconductor structure disposed between the one of the pad structures and the vertical memory cell string.

[0018] In one example, the second die includes peripheral circuitry for the vertical memory cell string.

[0019] In one embodiment, bonding the first die and the second die face to face further includes bonding a first bonding structure on the first die to a second bonding structure on the second die. The first bonding structure is conductively coupled to a first contact structure on the first die, and the second bonding structure is conductively coupled to an input / output circuit on the second die.

[0020] Aspects of the present disclosure provide a memory system including a semiconductor device and a controller. The semiconductor device includes a first die, a first semiconductor structure, and a first pad structure. The first die may include a first contact structure formed on a surface of the first die. The first semiconductor structure is disposed on a back surface of the first die and may be conductively connected to the first contact structure from the back surface of the first die. The first pad structure is disposed on the back surface of the first die and may be conductively coupled to the first semiconductor structure. The controller can be configured to control the operation of the semiconductor device to which the controller is connected to the semiconductor device.

Brief Description of the Drawings

[0021] Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with standard industry practice. In fact, the dimensions of various features can be arbitrarily increased or decreased to clarify the description.

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Modes for Carrying Out the Invention

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features so that the first and second features are not in direct contact. Further, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not in itself define a relationship between the various embodiments and / or configurations described.

[0023] Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to facilitate description of the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] Aspects of the present disclosure provide techniques for forming a pad structure for a semiconductor device having two dies (e.g., a first die and a second die) joined face to face. In some embodiments, circuit components are formed on the surfaces of the two dies. The pad structure is formed on the back surface of one of the two dies, such as the first die. In one example, the technique for forming the pad structure does not require forming a through-silicon contact (TSC) from the back surface of the first die, simplifying the process for forming the pad structure.

[0025] The first pad structure is disposed on the back surface of the first die and is conductively connected to a first contact structure formed on the surface of the first die where the first contact structure is connected to an input / output (I / O) circuit. According to an aspect of the present disclosure, the first pad structure is conductively coupled to the first contact structure via a first semiconductor structure disposed between the first pad structure and the first contact structure. Specifically, the first semiconductor structure is disposed on the back surface of the first die and is conductively connected from the back surface of the first die to the first contact structure. Further, the first pad structure is disposed on the back surface of the first die and is conductively coupled to the first semiconductor structure. In one example, an end of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure. In one example, the first semiconductor structure includes a highly doped semiconductor material such as highly doped polysilicon having a relatively high conductivity. Thus, the electrical coupling between the first pad structure and the first contact structure is facilitated by the conductivity of the highly doped semiconductor structure. In one example, by using the semiconductor structure, the stress of the semiconductor device is reduced.

[0026] In one embodiment, the second pad structure is disposed on the back surface of the first die and is conductively coupled to a second contact structure via a second semiconductor structure disposed between the second pad structure and the second contact structure. According to an aspect of the present disclosure, the first insulating structure is disposed between the first pad structure and the second pad structure and electrically insulates the first pad structure from the second pad structure.

[0027] In some examples, the first die includes a core region having a vertical memory cell string. In some embodiments, the pad structure within the core region can be configured as a connection of an array common source for one or more vertical memory cell strings.

[0028] According to some aspects of the present disclosure, in a semiconductor device, one of two dies is formed on a surface and includes a memory cell array such as a vertical memory cell string in the case of a three-dimensional (3D) NAND device called an array die, and the other of the two dies is formed on a surface and is a semiconductor memory device including a peripheral circuit called a peripheral die. In some examples, the peripheral circuit is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the peripheral die is also called a CMOS die. The pad structure can be formed on the back surface of the array die or on the back surface of the peripheral die.

[0029] According to some aspects of the present disclosure, two dies (e.g., an array die and a peripheral die) are separately formed on two wafers. In some embodiments, a first wafer including the array die and a second wafer including the peripheral die are separately formed. For example, the first wafer can be manufactured to optimize the density and performance of the vertical memory cell string without compromising the manufacturing limitations due to the peripheral circuit, and the second wafer can be manufactured to optimize the performance of the peripheral circuit without compromising the manufacturing limitations due to the vertical memory cell string. In some embodiments, the first wafer and the second wafer can be bonded face-to-face using wafer-to-wafer bonding technology, and thus, the array die on the first wafer is bonded to the peripheral die on the second wafer respectively. Next, using the technology provided in the present disclosure, a pad structure can be manufactured on the back surface of one of the two wafers.

[0030] FIG. 1 shows a cross-sectional view of a semiconductor device such as semiconductor device 100 according to some embodiments of the present disclosure. Semiconductor device 100 includes two dies bonded face-to-face. The pad structure is formed on the back surface of one of the two dies using the technology provided in the present disclosure. In some examples, semiconductor device 100 includes two wafers bonded face-to-face. Using the technology provided in the present disclosure, a pad structure is formed on the back surface of one of the two wafers.

[0031] Specifically, in the example of FIG. 1, the semiconductor device 100 includes array dies 102 and CMOS dies 101 that are joined face to face. In some embodiments, the semiconductor device can include a plurality of array dies and CMOS dies. The plurality of array dies and CMOS dies can be stacked and joined to each other. The CMOS dies are each coupled to the plurality of array dies and can drive each of the array dies in a similar manner.

[0032] The semiconductor device 100 can be any suitable device. In some examples, the semiconductor device 100 includes at least a first wafer and a second wafer joined face to face. The array dies 102 are arranged on the first wafer together with other array dies, and the CMOS dies 101 are arranged on the second wafer together with other CMOS dies. The first wafer and the second wafer are joined to each other, and thus the array dies on the first wafer are joined to the corresponding CMOS dies on the second wafer. In some examples, the semiconductor device 100 is a semiconductor chip in which at least the array die 102 and the CMOS die 101 are joined to each other. In one example, the semiconductor chip is diced from wafers joined to each other. In another example, the semiconductor device 100 is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0033] The array die 102 includes regions 107 to 109 that are separated by a second insulating structure 129a of the insulating layer 129 and are electrically insulated. The insulating layer 129 is disposed on the back side of the array die 102. The memory cell array can be formed within the region 107. The region 107 can be referred to as the core region 107. The region 108 can be referred to as the staircase region 108 and can be used, for example, to facilitate connections to gates of memory cells in the memory cell array, gates of select transistors, etc. The gates of the memory cells in the memory cell array correspond to word lines for a NAND memory architecture. The region 109 can provide a space for the contact structure 170. The CMOS die 101 includes a substrate 104 and peripheral circuits formed on the substrate 104. For simplicity, the main surface (of the die or wafer) is referred to as the X-Y plane, and the direction perpendicular to the main surface is referred to as the Z direction.

[0034] Furthermore, in the example of FIG. 1, the pad structures 121 to 123 are formed on the back surface of one of the two dies, such as the array die 102, within the layer stack.

[0035] In the example of FIG. 1, the layer stack on the back surface of the array die 102 includes a first etching stop layer 111, a semiconductor layer 116, an insulating layer 601, and an insulating layer 129 laminated on the back surface of the array die 102. Furthermore, the insulating layer 129 separates the first etching stop layer 111, the semiconductor layer 116, and the insulating layer 601 into a part of the first etching stop layer 111, semiconductor structures 116a to 116d of the semiconductor layer 116, and a part of the insulating layer 601 (e.g., 601a to 601d in FIG. 7). Referring to FIG. 1, the second insulating structure 129a of the insulating layer 129 separates the first etching stop layer 111, the semiconductor layer 116, and the insulating layer 601. In one example, the insulating layer 601 is omitted.

[0036] According to some aspects of the present disclosure, pad structures (e.g., 121-123) are each formed over semiconductor structures formed using semiconductor layer 116, as shown by semiconductor structures 116a, 116c, and 116d. The pad structures may be separated and electrically isolated by insulating layer 129. Referring to FIG. 1, insulating layer 129 includes second insulating structure 129a and first insulating structures 911-914. The set of first insulating structures 911-914 separates the pad structures. For example, pad structures 121, 123 are separated by first insulating structure 912, and pad structures 122, 123 are separated by first insulating structure 913.

[0037] Semiconductor structures 116a-116d are over respective portions of first etch stop layer 111. Certain pad structures (e.g., 122-123) can be conductively connected to one or more of contact structures 170, and certain pad structures (e.g., 121) can be configured as a connection to an array common source for vertical memory cell strings 180 within core region 107.

[0038] According to an aspect of the present disclosure, a pad structure (e.g., one of pad structures 122-123) can be disposed on the back surface of the first die and can be conductively coupled to contact structure 170 through a semiconductor structure disposed between the pad structure and the contact structure. The semiconductor structure can be conductively connected to the contact structure at the back surface of the first die. Further, the pad structure is conductively coupled to the semiconductor structure.

[0039] Referring to FIG. 1, semiconductor structure 116d is disposed between pad structure 122 and contact structure 170. Semiconductor structure 116d conductively couples pad structure 122 and contact structure 170. In some examples, an end 170a of contact structure 170 protrudes into semiconductor structure 116d without connecting to pad structure 122. Thus, pad structure 122 does not connect directly to contact structure 170. The electrical connection or coupling between pad structure 122 and contact structure 170 is formed using semiconductor structure 116d.

[0040] Other pad structures (e.g., 121, 123) can have the same or identical structures and materials as those described for pad structure 122, and thus detailed descriptions are omitted for the sake of brevity.

[0041] The pad structures (e.g., 121 - 123) can include any suitable conductive material such as a metallic material (e.g., aluminum (Al), copper (Cu), tungsten (W), etc.). In one example, the metallic material used for the pad structures (e.g., 121 - 123) facilitates the attachment of bonding wires. The pad structures can be formed using any suitable method such as physical vapor deposition (PVD), plating (or electroplating). In one example, Cu is formed using plating (or electroplating). In one example, pad structures 121 - 123 are formed using the same process and contain the same materials.

[0042] The semiconductor structures (e.g., 116a - 116d) can include any suitable semiconductor material or combination of semiconductor materials. In one example, the semiconductor structures (e.g., 116a - 116d) include doped semiconductor materials. For example, the doped semiconductor material is silicon (Si) such as polysilicon. In one example, the doping level of the doped semiconductor material is relatively high, and the semiconductor structures (e.g., 116a - 116d) have relatively good conductivity. In one example, the sheet resistance of the semiconductor structures (e.g., 116a - 116d) is less than 1000 Ω / sq. In one example, the semiconductor structures (e.g., 116a - 116d) are formed by depositing highly doped Si using chemical vapor deposition (CVD). In one example, the semiconductor structures (e.g., 116a - 116d) are formed using furnace CVD. In some examples, after the deposition process, the highly doped Si is recrystallized, and an annealing process follows to promote the growth of recrystallized grains. Thereby, the conductivity of the semiconductor structures (e.g., 116a - 116d) is enhanced, and the conductivity of the semiconductor structures (e.g., 116a - 116d) becomes good.

[0043] Generally, two pad structures (e.g., 122 - 123) can be physically separated and electrically insulated by a first insulating structure (e.g., the first insulating structure 913) within the insulating layer 129. The first insulating structure (e.g., 913) can be disposed between the two pad structures (e.g., 122 - 123). The semiconductor structures (e.g., 116c and 116d) under each of the two pad structures (e.g., 122 - 123) are physically separated and electrically insulated by a second insulating structure (e.g., 129a). The second insulating structure (e.g., 129a) is disposed between the semiconductor structures (e.g., 116c and 116d).

[0044] In the example of FIG. 1, the pad structure 121 is above the semiconductor structure 116a. Thus, the pad structure 121 is conductively connected or coupled to the source terminal of the vertical memory cell string 180 in the region 107 via the semiconductor structure 116a. The semiconductor structure 116a is disposed between the pad structure 121 and the vertical memory cell string 180.

[0045] In some examples, the semiconductor structure 116a can be coupled to the source terminals of multiple vertical memory cell strings 180 and serve as an array common source (ACS) for the multiple vertical memory cell strings 180. In some examples, the pad structure 121 is formed from one or more metal layers with a relatively low resistivity, and when the pad structure 121 covers a relatively large portion of the semiconductor structure 116a, the pad structure 121 can connect the ACS of a block of the memory cell array with a very small parasitic resistance. The pad structure 121 can include a portion configured as a pad structure for the ACS to receive an ACS signal from an external source. The pad structure 121 can have any suitable metal material. In one example, the pad structure 121 is formed together with the pad structures 122 - 123 in the same process and has the same material (e.g., Al, Cu, W, etc.) as that used in the pad structures 122 - 123.

[0046] Some components of the semiconductor device 100, such as passivation structures, are not shown for simplicity.

[0047] The array die 102 initially includes a substrate. The substrate is removed before the formation of the semiconductor structures 116a-116d and the pad structures 121-123.

[0048] FIG. 2 is a flowchart and diagram showing an overview of a process 200 for forming a semiconductor device such as the semiconductor device 100 according to some embodiments of the present disclosure, and FIGS. 3-10 show cross-sectional views of the semiconductor device 100 during the process according to some embodiments. The process 200 starts from S201 and proceeds to S210.

[0049] At S210, the first die and the second die are joined face to face. The first die includes a first substrate. In one embodiment, the first die includes a plurality of regions (e.g., a core region, a staircase region, a contact region, etc.). The first die also includes a first transistor (e.g., a transistor in the memory cell string 180) formed in the core region by a processing step operating from the surface side of the first die. Further, the first die includes a contact structure (e.g., the contact structure 170) disposed in the contact region outside the core region and the staircase region, for example. The contact structure can be formed by a processing step operating from the surface of the first die. The second die includes a second substrate on which a second transistor is formed on the surface of the second die.

[0050] In some embodiments, the first die is an array die such as the array die 102, and the second die is a CMOS die such as the CMOS die 101. In some examples, the first die can be a CMOS die, and the second die can be an array die.

[0051] FIG. 3 shows a cross-sectional view of the semiconductor device 100 after the bonding process of the two dies. The semiconductor device 100 includes the array die 102 and the CMOS die 101 bonded face to face.

[0052] In some embodiments, the array die 102 is manufactured using other array dies on the first wafer, and the CMOS die 101 is manufactured using other CMOS dies on the second wafer. In some examples, the first wafer and the second wafer are manufactured separately. For example, the memory cell array and the I / O contact structure are formed on the first wafer using a process operating on the surface of the first wafer. Also, a first bonding structure is formed on the surface of the first wafer. Similarly, the peripheral circuit is formed on the second wafer using a process operating on the surface side of the second wafer, and a second bonding structure is formed on the surface side of the second wafer.

[0053] In some embodiments, the first wafer and the second wafer can be face-to-face bonded using wafer-to-wafer bonding technology. The first bonding structure on the first wafer is bonded to the corresponding second bonding structure on the second wafer, and thus, the array die on the first wafer is bonded to the CMOS die on the second wafer respectively.

[0054] Referring to FIG. 3, the array die 102 includes a substrate 103. Regions 107-109 are formed on the substrate 103. A memory cell array can be formed in the core region 107, and a contact structure can be formed in the contact region 109. The staircase region 108 is used, for example, to facilitate connections to gates of memory cells in a vertical memory cell string, gates of select transistors, and the like. The CMOS die 101 includes a substrate 104 and includes a peripheral circuit formed on the substrate 104.

[0055] The substrate 103 and the substrate 104 can each be any suitable substrate such as a Si substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate 103 and the substrate 104 can each include a semiconductor material, for example, a Group IV semiconductor, a III-V compound semiconductor, or a II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate 103 and the substrate 104 can each be a bulk wafer or an epitaxial layer. In some examples, the substrate is formed from a plurality of layers. For example, as shown in FIG. 3, the substrate 103 includes a plurality of layers such as a bulk portion 118 and an insulating layer 114 (for example, a silicon oxide layer).

[0056] In the example of FIG. 3, the memory cell array is formed on the substrate 103 of the array die 102, and the peripheral circuit is formed on the substrate 104 of the CMOS die 101. The array die 102 and the CMOS die 101 are arranged face to face (the surface on which the circuit is arranged is called the front, and the opposite surface is called the back), and are joined to each other.

[0057] In some examples, the process steps operating on the surface of the array die 102 can form one or more layers on the substrate 103. In one example, the one or more layers can include a conductive layer 113, a second etch stop layer 112, and a first etch stop layer 111 that are sequentially formed on the substrate 103. A block of 3D NAND memory cell strings (for example, the memory cell string 180) can be formed on the substrate 103. In the example shown in FIG. 3, the 3D NAND memory cell string penetrates the conductive layer 113. In some examples, the memory cell array is formed in the core region 107 as an array of vertical memory cell strings.

[0058] The staircase region 108 is used, for example, to facilitate connections to gates of memory cells, gates of select transistors, etc. within a vertical memory cell string. The gates of the memory cells within the vertical memory cell string correspond to word lines for a NAND memory architecture. The contact structure 170 is formed in the contact region 109.

[0059] In the example of FIG. 3, one of the vertical memory cell strings 180 is shown as a representation of an array of vertical memory cell strings formed within the core region 107. The vertical memory cell string 180 is formed within a stack of layers 190. The stack of layers 190 includes alternately stacked gate layers 195 and insulating layers 194. The gate layer 195 and the insulating layer 194 are configured to form transistors stacked vertically. In some examples, the stack of transistors includes memory cells and select transistors such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the stack of transistors can include one or more dummy select transistors. The gate layer 195 corresponds to the gate of the transistor. The gate layer 195 is made of gate stack materials such as a high-k (High-k) gate insulator layer, a metal gate (MG) electrode, etc. The insulating layer 194 is made of an insulating material such as silicon nitride, silicon dioxide, etc.

[0060] In one embodiment, the vertical memory cell string 180 is formed from respective channel structures 181 (one of the channel structures 181 is shown in FIG. 3) that extend vertically (along the Z direction) within the stack of layer 190. The channel structures 181 can be arranged separated from each other in the X-Y plane. In some embodiments, the channel structures 181 are arranged in an array form between gate line cut structures (not shown). The gate line cut structures are used to facilitate the replacement of the sacrificial layer with the gate layer 195 in the gate last process. The array of channel structures 181 can have any suitable array shape, such as a matrix array shape along the X and Y directions, a zigzag array shape along the X or Y direction, a honeycomb (e.g., hexagonal) array shape, and the like. In some embodiments, each of the channel structures 181 has a circular shape in the X-Y plane and a pillar shape in the X-Z plane and the Y-Z plane. In some embodiments, the amount and arrangement of the channel structures between the gate line cut structures are not limited.

[0061] In some embodiments, the channel structure 181 has a pillar shape extending in the Z direction perpendicular to the main surface direction of the substrate 103. In one embodiment, the channel structure 181 is formed of a circular material in the X-Y plane and extends in the Z direction. For example, the channel structure 181 includes a semiconductor layer (also referred to as a channel layer) 185 (e.g., polysilicon) surrounded by one or more insulating layers 189. In one example, the one or more insulating layers 189 include a blocking insulating layer (e.g., silicon oxide), a charge storage layer (e.g., silicon nitride), and a tunnel insulating layer (e.g., silicon oxide) that forms an oxide-nitride-oxide (ONO) structure surrounding the channel layer 185. The channel structure 181 can further include a space 186 within the channel layer 185. The space 186 may be a void or may be filled with an insulating material and can be referred to as an insulating layer 186. The channel structure 181 can have a circular shape in the X-Y plane and extend in the Z direction. In one example, a blocking insulating layer (e.g., silicon oxide) is formed on the sidewalls of the hole for the channel structure 181 (within the stack of layer 190), and then a charge storage layer (e.g., silicon nitride), a tunnel insulating layer, a semiconductor layer 185, and an insulating layer 186 are sequentially laminated from the sidewalls. The semiconductor layer 185 can be any suitable semiconductor material such as polysilicon or single-crystalline silicon, and the semiconductor material may not be doped or may include p-type or n-type dopants. In some examples, the semiconductor material is an undoped intrinsic silicon material. However, in some examples, due to defects, the intrinsic silicon material can have a carrier density on the order of 10 10 cm -3 . The insulating layer 186 is formed of an insulating material such as silicon oxide and / or silicon nitride and / or may be formed as an air gap.

[0062] In one embodiment, the stack of the channel structure 181 and the layer 190 together form the memory cell string 180. For example, the semiconductor layer 185 corresponds to the channel portion of the transistor in the memory cell string 180, and the gate layer 195 corresponds to the gate of the transistor in the memory cell string 180. Generally, a transistor has a gate that controls a channel and has a drain and a source on both sides of the channel. For simplicity, in the example of FIG. 3, the bottom side of the channel of the transistor in FIG. 3 is called the drain, and the upper side of the channel of the transistor in FIG. 3 is called the source. The drain and the source can be switched under a specific driving configuration. In the example of FIG. 3, the semiconductor layer 185 corresponds to the connection channel of the transistor. In the example of FIG. 3, for a specific transistor, the drain of the specific transistor is connected to the source of the lower transistor below it, and the source of the specific transistor is connected to the drain of the upper transistor above it. Thereby, the transistors in the memory cell string 180 are connected in series. "Upper" and "lower" are specifically used in FIG. 3 where the array die 102 is arranged upside down.

[0063] The memory cell string 180 includes memory cell transistors (also referred to as memory cells). The memory cell transistors can have different threshold voltages based on carrier trapping in a part of the charge storage layer corresponding to the floating gate of the memory cell transistors. For example, when a significant amount of holes are trapped (accumulated) in the floating gate of the memory cell transistor and the threshold voltage of the memory cell transistor is lower than a predetermined value, the memory cell transistor is in a non-programmed state (also called an erased state) corresponding to logic "1". When the holes are released from the floating gate, the threshold voltage of the memory cell transistor exceeds the predetermined value, so the memory cell transistor is in a programmed state corresponding to logic "0" in some examples.

[0064] In one example, the memory cell string 180 includes one or more upper select transistors configured to couple / disconnect the memory cells in the memory cell string 180 to / from the bit lines, and one or more bottom select transistors configured to couple / disconnect the memory cells in the memory cell string 180 to / from the ACS.

[0065] The upper select transistors are controlled by an upper select gate (TSG). For example, when the TSG voltage (the voltage applied to the TSG) is greater than the threshold voltage of the upper select transistors in the memory cell string 180, the upper select transistors in the memory cell string 180 turn on, and the memory cells in the memory cell string 180 are coupled to the bit lines (e.g., the drains of the string of memory cells are coupled to the bit lines), and when the TSG voltage (the voltage applied to the TSG) is less than the threshold voltage of the upper select transistors, the upper select transistors are turned off, and the memory cells in the memory cell string 180 are disconnected from the bit lines (e.g., the drains of the string of memory cells are decoupled from the bit lines).

[0066] Similarly, the bottom select transistors are controlled by a bottom select gate (BSG). For example, when the BSG voltage (the voltage applied to the BSG) is greater than the threshold voltage of the bottom select transistors in the memory cell string 180, the bottom select transistors turn on, and the memory cells in the memory cell string 180 are coupled to the ACS (e.g., the sources of the columns of memory cells in the memory cell string 180 are coupled to the ACS), and when the BSG voltage (the voltage applied to the BSG) is less than the threshold voltage of the bottom select transistors, the bottom select transistors are turned off, and the memory cells are decoupled from the ACS (e.g., the sources of the string of memory cells in the memory cell string 180 are decoupled from the ACS).

[0067] In the example of FIG. 3, an interconnection structure such as via 162, metal wire 163, and bonding structure 164 can be formed to electrically couple the bottom of semiconductor layer 185 to bit line (BL). The interconnection structure can be appropriately adapted to include additional structures, to modify one of via 162, metal wire 163, and bonding structure 164, and / or to omit one of via 162, metal wire 163, and bonding structure 164.

[0068] Further, in the example of FIG. 3, the stepped region 108 includes steps formed to facilitate the word line (WL) connection to the gates of transistors (such as memory cells, upper select transistors (if any), bottom select transistors (if any), etc.). For example, the connection structure (also referred to as the word line connection structure) 150 includes contact plugs (also referred to as word line contact plugs) 151, via structures 152, and metal wires 153 that are conductively coupled to each other. The word line connection structure 150 can electrically couple the WL to the gate terminals of the transistors within the memory cell string 180. The connection structure 150 can be appropriately adapted to include additional structures, to modify one of contact plug 151, via structure 152, and metal wire 153, and / or to omit one of contact plug 151, via structure 152, and metal wire 153.

[0069] In the example of FIG. 3, the contact structure 170 is formed in the contact region 109. In some embodiments, the contact structure 170 can be formed simultaneously with the word line connection structure 150 by processing the surface of the array die 102. Thus, in some examples, the contact structure 170 has a structure and / or material similar to that of the word line connection structure 150. Specifically, the contact structure 170 can include a contact plug 171, a via structure 172, and a metal wire 173 that are conductively coupled to each other. The contact structure 170 can be suitably adapted to include additional structures, to modify one of the contact plug 171, the via structure 172, and the metal wire 173, and / or to omit one of the contact plug 171, the via structure 172, and the metal wire 173.

[0070] In some examples, a mask including patterns for the contact plug 171 and the word line contact plug 151 can be used. The mask is used to form contact holes for the contact plug 171 and the word line contact plug 151. An etching process can be used to form the contact holes. In one example, the etching of the contact hole for the word line contact plug 151 can stop on the gate layer 195, and the etching of the contact hole for the contact plug 171 can stop within the conductive layer 113. Further, the contact holes can be filled with a suitable liner layer (e.g., titanium / titanium nitride) and a metal layer (e.g., tungsten) to form contact plugs such as the contact plug 171 and the word line contact plug 151. The contact structure 170 can extend into the conductive layer 113 by only the penetration depth. Specifically, in the example of FIG. 3, the contact plug 171 extends into the conductive layer 113 through the first etch stop layer 111 and the second etch stop layer 112. A further back end of line (BEOL) process can be used to form various connection structures such as via structures, metal wires, and bonding structures.

[0071] Also, in the example of FIG. 3, bonding structures are respectively formed on the surfaces of the array die 102 and the CMOS die 101. For example, on the surface side of the array die 102, bonding structures 154, 164, and 174 of the word line connection structure 150, the memory cell string 180, and the contact structure 170 are formed, and on the surface of the CMOS die 101, bonding structures 131, 132, and 134 corresponding to the bonding structures 164, 154, and 174 are formed. The metal layers 191 to 193 can be formed in the COMS die 101 and can be respectively connected to the corresponding bonding structures 131, 132, and 134.

[0072] In the example of FIG. 3, the array die 102 and the CMOS die 101 are arranged facing each other (the circuit side is the front and the substrate side is the back), and are bonded to each other. The corresponding bonding structures on the array die 102 and the CMOS die 101 are aligned and bonded to each other to form a bonding interface that conductively couples the appropriate components on the two dies. For example, the bonding structure 164 and the bonding structure 131 are bonded to connect the drain side of the memory cell string 180 and the bit line (BL). In another example, the bonding structure 174 and the bonding structure 134 are bonded to each other to couple the contact structure 170 on the array die 102 to the I / O circuit on the CMOS die 101.

[0073] Referring back to FIG. 2, in S212, the first substrate of the first die is removed from the back surface of the first die. When the first substrate is removed, the memory cell string 180 and the contact structure 170 on the back surface of the first die are exposed. For example, when the first substrate is removed, the end 170a of the contact structure 170 is exposed.

[0074] FIG. 4 shows a cross-sectional view of the semiconductor device 100 after removing the first substrate 103 from the array die 102. In the example of FIG. 4, the bulk portion 118 and the insulating layer 114 are removed from the back surface of the array die 102. Further, the conductive layer 113 and the second etch stop layer 112 are removed from the back surface of the array die 102.

[0075] In some examples, after a wafer-to-wafer bonding process, a first wafer having array dies is bonded to a second wafer having CMOS dies. Then, the first substrate is thinned from the back surface of the first wafer. In one example, a chemical mechanical polishing (CMP) process or a grinding process is used to remove most of the bulk portion 118 of the first wafer. Further, an appropriate etching process can be used to remove the remaining bulk portion 118, the insulating layer 114, the conductive layer 113, and the second etch stop layer 112 from the back surface of the first wafer. Removal of the bulk portion 118, the insulating layer 114, the conductive layer 113, and the second etch stop layer 112 can expose the end portion 170a of the contact structure 170 protruding into the contact region 109. By removing the bulk portion 118, the insulating layer 114, the conductive layer 113, and the second etch stop layer 112, the end portion of the memory cell string 180 in the core region 107 can also be exposed.

[0076] Referring back to FIG. 2, steps S214, S216, S218, and S220 can be used to form semiconductor structures (e.g., 116a-116d) and pad structures (e.g., 121-123) on the back surface of the first die (e.g., array die 102), which will be described with reference to FIGS. 5-10.

[0077] Referring to FIGS. 2 and 5 - 7, steps S214 and S216 can be used to form semiconductor structures (e.g., 116a - 116d). In S214, a semiconductor layer (e.g., 116 in FIG. 5) used to form the semiconductor structure is formed on the back surface of the first die. Any suitable process such as CVD, furnace CVD, etc. can be used to form the semiconductor layer. According to an aspect of the present disclosure, the semiconductor layer includes a highly doped semiconductor material and can be annealed to further enhance the conductivity of the semiconductor material. The annealing process can promote the recrystallization of the semiconductor material and the further growth of crystal grains, resulting in a semiconductor layer having good conductivity. Referring to FIG. 5, in one example, the semiconductor layer 116 is deposited on the back surface of the array die 102 and on the first etching stop layer 111. The semiconductor layer 116 is also on the exposed memory cell string 180 and contact structure 170. In one example, the semiconductor layer 116 is disposed on the end 170a of the contact structure 170. The semiconductor layer 116 includes highly doped Si (e.g., polysilicon). The highly doped Si (e.g., polysilicon) in the semiconductor layer 116 is annealed and recrystallized to have good conductivity.

[0078] As shown in FIGS. 2, 6, and 7, in S216, semiconductor structures (e.g., 116a - 116d) can be formed from the semiconductor layer (e.g., 116) on the back surface of the first die. Referring to FIG. 6, an insulating layer 601 (also referred to as a hard mask layer) and a photoresist layer 602 are formed on the semiconductor layer 116 on the back surface of the first die (e.g., the array die 102). The hard mask layer 601 can include one or more insulating materials such as silicon oxide, silicon nitride, etc. The hard mask layer 601 can include one or more sub - layers. In one example, the hard mask layer 601 includes silicon oxide.

[0079] Referring to FIG. 7, on the back surface of the first die (e.g., array die 102), using a photolithography process, a pattern for the second insulating structure 129a of the insulating layer 129 is defined within the photoresist layer 602 according to a mask. By using an etching process to remove a part of the hard mask layer 601, the semiconductor layer 116, and the first etching stop layer 111, the first holes 701 - 704 are formed. The portion removed from the semiconductor layer 116 is referred to as the first portion of the semiconductor layer 116. The semiconductor structures 116a - 116d are formed by removing the first portion of the semiconductor layer 116, and the first holes 701 - 704 separate the semiconductor structures 116a - 116d.

[0080] In one example, the etching process includes a dry etching process. In one example, the etching process etches the back surface of the first die down to the stack of layers 190 including the gate layer 195 and the insulating layer 194. In one example, the stack of layers 190 remains intact or is minimally affected. Subsequently, the photoresist layer 602 is removed. In one example, as shown in FIG. 7, the hard mask layer 601 is not removed. Alternatively, a part or all of the hard mask layer 601 can be removed.

[0081] Referring to FIGS. 2 and 8, at S218, an insulating layer (e.g., insulating layer 129) is formed on the hard mask layer 601 on the back surface of the first die (e.g., array die 102). Further, the insulating layer 129 is deposited within the first holes 701 - 704, filling the first holes 701 - 704, and the second insulating structure 129a is formed within the first holes 701 - 704. Thereby, a composite insulating layer 801 including the insulating layer 129 and the hard mask layer 601 is formed on the semiconductor layer 116. In one example, the hard mask layer 601 is removed before forming the insulating layer 129, and thus the insulating layer 129 is formed on the semiconductor layer 116 and within the first holes 701 - 704.

[0082] Referring to FIG. 8, the array die 102 is separated into regions 107-109 by two of the second insulating structures 129a. Specifically, regions 107-108 are separated by the second insulating structure 129a within the first hole 701, and regions 108-109 are separated by the second insulating structure 129a within the first hole 702. The semiconductor layer 116 is separated into semiconductor structures 116a-116d by the second insulating structure 129a. Two semiconductor structures (e.g., 116c and 116d) can be separated and electrically insulated by the second insulating structure (e.g., 129a). The hard mask layer 601 is separated into portions 601a-601d by the second insulating structure 129a.

[0083] Referring to FIGS. 1, 2, 9, and 10, at S220, a pad structure (e.g., 121-123 within the semiconductor device 100) is formed on the back surface of the first die (e.g., the array die 102).

[0084] Referring to FIG. 9, a photoresist layer 902 is formed on the insulating layer 129. Subsequently, a photolithography process is used to define the pattern of the pad structure (e.g., 121-123) in the photoresist layer 902 according to a mask. An etching process is used to remove the second portion of the insulating layer 129 and the corresponding portion of the hard mask layer 601 to form the second holes 901-903 above the respective semiconductor structures. In one example, the etching process further etches the semiconductor layer 116 to remove the upper portions of the semiconductor structures 116a-116d. In one example, the etching process includes a dry etching process.

[0085] Referring to FIGS. 1 and 10, the pad structure is formed on the back surface of the first die (e.g., array die 102). In one example, the photoresist layer 902 is removed. Thereafter, the metal layer 1001 is formed by depositing a metal material on the back surface of the array die 102 using any suitable method such as PVD. In one example, the metal layer (e.g., Cu layer) 1001 is electroplated on the back surface of the first die. The metal layer 1001 fills the second holes 901 - 903.

[0086] Referring to FIG. 1, a part of the metal layer 1001 on the insulating layer 129 can be removed by, for example, an etching process, CMP, etc. A part of the metal layer 1001 in the second holes 901 - 903 forms the pad structure (e.g., 121 - 123). The pad structure (e.g., 121 - 123) is separated and electrically insulated by the first insulating structures 911 - 914 of the insulating layer 129.

[0087] The metal layer 1001 can include one or more materials such as the metal materials Al, Cu, W, etc. The metal layer 1001 can include one or more layers. In some embodiments, an interface layer can be formed between the metal material (e.g., Al) and the semiconductor layer 116. In some examples, a metal silicide thin film can be used as the interface layer. In one example, the metal silicide thin film can be used to enable an ohmic contact between Al and the semiconductor layer 116. In another example, a metal silicide thin film is used as a diffusion barrier to prevent the diffusion of aluminum into the semiconductor layer 116.

[0088] When the metal layer 1001 is formed on the semiconductor layer 116, pad structures (e.g., 121-123) are formed on respective semiconductor structures (e.g., 116a, 116c, and 116d). Thus, in some examples, contamination from the formation of the metal layer 1001 to the channel structure 181 is reduced or eliminated. In one example, a semiconductor material such as polysilicon within the semiconductor structures (e.g., 116a, 116c, and 116d) is used to facilitate the connection between the pad structure and respective contact structures, thereby reducing stress within the semiconductor device.

[0089] In the present disclosure, one pad structure (e.g., 121) is shown in the core region 107. Generally, one or more pad structures can be formed within the core region 107 using the processes described in the present disclosure.

[0090] The semiconductor device can include a first wafer and a second wafer joined to each other. In one example, the first wafer includes a first die (e.g., array die 102), and the second wafer includes a second die (e.g., CMOS die 101). The process 200 shown in FIGS. 1-10 can be suitably applied to a semiconductor device in which the first wafer and the second wafer are joined. For example, the substrate of one of the first wafer and the second wafer (e.g., the first wafer) is removed as described with reference to FIGS. 2-4. The semiconductor structure is formed on the back surface of the first wafer as described with reference to FIGS. 2 and 5-8. Subsequently, a pad structure is formed on the back surface of the first wafer as described with reference to FIGS. 2 and 9-10.

[0091] In one example, after forming the pad structure on the first wafer, dies can be formed by dicing the joined first wafer and second wafer. One of the dies can include the first die and the second die.

[0092] The wafer manufacturing process can continue with further processes such as passivation, testing, dicing, etc.

[0093] FIG. 11 shows a block diagram of a memory system device (or memory system) 1100 according to some examples of the present disclosure. The memory system device 1100 includes one or more semiconductor devices, each configured similarly to the semiconductor device 100, as shown by semiconductor devices 1111 to 1114. In some examples, the semiconductor device 100 and the semiconductor devices 1111 to 1114 are semiconductor memory devices. In some examples, the memory system device 1100 is a solid state drive (SSD).

[0094] The memory system device 1100 includes other suitable components. In one example, the memory system device 1100 includes a controller or master controller 1102. For example, the memory system device 1100 includes an interface 1101 and a controller coupled to each other as shown in FIG. 11. The memory system device 1100 can include a bus 1120 that couples the master controller 1102 to the semiconductor devices 1111 to 1114. Further, the master controller 1102 is connected to the semiconductor devices 1111 to 1114 respectively, as shown by respective control lines 1121 to 1124.

[0095] The interface 1101 is mechanically and electrically appropriately configured to connect between the memory system device 1100 and a host device and can be used to transfer data between the memory system device 1100 and the host device.

[0096] The master controller 1102 is configured to connect each semiconductor device 1111 to 1114 to the interface 1101 for data transfer. For example, the master controller 1102 is configured to provide enable / disable signals to the semiconductor devices 1111 to 1114 respectively to activate one or more of the semiconductor devices 1111 to 1114 for data transfer.

[0097] The master controller 1102 is responsible for the completion of various instructions within the memory system device 1100. For example, the master controller 1102 can perform bad block management, error checking and correction, garbage collection, and the like.

[0098] In some embodiments, the master controller 1102 is implemented using a processor chip. In some examples, the master controller 1102 is implemented using a plurality of microcontroller units (MCUs).

[0099] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent configurations do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a first die having a first contact structure formed on a surface of the first die; a first semiconductor structure disposed on a back surface of the first die and electrically connected to the first contact structure from the back surface of the first die; a first pad structure disposed on the back surface of the first die along a direction perpendicular to a main surface of the first die so as to be aligned with the first contact structure and electrically coupled to the first semiconductor structure; wherein: an end portion of the first pad structure protrudes into the first semiconductor structure without connecting to the first contact structure; an end portion of the first contact structure protrudes into the first semiconductor structure without connecting to the first pad structure.

2. a second semiconductor structure disposed on the back surface of the first die and electrically connected to a second contact structure from the back surface of the first die; a second pad structure disposed on the back surface of the first die and electrically coupled to the second semiconductor structure; a first insulating structure disposed between the first pad structure and the second pad structure and electrically insulating the first pad structure from the second pad structure.

3. a second insulating structure disposed between the first semiconductor structure and the second semiconductor structure and electrically insulating the first semiconductor structure from the second semiconductor structure.

4. The semiconductor device according to claim 1, wherein the first semiconductor structure includes a doped semiconductor material and the first pad structure includes a metal material.

5. The semiconductor device according to claim 4, wherein the doped semiconductor material is polysilicon.

6. The first die includes a core region including a vertical memory cell string, a staircase region for connecting to a gate of a memory cell in the vertical memory cell string, and a contact region including the first contact structure, and the core region, the staircase region, and the contact region are electrically insulated by respective insulating structures of an insulating layer disposed on the back surface of the first die.

7. A pad structure, further comprising a pad structure disposed on the back surface of the first die and conductively connected to the vertical memory cell string in the core region through a semiconductor structure disposed between the pad structure and the vertical memory cell string. The semiconductor device according to claim 6.

8. A second die, further comprising a second die having a peripheral circuit for the vertical memory cell string provided on a surface of the second die, wherein the first die and the second die are joined face to face. The semiconductor device according to claim 6.

9. The first contact structure on the first die is electrically coupled to an input / output circuit on the second die via a bonding structure. The semiconductor device according to claim 8.

10. A method of manufacturing a semiconductor device, Forming a first semiconductor structure on the back surface of the first die, the first semiconductor structure being conductively connected to a first contact structure from the back surface of the first die, the first die comprising a first substrate and a first contact structure formed on a surface of the first die. Forming, Forming a first pad structure on the back surface of the first die, the first pad structure being arranged to be aligned with the first contact structure along a direction perpendicular to a main surface of the first die and being conductively connected to the first semiconductor structure, an end of the first pad structure protruding into the first semiconductor structure without connecting to the first contact structure. Forming, Removing the first substrate from the back surface of the first die, an end of the first contact structure on the back surface of the first die being exposed and protruding into the first semiconductor structure without connecting to the first pad structure. Removing, including, a method.

11. The method according to claim 10, further comprising bonding the first die and the second die face to face.

12. Forming the first semiconductor structure includes Forming a semiconductor layer on the end of the first contact structure on the back surface of the first die, Forming a semiconductor structure by removing a first portion of the semiconductor layer, the first hole being formed to separate the semiconductor structure including the first semiconductor structure and the second semiconductor structure. Forming, Depositing an insulating layer on the semiconductor structure and within the first hole, wherein a part of the insulating layer within the first hole forms a second insulating structure, and one of the second insulating structures is disposed between the first semiconductor structure and the second semiconductor structure, electrically insulating the first semiconductor structure and the second semiconductor structure, and further including depositing, The method according to claim 11, wherein the first die is separated into a core region including a vertical memory cell string, a staircase region for connecting to a gate of a memory cell within the vertical memory cell string, and a contact region including the first contact structure, and the core region, the staircase region, and the contact region are electrically insulated by two of the second insulating structures.

13. Forming the first pad structure includes Removing a second portion of the insulating layer to form a second hole above each of the semiconductor structures, Forming a pad structure within the second hole above each of the semiconductor structures, the pad structure being electrically insulated by a first insulating structure of the insulating layer, the pad structure including the first pad structure, and further including forming, the method according to claim 12.

14. Forming the semiconductor layer includes depositing a doped semiconductor material that is conductive to form the semiconductor layer, and the first semiconductor structure includes the doped semiconductor material, the method according to claim 12.

15. The method according to claim 14, wherein the doped semiconductor material is polysilicon.

16. One of the pad structures is within the core region and is conductively connected to the vertical memory cell string within the core region through a semiconductor structure disposed between the one of the pad structures and the vertical memory cell string, the method according to claim 13.

17. The method according to claim 12, wherein the second die includes a peripheral circuit for the vertical memory cell string.

18. Bonding the first die and the second die face to face includes Bonding the first bonding structure on the first die to the second bonding structure on the second die, wherein the first bonding structure is conductively coupled to the first contact structure on the first die, and the second bonding structure is conductively coupled to the input / output circuit on the second die, and further comprising bonding, the method according to claim 11.

Images