Semiconductor device with deep trench insulation and trench capacitors

Abstract

To save time and costs by integrating trench insulation and a capacitor process.SOLUTION: A semiconductor device (100) comprises an insulation structure (120) and a trench capacitor (130). The insulation structure and the trench capacitor are formed by using a single resist mask for etching corresponding first and second trenches (121 and 131) different in width and depth. Dielectric liners (123-125 and 131-135) are formed on a side wall of the trench. Polysilicons (126 and 136) fill the trench, and deep doped regions (122 and 132) surround the trench. The semiconductor device also includes conductive features (160 and 162) of metallization structures (154 and 156). The conductive features form the insulation structure (120) by connecting the polysilicon (126) of the insulation structure trench (121) to the deep doped region (122).SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including an insulating structure and a capacitor.

Background Art

[0002] Insulating structures are used in integrated circuits to provide one or more transistors or other circuit components with an electrically isolated active region and to enable the use of different power domains (e.g., high-voltage circuits and low-voltage circuits) on a single IC. Deep trench insulation is one form of insulating structure. Deep trenches are also used to form trench capacitors in integrated circuits. In the manufacturing process of semiconductor devices, there are those that manufacture trench insulation and trench capacitors separately, which requires separate masking and other process steps, increasing cost and process complexity.

Summary of the Invention

[0003] This summary is provided to introduce concepts that are further illustrated and described below and is not intended to limit the scope of the claimed subject matter. The aspects described include semiconductor devices and methods of making the same. Exemplary semiconductor devices include an insulating structure and a trench capacitor, the insulating structure and the trench capacitor being formed using a single resist mask for etching corresponding first and second trenches. In one example, the trench includes a dielectric liner formed on the trench sidewalls and is filled with polysilicon. A deep doped region extends around the trench. In one example, the trench and the deep doped region extend from a semiconductor surface layer of a semiconductor structure to a buried layer. Conductive features of a metallization structure connect the polysilicon of the insulating trench to the deep doped region to form the insulating structure. A second conductive feature of the metallization structure connects to the polysilicon of the capacitor trench to form a first capacitor plate, and a further conductive feature of the metallization structure connects to the deep doped region around the capacitor trench to form a second capacitor plate. In one example, the insulating trench width is different from the capacitor trench width. In one example, the insulating trench and the capacitor trench have different depths. In one example, the trench includes a multi-layer dielectric liner such as an oxide-nitride-oxide (ONO) sub-layer. In one example, the capacitor includes a plurality of trenches surrounded by a second deep doped region and each including a corresponding dielectric sidewall liner and a polysilicon fill. In one example, the trench polysilicon is doped. One example also includes a shallow implant region that extends within the semiconductor surface layer along the sides of the insulating trench within the deep doped region.

[0004] A method for fabricating an insulating structure in a semiconductor device is described. The exemplary method includes forming a trench in a semiconductor structure, forming a deep doped region surrounding the trench, forming a dielectric on the sidewalls of the trench, filling the trench with polysilicon, and forming a conductive feature of a metallization structure, the conductive feature including connecting the polysilicon to the deep doped region to form an insulating structure. In one example, the dielectric is formed as a multi-layer dielectric liner by depositing a first oxide layer on the sidewalls of the trench, depositing a nitride layer on the first oxide layer, and depositing a second oxide layer on the nitride layer. In one example, the method further includes forming a shallow implant region along the sides of the trench within the deep doped region.

[0005] The method of manufacturing the described semiconductor device includes forming a resist layer having a first opening and a second opening on the top surface of a semiconductor structure, etching through the first opening to form a first trench, etching through the second opening to form a second trench, implanting a dopant through the first opening to form a first deep doped region surrounding the first trench, and implanting a dopant through the second opening to form a second deep doped region surrounding the second trench. This method further includes depositing a first dielectric liner through the first opening and the second opening, and depositing polysilicon through the first and second openings to fill the trenches. This method further includes forming a first conductive feature of a metallization structure, wherein the first conductive feature connects the first polysilicon to the first deep doped region to form an insulating structure, forming a second conductive feature of the metallization structure, wherein the second conductive feature connects to the second polysilicon to form a first capacitor plate, and forming a further conductive feature of the metallization structure, wherein the further conductive feature connects to the second deep doped region to form a second capacitor plate. In one example, the formation of the resist layer includes patterning the first opening with a first width and patterning the second opening with a smaller second width. In this example, the first trench is deeper than the second trench. In one example, the dielectric liner is formed as a multi-layer structure by performing a deposition process of depositing a first oxide layer on the sidewalls of the trenches, depositing a nitride layer on the first oxide layer, and depositing a second oxide layer on the nitride layer (or growing an oxide on the nitride to form an oxynitride) through a mask opening. In one example, this method further includes forming a shallow implant region along the sides of the trenches in the deep doped regions prior to the ONO deposition.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] In the drawings, like reference numerals consistently refer to like elements, and the various features are not necessarily drawn to scale. In the following description and claims, the terms "comprising," "having," "including," or variations thereof are as inclusive as the term "comprising" and mean "including but not limited to." Also, the term "coupled" includes indirect or direct electrical or mechanical connection or combinations thereof. For example, when a first device is coupled to or coupled with a second device, this connection can be by direct electrical connection or by indirect electrical connection through one or more intervening devices and connections. The various features of this example can be used in connection with various different semiconductor devices, including but not limited to integrated circuits having multiple electronic components and single-component semiconductor devices (e.g., single transistor products, single diode products, etc.).

[0011] The exemplary devices and fabrication methods provide process integration for both trench insulation and high density trench capacitors fabricated using a shared resist mask to save fabrication time and cost. In some examples, trenches are etched, implants are performed into deep doped regions surrounding the trenches, and liners are applied to and filled in the trenches using thick photoresist and a hard mask that is patterned with an opening for the capacitor trench and a wider opening for the insulation structure trench. The examples described provide a first and a second capacitor plate for a capacitor trench structure, and a metallization layout structure for providing connected polysilicon and deep doped regions for an insulation trench structure. The examples described use one mask and narrow the insulation (e.g., deep n region)-insulation spacing using self-aligned deep doped region implantation onto the deep trench sidewalls to facilitate the formation of deep trench insulation features as well as high density trench capacitors.

[0012] Figures 1 and 2 illustrate an exemplary integrated circuit semiconductor device 100 that includes two metal oxide semiconductor (MOS) transistors 101. In some examples, stand-alone discrete transistor semiconductor devices having a single transistor may also be included. The transistor 101 in FIG. 1 has a single gate, source, and drain finger structure. In other implementations, the transistor may be constructed using multiple finger structures surrounding a central finger, such as a source-centered configuration, a drain-centered configuration, etc. The concepts of deep trench insulation and trench capacitors in this description may be implemented in combination with any type or form of transistor, such as, for example, MOS transistors, bipolar transistors. Also, various aspects of this description may be used in combination with drain extended MOS transistors (not shown). The examples described include doped regions of various semiconductor structures that may be characterized as p-doped and / or n-doped regions or portions, and regions having a particular type of majority carrier dopant such as an n-type dopant or a p-type dopant.

[0013] Transistor 101 is fabricated on and / or within semiconductor substrate 102. The semiconductor substrate 102 in one example is a silicon wafer, a silicon-on-insulator (SOI) substrate, or other semiconductor structure. In one example, the substrate 102 is a p-doped silicon substrate or wafer having a first (e.g., top) side 103, various buried layers 104, 106 formed therein, and a second (e.g., bottom) side 105. In another possible implementation, the substrate 102 includes one or more epitaxial silicon layers (not shown) formed on the top surface, and one or more buried layers 104, 106 are formed in the epitaxial layers of the substrate. In the illustrated example, the substrate 102, the buried layers 104 and 106, and the upper semiconductor surface layer (e.g., body region 108) constitute a semiconductor structure. The exemplary semiconductor structure includes a first doped layer 106 including a p-type majority carrier dopant. In one implementation, the p-type layer includes a portion into which boron is implanted to form a p-type buried layer (PBL) having an upper or top side 107. The semiconductor surface layer 108 extends over (e.g., directly over) the p-type buried layer 106 and includes the upper side 103 of the semiconductor structure. The illustrated layer 104 (e.g., n-type buried layer or NBL) includes an n-type majority carrier dopant. The NBL 104 extends from under the PBL 106 along the vertical Z direction toward the second side 105. In one example, a first epitaxial silicon layer is formed on the upper surface of the silicon wafer substrate 102, and an n-type dopant (e.g., phosphorus, etc.) is implanted into all or part of the first epitaxial layer to form the NBL 104. In this example, a second epitaxial silicon layer is formed on the first epitaxial layer, and a p-type dopant (e.g., boron, etc.) is implanted into all or part of the second epitaxial layer to form a p-type buried layer 106 having an upper side 107. In one example, the PBL region 106 is formed using ion implantation through the first EPI surface. The illustrated surface layer 108 has a p-type majority carrier dopant and extends downward along the Z direction from the first side 103.

[0014] Transistor 101 is formed on or in the semiconductor surface layer 108 of the active region 110 of the semiconductor structures 102, 104, 106, 108. The exemplary semiconductor surface layer 108 includes a p-type majority carrier dopant. The illustrated device 100 includes an outer oxide insulation structure 118 that surrounds the transistor 101 along a first (e.g., top) side 103 in the semiconductor surface layer 108. The oxide structure 118 in one example is an example of a shallow trench isolation (STI) structure disposed laterally outward of the transistor 101. In the illustrated example, the STI structure 118 defines an end of the active region 110 of the semiconductor substrate 102 where the transistor 101 is formed.

[0015] The illustrated device 100 includes a trench-based insulation structure 120 referred to as a deep trench insulation structure. The deep trench insulation structure 120 of FIG. 1 is adjacent to the STI structure 118 and laterally surrounds or encloses the transistor 101 and the active region 110 of the semiconductor structure. The insulation structure 120 includes a first trench 121 that extends downward from the first side 103 through the semiconductor structures 102, 104, 106, 108 to the buried layer 104. The insulation structure 120 also includes a first deep doped region 122 having an n-type majority carrier dopant (e.g., phosphorus). The first deep doped region 122 surrounds the first trench 121 and extends from the semiconductor surface layer 108 to the buried layer 104.

[0016] The insulating structure 120 also includes a first dielectric liner that extends from the semiconductor surface layer 108 to the buried layer 104 along the sidewall of the first trench 121. Any single-layer or multi-layer dielectric liner can be used. In one example, the first dielectric liner includes a first oxide layer 123, a nitride layer 124, and a second oxide layer 125. The first oxide layer 123 (e.g., silicon dioxide or SiO2) extends from the semiconductor surface layer 108 to the buried layer 104 along the sidewall of the first trench 121. The nitride layer 124 (e.g., silicon nitride or silicon oxynitride) extends from the semiconductor surface layer 108 to the buried layer 104 along the first oxide layer 123. The second oxide layer 125 (e.g., silicon dioxide or SiO2) extends from the semiconductor surface layer 108 to the buried layer 104 along the nitride layer 124.

[0017] The insulating structure 120 also includes a first polysilicon 126 that extends inside the first dielectric liners 123, 124, 125. The first polysilicon 126 fills the first trench 121 up to the top side 103 of the semiconductor surface layer 108. The first polysilicon 126 in one example includes a p-type majority carrier dopant (e.g., boron). In the examples of FIGS. 1 and 2, the deep trench insulating structure 120 is formed as a ring structure that laterally surrounds the transistor 101. As shown in FIG. 1, the first trench 121 has a first depth 127 and a first width 128. The semiconductor device 100 also includes a shallow implant region 129 (e.g., a shallow n-well implanted with phosphorus) having an n-type majority carrier dopant. The shallow implant region 129 extends within the semiconductor surface layer 108 along the side of the first trench 121 within the first deep doped region 122. In one example, the shallow implant is also used to form the n-type source / drain features (not shown) of the lower case transistors of the device 100.

[0018] The illustrated device 100 also includes one or more trench-based capacitors. In one example, the trench capacitor 130 can be constructed using a single trench. In the examples of FIGS. 1 and 2, the capacitor 130 includes a plurality of second trenches 131 that individually extend through the semiconductor structures 102, 104, 106, 108 to the buried layer 104. Each of the second trenches 131 is surrounded by a second deep-doped region 132. FIG. 1 shows three trenches 131 that extend from the first side 103 through the semiconductor structure to the buried layer 104. The second trench 132 has a second depth 137 and a second width 138. The first (insulating) trench 121 has a first width 128 that is greater than the second (capacitor trench) width 138 in the devices of FIGS. 1 and 2. The first width 128 of the first trench 121 is greater than the second width 138 of the capacitor trench 131. In one example, the first width 128 of the first trench 121 is about 1.5 μm, for example, from 1.35 μm to 1.65 μm, and the second width 138 of the capacitor trench 131 is about 1.2 μm, for example, from 1.05 μm to 1.35 μm.

[0019] The exemplary capacitor 130 further includes, in each of the trenches 131, a second dielectric liner (e.g., layers 133, 134, and 135). The second dielectric liner extends along the sidewalls of the second trench 131 from the semiconductor surface layer 108 to the buried layer 104. The exemplary second dielectric liner is a multi-layer structure including a third oxide layer 133 that extends along the sidewalls of the second trench 131 from the semiconductor surface layer 108 to the buried layer 104. The exemplary second dielectric liner also includes a second nitride layer 134 that extends along the third oxide layer 133 from the semiconductor surface layer 108 to the buried layer 104, and a fourth oxide layer 135 that extends along the second nitride layer 134 from the semiconductor surface 108 to the buried layer 104.

[0020] Capacitor 130 also includes a second deep-doped region 132 into which an n-type majority carrier dopant (e.g., phosphorus) is implanted. The second deep-doped region 132 surrounds the second trench 131 and extends from the semiconductor surface layer 108 to the buried layer 104. In addition, capacitor 130 includes a second polysilicon 136 having a p-type majority carrier dopant (e.g., boron). The second polysilicon 136 extends inside the second dielectric liners 133, 134, 135 and fills the second trench 131 up to the top surface 103 of the semiconductor surface layer 108. Capacitor 130 also includes a shallow implantation region 129 having a majority carrier dopant of the second conductivity type. The shallow implantation region 129 extends within the semiconductor surface layer 108 between the second trenches 131 within the second deep-doped region 132.

[0021] Semiconductor device 100 includes a metallization structure that extends over the semiconductor surface layer 108. The metallization structure includes a conductive feature that connects the first polysilicon 126 to the first deep-doped region 122 for the trench-based insulation structure 120, a second conductive feature that is connected to the second polysilicon 136 to form the first capacitor plate, and a further conductive feature that is connected to the second deep-doped region 132 to form the second capacitor plate of capacitor 130. The metallization structure includes a first dielectric structure layer 154 formed over the semiconductor structure and a multi-level upper metallization structure 156. In one example, the first dielectric structure layer 154 is a pre-metal dielectric (PMD) layer disposed over the transistor 101 and the upper surface of the semiconductor structure. In one example, the first dielectric structure layer 154 includes silicon dioxide (SiO2) deposited over the transistor 101, the semiconductor surface layer 108, and the STI structure 118. The metallization structures 154, 156 cover the transistor 101 and provide internal and / or external electrical interconnections to the source, drain, and gate terminals of the transistor.

[0022] The PMD layer 154 includes a contact structure 160 (e.g., tungsten) that provides a direct electrical connection (e.g., a direct contact or a connection through a silicide layer such as CoSi2 not shown) to one or more features of the transistor 101. The PMD material layer 154 is formed over the illustrated structure, and the contact structure 160 is formed therein to provide electrical interconnect access to one or more further upper metallization layers 158 and 164 - 168. In one example, silicide is formed over the top surfaces of the source, drain, and gate electrode structures of the transistor 101, over the top surfaces of the polysilicon features 126, 136, and also down to the deep doped regions 122, 132. The contacts 160 of the PMD layer 154 are connected to the polysilicon features 126, 136, and to the deep doped regions 122, 132 of the insulating structure 120 and the capacitor 130.

[0023] The upper metallization structure 156 includes one or more layers. In the illustrated example, as shown in FIG. 1, the upper metallization structure 156 includes a first metallization layer 158 formed over the PMD layer 154, and further metallization layers 164, 165, 166, 167, and 168 formed progressively over the previous layer. The devices 100 of FIGS. 1 and 2 are shown as a wafer 170 before singulation and packaging, but the illustrated structure represents the described features after being separated as a die for packaging. The exemplary die 170 is an integrated circuit with multiple components such as the transistor 101, but implementations of other stand - alone discrete semiconductor devices can include a single transistor or other electronic components including the insulating structure 120 and at least one capacitor 130.

[0024] The upper metallization structure 156 is six-layered and includes a first layer 158, which is referred to herein as an intermediate or inter-level dielectric (ILD) layer. Different numbers of layers may be used in different implementations. In one example, the first ILD layer 158 and the other ILD layers of the upper metallization structure 156 are formed of silicon dioxide (SiO2) or other suitable dielectric materials. In certain implementations, the individual layers of the multi-layer upper metallization structure 156 are formed in two stages and include a metal-inside-dielectric (IMD, not shown) sub-layer with conductive metal routing features or lines 162 (e.g., aluminum, copper, etc.), and an ILD sub-layer that overlaps the IMD sub-layer with conductive contacts or plugs 163 (e.g., tungsten via). The individual IMD and ILD sub-layers may be formed of any suitable one or more dielectric materials, such as SiO2-based dielectric materials. The first layer 158 and subsequent layers in the upper metallization structure 156 include conductive metallization interconnect structures 162, referred to as lines, formed on the top surface of the underlying layer. In this example, the first layer 158 and subsequent ILD layers also include conductive vias 163, such as tungsten or aluminum, that provide electrical connection from the metallization features 162 of the individual layers to the overlying metallization layer.

[0025] The example of FIG. 1 includes a second layer 164 disposed on top of the first layer 158. The ILD layer 158 includes conductive interconnect structures 162 and vias 163. The structures 162, 163 may be the same metal or different metals in various implementations. The individual layers may be constructed using any suitable metallization fabrication process, such as a single damascene or dual damascene process. The illustrated structure includes additional metallization levels, which include corresponding dielectric layers 165, 166, and 167, and a top or uppermost metallization layer 168. The individual layers 165 - 168 in this example include conductive interconnect structures 162 and associated vias or contact plugs 163.

[0026] A semiconductor structure, an electronic component (e.g., transistor 101), a capacitor 130, a first dielectric structure layer 154, and an upper metallization structure 156 form a wafer or die 170 having an upper or surface 171. The upper 171 of the metallization structure 156 forms the upper side of the wafer or die 170. The top metallization layer 168 includes conductive features 169 such as top aluminum vias. The conductive features 169 include the sides or surface of the upper 171 of the wafer or die 170 at the top of the top metallization layer 168. Any number of conductive features 169 may be provided. One or more of the conductive features 169 may be electrically coupled to an electronic component such as one of the transistors 101.

[0027] In one example, the upper ILD dielectric layer 168 includes one or more passivation layers 173 (e.g., a protective overcoat (PO) and / or a passivation layer), e.g., silicon nitride (SiN), silicon oxynitride (SiO x N y ), or silicon dioxide (SiO2). In one example, the one or more passivation layers 173 include one or more openings that expose a portion of the conductive features 169 to enable electrical connection to corresponding contact structures 174 of the features 169. The contact structures 174 extend outwardly (e.g., upwardly along the "Z" direction of FIG. 17) from the upper 171 of the metallization structure 156. Individual contact structures 174 in one example include a conductive seed layer such as copper that extends outwardly from the upper 171 of the metallization structure 156. In one example, the contact structures 174 include titanium (Ti) or titanium tungsten (TiW).

[0028] The metallization structures 154, 156 include first conductive features 160, 162 of the metallization structures 154, 156 that connect the first polysilicon 126 to the first deep doped regions 122. Thereby, an insulating trench structure 120 is provided that electrically insulates the active region 110 of the semiconductor structure from the capacitor 130 and from other regions of the wafer or die 170. In addition, the metallization structure includes second conductive features 160, 162 that are connected to the second polysilicon 136 to form the first capacitor plate, and further conductive features 160, 162 that are connected to the second deep doped region 132 to form the second capacitor plate. The metallization structures 154, 156 enable further conductive connections (not shown) for connecting the first and second capacitor plates to other circuit elements within the wafer or die 170 and / or for providing an external connection to one or both of the first and second capacitor plates.

[0029] FIG. 2 shows a top view of a portion of the device 100. In the illustrated example, the insulating structure 120 extends around the lateral periphery of the active region 110 and also extends around three sides of the capacitor region. In this example, the capacitor region includes a plurality of capacitor trenches 311, three of which are shown in the side view of FIG. 1. In one example, the capacitor trench width 138 is about 1.2 μm and the spacing distance between adjacent capacitor structures is about 0.6 μm. In one example, a shallow n-well implant (e.g., region 129 of FIG. 1, not shown in FIG. 2) extends about 0.1 μm into the capacitor region and surrounds the capacitor region by about 0.65 μm. In one example, the NBL 104 extends into the capacitor region as shown in FIG. 1. In another example (not shown), the capacitor region is surrounded by the NBL 104. In one example, a silicide block layer (not shown) extends about 0.25 μm beyond the capacitor region and extends about 0.255 μm within the capacitor region.

[0030] Referring also to FIGS. 3 - 18, FIG. 3 shows a method 300 for fabricating an electronic device such as an integrated circuit or a stand - alone device. The illustrated method 300 also includes a process or method for fabricating an insulating structure in a semiconductor device. FIGS. 4 - 18 show the integrated circuits of FIGS. 1 and 2 at various stages of fabrication according to method 300. Method 300 begins at 302, where an n - type implantation is performed to form an n - doped region such as NBL region 104 in FIG. 1.

[0031] In one example, at 302, a first epitaxial silicon layer is formed on the upper surface of a silicon wafer substrate 102, and an n - type dopant (e.g., Sb, etc.) is implanted into all or part of the first epitaxial layer to form NBL 104. In one example, at 303, a p - type dopant (e.g., boron, etc.) is implanted into all or part of the first epitaxial layer to form a p - type buried layer 106 with an upper side 107. In one example, the PBL region 106 is formed at a depth set by using a high implantation energy by ion implantation through the final silicon surface (e.g., the top of the second epitaxial layer). In one example, at 304, a further epitaxial silicon deposition process is performed to deposit a second epitaxial silicon layer on the first epitaxial layer. At 306, a p - type majority - carrier dopant (e.g., boron) is implanted into the semiconductor surface layer 108 (e.g., the portion labeled as P - body), and the semiconductor surface layer 108 extends downward along the Z - direction from the first side 103 of PBL 106 to the upper side 107.

[0032] Method 300 also includes, at 306, depositing an etch stop layer. FIG. 4 illustrates an example in which a deposition process 402 is performed to deposit a nitride or oxynitride or oxide layer 400 on a first side 103 of a semiconductor structure. In one example, layer 400 functions as an etch stop layer for subsequent planarization such as chemical mechanical polishing (CMP). In one example, the etch stop layer 400 includes a pad oxide formed to a thickness of about 150 Å, such as 100 - 160 Å, and a nitride formed to a thickness of about 0.2 μm on the pad oxide.

[0033] Method 300 further includes, at 308, depositing and patterning a thick resist layer that includes an opening for an insulating structure and a second opening for a trench capacitor. FIG. 5 shows an example in which process 503 is performed. Process 503 deposits and patterns a resist mask 500 on a hard mask layer 400 on a first surface 103 of a semiconductor structure. The process 503 in one example includes forming a resist layer 500, patterning a first opening 501 with a first width 128, and patterning a second opening 502 with a second width 138, where the first width 128 is wider than the second width 138. The first opening 501 is patterned with a width 128 corresponding to a desired width of a predicted insulating structure trench 121 (e.g., FIG. 1) on a predicted insulating structure 120. The second opening 502 is patterned with a width 138 corresponding to a desired width of a predicted capacitor trench 131 (FIG. 1) on a predicted capacitor structure 130. In one example, the width 128 of the first resist opening 501 is about 1.5 μm and the width 138 of the second resist opening 502 is about 1.2 μm.

[0034] Method 300 continues, at 310, with deep trench etching through nitride 400, and silicon of semiconductor surface layer 108, through PBL 106, and through at least a portion of NBL 104 to form trenches 121 and 311 using the patterned resist 500 as an etch mask. FIG. 6 shows an example where an etching process 600 etches a first trench 121 that extends into the buried layer 104 through the semiconductor surface layer 108 through a resist opening 501. The etching process 600 simultaneously etches through a second opening 502 to form a trench 131 that extends into NBL 104. In the illustrated example, the first trench width 128 generally corresponds to the dimension of the first opening 501, and the second trench width 138 generally corresponds to the dimension of the second opening 502. The wider first opening 501 extends the first trench 121 to a first depth 127 (e.g., from 6.2 μm to 7.2 μm, about 6.8 μm, which is deeper than the second depth 137 of the second trench 131).

[0035] Subsequently, at 312 and 314, method 300 further includes one or more deep trench implants to form a first deep doped region 122 surrounding the first trench 121 and a second deep doped region 132 surrounding the second trench 131. FIGS. 7 and 8 show an example including performing a first implant process 700 using the remaining resist mask 500 to simultaneously implant an n-type dopant (e.g., phosphorus) through openings 501 and 502 to form the first deep doped region 122 and the second deep doped region 132, respectively. The first deep doped region 122 surrounds the first trench 121 and extends from the semiconductor surface layer 108 to the buried layer 104. The second deep doped region 132 surrounds the second trench 132 and extends from the semiconductor surface layer 108 to the buried layer 104.

[0036] In one example, the first implantation process at 312 is an angled deep N-trench sidewall implantation. FIG. 7 shows an angled implantation process 700 that implants phosphorus or other n-type dopants through resist openings 501, 502 into the sidewalls of trenches 121 and 131 at a dose of 9×104 cm-3 and an implantation energy of 200 keV, forming a first deep dopant region 122 and a second deep dopant region 132 by rotating four times at a twist angle of 45 degrees with respect to the layout direction (e.g., with respect to the direction of the source, drain, and gate fins of the transistor) at an implantation angle of 16 degrees.

[0037] At 314, a second implantation is performed to implant the regions 122 and 132 at the bottom. FIG. 8 shows an implantation step 800 of implanting phosphorus or other n-type dopants through resist openings 501 and 502 and further implanting into the silicon below the bottoms of trenches 121 and 131 at a dose of 9×104 cm-3, an implantation energy of 50 keV, and an implantation angle of 0 degrees.

[0038] In one example, at 316 in FIG. 3, an annealing process is performed. In this annealing process, the silicon on the trench sidewalls is oxidized to form a dummy or sacrificial oxide layer, for example, up to a thickness of 150 Å on the sidewalls of trenches 121 and 311. In one example, at 316, the sacrificial oxide is removed using a wet cleaning process with 50% overetching, removing about 300 Å of material from the sidewalls of trenches 121 and 311. In one example, the overetching at 316 removes the deposited sacrificial oxide and the original silicon that may have been damaged during implantation at 312 and / or 314.

[0039] The exemplary method 300 continues, at 318, 320, and 322, with a deposition process for forming a dielectric liner on the sidewalls of trenches 121 and 311. The dielectric liner deposition process deposits a dielectric material through the first opening 501 and the second opening 502 of the remaining resist mask 500. Any suitable dielectric can be used to form the capacitor dielectric in the completed trench capacitor 130. The dielectric liner can be a single-layer or multi-layer structure. FIGS. 9-11 illustrate a multi-step deposition for forming an oxide-nitride-oxide (ONO) dielectric liner on each of trenches 121 and 131.

[0040] At 318 in FIG. 3, a first oxide deposition is performed, whereby a first oxide layer is formed on the sidewalls of trenches 121 and 311. FIG. 9 shows an example where an oxidation annealing process 900 is performed at 850° C., whereby silicon dioxide 123 (e.g., SiO2) is deposited on the sidewall of the first trench 121 and silicon dioxide 133 is deposited on the sidewall of the second trench. In one example, process 900 (850° C.) causes thermal oxidation of the trench sidewall silicon, and the first oxide layers 123 and 133 are formed to a thickness of about 65 Å, e.g., 60 Å to 70 Å.

[0041] At 320, a second deposition process (e.g., nitride deposition) is performed, whereby a nitride layer is deposited on the first oxide layer along the sidewalls of trenches 121 and 311. FIG. 10 shows an example where a deposition process 1000 (e.g., deposition temperature of 650° C.) deposits a nitride material 124 (e.g., silicon nitride, silicon oxynitride) on the first oxide layer 123 of the first trench 121 through the first and second openings of the resist layer 500 and deposits a nitride material 134 on the first oxide layer 133 along the sidewall of the second trench 131 through the first and second openings of the resist layer 500. In one example, process 1000 forms the nitride material layers 124 and 134 to a thickness of about 140 Å, e.g., 106 Å to 166 Å.

[0042] At 322, a third deposition process (e.g., oxide deposition) is performed, whereby a second oxide layer is deposited on the nitride layer along the sidewalls of trenches 121 and 311. FIG. 11 shows an example where a wet oxidation process 1100 grows a second oxide layer such as oxynitride 125 through a first opening on the nitride layer 124 of the first trench 121. The deposition process 1100 in this example deposits a second nitride layer 135 on the nitride layer 134 of the second trench 132 through a second opening in the resist layer 500. In one example, the process 1100 forms the second oxide material layers 125 and 135 to a thickness of about 20 Å, e.g., 10 Å to 30 Å.

[0043] The exemplary method 300 continues, at 324 and 326, with the deposition of polysilicon to fill trenches 121 and 311. FIG. 12 shows an example where a first polysilicon deposition process 1200 (e.g., the process at 324 in FIG. 3) deposits a first polysilicon 126 through a first opening in the resist layer 500 to fill the first trench 121. The first polysilicon deposition process 1200 also deposits a second polysilicon 136 through a second opening in the resist layer 500 to fill the second trench 131. The initial deposition process 1200 in one example deposits p-doped polysilicons 126, 136 having a p-type majority carrier dopant (e.g., boron) to a thickness of 3400 Å.

[0044] In 326, a second polysilicon deposition is performed in which polysilicon 126 is deposited to fill trench 121 and polysilicon 136 is deposited to fill the second trench 311. FIG. 13 shows an example in which the second polysilicon deposition process 1300 deposits on the doped polysilicon to fill trenches 121 and 131 to a thickness of, for example, about 10,000 Å. In one example, for filling trenches 121 and 131, the target polysilicon deposition thickness is about 13,400 Å, such as between 10,900 Å and 15,900 Å. As shown in FIGS. 12 and 13, in one example, the initial polysilicon deposition process 1200 and the trench fill deposition process 1300 form polysilicons 126 and 136 on both sides of the device 100, including the deposition along the bottom side 105 of the semiconductor structure.

[0045] Following 328 - 332 in FIG. 3, method 300 further includes a backside polysilicon removal or stripping step at 328. In one example, a wet etching process (not shown) is performed to strip excess polysilicon from the bottom side 105 of the semiconductor structure. At 330, the top side of the wafer is planarized. FIG. 14 shows an example in which a chemical mechanical polishing (CMP) process 1400 removes the polysilicon remaining on the top side 103 of the wafer and planarizes the top side of the wafer. The CMP process 1500 stops on the nitride hard mask layer 400 as shown in FIG. 14. At 332, a wet etching process is performed to strip the remaining nitride hard mask layer. FIG. 15 shows an example in which a wet etching process 1500 is performed to remove the remaining nitride layer from the top side 103 of the wafer.

[0046] Method 300 also includes a shallow trench isolation (STI) process at 334. FIG. 16 shows an example in which an STI fabrication process 1600 is performed that etches trenches and fills the trenches with an oxide material 118. In one example, the STI process includes growing a pad oxide, depositing a nitride layer (not shown) using low-pressure chemical vapor deposition (LPCVD), patterning and etching the trenches in the liners of trenches 121 and 131 and the silicon of the surface layer in the silicon, growing a liner oxide of the STI trenches to repair the silicon and round sharp corners, followed by plasma enhanced CVD (PECVD) deposition of TEOS oxide. This process further includes another chemical mechanical polishing of the trench oxide using the nitride as an etch stop, followed by removal of the nitride etch stop layer.

[0047] At 336, a transistor fabrication process is performed that includes fabricating transistor 101. FIG. 17 shows a simplified example in which a transistor fabrication process 1700 is performed to create a transistor structure 101. In one example, the transistor fabrication at 336 includes performing an implantation process that implants n-type majority carriers into the semiconductor surface layer 108 to form a shallow implantation region 129 that extends along the side of the first trench 121 within the deep doped region 122. In one example, the same implantation process is used to form features of the N-p type source / drain regions of the lower stage of transistor 101 or other components (not shown) of wafer 170.

[0048] In 338 of FIG. 3, method 300 continues with metallization to form one or more layers of a dielectric with conductive metal features to provide interconnections to the transistors and / or other components of wafer 170. The metallization process in 338 includes forming conductive features to provide capacitor plates for trench capacitor 130 and also interconnecting the features of trench-based insulating structure 120. FIG. 18 illustrates a portion of metallization process 1800 that forms first conductive features 160, 162 that extend over semiconductor surface layer 108 and connect first polysilicon 126 to first deep doped region 122 to form trench-based insulating structure 120. Metallization process 1800 also forms second conductive features 160, 162 that connect to second polysilicon 136 to form a first capacitor plate and also forms additional conductive features 160, 162 of metallization structures 154, 156 that connect to a second deep doped region to form second capacitor region 132.

[0049] The process 300 of FIG. 3 also includes die singulation in 340 to separate one or more product dies from wafer 170. The process in 340 also includes packaging to provide one or more finished semiconductor devices such as stand-alone components and / or integrated circuits.

[0050] Method 300 provides an integrated process for simultaneously fabricating both the trench insulation structure 120 and the high-density trench capacitor 130 using a common resist mask 500. In an exemplary implementation, a thick resist mask 500 is also used to facilitate the processing of both trench types. By using a thick common mask and a similar trench structure architecture for both the insulation structure 120 and the trench capacitor 130, process steps and cost economies are realized. Also, in some examples, density advantages are promoted compared to the use of non-trench insulation structures using deep well implantation. In this regard, deep implanted insulation features that extend into the buried layer within the semiconductor structure (e.g., a deep n-well where implantation and diffusion are performed and extend into the NBL 104) are accompanied by significant lateral diffusion, thereby expanding the lateral extent of the insulation feature. In some examples, the need for a separate deep implant mask is eliminated, and by using a trench pillar type insulation layout, it is also easier to reduce the resistance of the deep doped region. In some examples, in addition to the fabrication cost and time advantages by simultaneously constructing the insulation structure 120 and the trench capacitor 130, lateral region control for the insulation feature 120 for a narrowed insulation-insulation spacing using self-aligned deep doped region implantation onto the deep trench sidewall is provided. These features provide significant advantages, especially in combination with a simple modification of the metallization structure by shorting the bottom plate and the top plate (e.g., the deep doped region 122 and the p-type polysilicon structure 126) for forming the insulation structure 120. Modifications within the scope of the claims are possible, and other embodiments are possible for the described embodiments.

Claims

1. A semiconductor device comprising: a semiconductor layer of a first conductivity type; an embedded layer of a second conductivity type opposite to the first conductivity type, the embedded layer being disposed below the semiconductor layer; a first trench extending through the semiconductor layer into the embedded layer; a second trench extending through the semiconductor layer into the embedded layer; a first doped region of the second conductivity type extending through the semiconductor layer into the embedded layer and surrounding the first trench; a second doped region of the second conductivity type extending through the semiconductor layer into the embedded layer and surrounding the second trench; a first dielectric liner on a sidewall of the first trench; a second dielectric liner on a sidewall of the second trench; a first polysilicon in the first trench; a second polysilicon in the second trench; a first conductive feature extending over the semiconductor layer and connecting the first polysilicon to the first doped region; a second conductive feature extending over the semiconductor layer and connected to the second polysilicon; a third conductive feature extending over the semiconductor layer and connected to the second doped region. A semiconductor device as described above.

2. The semiconductor device according to Claim 1, wherein the first and second dielectric liners each include a first oxide layer, a nitride layer on the first oxide layer, and a second oxide layer on the nitride layer.

3. The semiconductor device according to Claim 1, wherein the first trench has a first depth and the second trench has a second depth shallower than the first depth.

4. The semiconductor device according to Claim 1, further comprising a shallow implantation region extending along a side portion of the first trench within the first doped region.

5. The semiconductor device according to Claim 1, further comprising a shallow implantation region extending along a side portion of the second trench within the second doped region.

6. The semiconductor device according to Claim 1, wherein the first trench has a first width and the second trench has a second width narrower than the first width.

7. The semiconductor device according to Claim 1, wherein A semiconductor device, wherein the second conductive feature corresponds to a first plate of a capacitor, and the third conductive feature corresponds to a second plate of the capacitor.

8. A semiconductor device according to Claim 1, wherein the first trench is part of an isolation structure, and the second trench is part of a capacitor.

9. A semiconductor device, comprising a semiconductor structure, a semiconductor layer of a first conductivity type, an embedded layer of a second conductivity type opposite to the first conductivity type, the embedded layer being disposed below the semiconductor layer, the semiconductor structure including the same, a metallization structure extending over the semiconductor layer, an isolation structure, a first trench extending through the semiconductor layer to the embedded layer, a first dielectric liner extending from the semiconductor layer to the embedded layer along a sidewall of the first trench, a first polysilicon of the first conductivity type, the first trench being filled up to a top side of the semiconductor layer with the first polysilicon, a first doped region of the second conductivity type, the first doped region extending from the semiconductor layer to the embedded layer and surrounding the first trench, a first conductive feature of the metallization structure, the first conductive feature connecting the first polysilicon to the first doped region, the isolation structure including the same, a capacitor, a second trench extending through the semiconductor layer to the embedded layer, a second dielectric liner extending from the semiconductor layer to the embedded layer along a sidewall of the second trench, a second polysilicon of the first conductivity type, the second trench being filled up to a top side of the semiconductor layer with the second polysilicon, a second doped region of the second conductivity type, the second doped region extending from the semiconductor layer to the embedded layer and surrounding the second trench, a second conductive feature of the metallization structure, the second conductive feature being connected to the second polysilicon so as to form a first plate of the capacitor, a third conductive feature of the metallization structure, the third conductive feature being connected to the second doped region so as to form a second plate of the capacitor, the capacitor including the same, a semiconductor device including the same.

10. A semiconductor device according to Claim 9, A semiconductor device, wherein the first trench has a first depth and the second trench has a second depth shallower than the first depth.

11. The semiconductor device according to claim 9, A semiconductor device, wherein the first trench has a first width and the second trench has a second width narrower than the first width.

12. The semiconductor device according to claim 9, wherein the first dielectric liner includes a first oxide layer extending from the semiconductor layer to the buried layer along the sidewall of the first trench, a first nitride layer extending from the semiconductor layer to the buried layer along the first oxide layer, and a second oxide layer extending from the semiconductor layer to the buried layer along the first nitride layer; A semiconductor device, wherein the second dielectric liner includes a third oxide layer extending from the semiconductor layer to the buried layer along the sidewall of the second trench, a second nitride layer extending from the semiconductor layer to the buried layer along the third oxide layer, and a fourth oxide layer extending from the semiconductor layer to the buried layer along the second nitride layer.

13. The semiconductor device according to claim 9, wherein the second trench is one of a plurality of second trenches of the capacitor, and each of the plurality of second trenches is surrounded by the second doped region.

14. The semiconductor device according to claim 9, a first shallow implantation region extending along a side portion of the first trench within the first doped region; a second shallow implantation region extending along a side portion of the second trench within the second doped region; A semiconductor device further comprising:

15. A method comprising: forming a resist layer on a surface of a semiconductor structure, the resist layer including a first opening and a second opening, the semiconductor structure including: a semiconductor layer of a first conductivity type; a buried layer of a second conductivity type opposite to the first conductivity type, the buried layer being disposed below the semiconductor layer; forming the resist layer; performing an etching process, the etching process including etching through the first opening to form a first trench extending from the semiconductor layer to the buried layer, and etching through the second opening to form a second trench extending from the semiconductor layer to the buried layer. Performing a first implantation process, wherein the first implantation process injects a majority carrier dopant of the second conductivity type through the first opening to form a first doped region that extends from the semiconductor layer to the buried layer and surrounds the first trench, and injects a majority carrier dopant of the second conductivity type through the second opening to form a second doped region that extends from the semiconductor layer to the buried layer and surrounds the second trench; performing the first implantation process; Performing a first process, wherein the first process forms a first dielectric liner on the sidewalls of the first trench and forms a second dielectric liner on the sidewalls of the second trench; performing the first process; Performing a second process, wherein the second process deposits a first polysilicon that fills the first trench and deposits a second polysilicon that fills the second trench; performing the second process; Forming a first conductive feature that extends over the semiconductor layer, wherein the first conductive feature connects the first polysilicon to the first doped region; forming the first conductive feature; Forming a second conductive feature that extends over the semiconductor layer, wherein the second conductive feature is connected to the second polysilicon; forming the second conductive feature; Forming a third conductive feature that extends over the semiconductor layer, wherein the third conductive feature is connected to the second doped region; forming the third conductive feature; A method comprising.

16. The method according to claim 15, wherein Performing the first process comprises Performing a first heat treatment to form a first oxide layer on the sidewalls of the first and second trenches; Performing a second heat treatment to form a nitride layer on the first oxide layer; Performing a third heat treatment to form a second oxide layer on the nitride layer; A method comprising.

17. The method according to claim 16, wherein The third heat treatment includes a wet oxidation treatment.

18. The method according to claim 15, wherein The first opening has a first width and the second opening has a second width that is narrower than the first width.

19. The method according to claim 15, wherein A method, wherein the first trench has a first depth and the second trench has a second depth shallower than the first depth. **Claim 20** The method according to claim 15, wherein a second implantation process is performed, the second implantation process including implanting a majority carrier dopant of the second conductivity type into the semiconductor layer to form a first shallow implantation region extending along a side portion of the first trench within the first doped region and a second shallow implantation region extending along a side portion of the second trench within the second doped region.

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