Semiconductor device

Abstract

To provide a semiconductor device having excellent electric characteristics and high reliability.SOLUTION: A semiconductor device has a semiconductor layer, a first insulation layer, a second insulation layer, a metal oxide layer, and a conductive layer. The first insulation layer, the metal oxide layer, and the conductive layer are stacked on the semiconductor layer in this order. Ends of the first insulation layer are located more inside than ends of the semiconductor layer. Ends of the metal oxide layer are located more inside than ends of the first insulation layer. Ends of conductive layer are located inside than ends of the metal oxide layer. The second insulation layer is preferably provided to cover the semiconductor layer, the first insulation layer, the metal oxide layer, and the conductive layer. The semiconductor layer has a first area, a pair of second areas, and a pair of third areas. The first area overlaps the first insulation layer and the metal oxide layer. The second area sandwiches the first area, and overlaps the first insulation layer, but does not overlap the metal oxide layer. The third area sandwiches the first area and the pair of second areas, and does not overlap the first insulation layer. The third area preferably comes into contact with the second insulation layer.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a display device. One aspect of the present invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and by making the ratio of indium larger than the ratio of gallium, a semiconductor device having an increased field-effect mobility (sometimes simply referred to as mobility or μFE) is disclosed.

[0004] Since the metal oxide that can be used for the semiconductor layer can be formed using a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large-sized display device. In addition, since a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon can be improved and utilized, capital investment can be suppressed. Further, a transistor using a metal oxide has a higher field-effect mobility than when using amorphous silicon, so a high-performance display device provided with a driving circuit can be realized.

[0005] In display devices, the screen size tends to increase, and development has been carried out with a view to screen sizes of 60 inches or more in diagonal, and even 120 inches or more in diagonal. In addition, the screen resolution also tends to be higher definition, such as full high vision (pixel count 1920 × 1080, also referred to as "2K", etc.), ultra high vision (pixel count 3840 × 2160, also referred to as "4K", etc.), and super high vision (pixel count 7680 × 4320, also referred to as "8K", etc.).

[0006] The increase in screen size and high definition tend to increase the wiring resistance within the display unit. In Patent Document 2, in a liquid crystal display device using amorphous silicon transistors, a technique for forming a low-resistance wiring layer using copper (Cu) in order to suppress the increase in wiring resistance is disclosed.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention has a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer. The first insulating layer, the metal oxide layer, and the conductive layer are laminated in this order on the semiconductor layer. The end of the first insulating layer is located inside the end of the semiconductor layer. The end of the metal oxide layer is located inside the end of the first insulating layer. The end of the conductive layer is located inside the end of the metal oxide layer. The second insulating layer is provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer. The semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the first insulating layer and the metal oxide layer. The second region sandwiches the first region, overlaps with the first insulating layer, and does not overlap with the metal oxide layer. The third region sandwiches the first region and the pair of second regions and does not overlap with the first insulating layer. The third region is in contact with the second insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region. This is a semiconductor device.

[0011] In the above-described semiconductor device, it is preferable that the second region includes a portion having a lower resistance than the first region.

[0012] In the above-described semiconductor device, the second region has a sheet resistance of 1×10 3 Ω / □ or more and 1×10 9 Ω / □ or less. It is preferable that the second region includes such a portion.

[0013] In the above-described semiconductor device, in the cross-section in the channel length direction, it is preferable that the width of the second region is 100 nm or more and 2 μm or less.

[0014] In the above-described semiconductor device, it is preferable that the second insulating layer is a silicon nitride film.

[0015] In the above-described semiconductor device, the ends of the first insulating layer and the metal oxide layer each have a tapered shape, and it is preferable that the tapered angle of the end of the metal oxide layer is smaller than the tapered angle of the end of the first insulating layer.

[0016] In the above semiconductor device, it preferably has a functional layer between the metal oxide layer and the conductive layer. The functional layer has conductivity, and the end of the functional layer substantially coincides with the end of the metal oxide layer or is located between the end of the metal oxide layer and the end of the conductive layer.

[0017] In the above semiconductor device, it is preferable that the semiconductor layer, the metal oxide layer, and the functional layer each contain the same metal element.

[0018] In the above semiconductor device, the metal element is preferably at least one of indium and zinc.

Advantages of the Invention

[0019] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided. Or, a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0021]

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DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different modes, and the forms and details thereof can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0023] In each of the figures described in this specification, the size, layer thickness, or area of each component may be exaggerated for clarity.

[0024] The ordinal numbers "first", "second", "third", etc. used in this specification and the like are attached to avoid confusion of components and are not numerically limiting.

[0025] In this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0026] In this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors with different polarities are employed or when the direction of current changes in a circuit operation. For this reason, the terms "source" and "drain" are assumed to be interchangeable.

[0027] In this specification and the like, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region at the shortest distance. That is, the channel length direction corresponds to one of the directions of the current flowing through the semiconductor layer when the transistor is in the on state. Also, the channel width direction refers to the direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be uniquely determined.

[0028] In this specification and the like, "electrically connected" includes cases where connection is made through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0029] In this specification and the like, the term "film" and the term "layer" can be interchanged with each other. For example, terms such as "conductive layer" and "insulating layer" may be mutually interchangeable with terms such as "conductive film" and "insulating film".

[0030] In this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel transistor, is a state where the voltage V gs between the gate and the source is lower than the threshold voltage V th (for a p-channel transistor, it is a state where it is higher than V th ).

[0031] In this specification and the like, a display panel, which is an aspect of a display device, has the function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is an aspect of an output device.

[0032] In this specification and the like, a display panel module, a display module, or simply a display panel may refer to a display panel on whose substrate a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached, or a display panel on whose substrate an IC is mounted by a COG (Chip On Glass) method or the like.

[0033] In this specification and the like, a touch panel, which is an aspect of a display device, has the function of displaying an image or the like on a display surface and the function as a touch sensor for detecting that a detection object such as a finger or a stylus touches, presses, or approaches the display surface. Therefore, the touch panel is an aspect of an input / output device.

[0034] The touch panel can also be referred to as, for example, a display panel (or a display device) with a touch sensor, or a display panel (or a display device) with a touch sensor function. The touch panel can also be configured to have a display panel and a touch sensor panel. Alternatively, it can be configured to have a function as a touch sensor inside or on the surface of the display panel.

[0035] In this specification and the like, a substrate of a touch panel on which a connector or an IC is mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0036] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to an aspect of the present invention will be described. In particular, in this embodiment, as an example of the semiconductor device, a transistor using an oxide semiconductor for a semiconductor layer in which a channel is formed will be described.

[0037] One aspect of the present invention is a transistor having, on a surface to be formed, a semiconductor layer in which a channel is formed, a gate insulating layer (also referred to as a first insulating layer) on the semiconductor layer, a metal oxide layer on the gate insulating layer, and a conductive layer (also referred to as a first conductive layer) that functions as a gate electrode on the metal oxide layer. The semiconductor layer is preferably configured to include a metal oxide (hereinafter also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.

[0038] It is preferable that an end portion of the first insulating layer is located inside an end portion of the semiconductor layer, an end portion of the metal oxide layer is located inside an end portion of the first insulating layer, and an end portion of the conductive layer is located inside an end portion of the metal oxide layer.

[0039] It is preferable that a second insulating layer is provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer.

[0040] The semiconductor layer has a first region, a pair of second regions, and a pair of third regions. The first region overlaps with the first insulating layer and the metal oxide layer. The second region is a region that sandwiches the first region, overlaps with the first insulating layer, and does not overlap with the metal oxide layer. The third region is a region that sandwiches the first region and the pair of second regions and does not overlap with the first insulating layer. The third region is in contact with the second insulating layer. It is preferable that the third region includes a portion having a lower resistance than the first region, and the second region includes a portion having a higher resistance than the third region.

[0041] Hereinafter, more specific examples will be described with reference to the drawings.

[0042] <Configuration Example 1> FIG. 1A is a top view of the transistor 100, FIG. 1B corresponds to a cross-sectional view of the cutting plane along the dashed line A1 - A2 shown in FIG. 1A, and FIG. 1C corresponds to a cross-sectional view of the cutting plane along the dashed line B1 - B2 shown in FIG. 1A. In FIG. 1A, a part of the components (such as the protective layer) of the transistor 100 is omitted in the illustration. Also, the direction of the dashed line A1 - A2 corresponds to the channel length direction, and the direction of the dashed line B1 - B2 corresponds to the channel width direction. Also, for the top view of the transistor, in the following drawings, as in FIG. 1A, a part of the components will be omitted in the illustration.

[0043] The transistor 100 is provided on the substrate 102 and has an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, an insulating layer 118, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided to cover a part of the upper surface of the insulating layer 103 and a part of the upper surface of the semiconductor layer 108. The metal oxide layer 114 and the conductive layer 112 are laminated in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108. An enlarged view of the region P surrounded by the dashed line in FIG. 1B is shown in FIG. 2.

[0044] The ends of the conductive layer 112 and the metal oxide layer 114 are located inside the ends of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the ends of the conductive layer 112 and the metal oxide layer 114 at least on the semiconductor layer 108. Also, the end of the conductive layer 112 is located inside the end of the metal oxide layer 114. In other words, the metal oxide layer 114 has a portion that protrudes outside the end of the conductive layer 112 at least on the semiconductor layer 108.

[0045] The semiconductor layer 108 has a pair of regions 108L sandwiching the channel formation region and a pair of regions 108N outside thereof. The region 108L is a region of the semiconductor layer 108 that overlaps with the insulating layer 110 and does not overlap with the conductive layer 112. In FIG. 2, the width of the channel formation region in the channel length direction of the transistor 100 is denoted as L1, and the width of the region 108L is denoted as L2.

[0046] The region 108L can also be referred to as a region having a resistance comparable to or lower than that of the channel formation region, a region having a carrier concentration comparable to or higher than that of the channel formation region, a region having an oxygen defect density comparable to or higher than that of the channel formation region, or a region having an impurity concentration comparable to or higher than that of the channel formation region.

[0047] The region 108L can also be referred to as a region having a resistance comparable to or higher than that of the region 108N, a region having a carrier concentration comparable to or lower than that of the region 108N, a region having an oxygen defect density comparable to or lower than that of the region 108N, or a region having an impurity concentration comparable to or lower than that of the region 108N.

[0048] The sheet resistance of the region 108L is preferably 1×10 3 Ω / □ or more and 1×10 9 Ω / □ or less, more preferably 1×10 3 Ω / □ or more and 1×10 8 Ω / □ or less, and even more preferably 1×10 3 Ω / □ or more and 1×10 7 Ω / □ or less. By setting the resistance within the above range, a transistor with good electrical characteristics and high reliability can be obtained. Note that the sheet resistance can be calculated from the resistance value. By providing such a region 108L between the region 108N and the channel formation region, the source-drain breakdown voltage of the transistor 100 can be increased.

[0049] Note that the carrier concentration in the region 108L does not have to be uniform, and may have a gradient such that the carrier concentration decreases from the region 108N side toward the channel formation region. For example, either one or both of the hydrogen concentration or the oxygen defect concentration in the region 108L may have a gradient such that the concentration decreases from the region 108N side toward the channel formation region side.

[0050] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 has a portion that overlaps with the conductive layer 112 and functions as a gate insulating layer, and a portion that does not overlap with the conductive layer 112 and the metal oxide layer 114 (i.e., the portion that overlaps with the region 108L).

[0051] The insulating layer 116 is provided to cover the upper surface and side surfaces of the conductive layer 112, the side surfaces of the metal oxide layer 114, the upper surface and side surfaces of the insulating layer 110, the upper surface and side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 116 has a function of suppressing the diffusion of impurities from above the insulating layer 116 into the semiconductor layer 108. Further, the insulating layer 116 has a function of reducing the resistance of the semiconductor layer 108 in contact with the insulating layer 116 during film formation. The region 108N is in contact with the insulating layer 116. Since the region 108L is not in contact with the insulating layer 116 due to the presence of the insulating layer 110 in between, the amount of hydrogen supplied from the insulating layer 116 is less than that of the region 108N. Furthermore, since the impurity concentration is also smaller than that of the region 108N, the region 108L can be in a higher resistance state than the region 108N.

[0052] As will be described later, since the region 108L can be formed self-alignedly, a photomask for forming the region 108L is not required, and the manufacturing cost can be reduced. Also, by forming the region 108L self-alignedly, there is no relative displacement in the position between the region 108L and the conductive layer 112, so that the width of the region 108L in the semiconductor layer 108 can be made substantially the same.

[0053] The region 108L, which functions as an offset region where the electric field of the gate is not applied (or is less likely to be applied than in the channel formation region), can be stably formed without variation between the channel formation region and the low-resistance region 108N in the semiconductor layer 108. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor and semiconductor device can be realized.

[0054] The width L2 of the region 108L is preferably 100 nm or more and 2 μm or less, more preferably 150 nm or more and 1 μm or less, and still more preferably 200 nm or more and 1 μm or less. By providing the region 108L, the concentration of the electric field near the drain is alleviated, and in particular, the deterioration of the transistor in a state where the drain voltage is high can be suppressed. In addition, in particular, by making the width L2 of the region 108L larger than the thickness of the insulating layer 110, the concentration of the electric field near the drain can be effectively suppressed. On the other hand, if the width L2 is longer than 2 μm, the source-drain resistance increases, and the driving speed of the transistor may become slow. By setting the width L2 within the above-mentioned range, a highly reliable and fast-driving transistor and semiconductor device can be obtained. Note that the width L2 of the region 108L can be determined according to the thickness of the semiconductor layer 108, the thickness of the insulating layer 110, and the magnitude of the voltage applied between the source and the drain when driving the transistor 100.

[0055] By providing the region 108L between the channel formation region and the low-resistance region 108N, the current density at the boundary between the channel formation region and the region 108N can be alleviated, the heat generation at the boundary between the channel and the source or the drain can be suppressed, and a highly reliable transistor and semiconductor device can be obtained.

[0056] It is preferable to use a low-resistance material for the conductive layer 112. By using a low-resistance material for the conductive layer 112, the parasitic resistance can be reduced, and a transistor having a high on-current can be obtained, and a semiconductor device having a high on-current can be obtained. In addition, in a large display device or a high-definition display device, by reducing the wiring resistance, the signal delay can be suppressed, and high-speed driving becomes possible. As the conductive layer 112, copper, silver, gold, aluminum, or the like can be used. In particular, copper is preferable because of its excellent mass productivity.

[0057] When the end of the layer to be formed of the conductive layer 112 is located inside the end of the conductive layer 112, that is, when a so-called undercut occurs, the coverage of the layer formed later decreases, and defects such as steps and looseness occur in the layer. Due to shape defects such as undercuts, there is a risk that problems such as variations in the electrical characteristics of the transistor may occur.

[0058] As shown in FIGS. 1B, 1C, and 2, it is preferable to provide the functional layer 113 as the layer to be formed of the conductive layer 112, and to configure the etching rate in the etchant used for processing the conductive layer 112 to be about the same as or slower than that of the conductive layer 112. By configuring in this way, the occurrence of undercuts can be suppressed, and a transistor with less likely shape defects can be obtained. Also, a transistor and a semiconductor device with good electrical characteristics can be obtained.

[0059] As shown in FIGS. 1B, 1C, etc., it is preferable to provide the functional layer 113 between the conductive layer 112 and the metal oxide layer 114. In particular, it is preferable to use a material having conductivity for the functional layer 113. Also, it is preferable to use a material having high adhesion to the conductive layer 112 for the functional layer 113. Since the adhesion between the functional layer 113 and the conductive layer 112 is high, it is possible to suppress the etchant from entering between these two layers when forming the functional layer 113 and the conductive layer 112, and to prevent voids from occurring between the functional layer 113 and the conductive layer 112.

[0060] The conductive layer 112 and the functional layer 113 preferably have a shape in which their respective cross-sections are continuous. By making the cross-sections of the conductive layer 112 and the functional layer 113 continuous, the coverage of the layer (for example, the insulating layer 116) formed on the conductive layer 112 and the functional layer 113 is improved, and it is possible to suppress the occurrence of defects such as steps and looseness in the layer.

[0061] The ends of the insulating layer 110 and the ends of the metal oxide layer 114 preferably each have a tapered shape. Further, the ends of the metal oxide layer 114 preferably have a taper angle smaller than the taper angle of the ends of the insulating layer 110. With such a configuration, the coverage of the layer formed on the insulating layer 110 and the metal oxide layer 114 (for example, the insulating layer 116) is improved, and it is possible to suppress the occurrence of defects such as steps and looseness in the layer.

[0062] In this specification and the like, "substantially the same top surface shape" means that at least a part of the contours overlap between the stacked layers. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. However, strictly speaking, the contours do not overlap, and the end of the upper layer may be located inside the end of the lower layer or the end of the upper layer may be located outside the end of the lower layer. In this case as well, it is said that "the top surface shapes are substantially the same".

[0063] In this specification and the like, the taper angle refers to the inclination angle formed by the side surface and the bottom surface of the target layer when the target layer is observed from a direction perpendicular to the cross section (for example, a plane perpendicular to the surface of the substrate).

[0064] The insulating layer 116 is provided to cover the upper surface and the side surface of the conductive layer 112, the upper surface and the side surface of the functional layer 113, the side surface of the metal oxide layer 114, the upper surface and the side surface of the insulating layer 110, the upper surface and the side surface of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116. The insulating layer 116 and the insulating layer 118 function as a protective layer and can suppress the diffusion of impurities from the outside.

[0065] A part of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top gate type transistor in which a gate electrode is provided on the semiconductor layer 108.

[0066] As shown in FIGS. 1A and 1B, the transistor 100 may have a conductive layer 120a and a conductive layer 120b on the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as source electrodes or drain electrodes. The conductive layer 120a and the conductive layer 120b are electrically connected to a region 108N described later through an opening 141a or an opening 141b provided in the insulating layer 118 and the insulating layer 116, respectively.

[0067] The semiconductor layer 108 preferably contains a metal oxide.

[0068] For example, the semiconductor layer 108 preferably has indium, an element M (the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. In particular, the element M is preferably one or more selected from aluminum, gallium, yttrium, or tin.

[0069] In particular, it is preferable to use an oxide containing indium, gallium, and zinc as the semiconductor layer 108.

[0070] The semiconductor layer 108 may have a laminated structure in which layers with different compositions, or layers with different crystallinities, or layers with different impurity concentrations are laminated.

[0071] As the conductive layer 112, one or more selected from copper, silver, gold, or aluminum can be used. In particular, copper is preferable because it has low resistance and excellent mass productivity.

[0072] The metal oxide layer 114 positioned between the insulating layer 110 and the functional layer 113 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing toward the conductive layer 112 side. Furthermore, the metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing toward the insulating layer 110 side. For the metal oxide layer 114, for example, a material that is less permeable to oxygen and hydrogen than at least the insulating layer 110 can be used.

[0073] Even when a metal material that easily attracts oxygen, such as aluminum or copper, is used for the conductive layer 112, the metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112. Also, even when the conductive layer 112 contains hydrogen, it is possible to prevent hydrogen from diffusing from the conductive layer 112 through the insulating layer 110 to the semiconductor layer 108. As a result, the carrier concentration in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0074] As the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has insulating properties, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, it functions as part of the gate electrode.

[0075] Preferably, an insulating material having a higher dielectric constant than silicon oxide is used as the metal oxide layer 114. In particular, using an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferable because the driving voltage can be reduced.

[0076] As the metal oxide layer 114, for example, a conductive oxide such as indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can also be used. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0077] As the metal oxide layer 114, it is preferable to use an oxide material containing one or more elements the same as those in the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. At this time, as the metal oxide layer 114, it is preferable to apply a metal oxide film formed using the same sputtering target as the semiconductor layer 108 because the apparatus can be shared.

[0078] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material with a higher gallium composition (content ratio) for the metal oxide layer 114 than the material used for the semiconductor layer 108 because the blocking property against oxygen can be further enhanced. At this time, for the semiconductor layer 108, by using a material with a higher indium composition than the material used for the metal oxide layer 114, the field-effect mobility of the transistor 100 can be increased.

[0079] The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when forming an oxide film using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming it in an atmosphere containing oxygen gas.

[0080] For the functional layer 113 located between the metal oxide layer 114 and the conductive layer 112, it is preferable to use a conductive material having oxidation resistance. By using a material having oxidation resistance, an increase in the resistance of the functional layer 113 can be suppressed.

[0081] It is preferable that the etching rate of the metal oxide layer 114 and the functional layer 113 in the etchant used for processing the conductive layer 112 is about the same as or slower than that of the conductive layer 112.

[0082] When the etching rates of the metal oxide layer 114 and the functional layer 113 are faster than that of the conductive layer 112, an undercut is likely to occur where the ends of the metal oxide layer 114 and the functional layer 113 are located more inward than the ends of the conductive layer 112. When an undercut occurs, the covering properties of the subsequently formed insulating layer 116 and insulating layer 118 deteriorate, and defects such as steps or low-density regions (also called looseness) occur in the insulating layer 116 and insulating layer 118.

[0083] In one aspect of the present invention, by configuring the etching rates of the metal oxide layer 114 and the functional layer 113 to be approximately the same as or slower than that of the conductive layer 112, the occurrence of undercuts can be suppressed, and a transistor with less likelihood of shape defects can be obtained. Also, a transistor with good electrical characteristics can be obtained.

[0084] The functional layer 113, the metal oxide layer 114, and the conductive layer 112 can be formed in the same process using the etchant used for processing the conductive layer 112. Furthermore, the upper surface shapes of the metal oxide layer 114, the functional layer 113, and the conductive layer 112 can be made to generally coincide with each other.

[0085] The etching rate of the insulating layer 110 is preferably slower than those of the metal oxide layer 114, the functional layer 113, and the conductive layer 112. By configuring the etching rate of the insulating layer 110 to be slower than those of the metal oxide layer 114, the functional layer 113, and the conductive layer 112, the amount of etching of the insulating layer 110 can be reduced when the metal oxide layer 114, the functional layer 113, and the conductive layer 112 are formed.

[0086] The functional layer 113 preferably has high adhesion to the metal oxide layer 114 and the conductive layer 112. For example, in a configuration where the conductive layer 112 is formed on the metal oxide layer 114, if the adhesion between these layers is low, when the metal oxide layer 114 and the conductive layer 112 are formed, an etchant may penetrate between these two layers, resulting in voids between the metal oxide layer 114 and the conductive layer 112. In one aspect of the present invention, by providing the functional layer 113 between the metal oxide layer 114 and the conductive layer 112, the adhesion of the metal oxide layer 114, the functional layer 113, and the conductive layer 112 is enhanced, voids between these layers can be suppressed from occurring, and a transistor with less likelihood of shape defects can be obtained. Also, a transistor with good electrical characteristics can be obtained.

[0087] The functional layer 113 preferably has a low emission amount of impurities having hydrogen. Examples of impurities having hydrogen include hydrogen, water, and the like. When impurities having hydrogen are emitted from the functional layer 113, when the hydrogen reaches the channel formation region of the semiconductor layer 108, it may combine with oxygen in the channel formation region and desorb as water, forming oxygen vacancies (hereinafter also referred to as V O ). Also, when oxygen vacancies (V O ) and hydrogen are present in the channel formation region, a state in which hydrogen enters the oxygen vacancies (V O ), hereinafter also referred to as V O H, may be formed. V O H serves as a carrier generation source and may have an adverse effect on the electrical characteristics and reliability of the transistor. By using the functional layer 113 with a low emission amount of impurities having hydrogen, good electrical characteristics and reliability can be obtained.

[0088] The functional layer 113 preferably has a low emission amount of impurities having oxygen. Examples of impurities having oxygen include oxygen, water, and the like. When impurities having oxygen are emitted from the functional layer 113, when the oxygen reaches the conductive layer 112, the resistance of the conductive layer 112 may increase. By using the functional layer 113 with a low emission amount of impurities having oxygen, an increase in the resistance of the conductive layer 112 can be suppressed.

[0089] As the functional layer 113, a metal oxide can be used. For example, oxides containing indium such as indium oxide, indium tin oxide (ITO), and indium tin oxide containing silicon (ITSO) can be used. Since ITSO is difficult to crystallize due to containing silicon and has high flatness, the adhesion to the film formed on ITSO becomes high, which is particularly preferable. Further, metal oxides such as indium zinc oxide, zinc oxide, and zinc oxide containing gallium can be used.

[0090] As the functional layer 113, an oxide having indium, element M (element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) and zinc can be used. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, or tin. For example, among In-Ga-Zn oxides, it is preferable that the atomic ratio of In to Ga is greater than 1 because the conductivity increases. In particular, it is preferable that the atomic ratio of In, element M, and Zn in the functional layer 113 is In:M:Zn = 4:2:3 or in the vicinity thereof. Alternatively, it is preferable that the atomic ratio of In, element M, and Zn is In:M:Zn = 5:1:6 or in the vicinity thereof. Further, as the composition of the semiconductor layer 108, the atomic ratios of In, element M, and Zn in the semiconductor layer 108 may be made substantially equal. That is, a material having an atomic ratio of In:M:Zn = 1:1:1 or in the vicinity thereof may be included.

[0091] As the functional layer 113, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys mainly composed of these can be used.

[0092] The functional layer 113 preferably uses a material different from that of the metal oxide layer 114 and the conductive layer 112. In this specification and the like, the different materials refer to materials having different constituent elements or materials having the same constituent elements but different compositions. Even when the metal oxide layer 114 has low adhesion to the conductive layer 112, by providing a functional layer 113 having a material different from that of the metal oxide layer 114 between the metal oxide layer 114 and the conductive layer 112, the adhesion to the metal oxide layer 114 and the conductive layer 112 can be enhanced.

[0093] The functional layer 113 may have a structure in which two or more of the above-described materials are laminated.

[0094] The semiconductor layer 108 has a channel formation region that overlaps the conductive layer 112 via the insulating layer 110. Further, the semiconductor layer 108 has a pair of regions 108N sandwiching the channel formation region. The region 108N is a region of the semiconductor layer 108 that does not overlap with either the conductive layer 112 or the insulating layer 110 and is a region in contact with the insulating layer 116.

[0095] The region 108N can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier concentration, a region having a high oxygen defect density, a region having a high impurity concentration, or an n-type region.

[0096] The region 108N is a region containing an impurity element (hereinafter referred to as the first element). Examples of the first element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, or a noble gas. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron, phosphorus, magnesium, or aluminum. Also, two or more of these elements may be contained.

[0097] Here, the concentration of the first element in the region 108N preferably has a concentration gradient such that the closer it is to the insulating layer 116, the higher the concentration. Thereby, compared with the case where a uniform concentration is set throughout the region 108N, the total amount of the first element in the region 108N can be reduced, so that the amount of the first element that can diffuse into the channel formation region due to the influence of heat or the like during the manufacturing process can be kept low. Also, since the upper part of the region 108N has a lower resistance, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced.

[0098] As will be described later, the process of adding the first element to the region 108N can be performed using the insulating layer 110 as a mask. Thereby, the region 108N can be formed self-aligned.

[0099] The region 108N has a concentration of the first element of 1×10 19 atoms / cm 3 or more and 1×10 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5×10 22 atoms / cm 3 or less, more preferably 1×10 20 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less, and preferably includes a region having such a concentration.

[0100] The concentration of the first element contained in the region 108N can be analyzed by an analysis method such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When using XPS analysis, by combining ion sputtering from the front side or the back side and XPS analysis, the concentration distribution in the depth direction can be known.

[0101] In the region 108N, the first element is preferably present in an oxidized state. For example, it is preferable to use an easily oxidized element such as boron, phosphorus, magnesium, aluminum, or silicon as the first element. Since such an easily oxidized element can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, even if a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process, desorption is suppressed. In addition, the first element removes oxygen from the semiconductor layer 108, and many oxygen vacancies are generated in the region 108N. These oxygen vacancies bond with hydrogen in the film to become a carrier supply source, and the region 108N becomes in an extremely low resistance state.

[0102] In addition, when a high-temperature process is performed in a later step, if a large amount of oxygen is supplied to the region 108N from the outside or a film in the vicinity of the region 108N, the resistance may increase. Therefore, when performing a high-temperature process, it is preferable to perform the process in a state where the semiconductor layer 108 is covered with the insulating layer 116 that has a high barrier property against oxygen.

[0103] The insulating layer 116 is provided in contact with a region 108N of the semiconductor layer 108.

[0104] The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen when heated. By providing such an insulating layer 116 in contact with the region 108N and performing heat treatment after the insulating layer 116 is formed, hydrogen can be supplied to the region 108N to reduce the resistance.

[0105] The insulating layer 116 is preferably formed by using a deposition gas containing hydrogen elements, so that hydrogen can be effectively supplied to the region 108N during the deposition of the insulating layer 116.

[0106] The insulating layer 116 can be, for example, an insulating film made of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like.

[0107] Region 108N is in a state with a large amount of oxygen deficiency due to the addition of the first element as described above. Therefore, in addition to the hydrogen contained in the semiconductor layer 108, by further supplying hydrogen from the insulating layer 116, the carrier concentration can be increased more.

[0108] The insulating layer 118 functions as a protective layer for protecting the transistor 100. As the insulating layer 118, an inorganic insulating material such as an oxide or a nitride can be used. As a more specific example, an inorganic insulating material such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium aluminate can be used. Further, the insulating layer 118 can also be used as a planarization layer. In that case, an organic resin material can be used as the insulating layer 118.

[0109] Here, the case where the laminated structure of the insulating layer 116 and the insulating layer 118 is used as the protective layer is shown, but if the insulating layer 118 is not necessary, it may not be provided. Further, the insulating layer 118 may have a laminated structure of two or more layers.

[0110] Here, the semiconductor layer 108 and the oxygen deficiency that can be formed in the semiconductor layer 108 will be described.

[0111] The oxygen deficiency formed in the channel formation region of the semiconductor layer 108 becomes a problem because it affects the transistor characteristics. For example, when oxygen deficiency is formed in the semiconductor layer 108, hydrogen binds to the oxygen deficiency and can become a carrier supply source. When a carrier supply source is generated in the channel formation region, fluctuations in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage, occur. Therefore, in the channel formation region, it is preferable that the amount of oxygen deficiency is less.

[0112] Therefore, in one aspect of the present invention, the insulating films near the channel formation region of the semiconductor layer 108, specifically, the insulating layer 110 located above the channel formation region and the insulating layer 103 located below it, are configured to include an oxide film. By moving oxygen from the insulating layer 103 and the insulating layer 110 to the channel formation region due to heat during the manufacturing process or the like, it becomes possible to reduce oxygen deficiencies in the channel formation region.

[0113] The semiconductor layer 108 preferably has a region where the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0114] Here, in the case of a metal oxide containing In, Ga, and Zn, the binding force between In and oxygen is weaker than that between Ga and oxygen. Therefore, when the In content is high, oxygen deficiencies are likely to be formed in the metal oxide film. Also, when using the metal element represented by the above element M instead of Ga, there is a similar tendency. When there are many oxygen deficiencies in the metal oxide film, the electrical characteristics and reliability of the transistor deteriorate.

[0115] However, in one aspect of the present invention, since an extremely large amount of oxygen can be supplied into the channel formation region of the semiconductor layer 108 containing a metal oxide, it becomes possible to use a metal oxide material with a high In content. Thereby, a transistor having extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0116] For example, a metal oxide in which the atomic ratio of In to the element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be preferably used.

[0117] In particular, it is preferable that the atomic ratio of In, M, and Zn in the semiconductor layer 108 be In:M:Zn = 4:2:3 or in the vicinity thereof. Alternatively, it is preferable that the atomic ratio of In, M, and Zn be In:M:Zn = 5:1:6 or in the vicinity thereof. Further, as the composition of the semiconductor layer 108, the atomic ratios of In, M, and Zn in the semiconductor layer 108 may be made substantially equal. That is, it may contain a material in which the atomic ratio of In, element M, and Zn is In:M:Zn = 1:1:1 or in the vicinity thereof.

[0118] For example, by using the above transistor with a high field-effect mobility in a gate driver that generates a gate signal, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Further, by using the above transistor with a high field-effect mobility in a source driver (particularly, a demultiplexer connected to the output terminal of the shift register included in the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0119] Note that even if the semiconductor layer 108 has a region where the atomic ratio of In to element M is greater than 1, when the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may be low. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by using X-ray diffraction (XRD) or by using a transmission electron microscope (TEM).

[0120] Here, by reducing the impurity concentration and the defect level density (reducing oxygen deficiency) in the channel formation region of the semiconductor layer 108, the carrier concentration in the film can be reduced. A transistor using such a metal oxide film in the channel formation region of the semiconductor layer rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage becomes negative. Further, a transistor using such a metal oxide film can obtain characteristics in which the off-current is extremely small.

[0121] When a highly crystalline metal oxide film is used for the semiconductor layer 108, damage during the processing of the semiconductor layer 108 or during the film formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with relatively low crystallinity for the semiconductor layer 108, the electrical conductivity can be improved, and a transistor with high field-effect mobility can be realized.

[0122] For the semiconductor layer 108, it is preferable to use a metal oxide film having a CAAC (c-axis aligned crystal) structure, a metal oxide film having an nc (nano crystal) structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed, which will be described later.

[0123] The semiconductor layer 108 may have a stacked structure of two or more layers.

[0124] For example, a semiconductor layer 108 formed by stacking two or more metal oxide films having different compositions can be used. For example, when an In-M-Zn oxide is used, among the films formed by sputtering targets in which the atomic number ratios of In, element M, and Zn are In:M:Zn = 5:1:6, In:M:Zn = 4:2:3, In:M:Zn = 1:1:1, In:M:Zn = 2:2:1, In:M:Zn = 1:3:4, In:M:Zn = 1:3:2, or in the vicinity thereof, it is preferable to stack and use two or more of them.

[0125] A semiconductor layer 108 formed by stacking two or more metal oxide films having different crystallinities can be used. In that case, it is preferable that they are continuously formed without exposure to the atmosphere by using the same oxide target and varying the film formation conditions.

[0126] At this time, the semiconductor layer 108 can have a laminated structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, it may have a laminated structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Note that, regarding the functions of metal oxides or the material configurations that can be suitably used for these metal oxide films, the description of CAC (Cloud-Aligned Composite) described later can be incorporated by reference.

[0127] For example, the oxygen flow rate ratio during the formation of the first metal oxide film formed first is made smaller than the oxygen flow rate ratio during the formation of the second metal oxide film formed later. Alternatively, the condition of not flowing oxygen is set during the formation of the first metal oxide film. Thereby, oxygen can be effectively supplied during the formation of the second metal oxide film. In addition, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, by making the second metal oxide film provided on the upper part a film having higher crystallinity than the first metal oxide film, damage during the processing of the semiconductor layer 108 or during the formation of the insulating layer 110 can be suppressed.

[0128] More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. Also, the oxygen flow rate ratio during the formation of the second metal oxide film is 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, still more preferably 90% or more and 100% or less, and typically 100%. In addition, the conditions such as pressure, temperature, and power during the film formation may be different between the first metal oxide film and the second metal oxide film, but it is preferable to make the conditions other than the oxygen flow rate ratio the same because the time required for the film formation process can be shortened.

[0129] By adopting such a configuration, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0130] It is preferable to use an oxide film for the insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. Thereby, oxygen desorbed from the insulating layer 103 or the insulating layer 110 can be supplied to the channel formation region of the semiconductor layer 108 during heat treatment or the like in the manufacturing process of the transistor 100, and oxygen vacancies in the semiconductor layer 108 can be reduced.

[0131] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 overlaps with the conductive layer 112 and has a region that functions as a gate insulating layer.

[0132] The insulating layer 110 may have a stacked structure of two or more layers. FIG. 2 shows an example in which the insulating layer 110 has a three-layer structure including an insulating layer 110a, an insulating layer 110c on the insulating layer 110a, and an insulating layer 110b between the insulating layer 110a and the insulating layer 110c. Since the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can use insulating films of the same material, the interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c may not be clearly confirmed. Therefore, in the present embodiment, the interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are illustrated by broken lines.

[0133] The insulating layer 110a in contact with the channel formation region of the semiconductor layer 108 preferably has a low defect density in the vicinity of the interface with the channel formation region and in the film. Further, the insulating layer 110a preferably has a low impurity concentration of hydrogen in the film. Further, it is preferable that the damage to the semiconductor layer 108 during the formation of the insulating layer 110a is small. By using a film with a low defect density and impurity concentration for the insulating layer 110a and using film formation conditions with little damage to the semiconductor layer 108, a transistor with good electrical characteristics can be obtained.

[0134] For example, when forming a film having silicon as the insulating layer 110 by the PECVD method, the insulating layer 110a can use a film formation condition in which the ratio of the silicon-containing gas to the film formation gas used during film formation is low. By using a film formation condition in which the ratio of the silicon-containing gas to the film formation gas is low, an insulating layer 110a with a low defect density and impurity concentration can be formed. Also, by lowering the film formation power during the formation of the insulating layer 110a, the damage to the semiconductor layer 108 can be reduced.

[0135] The insulating layer 110c in contact with the metal oxide layer 114 preferably has a configuration in which the etching rate in the etchant used for processing the conductive layer 112 is about the same as or slower than that of the conductive layer 112.

[0136] The insulating layer 110c is preferably a denser film than the insulating layer 110a. The dense insulating layer 110c can be formed under film formation conditions with a slower film formation rate than the insulating layer 110a. Also, water adsorption on the surface of the dense insulating layer 110c is suppressed. That is, by providing the insulating layer 110c on the upper surface of the insulating layer 110, water adsorption on the surface of the insulating layer 110 can be suppressed.

[0137] When water is adsorbed on the surface of the insulating layer 110, if the hydrogen in the adsorbed water reaches the channel formation region, carriers may be formed in the channel formation region, which may adversely affect the electrical characteristics and reliability of the transistor. By providing the insulating layer 110c, on which water is less likely to be adsorbed, on the upper surface of the insulating layer 110, the formation of carriers in the channel formation region can be suppressed, and good electrical characteristics and reliability can be obtained.

[0138] For the formation of the insulating layer 110c, film formation conditions with a slower film formation rate than the insulating layer 110a can be used. For example, when using a film having silicon as the insulating layer 110, the insulating layer 110c can use conditions in which the ratio of the silicon-containing gas to the film formation gas used during film formation is low. Furthermore, compared with the insulating layer 110a, the insulating layer 110c can be made into an insulating layer on which water is less likely to be adsorbed by increasing the film formation power during film formation.

[0139] The insulating layer 110c preferably has a slower etching rate in a single etchant than the insulating layer 110a. Note that, compared with the insulating layer 110a, the insulating layer 110c may have a higher film density. The difference in the film density between the insulating layer 110a and the insulating layer 110c can be evaluated, for example, by the density (luminance) of a TEM image.

[0140] For forming the insulating layer 110b, film formation conditions with a higher film formation rate than those for the insulating layer 110a and the insulating layer 110c can be used. By using the insulating layer 110b with a high film formation rate, the insulating layer 110 having a laminated structure can be formed with high productivity.

[0141] For example, when a film containing silicon is used as the insulating layer 110, compared with the insulating layer 110a and the insulating layer 110c, for the insulating layer 110b, conditions with a higher ratio of the silicon-containing gas to the film formation gas used during film formation can be used. Also, the insulating layer 110b can be made into an insulating layer with fewer impurities by increasing the power during film formation. Furthermore, the insulating layer 110b can be made into an insulating layer with fewer impurities by increasing the pressure during film formation.

[0142] The insulating layer 110b preferably has an etching rate in a single etchant that is faster than those of the insulating layer 110a and the insulating layer 110c. Note that, compared with the insulating layer 110a and the insulating layer 110c, the insulating layer 110b may have a lower film density. The difference in the film density among the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be evaluated, for example, by the density (luminance) of a TEM image. Also, compared with the insulating layer 110a and the insulating layer 110c, the insulating layer 110b may have a higher hydrogen concentration in the film. The difference in the hydrogen concentration among the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be evaluated, for example, by secondary ion mass spectrometry (SIMS).

[0143] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the film thickness of the insulating layer 110c in the region that does not overlap with the conductive layer 112 may become thin. As shown in FIG. 2, it is preferable that the insulating layer 110c remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110c remains in the region that does not overlap with the conductive layer 112, adsorption of water to the insulating layer 110 can be suppressed. The thickness of the insulating layer 110c in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less.

[0144] As shown in FIG. 3A, the insulating layer 110 may have a two-layer structure including the insulating layer 110a and the insulating layer 110c on the insulating layer 110a.

[0145] As shown in FIG. 3B, the insulating layer 110 may have a single-layer structure. As the insulating layer 110, any one of the aforementioned insulating layer 110a, insulating layer 110b, or insulating layer 110c may be appropriately selected according to the purpose.

[0146] The insulating layer 103 can have a laminated structure. Examples of transistors with the insulating layer 103 having a laminated structure are shown in FIGS. 4A and 4B. FIG. 4A is a cross-sectional view of the transistor 100 in the channel length direction, and FIG. 4B is a cross-sectional view of the transistor 100 in the channel width direction.

[0147] As the insulating layer 103, it is preferable to adopt a stacked structure including an insulating layer 103a and an insulating layer 103b on the insulating layer 103a. For example, as the insulating layer 103a, nitrides or oxynitrides such as silicon nitride, silicon oxynitride, aluminum nitride, and aluminum oxynitride can be preferably used. For example, as the insulating layer 103b, oxides or oxynitrides such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, and hafnium oxynitride can be preferably used. By providing the insulating layer 103a on the lower side of the insulating layer 103, it is possible to suppress the diffusion of impurities from the layer below the insulating layer 103 to the layer above the insulating layer 103. At the same time, by providing the insulating layer 103b on the upper side of the insulating layer 103 in contact with the channel formation region, the oxygen desorbed from the insulating layer 103 can be supplied to the channel formation region. As the insulating layer 103, for example, a stacked structure including a silicon nitride film and a silicon oxynitride film on the silicon nitride film can be adopted.

[0148] In addition, in this specification and the like, oxynitride refers to a substance whose oxygen content is higher than that of nitrogen in terms of its composition, and oxynitrides are included in oxides. Nitroxide refers to a substance whose nitrogen content is higher than that of oxygen in terms of its composition, and nitroxides are included in nitrides.

[0149] As shown in FIGS. 4A and 4B, the transistor 100 preferably has a region where the insulating layer 103a is in contact with the insulating layer 116. By having a region where the insulating layer 103a is in contact with the insulating layer 116, it is possible to suppress the diffusion of impurities from outside the transistor 100 into the transistor 100.

[0150] The transistor 100 has a conductive layer 106 between the substrate 102 and the insulating layer 103, and the conductive layer 106 has a region overlapping with the channel formation region of the semiconductor layer 108, the metal oxide layer 114, the functional layer 113, and the conductive layer 112.

[0151] In transistor 100, conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and functional layer 113 and conductive layer 112 function as a second gate electrode (also referred to as a top gate electrode). Also, a part of insulating layer 103 functions as a first gate insulating layer, and a part of insulating layer 110 functions as a second gate insulating layer.

[0152] A portion of semiconductor layer 108 that overlaps with any one or more of functional layer 113, conductive layer 112, and conductive layer 106 functions as a channel formation region. For ease of explanation hereinafter, a portion of semiconductor layer 108 that overlaps with functional layer 113 and conductive layer 112 may be referred to as a channel formation region, but actually, a channel may be formed in a portion that overlaps with conductive layer 106 (a portion including region 108N) without overlapping with functional layer 113 and conductive layer 112.

[0153] As shown in FIGS. 1C and 4B, conductive layer 106 may be electrically connected to conductive layer 112 through an opening 142 provided in functional layer 113, metal oxide layer 114, insulating layer 110, and insulating layer 103. Thereby, the same potential can be applied to conductive layer 106 and conductive layer 112.

[0154] The same material as that of conductive layer 112, conductive layer 120a, or conductive layer 120b can be used for conductive layer 106. In particular, it is preferable to use a material containing copper for conductive layer 106 because the wiring resistance can be reduced. Also, when a material containing a high melting point metal such as tungsten or molybdenum is used for conductive layer 106, processing can be performed at a high temperature in a later process.

[0155] As shown in FIGS. 1C and 4B, in the channel width direction, it is preferable that functional layer 113, conductive layer 112, and conductive layer 106 protrude outside the end of semiconductor layer 108. At this time, the entire channel width direction of semiconductor layer 108 is covered with functional layer 113, conductive layer 112, and conductive layer 106 via insulating layer 110 and insulating layer 103.

[0156] With such a configuration, the semiconductor layer 108 can be electrically surrounded by the electric field generated by the pair of gate electrodes. At this time, in particular, it is preferable to apply the same potential to the conductive layer 106, the functional layer 113, and the conductive layer 112. Thereby, since an electric field for inducing a channel in the semiconductor layer 108 can be effectively applied, the on-current of the transistor 100 can be increased. Therefore, it is also possible to miniaturize the transistor 100.

[0157] Note that the functional layer 113 and the conductive layer 112 may not be connected to the conductive layer 106. At this time, a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100 may be applied to the other. At this time, the threshold voltage when driving the transistor 100 with the other gate electrode can also be controlled by the potential applied to one gate electrode.

[0158] Hereinafter, a configuration example of a transistor that is partially different from the above-described Configuration Example 1 will be described. Note that, hereinafter, the description of the portions overlapping with the above-described Configuration Example 1 may be omitted. In the drawings shown below, the portions having the same functions as those in the above-described Configuration Example 1 may have the same hatching pattern and may not be labeled.

[0159] <Configuration Example 2> FIG. 5A is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 5B is a cross-sectional view of the transistor 100A in the channel width direction. An enlarged view of the region Q surrounded by the dashed-dotted line in FIG. 5A is shown in FIG. 5C.

[0160] The transistor 100A is mainly different from Configuration Example 1 in that the film thickness of the functional layer 113 in the region not overlapping with the conductive layer 112 is thinner than the film thickness of the functional layer 113 in the region overlapping with the conductive layer 112.

[0161] By making the film thickness of the functional layer 113 in the region not overlapping with the conductive layer 112 thin, the step difference is reduced, the coverage of the layer formed on the functional layer 113 is improved, and the occurrence of defects such as steps and looseness in the layer can be suppressed.

[0162] The above is the description of Configuration Example 2.

[0163] <Configuration Example 3> FIG. 6A is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 6B is a cross-sectional view of the transistor 100B in the channel width direction. An enlarged view of the region R surrounded by the dashed-dotted line in FIG. 6A is shown in FIG. 6C.

[0164] The transistor 100B is mainly different from Configuration Example 1 in that the film thickness of the functional layer 113 in the region not overlapping with the conductive layer 112 is thinner than the film thickness of the functional layer 113 in the region overlapping with the conductive layer 112, and the film thickness of the metal oxide layer 114 in the region not overlapping with the conductive layer 112 is thinner than the film thickness of the metal oxide layer 114 in the region overlapping with the conductive layer 112.

[0165] The conductive layer 112 and the functional layer 113 preferably have a shape in which their respective cross-sections are continuous. By making the cross-sections of the conductive layer 112 and the functional layer 113 continuous, the covering property of the layer formed on the conductive layer 112 and the functional layer 113 is improved, and it is possible to suppress the occurrence of defects such as steps and looseness in the layer.

[0166] The above is the description of Configuration Example 3.

[0167] <Fabrication Method Example 1> Hereinafter, a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. Here, the transistor 100 illustrated in the above configuration example will be described as an example.

[0168] Note that thin films (such as insulating films, semiconductor films, and conductive films) constituting a semiconductor device can be formed using sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. As for the CVD method, there are plasma enhanced CVD (PECVD) and thermal CVD. Also, one type of thermal CVD is metal organic CVD (MOCVD).

[0169] For the formation of thin films (such as insulating films, semiconductor films, and conductive films) constituting a semiconductor device, methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating can be used.

[0170] When processing a thin film constituting a semiconductor device, it can be processed using photolithography or the like. In addition, the thin film may be processed by nanoimprinting, sandblasting, lift-off, etc. Also, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0171] Typically, there are the following two methods for photolithography. One is a method of forming a resist mask on a thin film to be processed, processing the thin film by etching or the like, and then removing the resist mask. The other is a method of forming a photosensitive thin film and then performing exposure and development to process the thin film into a desired shape.

[0172] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Further, exposure may be performed by immersion exposure technology. Also, as the light used for exposure, extreme ultraviolet (EUV) light or X-rays may be used. Instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0173] For etching a thin film, a dry etching method, a wet etching method, a sandblasting method, etc. can be used.

[0174] Each of FIGS. 7A to 11B shows a cross section at each stage of the manufacturing process of the transistor 100A. In each figure, cross sections in the channel length direction are arranged on the left side and cross sections in the channel width direction are arranged on the right side of the central broken line.

[0175] 〔Formation of conductive layer 106〕 A conductive film is formed on the substrate 102 and processed by etching to form a conductive layer 106 that functions as a first gate electrode (FIG. 7A).

[0176] 〔Formation of insulating layer 103〕 Subsequently, an insulating layer 103 is formed covering the substrate 102 and the conductive layer 106 (FIG. 7B). The insulating layer 103 can be formed using a PECVD method, an ALD method, a sputtering method, etc.

[0177] When the insulating layer 103 has a laminated structure, insulating films that will form the insulating layer 103 are formed in order. For example, when the insulating layer 103 has a laminated structure of a nitride film and an oxide film on the nitride film, the nitride film and the oxide film are formed in this order.

[0178] The nitride film included in the insulating layer 103 may have a stacked structure of two or more layers. For example, when the insulating layer 103 has a stacked structure including a first silicon nitride film, a second silicon nitride film on the first silicon nitride film, a third silicon nitride film on the second silicon nitride film, and a silicon oxynitride film on the third silicon nitride film, the first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the silicon oxynitride film are formed in this order.

[0179] When the insulating layer 103 has a stacked structure including a first silicon nitride film, a second silicon nitride film, a third silicon nitride film, and a silicon oxynitride film, the first silicon nitride film preferably has a function of blocking impurities. By providing the first silicon nitride film, diffusion of impurities from the layer below the insulating layer 103 to the layer above the insulating layer 103 can be suppressed. The second silicon nitride film preferably has low stress and high breakdown voltage. By providing the second silicon nitride film, the insulating layer 103 having low stress and high breakdown voltage can be obtained. The third silicon nitride film preferably has little release of impurities containing hydrogen and has a function of blocking impurities containing hydrogen. By providing the third silicon nitride film, diffusion of hydrogen into the channel formation region can be suppressed. The silicon oxynitride film preferably has a low defect density and little release of impurities containing hydrogen.

[0180] For example, the insulating layer 103 is formed by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia to form a first silicon nitride film having a function of blocking impurities. Next, a second silicon nitride film having low stress and high breakdown voltage is formed using a mixed gas with a higher ammonia flow rate than that of the first silicon nitride film. Next, a third silicon nitride film having a function of blocking impurities containing hydrogen and having less release of impurities containing hydrogen is formed using a mixed gas with a lower ammonia flow rate than that of the second silicon nitride film. Next, an oxynitride silicon film having a low defect density and less release of impurities containing hydrogen can be formed by using a mixed gas of silane and dinitrogen monoxide, and the insulating layer 103 can be formed. Further, by switching the film formation conditions in the same chamber, the first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the oxynitride silicon film can be continuously formed in a vacuum, and the insulating layer 103 can be formed with high productivity.

[0181] Alternatively, after forming the third silicon nitride film, a plasma treatment can be performed in an oxygen-containing atmosphere to oxidize the surface of the third silicon nitride film, thereby forming an oxynitride silicon film on the third silicon nitride film.

[0182] Compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film may have a lower film density. The difference in the film density of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be evaluated, for example, by the density (luminance) of a TEM image. Also, compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film may have a higher hydrogen concentration in the film. The difference in the hydrogen concentration of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be evaluated, for example, by secondary ion mass spectrometry (SIMS).

[0183] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method, an ion implantation method, or the like. Note that heat treatment may not be performed after forming the insulating layer 103.

[0184] 〔Formation of semiconductor layer 108〕 Subsequently, a metal oxide film is formed on the insulating layer 103, and this is processed to form island-shaped semiconductor layers 108 (FIG. 7C).

[0185] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0186] When forming the metal oxide film, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (oxygen flow rate ratio), the higher the crystallinity of the metal oxide film can be enhanced, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio, the lower the crystallinity of the metal oxide film, and a transistor with a higher on-current can be obtained.

[0187] When the semiconductor layer 108 has a stacked structure, it is preferable to continuously form films in the same film-forming chamber using the same sputtering target because the interface can be made good. In particular, as the film-forming conditions for each metal oxide film, conditions such as the pressure, temperature, and power during film formation may be different, but it is preferable to make the conditions other than the oxygen flow rate ratio the same because the time required for the film-forming process can be shortened. Also, when laminating metal oxide films with different compositions, it is preferable to continuously form films without exposure to the atmosphere.

[0188] The metal oxide film is preferably formed under conditions such that it is a metal oxide film having a CAAC structure, a metal oxide film having an nc structure, or a metal oxide film in which the CAAC structure and the nc structure coexist. Note that since the film formation conditions for the metal oxide film to have a CAAC structure and the film formation conditions for it to have an nc structure differ depending on the composition of the sputtering target used, in addition to the substrate temperature and oxygen flow rate ratio, the pressure, power, etc. may be appropriately set according to the composition.

[0189] As the film formation conditions for the metal oxide film, the substrate temperature may be set to be not lower than room temperature and not higher than 450°C, preferably not lower than room temperature and not higher than 300°C, more preferably not lower than room temperature and not higher than 200°C, and still more preferably not lower than room temperature and not higher than 140°C. For example, when a large glass substrate or a resin substrate is used for the substrate 102, if the substrate temperature is set to be not lower than room temperature and lower than 140°C, the productivity will be high, which is preferable. Also, by forming the metal oxide film at room temperature or without heating, the crystallinity can be lowered.

[0190] Before forming the metal oxide film, it is preferable to perform a treatment for desorbing water, hydrogen, organic substances, etc. adsorbed on the surface of the insulating layer 103, or a treatment for supplying oxygen into the insulating layer 103. For example, a heat treatment can be performed at a temperature of not lower than 70°C and not higher than 200°C in a reduced-pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. Also, when plasma treatment is performed in an atmosphere containing nitrous oxide gas, the organic substances on the surface of the insulating layer 103 can be preferably removed. After such treatment, it is preferable to continuously form the metal oxide film without exposing the surface of the insulating layer 103 to the atmosphere.

[0191] For processing the metal oxide film, either one or both of the wet etching method and the dry etching method may be used. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner.

[0192] After forming the metal oxide film or after processing the semiconductor layer 108, a heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment can typically be 150°C or higher and less than the strain point of the substrate, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower. Note that after forming the metal oxide film or after processing the semiconductor layer 108, the heat treatment may not be performed. Further, the heat treatment may be performed at any stage as long as it is after forming the metal oxide film. Also, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0193] The heat treatment can be performed in an atmosphere containing a rare gas or nitrogen. Alternatively, after heating in such an atmosphere, it may be heated in an atmosphere containing oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, ultra-dry air (CDA: Clean Dry Air) may be used. Note that it is preferable that the atmosphere of the above heat treatment does not contain hydrogen, water, etc. By using a gas purified to a dew point of -60°C or lower, preferably -100°C or lower, it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 108 as much as possible. The heat treatment can use an electric furnace, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0194] Note that after forming the semiconductor layer 108, it is preferable to form the insulating film 110f promptly. When the surface of the semiconductor layer 108 is exposed, water may be adsorbed on the surface of the semiconductor layer 108. When water is adsorbed on the surface of the semiconductor layer 108, hydrogen diffuses into the semiconductor layer 108 due to subsequent heat treatment or the like, and O VH may be formed. O Since VH can be a carrier generation source, it is preferable that the adsorbed water on the semiconductor layer 108 is less.

[0195] 〔Formation of Insulating Film 110f, Metal Oxide Film 114f, and Functional Film 113f〕 Subsequently, an insulating film 110f and a metal oxide film 114f are formed to cover the insulating layer 103 and the semiconductor layer 108.

[0196] The insulating film 110f is a film that will later become the insulating layer 110. As the insulating film 110f, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma chemical vapor deposition apparatus (PECVD apparatus, or simply referred to as a plasma CVD apparatus). Also, it may be formed using a PECVD method using microwaves.

[0197] When the insulating layer 110 has a laminated structure, the insulating films that will become the insulating layer 110 are formed in order. For example, as shown in FIG. 2, when the insulating layer 110 has a three-layer structure of an insulating layer 110a, an insulating layer 110b, and an insulating layer 110c, the insulating film that will become the insulating layer 110a, the insulating film that will become the insulating layer 110b, and the insulating film that will become the insulating layer 110c are formed in this order.

[0198] For example, the insulating layer 110 is formed by a plasma CVD method using a mixed gas of silane and dinitrogen monoxide to form an insulating film that will become the insulating layer 110a. Next, a mixed gas with a higher silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film that will become the insulating layer 110a is used, and an insulating film that will become the insulating layer 110b is formed under high power conditions. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film that will become the insulating layer 110b is used, and an insulating film that will become the insulating layer 110c is formed under low pressure conditions, and the insulating film that will become the insulating layer 110 can be formed. Also, by switching the film formation conditions in the same chamber, the insulating film that will become the insulating layer 110a, the insulating film that will become the insulating layer 110b, and the insulating film that will become the insulating layer 110c can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity.

[0199] For example, as shown in FIG. 3A, when the insulating layer 110 has a two-layer structure of an insulating layer 110a and an insulating layer 110c, the insulating film that will become the insulating layer 110a and the insulating film that will become the insulating layer 110c are formed in this order.

[0200] For example, the insulating layer 110 is formed by a plasma CVD method using a mixed gas of silane and dinitrogen monoxide to form an insulating film that becomes the insulating layer 110a. Next, an insulating film that becomes the insulating layer 110c can be formed under conditions of lower pressure and higher power than the insulating film that becomes the insulating layer 110a, and an insulating film that becomes the insulating layer 110 can be formed. Further, by switching the film formation conditions in the same chamber, the insulating film that becomes the insulating layer 110a and the insulating film that becomes the insulating layer 110c can be continuously formed in a vacuum, and the insulating film 110f can be formed with high productivity.

[0201] After the formation of the insulating film 110f, a heat treatment may be performed. By performing the heat treatment, impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f can be removed. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and rare gases. Note that after the formation of the insulating film 110f, the heat treatment may not be performed. Further, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Further, it may also be combined with a subsequent heat treatment or a process in which heat is applied.

[0202] The metal oxide film 114f is a film that will later become the metal oxide layer 114. The metal oxide film 114f is preferably formed by a sputtering method in an atmosphere containing oxygen, for example. Thereby, oxygen can be supplied to the insulating film 110f during the film formation of the metal oxide film 114f.

[0203] When the metal oxide film 114f is formed by a sputtering method using an oxide target containing the same metal oxide as in the case of the semiconductor layer 108 described above, the above description can be incorporated by reference.

[0204] The metal oxide film 114f may be formed by a reactive sputtering method using oxygen as a film formation gas and a metal target. When aluminum is used for the metal target, an aluminum oxide film can be formed.

[0205] When forming the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the film-forming gas introduced into the film-forming chamber of the film-forming apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the film-forming chamber, the more oxygen can be supplied into the insulating film 110f. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and still more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and make the oxygen partial pressure as close to 100% as possible.

[0206] Thus, by forming the metal oxide film 114f by the sputtering method in an atmosphere containing oxygen, it is possible to supply oxygen to the insulating film 110f and prevent oxygen from desorbing from the insulating film 110f when forming the metal oxide film 114f. As a result, an extremely large amount of oxygen can be confined in the insulating film 110f. Then, by subsequent heat treatment, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, oxygen deficiency in the channel formation region can be reduced, and a highly reliable transistor can be realized.

[0207] As the film-forming conditions of the metal oxide film 114f, the substrate temperature may be set to room temperature or higher and 450°C or lower, preferably room temperature or higher and 300°C or lower, more preferably room temperature or higher and 200°C or lower, and still more preferably room temperature or higher and 140°C or lower. For example, when a large glass substrate or a resin substrate is used for the substrate 102, if the substrate temperature is set to room temperature or higher and lower than 140°C, productivity will be high, which is preferable. Also, when the film-forming temperature of the metal oxide film 114f is high, the crystallinity of the metal oxide film 114f becomes high, and the etching rate may become slow. When the film-forming temperature of the metal oxide film 114f is low, the crystallinity of the metal oxide film 114f becomes low, and the etching rate may become fast. The film-forming temperature of the metal oxide film 114f may be appropriately selected so as to obtain a desirable etching rate with respect to the etchant used when processing the metal oxide film 114f.

[0208] After the formation of the metal oxide film 114f, heat treatment may be performed to supply oxygen from the insulating film 110f to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and noble gas. Note that heat treatment may not be necessary after the formation of the metal oxide film 114f. Also, the heat treatment may be performed at any stage as long as it is after the formation of the metal oxide film 114f. Further, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0209] Subsequently, a functional film 113f serving as the functional layer 113 is formed on the metal oxide film 114f (FIG. 8A). The functional film 113f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy.

[0210] Heat treatment may be performed after the formation of the functional film 113f. When a material containing oxygen is used for the functional film 113f, heat treatment after the formation of the functional film 113f can supply oxygen from the functional film 113f to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and noble gas. Note that heat treatment may not be necessary after the formation of the functional film 113f.

[0211] Subsequently, by etching a part of the functional film 113f, the metal oxide film 114f, the insulating film 110f, and the insulating layer 103, an opening 142 reaching the conductive layer 106 is formed (FIG. 8B). Thereby, the conductive layer 112 to be formed later and the conductive layer 106 can be electrically connected through the opening 142.

[0212] 〔Formation of the conductive film 112f〕 Subsequently, a conductive film 112f serving as the conductive layer 112 is formed on the functional film 113f (FIG. 9A). The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy.

[0213] 〔Formation of the insulating layer 110, the metal oxide layer 114, the functional layer 113, and the conductive layer 112〕 Subsequently, a resist mask 115 is formed on the conductive film 112f (FIG. 9B). Thereafter, in the regions not covered by the resist mask 115, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are removed to form the conductive layer 112, the functional layer 113, and the metal oxide layer 114 (FIG. 10A).

[0214] For the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, a wet etching method can be preferably used. For the wet etching method, for example, an etchant having hydrogen peroxide can be used. For example, an etchant having one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid can be used. In particular, when a material having copper is used for the conductive layer 112, an etchant having phosphoric acid, acetic acid, and nitric acid can be preferably used.

[0215] By configuring the etching rates of the metal oxide layer 114 and the functional layer 113 to be slower than that of the conductive layer 112, the functional layer 113, the metal oxide layer 114, and the conductive layer 112 can be formed in the same process. Further, the end portion of the conductive layer 112 can be made inner than the end portions of the metal oxide layer 114 and the functional layer 113. Also, since they can be formed in the same process, the process can be simplified and the productivity can be improved.

[0216] The end portions of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are processed so as to be located inner than the contour of the resist mask 115. For the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, it is preferable to use a wet etching method. By adjusting the etching time, the width of the region 108L can be controlled.

[0217] For the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, after etching the conductive film 112f, the functional film 113f, and the metal oxide film 114f using an anisotropic etching method, the side surfaces of the conductive film 112f, the functional film 113f, and the metal oxide film 114f may be etched using an isotropic etching method to retreat the end faces (also referred to as side etching). Thereby, in plan view, the conductive layer 112, the functional layer 113, and the metal oxide layer 114 whose ends are located inside the insulating layer 110 can be formed.

[0218] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the conductive layer 112 may retreat from the functional layer 113 and the metal oxide layer 114, and the film thickness of the functional layer 113 in the region where the conductive layer 112 does not overlap may be thinner than the film thickness of the functional layer 113 in the region where the conductive layer 112 overlaps (see FIGS. 5A, 5B, and 5C). Further, the film thickness of the metal oxide layer 114 in the region where the conductive layer 112 does not overlap may be thinner than the film thickness of the metal oxide layer 114 in the region where the conductive layer 112 and the functional layer 113 overlap (see FIGS. 6A, 6B, and 6C).

[0219] Note that for the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, different etching conditions or techniques may be used to etch in at least two steps. For example, the conductive film 112f may be etched first, and then the functional film 113f and the metal oxide film 114f may be etched under different etching conditions.

[0220] Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 10B). For the formation of the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but by leaving the resist mask 115, it is possible to suppress a reduction in the film thickness of the conductive layer 112.

[0221] After the formation of the insulating layer 110, the resist mask 115 is removed.

[0222] 〔Formation of Insulating Layer 116 and Region 108N (Hydrogen Supply Process)〕 Subsequently, a process of supplying hydrogen is performed on the exposed region of the semiconductor layer 108. Here, hydrogen is supplied by forming an insulating layer 116 containing hydrogen in contact with the exposed region of the semiconductor layer 108 (FIG. 11A).

[0223] The insulating layer 116 is preferably formed by plasma CVD using a film-forming gas containing hydrogen. For example, a silicon nitride film is formed using a film-forming gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the film. Also, it becomes possible to supply hydrogen to the exposed portion of the semiconductor layer 108 even during film formation.

[0224] After forming the insulating layer 116, it is preferable to perform a heat treatment to supply a part of the hydrogen released from the insulating layer 116 to a part of the semiconductor layer 108. The heat treatment is preferably performed at a temperature of 150°C or higher and 450°C or lower, preferably 200°C or higher and 400°C or lower, in an atmosphere containing one or more of nitrogen, oxygen, and rare gases.

[0225] By supplying hydrogen in this way, an extremely low-resistance region 108N can be formed in the semiconductor layer 108.

[0226] Oxygen can be supplied from the insulating layer 110 to the channel formation region of the semiconductor layer 108 by the heat treatment.

[0227] 〔Formation of Insulating Layer 118〕 Subsequently, an insulating layer 118 is formed on the insulating layer 116.

[0228] When forming the insulating layer 118 by plasma CVD method, if the film formation temperature is too high, depending on the impurities contained in the region 108N etc., there is a risk that the impurities diffuse into the periphery including the channel formation region of the semiconductor layer 108. As a result, there is a risk that the resistance of the channel formation region decreases or the resistance of the region 108N increases. The film formation temperature of the insulating layer 116 or the insulating layer 118 is preferably, for example, 150°C or higher and 400°C or lower, more preferably 180°C or higher and 360°C or lower, still more preferably 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0229] Heat treatment may be performed after the formation of the insulating layer 118.

[0230] 〔Formation of the openings 141a and 141b〕 Subsequently, after forming a mask by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the insulating layer 116 are etched to form the openings 141a and 141b reaching the region 108N.

[0231] 〔Formation of the conductive layers 120a and 120b〕 Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the openings 141a and 141b, and the conductive film is processed into a desired shape to form the conductive layers 120a and 120b (FIG. 11B).

[0232] Through the above steps, the transistor 100 can be fabricated.

[0233] <Components of the semiconductor device> Next, the components included in the semiconductor device of the present embodiment will be described in detail.

[0234] 〔Substrate〕 There are no major restrictions on the material of the substrate 102, etc., but at least, it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, a single-crystalline semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Also, those with semiconductor elements provided on these substrates may be used as the substrate 102.

[0235] As the substrate 102, a flexible substrate may be used, and transistors 100, etc. may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistors 100, etc. The release layer can be used to separate from the substrate 102 after partially or completely completing the semiconductor device thereon and transfer it to another substrate. At that time, the transistors 100, etc. can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0236] 〔Insulating layer 103〕 The insulating layer 103 can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD) method, etc. Also, as the insulating layer 103, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or in a stack. In order to improve the interface characteristics with the semiconductor layer 108, it is preferable that at least the region in the insulating layer 103 in contact with the semiconductor layer 108 is formed of an oxide insulating film. Also, it is preferable to use a film that releases oxygen by heating for the insulating layer 103.

[0237] As the insulating layer 103, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide, etc. may be used, and they can be provided as a single layer or in a stack.

[0238] When a film other than an oxide film such as a silicon nitride film is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform a pretreatment such as oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0239] [Conductive film] As the conductive layer 106 and the conductive layer 112 that function as gate electrodes, the conductive layer 120a that functions as one of the source electrode or the drain electrode, and the conductive layer 120b that functions as the other of the source electrode or the drain electrode, chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, a metal element selected therefrom, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements can be used to form each of them.

[0240] For the conductive layer 106, the conductive layer 112, the conductive layer 120a, and the conductive layer 120b, an oxide conductor such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, In-Ga-Zn oxide, or a metal oxide film can also be applied.

[0241] Here, the oxide conductor (OC: Oxide Conductor) will be described. For example, when oxygen deficiency is formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen deficiency, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide that has been converted into a conductor can be referred to as an oxide conductor.

[0242] As the conductive layer 106 or the like, a laminated structure of a conductive film containing the above-described oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may be used. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced. At this time, it is preferable to apply a conductive film containing an oxide conductor on the side in contact with the insulating layer that functions as a gate insulating film.

[0243] It is preferable that the conductive layers 106, 112, 120a, and 120b each have one or more selected from among titanium, tungsten, tantalum, and molybdenum, which are among the above-described metal elements. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has conductivity, has a high barrier property against copper, oxygen, or hydrogen, and emits little hydrogen from itself. Therefore, it can be suitably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[0244] 〔Insulating layer 110〕 The insulating layer 110 that functions as a gate insulating film for the transistor 100 or the like can be formed by a PECVD method, a sputtering method, or the like. As the insulating layer 110, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. Note that the insulating layer 110 may have a two-layer stacked structure or a three-layer or more stacked structure.

[0245] The insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the formed insulating layer 110 in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0246] As the insulating layer 110, a material such as hafnium oxide having a higher relative dielectric constant than silicon oxide or silicon oxynitride can also be used. Thereby, the film thickness of the insulating layer 110 can be increased and the leakage current due to the tunnel current can be suppressed. In particular, crystalline hafnium oxide is preferable because it has a higher relative dielectric constant than amorphous hafnium oxide.

[0247] 〔Semiconductor layer〕 When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used to form the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. Examples of the atomic ratio of the metal elements of such a sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc.

[0248] It is preferable to use a target containing a polycrystalline oxide as the sputtering target because it facilitates the formation of the semiconductor layer 108 having crystallinity. The atomic ratio of the semiconductor layer 108 to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio].

[0249] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or in the vicinity thereof, when In is 4, it includes the case where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. When the atomic ratio is described as In:Ga:Zn = 5:1:6 or in the vicinity thereof, when In is 5, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. When the atomic ratio is described as In:Ga:Zn = 1:1:1 or in the vicinity thereof, when In is 1, it includes the case where Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0250] The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having an energy gap wider than that of silicon in this way, the off-current of the transistor can be reduced.

[0251] It is preferable to use a metal oxide with a low carrier concentration for the semiconductor layer 108. When reducing the carrier concentration of the metal oxide, the impurity concentration in the metal oxide may be lowered and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in the metal oxide include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0252] In particular, hydrogen contained in the metal oxide may react with oxygen bonded to the metal atom to form water, and thus oxygen vacancies may be formed in the metal oxide. If the channel formation region in the metal oxide contains oxygen vacancies, the transistor may have normally-on characteristics. Further, a defect in which hydrogen enters the oxygen vacancy may function as a donor, and electrons serving as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to the metal atom to generate electrons serving as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen tends to have normally-on characteristics.

[0253] A defect in which hydrogen enters the oxygen vacancy may function as a donor in the metal oxide. However, it is difficult to quantitatively evaluate the defect. Therefore, in the metal oxide, it may be evaluated by the carrier concentration instead of the donor concentration. Thus, in this specification and the like, as a parameter of the metal oxide, the carrier concentration assuming a state where no electric field is applied may be used instead of the donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as the "donor concentration" in some cases.

[0254] Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , even more preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0255] The carrier concentration of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 , even more preferably less than 1×10 16 cm -3 , still even more preferably less than 1×10 13 cm -3 , still even more preferably less than 1×10 12 cm -3 , and still even more preferably less than 1×10 -9 cm -3 . Note that the lower limit value of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, and for example, it can be set to 1×10 -9 cm -3 .

[0256] The semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later. Among the non-single crystal structures, the amorphous structure has the highest density of defect levels, and the CAAC structure has the lowest density of defect levels.

[0257] Hereinafter, CAAC (c-axis aligned crystal) will be described. CAAC represents an example of a crystal structure.

[0258] The CAAC structure is one of the crystal structures such as a thin film having a plurality of nanocrystals (crystalline regions with a maximum diameter of less than 10 nm). Each nanocrystal has a characteristic that the c-axis is oriented in a specific direction, the a-axis and the b-axis have no orientation, and the nanocrystals are continuously connected without forming grain boundaries with each other. In particular, a thin film having a CAAC structure has a characteristic that the c-axis of each nanocrystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

[0259] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. On the other hand, since it is not possible to confirm clear crystal grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable.

[0260] Here, in crystallography, it is common to take a unit cell with a specific axis as the c-axis for the three axes (crystal axes) of the a-axis, b-axis, and c-axis that make up the unit cell. In particular, in a crystal having a layered structure, it is common to use two axes parallel to the plane direction of the layer as the a-axis and the b-axis, and the axis intersecting the layer as the c-axis. As a typical example of such a crystal having a layered structure, there is graphite classified into the hexagonal system. The a-axis and the b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, the crystal of InGaZnO4 having a YbFe2O4-type crystal structure, which is a layered structure, can be classified into the hexagonal system. The a-axis and the b-axis of its unit cell are parallel to the plane direction of the layer, and the c-axis is perpendicular to the layer (that is, the a-axis and the b-axis).

[0261] An oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film) may not allow the crystal part to be clearly confirmed in an observation image by TEM. The crystal parts contained in the microcrystalline oxide semiconductor film often have a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystal) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is called an nc-OS (nanocrystalline Oxide Semiconductor) film. Also, in an observation image by TEM, for example, the grain boundaries of the nc-OS film may not be clearly confirmed.

[0262] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, the nc-OS film shows no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is seen in the whole film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays with a diameter larger than that of the crystal part, no peak indicating a crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also called restricted field electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also called nano-beam electron beam diffraction) on the nc-OS film using an electron beam with a probe diameter close to or smaller than that of the crystal part (for example, 1 nm or more and 30 nm or less), regions with high luminance are observed in a circular (ring-shaped) manner, and a plurality of spots may be observed within the regions.

[0263] The nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However, in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier concentration and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility.

[0264] The nc-OS film can be formed by reducing the oxygen flow rate ratio during film formation compared with the CAAC-OS film. Also, the nc-OS film can be formed by reducing the substrate temperature during film formation compared with the CAAC-OS film. For example, since the nc-OS film can be formed even when the substrate temperature is relatively low (for example, a temperature of 130 °C or lower) or when the substrate is not heated, it is suitable for use when using a large glass substrate, a resin substrate, etc., and the productivity can be increased.

[0265] An example of the crystal structure of a metal oxide will be described. Hereinafter, a metal oxide formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be described as an example. When the substrate temperature is 100 °C or higher and 130 °C or lower and the metal oxide is formed by the sputtering method using the above target, it is likely to have either an nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, when the substrate temperature is room temperature (R.T.) and the metal oxide is formed by the sputtering method, it is likely to have an nc crystal structure. Here, the room temperature (R.T.) as used herein includes the temperature when the substrate is not heated.

[0266] <Constitution of Metal Oxide> Hereinafter, the constitution of CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one aspect of the present invention will be described.

[0267] In this specification and the like, CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) may be described. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material composition.

[0268] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) serving as carriers, and the insulating function is the function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating the respective functions, both functions can be maximally enhanced.

[0269] CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0270] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0271] CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide band gap due to an insulating region and a component having a narrow band gap due to a conductive region. In this configuration, when carriers flow, the carriers mainly flow in the component having the narrow band gap. Also, the component having the narrow band gap acts complementarily to the component having the wide band gap, and carriers also flow in the component having the wide band gap in conjunction with the component having the narrow band gap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0272] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0273] The above is the description of the components.

[0274] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

[0275] (Embodiment 2) In this embodiment, an example of a display device having the transistor exemplified in the previous embodiment will be described.

[0276] <Configuration Example> FIG. 12A shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together by a sealing material 712. In a region sealed by the first substrate 701, the second substrate 705, and the sealing material 712, a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided on the first substrate 701. A plurality of display elements are provided in the pixel portion 702.

[0277] An FPC terminal portion 708 to which an FPC 716 (FPC: Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Through the FPC 716, various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC terminal portion 708 and signal lines 710.

[0278] A plurality of gate driver circuit portions 706 may be provided. Also, the gate driver circuit portion 706 and the source driver circuit portion 704 may be separately formed on a semiconductor substrate or the like and may be in the form of packaged IC chips. The IC chips can be mounted on the first substrate 701 or the FPC 716.

[0279] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be applied with the transistors of a semiconductor device according to an aspect of the present invention.

[0280] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light emitting elements. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used. Further, examples of the light emitting element include self-luminous light emitting elements such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. In addition, a MEMS (Micro Electro Mechanical Systems) element of a shutter method or an optical interference method, a display element to which a microcapsule method, an electrophoresis method, an electro-wetting method, or an electronic ink (registered trademark) method is applied, or the like can also be used.

[0281] The display device 700A shown in FIG. 12B is an example of a display device that can be used as a flexible display in which a resin layer 743 having flexibility is applied instead of the first substrate 701.

[0282] The display device 700A has a shape in which the pixel section 702 is not rectangular but has arcuate corners. Further, as shown in the region P1 in FIG. 12B, the pixel section 702 and a part of the resin layer 743 have a cutout portion. The pair of gate driver circuit sections 706 are provided on both sides with the pixel section 702 interposed therebetween. Further, the gate driver circuit section 706 is provided along an arcuate contour at the corners of the pixel section 702.

[0283] The resin layer 743 has a shape in which a portion where the FPC terminal section 708 is provided protrudes. Further, a part of the resin layer 743 including the FPC terminal section 708 can be folded back to the back side in the region P2 in FIG. 12B. By folding back a part of the resin layer 743, the display device 700A can be mounted on an electronic device in a state where the FPC 716 is arranged to overlap the back side of the pixel section 702, and the space saving of the electronic device can be achieved.

[0284] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as a source driver circuit, for example. At this time, the source driver circuit section 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0285] The display device 700B shown in FIG. 12C is a display device that can be suitably used for an electronic device having a large screen. The display device 700B can be suitably used for, for example, a television device, a monitor device, a personal computer (including a notebook type or a desktop type), a tablet terminal, digital signage, and the like.

[0286] The display device 700B has a plurality of source driver ICs 721 and a pair of gate driver circuit sections 722.

[0287] The plurality of source driver ICs 721 are each attached to an FPC 723. Further, one terminal of each of the plurality of FPCs 723 is connected to the first substrate 701, and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby saving space in the electronic device.

[0288] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. Thereby, an electronic device with a narrow bezel can be realized.

[0289] With such a configuration, a large and high-resolution display device can be realized. For example, a display device with a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more in diagonal can be realized. In addition, a display device with an extremely high resolution such as 4K2K or 8K4K can be realized.

[0290] <Cross-sectional configuration example> Hereinafter, a configuration using a liquid crystal element as a display element and a configuration using an EL element will be described with reference to FIGS. 13 to 16. FIGS. 13 to 15 are cross-sectional views taken along the dashed-dotted line Q-R shown in FIG. 12A, respectively. FIG. 16 is a cross-sectional view taken along the dashed-dotted line S-T in the display device 700A shown in FIG. 12B. FIGS. 13 and 14 show a configuration using a liquid crystal element as a display element, and FIGS. 15 and 16 show a configuration using an EL element.

[0291] 〔Explanation of the common part of the display device〕 The display devices shown in FIGS. 13 to 16 include a routing wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The routing wiring portion 711 has signal lines 710. The pixel portion 702 includes transistors 750 and capacitor elements 790. The source driver circuit portion 704 includes a transistor 752. FIG. 14 shows a case where the capacitor element 790 is absent.

[0292] As the transistors 750 and 752, the transistors exemplified in Embodiment 1 can be applied.

[0293] The transistor used in this embodiment has an oxide semiconductor film with high purity and suppression of the formation of oxygen deficiency. The transistor can reduce the off-current. Therefore, the holding time of an electrical signal such as an image signal can be extended, and the writing interval of an image signal or the like can also be set longer. Therefore, the frequency of the refresh operation can be reduced, and the effect of reducing power consumption is achieved.

[0294] Since the transistor used in this embodiment can obtain a relatively high field-effect mobility, high-speed driving is possible. For example, by using such a transistor capable of high-speed driving in a display device, the switching transistor in the pixel portion and the driver transistor used in the driving circuit portion can be formed on the same substrate. That is, a configuration that does not apply a driving circuit formed by a silicon wafer or the like is also possible, and the number of components of the display device can be reduced. Also, in the pixel portion, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0295] The capacitive element 790 shown in FIGS. 13, 15, and 16 has a lower electrode formed by processing a film identical to the first gate electrode of the transistor 750, and an upper electrode formed by processing a metal oxide identical to the semiconductor layer. The upper electrode is made to have a low resistance similar to the source region and drain region of the transistor 750. Also, a part of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitive element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. Further, a wiring obtained by processing a film identical to the source electrode and drain electrode of the transistor is connected to the upper electrode.

[0296] A planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitive element 790.

[0297] For the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704, transistors having different structures may be used. For example, a configuration may be adopted in which a top gate type transistor is applied to one of them and a bottom gate type transistor is applied to the other. Note that the same applies to the gate driver circuit portion 706 as to the source driver circuit portion 704.

[0298] The signal line 710 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752. At this time, it is preferable to use a low-resistance material such as a material containing copper element because signal delay and the like due to wiring resistance are small and display on a large screen becomes possible.

[0299] The FPC terminal portion 708 has a wiring 760 that partially functions as a connection electrode, an anisotropic conductive film 780, and an FPC 716. The wiring 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0300] As the first substrate 701 and the second substrate 705, a flexible substrate such as a glass substrate or a plastic substrate can be used, for example. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistor 750 or the like.

[0301] On the second substrate 705 side, a light-shielding film 738, a coloring film 736, and an insulating film 734 in contact with these are provided.

[0302] 〔Configuration example of a display device using a liquid crystal element〕 The display device 700 shown in FIG. 13 includes a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or the drain electrode of the transistor 750. The conductive layer 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0303] For the conductive layer 772, a material that is transparent to visible light or a reflective material can be used. As the transparent material, for example, an oxide material containing indium, zinc, tin, or the like may be used. As the reflective material, for example, a material containing aluminum, silver, or the like may be used.

[0304] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a transparent material is used for the conductive layer 772, it becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0305] The display device 700 shown in FIG. 14 shows an example using a liquid crystal element 775 of the horizontal electric field type (for example, FFS mode). A conductive layer 774 that functions as a common electrode is provided on the conductive layer 772 via an insulating layer 773. The alignment state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive layer 772 and the conductive layer 774.

[0306] In FIG. 14, the holding capacitance can be configured by the laminated structure of the conductive layer 774, the insulating layer 773, and the conductive layer 772. Therefore, it is not necessary to separately provide a capacitance element, and the aperture ratio can be increased.

[0307] Although not shown in FIGS. 13 and 14, a configuration may be adopted in which an alignment film in contact with the liquid crystal layer 776 is provided. Further, optical members (optical substrates) such as polarizing members, retardation members, and antireflection members, and light sources such as backlights and side lights can be appropriately provided.

[0308] For the liquid crystal layer 776, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal (PDLC), a polymer network liquid crystal (PNLC), a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Further, when adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used.

[0309] As the mode of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, etc. can be used.

[0310] It is also possible to use a scattering type liquid crystal such as a polymer dispersed liquid crystal or a polymer network liquid crystal in the liquid crystal layer 776. At this time, it may be configured to perform black and white display without providing the color film 736, or it may be configured to perform color display using the color film 736.

[0311] As a driving method of the liquid crystal element, a time-division display method (also referred to as a field sequential driving method) that performs color display based on a sequential addition color mixing method may be applied. In that case, the configuration may be such that the color film 736 is not provided. When the time-division display method is used, for example, it is not necessary to provide sub-pixels that exhibit each of the colors R (red), G (green), and B (blue), so there are advantages such as improving the aperture ratio of the pixels and enhancing the fineness.

[0312] [Display device using a light-emitting element] The display device 700 shown in FIG. 15 has a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0313] Examples of materials that can be used for the organic compound include fluorescent materials or phosphorescent materials. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, and the like.

[0314] In the display device 700 shown in FIG. 15, an insulating film 730 that covers a part of the conductive layer 772 is provided on the planarizing insulating film 770. Here, the light-emitting element 782 has a light-transmissive conductive film 788 and is a top emission type light-emitting element. Note that the light-emitting element 782 may have a bottom emission structure that emits light to the conductive layer 772 side, or a dual emission structure that emits light to both the conductive layer 772 side and the conductive film 788 side.

[0315] The color filter 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided at positions overlapping with the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. Further, the color filter 736 and the light-shielding film 738 are covered with the insulating film 734. Also, the space between the light-emitting element 782 and the insulating film 734 is filled with the sealing film 732. Note that when the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, when formed by painting, the color filter 736 may not be provided.

[0316] FIG. 16 shows a configuration of a display device suitably applicable to a flexible display. FIG. 16 is a cross-sectional view taken along the dashed-dotted line S-T in the display device 700A shown in FIG. 12B.

[0317] The display device 700A shown in FIG. 16 has a configuration in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated instead of the first substrate 701 shown in FIG. 15. Transistors 750, capacitor elements 790, etc. are provided on the insulating layer 744 provided on the resin layer 743.

[0318] The support substrate 745 includes an organic resin, glass, etc., and is a substrate that is thin enough to have flexibility. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The insulating layer 744 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by the adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0319] The display device 700 shown in FIG. 16 has a protective layer 740 instead of the substrate 705 shown in FIG. 15. The protective layer 740 is bonded to the sealing film 732. As the protective layer 740, a glass substrate, a resin film, etc. can be used. Also, as the protective layer 740, an optical member such as a polarizing plate or a diffusing plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be applied.

[0320] The EL layer 786 of the light-emitting element 782 is provided in an island shape on the insulating film 730 and the conductive layer 772. By making the EL layer 786 different in light-emitting color for each sub-pixel, color display can be realized without using the color filter 736. Further, a protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. It is preferable to use an inorganic insulating film for the protective layer 741. More preferably, a laminated structure including one or more inorganic insulating films and one or more organic insulating films is used.

[0321] In FIG. 16, a foldable region P2 is shown. In the region P2, in addition to the support substrate 745 and the adhesive layer 742, there is a portion where an inorganic insulating film such as the insulating layer 744 is not provided. Further, in the region P2, a resin layer 746 is provided to cover the wiring 760. By forming a configuration in which an inorganic insulating film is not provided as much as possible in the foldable region P2 and only a conductive layer containing a metal or an alloy and a layer containing an organic material are laminated, it is possible to prevent cracks from occurring when bent. Further, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0322] 〔Configuration example of providing an input device in the display device〕 An input device may be provided in the display device shown in FIGS. 13 to 16. Examples of the input device include a touch sensor and the like.

[0323] For example, as the sensor method, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used. Or, two or more of these may be used in combination.

[0324] Note that the configuration of the touch panel includes a so-called in-cell type touch panel in which the input device is formed between a pair of substrates, a so-called on-cell type touch panel in which the input device is formed on the display device, or a so-called out-cell type touch panel that is attached to and used with the display device.

[0325] The configuration examples illustrated in this embodiment, and the corresponding drawings and the like can be implemented by appropriately combining at least a part of them with other configuration examples, or drawings and the like.

[0326] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0327] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to one aspect of the present invention will be described with reference to FIG. 17.

[0328] The display device shown in FIG. 17A includes a pixel portion 502, a drive circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that the protection circuit 506 may not be provided. In FIG. 17A, hatching is applied to the pixel circuit 501 to distinguish it from the protection circuit 506.

[0329] The transistors included in the pixel portion 502 and the drive circuit portion 504 can be the transistors according to one aspect of the present invention. The transistors according to one aspect of the present invention may also be applied to the protection circuit 506.

[0330] The pixel portion 502 includes a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more).

[0331] The drive circuit portion 504 includes drive circuits such as a gate driver 504a that outputs a scan signal to scan lines GL_1 to GL_X and a source driver 504b that supplies a data signal to data lines DL_1 to DL_Y. The gate driver 504a may be configured to include at least a shift register. The source driver 504b is configured using, for example, a plurality of analog switches or the like. The source driver 504b may also be configured using a shift register or the like.

[0332] The terminal portion 507 refers to a portion where terminals for inputting power supply, control signals, image signals, etc. from an external circuit to the display device are provided.

[0333] The protection circuit 506 is a circuit that makes a wiring to which it is connected and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected. The protection circuit 506 shown in FIG. 17A is connected to various wirings such as scanning lines GL_1 to GL_X which are wirings between the gate driver 504a and the pixel circuit 501, or data lines DL_1 to DL_Y which are wirings between the source driver 504b and the pixel circuit 501.

[0334] The gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel portion 502, respectively, or a substrate on which a gate driver circuit or a source driver circuit is separately formed (for example, a driving circuit substrate formed of a single crystal semiconductor or a polycrystalline semiconductor) may be mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0335] The plurality of pixel circuits 501 shown in FIG. 17A can have, for example, the configurations shown in FIGS. 17B and 17C.

[0336] The pixel circuit 501 shown in FIG. 17B includes a liquid crystal element 570, a transistor 550, and a capacitor element 560. Further, a data line DL_n, a scanning line GL_m, a potential supply line VL, etc. are connected to the pixel circuit 501.

[0337] One potential of a pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The liquid crystal element 570 has its alignment state set by the data to be written. Note that a common potential (common potential) may be applied to one of a pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Also, different potentials may be applied to one of a pair of electrodes of the liquid crystal element 570 of the pixel circuits 501 in each row.

[0338] The pixel circuit 501 shown in FIG. 17C includes transistors 552 and 554, a capacitor element 562, and a light-emitting element 572. Further, a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a potential supply line VL_b, etc. are connected to the pixel circuit 501.

[0339] Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled according to the potential applied to the gate of the transistor 554, thereby controlling the emission luminance from the light-emitting element 572.

[0340] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other configuration examples, drawings, etc.

[0341] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0342] (Embodiment 4) Hereinafter, a pixel circuit including a memory for correcting the gradation displayed on a pixel and a display device having the same will be described. The transistor illustrated in Embodiment 1 can be applied to the transistor used in the pixel circuit illustrated below.

[0343] <Circuit Configuration> FIG. 18A shows a circuit diagram of the pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. Further, a wiring S1, a wiring S2, a wiring G1, and a wiring G2 are connected to the pixel circuit 400.

[0344] The gate of the transistor M1 is connected to the wiring G1, one of the source and the drain is connected to the wiring S1, and the other of the source and the drain is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring G2, one of the source and the drain is connected to the wiring S2, and the other of the source and the drain is connected to the other electrode of the capacitor C1 and the circuit 401.

[0345] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, light-emitting elements such as organic EL elements and LED elements, liquid crystal elements, or MEMS (Micro Electro Mechanical Systems) elements can be applied.

[0346] Let the node connecting the transistor M1 and the capacitor C1 be node N1, and the node connecting the transistor M2 and the circuit 401 be node N2.

[0347] The pixel circuit 400 can hold the potential of node N1 by turning off the transistor M1. Also, the potential of node N2 can be held by turning off the transistor M2. Further, with the transistor M2 turned off, by writing a predetermined potential to node N1 via the transistor M1, the potential of node N2 can be changed according to the displacement of the potential of node N1 by capacitive coupling via the capacitor C1.

[0348] Here, a transistor in which an oxide semiconductor exemplified in Embodiment 1 is applied can be applied to one or both of the transistor M1 and the transistor M2. Therefore, due to an extremely low off-current, the potentials of node N1 and node N2 can be held for a long period. When the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or more, etc.), a transistor using a semiconductor such as silicon may be used.

[0349] <Example of driving method> Subsequently, an example of the operation method of the pixel circuit 400 will be described with reference to FIG. 18B. FIG. 18B is a timing chart related to the operation of the pixel circuit 400. Here, for ease of explanation, the effects of various resistances such as wiring resistance, parasitic capacitances of transistors and wirings, and threshold voltages of transistors are not considered.

[0350] In the operation shown in FIG. 18B, one frame period is divided into a period T1 and a period T2. The period T1 is a period for writing a potential to the node N2, and the period T2 is a period for writing a potential to the node N1.

[0351] 〔Period T1〕 In the period T1, a potential for turning on the transistors is applied to both the wiring G1 and the wiring G2. Also, a potential V ref which is a fixed potential is supplied to the wiring S1, and a first data potential V w is supplied to the wiring S2.

[0352] To the node N1, a potential V ref is applied from the wiring S1 via the transistor M1. Also, to the node N2, a first data potential V w is applied from the wiring S2 via the transistor M2. Therefore, a potential difference V w -V ref is held in the capacitor C1.

[0353] 〔Period T2〕 Subsequently, in the period T2, a potential for turning on the transistor M1 is applied to the wiring G1, and a potential for turning off the transistor M2 is applied to the wiring G2. Also, a second data potential V data is supplied to the wiring S1. A predetermined fixed potential may be applied to the wiring S2, or it may be in a floating state.

[0354] To the node N1, a second data potential V data is applied from the wiring S1 via the transistor M1. At this time, due to the capacitive coupling by the capacitor C1, the potential of the node N2 changes by a potential dV according to the second data potential V data . That is, a potential obtained by adding the first data potential V w and the potential dV is input to the circuit 401. Although FIG. 18B shows that the potential dV is a positive value, it may be a negative value. That is, the second data potential V data may be lower than the potential V ref .

[0355] Here, the potential dV is generally determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes a potential close to the second data potential V data near the potential.

[0356] In this way, since the pixel circuit 400 can generate a potential for supplying two types of data signals to the circuit 401 including the display element, it becomes possible to perform gradation correction within the pixel circuit 400.

[0357] Also, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Also, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0358] <Application Example> [Example Using a Liquid Crystal Element] The pixel circuit 400LC shown in FIG. 18C has a circuit 401LC. The circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0359] One electrode of the liquid crystal element LC is connected to the other electrode of the capacitor C1, the other of the source and drain of the transistor M2, and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which the potential V com2 is applied. The capacitor C2 has the other electrode connected to a wiring to which the potential V com1 is applied.

[0360] The capacitor C2 functions as a holding capacitor. Note that the capacitor C2 can be omitted if it is not necessary.

[0361] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, high-speed display can be realized by overdrive driving, and a liquid crystal material with a high driving voltage can be applied. Also, by supplying a correction signal to the wiring S1 or the wiring S2, gradation can be corrected according to the use temperature, the deterioration state of the liquid crystal element LC, or the like.

[0362] [Example using a light-emitting element] The pixel circuit 400EL shown in FIG. 18D has a circuit 401EL. The circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0363] The transistor M3 has a gate connected to one electrode of the capacitor C2, a source or a drain connected to a wiring to which a potential V H is applied, and the other connected to one electrode of the light-emitting element EL, respectively. The capacitor C2 has the other electrode connected to a wiring to which a potential V com is applied. The light-emitting element EL has the other electrode connected to a wiring to which a potential V L is applied.

[0364] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a holding capacitor. The capacitor C2 can be omitted if not necessary.

[0365] Here, a configuration in which the anode side of the light-emitting element EL is connected to the transistor M3 is shown, but the transistor M3 may be connected to the cathode side. In that case, the values of the potential V H and the potential V L can be appropriately changed.

[0366] By applying a high potential to the gate of the transistor M3, a large current can flow through the light-emitting element EL, so that, for example, HDR display can be realized. Also, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0367] Note that the present invention is not limited to the circuits illustrated in FIGS. 18C and 18D, and a configuration in which transistors, capacitors, etc. are separately added may also be used.

[0368] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0369] (Embodiment 5) In this embodiment, a display module that can be manufactured using one aspect of the present invention will be described.

[0370] The display module 6000 shown in FIG. 19A includes a display device 6006, a frame 6009, a printed circuit board 6010, and a battery 6011 to which an FPC 6005 is connected between an upper cover 6001 and a lower cover 6002.

[0371] For example, a display device manufactured using one aspect of the present invention can be used as the display device 6006. With the display device 6006, a display module with extremely low power consumption can be realized.

[0372] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape and dimensions according to the size of the display device 6006.

[0373] The display device 6006 may have a function as a touch panel.

[0374] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0375] The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0376] FIG. 19B is a schematic cross-sectional view of the display module 6000 including an optical touch sensor.

[0377] The display module 6000 includes a light emitting unit 6015 and a light receiving unit 6016 provided on the printed circuit board 6010. Further, it has a pair of light guide parts (light guide part 6017a, light guide part 6017b) in a region surrounded by the upper cover 6001 and the lower cover 6002.

[0378] The display device 6006 is provided so as to overlap with the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.

[0379] The light 6018 emitted from the light emitting portion 6015 passes through the upper part of the display device 6006 by the light guide portion 6017a and reaches the light receiving portion 6016 through the light guide portion 6017b. For example, when the light 6018 is blocked by a detected object such as a finger or a stylus, a touch operation can be detected.

[0380] A plurality of light emitting portions 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving portions 6016 are provided at positions facing the light emitting portions 6015. Thereby, information on the position where the touch operation is performed can be acquired.

[0381] As the light emitting portion 6015, a light source such as an LED element can be used, and in particular, a light source that emits infrared rays is preferably used. As the light receiving portion 6016, a photoelectric element that receives the light emitted from the light emitting portion 6015 and converts it into an electrical signal can be used. Preferably, a photodiode capable of receiving infrared rays can be used.

[0382] By the light guide portions 6017a and 6017b that transmit the light 6018, the light emitting portion 6015 and the light receiving portion 6016 can be arranged below the display device 6006, and it is possible to suppress external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, when a resin that absorbs visible light and transmits infrared rays is used, malfunction of the touch sensor can be more effectively suppressed.

[0383] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0384] (Embodiment 6) In this embodiment, examples of electronic devices to which the display device according to one aspect of the present invention can be applied will be described.

[0385] The electronic device 6500 shown in FIG. 20A is a portable information terminal that can be used as a smartphone.

[0386] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, etc. The display unit 6502 has a touch panel function.

[0387] The display device according to an aspect of the present invention can be applied to the display unit 6502.

[0388] FIG. 20B is a schematic cross-sectional view including an end portion on the microphone 6506 side of the housing 6501.

[0389] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in a space surrounded by the housing 6501 and the protective member 6510.

[0390] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0391] In a region outside the display unit 6502, a part of the display panel 6511 is folded back. An FPC 6515 is connected to the folded-back portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on the printed circuit board 6517.

[0392] The flexible display panel according to an aspect of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Further, since the display panel 6511 is extremely thin, it is possible to mount a large-capacity battery 6518 while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow bezel can be realized.

[0393] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0394] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured using one aspect of the present invention will be described.

[0395] The electronic devices exemplified below include a display device according to one aspect of the present invention in a display unit. Therefore, it is an electronic device that realizes a high resolution. Also, it can be an electronic device that achieves both a high resolution and a large screen.

[0396] In the display unit of the electronic device according to one aspect of the present invention, for example, video having a resolution of full high vision, 4K2K, 8K4K, 16K8K, or higher can be displayed.

[0397] Examples of the electronic device include, in addition to electronic devices having a relatively large screen such as a television device, a notebook personal computer, a monitor device, a digital signage, a pachinko machine, and a game machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproduction device, and the like.

[0398] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of an inner wall or outer wall of a house or building, an interior or exterior of an automobile, or the like.

[0399] Figure 21A is a diagram showing the appearance of the camera 8000 with the finder 8100 attached.

[0400] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000.

[0401] Note that the camera 8000 may have the lens 8006 and the housing integrated.

[0402] The camera 8000 can be imaged by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel.

[0403] The housing 8001 has a mount with electrodes, and in addition to the viewfinder 8100, a strobe device or the like can be connected.

[0404] The viewfinder 8100 has a housing 8101, a display unit 8102, buttons 8103, etc.

[0405] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image or the like received from the camera 8000 on the display unit 8102.

[0406] The button 8103 has a function as a power button or the like.

[0407] The display device according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0408] FIG. 21B is a diagram showing the appearance of the head-mounted display 8200.

[0409] The head-mounted display 8200 has a mounting portion 8201, a lens 8202, a main body 8203, a display unit 8204, a cable 8205, etc. A battery 8206 is built in the mounting portion 8201.

[0410] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 is equipped with a wireless receiver and the like, and can display the received video information on the display unit 8204. Further, the main body 8203 is equipped with a camera, and information on the movement of the user's eyeballs and eyelids can be used as input means.

[0411] The mounting portion 8201 may be provided with a plurality of electrodes capable of detecting an electric current flowing along with the movement of the user's eyeballs at a position where it touches the user, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the user's pulse based on the current flowing through the electrodes. Further, the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204, or a function of changing the video displayed on the display unit 8204 in accordance with the movement of the user's head.

[0412] The display device according to an aspect of the present invention can be applied to the display unit 8204.

[0413] Figures 21C, 21D, and 21E are views showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0414] The user can visually recognize the display of the display unit 8302 through the lenses 8305. It is preferable to arrange the display unit 8302 in a curved shape because the user can feel a high sense of immersion. Further, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the configuration is not limited to providing one display unit 8302, and two display units 8302 may be provided, with one display unit arranged for each of the user's eyes.

[0415] Note that the display device according to one aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to one aspect of the present invention has extremely high definition, even if it is enlarged using the lens 8305 as shown in FIG. 21E, pixels cannot be visually recognized by the user, and a more realistic video can be displayed.

[0416] The electronic device shown in FIGS. 22A to 22G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, and the like.

[0417] The electronic device shown in FIGS. 22A to 22G has various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. Further, the electronic device may be provided with a camera or the like and have functions such as taking still images and moving images and storing them in a recording medium (external or built in the camera), and a function of displaying the taken images on the display unit.

[0418] Details of the electronic device shown in FIGS. 22A to 22G will be described below.

[0419] FIG. 22A is a perspective view showing a television device 9100. The television device 9100 can incorporate a display unit 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

[0420] FIG. 22B is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Further, the portable information terminal 9101 can display character and image information on a plurality of its surfaces. FIG. 22B shows an example in which three icons 9050 are displayed. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming calls such as e-mail, SNS, and telephone, titles of e-mail and SNS, sender names, dates, times, remaining battery levels, antenna reception strengths, etc. Alternatively, an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0421] FIG. 22C is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are respectively displayed on different surfaces. For example, the user can also confirm the information 9053 displayed at a position where it can be observed from above the portable information terminal 9102 in a state where the portable information terminal 9102 is stored in the breast pocket of a coat. The user can check the display without taking the portable information terminal 9102 out of the pocket and can, for example, determine whether or not to answer a call.

[0422] FIG. 22D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch (registered trademark). Also, the display surface of the display unit 9001 is provided to be curved, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can also make a hands-free call by communicating with, for example, a wirelessly communicable headset. Also, the portable information terminal 9200 can perform data transmission with other information terminals and charging by means of the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0423] FIG. 22E, FIG. 22F, and FIG. 22G are perspective views showing a foldable mobile information terminal 9201. Further, FIG. 22E shows the unfolded state of the mobile information terminal 9201, FIG. 22G shows the folded state, and FIG. 22F is a perspective view of the state in the middle of changing from one of FIG. 22E and FIG. 22G to the other. The mobile information terminal 9201 has excellent portability in the folded state and excellent display listability due to a seamless wide display area in the unfolded state. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0424] An example of a television apparatus is shown in FIG. 23A. In the television apparatus 7100, a display unit 7500 is incorporated in a housing 7101. Here, a configuration in which the housing 7101 is supported by a stand 7103 is shown.

[0425] The operation of the television apparatus 7100 shown in FIG. 23A can be performed by an operation switch provided in the housing 7101 or a separate remote control operation unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television apparatus 7100 may be operated by touching it. The remote control operation unit 7111 may have a display unit in addition to operation buttons.

[0426] Note that the television apparatus 7100 may have a television broadcast receiver or a communication device for network connection.

[0427] A notebook personal computer 7200 is shown in FIG. 23B. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display unit 7500 is incorporated in the housing 7211.

[0428] An example of digital signage is shown in FIGS. 23C and 23D.

[0429] The digital signage 7300 shown in FIG. 23C includes a housing 7301, a display unit 7500, a speaker 7303, etc. Furthermore, it can have an LED lamp, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

[0430] FIG. 23D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0431] The larger the display unit 7500 is, the more information can be provided at one time, and it is also easier to catch people's eyes. Therefore, for example, it has the effect of enhancing the advertising effect.

[0432] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. Thereby, it can be used not only for advertising purposes but also for applications such as providing information required by the user, such as route information, traffic information, and guidance information for commercial facilities.

[0433] As shown in FIGS. 23C and 23D, the digital signage 7300 or the digital signage 7400 is preferably capable of communicating wirelessly with an information terminal 7311 such as a smartphone held by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, and the display of the display unit 7500 can be switched by operating the information terminal 7311.

[0434] A game can also be executed on the digital signage 7300 or the digital signage 7400 using the information terminal 7311 as an operation means (controller). Thereby, an unspecified number of users can participate in the game and enjoy it at the same time.

[0435] The display device according to one aspect of the present invention can be applied to the display unit 7500 in FIGS. 23A to 23D.

[0436] Although the electronic device of this embodiment is configured to have a display unit, one aspect of the present invention can also be applied to an electronic device that does not have a display unit.

[0437] This embodiment can be implemented by appropriately combining at least a part thereof with other embodiments described in this specification.

Example

[0438] In this example, samples (sample A1 and sample A2) corresponding to the transistor 100 shown in FIG. 1 were fabricated, and the cross-sectional shape and the drain current-drain voltage characteristics (ID-VD characteristics) of the transistor were evaluated. Here, a transistor without the conductive layer 106 was fabricated.

[0439] <Fabrication of Samples> First, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 150 nm, a third silicon nitride film with a thickness of 100 nm, and a first silicon oxynitride film with a thickness of 3 nm were formed on a glass substrate in this order.

[0440] The first silicon nitride film and the third silicon nitride film were each formed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 100 Pa, the power was 2000 W, and the substrate temperature was 350°C.

[0441] The second silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm. The pressure during film formation was 200 Pa, the power was 3000 W, and the substrate temperature was 350°C.

[0442] The first silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm. The pressure during film formation was 40 Pa, the power was 3000 W, and the substrate temperature was 350°C.

[0443] Subsequently, a first metal oxide film with a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The pressure during film formation was 0.6 Pa, the power was 2.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was 10%.

[0444] Subsequently, after heat treatment at 370 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0445] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0446] Subsequently, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 130 nm, and a fourth silicon oxynitride film with a thickness of 5 nm were formed in this order as the gate insulating layer.

[0447] The second silicon oxynitride film was formed by a PECVD method using a mixed gas of silane gas with a flow rate of 24 sccm and dinitrogen monoxide gas with a flow rate of 18000 sccm. The pressure during film formation was 200 Pa, the power was 130 W, and the substrate temperature was 350 °C. The second silicon oxynitride film corresponds to the insulating layer 110a shown in Embodiment 1.

[0448] The third silicon oxynitride film was formed by a PECVD method using a mixed gas of silane gas with a flow rate of 200 sccm and dinitrogen monoxide gas with a flow rate of 10000 sccm. The pressure during film formation was 300 Pa, the power was 750 W, and the substrate temperature was 350 °C. The third silicon oxynitride film corresponds to the insulating layer 110b shown in Embodiment 1.

[0449] The fourth silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm. The pressure during film formation was 40 Pa, the power was 500 W, and the substrate temperature was 350 °C. The fourth silicon oxynitride film corresponds to the insulating layer 110c shown in Embodiment 1.

[0450] Subsequently, heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0451] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the power was 3.5 kW, and the substrate temperature was 200 °C. Oxygen gas (oxygen flow ratio 100%) was used as the film-forming gas.

[0452] Subsequently, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0453] Subsequently, a 10-nm-thick ITSO film and a 100-nm-thick copper film were formed on the second metal oxide film in this order. The ITSO film and the copper film were formed by sputtering. The ITSO film was formed using an ITSO target (In2O3:SnO2:SiO2 = 85:10:5 [weight ratio]). The copper film was formed using a Cu target.

[0454] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. The processing used a wet etching method. As the etchant, a chemical solution prepared by mixing two chemical solutions, Chemical Solution A and Chemical Solution B, at a volume ratio of 5:1 immediately before use was used. Chemical Solution A was an aqueous solution of phosphoric acid (less than 5 wt%), hydrofluoric acid (less than 1 wt%), nitric acid (less than 10 wt%), and an additive (less than 22 wt%). Chemical Solution B was an aqueous solution of hydrogen peroxide (31 wt%). The temperature of the etchant during etching was set at 30°C.

[0455] Here, the wet etching treatment time was varied between sample A1 and sample A2, and the width L2 in the channel length direction of region 108L was varied. The wet etching treatment time for sample A1 was 110 sec, and for sample A2 it was 60 sec.

[0456] Subsequently, using the aforementioned resist mask as a mask, the second silicon oxynitride film, the third silicon oxynitride film, and the fourth silicon oxynitride film were etched to form a gate insulating layer. The processing used a dry etching method. After that, the resist mask was removed.

[0457] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a fifth silicon oxynitride film with a thickness of 300 nm were formed in this order.

[0458] The fourth silicon nitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 150 sccm, nitrogen gas with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm. The pressure during film formation was 200 Pa, the power was 2000 W, and the substrate temperature was 350°C.

[0459] The fifth silicon oxynitride film was formed by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm and dinitrogen monoxide gas with a flow rate of 4000 sccm. The pressure during film formation was 133 Pa, the power was 1000 W, and the substrate temperature was 350 °C.

[0460] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm, a copper film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were formed in this order using the sputtering method. Then, this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0461] Transistors (sample A1 and sample A2) formed on the glass substrate were obtained through the above steps.

[0462] <Cross-sectional Observation> Next, sample A1 and sample A2 were thinned by a focused ion beam (FIB), and the cross-sections of sample A1 and sample A2 were observed by STEM.

[0463] <ID-VD Characteristic Evaluation> Subsequently, the ID-VD characteristics of the transistors fabricated above were measured.

[0464] The measurement conditions for the ID-VD characteristics of the transistors were as follows: the source potential was set to the ground potential (GND), and the drain voltage (VD) was swept in the range from 0 V to 30 V at intervals of 0.25 V for measurement. ID-VD measurements were continuously performed using the same transistors under four conditions of gate voltage (VG) of 0 V, 2 V, 4 V, and 6 V. The transistors used had a channel length of 3 μm and a channel width of 10 μm, and the ID-VD characteristics of 20 transistors were measured for each sample.

[0465] The STEM image of the cross-section of sample A1 is shown in Fig. 24A. Fig. 24A is a transmission electron image (TE image) with a magnification of 80,000 times. As shown in Fig. 24A, in sample A1, the width L2 of region 108L was 583 nm. In Fig. 24A, the glass substrate is denoted as Glass, each silicon nitride film as SiN, each silicon oxynitride film as SiON, each metal oxide film as IGZO, the ITSO film as ITSO, and the copper film as Cu.

[0466] The ID-VD characteristics of sample A1 are shown in Fig. 24B. In Fig. 24B, the horizontal axis represents the drain voltage (VD), and the vertical axis represents the drain current (ID). As shown in Fig. 24B, it was confirmed that sample A1 exhibited good ID-VD characteristics under any of the conditions where the gate voltage (VG) was 2V, 4V, or 6V.

[0467] The STEM image of the cross-section of sample A2 is shown in Fig. 25A. Fig. 25A is a transmission electron image (TE image) with a magnification of 80,000 times. As shown in Fig. 25A, in sample A2, the width L2 of region 108L was 238 nm. In Fig. 25A, the glass substrate is denoted as Glass, each silicon nitride film as SiN, each silicon oxynitride film as SiON, each metal oxide film as IGZO, the ITSO film as ITSO, and the copper film as Cu.

[0468] The ID-VD characteristics of sample A2 are shown in FIG. 25B. In FIG. 25B, the horizontal axis represents the drain voltage (VD), and the vertical axis represents the drain current (ID). As shown in FIG. 25B, in sample A2, a decrease in the on-current was confirmed at gate voltages (VG) of 4V and 6V. Since no decrease in the on-current was confirmed at a gate voltage (VG) of 2V, it is presumed that the transistor deteriorated in the high drain voltage region at a gate voltage (VG) of 2V. Since no decrease in the on-current was confirmed in the aforementioned sample A1, it is considered that in sample A1, the width of region 108L was large, thereby suppressing the deterioration of the transistor at high drain voltages.

Example

[0469] In this example, samples (sample B1 to sample B5) corresponding to the transistor 100 shown in FIG. 1 were fabricated, and the drain current-drain voltage characteristics (ID-VD characteristics) of the transistors were evaluated.

[0470] <Fabrication of Samples> First, a titanium film with a thickness of 30 nm and a copper film with a thickness of 100 nm were formed on a glass substrate in this order by sputtering, and this was processed to obtain a first gate electrode (bottom gate).

[0471] Next, as the first gate insulating layer, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 150 nm, a third silicon nitride film with a thickness of 100 nm, and a first silicon oxynitride film with a thickness of 3 nm were formed in this order. Since the descriptions of the first silicon nitride film to the third silicon nitride film and the first silicon oxynitride film can be referred to in Example 1, detailed descriptions are omitted.

[0472] Subsequently, a first metal oxide film with a thickness of 25 nm was formed on the first silicon oxynitride film. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The pressure during film formation was 0.3 Pa, the power was 4.5 kW, and the substrate temperature was room temperature. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was 10%.

[0473] Subsequently, after heat treatment at 370 °C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0474] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0475] Subsequently, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 130 nm, and a fourth silicon oxynitride film with a thickness of 5 nm were formed in this order as a gate insulating layer. Since the description of Example 1 can be referred to for the second to fourth silicon oxynitride films, detailed explanations are omitted.

[0476] Subsequently, heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0477] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The pressure during film formation was 0.8 Pa, the power was 3.5 kW, and the substrate temperature was 200 °C. Oxygen gas (oxygen flow ratio 100%) was used as the film-forming gas.

[0478] Subsequently, heat treatment was performed at 370 °C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 4:1). An oven device was used for the heat treatment.

[0479] Subsequently, a 10-nm-thick ITSO film and a 100-nm-thick copper film were formed in this order on the second metal oxide film. The ITSO film and the copper film were formed by sputtering. The ITSO film was formed using an ITSO target (In2O3:SnO2:SiO2 = 85:10:5 [weight ratio]). The copper film was formed using a Cu target.

[0480] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. The processing used the wet etching method. Since the description of Example 1 can be referred to for the etchant used, detailed description is omitted.

[0481] Here, the wet etching treatment time was varied for each of sample B1 to sample B5, and the width L2 in the channel length direction of region 108L was varied. For sample B1, the wet etching treatment time was 60 sec, for sample B2 it was 75 sec, for sample B3 it was 90 sec, for sample B4 it was 105 sec, and for sample B5 it was 120 sec.

[0482] Subsequently, using the aforementioned resist mask as a mask, the second silicon oxynitride film was etched to form a second gate insulating layer. The processing used the dry etching method. After this, the resist mask was removed.

[0483] Subsequently, as a protective layer covering the transistor, a 100-nm-thick fourth silicon nitride film and a 300-nm-thick fifth silicon oxynitride film were formed in this order. Since the description of Example 1 can be referred to for the fourth silicon nitride film and the fifth silicon oxynitride film, detailed description is omitted.

[0484] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm, a copper film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were formed in this order by sputtering method. Then, this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a temperature of 250 °C for 1 hour in a nitrogen atmosphere.

[0485] Transistors (sample B1 to sample B5) formed on the glass substrate were obtained through the above steps.

[0486] <ID-VD Characteristic Evaluation> Subsequently, the ID-VD characteristics of the transistors fabricated above were measured.

[0487] The measurement conditions for the ID-VD characteristics of the transistors were as follows: the source potential was set to the ground potential (GND), and the drain voltage (VD) was swept from 0 V to 30 V at intervals of 0.25 V for measurement. The ID-VD measurements were continuously performed using the same transistor under four conditions of gate voltage (VG) of 0 V, 2 V, 4 V, and 6 V. The transistors had a channel length of 3 μm and a channel width of 10 μm.

[0488] The ID-VD characteristics of sample B1 to sample B5 are shown in FIGS. 26, 27, and 28. In FIGS. 26, 27, and 28, the horizontal axis represents the drain voltage (VD), and the vertical axis represents the drain current (ID), respectively.

[0489] Figure 26 shows the results of sample B1 and sample B2 horizontally. Figure 27 shows the results of sample B3 and sample B4 horizontally. Figure 28 shows the result of sample B5. Note that for sample B1, the width L2 was approximately 200 nm, the channel length was 2.86 μm, and the channel width was 10 μm. For sample B2, the width L2 was approximately 300 nm, the channel length was 2.63 μm, and the channel width was 10 μm. For sample B3, the width L2 was approximately 400 nm, the channel length was 2.5 μm, and the channel width was 10 μm. For sample B4, the width L2 was approximately 500 nm, the channel length was 3.32 μm, and the channel width was 10 μm. For sample B5, the width L2 was approximately 600 nm, the channel length was 3.06 μm, and the channel width was 10 μm.

[0490] In FIGS. 26 to 28, different conditions of the transistor structure are shown vertically. What is marked as Single Gate shows the result of performing ID-VD measurement by applying a gate voltage (VG) to the conductive layer 112 in a transistor having no conductive layer 106. What is marked as Source Sync. shows the result of performing ID-VD measurement by applying a gate voltage (VG) to the conductive layer 112 (top gate electrode) in a state where the conductive layer 106 (bottom gate electrode) and the source electrode (GND) are electrically connected in a transistor having the conductive layer 106. What is marked as Top Gate Sync. shows the result of performing ID-VD measurement by applying a gate voltage (VG) to the conductive layer 112 (top gate electrode) in a state where the conductive layer 106 (bottom gate electrode) and the conductive layer 112 (top gate electrode) are electrically connected in a transistor having the conductive layer 106.

[0491] As shown in FIGS. 26 to 28, in the Single Gate, a decrease in the on-current was confirmed when the width L2 was about 200 nm, but no decrease in the on-current was confirmed when the width L2 was about 300 nm or more, and good ID-VD characteristics were shown. In Source Sync. and Top Gate Sync., a decrease in the on-current was confirmed when the width L2 was about 200 nm, about 300 nm, and about 400 nm, but no decrease in the on-current was confirmed when the width L2 was about 500 nm or more, and good ID-VD characteristics were shown. In any transistor structure, it was confirmed that an increase in the width L2 could suppress a decrease in the on-current when a high drain voltage was applied.

[0492] The second metal oxide film, the ITSO film, and the copper film described above were processed, and the relationship between the wet etching treatment time and the width L2 during the formation of the second metal oxide layer, the ITSO layer, and the copper layer is shown in FIG. 29. In FIG. 29, the horizontal axis represents the wet etching treatment time (Wet-etching Time), and the vertical axis represents the width L2. Also, in FIG. 29, the black filled circles represent the average value within the substrate surface, and the error bars represent the maximum and minimum values within the substrate surface. Samples with wet etching treatment times of 60 sec, 75 sec, and 105 sec were measured at four locations within the substrate surface, and samples with wet etching treatment times of 90 sec and 120 sec were measured at one location within the substrate surface. As shown in FIG. 29, the wet etching treatment time and the width L2 are almost linearly related, and it was found that the width L2 can be accurately controlled by the wet etching treatment time.

Example

[0493] In this example, samples in which a metal oxide film was formed on an insulating film were prepared, and the desorption amounts of oxygen and nitrogen monoxide from the insulating film and the spin density of the insulating film were evaluated. A plurality of samples (sample C1 to sample C4, sample D1 to sample D4, sample E1 to sample E4, sample F1 to sample F4) were prepared with different film formation conditions for the insulating film and the metal oxide film.

[0494] <Preparation of Samples> First, an insulating film was formed on a substrate.

[0495] As the substrates, glass substrates were used for samples C1 to C4 and samples D1 to D4. Quartz substrates were used for samples E1 to E4 and samples F1 to F4.

[0496] As the insulating film, for samples C1 to C4 and samples E1 to E4, a silicon oxynitride film with a thickness of about 140 nm was formed by plasma CVD. For the formation of the silicon oxynitride film, the flow rates of silane gas and dinitrogen monoxide gas were set to 160 sccm and 4000 sccm respectively, the pressure was 200 Pa, the power was 1500 W, and the substrate temperature was 220 °C.

[0497] As the insulating film, for samples D1 to D4 and samples F1 to F4, a first silicon oxynitride film with a thickness of about 5 nm, a second silicon oxynitride film with a thickness of about 130 nm, and a third silicon oxynitride film with a thickness of about 5 nm were each formed by plasma CVD. For the formation of the first silicon oxynitride film, the flow rates of silane gas and dinitrogen monoxide gas were set to 24 sccm and 18000 sccm respectively, the pressure during film formation was 200 Pa, the power was 130 W, and the substrate temperature was 350 °C. For the formation of the second silicon oxynitride film, the flow rates of silane gas and dinitrogen monoxide gas were set to 200 sccm and 4000 sccm respectively, the pressure during film formation was 300 Pa, the power was 750 W, and the substrate temperature was 350 °C. For the formation of the third silicon oxynitride film, the flow rates of silane gas and dinitrogen monoxide gas were set to 20 sccm and 3000 sccm respectively, the pressure during film formation was 40 Pa, the power was 500 W, and the substrate temperature was 350 °C.

[0498] Subsequently, a heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere.

[0499] Subsequently, a metal oxide film with a thickness of approximately 20 nm was formed on the insulating film by sputtering. The metal oxide film was formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 4:2:3 [atomic ratio]. A mixed gas of argon gas and oxygen gas was used as the film-forming gas.

[0500] For sample C2, sample D2, sample E2, and sample F2, the ratio of the flow rate of oxygen gas to the total flow rate of the film-forming gas (oxygen flow ratio) was set to 50%. For sample C3, sample D3, sample E3, and sample F3, the oxygen flow ratio was set to 70%. For sample C4, sample D4, sample E4, and sample F4, the oxygen flow ratio was set to 100%.

[0501] For sample C1, sample D1, sample E1, and sample F1, no metal oxide film was formed.

[0502] Subsequently, each sample was heat-treated at 370 °C for 1 hour in a mixed atmosphere of oxygen gas and nitrogen gas.

[0503] Thereafter, for sample C2 to sample C4, sample D2 to sample D4, sample E2 to sample E4, and sample F2 to sample F4, the metal oxide film was removed by wet etching.

[0504] Through the above steps, sample C1 to sample C4, sample D1 to sample D4, sample E1 to sample E4, and sample F1 to sample F4 were fabricated.

[0505] <TDS analysis> For the above-mentioned samples C1 to C4 and samples D1 to D4, temperature-programmed desorption gas (TDS: Thermal Desorption Spectroscopy) analysis was performed respectively. The TDS analysis was carried out at a heating rate such that the stage temperature was 30 °C / min.

[0506] Figures 30A and 30B show the TDS analysis results. Figure 30A shows the emission amount of the gas with a mass-to-charge ratio (M / z) = 32 corresponding to oxygen molecules, and Figure 30B shows the emission amount of the gas with a mass-to-charge ratio (M / z) = 30 corresponding to nitric oxide molecules. In Figures 30A and 30B, the horizontal axis represents the oxygen flow ratio (O2ratio) during the formation of the metal oxide film, and the vertical axis represents the emission amount (desorption) of the gas. Also, in Figures 30A and 30B, the black-filled square marks indicate the condition where the substrate temperature during the formation of the insulating film is 220 °C, and the black-filled triangle marks indicate the condition where the substrate temperature during the formation of the insulating film is 350 °C. Note that samples C1 and D1 on which the metal oxide film was not formed are indicated as "none" on the horizontal axis of Figures 30A and 30B.

[0507] As shown in Figure 30A, it was found that by forming a metal oxide film on the insulating film, the emission amount of oxygen molecules from the insulating film increased, and oxygen was supplied to the insulating film by the formation of the metal oxide film. Also, it was confirmed that the higher the oxygen flow ratio during the formation of the metal oxide film, the greater the emission amount of oxygen molecules from the insulating film. There was no difference in the oxygen emission amount due to the substrate temperature during the formation of the insulating film.

[0508] As shown in FIG. 30B, by forming a metal oxide film on the insulating film, it was suggested that the emission amount of nitrogen monoxide molecules from the insulating film increased, and nitrogen oxides were formed in the insulating film by the formation of the metal oxide film. It was confirmed that the emission amount of nitrogen monoxide molecules was smaller under the condition of 350 ° C. than under the condition of 220 ° C. for the substrate temperature during the formation of the insulating film. Further, under the condition of 350 ° C. for the substrate temperature during the formation of the insulating film, the emission amount of nitrogen monoxide molecules from the insulating film decreased as the oxygen flow rate ratio during the formation of the metal oxide film increased. Under the condition of 220 ° C. for the substrate temperature during the formation of the insulating film, the emission amount of nitrogen monoxide molecules tended to increase under the condition of 70% rather than 50% for the oxygen flow rate ratio during the formation of the metal oxide film.

[0509] <ESR analysis> For the above samples E1 to E4 and samples F1 to F4, electron spin resonance (ESR) analysis was performed respectively. For the ESR analysis, the measurement temperature was set to 85K, the high-frequency power (microwave power) at 9.2 GHz was set to 10 mW, and the direction of the magnetic field was parallel to the film surface of the sample. The detection limit was 3.5×10 17 spins / cm 3 was.

[0510] Figure 30C shows the ESR analysis results. Figure 30C shows the spin density of the signal caused by nitrogen dioxide (NO2). Note that the signal caused by nitrogen dioxide (NO2) is split into three signals by the nuclear spin of nitrogen, and the g-values of the three signals are observed to be around 2.04, around 2.00, and around 1.96, respectively. In Figure 30C, the horizontal axis represents the oxygen flow ratio (O2ratio) during the formation of the metal oxide film, and the vertical axis represents the spin density. Also, in Figure 30C, the black-filled square marks indicate the condition where the substrate temperature during the formation of the insulating film is 220 °C, and the black-filled triangle marks indicate the condition where the substrate temperature during the formation of the insulating film is 350 °C. The spin density indicates the number of spins per unit volume of the insulating film, and is calculated by dividing the number of spins obtained by the ESR analysis by the volume of the insulating film used in the ESR analysis. Note that sample E1 and sample F1 on which the metal oxide film was not formed are indicated as "none" on the horizontal axis of Figure 30C.

[0511] As shown in Figure 30C, by forming a metal oxide film on the insulating film, the spin density of the insulating film caused by nitrogen dioxide (NO2) increased. It was confirmed that the spin density caused by nitrogen dioxide (NO2) was lower under the condition of 350 °C compared to the condition where the substrate temperature during the formation of the insulating film was 220 °C. Also, under the condition where the substrate temperature during the formation of the insulating film was 350 °C, the spin density caused by nitrogen dioxide (NO2) decreased as the oxygen flow ratio during the formation of the metal oxide film increased.

Description of symbols

[0512] C1: Capacity, C2: Capacity, DL_n: Data line, DL_Y: Data line, DL_1: Data line, EL: Light-emitting element, G1: Wiring, G2: Wiring, GL_m: Scanning line, GL_X: Scanning line, GL_1: Scanning line, LC: Liquid crystal element, M1: Transistor, M2: Transistor, M3: Transistor, N1: Node, N2: Node, P: Region, P1: Region, P2: Region, Q: Region, R: Region, S1: Wiring, S2: Wiring, T1: Period, T2: Period, 100: Transistor, 100A: Transistor, 100B: Transistor, 102: Substrate, 103: Insulating layer, 103a: Insulating layer, 103b: Insulating layer, 106: Conductive layer, 108: Semiconductor layer, 108L: Region, 108N: Region, 110: Insulating layer, 110a: Insulating layer, 110b: Insulating layer, 110c: Insulating layer, 110f: Insulating film, 112: Conductive layer, 112f: Conductive film, 113: Functional layer, 113f: Functional film, 114: Metal oxide layer, 114f: Metal oxide film, 115: Resist mask, 116: Insulating layer, 118: Insulating layer, 120a: Conductive layer, 120b: Conductive layer, 141a: Opening, 141b: Opening, 142: Opening, 400: Pixel circuit, 400EL: Pixel circuit, 400LC: Pixel circuit, 401: Circuit, 401EL: Circuit, 401LC: Circuit, 501: Pixel circuit, 502: Pixel portion, 504: Driving circuit portion, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal portion, 550: Transistor, 552: Transistor, 554: Transistor, 560: Capacitor element, 562: Capacitor element, 570: Liquid crystal element, 572: Light-emitting element, 700: Display device, 700A: Display device, 700B: Display device, 701: First substrate, 702: Pixel portion, 704: Source driver circuit portion, 705: Second substrate, 706: Gate driver circuit portion, 708: FPC terminal portion, 710: Signal line, 711: Wiring portion, 712: Sealant, 716: FPC, 717: IC, 721: Source driver IC, 722: Gate driver circuit portion, 723: FPC, 724: Printed circuit board, 730: Insulating film, 732: Encapsulation film, 734: Insulating film, 736: Coloring film, 738: Light-shielding film, 740: Protection layer, 741: Protection layer, 742: Adhesive layer, 743: Resin layer, 744: Insulating layer, 745: Support substrate, 746: Resin layer, 750: Transistor, 752: Transistor, 760: Wiring, 770: Planarization insulating film, 772: Conductive layer, 773: Insulating layer,774: Conductive layer, 775: Liquid crystal element, 776: Liquid crystal layer, 778: Spacer, 780: Anisotropic conductive film, 782: Light-emitting element, 786: EL layer, 788: Conductive film, 790: Capacitive element, 6000: Display module, 6001: Upper cover, 6002: Lower cover, 6005: FPC, 6006: Display device, 6009: Frame, 6010: Printed circuit board, 6011: Battery, 6015: Light-emitting part, 6016: Light-receiving part, 6017a: Light guide part, 6017b: Light guide part, 6018: Light, 6500: Electronic device, 6501: Housing, 6502: Display part, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protection member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 7100: Television device, 7101: Housing, 7103: Stand, 7111: Remote control operation unit, 7200: Notebook personal computer, 7211: Housing, 7212: Keyboard, 7213: Pointing device, 7214: External connection port, 7300: Digital signage, 7301: Housing, 7303: Speaker, 7311: Information terminal device, 7400: Digital signage, 7401: Column, 7500: Display part, 8000: Camera, 8001: Housing, 8002: Display part, 8003: Operation button, 8004: Shutter button, 8006: Lens, 8100: Finder, 8101: Housing, 8102: Display part, 8103: Button, 8200: Head-mounted display, 8201: Mounting part, 8202: Lens, 8203: Main body, 8204: Display part, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302: Display part, 8304: Fixture, 8305: Lens, 9000: Housing, 9001: Display part, 9003: Speaker, 9005: Operation key, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9100: Television device, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

1. A semiconductor device comprising a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer, wherein the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order on the semiconductor layer, the first insulating layer has a stacked structure in which a first layer, a second layer, and a third layer are stacked in this order, in a cross-section in the channel length direction, an end portion of the first insulating layer is located inside an end portion of the semiconductor layer, in a cross-section in the channel length direction, an end portion of the metal oxide layer is located inside an end portion of the first insulating layer, in a cross-section in the channel length direction, an end portion of the conductive layer is located inside an end portion of the metal oxide layer, the second insulating layer is provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer, the semiconductor layer contains indium and oxygen, a film density of the second layer is lower than film densities of the first layer and the third layer, and a hydrogen concentration of the second layer measured by secondary ion mass spectrometry is higher than hydrogen concentrations of the first layer and the third layer measured by secondary ion mass spectrometry.

2. A semiconductor device comprising a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer, wherein the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order on the semiconductor layer, the first insulating layer has a stacked structure in which a first layer, a second layer, and a third layer are stacked in this order, in a cross-section in the channel length direction, an end portion of the first insulating layer is located inside an end portion of the semiconductor layer, in a cross-section in the channel length direction, an end portion of the metal oxide layer is located inside an end portion of the first insulating layer, in a cross-section in the channel length direction, an end portion of the conductive layer is located inside an end portion of the metal oxide layer, the second insulating layer is provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer, the semiconductor layer has a first region, a pair of second regions, and a pair of third regions, the first region overlaps with the first insulating layer and the metal oxide layer, the second regions sandwich the first region, overlap with the first insulating layer, and do not overlap with the metal oxide layer, the third regions sandwich the first region and the pair of second regions and do not overlap with the first insulating layer, and the third regions are provided in contact with the second insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region. The semiconductor layer contains indium and oxygen. The film density of the second layer is lower than the film densities of the first layer and the third layer. A semiconductor device in which the hydrogen concentration of the second layer measured by secondary ion mass spectrometry is higher than the hydrogen concentrations of the first layer and the third layer measured by secondary ion mass spectrometry.

3. In claim 1 or claim 2, A semiconductor device in which the second insulating layer is a silicon nitride film.

4. In any one of claims 1 to 3, The end portions of the first insulating layer and the end portions of the metal oxide layer each have a tapered shape, A semiconductor device in which the end portion of the metal oxide layer has a taper angle smaller than the taper angle of the end portion of the first insulating layer.

5. In any one of claims 1 to 4, A semiconductor device in which the semiconductor layer further contains gallium and zinc.

Images