Memory device

Abstract

To provide a storage device with large memory capacity.SOLUTION: A NAND-type storage device has a plurality of memory cells connected together, each comprising a write transistor, a read transistor, and capacity. An oxide semiconductor is used for a semiconductor layer of the writing transistor. The read transistor includes a back gate. The information held by the memory cells is read by applying a voltage for reading to the back gate.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a memory device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] In this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, a display device, a light-emitting device, a lighting device, an electro-optical device, an imaging device, a memory device, a communication device, and an electronic device may include semiconductor elements or semiconductor circuits. Therefore, a display device, a light-emitting device, a lighting device, an electro-optical device, an imaging device, a memory device, a communication device, and an electronic device may also be referred to as a semiconductor device.

Background Art

[0004] In recent years, transistors using an oxide semiconductor or a metal oxide in a channel formation region (Oxide Semiconductor transistor, hereinafter also referred to as "OS transistor" or "OS-FET") have attracted attention (Patent Document 1).

[0005] The off-current (the current flowing between the source and the drain when the transistor is in the off state) of an OS transistor is very small. Non-volatile memories utilizing this feature are disclosed in Patent Document 2 and Patent Document 3. The non-volatile memory using an OS transistor has no limit on the number of times of data rewriting, and further has low power consumption when rewriting data. In addition, Patent Document 3 discloses an example in which a memory cell of a non-volatile memory is constituted only by OS transistors.

[0006] In this specification, the non-volatile memory using an OS transistor may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation of "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having a gain cell type (2T type, 3T type) memory cell.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention aims to provide a highly reliable memory device. Or, one aspect of the present invention aims to provide a memory device with a large storage capacity. Or, one aspect of the present invention aims to provide a memory device with a small occupied area. Or, one aspect of the present invention aims to provide a memory device with a low manufacturing cost. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device with a low manufacturing cost. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0009] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention does not necessarily need to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention is a NAND-type storage device in which a plurality of memory cells each including a writing transistor and a reading transistor are connected. By using an oxide semiconductor for the semiconductor layer of the writing transistor, the holding capacitance can be made unnecessary or reduced in size. The reading transistor includes a back gate. By applying a reading voltage to the back gate, the information held in the memory cell can be read out.

[0011] One aspect of the present invention includes n memory cells (where n is an integer of 3 or more), n first wirings, n second wirings, and a third wiring. The i-th memory cell (where i is an integer greater than or equal to 2 and less than n) includes a first transistor [i], a second transistor [i], and a capacitor [i]. The (i - 1)-th memory cell includes a first transistor [i - 1], a second transistor [i - 1], and a capacitor [i - 1]. The (i + 1)-th memory cell includes a first transistor [i + 1], a second transistor [i + 1], and a capacitor [i + 1]. The gate of the first transistor [i] is electrically connected to the i-th first wiring. The source of the first transistor [i] is electrically connected to the drain of the first transistor [i - 1]. The drain of the first transistor [i] is electrically connected to the source of the first transistor [i + 1]. The gate of the second transistor [i] is electrically connected to the drain of the first transistor [i]. The source of the second transistor [i] is electrically connected to the drain of the second transistor [i - 1]. The drain of the second transistor [i] is electrically connected to the source of the second transistor [i + 1]. The back gate of the second transistor [i] is electrically connected to the i-th second wiring. The back gate of the second transistor [i - 1] is electrically connected to the (i - 1)-th second wiring. The back gate of the second transistor [i + 1] is electrically connected to the (i + 1)-th second wiring. A capacitor [i] is provided between the gate of the second transistor [i] and the third wiring. A capacitor [i - 1] is provided between the gate of the second transistor [i - 1] and the third wiring. A capacitor [i + 1] is provided between the gate of the second transistor [i + 1] and the third wiring. It is a storage device.

[0012] The first transistor [i] preferably includes an oxide semiconductor in the semiconductor layer. The second transistor [i] preferably includes an oxide semiconductor in the semiconductor layer. The oxide semiconductor preferably includes at least one of indium or zinc.

Effects of the Invention

[0013] According to one aspect of the present invention, a highly reliable memory device can be provided. Or, according to one aspect of the present invention, a memory device with a large storage capacity can be provided. Or, according to one aspect of the present invention, a memory device with a small occupied area can be provided. Or, according to one aspect of the present invention, a memory device with a low manufacturing cost can be provided. Or, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Or, according to one aspect of the present invention, a semiconductor device with a low manufacturing cost can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0014] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.

Brief Description of Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Best Mode for Carrying Out the Invention

[0016] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having the same functions are commonly used with the same reference numerals among different drawings, and the repeated description thereof will be omitted.

[0017] In addition, the position, size, range, etc. of each component shown in the drawings and the like may not represent the actual position, size, range, etc. in order to facilitate the understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but it may not be reflected in the drawing for the sake of easy understanding.

[0018] In addition, in a top view (also referred to as a "plan view") or a perspective view, etc., for the sake of easy understanding of the drawing, the description of some components may be omitted.

[0019] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as a part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0020] In addition, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0021] In addition, in this specification and the like, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly on insulating layer A in contact therewith, and those including other components between insulating layer A and electrode B are not excluded.

[0022] Also, since the functions of the source and the drain are interchangeable depending on operating conditions such as when transistors of different polarities are employed or when the direction of current changes in circuit operation, it is difficult to limit which is the source or the drain. Therefore, in this specification, the terms source and drain can be used interchangeably. Thus, for the purpose of facilitating the understanding of the description according to one aspect of the present invention, in this specification and the like, one of the source or the drain may be referred to as the "source", and the other of the source or the drain may be referred to as the "drain".

[0023] In addition, in this specification and the like, "electrically connected" includes both the case of direct connection and the case of connection via "something having some electrical action". Here, the "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends.

[0024] In addition, in this specification and the like, "parallel" means, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" mean, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0025] In addition, in this specification and the like, when referring to count values and measured values as "identical", "the same", "equal", or "uniform", etc., unless otherwise specified, it shall include an error of plus or minus 20%.

[0026] Also, voltage often indicates the potential difference between a certain potential and a reference potential (such as ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be used interchangeably.

[0027] Note that even when denoted as "semiconductor", for example, when the conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to use "semiconductor" by replacing it with "insulator". In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be able to be read interchangeably with each other.

[0028] Also, even when denoted as "semiconductor", for example, when the conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to use "semiconductor" by replacing it with "conductor". In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be able to be read interchangeably with each other.

[0029] In addition, ordinal numbers such as "first", "second", etc. in this specification and the like are attached to avoid confusion of components, and do not indicate any order or ranking such as process order or stacking order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be attached in the claims to avoid confusion of components. Also, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be attached in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0030] In addition, in this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically short-circuited (also referred to as the "conducting state"). Also, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be regarded as being electrically disconnected (also referred to as the "non-conducting state").

[0031] In addition, in this specification and the like, the "on-current" may refer to the current flowing between the source and drain when the transistor is in the on state. Also, the "off-current" may refer to the current flowing between the source and drain when the transistor is in the off state.

[0032] In addition, in this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as "VDD", "H potential", or "H") indicates a power supply potential having a potential higher than the low power supply potential VSS (hereinafter, also simply referred to as "VSS", "L potential", or "L"). Also, VSS indicates a power supply potential having a potential lower than VDD. Also, the ground potential (hereinafter, also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0033] In addition, the transistors shown in this specification and the like are, unless otherwise specified, enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, its threshold voltage (also referred to as "Vth") is greater than 0V. Also, unless otherwise specified, "supplying an H potential to the gate of the transistor" may be synonymous with "turning on the transistor". Also, unless otherwise specified, "supplying an L potential to the gate of the transistor" may be synonymous with "turning off the transistor".

[0034] In addition, in this specification and the like, the gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0035] In addition, in this specification and the like, the source refers to a part or all of the source region, the source electrode, and the source wiring. The source region refers to the region in the semiconductor layer where the resistivity is equal to or less than a certain value. The source electrode refers to the conductive layer connected to the source region. The source wiring refers to the wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0036] In addition, in this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to the region in the semiconductor layer where the resistivity is equal to or less than a certain value. The drain electrode refers to the conductive layer connected to the drain region. The drain wiring refers to the wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0037] In addition, in the drawings and the like, in order to make the potential of the wiring and the electrode easier to understand, "H" indicating the H potential or "L" indicating the L potential may be added adjacent to the wiring and the electrode. In addition, for the wiring and the electrode where a potential change has occurred, "H" or "L" may be added in enclosed characters. In addition, when the transistor is in the off state, an "×" symbol may be added over the transistor.

[0038] In general, a "capacitor" has a structure in which two electrodes face each other with an insulator (dielectric) in between. In this specification and the like, the "capacitor element" includes the case where it is the aforementioned "capacitor". That is, in this specification and the like, the "capacitor element" means one having a structure in which two electrodes face each other with an insulator in between, one having a structure in which two wirings face each other with an insulator in between, or one in which two wirings are arranged with an insulator in between.

[0039] Also, in this specification and the like, when the same reference numeral is used for a plurality of elements, when it is particularly necessary to distinguish them, identification symbols such as "_1", "_2", "[n]", "[m,n]" may be attached to the reference numeral for description. For example, the second wiring GL may be described as wiring GL[2].

[0040] (Embodiment 1) FIG. 1A shows a circuit diagram of a memory device 100 according to an aspect of the present invention. The memory device 100 has a configuration including a plurality of memory cells 110 between a transistor 131 and a transistor 132.

[0041] In this embodiment and the like, the first memory cell 110 is denoted as memory cell 110[1], and the nth memory cell 110 (n is an integer of 3 or more) is denoted as memory cell 110[n]. Also, the ith memory cell 110 (i is an integer greater than or equal to 2 and less than n) is denoted as memory cell 110[i]. When explaining matters common to memory cells 110[1] to memory cells 110[n], it may be simply denoted as "memory cell 110".

[0042] The memory cell 110 has a transistor 111, a transistor 112, and a capacitor 113. In this embodiment and the like, the transistor 111, the transistor 112, and the capacitor 113 included in the ith memory cell 110 are denoted as transistor 111[i], transistor 112[i], and capacitor 113[i].

[0043] <Configuration example of memory device> A circuit configuration example of the memory device 100 shown in FIG. 1A will be described in detail. The gate of the transistor 111[1] included in the memory cell 110[1] is electrically connected to the terminal 121[1]. One of the source or drain of the transistor 111[1] is electrically connected to the terminal 137, and the other is electrically connected to one electrode of the capacitor 113[1]. The other electrode of the capacitor 113[1] is electrically connected to the terminal 123[1].

[0044] The gate of the transistor 112[1] is electrically connected to the other of the source or drain of the transistor 111[1]. One of the source or drain of the transistor 112[1] is electrically connected to the transistor 131. The other of the source or drain of the transistor 112[1] is electrically connected to one of the source or drain of the transistor 112[2]. The back gate of the transistor 112[1] is electrically connected to the terminal 122[1].

[0045] The node where the other of the source or drain of the transistor 111[1], one electrode of the capacitor 113[1], and the gate of the transistor 112[1] are electrically connected is called node ND[1].

[0046] Also, one of the source or drain of the transistor 131 is electrically connected to the terminal 138, and the other is electrically connected to one of the source or drain of the transistor 112[1]. The gate of the transistor 131 is electrically connected to the terminal 133.

[0047] The gate of the transistor 111[2] included in the memory cell 110[2] is electrically connected to the terminal 121[2]. One of the source or drain of the transistor 111[2] is electrically connected to the node ND[1], and the other is electrically connected to one electrode of the capacitor 113[2]. The other electrode of the capacitor 113[2] is electrically connected to the terminal 123[2].

[0048] The gate of transistor 112[2] is electrically connected to the other of the source or drain of transistor 111[2]. One of the source or drain of transistor 112[2] is electrically connected to the other of the source or drain of transistor 112[1]. The other of the source or drain of transistor 112[2] is electrically connected to one of the source or drain of transistor 112[3] (not shown). The back gate of transistor 112[2] is electrically connected to terminal 122[2].

[0049] The node where the other of the source or drain of transistor 111[2], one electrode of capacitor 113[2], and the gate of transistor 112[2] are electrically connected is called node ND[2].

[0050] The gate of transistor 111[i] included in memory cell 110[i] is electrically connected to terminal 121[i]. One of the source or drain of transistor 111[i] is electrically connected to node ND[i - 1] (not shown), and the other is electrically connected to one electrode of capacitor 113[i]. The other electrode of capacitor 113[i] is electrically connected to terminal 123[i].

[0051] The gate of transistor 112[i] is electrically connected to the other of the source or drain of transistor 111[i]. One of the source or drain of transistor 112[i] is electrically connected to the other of the source or drain of transistor 112[i - 1]. The other of the source or drain of transistor 112[i] is electrically connected to one of the source or drain of transistor 112[i + 1] (not shown). The back gate of transistor 112[i] is electrically connected to terminal 122[i].

[0052] The node where the other of the source or drain of transistor 111[i], one electrode of capacitor 113[i], and the gate of transistor 112[i] are electrically connected is called node ND[i].

[0053] The gate of transistor 111[n] included in memory cell 110[n] is electrically connected to terminal 121[n]. One of the source or drain of transistor 111[n] is electrically connected to node ND[n - 1] (not shown), and the other is electrically connected to one electrode of capacitor 113[n]. The other electrode of capacitor 113[n] is electrically connected to terminal 123[n].

[0054] The gate of transistor 112[n] is electrically connected to the other of the source or drain of transistor 111[n]. One of the source or drain of transistor 112[n] is electrically connected to the other of the source or drain of transistor 112[n - 1] (not shown). The other of the source or drain of transistor 112[n] is electrically connected to transistor 132. The back gate of transistor 112[n] is electrically connected to terminal 122[n].

[0055] The node where the other of the source or drain of transistor 111[n], one electrode of capacitor 113[n], and the gate of transistor 112[n] are electrically connected is referred to as node ND[n].

[0056] Also, one of the source or drain of transistor 132 is electrically connected to the other of the source or drain of transistor 112[n]. The other of the source or drain of transistor 132 is electrically connected to terminal 139. The gate of transistor 132 is electrically connected to terminal 134.

[0057] The memory device 100 shown in FIG. 1A has n memory cells 110 between transistor 131 and transistor 132, and transistors 111[1] to 111[n] are connected in series while sharing (electrically connecting) the source of one transistor and the drain of the other transistor between adjacent transistors. Also, transistors 112[1] to 112[n] are connected in series while sharing (electrically connecting) the source and drain between adjacent transistors.

[0058] More specifically, the source of transistor 111[i] is electrically connected to the drain of transistor 111[i - 1], and the drain of transistor 111[i] is electrically connected to the source of transistor 111[i + 1]. Also, the source of transistor 112[i] is electrically connected to the drain of transistor 112[i - 1], and the drain of transistor 112[i] is electrically connected to the source of transistor 112[i + 1].

[0059] Also, in this specification and the like, when the gate of a transistor is called the first terminal, one of the source or drain is called the second terminal, the other of the source or drain is called the third terminal, and the back gate is called the fourth terminal. For example, it can be said that the second terminal of transistor 111[i] is electrically connected to the third terminal of transistor 111[i - 1], the third terminal of transistor 111[i] is electrically connected to the second terminal of transistor 111[i + 1], and the third terminal of transistor 111[i] is electrically connected to the first terminal of transistor 112[i].

[0060] In this way, a structure in which the transistors included in one memory cell 110 are connected in series with the transistors included in adjacent memory cells 110, and a plurality of memory cells 110 are connected in a row, may be called a "string", "cell string", or "memory cell string". For example, one storage device 100 having a string structure may be called "one string", or simply "string". Note that "string", "cell string", and "memory cell string" may also be used as units of reference.

[0061] 〔Memory Cell〕 The memory cell 110 has a function of holding the potential (charge) written to the node ND. Specifically, a voltage that turns on the transistor 111 is supplied to the gate of the transistor 111, and charge for setting the node ND to a predetermined voltage is supplied to the node ND via the source and drain of the transistor 111. Thereafter, a voltage that turns off the transistor 111 is supplied to the gate of the transistor 111. By turning off the transistor 111, the charge written to the node ND can be held.

[0062] The semiconductor layers of the transistor 111 and the transistor 112 can be used singly or in combination, such as single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, for example, silicon, germanium, etc. can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductor, nitride semiconductor, etc. may be used. The semiconductor layers of the transistor 131 and the transistor 132 can also use the same semiconductor materials.

[0063] Note that the semiconductor layers used for the transistor may be laminated. When laminating the semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.

[0064] In particular, the transistor 111 is preferably an OS transistor. Since the oxide semiconductor has a band gap of 2 eV or more, the off-current is extremely small. When an OS transistor is used for the transistor 111, the charge written to the node ND can be held for a long period. When an OS transistor is used for the transistor 111, the memory cell 110 can be called an "OS memory".

[0065] The OS memory can hold the information written for a period of 1 year or more, and even 10 years or more, even when the power supply is stopped. Therefore, the OS memory can also be regarded as a non-volatile memory.

[0066] In addition, since the charge amount written in the OS memory hardly changes over a long period of time, the OS memory can hold multi-valued (multi-bit) information, not limited to binary (1 bit).

[0067] In addition, since the OS memory writes charges to the node via the OS transistor, the high voltage required in the conventional flash memory is unnecessary, and a high-speed write operation can also be realized. Also, the erasure operation before data rewriting performed in the flash memory is unnecessary in the OS memory. Further, since charge injection and extraction into / from the floating gate or charge trapping layer are not performed, the OS memory can perform data writing and reading substantially an unlimited number of times. The OS memory has less degradation and higher reliability compared to the conventional flash memory.

[0068] In addition, the OS memory does not involve a structural change at the atomic level like the magnetic resistance memory (MRAM) or the resistive change memory (ReRAM). Therefore, the OS memory has better rewrite resistance than the magnetic resistance memory and the resistive change memory.

[0069] Also, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environmental temperature range from room temperature to 200°C. Also, the on-current is less likely to decrease even in a high-temperature environment. The storage device including the OS memory operates stably even in a high-temperature environment and has high reliability. In addition, the OS transistor has a high breakdown voltage between the source and the drain. By using the OS transistor for the transistors constituting the semiconductor device, a semiconductor device that operates stably and has good reliability can be realized even in a high-temperature environment.

[0070] Also, as shown in FIGS. 1B and 1C, a transistor having a back gate may be used for the transistor 111 included in the memory cell 110. FIG. 1B shows an example in which the back gate of the transistor 111 is electrically connected to the terminal 124. FIG. 1C shows an example in which the gate and the back gate of the transistor 111 are electrically connected.

[0071] Also, as shown in FIG. 1D, by using a transistor with a small off-current for transistor 111, capacitor 113 can be omitted.

[0072] Also, as shown in FIG. 1E, transistors having back gates may be used for transistor 131 and / or transistor 132. FIG. 1E shows an example in which the gate and the back gate of the transistor are electrically connected.

[0073] Also, the gate of transistor 111 may be electrically connected to wiring WL. Or, the gate of transistor 111 may be electrically connected to wiring WL via terminal 121. Also, the back gate of transistor 112 may be electrically connected to wiring CL. Or, the back gate of transistor 112 may be electrically connected to wiring CL via terminal 122. Also, the other terminal of capacitor 113 may be electrically connected to wiring GL. Or, the other terminal of capacitor 113 may be electrically connected to wiring GL via terminal 123.

[0074] In FIG. 2, an example is shown in which the gate of transistor 111[1] is electrically connected to wiring WL[1], the gate of transistor 111[2] is electrically connected to wiring WL[2], the gate of transistor 111[i] is electrically connected to wiring WL[i], and the gate of transistor 111[n] is electrically connected to wiring WL[n].

[0075] Also, in FIG. 2, an example is shown in which the back gate of transistor 112[1] is electrically connected to wiring CL[1], the back gate of transistor 112[2] is electrically connected to wiring CL[2], the back gate of transistor 112[i] is electrically connected to wiring CL[i], and the back gate of transistor 112[n] is electrically connected to wiring CL[n].

[0076] Also, FIG. 2 shows an example in which the other terminals of the capacitances 113[1], 113[2], 113[i], and 113[n] are electrically connected to the wiring GL. It is preferable that a fixed potential is supplied to the wiring GL. For example, it is preferable that a fixed potential such as VSS or GND is supplied to the wiring GL. Note that, as long as it is a fixed potential, it may be a potential other than VSS or GND. For example, it may be VDD.

[0077] Also, the gate of the transistor 131 may be electrically connected to the wiring RSL. Alternatively, the gate of the transistor 131 may be electrically connected to the wiring RSL via the terminal 133. Also, one of the source or drain of the transistor 131 may be electrically connected to the wiring RBL. Alternatively, one of the source or drain of the transistor 131 may be electrically connected to the wiring RBL via the terminal 138.

[0078] Also, the gate of the transistor 132 may be electrically connected to the wiring SSL. Alternatively, the gate of the transistor 132 may be electrically connected to the wiring SSL via the terminal 134. Also, the other of the source or drain of the transistor 132 may be electrically connected to the wiring SL. Alternatively, the other of the source or drain of the transistor 132 may be electrically connected to the wiring SL via the terminal 139.

[0079] Also, by using a plurality of memory devices 100, the memory capacity of the semiconductor device including the memory device 100 can be increased. That is, by increasing the number of strings, the memory capacity of the semiconductor device can be increased. As an example, FIGS. 3 and 4 show circuit diagrams in which two memory devices 100 (two strings) are connected in parallel. In FIGS. 3 and 4, the first memory device 100 is denoted as the memory device 100[1], and the second memory device 100 is denoted as the memory device 100[2].

[0080] In this case, for example, as shown in FIG. 3, the wiring RBL, the wiring SSL, the wiring SL, the wiring WL, and the wiring CL can be used as common wiring among a plurality of memory devices 100. Therefore, the semiconductor device having a plurality of memory devices 100 can be miniaturized. Further, as shown in FIG. 4, the wiring RSL may be used as common wiring, and the wiring RBL may be provided for each memory device 100. By providing the wiring RBL for each memory device 100, the information held by each memory device 100 can be read out simultaneously. Therefore, in a semiconductor device having a plurality of memory devices 100, the information readout speed can be increased.

[0081] Note that one string is often provided to extend in one direction. Further, the wirings (for example, the wiring WL and the wiring CL) for controlling writing or reading of information often extend in a direction orthogonal to the extending direction of the string.

[0082] <Modification Example 1> FIG. 5 shows a memory device 100A which is a modification example of the memory device 100. The difference between the memory device 100A and the memory device 100 is that one of the source or drain of the transistor 111[1] is electrically connected to the other of the source or drain of the transistor 131. In the memory device 100A, the wiring WBL shown in FIGS. 2 to 4 can be omitted. Therefore, the occupied area of the memory device 100 can be reduced.

[0083] <Operation Example of Memory Device> An operation example of the memory device 100 will be described with reference to the drawings. In the present embodiment, the memory device 100 shown in FIG. 2 including four memory cells 110 will be exemplified and described.

[0084] 〔Writing Operation〕 In the present embodiment, an operation example in the case of writing an H potential to the memory cells 110[1], 110[2], and 110[4], and writing an L potential to the memory cell 110[3] will be described. FIG. 6A is a timing chart for explaining the writing operation. FIGS. 7A, 7B, 8A, 8B, and 9 are circuit diagrams for explaining the writing operation.

[0085] As an initial state, assume that an L potential is written to memory cells 110[1] to 110[4]. Also, assume that an L potential is supplied to wirings WL[1] to WL[4], wirings CL[1] to CL[4], wiring RSL, wiring RBL, wiring SSL, and wiring SL. Also, assume that the potential of wiring GL is GND.

[0086] [Period T1] In period T1, supply an H potential to wirings WL[1] to WL[4] and wiring WBL (see Fig. 7A). Then, the potentials of nodes ND[1] to ND[4] become H potential. Therefore, transistors 112[1] to 112[4] turn on.

[0087] [Period T2] In period T2, supply an L potential to wiring WL[4] (see Fig. 7B). Then, transistor 111[4] turns off, and the charge written to node ND[4] is retained. Here, a charge corresponding to the H potential is retained. Also, after turning off transistor 111[4], supply an L potential to wiring WBL. Then, the potentials of nodes ND[1] to ND[3] become L potential. Therefore, transistors 112[1] to 112[3] turn off.

[0088] [Period T3] In period T3, supply an L potential to wiring WL[3] (see Fig. 8A). Then, transistor 111[3] turns off, and the charge written to node ND[3] is retained. Here, a charge corresponding to the L potential is retained. Also, after turning off transistor 111[3], supply an H potential to wiring WBL. Then, the potentials of nodes ND[1] and ND[2] become H potential. Therefore, transistors 112[1] and 112[2] turn on.

[0089] [Period T4] During period T4, an L potential is supplied to wiring WL[2] (see FIG. 8B). Then, transistor 111[2] turns off, and the charge written to node ND[2] is retained. Here, the charge corresponding to the H potential is retained.

[0090] [Period T5] During period T5, an L potential is supplied to wiring WL[1] (see FIG. 9). Then, transistor 111[1] turns off, and the charge written to node ND[1] is retained. Here, the charge corresponding to the H potential is retained. In this way, information can be written to memory cells 110[1] to 110[4].

[0091] As described above, the storage device 100 according to one aspect of the present invention does not require an erasing operation before data rewriting performed in a flash memory. Therefore, data rewriting can be performed in the same manner as the above-described writing operation.

[0092] Also, when writing information to a memory cell 110 close to wiring WBL, the operation of writing information to a memory cell 110 on the side farther from the wiring WBL than the memory cell 110 can be omitted. For example, when writing information to memory cell 110[1], the operations of writing information to memory cells 110[2] to 110[4] can be omitted. Also, when writing information to memory cell 110[2], the operations of writing information to memory cells 110[3] and 110[4] can be omitted. Therefore, by storing information with a high rewrite frequency in a memory cell 110 close to wiring WBL, the time required for writing (rewriting) the information can be shortened. That is, the speed of writing (rewriting) the information can be increased.

[0093] 〔Read operation〕 In this embodiment, an example of a read operation of the information held in the memory cells 110[1] to 110[4], specifically, the information held in the memory cell 110[2], will be described. Assume that the memory cell 110[2] holds an H potential. FIG. 6B is a timing chart for explaining the read operation. FIGS. 10A, 10B, 11A, and 11B are circuit diagrams for explaining the read operation.

[0094] [Period T6] In period T6, an H potential is supplied to the wirings CL[1] to CL[4] and the wiring RSL, turning on the transistors 112[1] to 112[4] and the transistor 131. Also, the wiring RBL is precharged to an H potential (see FIG. 10A). Specifically, after supplying an H potential to the wiring RBL, the wiring RBL is put into a floating state.

[0095] [Period T7] In period T7, an L potential is supplied to the wiring CL[2] (see FIG. 10B). Since the node ND[2] holds an H potential, the transistor 112[2] remains in the on state.

[0096] [Period T8] In period T8, an H potential is supplied to the wiring SSL, turning on the transistor 132 (see FIG. 11A). Since all of the transistors 112[1] to 112[4] are in the on state, the wiring RBL and the wiring SL are electrically connected, and the potential of the wiring RBL changes to an L potential.

[0097] Note that if the potential of the node ND[2] is an L potential, supplying an L potential to the wiring CL[2] turns off the transistor 112[2]. In this case, even when the transistor 132 is turned on, the potential of the wiring RBL remains at an H potential. By knowing the potential change of the wiring RBL, the information held in the memory cell 110 can be known.

[0098] That is, in period T8, by setting the potential of the wiring CL corresponding to the memory cell 110 to be read to the L potential, the information held in the memory cell 110 can be read out.

[0099] [Period T9] In period T9, an L potential is supplied to the wirings CL[1] to CL[4], the wiring RSL, and the wiring SSL (see FIG. 11B). Then, the transistors 131 and 132 are turned off.

[0100] Thus, the memory device 100 shown in this embodiment and the like functions as a NAND-type memory device.

[0101] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0102] (Embodiment 2) In this embodiment, other configuration examples and operation examples of the memory device 100 shown in the above embodiment will be described.

[0103] <Configuration Example of Memory Device> FIG. 12 shows a circuit diagram of the memory device 100B. FIG. 13 shows a circuit diagram of the memory device 100C. The memory devices 100B and 100C are modified examples of the memory device 100 shown in the above embodiment. To reduce repetition in the description, in this embodiment, the differences between the memory devices 100B and 100C and the memory device 100 will be mainly described.

[0104] The memory devices 100B and 100C have a configuration in which a transistor 116 is added to the memory device 100.

[0105] In the memory device 100B shown in FIG. 12, one of the source or drain of the transistor 111[1] is electrically connected to the wiring WBL1. Also, one of the source or drain of the transistor 116 is electrically connected to the node ND[n], and the other is electrically connected to the wiring WBL2. The gate of the transistor 116 is electrically connected to the terminal 136.

[0106] The memory device 100C shown in FIG. 13 is a modified example of the memory device 100B. In the memory device 100C, one of the source or drain of the transistor 111[1] is electrically connected to the other of the source or drain of the transistor 131. Also, in the memory device 100C, the other of the source or drain of the transistor 116 is electrically connected to one of the source or drain of the transistor 132.

[0107] Similar to the memory device 100, the gate of the transistor 111 included in the memory device 100B and the memory device 100C may be electrically connected to the wiring WL. Or, the gate of the transistor 111 may be electrically connected to the wiring WL via the terminal 121. Also, the back gate of the transistor 112 may be electrically connected to the wiring CL. Or, the back gate of the transistor 112 may be electrically connected to the wiring CL via the terminal 122. Also, the gate of the transistor 116 may be electrically connected to the wiring WSL described later. Or, the gate of the transistor 116 may be electrically connected to the wiring WSL via the terminal 136.

[0108] The same transistor as the transistor 111 can be used for the transistor 116. It is preferable to use an OS transistor for the transistor 116. Also, the transistor 116 may be a transistor having a back gate.

[0109] <Operation Example of Memory Device> An operation example of the memory device 100B will be described with reference to FIGS. 14, 15A, 15B, and 16. Here, a memory device 100B including four memory cells 110 will be exemplified and described. Also, in the memory device 100B, the gate of the transistor 111[1] is electrically connected to the wiring WL[1], the gate of the transistor 111[2] is electrically connected to the wiring WL[2], the gate of the transistor 111[3] is electrically connected to the wiring WL[3], the gate of the transistor 111[4] is electrically connected to the wiring WL[4], and the gate of the transistor 116 is electrically connected to the wiring WSL.

[0110] Also, in the memory device 100B, the back gate of the transistor 112[1] is electrically connected to the wiring CL[1], the back gate of the transistor 112[2] is electrically connected to the wiring CL[2], the back gate of the transistor 112[3] is electrically connected to the wiring CL[3], and the back gate of the transistor 112[4] is electrically connected to the wiring CL[4].

[0111] Also, in the memory device 100B, the gate of the transistor 131 is electrically connected to the wiring RSL, and one of the source or drain of the transistor 131 is electrically connected to the wiring RBL. Also, the gate of the transistor 132 is electrically connected to the wiring SSL, and the other of the source or drain of the transistor 132 is electrically connected to the wiring SL.

[0112] 〔Writing operation〕 In the present embodiment, an operation example in the case of writing an H potential to the memory cells 110[1] to 110[3] and writing an L potential to the memory cell 110[4] will be described. FIG. 14 is a timing chart for explaining the writing operation. FIGS. 15A, 15B, and 16 are circuit diagrams for explaining the writing operation.

[0113] As an initial state, assume that an L potential is written to memory cells 110[1] to 110[4]. Also, assume that an L potential is supplied to wirings WL[1] to WL[4], wirings CL[1] to CL[4], wiring RSL, wiring RBL, wiring SSL, wiring SL, wiring WSL, wiring WBL1, and wiring WBL2.

[0114] [Period T11] During period T11, supply an H potential to wirings WL[1], WL[2], WL[4], WSL, WBL1, and WBL2 (see Fig. 15A). Keep wiring WL[3] at the L potential. Then, transistors 111[1], 111[2], 111[4], and transistor 116 turn on, and the potentials of nodes ND[1] to ND[4] become the H potential. Thus, transistors 112[1] to 112[4] turn on.

[0115] [Period T12] During period T12, supply an L potential to wirings WL[2] and WL[4] (see Fig. 15B). Then, transistors 111[2] and 111[4] turn off, and the charges written to nodes ND[2] and ND[3] are retained. In this embodiment, charges corresponding to the H potential are retained. Also, supply an L potential to wiring WBL2. Then, the potential of node ND[4] becomes the L potential. Thus, transistor 112[4] turns off.

[0116] [Period T13] During period T13, supply an L potential to wirings WL[1] and WSL (see Fig. 16). Then, transistors 111[1] and 116 turn off, and the charges written to nodes ND[1] and ND[4] are retained. In this embodiment, charges corresponding to the H potential are retained at node ND[1], and charges corresponding to the L potential are retained at node ND[4].

[0117] In the memory device 100B, since information can be written from both the wiring WBL1 and the wiring WBL2, the time required for the writing operation can be made shorter than that of the memory device 100.

[0118] The memory device 100C can also operate in the same manner as the memory device 100B. However, in the memory device 100C, during the writing operation, the wiring RBL functions as the wiring WBL1, and the wiring SL functions as the wiring WBL2. In the memory device 100C, the transistors 131 and 132 are turned on during the writing operation. At this time, by supplying an L potential to at least one of the plurality of wirings CL, a short circuit between the wiring RBL and the wiring SL can be prevented.

[0119] In the memory device 100B and the memory device 100C, n is preferably an even number. When n is an even number, the transistor 111 that is turned off in the period T11 is the (n / 2 + 1)-th transistor 111.

[0120] 〔Read operation〕 The read operations of the memory device 100B and the memory device 100C can be performed in the same manner as the memory device 100. Therefore, the description in this embodiment is omitted.

[0121] <Modification example> A modification example of the memory device 100B is shown as the memory device 100D in FIG. 17. A modification example of the memory device 100C is shown as the memory device 100E in FIG. 18. The memory device 100D and the memory device 100E have a configuration in which the transistors 111[k] and 111[k + 1] are electrically separated except for the transistor 116 from the memory device 100B and the memory device 100C.

[0122] The memory device 100D and the memory device 100E preferably have n as an even number. When n is an even number, k may be n / 2.

[0123] In memory cell 110[k + 1], one of the source or drain of transistor 111[k + 1] is electrically connected to the gate of transistor 112[k + 1], and the other is electrically connected to one of the source or drain of transistor 111[k + 2] (not shown).

[0124] Also, in memory cell 110[n], one of the source or drain of transistor 111[n] is electrically connected to the gate of transistor 112[n], and the other is electrically connected to wiring WBL2. Also, one of the source or drain of transistor 111[n] is electrically connected to the other of the source or drain of transistor 111[n - 1] (not shown).

[0125] In memory cells 110[k + 1] to 110[n], the node where one of the source or drain of transistor 111 and the gate of transistor 112 are electrically connected functions as node ND.

[0126] The write operations of memory devices 100D and 100E can be performed in the same manner as memory devices 100B and 100C, except that there is no transistor 111 (for example, transistor 111[3] in the above write operation description) that is turned off during period T11. The read operation can also be performed in the same manner as memory devices 100B and 100C.

[0127] Also, in memory devices 100D and 100E, the write operations of memory cells 110[1] to 110[k] and the write operations of memory cells 110[k + 1] to 110[n] can be performed separately. Therefore, the power consumption required for the write operation can be reduced.

[0128] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0129] (Embodiment 3) In this embodiment, a configuration example of the semiconductor device 200 including the memory device 100 will be described.

[0130] FIG. 19 shows a block diagram illustrating a configuration example of a semiconductor device 200 which is one aspect of the present invention. The semiconductor device 200 shown in FIG. 19 includes a drive circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. FIG. 19 shows an example in which the memory array 220 includes a plurality of memory devices 100 (a plurality of strings) arranged in a matrix.

[0131] The drive circuit 210 includes PSW241 (power switch), PSW242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212 (Control Circuit), and a voltage generation circuit 228.

[0132] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alternatively, other circuits or other signals may be added. For example, a power supply circuit, a boost circuit, or the like may be provided. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0133] Also, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is a write data signal, and the signal RDA is a read data signal. The signals PON1 and PON2 are power gating control signals. Note that the signals PON1 and PON2 may be generated by the control circuit 212.

[0134] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit logically operates the signals CE, GW, and BW to determine the operation mode of the semiconductor device 200 (e.g., write operation, read operation). Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0135] The voltage generation circuit 228 has a function of generating a negative voltage. WAKE has a function of controlling the input to the voltage generation circuit 228 of CLK. For example, when a signal of H level is given to WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0136] The peripheral circuit 211 is a circuit for writing and reading data to and from the storage device 100. The peripheral circuit 211 includes a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0137] The row decoder 221 and the column decoder 222 have a function of decoding the signal ADDR. The row decoder 221 is a circuit for designating the row to be accessed, and the column decoder 222 is a circuit for designating the column to be accessed. The row driver 223 has a function of selecting the wiring WL designated by the row decoder 221. The column driver 224 has functions such as writing data to the storage device 100, reading data from the storage device 100, and holding the read data.

[0138] The input circuit 225 has a function of holding the signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is the data (Din) to be written into the storage device 100. The data (Dout) read by the column driver 224 from the storage device 100 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. Also, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0139] PSW241 has a function of controlling the supply of VDD to the peripheral circuit 215. PSW242 has a function of controlling the supply of VHM to the row driver 223. Here, the high power supply voltage of the semiconductor device 200 is VDD, and the low power supply voltage is GND (ground potential). Also, VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of PSW241 is controlled by the signal PON1, and the on / off of PSW242 is controlled by the signal PON2. In FIG. 19, in the peripheral circuit 215, the number of power supply domains to which VDD is supplied is set to 1, but it can also be made plural. In this case, a power switch may be provided for each power supply domain.

[0140] The drive circuit 210 and the memory array 220 may be provided on the same plane. Also, as shown in FIG. 20A, the drive circuit 210 and the memory array 220 may be provided in an overlapping manner. By providing the drive circuit 210 and the memory array 220 in an overlapping manner, the signal propagation distance can be shortened. Also, as shown in FIG. 20B, a plurality of memory arrays 220 may be provided in layers on the drive circuit 210.

[0141] Further, as shown in FIG. 20C, a memory array 220 may be provided in the upper layer and the lower layer of the drive circuit 210. FIG. 20C shows an example in which one layer of the memory array 220 is provided in the upper layer and the lower layer of the drive circuit 210, respectively. By arranging a plurality of memory arrays 220 so as to sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of layers of the memory array 220 laminated on the upper layer of the drive circuit 210 and the number of layers of the memory array 220 laminated on the lower layer of the drive circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 laminated on the upper layer of the drive circuit 210 is equal to the number of memory arrays 220 laminated on the lower layer of the drive circuit 210.

[0142] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0143] (Embodiment 4) In this embodiment, a transistor configuration applicable to the storage device 100 and the semiconductor device 200 described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked and provided will be described. By adopting such a configuration, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking and providing transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0144] A part of the cross-sectional structure of the semiconductor device is shown in FIG. 21. The semiconductor device shown in FIG. 21 includes a transistor 550, a transistor 500, and a capacitor 600. FIG. 23A is a cross-sectional view of the transistor 500 in the channel length direction, FIG. 23B is a cross-sectional view of the transistor 500 in the channel width direction, and FIG. 23C is a cross-sectional view of the transistor 550 in the channel width direction. For example, the transistor 500 corresponds to the transistor 111 shown in the above embodiment, and the transistor 550 corresponds to the transistor 112. Further, the capacitor 600 corresponds to the capacitor 113.

[0145] Transistor 500 is an OS transistor. The OS transistor has an extremely low off-current. Therefore, it is possible to hold the data voltage or charge written to the memory node via transistor 500 for a long period of time. That is, since the refresh operation frequency of the memory node (node ND) can be reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

[0146] In FIG. 21, transistor 500 is provided above transistor 550, and capacitor 600 is provided above transistor 550 and transistor 500.

[0147] Transistor 550 is provided on substrate 311 and has a semiconductor region 313 composed of a conductor 316, an insulator 315, and a part of substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b.

[0148] As shown in FIG. 23C, the upper surface and the side surface in the channel width direction of semiconductor region 313 of transistor 550 are covered with conductor 316 via insulator 315. In this way, by forming transistor 550 as a Fin type, the effective channel width can be increased, thereby improving the on characteristics of transistor 550. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of transistor 550 can be improved.

[0149] Note that transistor 550 may be either a p-channel type transistor or an n-channel type transistor.

[0150] In regions where the channel of the semiconductor region 313 is formed, regions in the vicinity thereof, source regions, or drain regions, such as the low-resistance regions 314a and 314b, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, by using GaAs, GaAlAs, etc., the transistor 550 may be a HEMT.

[0151] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron.

[0152] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron.

[0153] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding property, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0154] The transistor 550 may be formed using an SOI (Silicon on Insulator) substrate or the like.

[0155] As the SOI substrate, for example, after implanting oxygen ions into a mirror-polished wafer and then heating it at a high temperature, a SIMOX (Separation by Implanted Oxygen) substrate formed by forming an oxide layer to a certain depth from the surface and eliminating defects generated in the surface layer, or a smart cut method of splitting a semiconductor substrate by utilizing the growth by heat treatment of microvoids formed by hydrogen ion implantation, an SOI substrate formed using the ELTRAN method (registered trademark: Epitaxial Layer Transfer), etc. may be used. A transistor formed using a single crystal substrate has a single crystal semiconductor in the channel formation region.

[0156] Note that the transistor 550 shown in FIG. 21 is an example and is not limited to its configuration. An appropriate transistor may be used according to the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit of only OS transistors (meaning transistors of the same polarity such as only n-channel type transistors), as shown in FIG. 22, the configuration of the transistor 550 may be the same as that of the transistor 500. Details of the transistor 500 will be described later.

[0157] Over the transistor 550, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated and provided in this order.

[0158] As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0159] In this specification, silicon oxynitride refers to silicon with an oxygen content higher than its nitrogen content in terms of composition, and silicon nitride oxide refers to silicon with a nitrogen content higher than its oxygen content in terms of composition. Thus, in this specification, "oxynitride" refers to a material with an oxygen content higher than its nitrogen content in terms of composition, and "nitride oxide" refers to a material with a nitrogen content higher than its oxygen content in terms of composition.

[0160] The insulator 322 may function as a planarization film that planarizes steps generated by transistors 550 or the like provided therebelow. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0161] In addition, for the insulator 324, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from the substrate 311 or the transistors 550 or the like into the region where the transistor 500 is provided.

[0162] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor device having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor device may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0163] The amount of hydrogen desorption can be analyzed, for example, using a temperature programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 15 atoms / cm 2 preferably 5×10 15 atoms / cm 2 or less.

[0164] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0165] In addition, capacitors 600, or conductors 328 and 330 etc. connected to the transistors 500 are embedded in the insulators 320, 322, 324, and 326. Note that the conductors 328 and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral for a plurality of configurations. Also, in this specification etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0166] As materials for each plug and wiring (conductors 328, 330 etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in layers. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0167] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 21, the insulator 350, the insulator 352, and the insulator 354 are sequentially stacked and provided. Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function as a plug connected to the transistor 550 or a wiring. Note that the conductor 356 can be provided using the same material as the conductor 328 and the conductor 330.

[0168] Note that, for example, as with the insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 350. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0169] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0170] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 21, the insulator 360, the insulator 362, and the insulator 364 are sequentially stacked and provided. Further, a conductor 366 is formed on the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductor 328 and the conductor 330.

[0171] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. Further, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0172] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 21, the insulator 370, the insulator 372, and the insulator 374 are sequentially stacked and provided. Further, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function as a plug or a wiring. Note that the conductor 376 can be provided using the same materials as the conductor 328 and the conductor 330.

[0173] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. Further, the conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0174] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. 21, the insulator 380, the insulator 382, and the insulator 384 are sequentially stacked and provided. Further, a conductor 386 is formed in the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using the same materials as the conductor 328 and the conductor 330.

[0175] Note that, for example, as with insulator 324, it is preferable to use an insulator having a barrier property against hydrogen for insulator 380. Further, conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of insulator 380 having a barrier property against hydrogen. With this configuration, transistor 550 and transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from transistor 550 to transistor 500 can be suppressed.

[0176] In the above, the wiring layers including conductor 356, the wiring layers including conductor 366, the wiring layers including conductor 376, and the wiring layers including conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including conductor 356 may be three or less, or may be five or more.

[0177] On insulator 384, insulators 510, 512, 514, and 516 are sequentially stacked. It is preferable to use a material having a barrier property against oxygen or hydrogen for any of insulators 510, 512, 514, and 516.

[0178] For example, for insulators 510 and 514, it is preferable to use a film having a barrier property against hydrogen and impurities from, for example, substrate 311 or the region where transistor 550 is provided to the region where transistor 500 is provided. Therefore, the same material as that of insulator 324 can be used.

[0179] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between transistor 500 and transistor 550.

[0180] Also, as the film having barrier properties against hydrogen, for example, for the insulator 510 and the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0181] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0182] Also, for example, for the insulator 512 and the insulator 516, the same materials as those of the insulator 320 can be used. Further, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0183] Also, the conductor 518 and the conductor (for example, the conductor 503) constituting the transistor 500 are embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. Note that the conductor 518 functions as a capacitor 600, a plug connected to the transistor 550, or a wiring. The conductor 518 can be provided using the same materials as those of the conductor 328 and the conductor 330.

[0184] In particular, the insulator 510 and the conductor 518 in the region in contact with the insulator 514 are preferably conductors having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0185] Above the insulator 516, the transistor 500 is provided.

[0186] As shown in FIGS. 23A and 23B, the transistor 500 includes a conductor 503 disposed so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 disposed on the insulator 516 and the conductor 503, an insulator 522 disposed on the insulator 520, an insulator 524 disposed on the insulator 522, an oxide 530a disposed on the insulator 524, an oxide 530b disposed on the oxide 530a, conductors 542a and 542b disposed apart from each other on the oxide 530b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 disposed on the bottom surface and the side surface of the opening, and a conductor 560 disposed on the formation surface of the insulator 545.

[0187] Also, as shown in FIGS. 23A and 23B, it is preferable that an insulator 544 is disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Also, as shown in FIGS. 23A and 23B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 23A and 23B, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.

[0188] Note that in this specification and the like, the oxide 530a and the oxide 530b may be collectively referred to as the oxide 530.

[0189] Note that in the transistor 500, a configuration in which two layers of the oxide 530a and the oxide 530b are laminated in a region where a channel is formed and in its vicinity is shown, but the present invention is not limited to this. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0190] Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated configuration, but the present invention is not limited to this. For example, the conductor 560 may have a single-layer configuration or a laminated configuration of three or more layers. Also, the transistor 500 shown in FIGS. 21, 22, and 23A is an example, and the present invention is not limited to its configuration, and an appropriate transistor may be used according to the circuit configuration, driving method, and the like.

[0191] Here, the conductor 560 functions as a gate electrode of the transistor, and the conductors 542a and 542b function as a source electrode and a drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0192] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductors 542a and 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Thus, the switching speed of the transistor 500 can be improved, and it can have high frequency characteristics.

[0193] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0194] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thereby, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected and can cover the channel formation region formed in the oxide 530.

[0195] In this specification and the like, a configuration of a transistor in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is called a surrounded channel (S-channel) configuration. Further, the S-channel configuration disclosed in this specification and the like is different from the Fin type configuration and the planar type configuration. By adopting the S-channel configuration, the resistance to the short channel effect can be enhanced, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0196] Further, the conductor 503 has the same configuration as the conductor 518. A conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside. Note that in the transistor 500, the configuration in which the conductor 503a and the conductor 503b are laminated is shown, but the present invention is not limited thereto. For example, the conductor 503 may be provided in a single-layer or a laminated configuration of three or more layers.

[0197] Here, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material for the conductor 503a that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0198] For example, by having the function of suppressing the diffusion of oxygen in the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity.

[0199] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. Note that in this embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer configuration.

[0200] The insulator 520, the insulator 522, and the insulator 524 have a function as a second gate insulating film.

[0201] Here, as the insulator 524 in contact with the oxide 530, it is preferable to use an insulator containing more oxygen than the oxygen that satisfies the stoichiometric composition. Such oxygen is likely to be released from the film by heating. In this specification and the like, the oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancies in the oxide 530, such defects (hereinafter, may be referred to as V O H) may function as donors and electrons as carriers may be generated. Also, part of the hydrogen may combine with the oxygen that binds to the metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics. Also, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, it is preferable to reduce V O H in the oxide 530 as much as possible to make it highly pure intrinsic or substantially highly pure intrinsic. Thus, in order to obtain an oxide semiconductor in which V O H is sufficiently reduced, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to fill the oxygen vacancies (also referred to as "oxygen addition treatment"). By using an oxide semiconductor in which impurities such as V O H are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0202] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which a part of oxygen is desorbed by heating. The oxide that desorbs oxygen by heating means that in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0203] In addition, the insulator having the excess oxygen region and the oxide 530 may be subjected to any one or a plurality of treatments such as heat treatment, microwave treatment, or RF treatment in contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction in which the bond of VoH is broken occurs. In other words, a reaction of "V O H→Vo+H" occurs, and dehydrogenation can be achieved. A part of the hydrogen generated at this time may be combined with oxygen to form H2O and removed from the oxide 530 or the insulator near the oxide 530. In addition, a part of the hydrogen may be gettered by the conductor 542.

[0204] In addition, the microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Further, the microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. Further, as the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2+Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0205] In addition, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce the oxygen vacancies (V O ). The heat treatment may also be performed under reduced pressure. Alternatively, after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen. Alternatively, after performing the heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0206] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired by the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Furthermore, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 530 can be prevented from recombining with the oxygen deficiency to form V O H can be suppressed.

[0207] Also, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0208] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so that the oxygen contained in the oxide 530 does not diffuse to the insulator 520 side. In addition, the conductor 503 can be prevented from reacting with the oxygen contained in the insulator 524 and the oxide 530.

[0209] The insulator 522 is preferably a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0210] In particular, it is preferable to use an insulator containing one or both oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (the above oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and the like. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the mixing of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0211] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. The above insulators may be laminated with silicon oxide, silicon oxynitride, or silicon nitride and used.

[0212] Also, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining the insulator of the high-k material with silicon oxide or silicon oxynitride, an insulator 520 or an insulator 526 having a laminated structure that is thermally stable and has a high relative dielectric constant can be obtained.

[0213] In the transistor 500 of FIGS. 23A and 23B, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer laminated structure. However, the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0214] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for the oxide 530 including the channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0215] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0216] Also, as the metal oxide that functions as the channel formation region in the oxide 530, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0217] The oxide 530 has the oxide 530a under the oxide 530b, so that the diffusion of impurities from the constituent formed below the oxide 530a to the oxide 530b can be suppressed.

[0218] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0219] Further, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0220] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, it can also be said that the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0221] Specifically, when the oxide 530a and the oxide 530b have a common element (as the main component) other than oxygen, a mixed layer with a low density of defect energy levels can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0222] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0223] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0224] Also, in Fig. 23A, although the conductors 542a and 542b are shown as a single-layer structure, they may also have a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0225] Also, there are a three-layer structure in which a titanium film or a titanium nitride film and an aluminum film or a copper film are laminated on the titanium film or the titanium nitride film, and then a titanium film or a titanium nitride film is formed thereon, a three-layer structure in which a molybdenum film or a molybdenum nitride film and an aluminum film or a copper film are laminated on the molybdenum film or the molybdenum nitride film, and then a molybdenum film or a molybdenum nitride film is formed thereon, and the like. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0226] Also, as shown in Fig. 23A, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0227] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0228] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0229] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulator 544, silicon oxynitride or silicon nitride can also be used.

[0230] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, aluminum, and an oxide containing hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in a later process. Note that when the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material that does not significantly reduce conductivity even when absorbing oxygen, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0231] By having the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b. Further, it is possible to suppress the oxidation of the conductor 542 by the excess oxygen of the insulator 580.

[0232] The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains an excessive amount of oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0233] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0234] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the impurity concentration such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less. Also, the above-described microwave treatment may be performed before and / or after the formation of insulator 545.

[0235] Also, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0236] Note that insulator 545 may have a stacked structure similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be formed.

[0237] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 23A and 23B, but it may be a single-layer structure or a laminated structure of three or more layers.

[0238] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by oxygen contained in the insulator 545 and the resulting decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0239] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0240] The insulator 580 is provided on the conductors 542a and 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, as the insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, or resin, etc. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide with pores are preferable because an excess oxygen region can be easily formed in a later process.

[0241] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 from which oxygen is released by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in the insulator 580 is reduced.

[0242] The opening of the insulator 580 is formed to overlap the region between the conductors 542a and 542b. Thereby, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b.

[0243] When miniaturizing the semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. Therefore, if the film thickness of the conductor 560 is increased, the conductor 560 can have a shape with a high aspect ratio. In the present embodiment, since the conductor 560 is provided so as to be embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, it can be formed without collapsing the conductor 560 during the process.

[0244] The insulator 574 is preferably provided in contact with the upper surface of the insulator 580, the upper surface of the conductor 560, and the upper surface of the insulator 545. By forming the insulator 574 by a sputtering method, an excess oxygen region can be provided in the insulator 545 and the insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into the oxide 530.

[0245] For example, as the insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0246] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by a sputtering method can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0247] Also, it is preferable to provide an insulator 581 that functions as an interlayer film on the insulator 574. Similar to the insulator 524 and the like, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0248] Also, conductors 540a and 540b are arranged in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided to face each other with the conductor 560 interposed therebetween. The conductors 540a and 540b have the same configuration as the conductors 546 and 548 described later.

[0249] An insulator 582 is provided on an insulator 581. It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0250] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture which are factors causing fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0251] Also, an insulator 586 is provided on the insulator 582. The same material as that of the insulator 320 can be used for the insulator 586. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film, a silicon oxynitride film, etc. can be used.

[0252] Also, conductors 546, conductors 548, etc. are embedded in the insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, insulator 574, insulator 581, insulator 582, and insulator 586.

[0253] The conductor 546 and the conductor 548 have functions as plugs connected to the capacitor 600, the transistor 500, or the transistor 550, or as wirings. The conductor 546 and the conductor 548 can be provided using the same materials as those of the conductor 328 and the conductor 330.

[0254] Also, after forming the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having high barrier properties against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the above-described insulator having high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having high barrier properties against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and when the above-described insulator having high barrier properties is formed so as to be in contact with the insulator 522 or the insulator 514, a part of the manufacturing process of the transistor 500 can be also served, which is preferable. As the insulator having high barrier properties against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.

[0255] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0256] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0257] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) composed of the above-described elements can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide added with silicon oxide can also be applied.

[0258] In this embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the present invention is not limited to this configuration, and a stacked configuration of two or more layers may be used. For example, a conductor having barrier properties, and a conductor having high adhesiveness to the conductor having barrier properties and the conductor having high conductivity may be formed between the conductor having barrier properties and the conductor having high conductivity.

[0259] The conductor 620 is provided so as to overlap the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, when formed simultaneously with other components such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low-resistance metal material, may be used.

[0260] An insulator 640 is provided over the conductor 620 and the insulator 630. The insulator 640 can be formed using the same material as the insulator 320. Further, the insulator 640 may function as a planarization film covering the uneven shape therebelow.

[0261] By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0262] As substrates that can be used in a semiconductor device according to an aspect of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, or a compound semiconductor substrate, etc.), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of the present embodiment may be used. As an example of the glass substrate, there are barium borosilicate glass, aluminosilicate glass, or aluminoborosilicate glass, or soda lime glass, etc. In addition, crystallized glass, etc. can be used.

[0263] Alternatively, as the substrate, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film, etc. can be used. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Alternatively, as an example, there is a synthetic resin such as acrylic. Alternatively, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride, etc. Alternatively, as an example, there are polyamide, polyimide, aramid resin, epoxy resin, an inorganic vapor deposition film, or papers, etc. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., a transistor with little variation in characteristics, size, or shape, high current capacity, and small size can be manufactured. When a circuit is configured with such a transistor, power consumption reduction of the circuit or high integration of the circuit can be achieved.

[0264] Also, a flexible substrate may be used as the substrate, and transistors, resistors, and / or capacitors may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and transistors, resistors, and / or capacitors. After partially or fully completing a semiconductor device on the release layer, it can be separated from the substrate and transferred to another substrate. At this time, transistors, resistors, and / or capacitors can be transferred to substrates with poor heat resistance or flexible substrates. Note that for the above-mentioned release layer, for example, a laminated structure of inorganic films such as a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on the substrate, a silicon film containing hydrogen, etc. can be used.

[0265] That is, a semiconductor device may be formed on a certain substrate and then transferred to another substrate. As an example of the substrate to which the semiconductor device is transferred, in addition to the substrate on which the above-described transistors can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupra, rayon, regenerated polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is difficult to break, impart heat resistance, reduce weight, or reduce thickness.

[0266] By providing a semiconductor device on a flexible substrate, it is possible to suppress an increase in weight and provide a semiconductor device that is difficult to break.

[0267] <Modification Example 1 of Transistor> The transistor 500A shown in FIGS. 24A, 24B, and 24C is a modified example of the transistor 500 having the configuration shown in FIGS. 23A and 23B. FIG. 24A is a top view of the transistor 500A, FIG. 24B is a cross-sectional view of the transistor 500A in the channel length direction, and FIG. 24C is a cross-sectional view of the transistor 500A in the channel width direction. In the top view of FIG. 24A, the description of some elements is omitted for clarity of the drawing. The configurations shown in FIGS. 24A, 24B, and 24C can also be applied to other transistors included in a semiconductor device according to an aspect of the present invention, such as the transistor 550.

[0268] The transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C is different from the transistor 500 having the configuration shown in FIGS. 23A and 23B in that it has the insulator 552, the insulator 513, and the insulator 404. Further, the transistor 500A is different from the transistor 500 having the configuration shown in FIGS. 23A and 23B in that the insulator 552 is provided in contact with the side surfaces of the conductor 540a and the insulator 552 is provided in contact with the side surfaces of the conductor 540b. Furthermore, the transistor 500A is different from the transistor 500 having the configuration shown in FIGS. 23A and 23B in that it does not have the insulator 520.

[0269] In the transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C, the insulator 513 is provided on the insulator 512. Also, the insulator 404 is provided on the insulator 574 and on the insulator 513.

[0270] In the transistor 500A having the configuration shown in FIGS. 24A, 24B, and 24C, the insulators 514, 516, 522, 524, 544, 580, and 574 are patterned, and the insulator 404 is configured to cover them. That is, the insulator 404 is in contact with the upper surface of the insulator 574, the side surfaces of the insulator 574, the side surfaces of the insulator 580, the side surfaces of the insulator 544, the side surfaces of the insulator 524, the side surfaces of the insulator 522, the side surfaces of the insulator 516, the side surfaces of the insulator 514, and the upper surface of the insulator 513, respectively. Thereby, the oxide 530 and the like are isolated from the outside by the insulator 404 and the insulator 513.

[0271] The insulators 513 and 404 preferably have a high function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. For example, as the insulators 513 and 404, it is preferable to use silicon nitride or silicon oxynitride, which are materials with high hydrogen barrier properties. Thereby, since the diffusion of hydrogen or the like into the oxide 530 can be suppressed, the degradation of the characteristics of the transistor 500A can be suppressed. Therefore, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0272] The insulator 552 is provided in contact with the insulators 581, 404, 574, 580, and 544. The insulator 552 preferably has a function of suppressing the diffusion of hydrogen or water molecules. For example, as the insulator 552, it is preferable to use an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride, which is a material with high hydrogen barrier properties. In particular, since silicon nitride is a material with high hydrogen barrier properties, it is suitable for use as the insulator 552. By using a material with high hydrogen barrier properties as the insulator 552, the diffusion of impurities such as water or hydrogen from the insulator 580 or the like through the conductors 540a and 540b into the oxide 530 can be suppressed. Also, the absorption of oxygen contained in the insulator 580 by the conductors 540a and 540b can be suppressed. As described above, the reliability of the semiconductor device according to one aspect of the present invention can be enhanced.

[0273] <Modified Example 2 of Transistor> A configuration example of the transistor 500B will be described with reference to FIGS. 25A, 25B, and 25C. FIG. 25A is a top view of the transistor 500B. FIG. 25B is a cross-sectional view of the L1-L2 portion indicated by the dashed line in FIG. 25A. FIG. 25C is a cross-sectional view of the W1-W2 portion indicated by the dashed line in FIG. 25A. In the top view of FIG. 25A, the description of some elements is omitted for clarity of the drawing.

[0274] Transistor 500B is a modified example of transistor 500 and is a transistor that can be replaced with transistor 500. Therefore, to avoid repeating the description, mainly the differences between transistor 500B and transistor 500 will be described.

[0275] The conductor 560 that functions as the first gate electrode has the conductor 560a and the conductor 560b on the conductor 560a. It is preferable to use a conductive material for the conductor 560a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0276] Since the conductor 560a has a function of suppressing the diffusion of oxygen, the material selectivity of the conductor 560b can be improved. That is, by having the conductor 560a, oxidation of the conductor 560b can be suppressed, and a decrease in conductivity can be prevented.

[0277] Also, it is preferable to provide the insulator 544 so as to cover the upper surface and the side surface of the conductor 560 and the side surface of the insulator 545. Note that the insulator 544 may be made of an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon oxynitride, or silicon nitride can also be used.

[0278] By providing the insulator 544, oxidation of the conductor 560 can be suppressed. Also, by having the insulator 544, diffusion of impurities such as water and hydrogen that the insulator 580 has into the transistor 500B can be suppressed.

[0279] Since the conductor 560 overlaps a part of the conductor 542a and a part of the conductor 542b in the transistor 500B, the parasitic capacitance is likely to be larger than that of the transistor 500. Therefore, the operating frequency tends to be lower than that of the transistor 500. However, since the process of providing an opening in the insulator 580 and filling the conductor 560, the insulator 545, etc. is unnecessary, the productivity is high compared to the transistor 500.

[0280] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0281] (Embodiment 5) In this embodiment, the crystal structure of the oxide semiconductor and the like will be described in detail.

[0282] 〔Classification of Crystal Structure〕 First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 26A. FIG. 26A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0283] As shown in FIG. 26A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, "CAAC (c-axis-aligned crystalline)", "nc (nanocrystalline)", and "CAC (cloud-aligned composite)" are included in "Crystalline". Note that "single crystal", "poly crystal", and "completely amorphous" are excluded from the classification of "Crystalline". Further, "single crystal" and "poly crystal" are included in "Crystal".

[0284] Note that the structure within the thick frame shown in Fig. 26A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as an energetically unstable "Amorphous" or a structure completely different from "Crystal".

[0285] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained from the grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in Fig. 26B. Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained from the GIXD measurement shown in Fig. 26B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in Fig. 26B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in Fig. 26B is 500 nm.

[0286] As shown in Fig. 26B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected at around 2θ = 31°. Note that, as shown in Fig. 26B, the peak at around 2θ = 31° is asymmetric about the angle at which the peak intensity is detected.

[0287] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 26C. FIG. 26C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 26C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0288] As shown in FIG. 26C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0289] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 26A. For example, the oxide semiconductor can be divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. The non-single-crystalline oxide semiconductor also includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0290] Subsequently, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0291] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions are such that the c-axis is oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0292] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0293] Also, in an In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, the In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, the (M,Zn) layer) are laminated. Note that indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0294] When performing a structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in an out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0295] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0296] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is presumably because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0297] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and carriers are likely to be captured, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0298] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Thus, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0299] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Also, nc-OS has no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also referred to as restricted-view electron beam diffraction) using an electron beam with a probe diameter larger than the nanocrystals (for example, 50 nm or more) is performed on an nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on an nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0300] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0301] [Constitution of Oxide Semiconductor] Next, the details of the above-described CAC-OS will be explained. Note that the CAC-OS relates to the material constitution.

[0302] [CAC-OS] The CAC-OS is, for example, a constitution of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a state in which regions having the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0303] Furthermore, the CAC-OS is a constitution in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a constitution in which the first region and the second region are mixed.

[0304] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0305] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0306] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0307] For example, in the CAC-OS of In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0308] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0309] Oxide semiconductors have various structures, each with different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0310] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0311] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0312] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 16 cm -3 or less, even more preferably 1×10 13 cm -3 or less, even more preferably 1×10 12 cm-3 It is more preferable that it is less than. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, the fact that the impurity concentration is low and the density of defect levels is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0313] In addition, since the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0314] In addition, the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor having a high trap level density may have unstable electrical characteristics.

[0315] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0316] 〔Impurities〕 Here, the influence of each impurity in the oxide semiconductor will be described.

[0317] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon in the vicinity of the interface between the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3Hereinafter, it is preferably 2×10 17 atoms / cm 3 or less.

[0318] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0319] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 5×10 19 atoms / cm 3 less than, preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, even more preferably 5×10 17 atoms / cm 3 or less.

[0320] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , still more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0321] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0322] 〔Other Semiconductor Materials〕 The semiconductor materials that can be used for the oxide 530 are not limited to the above-described metal oxides. As the oxide 530, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layer material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, etc.) as the semiconductor material. In particular, it is suitable to use a layer material that functions as a semiconductor as the semiconductor material.

[0323] Here, in this specification and the like, the layer material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via a bond weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layer material has high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0324] Examples of the layer material include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing a chalcogen. Further, chalcogens are a general term for elements belonging to Group 16 and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0325] As the oxide 530, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 530 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0326] The configurations, structures, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, structures, methods, etc. shown in other embodiments and examples.

[0327] (Embodiment 6) In this embodiment, an example of a chip 1200, which is a type of semiconductor device in which the storage device of the present invention is implemented, will be described with reference to FIGS. 27A and 27B. A plurality of circuits (systems) are implemented in the chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as System on Chip (SoC).

[0328] As shown in FIG. 27A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0329] Bumps (not shown) are provided on the chip 1200 and are connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 27B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

[0330] Storage devices such as a DRAM 1221 and a flash memory 1222 may be provided on the motherboard 1203. It is preferable to use the semiconductor device shown in the previous embodiment as the flash memory 1222. By using the semiconductor device shown in the previous embodiment for the flash memory 1222, the storage capacity of the flash memory 1222 can be increased.

[0331] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. By providing an image processing circuit and a multiplication-accumulation circuit in the GPU 1212, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption.

[0332] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and transfer of the calculation result from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed at high speed.

[0333] The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the above multiplication-accumulation circuit may be provided in the analog operation unit 1213.

[0334] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0335] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0336] The network circuit 1216 has a network circuit for connecting to a LAN (Local Area Network) or the like. It may also have a circuit for network security.

[0337] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0338] A PCB 1201 provided with a chip 1200 having a GPU 1212, a motherboard 1203 provided with a DRAM 1221, and a flash memory 1222 can be called a GPU module 1204.

[0339] Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is preferably used in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. Further, by using the multiply-accumulate circuit using the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be executed. Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0340] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0341] (Embodiment 7) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as a memory card (e.g., SD card), USB memory, and SSD (Solid State Drive). Some configuration examples of the removable storage device are schematically shown in FIGS. 28A to 28E. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0342] FIG. 28A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The storage device or semiconductor device described in the previous embodiment can be incorporated into the memory chip 1105 or the like.

[0343] FIG. 28B is a schematic diagram of the appearance of an SD card, and FIG. 28C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data of the memory chip 1114 can be read and written by wireless communication between the host device and the SD card 1110. The storage device or semiconductor device described in the previous embodiment can be incorporated into the memory chip 1114 or the like.

[0344] FIG. 28D is a schematic diagram of the appearance of the SSD, and FIG. 28E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A storage device or a semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1154 and the like.

[0345] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

[0346] (Embodiment 8) FIGS. 29A to 29G show specific examples of electronic devices equipped with a storage device or a semiconductor device according to an aspect of the present invention.

[0347] <Electronic device / system> A storage device or a semiconductor device according to an aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book terminals, television devices, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, audio playback devices, and the like. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large computers such as server systems.

[0348] An electronic device according to an aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, and the like. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for wireless power transmission.

[0349] An electronic device according to an aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0350] An electronic device according to an aspect of the present invention can have various functions. For example, it can have functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, and a function of reading programs or data recorded on a recording medium.

[0351] [Information terminal] A storage device or a semiconductor device according to an aspect of the present invention can be used to form a storage device for holding a program of a microcontroller. Therefore, according to an aspect of the present invention, the microcontroller chip can be miniaturized.

[0352] FIG. 29A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to an aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Further, a storage device according to an aspect of the present invention may be used for the storage of the mobile phone. Thereby, the storage capacity per unit area of the storage can be increased.

[0353] FIG. 29B shows a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to an aspect of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Further, a storage device according to an aspect of the present invention may be used for the storage of the notebook information terminal. Thereby, the storage capacity per unit area of the storage can be increased.

[0354] Note that, in the above description, a smartphone and a notebook information terminal are illustrated in FIGS. 29A and 29B, respectively, as examples of electronic devices, but information terminals other than smartphones and notebook information terminals can be applied. Examples of information terminals other than smartphones and notebook information terminals include, for example, PDAs (Personal Digital Assistants), desktop information terminals, workstations, and the like.

[0355] [Game machine] FIG. 29C shows a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, and the like. The housing 5302 and the housing 5303 can be removed from the housing 5301. By attaching the connection unit 5305 provided in the housing 5301 to another housing (not shown), the video output to the display unit 5304 can be output to another video device (not shown). At this time, the housing 5302 and the housing 5303 can each function as an operation unit. Thereby, a plurality of players can play games simultaneously. A storage device or a semiconductor device according to an aspect of the present invention can be incorporated into chips and the like provided on the substrates of the housing 5301, the housing 5302, and the housing 5303.

[0356] Further, FIG. 29D shows a stationary game machine 5400 which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire.

[0357] By using a miniaturized microcontroller according to one aspect of the present invention in game machines such as the portable game machine 5300 and the stationary game machine 5400, the limited space inside the game machine can be effectively utilized. Further, a storage device or a semiconductor device according to one aspect of the present invention may be used for the storage of the portable game machine. Thereby, the storage capacity per unit area of the storage can be increased.

[0358] In FIGS. 29C and 29D, a portable game machine and a stationary game machine are illustrated as examples of game machines, but the game machines to which the microcontroller according to one aspect of the present invention is applied are not limited thereto. Examples of the game machines to which the microcontroller according to one aspect of the present invention is applied include, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), and pitching machines for batting practice installed in sports facilities.

[0359] [Mainframe computer] A storage device or a semiconductor device according to one aspect of the present invention can be applied to a mainframe computer.

[0360] FIG. 29E is a diagram showing a supercomputer 5500 which is an example of a mainframe computer. FIG. 29F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0361] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. Further, a plurality of circuit boards 5504 are provided in the computer 5502, and a microcontroller according to an aspect of the present invention can be mounted on the circuit board. By using the miniaturized microcontroller according to an aspect of the present invention, the limited space of a large computer can be effectively utilized. Also, a storage device or a semiconductor device according to an aspect of the present invention may be used for the storage of the large computer. Thereby, the storage capacity per unit area of the storage can be increased.

[0362] In FIGS. 29E and 29F, a supercomputer is illustrated as an example of a large computer, but the large computer to which the microcontroller according to an aspect of the present invention is applied is not limited thereto. Examples of the large computer to which the microcontroller according to an aspect of the present invention is applied include, for example, a computer (server) that provides services, a large general-purpose computer (mainframe), and the like.

[0363] [Home Appliance] FIG. 29G shows an electric refrigerator-freezer 5800 which is an example of a home appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0364] A storage device or a semiconductor device according to an aspect of the present invention can also be applied to the electric refrigerator-freezer 5800. For example, by applying the miniaturized microcontroller according to an aspect of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0365] Although an electric refrigerator has been described as an example of an electric appliance, other electric appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, and the like.

[0366] The electronic devices, the functions of the electronic devices, the effects, etc. described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0367] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

Example

[0368] A storage device 900 corresponding to the storage device 100B shown in the above embodiment was prototyped and its operation was verified. FIG. 30A shows an optical microscope photograph of the upper surface of the storage device 900. FIG. 30B shows a partial cross-sectional TEM photograph of the storage device 900.

[0369] <Circuit Configuration of Storage Device 900> FIG. 31 shows a circuit diagram of the storage device 900. The storage device 900 includes transistors WTr1 to WTr5 which are transistors for writing, transistors RTr1 to RTr4 which are transistors for reading, a transistor STr1, and a transistor STr2. These transistors are transistors using CAAC-IGZO for a semiconductor layer in which a channel is formed (also referred to as a "CAAC-IGZO FET"). Further, the channel length L of these transistors is 60 nm, and the channel width W is 60 nm. Further, these transistors are transistors having a back gate.

[0370] Further, the storage device 900 includes capacitances Cs1 to Cs4. Also, in FIG. 31, nodes SN1 to SN4 are shown. The capacitances of the capacitances Cs1 to Cs4 are each 3 fF.

[0371] In the memory device 900, the transistor WTr1 corresponds to the transistor 111[1] of the memory device 100B shown in the above embodiment, and the transistor RTr1 corresponds to the transistor 112[1] of the memory device 100B. Also, the transistor STr1 corresponds to the transistor 131, and the transistor STr2 corresponds to the transistor 132. Also, the capacitance Cs1 corresponds to the capacitance 113[1], and the node SN1 corresponds to the node ND[1].

[0372] The gate of the transistor WTr1 is electrically connected to the wiring WG1, the gate of the transistor WTr2 is electrically connected to the wiring WG2, the gate of the transistor WTr3 is electrically connected to the wiring WG3, the gate of the transistor WTr4 is electrically connected to the wiring WG4, and the gate of the transistor WTr5 is electrically connected to the wiring WG5. The back gates of the transistors WTr1 to WTr5 are electrically connected to the wiring WBG. The transistor WTr1 is electrically connected to the wiring WBL, and the transistor WTr5 is electrically connected to the wiring WSL.

[0373] The gate of the transistor RTr1 is electrically connected to the node SN1, the gate of the transistor RTr2 is electrically connected to the node SN2, the gate of the transistor RTr3 is electrically connected to the node SN3, and the gate of the transistor RTr4 is electrically connected to the node SN4.

[0374] The back gate of the transistor RTr1 is electrically connected to the wiring CG1, the back gate of the transistor RTr2 is electrically connected to the wiring CG2, the back gate of the transistor RTr3 is electrically connected to the wiring CG3, and the back gate of the transistor RTr4 is electrically connected to the wiring CG4. The gate of the transistor STr1 is electrically connected to the wiring SEL1, and the back gate is electrically connected to the wiring RBG1. The gate of the transistor STr2 is electrically connected to the wiring SEL2, and the back gate is electrically connected to the wiring RBG2. Also, the transistor STr1 is electrically connected to the wiring RBL, and the transistor STr2 is electrically connected to the wiring RSL.

[0375] <Verification of Write and Read Operations> Fig. 32A shows a timing chart used for verifying the write operation. The H potential supplied to wirings WG1 to WG5 was set to 3.3 V, and the L potential was set to -1.5 V. The H potential supplied to wiring WSL was set to 1.2 V, and the L potential was set to 0 V. Note that the H potential supplied to wiring WSL corresponds to Data "1", and the L potential supplied to wiring WSL corresponds to Data "0". A potential of 0 V was supplied to wiring WBL. In Fig. 32A, Write SN1 to Write SN4 indicate the periods for writing information to nodes SN1 to SN4.

[0376] Fig. 32B shows a timing chart used for verifying the read operation. The H potential supplied to wirings CG1 to CG4 was set to 3.3 V, and the L potential was set to 0 V. The H potential supplied to wiring RSL was set to 1.2 V, and the L potential was set to 0 V. The H potential supplied to wiring RBL was set to 3.3 V, and the L potential was set to 0 V. The H potential supplied to wirings SEL1 and SEL2 was set to 3.3 V, and the L potential was set to 0 V. Also, a potential of 1.0 V was supplied to wirings RBG1 and RBG2. In Fig. 32B, Read SN1 to Read SN4 indicate the periods for reading the information held by nodes SN1 to SN4.

[0377] <Temperature Dependence of Off-Current of CAAC-IGZO FET> Here, Fig. 33A shows the temperature dependence of the off-current (leakage current) of the CAAC-IGZO FET used in the memory device 900. The horizontal axis in Fig. 33A indicates the reciprocal of the temperature T, and the vertical axis indicates the off-state current per channel width of 1 μm. Also, Fig. 33A shows the results of measuring 20,000 transistors (M = 20,000) connected in parallel with a channel length L of 60 nm and a channel width W of 60 nm.

[0378] By performing an Arrhenius plot of the off-currents at 150°C, 125°C, 100°C, and 85°C, it was confirmed that the off-current at room temperature (R.T.) is approximately 2 [zA / μm].

[0379] Figure 33B shows the measurement results of the retention time of the information written in the memory device 900 at 85°C. The retention time is defined as the time until the potential of the node SN (any one of nodes SN1 to SN4) decreases by 0.2 V from the potential when the transistor WTr (any one of transistors WTr1 to WTr5) electrically connected to the node SN is turned off. The horizontal axis in Figure 33B is the retention time, and the vertical axis is the potential of the node SN (potential V SN ).). It can be seen from Figure 33B that information can be retained for 1 hour or more in an environment of 85°C. Note that since the off-current at 85°C is 50 times that at room temperature (see Figure 33A), it is suggested that data can be retained for about 2 days at room temperature.

[0380] <Verification of Rewrite Resistance> Next, the rewrite resistance of the memory device 900 was verified. The verification of the rewrite resistance was performed with -1.5 V supplied to wirings WG1 to WG4, 0 V supplied to wirings WBL, WBG, and RBL, 3.3 V supplied to wirings CG1 to CG3, 1 V supplied to wirings RBG1 and RBG2, and 1.2 V supplied to wiring RSL. In the above state, H potential (Data "1") and L potential (Data "0") were alternately written from wiring WSL to node SN4. The information (potential) written to node SN4 switches each time a signal (H potential) with a pulse width of 20 ns is supplied to wiring WG5. Figure 34A shows the timing chart of the signals supplied to wiring WG5 and wiring WSL.

[0381] Each time the number of write operations reaches 10 to the power of X (X is a natural number of 0 or more), the potential V SN when Data "1" is written to node SN4 and the potential V SN when Data "0" is written to node SN4 were obtained from the Id-Vg characteristics of the transistor and the current value of wiring RBL.

[0382] Figure 34B shows the verification results of rewrite endurance. The horizontal axis of Figure 34B is the number of write cycles, and the vertical axis is the potential V SN is. From Figure 34B, it can be seen that the memory device 900 has a clear potential difference (voltage window) between Data "1" and Data "0" even after 10^13 write operations, indicating good rewrite endurance.

[0383] <Verification of write disturbance resistance> Next, the write disturbance resistance of the memory device 900 was verified. In the memory device 900, the node SN is electrically connected by a single wiring via a transistor, and information can be written into different nodes SN simultaneously from both the wiring WBL and the wiring WSL. In this case, there is a concern that the data being held may be damaged due to the influence of the write operation of adjacent nodes SN.

[0384] Figure 35A is a timing chart for explaining the initial operation for verifying write disturbance resistance. As the initial operation, Data "0" is written into nodes SN1 and SN3, and Data "1" is written into nodes SN2 and SN4, and these pieces of information are held. Note that information was written into nodes SN1 and SN2 from the wiring WBL (Write from WBL). Information was written into nodes SN3 and SN4 from the wiring WSL (Write from WSL).

[0385] Thereafter, the information of nodes SN1 and SN4 was repeatedly rewritten in the same manner as the verification of rewrite endurance. Figure 35B shows a timing chart for verifying write disturbance resistance.

[0386] During the verification period, Data "1" is held in node SN2 and Data "0" is held in node SN3. Every time the number of write (rewrite) operations to nodes SN1 and SN4 reaches 10 to the power of X (where X is a natural number greater than or equal to 0), the information (potential) held in nodes SN2 and SN3 is measured. Figure 36A shows the verification results of write disturbance resistance. The horizontal axis in Figure 36A is the number of write cycles to nodes SN1 and SN4, and the vertical axis is the potential V of nodes SN2 and SN3 SN is shown.

[0387] From Figure 36A, it can be seen that even after 10 to the power of 9 cycles, there is no significant potential change in nodes SN2 and SN3, indicating that the information is retained. Therefore, it was found that the memory device 900 is less susceptible to the influence of write disturb. The CAAC-IGZO FET has a small parasitic capacitance such as the fringe factor. Therefore, it is speculated that even if the capacitance Cs is small, it is less susceptible to the influence of write disturb.

[0388] <Shmoo Plot of Gate Potential and Write Speed of Transistor WTr> Figure 36B shows the Shmoo plot of the potential V of the signal supplied to the gate of the write transistor WTr when writing information to the memory cell WG and the pulse width of the signal. The horizontal axis in Figure 36B is the pulse width (write pulse width) of the signal, and the vertical axis is the potential V WG is shown. Also, in Figure 36B, the combinations of potential V WG and pulse width when the information is successfully written are marked as "PASS", and the combinations when the information is not successfully written are marked as "FAIL".

[0389] From Figure 36B, the potential V WGIf it is 3.3V, it can be seen that information can be written normally even with a pulse width of 20 ns. The same applies when rewriting Data “1” to Data “0” and when rewriting Data “0” to Data “1”. Note that the pulse width corresponds to the writing speed. The shorter the pulse width when information is written normally, the faster the writing speed can be said.

[0390] Table 1 shows a comparison table between the prototype memory device 900 (This work) and NAND flash, PCM, and STT-MRAM.

[0391]

Table 1

[0392] Generally, in semiconductor devices such as computers, various memory devices are used according to the application. Fig. 37 shows various memory devices by layer. The higher the memory device is located in the hierarchy, the higher the access speed is required, and the lower the memory device is located in the hierarchy, the larger the memory capacity and the higher the recording density are required. In Fig. 37, from the top layer in order, it shows the memory mixed as a register in an arithmetic processing device such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0393] The memory mixed as a register in an arithmetic processing device such as a CPU is used for temporarily storing calculation results, etc., so the access frequency from the arithmetic processing device is high. Therefore, a faster operating speed is required rather than a memory capacity. Also, the register has a function of holding setting information of the arithmetic processing device, etc.

[0394] SRAM is used for, for example, a cache. The cache has a function of replicating and holding a part of the information held in the main memory. By replicating frequently used data in the cache, the access speed to the data can be increased.

[0395] DRAM is used, for example, as main memory. The main memory has a function of holding programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0396] 3D NAND memory is used, for example, as storage. The storage has a function of holding data that needs to be stored long-term and various programs used in the arithmetic processing unit. Therefore, the storage is required to have a storage capacity larger than the operating speed and a high recording density. The recording density of the storage device used for storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0397] The storage device according to one aspect of the present invention has a high operating speed and can hold data for a long period of time. The storage device according to one aspect of the present invention can be suitably used as a storage device located in the boundary region 901 including both the layer where the cache is located and the layer where the main memory is located. Further, the storage device according to one aspect of the present invention can be suitably used as a storage device located in the boundary region 902 including both the layer where the main memory is located and the layer where the storage is located.

[0398] <Device simulation of 3D OS NAND type memory device> CAAC-IGZO used for the storage device 900 can also be formed by ALD method. This suggests that transistors and the like according to one aspect of the present invention can be manufactured not only in the X-Y plane direction but also in the three-dimensional direction (Z-axis direction). A device simulation was performed assuming a 3D OS NAND type memory device in which a NAND type memory device according to one aspect of the present invention is provided in the three-dimensional direction.

[0399] Device simulation was performed using Synopsys' TCAD Sentaurus. FIG. 38 shows a two-dimensional structure diagram of the memory device 950 used in the device simulation. The device simulation was performed assuming a memory device 950 having a cylindrical structure obtained by rotating the two-dimensional structure shown in FIG. 38 by 360° about the Z-axis (Z-axis) as the central axis. Note that in the memory device 950, conductors FG1 to FG4 corresponding to nodes SN1 to SN4 are assumed. Also, in each of the IGZO layer of the Inner active layer and the IGZO layer of the Outer active layer, a doped region and a not doped region where impurities are not introduced were set.

[0400] Table 2 shows the calculation parameters used in the device simulation.

[0401]

Table 2

[0402] FIG. 39 shows the calculation results of the write operation and read operation of the memory device 950. FIG. 9 shows the potential changes of the wiring RBL, wiring CG, wiring WG, and wiring WSL in the write operation (Write Operation) and read operation (Read Operation). The horizontal axis in FIG. 39 is the elapsed time (Time).

[0403] From FIG. 39, it was found that the memory device 950 can perform data writing and reading operations based on the same principle as the memory device shown in the above embodiment and the like. Thereby, it was shown that the prototype memory device 900 can be manufactured vertically, and further miniaturization and high integration are possible.

[0404] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and the like.

Explanation of Reference Numerals

[0405] 100: Memory device, 110: Memory cell, 111: Transistor, 112: Transistor, 121: Terminal, 122: Terminal, 123: Terminal, 131: Transistor, 132: Transistor, 133: Terminal, 134: Terminal, 200: Semiconductor device, 210: Drive circuit, 211: Peripheral circuit, 212: Control circuit, 215: Peripheral circuit, 220: Memory array, 221: Row decoder, 222: Column decoder, 223: Row driver, 224: Column driver, 225: Input circuit, 226: Output circuit, 227: Sense amplifier, 228: Voltage generation circuit

Claims

【Claim 1】 having a first memory cell to a third memory cell and a first transistor, wherein the first memory cell has a second transistor, a third transistor, and a first capacitive element, wherein the second memory cell has a fourth transistor, a fifth transistor, and a second capacitive element, wherein the third memory cell has a sixth transistor, a seventh transistor, and a third capacitive element, wherein one of the source or drain of the first transistor is electrically connected to a first wiring, wherein the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the third transistor, wherein the gate of the first transistor is electrically connected to a second wiring, wherein one of the source or drain of the second transistor is electrically connected to a third wiring, wherein the other of the source or drain of the second transistor is electrically connected to the gate of the third transistor, wherein the gate of the second transistor is electrically connected to a fourth wiring, wherein the other of the source or drain of the third transistor is electrically connected to one of the source or drain of the fifth transistor, wherein the back gate of the third transistor is electrically connected to a fifth wiring, wherein the first electrode of the first capacitive element is electrically connected to the gate of the third transistor, wherein the second electrode of the first capacitive element is electrically connected to a sixth wiring, wherein one of the source or drain of the fourth transistor is electrically connected to the gate of the third transistor, wherein the other of the source or drain of the fourth transistor is electrically connected to the gate of the fifth transistor, wherein the gate of the fourth transistor is electrically connected to a seventh wiring, wherein the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the seventh transistor, wherein the back gate of the fifth transistor is electrically connected to an eighth wiring, wherein the first electrode of the second capacitive element is electrically connected to the gate of the fifth transistor, wherein the second electrode of the second capacitive element is electrically connected to the sixth wiring, wherein one of the source or drain of the sixth transistor is electrically connected to the gate of the fifth transistor, The other of the source or drain of the sixth transistor is electrically connected to the gate of the seventh transistor, The gate of the sixth transistor is electrically connected to a ninth wiring, The back gate of the seventh transistor is electrically connected to a tenth wiring, The first electrode of the third capacitive element is electrically connected to the gate of the seventh transistor, The second electrode of the third capacitive element is electrically connected to the sixth wiring, Memory device.

Images