Semiconductor device

Abstract

To provide a novel and nonvolatile latch circuit and a semiconductor device using the latch circuit.SOLUTION: A semiconductor device comprises: a latch part having a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element; and a data holding part for holding data, and the latch part and the data holding part compose a nonvolatile latch circuit. In the data holding part, a transistor which uses an oxide semiconductor as a semiconductor material for composing a channel formation region is used as a switching element. The semiconductor device further comprises an inverter electrically connected to a source electrode or a drain electrode of the transistor. By using the above-described transistor, data held by the latch part can be written in gate capacitance of the inverter or in separately prepared capacitance.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention is a non-volatile logic circuit and In particular, the present invention relates to a non-volatile latch circuit and a semiconductor device using the same. Relating to the body apparatus. [Background technology]

[0002] Non-volatile logic circuitry that retains its memory even when the power is turned off. For example, a non-volatile integrated circuit using a ferroelectric element has been proposed. A latch circuit has been proposed as a non-volatile logic (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2003 / 044953 Summary of the Invention [Problem to be solved by the invention]

[0004] However, non-volatile latch circuits using ferroelectric elements have problems such as reliability in terms of the number of rewrites and low voltage operation. In addition, ferroelectric elements are polarized by the electric field applied to the element, and this polarization However, if this residual polarization is small, the effect of variation is large. The size of the readout circuit may become larger, and a highly accurate readout circuit may be required.

[0005] In view of the above problem, one aspect of the present invention is a novel nonvolatile latch circuit and An object of the present invention is to provide a semiconductor device. [Means for solving the problem]

[0006] One embodiment of the present invention has a latch section having a loop structure in which the output of a first element is electrically connected to the input of a second element and the output of the second element is electrically connected to the input of the first element, and a data holding section for holding the data of the latch section. The latch section and the data holding section constitute a non-volatile latch circuit. The data holding section uses a transistor using an oxide semiconductor as a semiconductor material forming a channel region as a switching element. Further, it has an inverter electrically connected to the source electrode or the drain electrode of this transistor. Using the above transistor, the data held in the latch section can be written into the gate capacitance of the inverter or a separately provided capacitance. Also, using the above transistor, the data written into the gate capacitance of the inverter or a separately provided capacitance can be held. That is, one embodiment of the present invention has a latch section and a data holding section for holding the data of the latch section. The data holding section has a transistor and an inverter. The channel formation region of the transistor has an oxide semiconductor layer. One of the source electrode and the drain electrode of the transistor is electrically connected to a wiring to which an output signal is applied. The other of the source electrode and the drain electrode of the transistor is electrically connected to the input of the inverter. The output of the inverter is electrically connected to the wiring to which an input signal is applied, thereby constituting a non-volatile latch circuit. In the above, the data holding section can have a capacitance in addition to the transistor and the inverter.

[0007]

[0008] ​​​​​​​​​​​​​​​This capacity can be used for writing and holding data held in the latch section. One electrode of the above capacity can be used by being electrically connected to the other of the source electrode and the drain electrode of the transistor.

[0009] In the above, the latch section has a first element and a second element, the output of the first element is electrically connected to the input of the second element, and the output of the second element is electrically connected to the input of the first element, having a loop structure. Also, the input of the first element is electrically connected to a wiring to which an input signal is applied, and the output of the first element is electrically connected to a wiring to which an output signal is applied, having such a structure. For example, an inverter can be used as the first element and an inverter can be used as the second element. Also, for example, NAND can be used as the first element and a clocked inverter can be used as the second element.

[0010] In the above, the transistor has a function of writing data held in the latch section into the gate capacitance of the inverter in the data holding section or a separately prepared capacitance. Also, the transistor has a function of holding data written into the gate capacitance of the inverter in the data holding section or a separately prepared capacitance.

[0011] In the above, a transistor using an oxide semiconductor layer formed of an oxide semiconductor material for the channel formation region, for example, even an element with a channel width W of 1×10 μm and a channel length of 3μm 4 has an off-current at room temperature of 1×10 A or less and a subthreshold swing value (S value) of about 0.1V / dec. (gate insulating film thickness 100nm) can be obtained. -13 ​​​​​​​​​​​​Therefore, the off-current, that is, the leakage current, is significantly smaller than that of a transistor using silicon. Therefore, when a transistor using an oxide semiconductor layer in the channel formation region is used as a switching element, even after the supply of the power voltage to the latch circuit is stopped, the charges accumulated in the capacitance of the data holding section can be continuously held as they are. That is, the data written in the data holding section can be continuously held as they are. Further, after the supply of the power voltage to the latch circuit is restarted , the data held in the data holding section can be read out. Thereby, it is possible to restore to the logical state before the supply of the power voltage is stopped. Also, in terms of temperature characteristics, it is possible to obtain one with a sufficiently low off-current and a sufficiently high on-current even at high temperatures. For example, data has been obtained indicating that the Vg-Id characteristics of this transistor have little temperature dependence of the off-current, on-current, mobility, and S value in the range of -25°C to 150°C. As described above, one aspect of the present invention provides a non-volatile latch circuit that has a wide temperature operation range, operates stably even at high temperatures, and does not lose the stored logical state even when the power is turned off. In the above, by using a non-volatile latch circuit, various logic circuits can be provided. Also, various semiconductor devices using the above logic circuit can be provided.

[0012] For example, among the plurality of block circuits included in the logic circuit, the supply of the power voltage to one or more unused block circuits can be stopped. By using the above non-volatile latch circuit, even after the supply of the power voltage to the block circuit is stopped, the logical state of the block circuit can be stored. It can continue to store. Also, after the supply of the power voltage to the block circuit is restarted the stored logical state can be read out. As a result, it can be restored to the logical state before the supply of the power voltage is stopped

[0013] In the above, the oxide semiconductor layer can use materials of In-Ga-Zn-O system, In-Sn-O system, In- Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Z n-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn -O system, In-O system, Sn-O system, Zn-O system. Also, the oxide semiconductor layer can use one containing indium, gallium, and zinc. Also the hydrogen concentration of the oxide semiconductor layer is 5×10 19 / cm 3 or less, desirably 5×10 18 / cm 3 or less, more desirably 5×10 17 / cm 3 or less, more desirably 1×10 16 / cm 3 or less, more desirably 1×10 16 / cm 3 and can be less than. Also, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 or less, desirably 1×10 12 / cm 3 or less, more desirably 1×10 11 / cm 3 and can be less than. Also, the off-current at room temperature of the transistor can be 1×10 -13 A or less.

[0014] In the above, the transistor using the oxide semiconductor may be a bottom gate type​ It may be a top gate type. Also, it may be a bottom contact type or a top contact type. A bottom gate type transistor has at least a gate electrode on an insulating surface, a gate insulating film on the gate electrode, and an oxide semiconductor layer serving as a channel formation region overlapping the gate electrode on the gate insulating film. A top gate type transistor has at least an oxide semiconductor layer serving as a channel formation region on an insulating surface, a gate insulating film on the oxide semiconductor layer, and a gate electrode overlapping the oxide semiconductor layer on the gate insulating film. A bottom contact type transistor has an oxide semiconductor layer serving as a channel formation region on a source electrode and a drain electrode. A top contact type transistor has a source electrode and a drain electrode on an oxide semiconductor layer serving as a channel formation region.

[0015] Note that in this specification and the like, terms such as "above" and "below" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "a gate electrode on a gate insulating layer", it includes those that contain other components between the gate insulating layer and the gate electrode, except in the case where other components are included between the gate insulating layer and the gate electrode. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, they also include those with their top and bottom reversed.

[0016] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0017] ​​​​​​​​​​​ In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are employed, or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0018] In addition, in this specification and the like, "electrically connected" includes cases where connection is made via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0019] For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistive elements, inductors, capacitors, and other elements having various functions.

Advantages of the Invention

[0020] According to one embodiment of the present invention, by using a transistor that uses an oxide semiconductor as a semiconductor material constituting a channel formation region as a switching element of a data holding unit, a non-volatile latch circuit that has a wide temperature operation range and operates stably even at high temperatures, and whose stored logical state does not disappear even when the power is turned off, or a latch circuit incorporating a data holding unit with a sufficiently long refresh period can be realized. Since data writing is performed by switching the transistor, there is substantially no limit to the number of rewrite cycles. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operating voltage is about 1V. ​​​​​​​​​Or it can be made lower. Also, since the charge accumulated in the capacity of the data holding part is held as data as it is, compared with the case where the residual polarization component is used as data, it is less affected by variations and it is possible to easily read the data.

[0021] By using the above non-volatile latch circuit, it is possible to realize various logic circuits For example, in a logic circuit using a non-volatile latch circuit, the power supply of unused blocks can be turned off to reduce power consumption. Also, since the logic state is stored even when the power supply is turned off, system startup when the power supply is turned on and system termination when the power supply is turned off can be performed quickly and with low power.

Brief Description of Drawings

[0022]

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Embodiments for Carrying Out the Invention

[0023] Embodiments and examples of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments and examples shown below. In describing the configuration of the present invention using the drawings, the same reference numerals are commonly used among different drawings to indicate the same components.

[0024] Note that the size, layer thickness, or area of each component shown in the drawings and the like of each embodiment may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0025] Note that the ordinal terms such as first, second, and third used in this specification are for convenience in identifying components and do not limit the number thereof.

[0026] (Embodiment 1) This embodiment describes the configuration, operation, and manufacturing method of elements included in a non-volatile latch circuit, which is one aspect of the disclosed invention, with reference to FIGS. 1, 2, 3 to 6, FIGS. 7 to 17.

[0027] [Configuration and Operation of Non-volatile Latch Circuit] FIG. 1(A) shows the configuration of a non-volatile latch circuit 400 having a latch unit 411 and a data holding unit 401 that holds the data of the latch unit. FIG. 1(B) shows the configuration of the data holding unit 4 01.

[0028] The non-volatile latch circuit 400 shown in Fig. 1(A) has a latch section 411 having a loop structure in which the output of the first element (D1) 412 is electrically connected to the input of the second element (D2) 413, and the output of the second element (D2) 413 is electrically connected to the input of the first element (D1) 412, and a data holding section 401 for holding the data of the latch section. The input of the first element (D1) 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit is applied. The output of the first element (D1) 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit is applied. If there are a plurality of inputs of the first element (D1) 412, one of them can be electrically connected to the wiring 414 to which the input signal of the latch circuit is applied. If there are a plurality of inputs of the second element (D2) 413, one of them can be electrically connected to the output of the first element (D1) 412. The first element (D1) 412 can use an element that outputs an inverted input signal. For example, an inverter, NAND, NOR, clocked inverter, etc. can be used for the first element (D1) 412. Also, the second element (D2) 413 can use an element that outputs an inverted input signal. For example, an inverter, NAND, NOR, clocked inverter, etc. can be used for the second element (D2) 413.

[0029] The data holding section 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region.

[0030]

[0031]

[0032] ​​​​​​​​​​​​​The damaged transistor 402 is used as a switching element. This transistor 402 One of the source electrode and the drain electrode of is electrically connected to the wiring 415 to which the output signal is applied Further, the data holding unit 401 has a capacitor 404 and an inverter 403 that are electrically connected to the other of the source electrode and the drain electrode of this transistor 402 That is, one of the electrodes of the capacitor 404 and the input (input terminal) of the inverter 403 are electrically connected to the other of the source electrode and the drain electrode of this transistor 402 That is, one of the electrodes of the capacitor 404 and the input of the inverter 403 and the other of the source electrode and the drain electrode of the transistor 402 are electrically connected. The node where they are connected will be called node S A potential Vc is applied to the other electrode of the capacitor 404 Also, the output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is applied The inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is electrically connected to the high-level power supply voltage VDD The source electrode of the transistor 421 is electrically connected to the low-level power supply voltage VSS

[0033] Also, the output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is applied The inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is electrically connected to the high-level power supply voltage VDD The source electrode of the transistor 420 is electrically connected to the high-level power supply voltage VDD The source electrode of the transistor 421 is electrically connected to the low-level power supply voltage VSS is

[0034] The inverter 403 is not limited to the configuration shown in Fig. 1(B). For example, as shown in Fig. 2(A), , it may be composed of an N-channel transistor 420 and an N-channel transistor 421 , and a configuration with a buffer provided at the output may also be used. Also, instead of the inverter 403, a sense amplifier circuit may also be used . For example, a differential amplification type sense amplifier circuit as shown in Fig. 2(B) may be used . The differential amplification type sense amplifier circuit as shown in Fig. 2(B) is an N-channel The transistor 421 has an L shape, and transistors 501, 502 are N-channel transistors, and transistors 503 to 506 are P-channel transistors. In any case, it is important that the input (input terminal) is in a floating state (high impedance state). The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch section 411 into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403. Further, the transistor 402 has a function of holding the data written into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403. The operations of writing, holding, reading, and rewriting the data held in the latch section 411 to and from the data holding section 401 will be described. First, a potential at which the transistor 402 is turned on is supplied to the gate electrode of the transistor 402 to turn on the transistor 402. As a result, the data held in the latch section, that is, the potential of the wiring 415 to which the output signal is applied, is applied to one electrode of the capacitance 404 and the input terminal of the inverter 403. Consequently, charges corresponding to the potential of the wiring 415 are accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 (writing). Then, the potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 is turned off to turn off the transistor 402, whereby the charges accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 are held (holding). By reading the potential of one electrode of this capacitance 404 and the input terminal of the inverter 403, the data can be read (reading).

[0035] The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch section 411 into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403. The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch section 411 into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403. Further, the transistor 402 has a function of holding the data written into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403. The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch section 411 into the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403.

[0036] The operations of writing, holding, reading, and rewriting the data held in the latch section 411 to and from the data holding section 401 will be described. First, a potential at which the transistor 402 is turned on is supplied to the gate electrode of the transistor 402 to turn on the transistor 402. As a result, the data held in the latch section, that is, the potential of the wiring 415 to which the output signal is applied, is applied to one electrode of the capacitance 404 and the input terminal of the inverter 403. Consequently, charges corresponding to the potential of the wiring 415 are accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 (writing). Then, the potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 is turned off to turn off the transistor 402. As a result, the charges accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 are held (holding). By reading the potential of one electrode of this capacitance 404 and the input terminal of the inverter 403, the data can be read (reading). Then, the potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 is turned off to turn off the transistor 402, whereby the charges accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 are held (holding). By reading the potential of one electrode of this capacitance 404 and the input terminal of the inverter 403, the data can be read (reading). The operations of writing, holding, reading, and rewriting the data held in the latch section 411 to and from the data holding section 401 will be described. First, a potential at which the transistor 402 is turned on is supplied to the gate electrode of the transistor 402 to turn on the transistor 402. As a result, the data held in the latch section, that is, the potential of the wiring 415 to which the output signal is applied, is applied to one electrode of the capacitance 404 and the input terminal of the inverter 403. Consequently, charges corresponding to the potential of the wiring 415 are accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 (writing). Then, the potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 is turned off to turn off the transistor 402, whereby the charges accumulated in one electrode of the capacitance 404 and the gate capacitance of the inverter 403 are held (holding). By reading the potential of one electrode of this capacitance 404 and the input terminal of the inverter 403, the data can be read (reading). By reading the potential of one electrode of this capacitance 404 and the input terminal of the inverter 403, the data can be read (reading). )。The data can be rewritten in the same manner as the above-mentioned data writing and holding.

[0037] The oxide semiconductor layer of the transistor 402 is an In-Ga-Zn-O system, In-Sn- O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, A l-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system , Al-Zn-O system, In-O system, Sn-O system, Zn-O system materials are preferably used.

[0038] It is desirable that the oxide semiconductor layer is sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer is 5×10 / cm 19 or less, preferably 5×10 3 / cm or less, more preferably 5×10 18 / cm 3 or less, more preferably 5×10 17 / cm 3 or less, more preferably 1×10 / cm 16 or less, more preferably 1×10 3 / cm 16 or less, and less than. 3 In addition, the carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 or less, preferably 1×10 12 / cm 3 or less, more preferably 1×10 11 / cm 3 or less. Also , the oxide semiconductor layer with a sufficiently reduced hydrogen concentration and high purity has a carrier concentration (1×10 / cm 14 in a general silicon wafer (a silicon wafer doped with trace amounts of impurity elements such as phosphorus and boron) 3 ​​takes a value of carrier concentration that is sufficiently small compared to (a certain level) .

[0039] In this way, by using an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and purified and the carrier concentration is sufficiently low, and which is of i-type or substantially i-type, a transistor 402 with extremely excellent off-current characteristics can be obtained. For example, even in an element with a channel width W of 1×10 μm and a channel length L of 3 μm, when the drain voltage Vd applied to the drain electrode is + 1 V or +10 V, and the gate voltage Vg applied to the gate electrode is in the range from -5 V to 4 -20 V, the off-current at room temperature is 1×10 A or less. Also, in terms of temperature characteristics, a transistor can be obtained in which the off-current is sufficiently low and the on-current is sufficiently high even at high temperatures. For example, data has been obtained indicating that the temperature dependencies of the off-current, on-current, mobility, and S value of the Vg-Id characteristics of the transistor 402 are small in the range of -25°C to 150°C. Note that the hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS). -13 econdary Ion Mass Spectroscopy).

[0040] Note that the oxide semiconductor constituting the oxide semiconductor layer is not particularly limited as long as it has a non-single crystal structure. For example, various structures can be applied, such as an amorphous structure, a microcrystalline (microcrystal, nanocrystal, etc.) structure, a polycrystalline structure, a structure in which microcrystals or polycrystals are included in the amorphous, and a structure in which microcrystals or polycrystals are formed on the surface of the amorphous structure.

[0041] In this way, by using an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and purified and the carrier concentration is sufficiently low, and which is of i-type or substantially i-type​​​​​​​​​ By using a transistor 402 made of a typed or substantially typed oxide semiconductor for switching element, even after the supply of the power voltage to the latch circuit 400 is stopped, the charges accumulated in the capacitance 404 of the data holding section 401 and the gate capacitance of the inverter 403 can be held continuously for an extremely long time. That is, the data written into the data holding section 401 can be held continuously for an extremely long time. Also, after the supply of the power voltage to the latch circuit 4 00 is restarted, the data held in the data holding section 401 can be read out. Thereby, it is possible to restore to the logical state before the supply of the power voltage is stopped. Thus, by using a transistor 40 2 made of an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and highly purified and the carrier concentration is sufficiently low as a switching element, a new non-volatile latch circuit with a wide temperature operation range that operates stably even at high temperatures and does not lose the stored logical state even when the power is turned off can be realized.

[0042] Among the elements of the non-volatile latch circuit 400, elements other than the transistor 402 can use materials other than the oxide semiconductor as the semiconductor material. As materials other than the oxide semiconductor, single crystal silicon, crystalline silicon, etc. can be used. For example, elements other than the transistor 40 2 can be provided on a substrate containing a semiconductor material. As a substrate containing a semiconductor material, a silicon wafer, an SOI (Silicon on Insulato r) substrate, a silicon film on an insulating surface, etc. can be used. By using materials other than the oxide semiconductor, high-speed operation becomes possible. ​

[0043] Among the elements included in the non-volatile latch circuit 400, elements other than the transistor 402 can also use an oxide semiconductor as the semiconductor material.

[0044] <Planar and cross-sectional configurations of elements included in the non-volatile latch circuit> FIG. 3 is an example of the configuration of the transistor 402 included in the non-volatile latch circuit and elements other than the transistor 402. Here, as an example of an element other than the transistor 402, the transistor 421 included in the inverter 403 of the data holding section 401 will be described. Other elements other than the transistor 402 can have the same or similar configuration as the transistor 421. Elements such as the capacitor 404 can be formed using a film that constitutes an element other than the transistor 402 or the transistor 402. FIG. 3(A) shows a cross-section, and FIG. 3(B) shows a plan view. Here, FIG. 3(A) corresponds to a cross-section along lines A1 - A2 and B1 - B2 in FIG. 3(B). As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part. The transistor 421 includes a channel formation region 116 provided on a substrate 100 containing a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. FIG. 3(A) shows a cross-section, and FIG. 3(B) shows a plan view. Here, FIG. 3(A) corresponds to a cross-section along lines A1 - A2 and B1 - B2 in FIG. 3(B). As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part. Here, FIG. 3(A) corresponds to a cross-section along lines A1 - A2 and B1 - B2 in FIG. 3(B). As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part. 1 - B2. As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part. 1 - B2. As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part. 1 - B2. As shown in FIGS. 3(A) and 3(B), a transistor 421 using a material other than an oxide semiconductor is provided at the lower part, and a transistor 402 using an oxide semiconductor is provided at the upper part.

[0045] The transistor 421 is provided with a channel formation region 116 provided on a substrate 100 containing a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. 6, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. 6, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. 6, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. 6, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 1 electrically connected to the impurity region 114. It has a source electrode or a drain electrode 130b.

[0046] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 when viewed from the plane, a high-concentration impurity region 120 exists, and a metal compound region 124 exists on the high-concentration impurity region 120. Also, an element isolation insulating layer 1 06 is provided so as to surround the transistor 421, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 421. The source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b is electrically connected to the metal compound region 124 through openings formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. That is, the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b is electrically connected to the high-concentration impurity region 120 and the impurity region 114 through the metal compound region 1 24. Also, an electrode 130c provided in the same manner as the source electrode or the drain electrode 130a or the source electrode or the drain electrode 130b is electrically connected to the gate electrode 110a.

[0047] The transistor 402 has a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, an oxide semiconductor layer 140 provided on the gate insulating layer 138, and a source electrode or a drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or a drain electrode 142b.

[0048] ​​​​​​​ Here, the gate electrode 136d is provided so as to be embedded in the insulating layer 132 formed on the interlayer insulating layer 128. Also, similar to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or the drain electrode 130a, an electrode 136b is formed in contact with the source electrode or the drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c.

[0049] Further, a protective insulating layer 144 is provided on the transistor 402 so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, electrodes 150d and 150e are formed in contact with the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b. Also, simultaneously with the formation of the electrodes 150d and 150e, electrodes 150a, 150b, and 150c in contact with the electrodes 136a, 136b, and 136c are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0050] Here, it is desirable that the oxide semiconductor layer 140 has sufficiently removed impurities such as hydrogen and is highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 / cm 19 or less, desirably 5×10 3 / cm 18 or less, more desirably 5×10 3 / cm 17 or less, more desirably 1×10 3 / cm or less.16 / cm 3 Hereinafter, more preferably 1×10 16 / cm 3 or less. Further, the carrier concentration of the oxide semiconductor layer 140 is 1×10 14 / cm 3 or less, preferably 1×10 12 / cm 3 or less, more preferably 1×10 11 / cm 3 not fully filled. Further, the oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and purified has a carrier concentration (1×10 in the case of a general silicon wafer (a silicon wafer doped with trace amounts of impurity elements such as phosphorus and boron)) and takes a value of a carrier concentration that is sufficiently small compared to (about 14 / cm 3 ). Thus, by using an oxide semiconductor in which the hydrogen concentration is sufficiently reduced and purified and the carrier concentration is sufficiently low, i-type or substantially i-type, a transistor 402 with extremely excellent off-current characteristics can be obtained. For example, even in an element with a channel width W of 1×10 μm and a channel length L of 3 μm, when the drain voltage Vd applied to the drain electrode is +1V or +10V, and the gate voltage Vg applied to the gate electrode is in the range of -5V to -20V, the off-current at room temperature is 1× 10 A or less. Note that the hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy). 4 (SIMS: Secondary Ion Mass Spectroscopy) is measured by it. When the drain voltage Vd applied to the drain electrode is +1V or +10V, and the gate voltage Vg applied to the gate electrode is in the range of -5V to -20V, the off-current at room temperature is 1× 10 -13 A or less. The hydrogen concentration in the oxide semiconductor layer is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy) and is determined by it.

[0051] Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and the insulating layer 152 is filled The electrodes 154a, 154b, 154c, and 154d are provided so as to be embedded. Here, the electrode 154a is in contact with the electrode 150a, and the electrode 154b is in contact with the electrode 150 b. The electrode 154c is in contact with the electrodes 150c and 150d, and the electrode 1 54d is in contact with the electrode 150e.

[0052] That is, in the elements of the non-volatile latch circuit shown in FIG. 3, the gate electrode 110a of the transistor 421 and the source electrode or drain electrode 142a of the transistor 402 are electrically connected through the electrodes 130c, 136c, 150c, 154c, and 150d.

[0053] <Fabrication method of elements included in non-volatile latch circuit> Next, an example of the fabrication method of the elements included in the non-volatile latch circuit will be described. Hereinafter with reference to FIG. 4, the fabrication method of the lower transistor 421 will be described first, and then with reference to FIGS. 5 and 6, the fabrication method of the upper transistor 402 will be described.

[0054] <Fabrication method of lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4(A)). As the substrate 100 containing a semiconductor material a single-crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, an example in the case of using a single-crystal silicon substrate as the substrate 100 containing a semiconductor material will be shown. Generally, the "SOI substrate" refers to a substrate having a silicon semiconductor layer provided on an insulating surface. In this specification, etc., silicon on an insulating surface ​ It is used as a concept including a substrate having a semiconductor layer made of a material other than this. That is, the semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. Also, for the SOI substrate, those having a structure in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate are also included.

[0055] On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see Fig. 4(A)). As the protective layer 102, for example, an insulating layer made of a material such as silicon oxide, silicon nitride, or silicon oxynitride can be used. Note that, before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon, as the impurity imparting n-type conductivity, for example, phosphorus or arsenic can be used. Also, as the impurity imparting p-type conductivity, for example, boron, aluminum, gallium, etc. can be used.

[0056] Next, etching is performed using the above protective layer 102 as a mask, and a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region) is removed. Thereby, the separated semiconductor region 104 is formed (see Fig. 4(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected according to the material to be etched.

[0057] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region By selectively removing the insulating layer, the element isolation insulating layer 106 is formed (see Fig. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As methods for removing the insulating layer, there are polishing processes such as CMP and etching processes, and any of them may be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0058] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer.

[0059] The insulating layer will be the subsequent gate insulating layer, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. obtained by using the CVD method, sputtering method, etc. Alternatively, the surface of the semiconductor region 104 may be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above insulating layer. The high-density plasma treatment can be performed using, for example, a mixed gas of rare gases such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer is not particularly limited, but can be, for example, 1 nm or more and 100 nm or less.

[0060] The layer containing the conductive material can be formed using metal materials such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, a semiconductor material such as polycrystalline silicon containing the conductive material may be used to form the layer containing the conductive material. The formation method is not particularly limited, and various film formation methods such as evaporation, CVD, sputtering, spin coating can be used. ​​​​​​​​​​​​ In addition, in this embodiment, an example of forming a layer containing a conductive material using a metal material is shown below.

[0061] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 a and the gate electrode 110a (see FIG. 4(C)).

[0062] Next, an insulating layer 112 covering the gate electrode 110a is formed (see FIG. 4(C)). Then, phosphorus (P), arsenic (As), or the like is added to the semiconductor region 104 to form an impurity region 114 having a shallow junction depth (see FIG. 4(C)). Here, phosphorus or arsenic is added to form an n-type transistor, but when forming a p-type transistor, impurity elements such as boron (B) or aluminum (Al) may be added. Note that by forming the impurity region 114, a channel formation region 11 6 is formed below the gate insulating layer 108a of the semiconductor region 104 (see FIG. 4(C)). Here, the concentration of the added impurity can be set as appropriate, but when the semiconductor device is highly miniaturized, it is desirable to increase the concentration. Also, here, the step of forming the impurity region 114 after forming the insulating layer 112 is adopted, but the step of forming the insulating layer 112 after forming the impurity region 114 may also be good.

[0063] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The sidewall insulating layer 118 can be self-alignedly formed by forming an insulating layer so as to cover the insulating layer 112 and then applying an anisotropic etching process to the insulating layer. Also, at this time high etching process is applied to the insulating layer, and then the sidewall insulating layer 118 can be formed self-alignedly. Also, at this time Partially etch the insulating layer 112 to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114.

[0064] Next, form an insulating layer to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, add phosphorus (P), arsenic (As), etc. to the region in contact with the impurity region 114 to form a high-concentration impurity region 120. After that, remove the above insulating layer and form a metal layer 122 to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 4(E)). The metal layer 122 can be formed using various film-forming methods such as vacuum evaporation method, sputtering method, spin coating method, etc. It is desirable to form the metal layer 122 using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metallization compound. Examples of such metal materials include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc.

[0065] Next, perform a heat treatment to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see Fig. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, a metal compound region is also formed at the portion where the metal layer 122 of the gate electrode 11 0a contacts.

[0066] As the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods can also be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method that can achieve a very short heat treatment time. This is preferable. Note that the above metal compound region is formed by the reaction between the metal material and the semiconductor material and is a region with sufficiently enhanced conductivity. By forming the metal compound region, the electrical resistance can be sufficiently reduced and the device characteristics can be improved. After forming the metal compound region 124, the metal layer 122 is removed.

[0067] Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each component formed by the above-described process (see Fig. 4(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form them using an organic insulating material such as polyimide or acrylic. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is adopted, but the configuration of the interlayer insulating layer is not limited to this. After forming the interlayer insulating layer 128, it is desirable to planarize its surface by CMP, etching treatment, or the like.

[0068] Thereafter, an opening reaching the metal compound region 124 is formed in the above interlayer insulating layer, and a source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening (see Fig. 4(H)). The source electrode or drain electrode 130a and the source electrode or drain electrode 130b can be formed, for example, by forming a conductive layer in the region including the opening using a PVD method, a CVD method, or the like, and then removing a part of the conductive layer using a method such as etching treatment or CMP.

[0069] ​​​​​​​​​In addition, when forming the source electrode or drain electrode 130a or the source electrode or drain electrode 130b by removing a part of the conductive layer, it is desirable to process it so that its surface becomes flat. For example, after thinly forming a titanium film or a titanium nitride film in a region including an opening, when forming a tungsten film so as to embed it in the opening, unnecessary tungsten, titanium, titanium nitride, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface including the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. Here, only the source electrode or drain electrode 130 a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this process, an electrode (for example, the electrode 130c in FIG. 3(A)) in contact with the gate electrode 110a, etc.

[0070] can be formed together. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. Here, only the source electrode or drain electrode 130 a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this process, an electrode (for example, the electrode 130c in FIG. 3(A)) in contact with the gate electrode 110a, etc. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used.

[0071] As described above, the transistor 421 using the substrate 100 including a semiconductor material is formed. In addition, after the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure, high In addition, after the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure, high In addition, after the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure having a laminated structure of an interlayer insulating layer and a conductive layer as the wiring structure, high It is possible to provide a semiconductor device with increased integration density.

[0072] <Fabrication method of upper transistor> Next, with reference to FIGS. 5 and 6, the process of fabricating the transistor 402 on the interlayer insulating layer 128 will be described. Note that FIGS. 5 and 6 show the fabrication processes of various electrodes on the interlayer insulating layer 128 and the transistor 402, etc., and transistors 421 etc. existing below the transistor 402 are omitted.

[0073] First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and the electrode 130c (see FIG. 5(A)). The insulating layer 132 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0074] Next, openings reaching the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and the electrode 130c are formed in the insulating layer 132. At this time, openings are also formed in the region where the gate electrode 136d will be formed later. Then, a conductive layer 134 is formed so as to fill the above openings (see FIG. 5(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching can be used, but from the viewpoint of microfabrication, dry etching is preferred. It is preferable to use a thing. The formation of the conductive layer 134 can be carried out using a film formation method such as PVD method or CVD method. As materials that can be used for the formation of the conductive layer 134, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc., and alloys and compounds (such as nitrides) thereof can be mentioned.

[0075] More specifically, for example, a titanium film is thinly formed by PVD method in a region including an opening, and after thinly forming a titanium nitride film by CVD method, a tungsten film can be formed so as to be embedded in the opening. Here, the titanium film formed by PVD method reduces the contact resistance with the lower electrode (here, the source electrode or drain electrode 130a, source electrode or drain electrode 130b, electrode 130c, etc.) by reducing the oxide film on the interface. Also, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material. Also, after forming a barrier film with titanium or titanium nitride, etc., a copper film may be formed by plating method.

[0076] After forming the conductive layer 134, a part of the conductive layer 134 is removed using methods such as etching treatment or CMP to expose the insulating layer 132, and the electrodes 136a, 136b, 136c, and gate electrode 136d are formed (see Fig. 5(C)). Note that when removing a part of the conductive layer 134 to form the electrodes 136a, 136b, 136c, and gate electrode 136d, it is desirable to process so that the surface becomes flat. In this way, the surfaces of the insulating layer 132, electrodes 136a, 136b, 136c, and gate electrode 136d are flattened. ​​​​​​​​By doing so, in subsequent processes, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. This becomes possible.

[0077] Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrodes 136a, 136b, 136c, and the gate electrode 136d (see FIG. 5(D)). The gate insulating layer 138 can be formed using a CVD method, a sputtering method, or the like. Further, the gate insulating layer 138 can be formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 138 may have a single-layer structure or a stacked structure. For example, a gate insulating layer 138 made of non-silicon oxynitride can be formed by a plasma CVD method using silane (SiH4), oxygen, and nitrogen as raw material gases. The thickness of the gate insulating layer 138 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less. In the case of a stacked structure, for example, it is preferable to form a stack of a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer.

[0078] Note that an oxide semiconductor that has been i-type or substantially i-type by removing impurities (a highly purified oxide semiconductor) is extremely sensitive to interface states and interface charges. Therefore, when such an oxide semiconductor is used for an oxide semiconductor layer, the interface with the gate insulating layer is important. That is, high quality is required for the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer.

[0079] For example, the high-density plasma CVD method using microwaves (2.45 GHz) is suitable in that it can form a dense gate insulating layer 138 with a high breakdown voltage. By closely contacting the highly purified oxide semiconductor layer with the high-quality gate insulating layer, the interface level can be reduced and the interface characteristics can be improved. Of course, as long as a high-quality insulating layer can be formed as the gate insulating layer, other methods such as sputtering or plasma CVD can be applied even when using a purified oxide semiconductor layer. Also, an insulating layer whose film quality and interface characteristics are modified by heat treatment after formation may be applied. In any case, a gate insulating layer 138 with good film quality should be formed, which can reduce the interface level density with the oxide semiconductor layer and form a good interface. Moreover, in the gate bias thermal stress test (BT test) at 85°C, 2×10 V / cm for 12 hours, if impurities are added to the oxide semiconductor, the bonds between the impurities and the main components of the oxide semiconductor are broken by the strong electric field (B: bias) and high temperature (T: temperature), and the generated unbonded bonds induce the drift of the threshold voltage (Vth).

[0080] On the contrary, by minimizing the impurities in the oxide semiconductor, especially hydrogen and water, and improving the interface characteristics with the gate insulating layer as described above, it is possible to obtain a stable transistor even for the BT test. Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching using a mask is performed.

[0081]

[0082] 6

[0083]

[0082]

[0083]

[0083] The oxide semiconductor layer is processed by a method such as this to form an island-shaped oxide semiconductor layer 140 (see Fig. 5(E)). (See Fig. 5(E).)

[0084] As the oxide semiconductor layer, an In-Ga-Zn-O system, In-Sn-Zn-O system, In-A l-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn -O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn- O system, or Zn-O system oxide semiconductor layer is preferably used. In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using a metal oxide target of an In-Ga-Zn-O system as the oxide semiconductor layer. Note that since crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer, for example, a target containing 2 wt% or more and 10 wt% or less of SiO2 may be used to form the oxide semiconductor layer. Note that since crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer, for example, a target containing 2 wt% or more and 10 wt% or less of SiO2 may be used to form the oxide semiconductor layer. Note that since crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer, for example, a target containing 2 wt% or more and 10 wt% or less of SiO2 may be used to form the oxide semiconductor layer. Note that since crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer, for example, a target containing 2 wt% or more and 10 wt% or less of SiO2 may be used to form the oxide semiconductor layer.

[0085] As a target for producing the oxide semiconductor layer by sputtering, for example, a metal oxide target mainly composed of zinc oxide can be used. Also, a metal oxide target containing In, Ga, and Zn (such as a composition ratio of In2O3:Ga2O3:Zn O = 1:1:1 [mol ratio] etc.) can also be used. Also, as a metal oxide target containing In, Ga, and Zn targets having a composition ratio of In2O3:Ga2O3:ZnO = 1:1:2 [m ol ratio], or In2O3:Ga2O3:ZnO = 1:1:4 [mol ratio] etc. can also be used. The filling rate of the metal oxide target is 90% or more and 10 0% or less, preferably 95% or more (for example, 99.9%). A metal oxide with a high filling rate target etc. may be used. The filling rate of the metal oxide target is 90% or more and 10 0% or less, preferably 95% or more (for example, 99.9%). A metal oxide with a high filling rate By using a target, a dense oxide semiconductor layer is formed.

[0086] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). Preferably, it is a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). Preferably, it is a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less). Preferably, it is a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of several ppm or less (preferably several ppb or less).

[0087] When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. In a film-forming chamber evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms as well) are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film-forming chamber can be reduced.

[0088] As formation conditions, for At a pressure of Pa, a DC power of 0.5 kW, and an oxygen atmosphere (oxygen flow ratio 100%), such conditions can be applied. When using a pulsed DC power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness can be appropriately selected according to the material used.

[0089] Before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering by introducing argon gas to generate plasma and removing the dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, contrary to the normal sputtering where ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that nitrogen, helium, oxygen, etc. can also be used instead of the argon atmosphere.

[0090] For the etching of the above oxide semiconductor layer, either dry etching or wet etching can be used. Of course, both can also be used in combination. Set the etching conditions (etching gas, etching solution, etching time, temperature, etc.) appropriately according to the material so that etching can be performed into the desired shape.

[0091] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, For example, there are chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. Further, gases containing fluorine (fluorine-based gases, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (C HF3), etc.), hydrogen bromide (HBr), oxygen (O2), gases added with noble gases such as helium (He) or argon (Ar), etc. may also be used.

[0092] As the dry etching method, a parallel plate type RIE (Reactive Ion Etch ing) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. The etching conditions (the amount of electric power applied to the coil-type electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) are appropriately set so that etching can be performed into a desired shape. As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (a mixed solution of ammonia, water, and hydrogen peroxide solution), etc. can be used. Further, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may also be used.

[0093] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. By this first heat treatment, dehydration or dehydrogenation of the oxide semiconductor layer can be performed. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400°C or higher and less than the distortion point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere.

[0094] Prevent re-mixing of water and hydrogen without contact.

[0095] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas, or heat radiation. For example, it may be an apparatus that uses an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. For example, as the first heat treatment, the substrate is introduced into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then a GRTA treatment of taking out the substrate from the inert gas is performed. This enables high-temperature heat treatment in a short time. Also, because it is a short-time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0096] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or noble gases (helium, neon, argon, etc.) and free of water, hydrogen, etc. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is used. Since it is a heat treatment for a short time, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0097] In addition, the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or noble gases (helium, neon, argon, etc.) and free of water, hydrogen, etc. For example, it is desirable to perform the heat treatment in an atmosphere that does not contain water, hydrogen, etc. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is , the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0098] When an electric furnace is used for the first heat treatment, the atmosphere can be switched during the cooling of the heat treatment. For example, the atmosphere during the heat treatment can be an inert gas such as nitrogen, or a noble gas atmosphere such as helium, neon, argon, etc., and the atmosphere can be switched during cooling to an atmosphere containing oxygen. As the atmosphere containing oxygen, oxygen gas or a gas mixture of oxygen gas and nitrogen gas can be used. Even when this oxygen-containing atmosphere is used, it is preferable that water, hydrogen, etc. are not contained in the atmosphere. Or, the purity of the oxygen gas and nitrogen gas used is 6N (99.9999%) or more, preferably 7N (99.99999%) or more, ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0099] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, the crystallization rate may be 90% or more, or 80 % or more of a microcrystalline oxide semiconductor layer. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, there may be a case where an amorphous oxide semiconductor layer containing no crystal components is obtained.

[0100] Also, there may be a case where the oxide semiconductor layer has microcrystals (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) mixed in the amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer).

[0101] ​​​Also, by arranging microcrystals in the amorphous material, the electrical characteristics of the oxide semiconductor layer can be changed. This is also possible. For example, when forming an oxide semiconductor layer using a metal oxide target of the In-Ga-Zn-O system, by forming a microcrystalline portion in which the crystal grains of In2Ga2ZnO7 having electrical anisotropy are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. It can be done.

[0102] More specifically, for example, by orienting the c-axis of In2Ga2ZnO7 to be perpendicular to the surface of the oxide semiconductor layer, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved, and the insulation in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Also, such a microcrystalline portion has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0103] Note that the oxide semiconductor layer having the above-described microcrystalline portion can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Also, by using a sputtering target in which the Zn content is smaller than the In or Ga content, it is possible to form it more suitably.

[0104] The first heat treatment for the oxide semiconductor layer 140 can also be performed on the oxide semiconductor layer before processing it into the island-shaped oxide semiconductor layer 140. In that case, after the first heat treatment, the substrate is taken out from the heating device, and a photolithography process is performed.

[0105] Note that since the above heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140, it can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such a dehydration treatment, dehydrogenation The process can be performed at a timing such as after forming the oxide semiconductor layer and then laminating a source electrode or a drain electrode on the oxide semiconductor layer 140, and then forming a protective insulating layer on the source electrode or the drain electrode. Further, such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times. Next, source electrodes or drain electrodes 142a and 142b are formed so as to be in contact with the oxide semiconductor layer 140 (see FIG. 5(F)). The source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer. The conductive layer can be formed by a PVD (Physical Vapor Deposition) method such as a sputtering method or a CVD (Chemical Vapor Deposition) method such as a plasma CVD method. Also, as the material of the conductive layer, an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components can be used. Instead of the above-described materials, a material selected from any one or more of manganese, magnesium, zirconium, beryllium, thorium, and yttrium may be used. Further, a material in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium is singly or plurally combined with aluminum may be used. The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon

[0106]

[0107] ​​ A single-layer structure of a film, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, and the like can be mentioned. Further, an In-Ga-Zn- O-based, In-Sn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-G a-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based , Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, Zn-O-based oxide conductive films can be used. In this case, compared with the material used for the oxide semiconductor layer 140, it is preferable to use a material with a high conductivity or a low resistivity for the oxide conductive film. The conductivity of the oxide conductive film can be increased by increasing the carrier concentration. The carrier concentration of the oxide conductive film can be increased by increasing the hydrogen concentration. Also, the carrier concentration of the oxide conductive film can be increased by increasing the oxygen deficiency.

[0108] Here, for the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light.

[0109] The channel length (L) of the transistor is determined by the distance between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142b. Note that when performing exposure such that the channel length (L) is less than 25 nm, extreme ultraviolet light with a very short wavelength of several nm to several tens of nm is used for the exposure of mask formation. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, design such that the channel length (L) of the transistor formed later is less than 25 nm This is possible, that is, the channel length (L) can be set to 10 nm or more and 1000 nm or less. This is possible and the operating speed of the circuit can be increased. Further, since the off-current value is extremely small, power consumption does not increase.

[0110] Note that when etching the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 140 is not removed. Depending on the materials and etching conditions, in this process, a part of the oxide semiconductor layer 140 may be etched to form an oxide semiconductor layer having a groove (recess ). )

[0111] Also, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or drain electrode 142b. The oxide conductive layer and the conductive layer for forming the source electrode or drain electrode 142a or the source electrode or drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, the low resistance of the source region or drain region can be achieved, and thus the high-speed operation of the transistor can be realized.

[0112] Also, in order to reduce the number of masks used and the number of processes, a resist mask is formed by a multi-tone mask which is an exposure mask having multiple light intensities, and the etching process is performed using this. The resist mask formed using the multi-tone mask has a shape (stepped shape) having multiple thicknesses and can be further deformed by ashing, so different It can be used in a plurality of etching processes for patterning. That is, a single multi-tone By using a mask, a resist mask corresponding to at least two or more different patterns can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0113] Note that after the above process, it is preferable to perform plasma treatment using a gas such as N2O, N2, or Ar. By this plasma treatment, water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0114] Next, without exposing to the atmosphere, a protective insulating layer 144 in contact with a part of the oxide semiconductor layer 140 is formed (see Fig. 5(G)).

[0115] The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness should be at least 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure can be a single-layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300 °C or lower, and the atmosphere is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen.

[0116] If the protective insulating layer 144 contains hydrogen, the intrusion of hydrogen into the oxide semiconductor layer and the influence of hydrogen ​​​​​​​​Oxygen extraction or the like occurs in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer may have its resistance reduced and a parasitic channel may be formed. Therefore, it is important that the protective insulating layer 14 4 contains as little hydrogen as possible and that hydrogen is not used in the formation method.

[0117] Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to ensure that the oxide semiconductor layer 140 and the protective insulating layer 144 do not contain hydrogen, hydroxyl groups, or moisture.

[0118] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump has, for example, compounds containing hydrogen atoms such as hydrogen atoms and compounds containing water (H2 O) removed, so the concentration of impurities contained in the protective insulating layer 144 formed in the film formation chamber can be reduced.

[0119] As the sputtering gas used when forming the protective insulating layer 144, it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed to a concentration of several ppm or less (preferably, several ppb or less).

[0120] Next, it is desirable to perform a second heat treatment (preferably at 20 0 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example , a second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere. When the second heat treatment is performed, traps​​​​ Variations in the electrical characteristics of the transistor can be reduced.

[0121] Also, even if heat treatment is performed in the atmosphere at a temperature of 100°C or higher and 200°C or lower for 1 hour or longer and 30 hours or shorter, it is acceptable. This heat treatment may be performed while maintaining a constant heating temperature, or may be repeated multiple times with a temperature increase from room temperature to a heating temperature of 100°C or higher to 200°C and a temperature decrease from the heating temperature to room temperature. Also, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the second heat treatment, or may be performed before or after the second heat treatment.

[0122] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6(A)). The interlayer insulating layer 146 can be formed using a method such as PVD or CVD. Also, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to planarize its surface by a method such as CMP or etching.

[0123] Next, openings reaching the electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source electrode or drain electrode 142b are formed in the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138, and a conductive layer 148 is formed so as to fill the openings (see FIG. 6(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. Therefore, it can be formed. As for the etching, either wet etching or dry etching can be used. However, from the perspective of microfabrication, using dry etching is preferred. The formation of the conductive layer 148 can be performed using a film formation method such as PVD method or CVD method. The materials that can be used for the formation of the conductive layer 148 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and alloys and compounds (such as nitrides) thereof. Specifically, for example, a titanium film is thinly formed by PVD method in a region including an opening, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to fill the opening. Here, the titanium film formed by PVD method reduces the oxide film at the interface and

[0124] has a function of reducing the contact resistance with the lower electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source electrode or drain electrode 142b). In addition, the subsequently formed titanium nitride film has a barrier function of suppressing the diffusion of the conductive material. Also, after forming a barrier film made of titanium or titanium nitride, a copper film may be formed by electroplating. After forming the conductive layer 148, a part of the conductive layer 148 is removed using methods such as etching or CMP to expose the interlayer insulating layer 146, and electrodes 150a, 150b, 150c, 150d, and 150e are formed (see FIG. 6(C)). Note that a part of the above-mentioned conductive layer 148 is removed to form electrodes 150a, 150b, 150c, 150d, and

[0125] 150e. (See FIG. 6(C)). After forming the conductive layer 148, a part of the conductive layer 148 is removed using methods such as etching or CMP to expose the interlayer insulating layer 146, and electrodes 150a, 150b, 150c, 150d, and 150e are formed (see FIG. 6(C)). Note that a part of the above-mentioned conductive layer 148 is removed to form electrodes 150a, 150b, 150c, 150d, and 150e. (See FIG. 6(C)). After removing a part of the conductive layer 148, electrodes 150a, 150b, 150c, 150d, and When forming the electrode 150e, it is desirable to process it so that the surface becomes flat. In this way, by planarizing the surfaces of the interlayer insulating layer 146, the electrodes 150a, 150b, 150c, 150d, and the electrode 150e, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes.

[0126] Furthermore, an insulating layer 152 is formed, and openings reaching the electrodes 150a, 150b, 150 c, 150d, and 150e are formed in the insulating layer 152. After forming a conductive layer so as to fill the openings, a part of the conductive layer is removed using methods such as etching or CMP to expose the insulating layer 152, and the electrodes 154a, 154b, 154c, and 154 d are formed (see FIG. 6(D)). This process is the same as when forming the electrodes 150a, etc., so the details are omitted.

[0127] When manufacturing the transistor 402 by the method as described above, the hydrogen concentration of the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 or less, and the off-current of the transistor 402 at room temperature is 1×10 A or less. By applying such an oxide semiconductor layer 140 with a sufficiently reduced hydrogen concentration -13 and high purity, a transistor 40 2 with excellent characteristics can be obtained. Also, a semiconductor device with excellent characteristics having a transistor 421 using a material other than an oxide semiconductor at the bottom and a transistor 402 using an oxide semiconductor at the top can be manufactured. Note that as a semiconductor material that can be a comparison target with an oxide semiconductor, silicon carbide (for example, 4H

[0128] ​-SiC). Oxide semiconductors and 4H-SiC have several commonalities. Carrier density is one example. According to the Fermi-Dirac distribution, the minority carriers of oxide semiconductors are estimated to be on the order of 10 -7 / cm 3 , which is an extremely low value similar to that of 6.7 ×10 -11 / cm 3 in 4H-SiC. Compared with the intrinsic carrier density of silicon (about 1. 4×10 10 / cm 3 ), it can be well understood that the degree is quite different.

[0129] Also, the energy bandgap of oxide semiconductors is 3.0 - 3.5 eV, and the energy bandgap of 4H-S iC is 3.26 eV. Therefore, in terms of being a wide-gap semiconductor, oxide semiconductors and silicon carbide have something in common.

[0130] On the other hand, there are extremely large differences between oxide semiconductors and silicon carbide. That is the pro cess temperature. The semiconductor process using silicon carbide generally requires heat treatment at 1500°C - 2000°C, so it is difficult to form a stacked structure with semiconductor devices using other semiconductor materials . This is because at such high temperatures, semiconductor substrates and semiconductor devices will be destroyed. On the other hand, oxide semiconductors can be fabricated by heat treatment at 300 - 500°C (below the glass transition temperature, at most about 700°C), and semiconductor devices made of oxide semiconductors can be formed on top of integrated circuits formed using other semiconductor materials.

[0131] Also, different from the case of silicon carbide, it is possible to use substrates with low heat resistance such as glass substrates. It has the advantage of being so. Further, in terms of not requiring heat treatment at high temperatures, it has the advantage of being able to sufficiently reduce the energy cost as compared with silicon carbide. It has the advantage of being able to sufficiently reduce the energy cost as compared with silicon carbide.

[0132] In the case of an oxide semiconductor, many physical property studies such as DOS (density of state) have been conducted, but these studies do not include the idea of sufficiently reducing DOS itself. In one aspect of the disclosed invention, by removing water and hydrogen that can cause an increase in DOS from the oxide semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of sufficiently reducing DOS itself. And this enables the production of extremely excellent industrial products. In one aspect of the disclosed invention, by removing water and hydrogen that can cause an increase in DOS from the oxide semiconductor, a highly purified oxide semiconductor is produced. This is based on the idea of sufficiently reducing DOS itself. And this enables the production of extremely excellent industrial products. And this enables the production of extremely excellent industrial products. And this enables the production of extremely excellent industrial products.

[0133] Furthermore, by supplying oxygen to the unbonded hands of metals generated by oxygen deficiency and reducing DOS due to oxygen defects, it is possible to obtain an even more highly purified (type-i) oxide semiconductor. For example, it is possible to form an oxygen-excess oxide film in close contact with the channel formation region and supply oxygen from the oxide film to reduce DOS due to oxygen defects. Furthermore, by supplying oxygen to the unbonded hands of metals generated by oxygen deficiency and reducing DOS due to oxygen defects, it is possible to obtain an even more highly purified (type-i) oxide semiconductor. For example, it is possible to form an oxygen-excess oxide film in close contact with the channel formation region and supply oxygen from the oxide film to reduce DOS due to oxygen defects. For example, it is possible to form an oxygen-excess oxide film in close contact with the channel formation region and supply oxygen from the oxide film to reduce DOS due to oxygen defects.

[0134] Defects in the oxide semiconductor are considered to be caused by levels of 0.1 to 0.2 eV below the conduction band due to excess hydrogen and deep levels due to oxygen deficiency. In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and sufficiently supplying oxygen is considered to be correct. Defects in the oxide semiconductor are considered to be caused by levels of 0.1 to 0.2 eV below the conduction band due to excess hydrogen and deep levels due to oxygen deficiency. In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and sufficiently supplying oxygen is considered to be correct. In order to eliminate these defects, the technical idea of thoroughly removing hydrogen and sufficiently supplying oxygen is considered to be correct.

[0135] Also, although the oxide semiconductor is generally of the n-type, in one aspect of the disclosed invention, by removing impurities, particularly water and hydrogen, type-i conversion is realized. In this regard, like silicon and the like Also, although the oxide semiconductor is generally of the n-type, in one aspect of the disclosed invention, by removing impurities, particularly water and hydrogen, type-i conversion is realized. It can be said that it does not involve i - type conversion by adding impurities, but rather includes a novel technical concept.

[0136] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of transistors using oxide semiconductors will be described with reference to FIGS. 7 to 10. In the following description, an ideal situation is assumed for ease of understanding, and not all of it reflects the actual situation. Also, it should be noted that the following description is merely a consideration and does not affect the validity of the invention.

[0137] FIG. 7 is a cross - sectional view of an inverted staggered - type transistor (thin - film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI) on a gate electrode (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. An insulating layer is provided so as to cover the source electrode (S) and the drain electrode (D).

[0138] FIG. 8 shows an energy - band diagram (schematic diagram) of the A - A' cross - section in FIG. 7. Also, the black circles (●) in FIG. 8 represent electrons, and the white circles (○) represent holes, each having a charge (-q, +q). After applying a positive voltage (V >0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V D =0), and the solid line indicates the case where a positive voltage (V >0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, carriers (electrons) are not injected from the electrode to the oxide - semiconductor side, indicating an off state where no current flows. G G On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, indicating an on state where current flows. ​​​​​​​​

[0139] Figure 9 shows the energy band diagram (schematic diagram) in the cross section of B-B’ in Figure 7. Figure 9(A) shows the on state in which carriers (electrons) flow between the source electrode and the drain electrode with a positive voltage (V G > 0) applied to the gate electrode (GE1). Figure 9(B) shows the off state (a state in which minority carriers do not flow) when a negative voltage (V <0) is applied to the gate electrode (GE1). G

[0140] Figure 10 shows the relationship M between the vacuum level, the work function (φ ) of the metal, and the electron affinity (χ) of the oxide semiconductor.

[0141] At room temperature, electrons in the metal are degenerate, and the Fermi level is located within the conduction band.

[0142] On the other hand, a conventional oxide semiconductor is n-type, and its Fermi level (E F ) is located closer to the conduction band, away from the intrinsic Fermi level (E ) located at the center of the band gap. Note that i it is known that in the oxide semiconductor, a part of hydrogen acts as a donor and is one of the factors for n-type conversion.

[0143] In contrast, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor for n-type conversion, from the oxide semiconductor, and highly purifies it so that elements (impurity elements) other than the main components of the oxide semiconductor are not contained as much as possible, thereby making it intrinsic (i-type) or attempting to make it intrinsic.

[0144] That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. ​​​​​​By doing so, it is characterized by obtaining a highly purified type i (intrinsic semiconductor) or approaching it. As a result, the Fermi level (E F ) can be made comparable to the intrinsic Fermi level (E i ). This can be achieved.

[0145] The band gap (E g ) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4.3 V. The work function of titanium (Ti) constituting the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons. At this time, electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor), as shown in Fig. 9(A).

[0146] As shown in Fig. 9(A), electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor). At this time, electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor).

[0147] Also, as shown in Fig. 9(B), when a negative potential is applied to the gate electrode (GE1), the number of holes, which are minority carriers, is substantially zero, so the current approaches a value infinitely close to zero. Since the number of holes, which are minority carriers, is substantially zero, the current approaches a value infinitely close to zero. This becomes the case.

[0148] By highly purifying the oxide semiconductor so that elements other than the main component (impurity elements) are not contained as much as possible, it becomes intrinsic (type i) or substantially intrinsic. Therefore, the interface characteristics with the gate insulating layer become important. For this reason, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. By highly purifying the oxide semiconductor so that elements other than the main component (impurity elements) are not contained as much as possible, it becomes intrinsic (type i) or substantially intrinsic. Therefore, the interface characteristics with the gate insulating layer become important. For this reason, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. By highly purifying the oxide semiconductor so that elements other than the main component (impurity elements) are not contained as much as possible, it becomes intrinsic (type i) or substantially intrinsic. Therefore, the interface characteristics with the gate insulating layer become important. For this reason, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used.

[0149] While purifying the oxide semiconductor to high purity, the interface between the oxide semiconductor and the gate insulating layer is made good. By doing so, for example, when the channel width W of the transistor is 1 × 10 4 μm and the channel length L is 3 μm, an off-current of 10 -13 A or less and a subthreshold swing value (S value) of 0.1 V / dec. (thickness of the gate insulating layer: 100 nm) can be realized.

[0150] In this way, by purifying to high purity so that elements (impurity elements) other than the main component of the oxide semiconductor are not contained as much as possible, the operation of the transistor can be made good.

[0151] <Hot carrier degradation resistance of a transistor using an oxide semiconductor> Next, the hot carrier degradation resistance of a transistor using an oxide semiconductor will be described with reference to FIGS. 11 to 13. In the following description, an ideal situation is assumed for ease of understanding, and not all of it reflects the actual situation. Also, it should be noted that the following description is only a consideration.

[0152] The main causes of hot carrier degradation are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). In the following, for simplicity, only electrons are considered.

[0153] CHE injection refers to a phenomenon in which electrons having energy higher than the barrier of the gate insulating layer in the semiconductor layer are injected into the gate insulating layer or the like. The energy is imparted to the electrons by accelerating the electrons in a low electric field.

[0154] DAHC injection refers to the phenomenon in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into a gate insulating layer or the like. The difference between DAHC injection and CHE injection lies in whether or not it is accompanied by avalanche breakdown due to impact ionization. In DAHC injection, electrons with kinetic energy equal to or greater than the band gap of the semiconductor are required. The difference between DAHC injection and CHE injection lies in whether or not it is accompanied by avalanche breakdown due to impact ionization. In DAHC injection, electrons with kinetic energy equal to or greater than the band gap of the semiconductor are required.

[0155] Figures 11 and 12 show the energies required for various hot carrier injections estimated from the band structures of silicon (Si) and an In-Ga-Zn-O-based oxide semiconductor (IGZO). In Figures 11 and 12, the left represents CHE injection and the right represents DAHC injection. Figures 11 and 12 show the energies required for various hot carrier injections estimated from the band structures of silicon (Si) and an In-Ga-Zn-O-based oxide semiconductor (IGZO). In Figures 11 and 12, the left represents CHE injection and the right represents DAHC injection.

[0156] In silicon, degradation due to DAHC injection is more serious than that due to CHE injection. This is because the carriers (such as electrons) that are accelerated without collision in silicon are very few, while silicon has a small band gap and is prone to avalanche breakdown. The number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases and easily exceeds the probability of CHE injection. This is because the carriers (such as electrons) that are accelerated without collision in silicon are very few, while silicon has a small band gap and is prone to avalanche breakdown. The number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases and easily exceeds the probability of CHE injection.

[0157] In an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not very different from that in the case of silicon, and its probability is still low. Also, the energy required for DAHC injection is about the same as that required for CHE injection due to the width of the band gap. In an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not very different from that in the case of silicon, and its probability is still low. Also, the energy required for DAHC injection is about the same as that required for CHE injection due to the width of the band gap.

[0158] That is, the probabilities of both CHE injection and DAHC injection are low, and the resistance to hot carrier degradation is high compared to silicon. That is, the probabilities of both CHE injection and DAHC injection are low, and the resistance to hot carrier degradation is high compared to silicon.

[0159] ​​​Incidentally, the bandgap of the In-Ga-Zn-O-based oxide semiconductor is comparable to that of silicon carbide (SiC), which is attracting attention as a high breakdown voltage material. Figure 13 shows the energy required for various hot carrier injections for 4H-SiC. Regarding CHE injection, the threshold of the In-Ga- Zn-O-based oxide semiconductor is slightly higher, which is advantageous.

[0160] As described above, it can be seen that the In-Ga-Zn-O-based oxide semiconductor has very high resistance to hot carrier degradation and source-drain breakdown compared to silicon. Also, it can be said that a breakdown voltage comparable to that of silicon carbide can be obtained.

[0161] <Short-channel effect in a transistor using an oxide semiconductor> Next, the short-channel effect in a transistor using an oxide semiconductor will be described with reference to FIGS. 14 and 15. In the following description, an ideal situation is assumed for ease of understanding, but not all of it reflects the actual situation. Also, it should be noted that the following description is only a consideration.

[0162] The short-channel effect refers to the deterioration of electrical characteristics that becomes apparent as the transistor is miniaturized (the channel length (L) is reduced). The short-channel effect is caused by the effect of the drain reaching the source. Specific examples of the short-channel effect include a decrease in the threshold voltage, an increase in the S value, and an increase in the leakage current.

[0163] Here, device simulation was used to verify the structure that can suppress the short-channel effect. Specifically, the carrier concentration and the thickness of the oxide semiconductor layer were varied. ​​​​​Four types of models were prepared to examine the relationship between the channel length (L) and the threshold voltage (Vth). As the models, transistors with a bottom gate structure were employed, and the carrier concentration of the oxide semiconductor was set to either 1.7×10 / cm -8 or 1.0×10 3 / cm 15 and the thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. Note that an In-Ga-Zn-O-based oxide semiconductor was used as the oxide semiconductor, and a silicon oxynitride film with a thickness of 100 nm was employed as the gate insulating layer. The bandgap of the oxide semiconductor was assumed to be 3.15 eV, the electron affinity was assumed to be 4.3 eV, the relative permittivity was assumed to be 15, and the electron mobility was assumed to be 10 cm 3 / Vs. The relative permittivity of the silicon oxynitride film was assumed to be 4.0. The device simulation software "Atlas" manufactured by Silvaco was used for the calculations. Note that there is no significant difference in the calculation results between the top gate structure and the bottom gate structure. The calculation results are shown in FIGS. 14 and 15. FIG. 14 shows the case where the carrier concentration is 1.7×10 / cm and FIG. 15 shows the case where the carrier concentration is 1.0×10 2 / cm . FIGS. 14 and 15 show the change amount (Δ Vth) of the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm with a transistor having a channel length (L) of 10 μm as a reference. As shown in FIG. 14, when the carrier concentration of the oxide semiconductor is 1.7×1 0

[0164] / cm and the thickness of the oxide semiconductor layer is 1 μm, the change amount of the threshold voltage

[0165] -8 / c m 3 and FIG. 15 shows the case where the carrier concentration is 1.0×10 15 / cm 3 . In FIGS. 14 and 15, with a transistor having a channel length (L) of 10 μm as a reference, the change amount (Δ Vth) of the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm is shown. As shown in FIG. 14, when the carrier concentration of the oxide semiconductor is 1.7×1 0 / cm -8 and the thickness of the oxide semiconductor layer is 1 μm, the change amount of the threshold voltage 3 (ΔVth) was -3.6V. Also, as shown in FIG. 14, the carrier concentration of the oxide semiconductor was 1.7×10 -8 / cm 3 . When the thickness of the oxide semiconductor layer was 30nm, the change amount of the threshold voltage (ΔVth) was -0.2V. Also, as shown in FIG. 15, the carrier concentration of the oxide semiconductor was 1.0×10 15 / cm 3 . When the thickness of the oxide semiconductor layer was 1μm, the change amount of the threshold voltage (ΔVth) was -3.6V. Also, as shown in FIG. 15, the carrier concentration of the oxide semiconductor was 1.0×10 15 / cm 3 . When the thickness of the oxide semiconductor layer was 30nm, the change amount of the threshold voltage (ΔVth) was -0.2 V. The results indicate that in a transistor using an oxide semiconductor, the short-channel effect can be suppressed by reducing the thickness of the oxide semiconductor layer. For example, when the channel length (L) is about 1μm, even if the oxide semiconductor layer has a sufficiently high carrier concentration , if its thickness is about 30nm, it is understood that the short-channel effect can be sufficiently suppressed.

[0166] <Carrier Concentration> The technical idea of the disclosed invention is to make the carrier concentration in the oxide semiconductor layer sufficiently low and approach the intrinsic (i-type) as much as possible. Hereinafter, the method for obtaining the carrier concentration and the actually measured carrier concentration will be described with reference to FIGS. 16 and 17.

[0167] First, the method for obtaining the carrier concentration will be briefly described. The carrier concentration is obtained by fabricating a MOS capacitor and evaluating the result of C-V measurement (C-V characteristics) of the MOS capacitor. It is possible to do so.

[0168] More specifically, a C-V characteristic in which the relationship between the gate voltage Vg and the capacitance C of the MOS capacitor is plotted is obtained, and from the C-V characteristic, a graph representing the relationship between the gate voltage Vg and (1 / C) is obtained. In the graph, the differential value of (1 / C) in the weak inversion region is obtained, and by substituting the differential value into Equation (1), the magnitude of the carrier concentration N 2 is obtained. In Equation (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor. is obtained. In the graph, the differential value of (1 / C) in the weak inversion region is obtained, and by substituting the differential value into Equation (1), the magnitude of the carrier concentration N 2 is obtained. The differential value is obtained, and by substituting the differential value into Equation (1), the magnitude of the carrier concentration N is obtained. By substituting the differential value into Equation (1), the magnitude of the carrier concentration N d is obtained. Note that in Equation (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor. is obtained.

[0169]

Equation

[0170] Next, the carrier concentration actually measured using the above method will be described. For the measurement, a titanium film was formed on a glass substrate with a thickness of 300 nm, a titanium nitride film was formed on the titanium film with a thickness of 100 nm, an oxide semiconductor layer using an In-Ga-Zn-O-based oxide semiconductor was formed on the titanium nitride film with a thickness of 2 μm, a silicon oxynitride film was formed on the oxide semiconductor layer with a thickness of 300 n m, and a silver film was formed on the silicon oxynitride film with a thickness of 300 nm (MOS capacitor) was used. The oxide semiconductor layer was formed by sputtering using a metal oxide target containing In, Ga, and Zn (In:Ga:Zn = 1:1:0.5 [atom%]). In addition, the formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm): 15 (sccm)). m, and a silver film was formed on the silicon oxynitride film with a thickness of 300 nm (MOS capacitor) was used. The oxide semiconductor layer was formed by sputtering using a metal oxide target containing In, Ga, and Zn (In:Ga:Zn = 1:1:0.5 [atom%]). In addition, the formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm): 15 (sccm)). In addition, the formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm): 15 (sccm)). In addition, the formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm): 15 (sccm)). In addition, the formation atmosphere of the oxide semiconductor layer was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm): 15 (sccm)).

[0171] Fig. 16 shows the C-V characteristics, and Fig. 17 shows the relationship between Vg and (1 / C). 2 respectively. In the weak inversion region of Fig. 17, the carrier 2 concentration obtained using Equation (1) from the differential value of (1 / C) is 6.0×10 10 / cm 3 .

[0172] Thus, by using an i-type or substantially i-type oxide semiconductor (for example, the carrier concentration is less than 1×10 12 / cm 3 , desirably, 1×10 11 / cm 3 or less), it is possible to obtain a transistor with extremely excellent off-current characteristics.

[0173] By using the non-volatile latch circuit according to this embodiment and using an oxide semiconductor as the semiconductor material constituting the channel formation region as the switching element of the data holding unit, it is possible to realize a non-volatile latch circuit that has a wide temperature operating range and operates stably even at high temperatures, and the stored logical state does not disappear even when the power is turned off, or a latch circuit incorporating a data holding unit with a sufficiently long refresh period. Since data writing is performed by switching the transistor , there is substantially no limit to the number of rewrite times. Also, the write voltage is about the threshold voltage of the transistor, and it is possible to operate at a low voltage. For example , the operating voltage can be set to 1 V or less. Also, since the charge accumulated in the capacitance of the data holding unit is directly held as data, it is less affected by variations, and data reading can be easily performed.

[0174] ​​​By using the above non-volatile latch circuit, various logic circuits can be realized. For example, power consumption can be reduced by turning off the power supply of unused blocks. Also, since the logic state is stored even when the power supply is turned off, system startup when the power supply is turned on and system shutdown when the power supply is turned off can be performed quickly and with low power. This is possible.

[0175] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0176] (Embodiment 2) This embodiment will describe an example different from FIG. 1 with reference to FIG. 18 regarding the configuration of a non-volatile latch circuit which is an aspect of the disclosed invention. FIG. 18(A) shows the configuration of a non-volatile latch circuit 400 having a latch section 411 and a data holding section 401 for holding the data of the latch section. FIG. 18(B) shows the configuration of the data holding section 401. FIG. 18 is an example in which the configuration of the data holding section 401 is different from that of FIG. 1. Specifically, it is an example in which the capacity of the data holding section 401 (capacity 404 in FIG. 1) is not provided. Since the other configurations are the same as those in FIG. 1, the description thereof is omitted. The configuration of the transistor 402 is the same as that in Embodiment 1.

[0177] FIG. 18 is an example in which the configuration of the data holding section 401 is different from that of FIG. 1. Specifically, it is an example in which the capacity of the data holding section 401 (capacity 404 in FIG. 1) is not provided. Since the other configurations are the same as those in FIG. 1, the description thereof is omitted. The configuration of the transistor 402 is the same as that in Embodiment 1. The data holding section 401 uses a transistor 402 made of an oxide semiconductor as a semiconductor material constituting the channel formation region as a switching element. Also, it has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402.

[0178] The data holding section 401 uses a transistor 402 made of an oxide semiconductor as a semiconductor material constituting the channel formation region as a switching element. Also, it has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402.

[0179] One of the source electrode and the drain electrode of this transistor 402 is supplied with an output signal and is electrically connected to the wiring 415. Also, the output of the inverter 403 is electrically connected to the wiring 414 to which an input signal is supplied and is electrically connected to the wiring 414. The inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is electrically connected to the high-level power supply voltage VDD. The source electrode of the transistor 421 is electrically connected to the low-level power supply voltage VSS of the power supply

[0180] This embodiment has a configuration without a capacitor connected to the node S. In this case, charge is accumulated in the gate capacitance of the transistors constituting the inverter 403. Here, preferably the gate capacitance of the transistor 421 included in the inverter 403 can be made larger than the gate capacitance of the transistor 420 included in the inverter 403. The size of the gate capacitance can be controlled by the channel length L, channel width W, film thickness of the gate insulating film, and dielectric constant of the transistor. By doing so, the ratio of the capacitance formed between VSS and the node S among the gate capacitances of the transistors 420 and 421 increases, and the potentials of the gate electrodes of the transistors 420 and 421 are less likely to be affected by fluctuations in VDD which is preferable and is thus preferable and is thus preferable and is thus preferable and is thus preferable and is thus preferable

[0181] The inverter 403 is not limited to the configuration shown in FIG. 18(B). For example, as shown in FIG. 2(A), it may be composed of N-channel transistors, or may have a configuration with a buffer at the output or may have a configuration with a buffer at the output or may have a configuration with a buffer at the output. Also, a sense amplifier circuit may be used instead of the inverter 403. For example, as shown in FIG. 2 A differential amplification type sense amplifier circuit as shown in (B) may be used. In any case, it is important that the input terminal is in a floating state (high impedance state). Also , in the circuit shown in FIG. 2(A), the input charge is stored in the gate capacitance of transistor 421. Also, in the circuit shown in FIG. 2(B), the input charge is stored in the gate capacitance of transistor 421. In the circuits shown in FIGS. 2(A) and 2(B), since these gate capacitances are mainly configured between VSS and node S, it is preferable because the potential of the input terminal is less likely to be affected by the fluctuation of VDD.

[0182] The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch section 411 to the gate capacitance of the inverter 403 in the data holding section 401. Also, the transistor 402 has a function of holding the data written to the gate capacitance of the inverter 403 in the data holding section 401.

[0183] The operations of writing, holding, reading, and rewriting the data held in the latch section 411 to the data holding section 401 will be described. First, a potential at which the transistor 402 turns on is supplied to the gate electrode of the transistor 402 to turn on the transistor 402. As a result, the data held in the latch section, that is, the potential of the wiring 4 15 where the output signal is applied is applied to the input terminal of the inverter 403. As a result, charges corresponding to the potential of the wiring 415 are stored in the gate capacitance of the inverter 403 (writing). Then, the potential of the gate electrode of the transistor 402 is set to a potential at which the transistor 402 turns off. , by turning off the transistor 402, the charge stored in the gate capacitance of the inverter 403 is retained (holding). By reading the potential of the input terminal of the inverter 403, data can be read (reading). Data rewriting can be performed in the same manner as the above-described data writing and holding. The charge stored in the gate capacitance of the inverter 403 is retained (holding). By reading the potential of the input terminal of the inverter 403, data can be read (reading). Data rewriting can be performed in the same manner as the above-described data writing and holding. By reading the potential of the input terminal of the inverter 403, data can be read (reading). Data rewriting can be performed in the same manner as the above-described data writing and holding. Data rewriting can be performed in the same manner as the above-described data writing and holding.

[0184] Using the non-volatile latch circuit according to this embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, thereby realizing a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and a logical state stored even when the power is turned off is not lost, or a latch circuit incorporating a data holding unit having a sufficiently long refresh period. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Using the non-volatile latch circuit according to this embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, thereby realizing a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and a logical state stored even when the power is turned off is not lost, or a latch circuit incorporating a data holding unit having a sufficiently long refresh period. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Using the non-volatile latch circuit according to this embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, thereby realizing a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and a logical state stored even when the power is turned off is not lost, or a latch circuit incorporating a data holding unit having a sufficiently long refresh period. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Using the non-volatile latch circuit according to this embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, thereby realizing a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and a logical state stored even when the power is turned off is not lost, or a latch circuit incorporating a data holding unit having a sufficiently long refresh period. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Using the non-volatile latch circuit according to this embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, thereby realizing a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and a logical state stored even when the power is turned off is not lost, or a latch circuit incorporating a data holding unit having a sufficiently long refresh period. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Since data writing is performed by switching the transistor, there is substantially no limit on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. For example, the operation voltage can be set to 1V or less. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Further, since the charge stored in the capacitance of the data holding unit is held as data as it is, it is hardly affected by variations, and data reading can be easily performed.

[0185] By using the non-volatile latch circuit, various logic circuits can be realized. For example, power consumption can be reduced by turning off the power of unused blocks. Further, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed at high speed and with low power consumption. By using the non-volatile latch circuit, various logic circuits can be realized. For example, power consumption can be reduced by turning off the power of unused blocks. Further, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed at high speed and with low power consumption. For example, power consumption can be reduced by turning off the power of unused blocks. Further, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed at high speed and with low power consumption. Further, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed at high speed and with low power consumption. Further, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed at high speed and with low power consumption.

[0186] This embodiment can be freely combined with other embodiments.

[0187] (Embodiment 3) This embodiment will describe the configuration and operation of a non-volatile latch circuit, which is an aspect of the disclosed invention, with reference to FIGS. 19 and 1. with reference to FIGS. 19 and 1.

[0188] FIG. 19(A) shows the configuration of a non-volatile latch circuit 400 having a latch section 411 and a data holding section 401 for holding the data of the latch section. FIG. 19(B) shows an example of a timing chart of the non-volatile latch circuit 400. FIG. 19(A) is an example specifically showing the configuration of the latch section 411 in FIG. 1(A). FIG. 19 (A) is an example in which an inverter is used as the first element and an inverter is used as the second element in the configuration of the latch section 411 in FIG. 1(A). The configuration of the transistor 402 is the same as that in Embodiment 1.

[0189] FIG. 19(A) is an example specifically showing the configuration of the latch section 411 in FIG. 1(A). FIG. 19 (A) is an example in which an inverter is used as the first element and an inverter is used as the second element in the configuration of the latch section 411 in FIG. 1(A). The configuration of the transistor 402 is the same as that in Embodiment 1. using an inverter as the first element and an inverter as the second element. The configuration of the transistor 402 is the same as that in Embodiment 1. The configuration of the transistor 402 is the same as that in Embodiment 1.

[0190] The latch section 411 has an inverter 412 and an inverter 413. The output of the inverter 4 12 is electrically connected to the input of the inverter 413, and the output of the inverter 413 is electrically connected to the input of the inverter 412, forming a loop structure. The latch section 41 1 also has a switch 431 and a switch 432, and the output of the inverter 413 is electrically connected to the input of the inverter 412 via the switch 432. The input of the inverter 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit is applied via the switch 431. The output of the inverter 412 is the output signal of the latch circuit. The output of the inverter 413 is electrically connected to the input of the inverter 412 via the switch 432.

[0191] The input of the inverter 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit is applied via the switch 431. The output of the inverter 412 is the output signal of the latch circuit. It is electrically connected to wiring 415 to which a signal is supplied.

[0192] The data holding unit 401 uses an oxide semiconductor as the semiconductor material constituting the channel formation region and uses the transistor 402 as a switching element. Also, in addition to the source electrode and the drain electrode of this transistor 4 02, it has a capacitor 404 and an inverter 403 that are electrically connected.

[0193] One of the source electrode and the drain electrode of this transistor 402 is electrically connected to the wiring 415 to which an output signal is supplied. Also, the output of the inverter 403 is electrically connected to the wiring 414 to which an input signal is supplied via the switch 405 and is electrically connected to the wiring 414 to which an input signal is supplied via the switch 405. and is electrically connected to the wiring 414 to which an input signal is supplied via the switch 405.

[0194] The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch unit 411 into the capacitor 404 of the data holding unit 401 and the gate capacitance of the inverter 403. Also, the transistor 402 has a function of holding the data written into the capacitor 404 of the data holding unit 401 and the gate capacitance of the inverter 403. The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch unit 411 into the capacitor 404 of the data holding unit 401 and the gate capacitance of the inverter 403. The transistor 402 using this oxide semiconductor has a function of writing the data held in the latch unit 411 into the capacitor 404 of the data holding unit 401 and the gate capacitance of the inverter 403. The transistor 402 using this oxide semiconductor has a function of holding the data written into the capacitor 404 of the data holding unit 401 and the gate capacitance of the inverter 403.

[0195] The potential of the input signal IN is supplied to the wiring 414 from the previous-stage circuit. The potential of the wiring 415 is supplied to the subsequent-stage circuit as the output signal OUT. The potential of the clock signal φ1 is supplied to the switch 431. When a high-level potential is supplied to the clock signal φ1, the switch 431 becomes on. The potential of the clock signal φ2 is supplied to the switch 432. When a high-level potential is supplied to the clock signal φ2, the switch 432 becomes on. The potential of the control signal ST is supplied to the gate of the transistor 4 02. The control signal ST is a high-level potential φ2, the switch 432 becomes on. The potential of the control signal ST is supplied to the gate of the transistor 4 02. The control signal ST is a high-level potential When given, the transistor 402 has a potential at which it turns on. The control signal LD is applied to the switch 405. The control signal LD has a potential at which the switch 405 turns on when a high-level potential is applied. During normal operation, the clock signal φ2 has a signal obtained by inverting the clock signal φ1. Here, an example is shown where the transistor and the switch turn on when the control signal and the clock signal are at a high level. The potential of the control signal LD is applied to the switch 405. When the control signal LD is at a high level, the switch 405 has a potential at which it turns on. During normal operation, the clock signal φ2 has a signal obtained by inverting the clock signal φ1. During normal operation, the clock signal φ2 has a signal obtained by inverting the clock signal φ1. Here, an example is shown where the transistor and the switch turn on when the control signal and the clock signal are at a high level. Here, an example is shown where the transistor and the switch turn on when the control signal and the clock signal are at a high level.

[0196] The inverter 403 included in the data holding unit 401, and the inverters 412 and 413 included in the latch unit 411 are each supplied with the high-level power supply voltage VDD and the low-level power supply voltage VSS. The inverter 403 included in the data holding unit 401, and the inverters 412 and 413 included in the latch unit 411 are each supplied with the high-level power supply voltage VDD and the low-level power supply voltage VSS. The inverter 403 included in the data holding unit 401, and the inverters 412 and 413 included in the latch unit 411 are each supplied with the high-level power supply voltage VDD and the low-level power supply voltage VSS.

[0197] Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied. Next, FIG. 19(B) shows an example of a timing chart of the potentials of the input signal IN, the output signal OUT, the control signal ST, the control signal LD, the clock signal φ1, and the clock signal φ2 during the operating period (operation period) and the stop period (non-operation period) of the non-volatile latch circuit 400. Also shown are the potential of the node S of the data holding unit 401 and the power supply voltage VDD. The node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403. A fixed potential is applied to the other electrode of the capacitor 404. For example, a ground potential is applied.

[0198] In FIG. 19(B), periods a, b, d, and e are operation periods, and period c is a non-operation period. Periods a and e are normal operation periods, and the clock signal φ1 and the clock signal φ2 are alternately given high-level or low-level potentials. Period b is a preparation period before the non-operation period. Period b is also called a falling period. Period d is the power supply voltage VDD In FIG. 19(B), periods a, b, d, and e are operation periods, and period c is a non-operation period. Periods a and e are normal operation periods, and the clock signal φ1 and the clock signal φ2 are alternately given high-level or low-level potentials. Period b is a preparation period before the non-operation period. Period b is also called a falling period. Period d is the power supply voltage VDD In FIG. 19(B), periods a, b, d, and e are operation periods, and period c is a non-operation period. Periods a and e are normal operation periods, and the clock signal φ1 and the clock signal φ2 are alternately given high-level or low-level potentials. Period b is a preparation period before the non-operation period. Period b is also called a falling period. Period d is the power supply voltage VDD In FIG. 19(B), periods a, b, d, and e are operation periods, and period c is a non-operation period. Periods a and e are normal operation periods, and the clock signal φ1 and the clock signal φ2 are alternately given high-level or low-level potentials. Period b is a preparation period before the non-operation period. Period b is also called a falling period. Period d is the power supply voltage VDD After it is turned on, it is a preparation period until it enters the normal operation period. Period d is also called the startup period. It is said.

[0199] During the normal operation period (period a), when a high-level potential is applied to the clock signal φ1 and a low-level potential is applied to the clock signal φ2, the switch 432 turns off and the inverter loop is disconnected. At the same time, the switch 431 turns on, and the potential of the input signal is input to the inverter 412. The potential of the input signal is inverted by the inverter 412 and given as the output signal OUT to the subsequent circuit. When a high-level potential is applied to the clock signal φ1, if the potential of the input signal is high level, an output signal with a low-level potential is obtained. When a high-level potential is applied to the clock signal φ1, if the potential of the input signal is low level, an output signal with a high-level potential is obtained. When a low-level potential is applied to the clock signal φ1 and a high-level potential is applied to the clock signal φ2, the switch 431 turns off and the switch 432 turns on to form an inverter loop, and the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the input signal is input to the inverter 412. The potential of the input signal is inverted by the inverter 412 and given as the output signal OUT to the subsequent circuit. When a high-level potential is applied to the clock signal φ1, if the potential of the input signal is high level, an output signal with a low-level potential is obtained. When a high-level potential is applied to the clock signal φ1, if the potential of the input signal is low level, an output signal with a high-level potential is obtained. When a low-level potential is applied to the clock signal φ1 and a high-level potential is applied to the clock signal φ2, the switch 431 turns off and the switch 432 turns on to form an inverter loop, and the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off,

[0200] Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. Next, in the preparation period (period b) before the non-operation period, when a potential at which the transistor 402 turns on is given to the control signal ST, the transistor 402 turns on, and the potential of the output signal is given to the node S (writing). If the potential of the output signal is high level, the potential of the node S becomes high level. Then, when the control signal ST is given a potential at which the transistor 402 turns off, the potential of the output signal OUT is held (data is latched). During the normal operation period, the control signal ST is not given a potential at which the transistor 402 turns on. The node S has the potential that it has held before. Here, it is taken as an indeterminate value. A potential is applied, transistor 402 turns off, and the potential of node S becomes floating. As a result, the potential written to node S is held as it is (holding). Note that the clock signal φ2 and the clock signal φ1 only need to hold the potential at the end of period a. Alternatively, the clock signal φ2 can be fixed at a high level, the clock signal φ1 can be fixed at a low level, and the data at the end of period a can be latched. The control signal ST may be given a potential that turns on transistor 40 2 after the start of period b, or a potential that turns on transistor 402 may be given simultaneously with the start of period b.

[0201] Next, during the non-operation period (period c), the power supply is stopped and the power supply voltage VDD decreases. The clock signal φ1, the clock signal φ2, the input signal IN, and the output signal OUT can take any value between VDD - VS S. During this time, the potentials of the control signal ST and the control signal LD are held at a low level. For example, they are held at the ground potential. During the non-operation period (period c), since the potential of node S is in a floating state, the charge accumulated in node S is held as it is (holding). Note that when the power supply voltage VDD decreases, the potential of node S may vary slightly due to the influence of capacitive coupling with the power supply potential. Of course, since the charge accumulated in node S is held, when the power supply voltage VDD is supplied again, it returns to the original potential.

[0202] Next, during the preparation period (period d) until entering the normal operation period after the power supply voltage VDD is turned on, with the clock signal φ2 and the clock signal φ1 fixed at a low level, when a potential that turns on switch 405 is given to the control signal LD, switch 405 turns on. ​ The potential held at node S is inverted by the inverter 403 and applied to the latch section 411. Then, after a potential at which the switch 405 is turned on is applied to the control signal LD, the clock signal φ2 and the clock signal φ1 are given the potential at the end of period a. As a result, the logical state in period d can be returned to the logical state before entering the non - operating period. The control signal LD may be set to a low level before the end of period d, or the potential at which the switch 405 remains on may be maintained until the end.

[0203] Next, in the normal operation period (period e), the clock signal φ1 and the clock signal φ2 are given high - level and low - level potentials, and the normal operation state is entered. At the start of the normal operation period (period e), the clock signal φ1 and the clock signal φ2 may start from the same potential as at the end of the previous normal operation period ( period a), or may start from the state next to the potential at the end of period a.

[0204] The potential of node S is rewritten at the timing when the transistor 402 is turned on by the control signal ST. Therefore, until the timing when the potential at which the transistor 402 is turned on is applied to the control signal ST next, the potential of node S is held as it is.

[0205] Note that in period d, the potential Vc of the other electrode of the capacitor 404 may be a value between VDD and VSS. As a result, a potential taking into account the increment of the potential Vc is applied to node S, and it becomes possible to perform the read operation more stably.

[0206] Using the non - volatile latch circuit according to this embodiment, a semiconductor material constituting the channel formation region ​​​​​​​​A transistor using an oxide semiconductor as a material is used as a switching element of a data holding section By using it, a non-volatile latch circuit having a wide temperature operating range and operating stably even at high temperatures, and storing data even when the power is turned off in which the logical state does not disappear, or a latch circuit incorporating a data holding section with a sufficiently long refresh period can be realized. Since data writing is performed by switching of the transistor there is substantially no limit to the number of rewrites. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example the operating voltage can be set to 1 V or less. Also, since the charge accumulated in the capacitance of the data holding section is held as data as it is, it is hardly affected by variations, and data reading can be easily performed. Since the charge accumulated in the capacitance of the data holding section is held as data as it is, it is hardly affected by variations, and data reading can be easily performed.

[0207] By using the above non-volatile latch circuit, various logic circuits can be realized For example, power consumption can be reduced by turning off the power of unused blocks Also, since the logical state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed quickly and with low power It is possible to do. It is possible to do.

[0208] This embodiment can be freely combined with other embodiments.

[0209] (Embodiment 4) This embodiment describes the configuration and operation of a non-volatile latch circuit, which is an aspect of the disclosed invention, with reference to FIGS. 20 and 18, which are different examples from FIG. 19. FIG. 20(A) shows a latch section 411 and a non-volatile latch having a data holding section 401 for holding the data of the latch section section 411 and a non-volatile latch having a data holding section 401 for holding the data of the latch section It shows the configuration of the latch circuit 400. FIG. 20(B) shows an example of the timing chart of the non-volatile latch circuit 400. It shows an example of the timing chart.

[0210] FIG. 20 shows an example in which the configuration of the data holding unit 401 is different from that in FIG. 19. Specifically, it is an example in which the capacity of the data holding unit (capacity 404 in FIG. 19) is not particularly provided. Since the other configurations are the same as those in FIG. 19, the description is omitted. The capacity of the data holding unit (capacity 404 in FIG. 19) is not particularly provided. Since the other configurations are the same as those in FIG. 19, the description is omitted. Since the other configurations are the same as those in FIG. 19, the description is omitted.

[0211] Also, FIG. 20(A) is an example specifically showing the configuration of the latch unit 411 in FIG. 18(A). FIG. 20(A) is an example in which an inverter is used as the first element and an inverter is used as the second element in the configuration of the latch unit 411 in FIG. 18(A). The configuration of the data holding unit 401 will be described with reference to FIG. 18. The configuration of the transistor 402 is the same as that in Embodiment 1. FIG. 20(A) is an example in which an inverter is used as the first element and an inverter is used as the second element in the configuration of the latch unit 411 in FIG. 18(A). The configuration of the data holding unit 401 will be described with reference to FIG. 18. The configuration of the transistor 402 is the same as that in Embodiment 1. The configuration of the data holding unit 401 will be described with reference to FIG. 18. The configuration of the transistor 402 is the same as that in Embodiment 1. The configuration of the transistor 402 is the same as that in Embodiment 1.

[0212] The data holding unit 401 uses the transistor 402 formed of an oxide semiconductor as the semiconductor material constituting the channel formation region as a switching element. It also has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402. The data holding unit 401 uses the transistor 402 formed of an oxide semiconductor as the semiconductor material constituting the channel formation region as a switching element. It also has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402. The data holding unit 401 uses the transistor 402 formed of an oxide semiconductor as the semiconductor material constituting the channel formation region as a switching element. It also has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402. It has an inverter 403 electrically connected to the other of the source electrode and the drain electrode of this transistor 402.

[0213] One of the source electrode and the drain electrode of this transistor 402 is electrically connected to the wiring 415 to which the output signal is applied. Also, the output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is applied via the switch 405. The configuration of the inverter 403 is as shown in FIG. 18(B), and the inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is at a high level voltage. One of the source electrode and the drain electrode of this transistor 402 is electrically connected to the wiring 415 to which the output signal is applied. Also, the output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is applied via the switch 405. The configuration of the inverter 403 is as shown in FIG. 18(B), and the inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is at a high level voltage. One of the source electrode and the drain electrode of this transistor 402 is electrically connected to the wiring 415 to which the output signal is applied. Also, the output of the inverter 403 is electrically connected to the wiring 414 to which the input signal is applied via the switch 405. The configuration of the inverter 403 is as shown in FIG. 18(B), and the inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is at a high level voltage. The configuration of the inverter 403 is as shown in FIG. 18(B), and the inverter 403 has a transistor 420 and a transistor 421. The configuration of the inverter 403 is as shown in FIG. 18(B), and the inverter 403 has a transistor 420 and a transistor 421. The source electrode of the transistor 420 is at a high level voltage. It is electrically connected to the source voltage VDD. The source electrode of the transistor 421 is electrically connected to the power supply voltage VSS at the low level level.

[0214] This embodiment has a configuration without a capacitor connected to the node S. In this case, charge is accumulated in the gate capacitance of the transistor connected to the input of the inverter 403. Here, preferably, the gate capacitance of the transistor 421 included in the inverter 403 is made larger than the gate capacitance of the transistor 420 included in the inverter 4 03. The magnitude of the gate capacitance can be controlled by factors such as the channel length L, channel width W, film thickness of the gate insulating film, and dielectric constant of the transistor. By doing so, the input capacitance of the inverter 403 is mainly composed of the capacitance between the node S and VSS, and it is preferable because the potential of the input terminal is less affected by the fluctuation of VDD become. The magnitude of the gate capacitance can be controlled by the channel length L, channel width W, film thickness of the gate insulating film, dielectric constant, etc. of the transistor. By doing so, the input capacitance of the inverter 403 is mainly composed of the capacitance between the node S and VSS, and the potential of the input terminal is less affected by the fluctuation of VDD become, which is preferable. become, which is preferable. become, which is preferable.

[0215] The inverter 403 is not limited to the configuration shown in FIG. 18(B). For example, it may be composed of N-channel transistors as shown in FIG. 2(A), or may have a configuration with a buffer provided at the output become. Also, a sense amplifier circuit may be used instead of the inverter 403. For example, a differential amplification type sense amplifier circuit as shown in FIG. 2 (B) may be used. In any case, it is important that the input terminal is in a floating state (high impedance state). Also (B) may be used. In any case, it is important that the input terminal is in a floating state (high impedance state). Also In any case, it is important that the input terminal is in a floating state (high impedance state). Also In the circuit shown in FIG. 2(A), the input charge is accumulated in the gate capacitance of the transistor 421. Also, in the circuit shown in FIG. 2(B), the input charge is accumulated in the gate capacitance of the transistor 421. In the circuits shown in FIGS. 2(A) and 2(B), since these gate capacitances are mainly configured between VSS and the node S, the potential of the input terminal is affected by the fluctuation of VDD accumulated. Also, in the circuit shown in FIG. 2(B), the input charge is accumulated in the gate capacitance of the transistor 421. In the circuits shown in FIGS. 2(A) and 2(B), since these gate capacitances are mainly configured between VSS and the node S, the potential of the input terminal is affected by the fluctuation of VDD accumulated. In the circuits shown in FIGS. 2(A) and 2(B), since these gate capacitances are mainly configured between VSS and the node S, the potential of the input terminal is affected by the fluctuation of VDD receive less influence. This is preferable because it becomes unappealing.

[0216] The transistor 402 using this oxide semiconductor has a function of writing data held in the latch section 411 into the gate capacitance of the inverter 403. Also, the transistor 402 has a function of holding the data written into the gate capacitance of the inverter 403. Yes.

[0217] FIG. 20(B) shows an example of the timing chart of the non-volatile latch circuit 400. FIG. 20 (B)'s timing chart is almost the same as the timing chart of FIG. 19(B), and the description thereof is omitted.

[0218] By using the non-volatile latch circuit according to this embodiment and using a transistor using an oxide semiconductor as a semiconductor material constituting the channel formation region as a switching element of the data holding section, a non-volatile latch circuit having a wide temperature operation range and operating stably even at high temperatures, and in which the stored logical state does not disappear even when the power is turned off, or a latch circuit incorporating a data holding section with a sufficiently long refresh period can be realized. Since the writing of data is performed by the switching of the transistor, there is substantially no limit to the number of rewrite times. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example the operating voltage can be set to 1V or less. Also, since the charge accumulated in the capacitance of the data holding section is held as data as it is, it is less affected by variations, and data reading can be easily performed. Since it is performed by the switching of the transistor, there is substantially no limit to the number of rewrite times. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example the operating voltage can be set to 1V or less. Also, since the charge accumulated in the capacitance of the data holding section is held as data as it is, it is less affected by variations, and data reading can be easily performed.

[0219] By using the above non-volatile latch circuit, various logic circuits can be realized.​ Yes. For example, power consumption can be reduced by turning off the power of unused blocks. Also, since the logic state is memorized even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed quickly and with low power. This is possible.

[0220] This embodiment can be freely combined with other embodiments.

[0221] (Embodiment 5) This embodiment describes the configuration and operation of a non-volatile latch circuit, which is an aspect of the disclosed invention, with reference to FIG. 21, showing an example different from FIG. 19. FIG. 21(A) shows the configuration of the non-volatile latch circuit 400. The configuration of the non-volatile latch circuit 400 is the same as that of FIG. 19(A). FIG. 21(B) shows an example of the timing chart of the non-volatile latch circuit 400.

[0222] In the timing chart shown in FIG. 21(B), during period d after the power supply voltage VDD is supplied again, the transistor 402 is given a potential at which it turns on in the control signal ST. The rising timing at which the control signal ST becomes high level may be after the falling timing from when the control signal LD is high level. Also, the falling timing at which the control signal ST falls may be within the period when the clock signal φ1 and the clock signal φ2 are at the same potential as at the end of period a. During period d, by giving the transistor 402 a potential at which it turns on in the control signal ST, the potential of node S can be refreshed.

[0223] In the timing chart of FIG. 21(B), the timings other than the control signal ST are the same as those in FIG. 19( B), so the description thereof will be omitted.

[0224] By using the non-volatile latch circuit according to this embodiment and using a transistor having an oxide semiconductor as a semiconductor material constituting a channel formation region as a switching element of a data holding unit, a non-volatile latch circuit that has a wide temperature operating range and operates stably even at high temperatures and stores the logical state without disappearing even when the power supply is turned off, or a latch circuit incorporating a data holding unit with a sufficiently long refresh period can be realized. Since the writing of data is performed by switching of the transistor, there is substantially no limitation on the number of rewrites. Further, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operating voltage can be set to 1 V or less. Further, since the charges accumulated in the capacitance of the data holding unit are held as data as they are, the data is hardly affected by variations, and the data can be easily read out.

[0225] By using the above non-volatile latch circuit, various logic circuits can be realized. For example, power consumption can be reduced by turning off the power supply of unused blocks. Further, since the logical state is stored even when the power supply is turned off, system startup when the power supply is turned on and system termination when the power supply is turned off can be performed

[0226]

[0227] quickly and with low power.

[0226] This embodiment can be freely combined with other embodiments.

[0227] (Embodiment 6) This embodiment describes the configuration of a logic circuit having a plurality of non-volatile latch circuits, which is one aspect of the disclosed invention. The configuration of the circuit will be described with reference to FIG. 22.

[0228] FIG. 22 shows the configuration of a logic circuit having two non-volatile latch circuits 400 each having a latch section 411 and a data holding section 401 for holding the data of the latch section. The configuration of the data holding section 401 is the same as that shown in FIG. 1(A) or FIG. 18(A). The configuration of the latch section 411 is an example in which a NAND is used as the first element and a clocked inverter is used as the second element in the configuration of the latch section 411 in FIG. 1(A) or FIG. 18(A).

[0229] The latch section 411 has a NAND 412 and a clocked inverter 413. The output of the NAND 412 is electrically connected to the input of the clocked inverter 413, and the output of the clocked inverter 413 is electrically connected to the input of the NAND 412, forming a loop structure. The latch section 411 also has an analog switch 431. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. The logic circuit shown in FIG. 22 has a non-volatile latch circuit 400a and a non-volatile latch circuit 400b as the above non-volatile latch circuits 400.

[0230] The latch section 411 includes a NAND 412 and a clocked inverter 413. The output of the NAND 412 is electrically connected to the input of the clocked inverter 413, and the output of the clocked inverter 413 is electrically connected to the input of the NAND 412, forming a loop structure. The latch section 411 also includes an analog switch 431. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. The output of the NAND 412 is electrically connected to the input of the clocked inverter 413, and the output of the clocked inverter 413 is electrically connected to the input of the NAND 412, forming a loop structure. The latch section 411 also includes an analog switch 431. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied.

[0231] One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. One of the inputs of the NAND 412 is electrically connected to a wiring 414 to which an input signal of the latch circuit 400 is applied via the analog switch 431. The output of the NAND 412 is electrically connected to a wiring 415 to which an output signal of the latch circuit 400 is applied. The other input of the NAND 412 is electrically connected to a wiring to which a signal RSTB is applied. is applied.

[0232] The logic circuit shown in FIG. 22 includes the non-volatile latch circuit 400 as the non-volatile latch circuit 400a and the non-volatile latch circuit 400b. The non-volatile latch circuit 4 00a is electrically connected to a wiring 414 to which the potential of an input signal is supplied from a circuit in the previous stage. A wiring 415 to which the potential of an output signal of the non-volatile latch circuit 400a is supplied is electrically connected to a wiring 414 to which the potential of an input signal of the non-volatile latch circuit 400b is supplied. The non-volatile latch circuit 400b is electrically connected to a wiring 415 to which the potential of an output signal is supplied to a circuit in the subsequent stage. In the non-volatile latch circuit 400a, a clock signal φ1 and an inverted signal of the clock signal φ1 are supplied to an analog switch 431, and a clock signal φ2 and an inverted signal of the clock signal φ2 are supplied to a clock inverter 413. Further, in the non-volatile latch circuit 400b, a clock signal φ2 and an inverted signal of the clock signal φ2 are supplied to an analog switch 431, and a clock signal φ1 and an inverted signal of the clock signal φ1 are supplied to a clock inverter 413. Using the non-volatile latch circuit according to the present embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, so that the temperature operation range is wide and it operates stably even at high temperatures, and the stored logical state does not disappear even when the power is turned off, or a non-volatile latch circuit or a latch circuit incorporating a data holding unit with a sufficiently long refresh period can be realized. Since data writing is performed by switching of the transistor, there is substantially no limit to the number of rewrites. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1 V or less. Also, the charge stored in the capacitance of the data holding unit

[0233] By using the non-volatile latch circuit according to the present embodiment, a transistor using an oxide semiconductor as a semiconductor material constituting a channel formation region is used as a switching element of a data holding unit, so that a non-volatile latch circuit with a wide temperature operation range that operates stably even at high temperatures and does not lose the stored logical state even when the power is turned off, or a latch circuit incorporating a data holding unit with a sufficiently long refresh period can be realized. Since data writing is performed by switching of the transistor, there is substantially no limit to the number of rewrites. Also, the write voltage is about the threshold voltage of the transistor, and operation at a low voltage is possible. For example, the operation voltage can be set to 1 V or less. Also, the charge stored in the capacitance of the data holding unit ​​​​​​​​Since it is retained as data as it is, it is less affected by variations, and data reading can be easily performed.

[0234] By using the non-volatile latch circuit, it is possible to realize various logic circuits For example, power consumption can be reduced by turning off the power of unused blocks. In addition, since the logic state is stored even when the power is turned off, system startup when the power is turned on and system termination when the power is turned off can be performed quickly and with low power. This is possible.

[0235] This embodiment can be freely combined with other embodiments.

[0236] (Embodiment 7) In this embodiment, an example of an electronic device equipped with a semiconductor device using the non-volatile latch circuit obtained in the previous embodiment will be described with reference to FIG. 23. The non-volatile latch circuit obtained in the previous embodiment is used to mount a semiconductor device. The electronic device has excellent characteristics that are not found in the prior art. Therefore, it is possible to provide an electronic device with a new configuration using the semiconductor device using the non-volatile latch circuit. Note that the semiconductor device using the non-volatile latch circuit according to the previous embodiment is integrated and mounted on a circuit board or the like, and is mounted inside each electronic device.

[0237] FIG. 23(A) is a notebook personal computer including a semiconductor device using the non-volatile latch circuit according to the previous embodiment, and is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. The semiconductor device according to the disclosed invention is used in a notebook type By applying it to a personal computer, a notebook personal computer with excellent performance can be provided.

[0238] FIG. 23(B) is a personal digital assistant (PDA) including a semiconductor device using a non-volatile latch circuit according to the previous embodiment. The main body 311 is provided with a display unit 313, an external interface 315, operation buttons 314, etc. Also, there is a stylus 312 as an accessory for operation. By applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a personal digital assistant (PDA) with excellent performance can be provided.

[0239] FIG. 23(C) shows an electronic book 320 as an example of an electronic paper including a semiconductor device using a non-volatile latch circuit according to the previous embodiment. The electronic book 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 3 337 and can perform an opening and closing operation around the shaft portion 337. With such a configuration, the electronic book 320 can be used like a paper book.

[0240] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, a text can be displayed on the right display unit (display unit 325 in FIG. 23(C)), and an image can be displayed on the left display unit (display unit 327 in FIG. 23 (C)).

[0241] Also, FIG. 23(C) shows an example in which the housing 321 is provided with an operation unit and the like. For example, the housing​​​​​​​ The body 321 includes a power source 331, operation keys 333, a speaker 335, etc. The page can be turned by pressing the arrow 333. In addition, a keyboard and a pointer are installed on the same surface as the display unit of the housing. The housing may be provided with an external display device or the like. Connection terminals (earphone terminal, USB terminal, AC adapter and USB cable, etc.) A configuration including a terminal that can be connected to various cables, a recording medium insertion portion, etc. Furthermore, the electronic book 320 may be configured to have the functionality of an electronic dictionary.

[0242] The electronic book 320 may be configured to transmit and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0243] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, in-car advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards. To provide electronic paper with excellent performance by applying a semiconductor device to the electronic paper. can be done.

[0244] FIG. 23D shows a semiconductor device using the nonvolatile latch circuit according to the previous embodiment. This mobile phone is composed of two housings, housing 340 and housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, and a microphone 345. 4. Pointing device 346, camera lens 347, external connection terminal 348, etc. It is provided. Further, the housing 340 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built inside the housing 341 and is.

[0245] The display panel 342 has a touch panel function, and a plurality of operation keys 345 shown by dotted lines are displayed in Figure 23(D). Note that the mobile phone implements a boosting circuit for boosting the voltage output from the solar cell 349 to the voltage required for each circuit. Also, in addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, etc. and so on.

[0246] The display direction of the display panel 342 changes appropriately according to the usage form. Also, since a camera lens 347 is provided on the same plane as the display panel 342, a video phone is possible. The speaker 343 and the microphone 344 are not limited to voice calls, but are also capable of video phone calls, recording, playback, etc. Further, the housing 340 and the housing 341 can slide and change from the expanded state shown in Figure 23(D) to an overlapping state, enabling miniaturization suitable for carrying.

[0247] The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, by inserting a recording medium into the external memory slot 350, it is possible to support the storage and transfer of a larger amount of data. Also, in addition to the above functions, it may be equipped with an infrared communication function, a television receiving function, etc. By applying the semiconductor device according to the disclosed invention to a mobile phone, it is possible to provide a mobile phone with excellent performance.

[0248] Figure 23(E) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment and is a digital camera. The digital camera includes a main body 361, a display unit (A) 367, an eyepiece unit 363, an operation switch 364, a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the disclosed invention to a digital camera, a digital camera with excellent performance can be provided.

[0249] Figure 23(F) includes a semiconductor device using the non-volatile latch circuit according to the previous embodiment and is a television device. In the television device 370, a display unit 373 is incorporated in a housing 371 and it is possible to display an image by the display unit 373. Here, a configuration in which the housing 371 is supported by a stand 375 is shown.

[0250] The operation of the television device 370 can be performed by an operation switch provided in the housing 371 or a separate remote control operation unit 380. Channel and volume operations can be performed by operation keys 379 provided in the remote control operation unit 380, and the image displayed on the display unit 373 can be operated. Further, the remote control operation unit 380 may be provided with a display unit 377 for displaying information output from the remote control operation unit 380. In addition, the television device 370 is preferably configured to include a receiver, a modem, etc.

[0251] The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem, one-way (from the sender to the receiver) communication can be performed ​It is possible to perform unidirectional (from a sender to a receiver) or bidirectional (between a sender and a receiver, or between receivers) information communication. By applying the semiconductor device according to the disclosed invention to a television device, a television device with excellent performance can be provided.

[0252] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

Example

[0253] In this example, the results of evaluating the operation of a non-volatile latch circuit, which is one aspect of the disclosed invention, are shown.

[0254] The configuration of the non-volatile latch circuit used for the evaluation is shown in FIG. 24. The non-volatile latch circuit 400 shown in FIG. 24 has a latch section 411 and a data holding section 401 that holds the data of the latch section.

[0255] The latch section 411 includes an inverter 412, an inverter 413, a switch 431 composed of transistors, and a switch 432 composed of transistors.

[0256] The data holding section 401 includes a transistor 402 using an oxide semiconductor as a semiconductor material forming a channel region, a capacitor 404, an inverter 403, and a switch 405 composed of transistors. Note that the node S indicates the potential of one electrode of the capacitor 404 and the input terminal of the inverter 403.

[0257] The transistor 402 was fabricated according to FIGS. 5(A) to (G) and FIGS. 6(A) to (D), and a transistor having the same structure as the transistor shown in FIG. 6(D) was used. The transistor 402 is a ​​​​​​​​​​ A transistor using a highly purified oxide semiconductor with a channel length L = 3 μm and a channel width W = 5 μm is provided.

[0258] The inverter 412, the inverter 413, the inverter 403, the switch 431 composed of transistors, the switch 432 composed of transistors, and the switch 405 composed of transistors are formed of transistors using silicon.

[0259] The potential of the input signal IN is applied to the wiring 414 from the previous-stage circuit. The potential of the wiring 415 is applied to the subsequent-stage circuit as the output signal OUT. The potential of the signal φ1 is applied to the switch 431. The potential of the signal φ2 is applied to the switch 432. The potential of the control signal ST is applied to the gate of the transistor 402. The potential of the control signal LD is applied to the switch 405.

[0260] The evaluation results of the non-volatile latch circuit 400 are shown in FIGS. 25(A) and (B). FIG. 25(A) shows the results of measuring the potentials of the power supply voltage VDD, the input signal IN, the control signal ST, and the output signal OUT with an oscilloscope during the write operation. FIG. 25(B) shows the results of measuring the potentials of the power supply voltage VDD, the input signal IN, the control signal LD, and the output signal OUT with an oscilloscope during the read operation. In the evaluation of the non-volatile latch circuit 400, the power supply voltage during power supply was set to VDD = 5V and VSS = 0V.

[0261] First, an operation of writing and holding the potential of the output signal OUT at the node S was performed (see FIG. 25(A)). The potential of the output signal OUT during writing was set to 5V, and the potential of the input signal IN was set to 0V. ​​​A potential at which the transistor 402 turns on (here, a potential of 5V) is applied to the control signal ST, the transistor 402 is turned on, and the potential of the output signal OUT (here, a potential of 5V) is applied to the node S (write). The period during which the transistor 402 is turned on was set to 200 microseconds.

[0262] Thereafter, a potential at which the transistor 402 turns off (here, a potential of 0V) is applied to the control signal ST, the transistor 402 is turned off, and the potential of the node S is set to a floating state ( hold).

[0263] During the write and hold operations, a potential at which the switch 405 turns off (here, 0 V potential) was applied to the control signal LD.

[0264] Note that during the write and hold operations, the signals φ2 and φ1 were held at the potentials before the write operation (here, the signal φ2 was at a low level (0V) and the signal φ1 was at a high level (5V) potential).

[0265] Next, the power supply was stopped (also referred to as turning off the power), and the non-volatile latch circuit 400 was left at room temperature for 10 minutes. When the power supply was stopped (also referred to as the non-operation period), the potential of the power supply voltage VDD decreased. During this time, the potentials of the control signal ST and the control signal LD were held at 0V.

[0266] Thereafter, the power supply was restarted (also referred to as turning on the power), and the potential of the power supply voltage VDD was set to 5V.

[0267] Next, an operation to read the potential of the node S was performed (see Fig. 25(B)). At the time of reading, the potentials of the signals φ2 and φ1 were set to a low level (0V), and the switches 432 and 431 ​​​​​It was turned off. In this state, a potential (here a potential of 5V) at which the switch 405 turns on was applied to the control signal LD, and the switch 405 was turned on. When the switch 405 was turned on, a potential of 5V was output (read) as the output signal OUT potential.

[0268] The potential of the output signal OUT is the potential of the node S output through the inverters 403 and 412. Therefore, from FIG. 25(B), it was confirmed that the potential written to the node S before the power supply was stopped was retained as it was even after the power supply was stopped and was output as the potential of the output signal OUT. That is, by using the non-volatile latch circuit 400, it was confirmed that the logic state before the power supply was stopped could be restored immediately after the power supply was resumed.

Explanation of Signs

[0269] 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108a Gate insulating layer 110a Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound region 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Drain electrode 130b Drain electrode 130c Electrode 132 Insulating layer 134 Conductive layer 136a Electrode 136b Electrode 136c Electrode 136d gate electrode 138 gate insulating layer 140 oxide semiconductor layer 142a drain electrode 142b drain electrode 144 protective insulating layer 146 interlayer insulating layer 148 conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 301 main body 302 housing 303 display unit 304 keyboard 311 main body 312 stylus 313 display unit 314 operation button 315 external interface 320 e - book 321 housing 323 housing 325 display unit 327 display unit 331 power supply 333 operation key 335 speaker 337 shaft portion 340 housing 341 housing 342 display panel 343 speaker 344 microphone 345 operation key 346 pointing device 347 camera lens 348 external connection terminal 349 solar cell 350 external memory slot 361 Body 363 Eyepiece 364 Operation Switch 365 Display Unit (B) 366 Battery 367 Display Unit (A) 370 Television Set 371 Housing 373 Display Unit 375 Stand 377 Display Unit 379 Operation Key 380 Remote Control Unit 400 Latch Circuit 400a Latch Circuit 400b Latch Circuit 401 Data Retention Unit 402 Transistor 403 Inverter 404 Capacity 405 Switch 411 Latch Section 412 First Element 413 Second Element 414 Wiring 415 Wiring 420 Transistor 421 Transistor 431 Switch 432 Switch 501 N-channel Transistor 502 N-channel Transistor 503 P-channel Transistor 504 P-channel Transistor 505 P-channel Transistor 506 P-channel Transistor

Claims

1. A semiconductor device having a first transistor having a crystalline silicon semiconductor and a second transistor having an oxide semiconductor, the semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an insulating layer, wherein the first transistor has a first channel formation region, the second transistor has a second channel formation region, the first transistor has a first gate electrode above the first channel formation region, the second transistor has a second gate electrode below the second channel formation region, the insulating layer having a region disposed above one of a source or a drain of the second transistor and a region disposed above the other of the source or the drain of the second transistor, the first conductive layer having a region disposed above the insulating layer, the second conductive layer having a region disposed above the insulating layer, the third conductive layer having a region that functions as the first gate electrode, the third conductive layer being electrically connected to one of a source or a drain of the second transistor via the first conductive layer, the fourth conductive layer having a region that functions as the second gate electrode, the other of the source or the drain of the second transistor being electrically connected to the second conductive layer, in plan view, the insulating layer having a first opening overlapping the third conductive layer and a second opening overlapping one of a source or a drain of the second transistor, in plan view, the first conductive layer having a region overlapping the first opening and a region overlapping the second opening, in plan view, the first opening not overlapping the first channel formation region, in plan view, the fourth conductive layer having a region extending in a first direction, in plan view, the second conductive layer having a region extending in a second direction, wherein the second direction is a direction along the channel length direction of the second transistor, wherein the second direction intersects the first direction, a semiconductor device.

2. A semiconductor device having a first transistor having a crystalline silicon semiconductor and a second transistor having an oxide semiconductor, the semiconductor device having a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and an insulating layer, The first transistor has a first channel formation region, The second transistor has a second channel formation region, The first transistor has a first gate electrode above the first channel formation region, The second transistor has a second gate electrode below the second channel formation region, The insulating layer has a region disposed above one of the source or drain of the second transistor and a region disposed above the other of the source or drain of the second transistor, The first conductive layer has a region disposed above the insulating layer, The second conductive layer has a region disposed above the insulating layer, The third conductive layer has a region that functions as the first gate electrode, The third conductive layer is electrically connected to one of the source or drain of the second transistor via the first conductive layer, The fourth conductive layer has a region that functions as the second gate electrode, The other of the source or drain of the second transistor is electrically connected to the second conductive layer, In plan view, the insulating layer has a first opening overlapping the third conductive layer and a second opening overlapping one of the source or drain of the second transistor, In plan view, the first conductive layer has a region overlapping the first opening and a region overlapping the second opening, In plan view, the first opening does not overlap the first channel formation region, In plan view, the first gate electrode does not overlap the second gate electrode, In plan view, the fourth conductive layer has a region extending in a first direction, In plan view, the second conductive layer has a region extending in a second direction, The second direction is a direction along the channel length direction of the second transistor, The second direction intersects the first direction, a semiconductor device.

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