Operation method of an information processing apparatus

Abstract

To provide an information processing device with a small circuit area and reduced power consumption.SOLUTION: An information processing device includes a NAND type memory unit and a controller. The memory unit also has a first string and a second string, each having a different block. The first string has a first memory cell, and the second string has a second memory cell. The controller writes first data into the first memory cell by receiving the first data and a signal including a command to write the first data. Thereafter, the controller reads the first data from the first memory cell and writes the first data to the second memory cell.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to an information processing apparatus and a method of operating the information processing apparatus.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an article, a method of operation, or a method of manufacture. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a sensor, a processor, an electronic device, an information processing apparatus, a system, a method of operating them, a method of manufacturing them, or a method of inspecting them.

Background Art

[0003] Research and development aimed at reducing the power consumption of information processing apparatuses have been actively conducted, and reducing the power consumption of integrated circuits (ICs) such as CPUs and storage devices has become a major issue in circuit design. The power consumption of an IC can be roughly divided into two types: power consumption during operation (dynamic power) and power consumption when not operating (standby power). By increasing the operating frequency for higher performance, the dynamic power increases. Most of the static power is the power consumed by the leakage current of transistors. The leakage current includes subthreshold leakage current, gate tunnel leakage current, gate-induced drain leakage (GIDL) current, and junction tunnel leakage current. Since these leakage currents increase with the miniaturization of transistors, the increase in power consumption has become a major obstacle to the higher performance and higher integration of ICs.

[0004] To reduce the power consumption of semiconductor devices such as integrated circuits and memory devices, or information processing devices including such semiconductor devices, circuits that do not need to be operated are stopped by power gating or clock gating. Since power gating stops the power supply, it has the effect of eliminating standby power. To enable power gating in a CPU, it is necessary to back up the stored contents of registers and caches to a non-volatile memory.

[0005] A memory circuit that can hold data even in a power-off state has been proposed by utilizing the characteristic that the off-current of a transistor in which an oxide semiconductor (also referred to as Oxide Semiconductor or simply OS) is included in the channel formation region (hereinafter sometimes referred to as "oxide semiconductor transistor" or "OS transistor") is extremely small. For example, Non-Patent Document 1 discloses an OS-SRAM (Static Random Access Memory) equipped with a backup circuit using an OS transistor. Non-Patent Document 1 discloses that a microprocessor equipped with an OS-SRAM can perform power gating with a short break-even time (BET) without affecting normal operation.

Prior Art Documents

Non-Patent Documents

[0006]

Non-Patent Document 1

[0007]

Non-Patent Document 2

Non-Patent Document 3

Non-Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0008] As an example, in a NAND - type memory device, etc., the input speed of write data (the amount of information input per unit time) is slower than the data writing speed to the memory unit. The cache memory in the memory device can write data to the memory unit without reducing the input speed of the write data input to the memory device by temporarily holding the write data input to the memory device. Also, the data read - out speed from the memory unit is slower than the output speed of the read - out data from the memory device (the amount of information output per unit time). The cache memory in the memory device can read data from the memory unit without reducing the read - out speed of the read - out data from the memory device by temporarily holding the data read from the memory device.

[0009] Also, as an example, the cache memory has a function of temporarily holding data when performing operations such as rearranging the data held in the memory unit and saving data that is not related to deletion.

[0010] For example, DRAM (Dynamic Random Access Memory) is applied to the cache memory. Therefore, since the cache memory and the NAND - type memory device are created in different processes, they are created as separate chips. For this reason, it is necessary to provide bus wiring between the cache memory and the NAND - type memory device, and the circuit area of the memory device may increase. Also, depending on the length of the bus wiring, the power consumption of the signal flowing through the bus wiring may increase.

[0011] One aspect of the present invention aims to provide an information processing apparatus with a reduced circuit area. Or, one aspect of the present invention aims to provide an information processing apparatus with low power consumption.

[0012] Or, one aspect of the present invention aims to provide a novel information processing apparatus. Or, one aspect of the present invention aims to provide a method for operating a novel information processing apparatus.

[0013] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this section as described below. Problems not mentioned in this section can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. One aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not necessarily need to solve all of the problems listed above and other problems.

Means for Solving the Problems

[0014] (1) One aspect of the present invention is an information processing apparatus having a NAND-type storage unit and a controller. The storage unit has a first string and a second string, each of which is different in block. Also, each of the first string and the second string has a transistor including a metal oxide in a channel formation region. Further, the first string has a first memory cell, and the second string has a second memory cell. The controller has a function of writing the first data into the first memory cell by receiving the first data and a signal including an instruction to write the first data. Also, the controller then has a function of reading the first data from the first memory cell and writing the first data into the second memory cell.

[0015] (2) Alternatively, one aspect of the present invention is an information processing apparatus including a NAND-type memory unit and a controller. The memory unit has a first string, a second string, and a third string, each of which is different in block. Each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, the second string has a second memory cell and a third memory cell, and the third string has a fourth memory cell. The controller has a function of writing the first data into the first memory cell by receiving the first data and a signal including an instruction to rewrite the second data held in the second memory cell into the first data. The controller also has a function of reading the third data held in the third memory cell and writing the third data into the fourth memory cell. The controller further has a function of erasing the second data held in the second memory cell and the third data held in the third memory cell. The controller also has a function of reading the first data held in the first memory cell and writing the first data into the second memory cell. The controller also has a function of reading the third data held in the fourth memory cell and writing the third data into the third memory cell.

[0016] (3) Alternatively, one aspect of the present invention is a method of operating an information processing apparatus having a NAND-type memory unit and a controller. The memory unit has a first string and a second string, each of which is different in a block. Further, each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, and the second string has a second memory cell. The method of operating the information processing apparatus has a first step to a third step. The first step includes a step in which the controller receives a first data and a signal including an instruction to write the first data, and a step in which the first data is written into the first memory cell by the controller. The second step has a step in which the first data is read from the first memory cell by the controller. The third step has a step in which the first data read in the second step is written into the second memory cell by the controller.

[0017] (4) Alternatively, one aspect of the present invention is a method of operating an information processing apparatus having a NAND-type memory unit and a controller. The memory unit has a first string, a second string, and a third string, each of which is different in block. Further, each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, the second string has a second memory cell and a third memory cell, and the third string has a fourth memory cell. The method of operating the information processing apparatus has steps from a first step to an eighth step. The first step includes a step in which the controller receives a signal including an instruction to rewrite the first data and the second data held in the second memory cell to the first data, and a step in which the first data is written into the first memory cell by the controller. The second step has a step in which the third data held in the third memory cell of the second string is read out by the controller. The third step has a step in which the third data read out in the second step is written into the fourth memory cell by the controller. The fourth step has a step in which the second data held in the second memory cell and the third data held in the third memory cell are erased by the controller. The fifth step has a step in which the first data held in the first memory cell is read out by the controller. The sixth step has a step in which the first data read out in the fifth step is written into the second memory cell by the controller. The seventh step has a step in which the third data held in the fourth memory cell is read out by the controller. The eighth step has a step in which the third data read out in the seventh step is written into the third memory cell by the controller.

[0018] (5) One aspect of the present invention is an information processing apparatus having an arithmetic processing unit, a storage device, and a plurality of wirings. The storage device has a plurality of strings, and one of the plurality of strings is electrically connected to the arithmetic processing unit via one of the plurality of wirings. The method of operating the information processing apparatus includes converting first data input by serial transmission into a plurality of second data, distributing the plurality of second data for each of the plurality of wirings, and simultaneously supplying the plurality of second data to the plurality of strings in response to a trigger signal.

[0019] (6) Alternatively, in one aspect of the present invention, in the configuration of (5) above, the string has a plurality of memory cells, and the memory cell may include an oxide semiconductor.

[0020] (7) Alternatively, in one aspect of the present invention, in the configuration of (5) or (6) above, the storage device may be a NAND-type storage device.

[0021] (8) Alternatively, one aspect of the present invention is an information processing apparatus having a NAND-type storage unit and a controller. The storage unit has a first string and a second string, each of which is in a different block. Each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has first memory cells, and the second string has second memory cells. The controller has a function of writing first data to the first memory cells by receiving the first data and a signal including an instruction to write the first data. Further, the controller then has a function of reading the first data from the first memory cells and writing the first data to the second memory cells.

[0022] (9) Alternatively, one aspect of the present invention is an information processing apparatus including a NAND-type memory unit and a controller. The memory unit has a first string, a second string, and a third string, each of which is different in block. Further, each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, the second string has a second memory cell and a third memory cell, and the third string has a fourth memory cell. The controller has a function of writing first data to the first memory cell by receiving the first data and a signal including an instruction to rewrite the second data held in the second memory cell to the first data. The controller also has a function of reading the third data held in the third memory cell and writing the third data to the fourth memory cell. The controller further has a function of erasing the second data held in the second memory cell and the third data held in the third memory cell. The controller also has a function of reading the first data held in the first memory cell and writing the first data to the second memory cell. The controller also has a function of reading the third data held in the fourth memory cell and writing the third data to the third memory cell.

[0023] (10) Alternatively, one aspect of the present invention is an operation method of an information processing apparatus including a NAND-type memory unit and a controller. The memory unit has a first string and a second string, which are different in each block. Each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, and the second string has a second memory cell. The operation method of the information processing apparatus includes a first step to a third step. The first step includes a step in which the controller receives a first data and a signal including an instruction to write the first data, and a step in which the first data is written into the first memory cell by the controller. The second step includes a step in which the first data is read from the first memory cell by the controller. The third step includes a step in which the first data read in the second step is written into the second memory cell by the controller.

[0024] (11) Alternatively, one aspect of the present invention is a method of operating an information processing apparatus having a NAND-type memory unit and a controller, wherein the memory unit has a first string, a second string, and a third string, each of which is different in a block. Further, each of the first string and the second string has a transistor including a metal oxide in a channel formation region. The first string has a first memory cell, the second string has a second memory cell and a third memory cell, and the third string has a fourth memory cell. The method of operating the information processing apparatus includes first to eighth steps. The first step includes a step in which the controller receives a signal including an instruction to rewrite the first data and the second data held in the second memory cell to the first data, and a step in which the first data is written into the first memory cell by the controller. The second step includes a step in which the third data held in the third memory cell of the second string is read out by the controller. The third step includes a step in which the third data read out in the second step is written into the fourth memory cell by the controller. The fourth step includes a step in which the second data held in the second memory cell and the third data held in the third memory cell are erased by the controller. The fifth step includes a step in which the first data held in the first memory cell is read out by the controller. The sixth step includes a step in which the first data read out in the fifth step is written into the second memory cell by the controller. The seventh step includes a step in which the third data held in the fourth memory cell is read out by the controller. The eighth step includes a step in which the third data read out in the seventh step is written into the third memory cell by the controller.

[0025] In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, and includes a circuit containing semiconductor elements (such as transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, or an electronic component in which a chip is housed in a package is an example of a semiconductor device. In addition, a storage device, a display device, a light-emitting device, a lighting device, an electronic device, an information processing device, etc. may be a semiconductor device itself or may have a semiconductor device.

[0026] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that the cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected are those disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in a figure or text, and those other than the connection relationship shown in the figure or text are also considered to be disclosed in the figure or text. It is assumed that X and Y are objects (such as devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0027] As an example of the case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitor elements, inductors, resistor elements, diodes, display devices, light-emitting devices, loads, etc.) that enable the electrical connection between X and Y can be connected between X and Y. Note that a switch has a function in which its on / off is controlled. That is, a switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0028] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0029] In addition, when it is explicitly described that X and Y are electrically connected, it shall include the case where X and Y are electrically connected (that is, the case where they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, the case where they are connected without another element or another circuit interposed between X and Y).

[0030] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By using an expression method similar to these examples to define the connection order in the circuit configuration, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0031] Note that even when components that are independent on the circuit diagram are shown as being electrically connected, one component may have the functions of multiple components combined. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component combined. Therefore, the electrically connected in this specification includes such cases where one conductive film has the functions of multiple components combined within its scope.

[0032] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, the "resistive element" includes wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" can be replaced with terms such as "resistance", "load", "region having a resistance value", and conversely, the terms "resistance", "load", "region having a resistance value" can be replaced with terms such as "resistive element". As the resistance value, for example, it can be preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it can be 1 Ω or more and 1×10 9 Ω or less.

[0033] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value, parasitic capacitance, the gate capacitance of a transistor, and the like. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also parasitic capacitance that appears between wirings, gate capacitance that appears between one of the source or drain of a transistor and the gate, and the like. Also, terms such as "capacitive element", "parasitic capacitance", "gate capacitance" can be replaced with terms such as "capacitance", and conversely, the term "capacitance" can be replaced with terms such as "capacitive element", "parasitic capacitance", "gate capacitance". Also, the term "pair of electrodes" of "capacitance" can be replaced with "pair of conductors", "pair of conductive regions", "pair of regions", and the like. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it can be 1 pF or more and 10 μF or less.

[0034] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain can be interchanged. Also, in this specification and the like, when explaining the connection relationship of the transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, it may have a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0035] Also, in this specification and the like, a node can be interchanged with a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, the device structure, etc. Also, it is possible to interchange a terminal, a wiring, etc. with a node.

[0036] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to a wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc. also change.

[0037] Also, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, in two wirings, if both are described as "functioning as a wiring that supplies a high-level potential", the respective high-level potentials provided by the two wirings do not have to be equal to each other. Similarly, in two wirings, if both are described as "functioning as a wiring that supplies a low-level potential", the respective low-level potentials provided by the two wirings do not have to be equal to each other.

[0038] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, a description such as "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring and the like is defined as the direction in which the carrier regarded as a positive charge moves, and is described with a positive current amount. In other words, the direction in which the carrier regarded as a negative charge moves is the direction opposite to the direction of current and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), a description such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, a description such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0039] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components, nor do they limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0040] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and the like, and can be appropriately rephrased according to the situation. For example, in the expression "insulator located on the upper surface of the conductor", by rotating the direction of the shown drawing by 180 degrees, it can be rephrased as "insulator located on the lower surface of the conductor".

[0041] Also, the terms "above" and "below" do not limit the positional relationship between components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be directly formed in contact with insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0042] In addition, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other according to the situation. For example, in some cases, the term "conductive layer" can be changed to the term "conductive film". Or, for example, in some cases, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases, or according to the situation, it is possible to replace with another term without using terms such as "film" and "layer". For example, in some cases, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, in some cases, the terms "insulating layer" and "insulating film" can be changed to the term "insulator".

[0043] In addition, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced by terms such as "region" in some cases.

[0044] In addition, in this specification and the like, terms such as "wiring", "signal line", "power line", etc. can be interchanged with each other in some cases or according to the situation. For example, the term "wiring" may be changed to the term "signal line" in some cases. Also, for example, the term "wiring" may be changed to terms such as "power line" in some cases. Also, vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring" in some cases. The term "power line" etc. may be changed to the term "signal line" etc. in some cases. Also, vice versa, terms such as "signal line" etc. may be changed to the term "power line" etc. in some cases. Also, the term "potential" applied to the wiring may be changed to the term "signal" etc. in some cases or according to the situation. Also, vice versa, terms such as "signal" etc. may be changed to the term "potential" in some cases.

[0045] In this specification and the like, impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements (however, oxygen and hydrogen are not included), etc.

[0046] In this specification and the like, a switch refers to something that has a function of controlling whether to conduct an electric current (on state) or not to conduct an electric current (off state). Or, a switch refers to something that has a function of selecting and switching a path through which an electric current flows. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control an electric current and is not limited to a specific one.

[0047] As an example of an electrical switch, there are a transistor (e.g., bipolar transistor, MOS transistor, etc.), a diode (e.g., PN diode, PIN diode, Schottky diode, MIM (Metal Insulator Metal) diode, MIS (Metal Insulator Semiconductor) diode, a diode-connected transistor, etc.), or a logic circuit combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conducting state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating a transistor as a mere switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0048] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology. The switch has an electrode that can be mechanically moved, and by moving the electrode, it controls conduction and non-conduction to operate.

[0049] In this specification, "parallel" refers to a state where two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "substantially parallel" or "approximately parallel" refers to a state where two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" refers to a state where two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially perpendicular" or "approximately perpendicular" refers to a state where two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0050] According to one aspect of the present invention, an information device with a reduced circuit area can be provided. Or, according to one aspect of the present invention, an information processing device with low power consumption can be provided.

[0051] Alternatively, according to one aspect of the present invention, a novel information processing apparatus can be provided. Alternatively, one of the problems is to provide an operation method for a novel information processing apparatus according to one aspect of the present invention.

[0052] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are those effects not mentioned in this item as described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, in some cases, one aspect of the present invention may not have the effects listed above.

Brief Description of the Drawings

[0053]

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DETAILED DESCRIPTION OF THE INVENTION

[0054] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors, and the like. For example, when a metal oxide is used in the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor.

[0055] In this specification and the like, a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0056] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Also, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0057] Note that the content described in one embodiment (even some of the content) can be applied to, combined with, or replaced with at least one of the content described in another content (even some of the content) described in the same embodiment and the content (even some of the content) described in one or more other embodiments.

[0058] Note that the content described in the embodiments refers to the content described using various figures in each embodiment (or example) or the content described using the text described in the specification.

[0059] Note that the figure (which may be a part) described in one embodiment can be combined with at least one of another part of the figure, another figure (which may be a part) described in the embodiment, and a figure (which may be a part) described in one or more other embodiments to form more figures.

[0060] The embodiments described in this specification will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and the form and details can be variously changed without departing from the spirit and scope. Therefore, the present invention is not construed as being limited to the description of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used among different drawings for the same part or parts having the same function, and the repeated description may be omitted. Also, in perspective views and the like, for the sake of clarity of the drawings, the description of some components may be omitted.

[0061] In this specification and the like, when the same reference numerals are used for a plurality of elements, in particular, when it is necessary to distinguish them, identification symbols such as “_1”, “[n]”, “[m,n]” may be appended to the reference numerals for description.

[0062] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0063] (Embodiment 1) In this embodiment, an information processing apparatus according to one aspect of the present invention having a function as a storage device will be described.

[0064] <Configuration Example> FIG. 1 is a block diagram showing a configuration example of an information processing apparatus. The information processing apparatus 50 includes, as an example, a storage unit 1196, a controller 1197, and a bus interface 1198.

[0065] The information processing apparatus 50 has a function of writing data to the storage unit 1196 in response to a command by acquiring a signal including command information from the outside, as an example.

[0066] Specifically, for example, a signal ISG including command information input to the information processing apparatus 50 is input to the controller 1197 via the bus interface 1198.

[0067] The controller 1197 has a function of decoding the signal ISG, for example. The controller 1197 also has a function of performing various controls based on the command included in the decoded signal. Specifically, the controller 1197 generates an address of the storage unit 1196 and reads and writes data in the storage unit 1196 according to the state of the information processing apparatus. When writing to the storage unit 1196, the data for writing can be, for example, data DT input to the information processing apparatus via the bus interface 1198. Note that the data DT is transmitted to the controller 1197 via the bus interface 1198.

[0068] Therefore, the controller 1197 may include, as an example, a circuit that decodes the signal ISG, a circuit that generates an address of a memory cell included in the storage unit 1196, and a circuit that outputs a signal for switching between the on state and the off state of a transistor included in the storage unit 1196.

[0069] The controller 1197 may also have a function of generating a signal for controlling the operation timing. For example, the controller 1197 may include an internal clock generation unit that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the above various circuits.

[0070] Further, the controller 1197 may have a function of performing error checking on the memory cells of the string included in the storage unit 1196. By having this function, for example, the controller 1197 can perform error checking on the memory cells of the string included in the storage unit 1196 before writing data to the storage unit 1196. At this time, if a defective cell is found in the string to be written, the controller 1197 can change the data write destination from the defective cell to another cell and perform the data write operation. Further, the controller 1197 may have a function of performing error checking on the memory cells of the string included in the storage unit 1196 at regular intervals and correcting the data when a defective cell is found in the string.

[0071] Further, as an example, the information processing apparatus 50 has a function of reading data from the storage unit 1196 according to the command by acquiring a signal including command information from the outside. Further, the information processing apparatus 50 has a function of outputting the read data as a signal OSG to the outside of the information processing apparatus 50 by the controller 1197.

[0072] In the information processing apparatus according to one aspect of the present invention, as the storage unit 1196, for example, a storage circuit having a NAND type string can be applied. In particular, as the NAND type storage circuit, it is preferable to apply a three-dimensional structure NAND type storage circuit using an OS transistor. Note that, as the configuration of the memory cell, there are a configuration in which a NAND type string using an OS transistor is horizontal and the strings are stacked one layer at a time, and a configuration in which a NAND type string using an OS transistor is vertical and the strings are formed in a batch by etching or the like. In this specification and the like, a structure in which a NAND type string using an OS transistor is vertical may be referred to as a 3D OS NAND (registered trademark) type storage circuit. Since a large number of memory cells can be formed simultaneously in the 3D OS NAND type storage circuit, the mounting density can be increased with fewer manufacturing steps. That is, a storage circuit with a high mounting density can be realized at low cost by reducing the cost per bit. For this reason, the storage unit 1196 has a plurality of NAND type strings. Note that FIG. 1 shows an example in which the storage unit 1196 has strings ST1 to ST3. In addition, in the storage unit 1196 of FIG. 1, strings other than strings ST1 to ST3 are omitted.

[0073] As an example, string ST1 has memory cells L[1] to L[n] (where n is an integer of 1 or more), string ST2 has memory cells M[1] to M[n], and string ST3 has memory cells N[1] to N[n].

[0074] Also, in string ST1, the memory cells L[1] to L[n] are electrically connected in series between wiring SL1 and wiring BL1. Similarly, in string ST2, the memory cells M[1] to M[n] are electrically connected in series between wiring SL2 and wiring BL2, and in string ST3, the memory cells N[1] to N[n] are electrically connected in series between wiring SL3 and wiring BL3.

[0075] Each of wirings SL1 to SL3 functions as a wiring for applying a predetermined potential to strings ST1 to ST3. Also, each of wirings BL1 to BL3 functions as a wiring for writing data to memory cells included in strings ST1 to ST3 and / or a wiring for reading data from the memory cells.

[0076] Note that, for strings not shown in the figure, the connection configuration is the same as that of strings ST1 to ST3.

[0077] <Example of operation method> Here, in the information processing apparatus 50 of FIG. 1, an example of an operation method of treating some memory cells included in the strings of the storage unit 1196 as a cache memory will be described.

[0078] FIG. 2 is a flowchart showing an example of the operation method of the information processing apparatus 50 of FIG. 1. The operation method has steps STP1 to STP8. Also, in conjunction with the flowchart, the movement of data in strings ST1 and ST2 is shown in FIGS. 3A to 3C.

[0079] Also, as an example of this operation method, consider a case where data is held in each of memory cells L[1] to L[n] of string ST1 and the data of memory cell L[6] is rewritten. Also, assume that at least strings ST2 and ST3 do not hold data.

[0080] In the information processing apparatus 50 of FIG. 1, when the operation starts, first, step STP1 is performed.

[0081] Step STP1 has a step of writing data for rewriting to memory cell L[1] into, for example, memory cell N[1] of string ST3. Specifically, for example, the information processing apparatus 50 in FIG. 1 acquires data DT for rewriting and a signal ISG including an instruction to rewrite the data, and a write signal is transmitted from the controller 1197 to the storage unit 1196 to hold the data DT for writing in the memory cell M[1].

[0082] After step STP1 ends, step STP2 is performed. Step STP2 has a step of reading out the data held in each of the memory cells L[1] to L[n] other than the memory cell to be rewritten in string ST1. Here, for example, it is assumed that the data held in each of the memory cells L[1] to L[5] is read out (see FIG. 3A).

[0083] Step STP3 has a step of sequentially writing (copying) the data of each of the memory cells L[1] to L[5] read out in step STP2 into the memory cells M[1] to M[5] of string ST2 (see FIG. 3A).

[0084] In the flowchart of FIG. 2, it is described that step STP3 is performed after step STP2, but the operation method of the information processing apparatus according to an aspect of the present invention is not limited to this. For example, in step STP2, the data held in each of the memory cells L[1] to L[5] of string ST1 may be sequentially read out, and the read data may be sequentially written into the memory cells M[1] to M[5] of string ST2. That is, step STP2 and step STP3 may be combined as the same step.

[0085] After step STP3 ends, step STP4 is performed. Step STP4 has a step of erasing the data held in the memory cells L[1] to L[5] of string ST1.

[0086] When the memory unit 1196 is a NAND-type memory circuit, since the data erasing operation is performed in units of strings, when attempting to erase the data held in the memory cells L[1] to L[5] of the string ST1, all the data in the memory cells L[1] to L[n] will be erased. Therefore, in steps STP2 and STP3, not only the memory cells L[1] to L[5], but also the data in the memory cells L[7] to L[n] need to be written to the string ST2.

[0087] For this reason, the memory unit 1196 is preferably an OS NAND-type memory circuit having the circuit configuration shown in FIGS. 4 to 6 described later. Although details will be described later, by using this memory device, it is possible to erase the data from the memory cell L[1] to any memory cell of the string ST1. Therefore, in this operation example, in order to rewrite the data of the memory cell L[6], only the data of the memory cells L[1] to L[6] of the string ST1 will be erased (see FIG. 3B).

[0088] Step STP5 has a step of reading the rewrite data DT from the memory cell N[1] of the string ST3.

[0089] Step STP6 has a step of writing the rewrite data DT of the memory cell N[1] read in step STP5 to the memory cell L[6] of the string ST1 (see FIG. 3B).

[0090] Step STP7 has a step of reading the data held in each of the memory cells M[1] to M[5] of the string ST2. The data corresponds to the data written in step STP3 (see FIG. 3C).

[0091] Step STP8 has a step of sequentially writing (copying) the respective data of memory cells M[1] to M[5] read in step STP5 to memory cells L[1] to L[5] of string ST1 (see FIG. 3C).

[0092] In the flowchart of FIG. 2, it is described that step STP8 is performed after step STP7. However, the operation method of the information processing apparatus according to an aspect of the present invention is not limited to this. For example, in step STP7, the data held in each of memory cells M[1] to M[5] of string ST2 may be sequentially read out, and the read data may be sequentially written to memory cells L[2] to N[5] of string ST1. That is, steps STP7 and STP8 may be grouped as the same step.

[0093] As in steps STP1 to STP8 described above, when writing data to a string in the storage unit 1196, when rewriting data held in the string, etc., memory cells of another string in the storage unit 1196 can be treated as a cache memory.

[0094] Incidentally, in the information processing apparatus 50 shown in FIG. 1, as the substrate for forming the circuit, for example, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate). Further, as the substrate, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film, etc. are available. As an example of the glass substrate, there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass, etc. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Or, as an example, there is a synthetic resin such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride, etc. Or, as an example, there are polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or papers, etc. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate, etc., it is possible to manufacture a transistor with little variation in characteristics, size, or shape, high current capacity, and small size. When a circuit is configured with such a transistor, it is possible to achieve low power consumption of the circuit or high integration of the circuit.

[0095] Further, as the substrate, a flexible substrate may be used, and a transistor may be directly formed on the flexible substrate. Or, a release layer may be provided between the substrate and the transistor. The release layer can be used to separate from the substrate after partially or completely completing the information processing apparatus thereon and transfer it to another substrate. At that time, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Incidentally, for the above-mentioned release layer, for example, a configuration of a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a configuration in which an organic resin film such as polyimide is formed on the substrate, etc. can be used.

[0096] That is, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and disposed on the other substrate. As an example of the substrate to which the transistor is transferred, in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including natural fibers (silk, cotton, hemp), synthetic fibers (nylon, polyurethane, polyester), or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), a leather substrate, or a rubber substrate, etc. By using these substrates, it is possible to form a transistor with good characteristics, form a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

[0097] Note that all of the circuits necessary to realize a predetermined function can be formed on the same substrate (for example, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate, etc.). In this way, it is possible to reduce costs by reducing the number of parts, or improve reliability by reducing the number of connection points with circuit components.

[0098] Note that it is possible not to form all of the circuits necessary to realize a predetermined function on the same substrate. That is, a part of the circuits necessary to realize a predetermined function may be formed on one substrate, and another part of the circuits necessary to realize a predetermined function may be formed on another substrate. For example, a part of the circuits necessary to realize a predetermined function may be formed on a glass substrate, and another part of the circuits necessary to realize a predetermined function may be formed on a single crystal substrate (or an SOI substrate). Then, a single crystal substrate (also referred to as an IC chip) on which another part of the circuits necessary to realize a predetermined function is formed can be connected to the glass substrate by COG (Chip On Glass) to place the IC chip on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board, etc. In this way, since a part of the circuits is formed on the same substrate as the pixel portion, it is possible to reduce costs by reducing the number of components, or to improve reliability by reducing the number of connection points with circuit components. In particular, circuits in parts where the drive voltage is large or the drive frequency is high often consume a large amount of power. Therefore, such circuits are formed on a substrate different from the pixel portion (for example, a single crystal substrate) to constitute an IC chip. By using this IC chip, an increase in power consumption can be prevented.

[0099] Note that one aspect of the present invention is not limited to the configuration of the information processing apparatus 50 shown in FIG. 1. One aspect of the present invention may change the configuration of the information processing apparatus 50 shown in FIG. 1 according to the situation. For example, the string configuration of the storage unit 1196 included in the information processing apparatus 50 shown in FIG. 1 may be changed to the string configuration described in Embodiment 2.

[0100] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0101] (Embodiment 2) In this embodiment, a configuration example of a memory unit (NAND-type memory circuit) applicable to the memory unit 1196 of Embodiment 1 will be described.

[0102] <Configuration Example of Memory Unit (Memory Circuit)> An example of the memory unit will be described with reference to FIG. 4A. FIG. 4A shows a circuit diagram of n memory cells (n is an integer of 1 or more). That is, the circuit shown in FIG. 4A includes memory cells of memory cells MC[1] to MC[n], wiring WWL[1] to WWL[n] for controlling them, wiring RWL[1] to RWL[n], wiring WBL, and wiring RBL. The wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

[0103] Each memory cell MC includes a transistor WTr, a transistor RTr, and a capacitor CS. The transistor RTr shown in FIG. 4A is a transistor having a back gate, and by applying a potential to the back gate, the threshold voltage of the transistor RTr can be varied. The wiring BGL shown in FIG. 4A is electrically connected to the back gates of the transistors RTr included in the memory cells MC[1] to MC[n], respectively. Further, the semiconductor device shown in FIG. 4A may be configured such that the wiring BGL is not electrically connected to each of the back gates of the transistors RTr included in the memory cells MC[1] to MC[n], but is electrically connected to each of the back gates independently and different potentials are applied to each other.

[0104] The channel formation region of the transistor WTr preferably has, for example, the metal oxide described in Embodiment 6. In particular, in the case of a metal oxide having one or more elements selected from indium, element M (as element M, for example, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc, since the metal oxide functions as a wide-gap semiconductor, the transistor in which the metal oxide is included in the channel formation region has a characteristic of extremely low off-current.

[0105] Also, as the channel formation region of the transistor RTr, it is preferable to use a material that increases the field-effect mobility of the transistor. By using such a transistor, the semiconductor device can operate faster. For example, as the material included in the channel formation region of the transistor RTr, it can have a semiconductor material such as silicon or the metal oxide described in Embodiment 6.

[0106] The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. The switching between the on state and the off state of the transistor WTr is performed by the potential applied to the wiring WWL. The potential of one electrode of the capacitor CS is controlled by the wiring RWL. The other electrode of the capacitor CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitor CS can be referred to as a memory node. The memory node of each memory cell MC is electrically connected to the first terminal of the transistor WTr included in the memory cell MC.

[0107] Also, the second terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr of the adjacent memory cell MC. Similarly, the first terminal of the transistor RTr is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell. And the second terminal of the transistor WTr included in the memory cell MC[n] is electrically connected to the wiring WBL, and the second terminal of the transistor RTr included in the memory cell MC[n] is electrically connected to the wiring RBL. In this embodiment, the connection point between the second terminal of the transistor RTr included in the memory cell MC[n] and the wiring RBL is referred to as node N1, and the first terminal of the transistor RTr included in the memory cell MC[1] is referred to as node N2. In addition, in order to control the conduction state between the node N1 and the wiring RBL, a selection transistor may be connected in series with the transistor RTr of the memory cell MC[n]. Similarly, in order to control the conduction state between the wiring connected to the node N2 and the node N2, a selection transistor may be connected in series with the transistor RTr of the memory cell MC[1].

[0108] Note that one aspect of the present invention is not limited to the semiconductor device shown in FIG. 4A. One aspect of the present invention can have a circuit configuration obtained by appropriately modifying the semiconductor device shown in FIG. 4A. For example, as shown in FIG. 4B, one aspect of the present invention may be a semiconductor device in which a back gate is also provided for the transistor WTr. The semiconductor device illustrated in FIG. 4B has a configuration in which, in addition to the configuration of the semiconductor device illustrated in FIG. 4A, back gates are provided for the transistors WTr included in the memory cells MC[1] to MC[n], and each of the back gates is electrically connected to a wiring BGL. Further, for example, as shown in FIG. 4C, one aspect of the present invention may be a semiconductor device in which no back gate is provided for the transistor RTr and the transistor WTr.

[0109] Incidentally, when it is desired to further increase the storage capacity of the semiconductor device shown in FIGS. 4A to 4C, the semiconductor devices shown in FIGS. 4A to 4C may be arranged in a matrix. For example, when the semiconductor devices shown in FIG. 4B are arranged in a matrix, the circuit configuration is as shown in FIG. 5.

[0110] The semiconductor device shown in FIG. 5 is formed by arranging the semiconductor devices shown in FIG. 4B in m columns (m is an integer of 1 or more) as one row, and is electrically connected so as to share the wiring RWL and the wiring WWL with the memory cells MC in the same row. That is, the semiconductor device shown in FIG. 5 is a matrix semiconductor device of n rows and m columns, and has memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG. 5 is electrically connected by the wiring RWL[1] to RWL[n], the wiring WWL[1] to WWL[n], the wiring RBL[1] to RBL[m], the wiring WBL[1] to WBL[m], and the wiring BGL[1] to BGL[m]. Specifically, one electrode of the capacitance CS of the memory cell MC[j,i] (j is an integer of 1 or more and n or less, and i is an integer of 1 or more and m or less) is electrically connected to the wiring RWL[j], and the gate of the transistor WTr of the memory cell MC[j,i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC[n,i], and the wiring RBL[i] is electrically connected to the second terminal of the transistor RTr of the memory cell MC[n,i].

[0111] Note that FIG. 5 only shows the memory cell MC[1,1], memory cell MC[1,i], memory cell MC[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC[j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[n,m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1], wiring WWL[j], wiring WWL[n], wiring RBL[1], wiring RBL[i], wiring RBL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1], wiring BGL[i], wiring BGL[m], capacitor CS, transistor WTr, transistor RTr, node N1, and node N2.

[0112] In this specification etc., as an example, the memory cells MC[1,i] to MC[n,i] electrically connected between the nodes N1 and N2 in the i-th column may be referred to as the string in the i-th column. Also, as an example, the memory cells MC[j,1] to MC[j,m] electrically connected to the wiring RWL[j] and wiring WWL[j] in the j-th row may be referred to as the page in the j-th row. Further, as an example, the memory cells MC[1,1] to MC[n,m] arranged in an n-row by m-column matrix shown in FIG. 5 may be collectively referred to as a block.

[0113] Also, FIG. 6 shows a configuration in which the semiconductor devices shown in FIG. 4C are arranged side by side in m columns (m is an integer of 1 or more) as one column. Note that the semiconductor device shown in FIG. 6 has a configuration in which no back gate is provided for each transistor included in all the memory cells MC, and thus, the semiconductor device shown in FIG. 6 does not have the wiring BGL. For the semiconductor device shown in FIG. 6, the description of the semiconductor device shown in FIG. 5 is referred to.

[0114] <<Example of Operating Method>> Next, an example of the operation method of the semiconductor device shown in FIGS. 4A to 4C will be described. Note that the low-level potential and high-level potential used in the following description do not mean specific potentials, and if the wiring is different, the specific potentials may also be different. For example, each of the low-level potential and high-level potential applied to the wiring WWL may be a potential different from the low-level potential and high-level potential applied to the wiring RWL.

[0115] Also, in this example of the operation method, it is assumed that potentials within the range where the transistors RTr and WTr operate normally are applied in advance to the wiring BGL shown in FIGS. 4A and 4B. Therefore, the operations of the semiconductor devices shown in FIGS. 4A to 4C can be considered similarly to each other.

[0116] FIG. 7A is a timing chart showing an example of the operation of writing data into the semiconductor device, and FIG. 7B is a timing chart showing an example of the operation of reading data from the semiconductor device. Each of the timing charts in FIGS. 7A and 7B shows the changes in the magnitudes of the potentials of the wirings WWL[1], WWL[2], WWL[n], RWL[1], RWL[2], RWL[n], node N1, and node N2. Also, the wiring WBL shows the data supplied to the wiring WBL.

[0117] FIG. 7A shows an example of writing each of the data D[1] to D[n] into the memory cells MC[1] to MC[n]. Note that the data D[1] to D[n] can be binary values, multi-valued values, analog values, etc. And the data D[1] to D[n] are assumed to be supplied from the wiring WBL. That is, in the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, the writing of data is sequentially performed from the memory cell MC[1] to the memory cell MC[n].

[0118] Also, for example, after writing data to memory cell MC[2], if one attempts to write data to memory cell MC[1], the data held in memory cell MC[2] will be lost when writing data to memory cell MC[1] unless the data written to memory cell MC[2] is first read out and saved elsewhere.

[0119] In the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, when writing data to memory cell MC[i] (where i is an integer from 2 to n), in order to prevent rewriting of the data held in memory cells MC[1] to MC[i - 1], a low-level potential is supplied to wirings WWL[1] to WWL[i - 1] to turn off respective transistors WTr of memory cells MC[1] to MC[i - 1]. Thereby, the respective data held in memory cells MC[1] to MC[i - 1] can be protected.

[0120] Also, when writing data to memory cell MC[i], since the data is supplied from wiring WBL, a high-level potential is supplied to wirings WWL[i] to WWL[n] to turn on respective transistors WTr of memory cells MC[i] to MC[n] sufficiently. Thereby, the data can be held in the memory node of memory cell MC[i].

[0121] Note that when writing data to the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, since wiring RBL can be controlled independently of other wirings, there is no need to set it to a specific potential, but for example, it can be set to a low-level potential. That is, the potential of node N1 can be set to a low-level potential. In addition, the potential of node N2 can also be set to a low-level potential.

[0122] Based on the above, the operation example shown in the timing chart of FIG. 7A will be described. At time T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are all at a low-level potential.

[0123] At time T11, the application of a high-level potential to the wirings WWL[1] to WWL[n] is started. As a result, between time T11 and time T12, each transistor WTr included in the memory cells MC[1] to MC[n] becomes fully on. Then, data D[1] is supplied to the wiring WBL. Since each transistor WTr included in the memory cells MC[1] to MC[n] is fully on, the data D[1] reaches the memory node of the memory cell MC[1] and is written.

[0124] At time T12, the application of a low-level potential to the wiring WWL[1] is started, and a high-level potential continues to be applied to the wirings WWL[2] to WWL[n]. As a result, between time T12 and time T13, the transistor WTr included in the memory cell MC[1] becomes off, and each transistor WTr included in the memory cells MC[2] to MC[n] becomes fully on. Then, data D[2] is supplied to the wiring WBL. Since each transistor WTr included in the memory cells MC[2] to MC[n] is fully on, the data D[2] reaches the memory node of the memory cell MC[2] and is written. Also, since the transistor WTr of the memory cell MC[1] is off, the data D[1] held in the memory cell MC[1] is not lost by the writing operation from time T12 to time T13.

[0125] Between time T13 and time T14, similar to the data D[1] writing operation to memory cell MC[1] between time T11 and time T12 and the data D[2] writing operation to memory cell MC[2] between time T12 and time T13, data D[3] to D[n - 1] are sequentially written to each of memory cells MC[3] to MC[n - 1]. Specifically, transistors WTr of memory cells MC[1] to MC[j - 1] (where j is an integer from 3 to n - 1) that already have data written are turned off, transistors WTr of memory cells MC[j] to MC[n] that do not have data written are turned to a sufficient on state, data D[j] is supplied from wiring WBL, and it may be written to the memory node of memory cell MC[j]. Then, when the writing of data D[j] to memory cell MC[j] is completed, the transistor WTr of memory cell MC[j] is turned off, data D[j + 1] is supplied from wiring WBL, and an operation of writing to the memory node of memory cell MC[j + 1] may be performed. In particular, the writing operation when j is n - 1 refers to the operation from time T14 to time T15 described below.

[0126] At time T14, a low-level potential is applied to wirings WWL[1] to WWL[n - 1], and a high-level potential is continuously applied to wiring WWL[n]. As a result, between time T14 and time T15, the transistors WTr included in memory cells MC[1] to MC[n - 1] are turned off, and the transistor WTr included in memory cell MC[n] is turned on sufficiently. Then, data D[n] is supplied to wiring WBL. Since the transistor WTr included in memory cell MC[n] is turned on sufficiently, data D[n] reaches the memory node of memory cell MC[n] and is written. Also, since the transistors WTr of memory cells MC[1] to MC[n - 1] are turned off, the data D[1] to D[n - 1] held in each of memory cells MC[1] to MC[n - 1] is not lost by the writing operation between this time T14 and time T15.

[0127] By the above operation, data can be written to the memory cell MC included in any one of the semiconductor devices shown in FIGS. 4A to 4C.

[0128] FIG. 7B shows an example of a timing chart for reading data D[1] to D[n] from memory cells MC[1] to MC[n]. At this time, in order to maintain the data held in each memory cell MC, the transistor WTr is required to be in the off state. Therefore, when reading data from memory cells MC[1] to MC[n], the potentials of wirings WWL[1] to WWL[n] are set to low-level potentials.

[0129] In the circuit configuration of the semiconductor device shown in FIGS. 4A to 4C, when reading the data of a specific memory cell MC, after turning on the transistors RTr of other memory cells MC sufficiently, the transistor RTr of the specific memory cell MC is operated in the saturation region. That is, the current flowing between the source and drain of the transistor RTr of the specific memory cell MC is determined according to the voltage between the source and drain and the data held in the specific memory cell MC.

[0130] For example, consider the case of reading the data held in the memory cell MC[k] (where k is an integer from 1 to n). At this time, in order to turn on the respective transistors RTr of the memory cells MC[1] to MC[n] excluding the memory cell MC[k] sufficiently, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[k].

[0131] On the other hand, for the transistor RTr of the memory cell MC[k] to be in an on state according to the held data, the wiring RWL[k] needs to be at the same potential as the wiring RWL[k] when the data was written to the memory cell MC[k]. Here, the potential of the wiring RWL[k] during the write operation and the read operation is considered to be a low-level potential.

[0132] For example, a potential of +3V is applied to node N1 and 0V to node N2. Then, node N2 is floated and the subsequent potential of node N2 is measured. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high-level potential, the transistors RTr of the memory cells MC[1] to MC[n] excluding the memory cell MC[k] are turned on sufficiently. On the other hand, since the voltage between the first terminal and the second terminal of the transistor RTr of the memory cell MC[k] is determined by the potential of the gate of the transistor RTr and the potential of node N1, the potential of node N2 is determined according to the data held in the memory node of the memory cell MC[k].

[0133] In this way, the data held in the memory cell MC[k] can be read out.

[0134] Based on the above, an operation example shown in the timing chart of FIG. 7B will be described. At time T20, the potentials of each of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wiring WBL, the node N1, and the node N2 are at a low-level potential. In particular, the node N2 is in a floating state. And it is assumed that data D[1] to D[n] are respectively held in the memory nodes of the memory cells MC[1] to MC[n].

[0135] Between time T21 and time T22, an application of a low-level potential to the wiring RWL[1] is started, and an application of a high-level potential to the wirings RWL[2] to RWL[n] is started. As a result, between time T21 and time T22, each transistor RTr included in the memory cells MC[2] to MC[n] becomes in a sufficient on state. And the transistor RTr of the memory cell MC[1] becomes in an on state according to the data D[1] held in the memory node of the memory cell MC[1]. Also, a potential V R is supplied to the wiring RBL. Thereby, the potential of the node N1 becomes V R , and the potential of the node N2 is determined according to the potential V R of the node N1 and the data held in the memory node of the memory cell MC[1]. Here, the potential of the node N2 is set to V D[1] . And by measuring the potential V D[1] of the node N2, the data D[1] held in the memory node of the memory cell MC[1] can be read out.

[0136] Between time T22 and time T23, the application of a low-level potential to wirings RWL[1] to RWL[n] is started. Also, a low-level potential is supplied to node N2, and thereafter, node N2 becomes a floating state. That is, between time T22 and time T23, the potentials of each of wirings RWL[1] to RWL[n] and node N2 become the same as the situation between time T20 and time T21. Note that the potential V R may be continuously supplied to wiring RBL, or a low-level potential may be supplied. In this operation example, it is assumed that the potential V R is continuously supplied to wiring RBL after time T21.

[0137] Between time T23 and time T24, a low-level potential is applied to wiring RWL[2], and the application of a high-level potential to wirings RWL[1], RWL[3] to RWL[n] is started. As a result, between time T23 and time T24, each transistor RTr included in memory cells MC[1], MC[3] to MC[n] becomes a sufficient on-state. And the transistor RTr of memory cell MC[2] becomes an on-state according to the data D[2] held in the memory node of memory cell MC[2]. Also, the potential V R is continuously supplied to wiring RBL. Thereby, the potential of node N2 is determined according to the potential V R of node N1 and the data held in the memory node of memory cell MC[2]. Here, the potential of node N2 is set to V D[2] . And by measuring the potential V D[2] of node N2, the data D[2] held in the memory node of memory cell MC[2] can be read out.

[0138] Between time T24 and time T25, in the same manner as the data D[1] read operation from the memory cell MC[1] between time T20 and time T22 and the data D[2] read operation from the memory cell MC[2] between time T22 and time T24, data D[3] to data D[n - 1] are sequentially read from each of the memory cells MC[3] to MC[n - 1]. Specifically, when reading data D[j] from the memory cell MC[j] (where j is an integer from 3 to n - 1), after setting the potential of node N2 to a low-level potential and floating node N2, a high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the wiring RWL[j], turning on the transistors RTr of the memory cells MC[1] to MC[n] excluding the memory cell MC[j] sufficiently, and turning on the transistor RTr of the memory cell MC[j] to an on state corresponding to the data D[j]. Next, by setting the potential of node N1 to V R , the potential of node N2 becomes a potential corresponding to the data D[j], and by measuring this potential, the data D[j] can be read. After the reading of the data D[j] held in the memory cell MC[j] is completed, as preparation for the next read operation, a low-level potential is applied to the wirings RWL[1] to RWL[n], the potential of node N2 is set to a low-level potential, and then node N2 is put into a floating state. In particular, when j is n - 1, this preparation refers to the operation between time T25 and time T26.

[0139] Between time T25 and time T26, the application of a low-level potential to the wirings RWL[1] to RWL[n] is started. Also, the application of a low-level potential to node N2 is started, and after the potential of node N2 becomes a low-level potential, node N2 becomes a floating state. That is, between time T25 and time T26, the potentials of the wirings RWL[1] to RWL[n] and node N2 are the same as the situation between time T20 and time T21. Note that the potential V RIt may be supplied, or a low-level potential may be applied. In this operation example, at time T21, the potential V R is started to be applied to the wiring RBL, and after time T22, the potential V R shall continue to be applied to the wiring RBL.

[0140] At time T26, a low-level potential is applied to the wiring RWL[n], and high-level potentials are supplied to the wirings RWL[1] to RWL[n - 1]. As a result, between time T26 and time T27, each transistor RTr included in the memory cells MC[1] to MC[n - 1] is in a sufficient on state. And the transistor RTr of the memory cell MC[n] is in an on state according to the data D[n] held in the memory node of the memory cell MC[n]. Also, the potential V R continues to be supplied to the wiring RBL. Thereby, the potential of the node N2 is determined according to the potential V R of the node N1 and the data held in the memory node of the memory cell MC[n]. Here, the potential of the node N2 is set to V D[n] . And by measuring the potential V D[n] of the node N2, the data D[n] held in the memory node of the memory cell MC[n] can be read out.

[0141] By the above operation, data can be read out from each memory cell MC of the semiconductor device shown in FIGS. 4A to 4C.

[0142] Note that the operation in the information processing apparatus according to an aspect of the present invention is not limited to the above-described operation example. The operation in the information processing apparatus according to an aspect of the present invention may be appropriately changed according to the situation. For example, in the above-described read operation, by supplying the potential V R to the node N1, the potential V D corresponding to the data held in the memory node of the MC of the desired memory cell is read out from the node N2.

[0143] Next, in order to apply the NAND-type memory circuit shown in FIGS. 5 and 6 to the memory unit 1196 of FIG. 1, an example of a method of treating it as a cache memory will be described.

[0144] FIG. 8 is a configuration example of a memory unit having blocks BLK_1 to BLK_k (k is an integer of 1 or more). Each of blocks BLK_1 to BLK_k has, for example, the n×m matrix-shaped memory cells MC[1,1] to MC[n,m] shown in FIGS. 5 and 6. Note that only the memory cells MC of a certain column are shown in blocks BLK_1 to BLK_k shown in FIG. 8. Therefore, in FIG. 8, the row address of the matrix-shaped memory cells MC included in block BLK is denoted by “[ ]” and the address of block BLK is denoted by “_” in the reference numerals, and the column address to the reference numerals is omitted. Further, when the configuration of the memory unit shown in FIG. 5 is applied to the memory unit shown in FIG. 8, the back gates of the respective transistors shown in FIG. 8 are assumed to be omitted.

[0145] The memory unit shown in FIG. 8 has a configuration in which transistors BTr_1 to BTr_k and transistors STr_1 to STr_k are provided with respect to the memory units shown in FIGS. 5 and 6.

[0146] Specifically, in the memory unit of FIG. 8, the wiring RBL_1 is electrically connected to the first terminal of the transistor BTr_1 and the first terminal of the transistor STr_1. Also, the second terminal of the transistor STr_1 is electrically connected to the wiring WBL_1 and the first terminal of the switch SW_1. The wiring RBL_h (where h is an integer from 1 to k) is electrically connected to the first terminal of the transistor BTr_h and the first terminal of the transistor STr_h. Also, the second terminal of the transistor STr_h is electrically connected to the wiring WBL_h and the first terminal of the switch SW_h. The wiring RBL_k is electrically connected to the first terminal of the transistor BTr_k and the first terminal of the transistor STr_k. Also, the second terminal of the transistor STr_k is electrically connected to the wiring WBL_k and the first terminal of the switch SW_k.

[0147] The second terminals of each of the switches SW_1 to SW_k are electrically connected to the wiring LN1. Also, the third terminals of each of the switches SW_1 to SW_k are electrically connected to the wiring LN2.

[0148] Each of the switches SW_1 to SW_k has a function of making the connection between the first terminal and either one of the second terminal or the third terminal in a conductive state. That is, each of the switches SW_1 to SW_k can select whether to make each of the blocks BLK_1 to BLK_k conductive to either the wiring LN1 or the wiring LN2.

[0149] The wiring LN1 functions as a wiring for transmitting write data to the memory cells of each string of the blocks BLK_1 to BLK_k, for example. Also, the wiring LN2 functions as a wiring for transmitting data read from the memory cells of each string of the blocks BLK_1 to BLK_k, for example. Note that the information processing apparatus according to one aspect of the present invention is not limited to this configuration. For example, the wirings LN1 and LN2 may not be two but may be combined into one (in this case, the switches SW_1 to SW_k may not be provided), or may be three or more (in this case, each of the switches SW_1 to SW_k may be replaced with a selector circuit or the like according to the number of wirings).

[0150] Each of the transistors BTr_1 to BTr_k functions as a transistor for adjusting the potential of the node N1 of each of the wirings RBL_1 to RBL_k. For this reason, it is assumed that a predetermined potential is input to the second terminal and the gate of each of the transistors BTr_1 to BTr_k. Specifically, for example, when a potential is read from any one of the memory cells MC[1]_h to MC[n]_h of the block BLK_h (h is an integer from 1 to k), the transistor BTr[i] has a function of varying the potential of the node N1 of the wiring RBL_h to a write potential. Therefore, the transistors BTr_1 to BTr_k may be replaced with an amplification circuit such as a sense amplifier.

[0151] Each of the transistors STr_1 to STr_k functions as a switching element. Therefore, the gate of each of the transistors STr_1 to STr_k is electrically connected to a wiring for transmitting a signal for switching each of the transistors STr_1 to STr_k to an on state or an off state.

[0152] Next, the operation method of the memory unit when a part of the memory unit in FIG. 8 functions as a cache memory will be described. For the description of the operation method, the memory unit shown in FIG. 9 will be used.

[0153] The memory unit in FIG. 9 is a simplified representation of the memory unit in FIG. 8. Specifically, the memory unit in FIG. 9 has a configuration in which m = 3 and k = 3 in the memory unit of FIG. 8.

[0154] The memory unit in FIG. 9 has blocks BLK_1 to BLK_3, and each of blocks BLK_1 to BLK_3 has one or more strings. Specifically, block BLK_1 has memory cells MC[1]_1 to MC[3]_1 as one string, block BLK_2 has memory cells MC[1]_2 to MC[3]_2 as one string, and block BLK_3 has memory cells MC[1]_3 to MC[3]_3 as one string.

[0155] It is assumed that data is held in each memory node of memory cells MC[1]_2 to MC[3]_2 included in the string of block BLK_2. Specifically, for example, it is assumed that potentials V[1]_2, V[2]_2, and V[3]_2 are held in each memory node of memory cells MC[1]_2 to MC[3]_2.

[0156] Also, it is assumed that no data is held in each memory node of memory cells MC[1]_1 to MC[3]_1 included in the string of block BLK_1 and memory cells MC[1]_3 to MC[3]_3 included in the string of block BLK_3.

[0157] Here, consider the case of rewriting V[1]_2 held in the memory node of memory cell MC[1]_2.

[0158] When rewriting the potential of the memory node of the memory cell MC[1]_2, in order to send the rewrite data to the memory cell MC[1]_2 from the wiring WBL_2 through the respective transistors WTr of the memory cells MC[2]_2 and MC[3]_2, it is necessary to temporarily save V[2]_2 and V[3]_2 that are pre-held in the respective memory nodes of the memory cells MC[2]_2 and MC[3]_3.

[0159] First, as the rewrite data, the potential V REW is written into the memory node of the memory cell MC[3]_1 included in the string of the block BLK_1. Specifically, the first terminal and the second terminal of the switch SW_1 are made conductive, a high-level potential is input to the wiring WWL[3]_1 to turn on the transistor WTr of the memory cell MC[3]_1, and V REW is input from the wiring LN1. At this time, a low-level potential is input to the wiring WWL[3]_2 of the block BLK_2 and the wiring WWL[3]_3 of the block BLK_3 to turn off the respective transistors WTr of the memory cells MC[3]_2 and MC[3]_3, and it is necessary to prevent the writing of V REW from the wiring WBL_1 to the respective memory cells MC of the blocks BLK_2 and BLK_3. Or, in each of the switches SW_2 and SW_3, the first terminal and the third terminal may be made conductive, that is, the first terminal and the second terminal may be made non-conductive.

[0160] Note that at this time, the memory cell MC[3]_1 can be regarded as a cache memory.

[0161] Next, temporarily save V[3]_2 held in the memory node of the memory cell MC[3]_2 of block BLK_2. In this operation example, assume that V[3]_2 in the memory node of the memory cell MC[3]_2 is saved to the memory node of the memory cell MC[2]_3 of block BLK_3. Specifically, make the first and second terminals of each of switch SW_2 and switch SW_3 in a conductive state, input a high-level potential to wiring RWL[1]_2 and wiring RWL[2]_2, and raise the potential of each memory node of memory cell MC[1]_2 and memory cell MC[2]_2 so that the respective transistors RTr of memory cell MC[1]_2 and memory cell MC[2]_2 are in a sufficient on state. Also, input a high-level potential to the gate of transistor STr_2 to turn on transistor STr_2. Also, input a low-level potential to the gate of transistor STr_3 to turn off transistor STr_3, input a high-level potential to wiring WWL[2]_3 and wiring WWL[3]_3 of block BLK_3, and turn on the respective transistors WTr of memory cell MC[2]_3 and memory cell MC[3]_3.

[0162] Here, by supplying V R to node N2 of block BLK_2, the potential of node N1 of block BLK_2 can be made the potential corresponding to V[3]_2 held in the memory node of the memory cell MC[3]_2 of block BLK_2. Also, the potential of node N1 can be varied to V[3]_2 by transistor BTr_2.

[0163] Also, at this time, since the connection between node N1 of block BLK_2 and the memory node of the memory cell MC[2]_3 of block BLK_3 is in a conductive state, the potential of the memory node of the memory cell MC[2]_3 of block BLK_3 becomes V[3]_2. Then, by inputting a low-level potential to wiring WWL[2]_3 and turning off the transistor WTr of memory cell MC[2]_3, the potential of V[3]_2 can be held in the memory node of memory cell MC[2]_3.

[0164] Next, temporarily save V[2]_2 held in the memory node of the memory cell MC[2]_2 of block BLK_2. In this operation example, assume that V[2]_2 in the memory node of the memory cell MC[2]_2 of block BLK_2 is saved to the memory node of the memory cell MC[3]_3 of block BLK_3. Specifically, make the connection between the first terminal and the second terminal of each of switch SW_2 and switch SW_3 in a conducting state, input a high-level potential to wiring RWL[1]_2 and wiring RWL[3]_2, and raise the potential of each memory node of memory cell MC[1]_2 and memory cell MC[3]_2 so that each transistor RTr of memory cell MC[1]_2 and memory cell MC[3]_2 is in a sufficient on state. Also, input a high-level potential to the gate of transistor STr_2 to turn on transistor STr_2. Further, input a low-level potential to the gate of transistor STr_3 to turn off transistor STr_3, input a high-level potential to wiring WWL[3]_3 of block BLK_3, and turn on each transistor WTr of memory cell MC[3]_3.

[0165] Here, by supplying V R to node N2 of block BLK_2, the potential of node N1 of block BLK_2 can be made to be a potential corresponding to V[2]_2 held in the memory node of the memory cell MC[2]_2 of block BLK_2. Also, the potential of node N1 can be varied to V[2]_2 by transistor BTr_2.

[0166] Also, at this time, since the connection between node N1 of block BLK_2 and the memory node of the memory cell MC[3]_3 of block BLK_3 is in a conducting state, the potential of the memory node of the memory cell MC[3]_3 of block BLK_3 becomes V[2]_2. Then, input a low-level potential to wiring WWL[3]_3 to turn off the transistor WTr of memory cell MC[3]_3, whereby the potential of V[2]_2 can be held in the memory node of memory cell MC[3]_3.

[0167] Next, the data held in each memory node of the memory cells MC[1]_2 to MC[3]_2 of the block BLK_2 is erased.

[0168] Specifically, first, the connection between the first terminal and the second terminal of the switch SW_2 is made conductive, and a low-level potential is input to the gates of the transistors STr_1 to STr_3 to turn off each of the transistors STr_1 to STr_3. Also, a low-level potential is input to the wiring WWL[3]_1 of the block BLK_1 and the wiring WWL[3]_3 of the block BLK_3 to turn off the transistors WTr of the memory cells MC[3]_1 of the block BLK_1 and MC[3]_3 of the block BLK_3, respectively. Further, the connection between the first terminal and the third terminal of each of the switches SW_1 and SW_3, that is, the connection between the first terminal and the second terminal may be made non-conductive.

[0169] Thereafter, a high-level potential is input to each of wirings WWL[1]_2 to WWL[3]_2 of block BLK_2 to turn on the respective transistors WTr of memory cells MC[1]_2 to MC[3]_2 of block BLK_2. At this time, by applying a potential for initializing data (for example, a low-level potential, a ground potential, etc.) from wiring LN1 to the memory nodes of each of memory cells MC[1]_2 to MC[3]_2, the potential held in the memory nodes of each of memory cells MC[1]_2 to MC[3]_2 is rewritten to the potential for initialization. Thereafter, a low-level potential is input to each of wirings WWL[1]_2 to WWL[3]_2 of block BLK_2 to turn off the respective transistors WTr of memory cells MC[1]_2 to MC[3]_2 of block BLK_2, whereby the erasure of the data of each of memory cells MC[1]_2 to MC[3]_2 of block BLK_2 is completed. Note that, at the timing of data writing described below, since the data is rewritten by turning on the transistors WTr of memory cells MC[1]_2 to MC[3]_2, the erasure operation described above may not be performed.

[0170] Next, V held in the memory node of the memory cell MC[3]_1 of block BLK_1 REWWrite to the memory cell MC[1]_2 of block BLK_2. Specifically, make the connection between the first terminal and the second terminal of each of switch SW_1 and switch SW_2 in a conductive state, input a high-level potential to wiring RWL[1]_1 and wiring RWL[2]_1, and raise the potential of each memory node of memory cell MC[1]_1 and memory cell MC[2]_1 so that each transistor RTr of memory cell MC[1]_1 and memory cell MC[2]_1 is in a sufficient on state. Also, input a high-level potential to the gate of transistor STr_1 to turn on transistor STr_1. Further, input a low-level potential to the gate of transistor STr_2 to turn off transistor STr_2, input a high-level potential to wiring WWL[1]_3 to wiring WWL[3]_3 of block BLK_2, and turn on each transistor WTr of memory cell MC[1]_3 to memory cell MC[3]_3.

[0171] At this time, input a low-level potential to wiring WWL[3]_3 of block BLK_3 to turn off the transistor WTr of memory cell MC[3]_3, input a low-level potential to the gate of transistor STr_3 to turn off transistor STr_3, and prevent the writing of V REW from block BLK_1 to memory cell MC[3]_3 of block BLK_3. Alternatively, the connection between the first terminal and the third terminal of switch SW_3, that is, the connection between the first terminal and the second terminal may be made in a non-conductive state.

[0172] Here, by supplying V R to node N2 of block BLK_1, the potential of node N1 of block BLK_1 can be made the potential corresponding to V REW held in the memory node of memory cell MC[3]_1 of block BLK_1. Also, the potential of node N1 can be varied to V REW by transistor BTr_2.

[0173] At this time, since conduction is established between the node N1 of block BLK_1 and the memory node of the memory cell MC[1]_2 of block BLK_2, the potential of the memory node of the memory cell MC[1]_2 of block BLK_2 becomes V REW After that, a low-level potential is input to the wiring WWL[1]_2 to turn off the transistor WTr of the memory cell MC[1]_2, thereby enabling the memory node of the memory cell MC[1]_2 to hold the potential of V REW .

[0174] Next, the V[2]_2 held in the memory node of the memory cell MC[3]_3 of block BLK_3 is rewritten to the memory cell MC[2]_2 of block BLK_2. Specifically, the conduction state is established between the first terminal and the second terminal of each of the switches SW_2 and SW_3, and a high-level potential is input to the wirings RWL[1]_3 and RWL[2]_3 to raise the potentials of the memory nodes of the memory cells MC[1]_3 and MC[2]_3 respectively so that the transistors RTr of the memory cells MC[1]_3 and MC[2]_3 are in a sufficient on state. Also, a high-level potential is input to the gate of the transistor STr_3 to turn on the transistor STr_3. Further, a low-level potential is input to the gate of the transistor STr_2 to turn off the transistor STr_2, and a high-level potential is input to the wirings WWL[2]_2 and WWL[3]_2 of block BLK_2 to turn on the transistors WTr of the memory cells MC[2]_2 and MC[3]_2 respectively.

[0175] At this time, a low-level potential is input to the wiring WWL[3]_1 of the block BLK_1 to turn off the transistor WTr of the memory cell MC[3]_1, and a low-level potential is input to the gate of the transistor STr_1 to turn off the transistor STr_1, so as to prevent the writing of V[2]_2 from the block BLK_3 to the memory cell MC[3]_1 of the block BLK_1. Alternatively, the first terminal and the third terminal of the switch SW_1 may be in a conductive state, that is, the first terminal and the second terminal may be in a non-conductive state.

[0176] Here, by supplying V R to the node N2 of the block BLK_3, the potential of the node N1 of the block BLK_3 can be made to be a potential corresponding to V[2]_2 held in the memory node of the memory cell MC[3]_3 of the block BLK_3. Also, the potential of the node N1 can be varied to V[2]_2 by the transistor BTr_3.

[0177] Also, at this time, since the node N1 of the block BLK_3 and the memory node of the memory cell MC[2]_2 of the block BLK_2 are in a conductive state, the potential of the memory node of the memory cell MC[2]_2 of the block BLK_2 becomes V[2]_2. Then, by inputting a low-level potential to the wiring WWL[2]_2 to turn off the transistor WTr of the memory cell MC[2]_2, the rewriting of the potential of V[2]_2 to the memory node of the memory cell MC[2]_2 is completed.

[0178] Next, write back V[3]_2 held in the memory node of the memory cell MC[2]_3 of block BLK_3 to the memory cell MC[3]_2 of block BLK_2. Specifically, make the first and second terminals of each of switch SW_2 and switch SW_3 conductive, input a high-level potential to wiring RWL[1]_3 and wiring RWL[3]_3, and raise the potential of each memory node of memory cell MC[1]_3 and memory cell MC[3]_3 so that the respective transistors RTr of memory cell MC[1]_3 and memory cell MC[3]_3 are in a sufficient on state. Also, input a high-level potential to the gate of transistor STr_3 to turn on transistor STr_3. Further, input a low-level potential to the gate of transistor STr_2 to turn off transistor STr_2, input a high-level potential to wiring WWL[3]_2 of block BLK_2, and turn on the respective transistors WTr of memory cell MC[3]_2.

[0179] At this time, it is necessary to input a low-level potential to wiring WWL[3]_1 of block BLK_1 to turn off the transistor WTr of memory cell MC[3]_1, input a low-level potential to the gate of transistor STr_1 to turn off transistor STr_1, and prevent the writing of V[3]_2 from block BLK_3 to the memory cell MC[3]_1 of block BLK_1. Alternatively, the first and third terminals of switch SW_1 may be made conductive, that is, the first and second terminals may be made non-conductive.

[0180] Here, by supplying V R to node N2 of block BLK_3, the potential of node N1 of block BLK_3 can be made the potential corresponding to V[3]_2 held in the memory node of the memory cell MC[2]_3 of block BLK_3. Also, the potential of node N1 can be varied to V[3]_2 by transistor BTr_3.

[0181] At this time, since conduction is established between the node N1 of block BLK_3 and the memory node of the memory cell MC[3]_2 of block BLK_2, the potential of the memory node of the memory cell MC[3]_2 of block BLK_2 becomes V[3]_2. Thereafter, a low-level potential is input to the wiring WWL[3]_2 to turn off the transistor WTr of the memory cell MC[3]_2, thereby completing the rewiring of the potential V[3]_2 to the memory node of the memory cell MC[3]_2.

[0182] By performing the above-described operations, the storage unit shown in FIG. 8 or FIG. 9 can treat a part of the storage unit as a cache memory when writing data to the storage unit, when rewriting data held in the storage unit, and the like.

[0183] Incidentally, due to soft errors caused by the environment (temperature, humidity, etc.) of the information processing apparatus or natural radiation, at least one of the transistor characteristics of the transistors WTr, RTr, BTr, and STr included in each memory cell of the string of the storage unit shown in FIG. 8 or FIG. 9 may deteriorate (for example, the source-drain current of the transistor in the off state increases). In this case, by having the controller 1197 of the information processing apparatus 50 shown in FIG. 1 with a function of performing error checking on the strings (memory cells) included in the storage unit, error checking can be performed on the strings of the storage unit shown in FIG. 8 or FIG. 9. Further, the controller 1197 may have a function of aborting access to the string including the memory cell when an error is detected in the memory cell on which the error check has been performed and performing access to another string.

[0184] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0185] (Embodiment 3) In this embodiment, a configuration example of the information processing apparatus described in Embodiment 1 and a configuration example of a transistor applicable to the information processing apparatus will be described.

[0186] <Configuration Example 1 of Information Processing Apparatus> The information processing apparatus shown in FIG. 10 includes a storage unit 100 and a control unit 200. FIG. 10 is a cross-sectional view of the transistor 300 in the channel length direction, and FIG. 11 is a cross-sectional view of the transistor 300 in the channel width direction.

[0187] In FIG. 10, the control unit 200 corresponds to a circuit including the controller 1197 in FIG. 1, and the storage unit 100 corresponds to the storage unit 1196 in FIG. 1.

[0188] First, the transistor 300 included in the control unit 200 and the insulators, conductors, etc. formed around it will be described.

[0189] As an example, the transistor 300 is provided on a substrate 311 and has a conductor 316, an insulator 315, a semiconductor region 313 composed of a part of the substrate 311, a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. Note that the transistor 300 can be applied to, for example, the transistors included in the controller 1197.

[0190] Also, it is preferable to use a semiconductor substrate (for example, a single-crystal substrate or a silicon substrate) as the substrate 311.

[0191] As shown in FIG. 11, the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with the conductor 316 via the insulator 315. In this way, by making the transistor 300 a Fin type, the effective channel width increases, thereby improving the on characteristics of the transistor 300. Also, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

[0192] Note that the transistor 300 may be either a p-channel type or an n-channel type.

[0193] In the region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or the drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 300 may be a HEMT (High Electron Mobility Transistor).

[0194] The low-resistance region 314a and the low-resistance region 314b include an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 313.

[0195] The conductor 316 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material, which includes an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron.

[0196] Note that since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0197] Note that the transistor 300 shown in FIGS. 10 and 11 is an example, and the present invention is not limited to its structure. An appropriate transistor may be used according to the circuit configuration and driving method. For example, the control unit 200 of the information processing apparatus may be a unipolar circuit including only OS transistors.

[0198] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially laminated and provided covering the transistor 300.

[0199] As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0200] In this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0201] The insulator 322 may function as a planarization film that planarizes a step generated by the transistor 300 or the like provided below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0202] Further, for the insulator 324, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 311 or the transistor 300 or the like to the storage unit 100 including the transistor 700, the plurality of transistors 800, and the transistor 900.

[0203] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by CVD method can be used. Here, when the transistor 700, the plurality of transistors 800, and the transistor 900 are OS transistors, the characteristics of the semiconductor element having the oxide semiconductors of the transistor 700, the plurality of transistors 800, and the transistor 900 may deteriorate due to the diffusion of hydrogen. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 700, the plurality of transistors 800, and the transistor 900 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0204] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 324 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50 °C to 500 °C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 324, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0205] Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0206] In addition, as an example, conductors 328 and 330 are embedded in insulators 320, 322, 324, and 326. Note that conductors 328 and 330 have functions as plugs or wirings. Also, conductors having functions as plugs or wirings may be given the same reference numeral collectively for a plurality of structures. Further, in this specification and the like, a wiring and a plug connected to the wiring may be an integral body. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0207] As materials for each plug and wiring (such as conductors 328 and 330), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0208] A wiring layer may be provided on insulator 326 and conductor 330. For example, in FIG. 10, insulators 350, 352, and 354 are sequentially stacked and provided. Also, a conductor 356 is formed in insulators 350, 352, and 354. Conductor 356 has a function as a plug connected to transistor 300 or a wiring. Note that conductor 356 can be provided using the same material as conductors 328 and 330.

[0209] Note that, for example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similar to the insulator 324. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 300 and the storage unit 100 including the transistor 700, the plurality of transistors 800, and the transistor 900 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 300 to the storage unit 100 can be suppressed.

[0210] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0211] It is preferable to use an insulator having a barrier property against hydrogen on the insulator 354 and the conductor 356. For example, in FIG. 10, an insulator 360 is provided on the insulator 354 and the conductor 356. Note that an opening may be provided in the insulator 360, and a conductor may be formed so as to be electrically connected to the conductor 356. At this time, the conductor has a function as a plug or a wiring. Further, the conductor can be provided using the same material as the conductor 328 and the conductor 330. In particular, the conductor preferably includes a conductor having a barrier property against hydrogen.

[0212] Also, by using an insulator having a barrier property against hydrogen for the insulator 360 and a conductor having a barrier property against hydrogen for the conductor, the transistor 300 can be separated from the transistor 700, the plurality of transistors 800, and the transistor 900 described later by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 300 to the transistor 700, the plurality of transistors 800, and the transistor 900 can be suppressed.

[0213] Next, the transistor 700 included in the memory unit 100, the plurality of transistors 800, the transistor 900, and the insulator, conductor, etc. formed around them will be described.

[0214] FIG. 10 shows an example in which the memory unit 100 has a three-dimensional NAND-type memory circuit. The memory unit 100 of the information processing apparatus shown in FIG. 10 includes a transistor 700, a plurality of transistors 800, and a transistor 900 as components of a three-dimensional NAND-type memory circuit. Note that the transistor 700 and the transistor 900 correspond to transistors for selecting a plurality of transistors 800 located in the same opening, and the transistor 800 corresponds to a cell transistor for storing data. In this specification, etc., the transistor 700, the plurality of transistors 800, and the transistor 900 located in the same opening may be referred to as a string.

[0215] The memory unit 100 shown in FIG. 10 is provided on the control unit 200. Also, the memory unit 100 has insulators 111 to 117, insulator 121, insulator 122, insulator 131, insulator 132, insulator 133, conductors 151 to 156, and semiconductors 141 to 143 above the control unit 200.

[0216] The insulator 111 is provided above the control unit 200. Therefore, the insulator 360 located below the insulator 111 is preferably formed by a film formation method with good flatness. Further, it is preferable that CMP processing is performed on the insulator 360.

[0217] As the insulator 111, for example, a material containing silicon oxide or silicon oxynitride can be used. Further, for example, an insulator containing a material selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. can be used in a single layer or in a laminate.

[0218] The conductor 151 is provided laminated on the insulator 111. As an example, the conductor 151 functions as a wiring for applying a predetermined potential to all the strings of the memory unit 100.

[0219] As the conductor 151, for example, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used. Further, a conductive material containing the metal elements and oxygen contained in the metal oxide described in Embodiment 6 may be used. Also, a conductive material containing metal elements such as titanium and tantalum and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride may be used. Also, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, etc. may be used. Also, for example, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen or water mixed in from surrounding insulators or the like.

[0220] There is no particular limitation on the method for forming the conductor 151. For example, film formation can be carried out by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE (Molecular Beam Epitaxy) method, an ALD (Atomic Layer Deposition) method, a PLD (Pulsed Laser Deposition) method, etc.

[0221] As the insulators 112 to 117, for example, the same material as that of the insulator 111 can be used. Further, as the insulators 112 to 117, for example, a material having a low dielectric constant is preferably used. By using a material having a low dielectric constant as the insulators 112 to 117, the values of the parasitic capacitances generated by the conductors 152 to 156 and the insulators 112 to 117 can be reduced. Therefore, the driving speed of the memory unit 100 can be improved.

[0222] There is no particular limitation on the method for forming the insulators 112 to 117. For example, film formation can be performed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like.

[0223] The conductor 152 functions as the gate of the transistor 900 and the wiring electrically connected to the gate. Further, the conductors 153 to 155 function as the gates of the plurality of transistors 800 and the wiring electrically connected to the gates. Further, the conductor 156 functions as the gate of the transistor 700 and the wiring electrically connected to the gate.

[0224] As the conductors 152 to 156, for example, the same material as that of the conductor 151 can be used. Further, as the method for forming the conductors 152 to 156, the same method as that of the conductor 151 can be used.

[0225] Further, openings are provided in the insulators 112 to 117 and the conductors 152 to 156. The insulators 121, 122, 131 to 133, and the semiconductors 141 to 143 are provided in the openings.

[0226] The semiconductor 141 is provided so as to be in contact with a part of the side surface and the bottom surface of the opening. Specifically, the semiconductor 141 is provided on a part of the conductor 151 and is provided so as to cover a part of the insulator 112 on the side surface of the opening.

[0227] As the semiconductor 141, for example, it is preferable to use silicon in which impurities are diffused. As the impurities, n-type impurities (donors) can be used. As the n-type impurities, for example, phosphorus, arsenic, etc. can be used. Further, as the impurities, p-type impurities (acceptors) can be used. As the p-type impurities, for example, boron, aluminum, gallium, etc. can be used. Further, as the silicon, for example, single-crystalline silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon, etc. can be used. Further, as the semiconductor 141, other than silicon, metal oxides with a high carrier concentration may be applicable in some cases. Also, semiconductors such as Ge, and compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. may be applicable in some cases.

[0228] Note that the materials applied to the semiconductor 142 and the semiconductor 143 described later are preferably the same materials as the semiconductor 141, and in some cases, the carrier concentration of the semiconductor 142 is preferably lower than that of the semiconductor 141 and the semiconductor 143.

[0229] For example, when applying silicon in which p-type impurities are diffused as the semiconductor 141, after forming the semiconductor 141 on the conductor 151, it is preferable to add p-type impurities such as boron, aluminum, gallium, etc. to the semiconductor 141. Thereby, a p-type region is formed in the semiconductor 141. Also, for example, when applying silicon in which n-type impurities are diffused, after forming the semiconductor 141 on the conductor 151, it is preferable to add n-type impurities such as phosphorus, arsenic, etc. to the semiconductor 141. Thereby, an n-type region is formed in the semiconductor 141.

[0230] Also, as an example, when applying a metal oxide as the semiconductor 141, after forming the semiconductor 141 on the conductor 151, it is preferable to add a metal element, etc. to the semiconductor 141. Thereby, the carrier concentration in the semiconductor 141 can be increased. In particular, when applying the metal oxide described in Embodiment 6 as the semiconductor 141, an n-type region (n+ A region is formed. Further, instead of adding a metal element or the like to the semiconductor 141, heat treatment may be performed after adding water, hydrogen, or the like to cause oxygen deficiency in the semiconductor 141. Since an n-type region is formed in the region where oxygen deficiency occurs in the semiconductor 141, as a result, the carrier concentration of the semiconductor 141 increases.

[0231] The insulator 121 is provided so as to contact a part of the bottom surface of the opening. Specifically, the insulator 121 is provided so as to cover a part on the semiconductor 141 and the conductor 152 on the side surface of the opening.

[0232] The insulator 121 functions as a gate insulating film of the transistor 900.

[0233] As the insulator 121, for example, silicon oxide, silicon oxynitride, or the like can be used. In particular, when a metal oxide is used as the semiconductor 142 described later, the insulator 121 is preferably a material that releases oxygen by heating. By providing the oxygen-containing insulator 121 in contact with the metal oxide applied as the semiconductor 142, the oxygen deficiency in the metal oxide can be reduced, and the reliability of the transistor 900 can be improved.

[0234] There is no particular limitation on the film formation method of the insulator 121. However, since the insulator 121 is formed on the side surface of the opening provided in the insulator 112, the conductor 152, and the insulator 113, a film formation method with high film formability is required. Examples of the film formation method with high film formability include the ALD method.

[0235] The insulator 131 is provided so as to contact a part of the side surface of the opening. Specifically, the insulator 131 is provided so as to cover the conductors 153 to 155 on the side surface of the opening. Therefore, the insulator 131 is also provided so as to cover the insulators 114 and 115 on the side surface of the opening.

[0236] The insulator 132 is provided so as to be in contact with the insulator 131. Further, the insulator 133 is provided so as to be in contact with the insulator 132. That is, the insulators 131 to 133 are laminated in order from the side surface to the center of the opening.

[0237] The insulator 131 functions as a gate insulating film of the transistor 800. Further, the insulator 132 functions as a charge storage layer of the transistor 800. Further, the insulator 133 functions as a tunnel insulating film of the transistor 800.

[0238] As the insulator 131, for example, silicon oxide or silicon oxynitride is preferably used. Further, as the insulator 131, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used. Further, the insulator 131 may be an insulator in which these are laminated. By making the insulator 131 thicker than the insulator 133, charge can be transferred from the semiconductor 142 described later to the insulator 132 through the insulator 133.

[0239] As the insulator 132, for example, silicon nitride or silicon oxynitride can be used. However, the materials applicable to the insulator 132 are not limited to these.

[0240] As the insulator 133, for example, silicon oxide or silicon oxynitride is preferably used. Further, as the insulator 133, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium may be used. Further, the insulator 133 may be an insulator in which these are laminated.

[0241] The insulator 122 is provided so as to be in contact with a part of the side surface of the opening. Specifically, it is provided so as to cover the conductor 156 on the side surface of the opening.

[0242] The insulator 122 functions as a gate insulating film of the transistor 700.

[0243] As the insulator 122, for example, the same material as the insulator 121 can be used. Further, as the method for forming the insulator 122, the same method as the insulator 121 can be used.

[0244] The semiconductor 142 is provided so as to be in contact with the side surfaces of the formed insulator 121, insulator 133, and insulator 122 in the opening.

[0245] The semiconductor 142 functions as a channel formation region of the transistors 700, 800, 900 and a wiring for electrically connecting the transistors 700, 800, 900 in series.

[0246] As the semiconductor 142, for example, it is preferable to use silicon. Further, as the silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used. Further, as the semiconductor 142, in addition to silicon, metal oxides may be applicable in some cases. Further, semiconductors such as Ge, and compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, SiGe may be applicable in some cases.

[0247] The semiconductor 143 is provided so as to fill the opening after the semiconductor 141, semiconductor 142, insulator 121, insulator 122, insulator 131, insulator 132, and insulator 133 are formed in the opening. Specifically, the semiconductor 143 is provided so as to be in contact with the insulator 122 and on the semiconductor 142 and in contact with the side surface of the insulator 117.

[0248] As the semiconductor 143, for example, it is preferable to use the same material as the semiconductor 141. Therefore, it is preferable that the polarities of the semiconductor 141 and the semiconductor 143 are equal.

[0249] A wiring layer may be provided on the insulator 117 and the semiconductor 143. For example, in FIG. 10, as the wiring layer, an insulator 382 and an insulator 384 are provided by being laminated in order. Further, a conductor 386 is formed on the insulator 382 and the insulator 384. The conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using the same materials as the conductor 328 and the conductor 330.

[0250] Note that the information processing apparatus according to an aspect of the present invention is not limited to the configuration of the NAND-type memory circuit included in the storage unit 100 shown in FIG. 10. The NAND-type memory circuit applied to the information processing apparatus according to an aspect of the present invention may have a configuration different from that of the NAND-type memory circuit shown in FIG. 10.

[0251] <Configuration Example 2 of Information Processing Apparatus> FIG. 12 shows a configuration example of an information processing apparatus different from that of FIG. 10. The information processing apparatus shown in FIG. 12 has a configuration in which the configuration of the storage unit 100 of the information processing apparatus in FIG. 10 is changed. Specifically, the storage unit 100 of the information processing apparatus in FIG. 12 has the configuration of the storage unit in FIG. 4A described in Embodiment 2.

[0252] In the storage unit 100 of the information processing apparatus shown in FIG. 12, as an example, a memory cell MC[1] included in a three-dimensional structure NAND-type memory circuit has a transistor RTr, a transistor WTr, and a capacitor CS.

[0253] Further, the storage unit 100 shown in FIG. 12 is provided on the control unit 200 in the same manner as the information processing apparatus in FIG. 10. Further, the storage unit 100 has insulators 211 to 215, insulators 240 to 243, conductors 221, 222, conductors 250 to 253, semiconductors 231, and semiconductors 232 above the control unit 200.

[0254] The insulator 240 is provided above the control unit 200. Therefore, the insulator 360 located below the insulator 240 is preferably formed by a film forming method with good flatness. Also, it is preferable that CMP processing is performed on the insulator 360.

[0255] As the insulator 240, for example, a material applicable to the insulator 111 can be used.

[0256] The insulator 241 is provided laminated on the insulator 240.

[0257] As the insulator 241, for example, similar to the insulator 240, a material applicable to the insulator 111 can be used.

[0258] Also, a conductor 250 is embedded in the insulator 240, and a conductor 251 is embedded in the insulator 241. The conductor 250 and the conductor 251 have functions as plugs or wirings. Also, similar to FIG. 10, conductors having functions as plugs or wirings shown in FIG. 12 may be given the same reference numeral collectively for a plurality of structures. Also, in this specification etc., a wiring and a plug connected to the wiring may be an integral body. That is, there are cases where a part of the conductor functions as a wiring, and cases where a part of the conductor functions as a plug.

[0259] As the conductor 250 and the conductor 251, for example, materials applicable to the conductor 328 and the conductor 330 can be used.

[0260] The insulator 211 is provided on the insulator 241. Also, the conductor 221 is provided on the insulator 211. Also, the insulator 212 is provided on the conductor 221. Also, the conductor 222 is provided on the insulator 212. That is, the insulator 211, the conductor 221, the insulator 212, and the conductor 222 are laminated in this order (these are referred to as a laminate). Also, the storage unit 100 of the information processing apparatus in FIG. 12 has as many laminates as the number of memory cells MC included in one string.

[0261] Also, in the manufacturing process of the information processing apparatus shown in FIG. 12, openings are provided in the insulator 211, the conductor 221, the insulator 212, and the conductor 222 by forming a resist mask and performing an etching process or the like. At this time, the conductor 221 is selectively removed so that a recess is formed by the insulator 211, the conductor 221, and the insulator 212. In this case, it is preferable that the conductor 221 be made of a material having an etching rate higher than those of the insulator 211, the insulator 212, and the conductor 222.

[0262] Note that the resist mask can be formed by appropriately using, for example, a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, a photomask is not used, so that the manufacturing cost can be reduced. Regarding the etching process, either a dry etching method or a wet etching method may be used, or both may be used.

[0263] Also, although details will be described later, an insulator 213, a semiconductor 231, an insulator 214, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are sequentially formed in the opening formed by the etching process.

[0264] As the insulator 211 and the insulator 212, for example, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse. Therefore, as the insulator 211 and the insulator 212, for example, the same material as the insulator 111 can be used.

[0265] As the conductor 221 and the conductor 222, for example, it is preferable to use a material applicable to the conductor 151. In particular, as the conductor 221 and the conductor 222, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen.

[0266] An insulator 213 and a semiconductor 231 are sequentially formed on the side surface of the opening formed by the etching process described above. Further, an insulator 214 is formed so as to fill the recess of the opening.

[0267] As a method for forming the insulator 214, for example, first, the insulator 214 is formed on the side surface of the opening so that the concave portion of the opening is filled, and then a part of the insulator 214 is removed by an etching process while leaving the insulator 214 in the concave portion and exposing the semiconductor 231.

[0268] As the insulator 213, for example, silicon oxide or silicon oxynitride can be used. Further, as the insulator 213, for example, aluminum oxide, hafnium oxide, or an oxide having aluminum and hafnium can be used. Further, the insulator 213 may be an insulator in which these are laminated.

[0269] As the semiconductor 231, it is preferable to use the metal oxide described in Embodiment 6. In this embodiment, hereinafter, it is assumed that a metal oxide is applied as the semiconductor 231. In particular, it is preferable to use CAAC-OS, which will be described later, as the metal oxide. For example, when polycrystalline silicon is used for the semiconductor 231, the electron trap density may increase due to grain boundaries that can be formed in the polycrystalline silicon, and the transistor characteristics may vary greatly. On the other hand, since no clear grain boundaries are confirmed in CAAC-OS, variations in transistor characteristics can be suppressed.

[0270] Further, before forming the insulator 214, oxygen can be supplied to the metal oxide of the semiconductor 231 by performing a heat treatment on the formed semiconductor 231 in an oxygen atmosphere. Then, after forming the insulator 214, the resistance of the region exposed at the opening of the semiconductor 231 can be reduced by performing a supply process of impurities or the like to the metal oxide of the semiconductor 231. That is, the region in contact with the insulator 214 of the semiconductor 231 becomes a high-resistance region, and the region not in contact with the insulator 214 of the semiconductor 231 becomes a low-resistance region.

[0271] In addition, examples of the supply process of impurities or the like to the metal oxide of the semiconductor 231 include forming a conductor on the side surface of the opening and removing the conductor after filling the recess of the opening with the insulator 214. When the conductive film contacts the metal oxide of the semiconductor 231, the metal elements contained in the conductive film may diffuse into the semiconductor 231 to form a metal compound with the constituent elements of the semiconductor 231. A low-resistance region is formed in the semiconductor 231 by this metal compound.

[0272] As the insulator 214, it is preferable that it is not a component that forms a compound with the components contained in the semiconductor 231 at the interface with the previously formed semiconductor 231 and in the vicinity of the interface. Specifically, for example, silicon oxide or the like can be used as the insulator 214.

[0273] Thereafter, an insulator 215, a semiconductor 232, an insulator 216, and a conductor 223 are sequentially formed on the formation surfaces of the semiconductor 231 and the insulator 214. It is assumed that the opening provided in the laminate is filled by the formation of the conductor 223.

[0274] As the insulator 215 and the insulator 216, it is preferable to use a material applicable to the insulator 213, for example.

[0275] As the semiconductor 232, it is preferable to use a metal oxide described in Embodiment 6, for example, in the same manner as the semiconductor 231.

[0276] As the conductor 223, it is preferable to use a material applicable to the conductor 151, for example. In particular, as the conductor 223, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen.

[0277] An insulator 242 and an insulator 243 are sequentially provided on the upper part of the formed string.

[0278] As the insulator 242 and the insulator 243, a material applicable to the insulator 111 can be used, for example.

[0279] In addition, a conductor 252 is embedded in the insulator 242, and a conductor 253 is embedded in the insulator 243. The conductor 252 and the conductor 253 function as plugs or wirings.

[0280] As the conductor 252 and the conductor 253, for example, materials applicable to the conductor 328 and the conductor 330 can be used.

[0281] By performing the above-described steps, an information processing apparatus having the storage unit 100 of FIG. 4A can be manufactured.

[0282] Specifically, each of the wiring WBL, the wiring RBL, and the wiring BGL in the storage unit of FIG. 4A corresponds to the semiconductor 231, the semiconductor 232, and the conductor 223 in FIG. 12. Also, each of the wiring WWL and the wiring RWL in the storage unit of FIG. 4A corresponds to the conductor 221 and the conductor 222.

[0283] Therefore, a capacitor CS is configured with the conductor 222 as one electrode, the region of the insulator 213 in contact with the conductor 222 as a dielectric, and the region of the semiconductor 231 overlapping the conductor 222 as the other electrode. Also, a transistor RTr is configured with the region of the semiconductor 231 overlapping the conductor 222 as a gate, the region of the insulator 215 overlapping the conductor 222 as a gate insulating film, the region of the semiconductor 232 overlapping the conductor 222 as a channel formation region, the region of the insulator 216 overlapping the conductor 222 as a gate insulating film, and the region of the conductor 223 overlapping the conductor 222 as a back gate. Further, a transistor WTr is configured with the conductor 221 as a gate, the insulator 213 overlapping the conductor 221 as a gate insulating film, and the region of the semiconductor 231 overlapping the conductor 221 as a channel formation region.

[0284] In addition, insulators, conductors, semiconductors, etc. disclosed in this specification and the like can be formed by PVD (Physical Vapor Deposition) method or CVD (Chemical Vapor Deposition) method. Examples of the PVD method include sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) method, etc. Examples of the CVD method include formation using plasma CVD method or thermal CVD method. In particular, examples of the thermal CVD method include MOCVD (Metal Organic Chemical Vepor Deposition) method, ALD (Atomic Layer Deposition) method, etc.

[0285] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0286] In the thermal CVD method, the film may be formed by simultaneously feeding a source gas and an oxidizing agent into the chamber, setting the inside of the chamber at atmospheric pressure or reduced pressure, and reacting near the substrate or on the substrate to deposit on the substrate.

[0287] In addition, in the ALD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and raw material gases for the reaction may be sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, by switching each switching valve (also referred to as a high-speed valve), two or more types of raw material gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the first raw material gas so that the plurality of types of raw material gases do not mix, and then the second raw material gas is introduced. When introducing the inert gas simultaneously, the inert gas serves as a carrier gas, and an inert gas may also be introduced simultaneously when introducing the second raw material gas. Alternatively, after discharging the first raw material gas by vacuum exhaust instead of introducing the inert gas, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form a first thin layer, and reacts with the second raw material gas introduced later, so that the second thin layer is laminated on the first thin layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times of repeating the gas introduction sequence, precise film thickness adjustment is possible, which is suitable for manufacturing fine FETs.

[0288] Thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Moreover, it is not limited to these combinations, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0289] For example, when forming a hafnium oxide film using a film forming apparatus that utilizes ALD, two types of gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizing agent. Also, as other materials, there are tetrakis(ethylmethylamide)hafnium and the like.

[0290] For example, when forming an aluminum oxide film using a film forming apparatus that utilizes ALD, two types of gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizing agent. Also, as other materials, there are tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

[0291] For example, when forming a silicon oxide film using a film forming apparatus that utilizes ALD, hexachlorodisilane is adsorbed onto the film forming surface, and radicals of an oxidizing gas (O2, nitrous oxide) are supplied to react with the adsorbed substance.

[0292] For example, when forming a tungsten film using a film forming apparatus that utilizes ALD, WF6 gas and B2H6 gas are sequentially introduced repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are sequentially introduced repeatedly to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0293] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film-forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are sequentially introduced repeatedly to form a GaO layer. Further, thereafter, Zn(CH3)2 gas and O3 gas are sequentially introduced repeatedly to form a ZnO layer. Note that the order of these layers is not limited to this example. Also, a mixed oxide layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed using these gases. Note that instead of O3 gas, H2O gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0294] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0295] (Embodiment 4) In this embodiment, an application example of an information processing apparatus according to one aspect of the present invention will be described.

[0296] Generally, a computer has, as components, a processor, a main memory, a storage, etc. on a motherboard, and each component is electrically connected by, for example, bus wiring. For this reason, as the bus wiring becomes longer, the parasitic resistance increases, and thus the power consumption required for signal transmission also increases.

[0297] Specifically, as for the computer, for example, it has a configuration as shown in FIG. 13A. The computer has a motherboard BD, and on the motherboard BD, an arithmetic processing unit (processor, CPU, etc.) 10, a main memory (such as DRAM (Dynamic Random Access Memory)) 30, a storage (a three-dimensional structure NAND-type storage device, a 3D OS NAND-type storage device, etc.) 40, an interface 60, etc. are provided. Note that in FIG. 13, an SRAM (Static Random Access Memory) 20 that also functions as a main memory is shown, but it does not necessarily have to be provided on the motherboard BD.

[0298] Note that FIG. 13 shows a configuration in which the arithmetic processing unit 10 has a register 11.

[0299] In FIG. 13A, the arithmetic processing unit 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. Also, the main memory 30 is electrically connected to the SRAM 20 and the storage 40.

[0300] Note that each component of the computer in FIG. 13A is electrically connected by a bus wiring BSH. That is, the more components the computer has, or the larger the motherboard BD becomes, the longer the bus wiring BSH to be routed, so the power consumption required for signal transmission increases.

[0301] By the way, the computer in FIG. 13A may integrate each component of the computer into one chip and make it into a monolithic IC (Integrated Circuit). Also, at this time, the information processing device 50 such as FIG. 1 described in the above embodiment can be applied as the main memory 30 and the storage 40. In this way, FIG. 13B shows the computer in FIG. 13A made into a monolithic IC.

[0302] The monolithic IC of FIG. 13B has a circuit layer LGC on a semiconductor substrate having Si. Further, it has a memory layer STR on the upper part of the circuit layer LGC, and has a circuit layer OSC on the upper part of the memory layer STR.

[0303] The circuit layer LGC has a plurality of circuits including, for example, Si transistors formed on a semiconductor substrate SBT having Si. As a part of the plurality of circuits, for example, in FIG. 13A, it can be an arithmetic processing unit 10, an SRAM 20, etc. Further, when an information processing device such as FIG. 1 is applied as the main memory 30 and the storage 40, as a part of the plurality of circuits, it can be a controller 1197 included in the information processing device 50.

[0304] In particular, as an example, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors.

[0305] The memory layer STR functions as a storage unit having Si transistors and / or OS transistors. As the memory layer STR, for example, it can be a three-dimensional structure NAND-type memory circuit, a 3D OS NAND-type memory circuit, etc. Therefore, the memory layer STR has a storage unit 1196 in the information processing device of FIG. 1, a storage 40 in FIG. 13A, etc.

[0306] Note that by using a 3D OS NAND-type memory circuit, the power consumption of the monolithic IC of FIG. 13B can be reduced.

[0307] The circuit layer OSC has a plurality of circuits including, for example, OS transistors. As a part of the plurality of circuits, for example, it can be a circuit different from the circuits included in the circuit layer LGC such as an arithmetic processing unit 10, an SRAM 20, etc.

[0308] In the monolithic IC of FIG. 13B, since there is no bus wiring BSH for routing on the motherboard, the wiring for electrically connecting the respective components is shortened. For this reason, the power consumption required for signal transmission can be reduced.

[0309] Also, the monolithic IC of FIG. 13B has an information processing device 50. For this reason, the information processing device 50 functions as the storage 40 and the main memory 30 in FIG. 13A. For this reason, the monolithic IC of FIG. 13B can use the main memory 30 as the storage unit 1196 of the storage layer STR.

[0310] Due to the point of not providing the bus wiring BSH and the point of using the storage unit 1196 as an alternative to the main memory 30, the monolithic IC of FIG. 13B can reduce the circuit area compared to the computer of FIG. 13A.

[0311] Next, an example of the storage hierarchy of the computer of FIG. 13A and the monolithic IC of FIG. 13B is shown in FIGS. 14A and 14B, respectively.

[0312] Generally, for the storage hierarchy, a storage device located in the upper layer is required to have a faster operating speed, and a storage device located in the lower layer is required to have a larger storage capacity and a higher recording density. In FIG. 14A, as an example, in order from the top layer, a register included in the CPU (arithmetic processing unit 10), an SRAM, a DRAM included in the main memory 30, and a three-dimensional structure NAND-type memory circuit included in the storage 40 are shown.

[0313] The register and the SRAM included in the arithmetic processing unit 10 are used for temporarily storing arithmetic results and the like, so the access frequency from the arithmetic processing unit 10 is high. Therefore, a faster operating speed is required than the storage capacity. Also, the register has a function of holding setting information of the arithmetic processing unit and the like.

[0314] The DRAM included in the main memory 30 has a function of holding programs and data read from the storage 40 as an example. The recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0315] The storage 40 has a function of holding data that needs to be stored long-term and various programs used in the arithmetic processing unit. Therefore, the storage 40 is required to have a storage capacity larger than the operating speed and a high recording density. The recording density of the storage device used for the storage 40 is approximately 0.6 to 6.0 Gbit / mm 2 is. For this reason, as the storage 40, a three-dimensional NAND-type memory circuit (3D OS NAND), a hard disk drive (HDD), etc. are used.

[0316] By the way, as described above, since the monolithic IC in FIG. 13B has the roles of the storage 40 and the main memory 30 in FIG. 1 of the information processing apparatus 50, the memory hierarchy of the monolithic IC in FIG. 13B is as shown in FIG. 14B.

[0317] That is, in the monolithic IC in FIG. 13B, the memory cells (cells of 3D OS NAND) included in the storage unit 100 of the information processing apparatus 50 in FIG. 1 can be treated not only as the cache memory of the storage unit 100 but also as the main memory 30 in the computer in FIG. 13A. For this reason, in the monolithic IC in FIG. 13B, there is no need to provide a main memory 30 such as a DRAM, so the circuit area of the monolithic IC in FIG. 13B can be reduced, and the power consumption required to operate the main memory 30 such as a DRAM can be reduced.

[0318] Note that the configuration of the monolithic IC shown in FIG. 13B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in FIG. 13B may be changed according to the situation. For example, in the monolithic IC of FIG. 13B, when a high-speed memory of 1 GHz or more is required as the SRAM, for example, the SRAM may be mounted on the arithmetic processing unit.

[0319] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0320] (Embodiment 5) In this embodiment, an example of a method for writing to a NAND-type storage device such as this specification will be described.

[0321] FIG. 15A shows the electrical connection between an arithmetic processing unit (processor, CPU, etc.) 70 and a storage device (three-dimensional structure NAND-type storage device, 3D OS NAND-type storage device) 80. Specifically, the arithmetic processing unit 70 is electrically connected to the storage device 80 via a plurality of wirings 90.

[0322] The arithmetic processing unit 70 has a function of transmitting data for writing to the memory cells included in the storage device 80 to the storage device 80 via a plurality of wirings 90. That is, the plurality of wirings 90 function as write bit lines corresponding to the wiring WBL and the like of the above-described embodiment. For example, when the storage device 80 is a storage device having a NAND structure and has a plurality of strings, each of the plurality of wirings 90 is electrically connected to the plurality of strings.

[0323] By the way, in order to increase the data writing speed to the memory cells included in the storage device 80, using a material with a low resistance value for the formation of the wiring 90, shortening the length of the wiring 90, and the like can be mentioned.

[0324] Also, as a means of increasing the data writing speed to the memory cells included in the memory device 80, the number of wirings 90 may be increased. That is, by increasing the number of wirings 90 (the number of strings of the memory device 80 electrically connected to the wirings 90), the number of data that can be written to the memory cells at one time can be increased.

[0325] Next, with reference to FIG. 15B, the method of transmitting write data will be described.

[0326] The arithmetic processing unit 70 includes, as an example, latch circuits LT1[1] to latch circuits LT1[z] (where z is an integer of 2 or more), latch circuits LT2[1] to latch circuits LT2[z], and wirings 90[1] to wirings 90[z]. Further, the memory device 80 includes, as an example, NAND type memory devices, and has strings STG[1] to strings STG[z].

[0327] In the arithmetic processing unit 70, the latch circuits LT1[1] to the latch circuits LT1[z] constitute a shift register. Therefore, a wiring CLK for transmitting a clock signal is electrically connected to each clock input terminal of the latch circuits LT1[1] to the latch circuits LT1[z]. The shift register can sequentially transmit the write data DA input to the input terminal of the latch circuit LT1[1] to the latch circuits LT1[2] to the latch circuits LT1[z] according to the number of pulse voltages input as the clock signal from the wiring CLK.

[0328] Also, the output terminal of the latch circuit LT1[v] (where v is an integer of 1 or more and z or less here) is electrically connected to the input terminal of the latch circuit LT2[v]. Therefore, the data DA output from the latch circuit LT1[v] is input to the latch circuit LT2[v]. Further, the latch circuit LT2[v] is electrically connected to the string STG[v] via the wiring 90[v].

[0329] The wiring ENL is electrically connected to the clock input terminals of each of the latch circuits LT2[1] to LT2[z]. The wiring ENL functions as a wiring for transmitting a trigger signal for transmitting the data DA from the arithmetic processing unit 70 to the storage device 80.

[0330] By serial transmission, when the data DA is input to the latch circuit LT1[1], the data DA is sequentially input to the latch circuit LT1[1]. Here, it is assumed that the data DA is sequentially input to the latch circuits LT1[1] to LT1[z], and the data DA[1] to data DA[z] are stored in each of the latch circuits LT1[1] to LT1[z].

[0331] At this time, the data DA[1] to data DA[z] are output from the output terminals of each of the latch circuits LT1[1] to LT1[z]. Also, each of the data DA[1] to data DA[z] is input to the latch circuits LT2[1] to LT2[z].

[0332] In this way, the data DA input by serial transmission can be distributed to the latch circuits LT1[1] to LT1[z] as the data DA[1] to data DA[z]. In other words, the data DA input by serial transmission can be distributed to the wirings 90[1] to 90[z] as the data DA[1] to data DA[z].

[0333] Thereafter, by the wiring ENL, a trigger signal is applied to the clock signal input terminals of each of the latch circuits LT2[1] to LT2[z], so that the data DA[1] to data DA[z] can be input in parallel from each of the latch circuits LT2[1] to LT2[z] to the strings STG[1] to STG[z] of the storage device 80 via the wirings 90[1] to 90[z].

[0334] By applying the above-described configuration and driving method, data to be written to the serially transmitted memory device 80 can be sent in parallel to the strings STG[1] to STG[z] of the memory device 80.

[0335] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0336] (Embodiment 6) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0337] The metal oxide preferably contains at least indium or zinc. Particularly preferably, it contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. may be contained.

[0338] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 16A. FIG. 16A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0339] As shown in FIG. 16A, oxide semiconductors are roughly classified into "Amorphous", "Crystalline", and "Crystal". Also, "Amorphous" includes completely amorphous. Further, "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Also, "Crystal" includes single crystal and poly crystal.

[0340] Note that the structure within the thick frame shown in FIG. 16A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, this structure can be rephrased as a structure that is energetically unstable "Amorphous" and is completely different from "Crystal".

[0341] Note that the crystal structure of a film or a substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of a CAAC-IGZO film classified as "Crystalline" is shown in FIG. 16B. Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 16B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 16B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 16B is 500 nm.

[0342] As shown in FIG. 16B, in the XRD spectrum of the CAAC-IGZO film, peaks indicating distinct crystallinity are detected. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected near 2θ = 31°. As shown in FIG. 16B, the peak near 2θ = 31° is asymmetric about the axis of the angle at which the peak intensity (Intensity) was detected.

[0343] Also, the crystal structure of the film or the substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 16C. FIG. 16C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 16C is near In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0344] As shown in FIG. 16C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0345] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from FIG. 16A. For example, the oxide semiconductor is divided into a single-crystalline oxide semiconductor and other non-single-crystalline oxide semiconductors. Examples of the non-single-crystalline oxide semiconductor include the above-mentioned CAAC-OS and nc-OS. Also, the non-single-crystalline oxide semiconductor includes a polycrystalline oxide semiconductor, an amorphous-like oxide semiconductor (a-like OS), an amorphous oxide semiconductor, and the like.

[0346] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0347] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. Here, the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Here, strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no clear orientation in the a-b plane direction.

[0348] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0349] In the In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and the element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain the element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0350] When performing structural analysis on the CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0351] Also, for example, in the electron diffraction pattern of the CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0352] When observing the crystal region from the above-mentioned specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be an irregular hexagon. Further, in the above-mentioned strain, there may be a lattice arrangement such as a pentagon or a heptagon. In CAAC-OS, even in the vicinity of the strain, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is considered to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0353] A crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries serve as recombination centers, and carriers are likely to be captured, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which no clear grain boundary is confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. To form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0354] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundary confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is unlikely to occur. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, it can also be said that CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen deficiency). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is resistant to heat and has high reliability. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0355] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS has no regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the whole film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scan. Further, when electron beam diffraction (also referred to as limited field electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when electron beam diffraction (also referred to as nanobeam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0356] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film compared with nc-OS and CAAC-OS.

[0357] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0358] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0359] Furthermore, CAC-OS becomes a mosaic state by separating the material into a first region and a second region, and the first region has a structure distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0360] Here, the atomic number ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0361] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0362] Note that there may be cases where a clear boundary cannot be observed between the above first region and the above second region.

[0363] For example, in CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (first region) and the region mainly composed of Ga (second region) are unevenly distributed and have a mixed structure.

[0364] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (on / off function) to be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be enhanced to the maximum extent. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be realized.

[0365] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0366] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0367] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0368] For the transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, and even more preferably less than 1×10 10 cm -3 and 1×10 -9 cm -3 or more. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0369] In addition, since an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0370] In addition, the charge trapped in the trap levels of the oxide semiconductor takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0371] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of the impurity include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

[0372] <Impurities> Here, the effects of various impurities in the oxide semiconductor will be described.

[0373] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 Hereinafter, preferably 2×10 17 atoms / cm 3 or less.

[0374] Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0375] Further, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is contained in the oxide semiconductor, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is less than 5×10 19 atoms / cm 3 preferably less than 5×10 18 atoms / cm 3 or less, more preferably 1×10 18atoms / cm 3 Hereinafter, more preferably 5×10 17 atoms / cm 3 or less.

[0376] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, carriers such as electrons may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate carriers such as electrons. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, still more preferably 1×10 18 atoms / cm 3 or less.

[0377] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0378] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0379] (Embodiment 7) In this embodiment, an example of a semiconductor wafer on which an information processing apparatus or the like described in the above embodiment is formed, and an example of an electronic component in which the information processing apparatus is incorporated will be described.

[0380] <Semiconductor Wafer> First, an example of a semiconductor wafer on which an information processing apparatus or the like is formed will be described with reference to FIG. 17A.

[0381] The semiconductor wafer 4800 shown in FIG. 17A has a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that, on the upper surface of the wafer 4801, the portion without the circuit portions 4802 is a spacing 4803, which is an area for dicing.

[0382] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. Further, thereafter, the surface of the wafer 4801 on the side opposite to the side where the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. By this process, warpage of the wafer 4801 and the like can be reduced, and miniaturization as a component can be achieved.

[0383] As the next process, a dicing process is performed. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. Note that, in order to facilitate the dicing process, the spacing 4803 is preferably provided such that a plurality of scribe lines SCL1 are parallel, a plurality of scribe lines SCL2 are parallel, and the scribe line SCL1 and the scribe line SCL2 are perpendicular.

[0384] By performing the dicing process, a chip 4800a as shown in FIG. 17B can be cut out from the semiconductor wafer 4800. The chip 4800a has a wafer 4801a, a circuit portion 4802, and a spacing 4803a. Note that the spacing 4803a is preferably made as small as possible. In this case, the width of the spacing 4803 between adjacent circuit portions 4802 may be approximately equal to the kerf of the scribe line SCL1 or the kerf of the scribe line SCL2.

[0385] Note that the shape of the element substrate according to one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 17A. For example, a semiconductor wafer having a rectangular shape may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0386] <Electronic component> FIG. 17C shows a perspective view of the electronic component 4700 and the substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 17C has a chip 4800a in a mold 4711. Note that the chip 4800a shown in FIG. 17C has a structure in which a circuit portion 4802 is laminated. That is, as the circuit portion 4802, the information processing apparatus described in the above embodiment can be applied. FIG. 17C omits a part in order to show the inside of the electronic component 4700. The electronic component 4700 has a land 4712 outside the mold 4711. The land 4712 is electrically connected to an electrode pad 4713, and the electrode pad 4713 is electrically connected to the chip 4800a by a wire 4714. The electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 4702 to complete the mounting substrate 4704.

[0387] FIG. 17D shows a perspective view of the electronic component 4730. The electronic component 4730 is an example of a SiP (System in package) or an MCM (Multi Chip Module). In the electronic component 4730, an interposer 4731 is provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and a plurality of semiconductor devices 4710 are provided on the interposer 4731.

[0388] The electronic component 4730 has a semiconductor device 4710. As the semiconductor device 4710, for example, the semiconductor device described in the above embodiment, a wide-band memory (HBM: High Bandwidth Memory), or the like can be used. Further, as the semiconductor device 4735, an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a storage device can be used.

[0389] As the package substrate 4732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer 4731, a silicon interposer, a resin interposer, or the like can be used.

[0390] The interposer 4731 has a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Further, the interposer 4731 has a function of electrically connecting an integrated circuit provided on the interposer 4731 to an electrode provided on the package substrate 4732. For these reasons, the interposer may be referred to as a "redistribution substrate" or an "intermediate substrate". Further, a through electrode may be provided on the interposer 4731, and the integrated circuit and the package substrate 4732 may be electrically connected using the through electrode. In the case of a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

[0391] It is preferable to use a silicon interposer as the interposer 4731. Since it is not necessary to provide active elements in a silicon interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring formation of a silicon interposer can be performed by a semiconductor process, it is easy to form fine wirings, which is difficult in the case of a resin interposer.

[0392] In HBM, a large number of wirings need to be connected to achieve a wide memory bandwidth. Therefore, for the interposer on which HBM is implemented, fine and high-density wiring formation is required. Thus, it is preferable to use a silicon interposer for the interposer on which HBM is implemented.

[0393] In addition, in SiP, MCM, etc. using a silicon interposer, a decrease in reliability due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer is less likely to occur. Also, since the silicon interposer has high surface flatness, a connection failure between the integrated circuit provided on the silicon interposer and the silicon interposer is less likely to occur. In particular, in a 2.5D package (2.5-dimensional implementation) in which a plurality of integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0394] Also, a heat sink (heat dissipation plate) may be provided so as to overlap with the electronic component 4730. When providing a heat sink, it is preferable to make the heights of the integrated circuits provided on the interposer 4731 uniform. For example, in the electronic component 4730 shown in the present embodiment, it is preferable to make the heights of the semiconductor device 4710 and the semiconductor device 4735 uniform.

[0395] In order to mount the electronic component 4730 on another substrate, electrodes 4733 may be provided at the bottom of the package substrate 4732. FIG. 17D shows an example in which the electrodes 4733 are formed of solder balls. By providing solder balls in a matrix pattern at the bottom of the package substrate 4732, BGA (Ball Grid Array) mounting can be realized. Also, the electrodes 4733 may be formed of conductive pins. By providing conductive pins in a matrix pattern at the bottom of the package substrate 4732, PGA (Pin Grid Array) mounting can be realized.

[0396] The electronic component 4730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0397] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0398] (Embodiment 8) In this embodiment, an example of an electronic device having the information processing apparatus described in the above embodiment will be described. Note that FIGS. 18A to 18J illustrate a state in which an electronic component 4700 having the information processing apparatus is included in each electronic device.

[0399] [Mobile phone] The information terminal 5500 shown in FIG. 18A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided in the display unit 5511, and buttons are provided in the housing 5510.

[0400] By applying the information processing apparatus described in the above embodiment, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0401] [Wearable terminal] Further, FIG. 18B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0402] Similar to the information terminal 5500 described above, the wearable terminal can hold temporary files generated during the execution of an application by applying the information processing apparatus described in the above embodiment.

[0403] [Information terminal] Also, FIG. 18C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0404] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can hold temporary files generated during the execution of an application by applying the information processing apparatus described in the above embodiment.

[0405] Note that in the above description, a smartphone and a desktop information terminal are used as examples of the information processing apparatus and are illustrated in FIGS. 18A and 18C, respectively. However, information terminals other than smartphones and desktop information terminals can be applied. Examples of information terminals other than smartphones and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0406] [Electrical appliance] Also, FIG. 18D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0407] By applying the information processing apparatus described in the above embodiment to the electric refrigerator 5800, the electric refrigerator 5800 can be used as, for example, IoT (Internet of Things). By using IoT, the electric refrigerator 5800 can transmit and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of the food to and from information terminals as described above through the Internet or the like. Further, when transmitting the information, the electric refrigerator 5800 can hold the information as a temporary file in the information processing apparatus.

[0408] In this example, an electric refrigerator has been described as an electrical appliance. Other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, etc.

[0409] [Game console] In addition, FIG. 18E shows a portable game console 5200 which is an example of a game console. The portable game console 5200 includes a housing 5201, a display unit 5202, buttons 5203, etc.

[0410] Furthermore, FIG. 18F shows a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. Note that the controller 7522 can be connected to the main body 7520 either wirelessly or by wire. Although not shown in FIG. 18F, the controller 7522 can be provided with a display unit for displaying game images, a touch panel, a stick, a rotary knob, a slide knob, etc. that serve as input interfaces other than buttons. Also, the controller 7522 is not limited to the shape shown in FIG. 18F, and the shape of the controller 7522 may be changed variously according to the genre of the game. For example, in a shooting game such as a FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. Also, for example, in a music game or the like, a controller shaped like a musical instrument or a music device can be used. Furthermore, the stationary game machine may be configured to operate by a gesture and / or voice of a game player, equipped with a camera, a depth sensor, a microphone, etc. instead of using a controller.

[0411] In addition, the video of the game machine described above can be output by a display device such as a television device, a personal computer display, a game display, a head-mounted display, etc.

[0412] By applying the information processing apparatus described in the above embodiment to the portable game machine 5200, a portable game machine 5200 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence on the circuit itself, the peripheral circuit, and the module due to heat generation can be minimized.

[0413] Furthermore, by applying the information processing apparatus described in the above embodiment to the portable game machine 5200, it is possible to hold temporary files etc. necessary for the calculations that occur during the execution of the game.

[0414] In FIGS. 18E and 18F, a portable game machine is illustrated as an example of a game machine, but the information processing apparatus according to an aspect of the present invention is not limited thereto. Examples of the information processing apparatus according to an aspect of the present invention include, for example, a home stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0415] [Mobile body] The information processing apparatus described in the above embodiment can be applied to an automobile, which is a mobile body, and the periphery of the driver's seat of the automobile.

[0416] An automobile 5700, which is an example of a mobile body, is illustrated in FIG. 18G.

[0417] An instrument panel for providing various information is provided around the driver's seat of the automobile 5700 by displaying a speedometer, a tachometer, the driving distance, a fuel gauge, the gear state, the setting of the air conditioner, and the like. Further, a display device for indicating such information may be provided around the driver's seat.

[0418] In particular, the display device can project an image from an imaging device (not shown) provided in the automobile 5700 to supplement a field of view blocked by a pillar or a blind spot of the driver's seat, thereby enhancing safety.

[0419] Since the information processing apparatus described in the above embodiment can temporarily hold information, for example, the computer can be used to hold necessary temporary information in an automatic driving system of the automobile 5700 or a system that performs road guidance, danger prediction, and the like. The display device may be configured to display temporary information such as road guidance and danger prediction. Further, it may be configured to hold an image of a driving recorder provided in the automobile 5700.

[0420] In the above description, an automobile is described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like.

[0421] [Camera] The information processing apparatus described in the above embodiment can be applied to a camera.

[0422] FIG. 18H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, operation buttons 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0423] By applying the information processing apparatus described in the above embodiment to the digital camera 6240, a digital camera 6240 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence of the heat on the circuit itself, the peripheral circuits, and the modules can be minimized.

[0424] [Video camera] The information processing apparatus described in the above embodiment can be applied to a video camera.

[0425] FIG. 18I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operation keys 6304, a lens 6305, a connection unit 6306, etc. The operation keys 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0426] When recording the video captured by the video camera 6300, it is necessary to perform encoding according to the data recording format. By using the information processing device described above, the video camera 6300 can hold temporary files generated during encoding.

[0427] [ICD] The information processing device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0428] FIG. 18J is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 4700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0429] The ICD body 5400 is implanted in the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0430] The ICD main body 5400 has the function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia or ventricular fibrillation), treatment by electric shock is performed.

[0431] In order to appropriately perform pacing and electric shock, the ICD main body 5400 needs to constantly monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. Also, the ICD main body 5400 can store data on the heart rate obtained by the sensor etc., the number of times and time of treatment by pacing, etc. in the electronic component 4700.

[0432] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, since the ICD main body 5400 has a plurality of batteries, the safety can be enhanced. Specifically, even if some of the batteries of the ICD main body 5400 become unusable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0433] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals. For example, a system for monitoring heart activities such that physiological signals such as pulse, respiratory rate, heart rate, body temperature, etc. can be confirmed by an external monitoring device may be configured.

[0434] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0435] (Embodiment 9) In this embodiment, a computer having the information processing apparatus described in the above embodiment will be described.

[0436] The computer 9600 shown in FIG. 19A is an example of a large computer. A plurality of rack-mounted computers 9620 are stored in the rack 9610 in the computer 9600.

[0437] The computer 9620 can be configured, for example, as shown in the perspective view of FIG. 19B. In FIG. 19B, the computer 9620 has a motherboard 9630, and the motherboard 9630 has a plurality of slots 9631 and a plurality of connection terminals. A PC card 9621 is inserted into the slot 9631. In addition, the PC card 9621 has connection terminals 9623, 9624, and 9625, which are respectively connected to the motherboard 9630.

[0438] The PC card 9621 shown in FIG. 19C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. The PC card 9621 has a board 9622. The board 9622 also has a connection terminal 9623, a connection terminal 9624, a connection terminal 9625, a semiconductor device 9626, a semiconductor device 9627, a semiconductor device 9628, and a connection terminal 9629. Although FIG. 19C shows semiconductor devices other than the semiconductor device 9626, the semiconductor device 9627, and the semiconductor device 9628, for those semiconductor devices, the descriptions of the semiconductor device 9626, the semiconductor device 9627, and the semiconductor device 9628 described below may be referred to.

[0439] The connection terminal 9629 has a shape that can be inserted into the slot 9631 of the motherboard 9630, and the connection terminal 9629 functions as an interface for connecting the PC card 9621 and the motherboard 9630. Examples of the standard of the connection terminal 9629 include PCIe, etc.

[0440] The connection terminals 9623, 9624, and 9625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 9621. Also, for example, they can be used as interfaces for outputting signals calculated by the PC card 9621. Examples of the specifications of each of the connection terminals 9623, 9624, and 9625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. Also, when outputting video signals from the connection terminals 9623, 9624, and 9625, examples of the specifications include HDMI (registered trademark), etc.

[0441] The semiconductor device 9626 has terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) provided on the board 9622, the semiconductor device 9626 and the board 9622 can be electrically connected.

[0442] The semiconductor device 9627 has a plurality of terminals. By performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 9622, the semiconductor device 9627 and the board 9622 can be electrically connected. Examples of the semiconductor device 9627 include FPGA (Field Programmable Gate Array), GPU, CPU, etc. As the semiconductor device 9627, for example, the electronic component 4730 can be used.

[0443] The semiconductor device 9628 has a plurality of terminals. By performing, for example, reflow soldering on the terminals with respect to the wiring provided on the board 9622, the semiconductor device 9628 and the board 9622 can be electrically connected. Examples of the semiconductor device 9628 include a storage device, an information processing device, etc. As the semiconductor device 9628, for example, the electronic component 4700 can be used.

[0444] The computer 9600 can also function as a parallel computer. By using the computer 9600 as a parallel computer, for example, large-scale computations required for artificial intelligence learning and inference can be performed.

[0445] By using the semiconductor device according to one aspect of the present invention in the above-described various electronic devices and the like, it is possible to reduce the size, increase the speed, or reduce the power consumption of the electronic device. Further, since the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, the adverse effects on the circuit itself, the peripheral circuit, and the module due to the heat generation can be reduced. Further, by using the semiconductor device according to one aspect of the present invention, an electronic device with stable operation even in a high-temperature environment can be realized. Therefore, the reliability of the electronic device can be improved.

[0446] Subsequently, a configuration example of a computer system applicable to the computer 9600 will be described. FIG. 20 is a diagram for explaining a configuration example of a computer system 1000. The computer system 1000 is configured to include software and hardware. Note that the hardware included in the computer system may sometimes be referred to as an information processing apparatus.

[0447] Examples of the software constituting the computer system 1000 include an operating system including a device driver, middleware, various development environments, an application program related to AI (AI Application), and an application program unrelated to AI.

[0448] The device driver includes an application program for controlling external connection devices such as an auxiliary storage device, a display device, and a printer.

[0449] The hardware constituting the computer system 1000 includes a first arithmetic processing unit, a second arithmetic processing unit, and a first storage device. Further, the second arithmetic processing unit has a second storage device.

[0450] As the first arithmetic processing unit, for example, a central processing unit such as a Noff OS CPU may be used. The Noff OS CPU has a storage means (e.g., non-volatile memory) using OS transistors, and when operation is not required, it has a function of holding necessary information in the storage means and stopping the power supply to the central processing unit. By using the Noff OS CPU as the first arithmetic processing unit, the power consumption of the computer system 1000 can be reduced.

[0451] As the second arithmetic processing unit, for example, a GPU, an FPGA, etc. can be used. Note that it is preferable to use an AI OS Accelerator as the second arithmetic processing unit. The AI OS Accelerator is configured using OS transistors and has arithmetic means such as a multiply-accumulate circuit. The AI OS Accelerator consumes less power than a general GPU, etc. By using the AI OS Accelerator as the second arithmetic processing unit, the power consumption of the computer system 1000 can be reduced.

[0452] It is preferable to have a semiconductor device according to an aspect of the present invention as the first storage device and the second storage device. The semiconductor device according to an aspect of the present invention may have, for example, a 3D OS NAND type storage device. In this case, the 3D OS NAND type storage device can function as a cache, main memory, and storage. In addition, by using the 3D OS NAND type storage device, it becomes easier to realize a non-Neumann type computer system.

[0453] The 3D OS NAND type storage device consumes less power than a 3D NAND type storage device using Si transistors. By using the 3D OS NAND type storage device as the storage device, the power consumption of the computer system 1000 can be reduced. In addition, since the 3D OS NAND type storage device can function as universal memory, the number of components for configuring the computer system 1000 can be reduced.

[0454] By configuring the semiconductor device that constitutes the hardware with a semiconductor device including an OS transistor, it becomes easy to monolithically integrate the hardware including the central processing unit, arithmetic processing unit, and storage device. By monolithically integrating the hardware, not only miniaturization, weight reduction, and thickness reduction are achieved, but also further power consumption reduction becomes easy.

[0455] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

Description of Reference Numerals

[0456] ST1: String, ST2: String, ST3: String, L[1]: Memory cell, L[2]: Memory cell, L[n]: Memory cell, M[1]: Memory cell, M[2]: Memory cell, M[n]: Memory cell, N[1]: Memory cell, N[2]: Memory cell, N[n]: Memory cell, SL1: Wiring, SL2: Wiring, SL3: Wiring, BL1: Wiring, BL2: Wiring, BL3: Wiring, ISG: Signal, OSG: Signal, DT: Data, STP1: Step, STP2: Step, STP3: Step, STP4: Step, STP5: Step, STP6: Step, STP7: Step, STP8: Step, MC[1]: Memory cell, MC[2]: Memory cell, MC[n]: Memory cell, MC[1,1]: Memory cell, MC[j,1]: Memory cell, MC[n,1]: Memory cell, MC[1,i]: Memory cell, MC[j,i]: Memory cell, MC[n,i]: Memory cell, MC[1,m]: Memory cell, MC[j,m]: Memory cell, MC[n,m]: Memory cell, N1: Node, N2: Node, RWL[1]: Wiring, RWL[2]: Wiring, RWL[j]: Wiring, RWL[n]: Wiring, WWL[1]: Wiring, WWL[2]: Wiring, WWL[j]: Wiring, WWL[n]: Wiring, WBL: Wiring, WBL[1]: Wiring, WBL[i]: Wiring, WBL[m]: Wiring, RBL: Wiring, RBL[1]: Wiring, RBL[i]: Wiring, RBL[m]: Wiring, BGL: Wiring, BGL[1]: Wiring, BGL[i]: Wiring, BGL[m]: Wiring, WTr: Transistor, RTr: Transistor, CS: Capacitance, BLK_1: Block, BLK_h: Block, BLK_k: Block, BLK_2: Block, BLK_3: Block, MC[1]_1: Memory cell, MC[j]_1: Memory cell, MC[n]_1: Memory cell, MC[1]_h: Memory cell, MC[j]_h: Memory cell, MC[n]_h: Memory cell, MC[1]_k: Memory cell, MC[j]_k: Memory cell, MC[n]_k: Memory cell, MC[2]_1: Memory cell, MC[3]_1: Memory cell, MC[1]_2: Memory cell, MC[2]_2: Memory cell, MC[3]_2: Memory cell, MC[1]_3: Memory cell, MC[2]_3: Memory cell, MC[3]_3: Memory cell, RWL[1]_1: Wiring, RWL[j]_1: Wiring, RWL[n]_1: Wiring,RWL[1]_h: Wiring, RWL[j]_h: Wiring, RWL[n]_h: Wiring, RWL[1]_k: Wiring, RWL[j]_k: Wiring, RWL[n]_k: Wiring, RWL[2]_1: Wiring, RWL[3]_1: Wiring, RWL[1]_2: Wiring, RWL[2]_2: Wiring, RWL[3]_2: Wiring, RWL[1]_3: Wiring, RWL[2]_3: Wiring, RWL[3]_3: Wiring, WWL[1]_1: Wiring, WWL[j]_1: Wiring, WWL[n]_1: Wiring, WWL[1]_h: Wiring, WWL[j]_h: Wiring, WWL[n]_h: Wiring, WWL[1]_k: Wiring, WWL[j]_k: Wiring, WWL[n]_k: Wiring, WWL[2]_1: Wiring, WWL[3]_1: Wiring, WWL[1]_2: Wiring, WWL[2]_2: Wiring, WWL[3]_2: Wiring, WWL[1]_3: Wiring, WWL[2]_3: Wiring, WWL[3]_3: Wiring, RBL_1: Wiring, RBL_h: Wiring, RBL_k: Wiring, RBL_2: Wiring, RBL_3: Wiring, WBL_1: Wiring, WBL_h: Wiring, WBL_k: Wiring, WBL_2: Wiring, WBL_3: Wiring, LN1: Wiring, LN2: Wiring, BTr_1: Transistor, BTr_h: Transistor, BTr_k: Transistor, BTr_2: Transistor, BTr_3: Transistor, STr_1: Transistor, STr_h: Transistor, STr_k: Transistor, STr_2: Transistor, STr_3: Transistor, BD: Motherboard, BSH: Bus Wiring, SBT: Semiconductor Substrate, LGC: Circuit Layer, STR: Memory Layer, OSC: Circuit Layer, LT1[1]: Latch Circuit, LT1[2]: Latch Circuit, LT1[3]: Latch Circuit, LT1[z]: Latch Circuit, LT2[1]: Latch Circuit, LT2[2]: Latch Circuit, LT2[3]: Latch Circuit, LT2[z]: Latch Circuit, DA: Data, CLK: Wiring, ENL: Wiring, STG[1]: String, STG[2]: String, STG[3]: String, STG[z]: String, 10: Arithmetic Processing Unit, 20: SRAM, 30: Main Memory, 40: Storage, 50: Information Processing Device, 60: Interface, 70: Arithmetic Processing Unit, 80: Memory Device, 90: Wiring, 100: Memory Section, 111: Insulator, 112: Insulator, 113: Insulator, 114: Insulator, 115: Insulator, 116: Insulator, 117: Insulator, 121: Insulator, 122: Insulator131: Insulator, 132: Insulator, 133: Insulator, 141: Semiconductor, 142: Semiconductor, 143: Semiconductor, 151: Conductor, 152: Conductor, 153: Conductor, 154: Conductor, 155: Conductor, 156: Conductor, 200: Control Unit, 211: Insulator, 212: Insulator, 213: Insulator, 214: Insulator, 215: Insulator, 216: Insulator, 221: Conductor, 222: Conductor, 223: Conductor, 231: Semiconductor, 232: Semiconductor, 240: Insulator, 241: Insulator, 242: Insulator, 243: Insulator, 250: Conductor, 251: Conductor, 252: Conductor, 253: Conductor, 300: Transistor, 311: Substrate, 313: Semiconductor Region, 314a: Low-Resistance Region, 314b: Low-Resistance Region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 382: Insulator, 384: Insulator, 386: Conductor, 700: Transistor, 800: Transistor, 900: Transistor, 1000: Computer System, 1196: Memory Unit, 1197: Controller, 1198: Bus Interface, 4700: Electronic Component, 4702: Printed Circuit Board, 4704: Mounting Board, 4710: Semiconductor Device, 4714: Wire, 4730: Electronic Component, 4731: Interposer, 4732: Package Board, 4733: Electrode, 4735: Semiconductor Device, 4800: Semiconductor Wafer, 4800a: Chip, 4801: Wafer, 4801a: Wafer, 4802: Circuit Section, 4803: Spacing, 4803a: Spacing, 5200: Portable Game Machine, 5201: Housing, 5202: Display Unit, 5203: Button, 5300: Desktop Information Terminal, 5301: Main Body, 5302: Display, 5303: Keyboard, 5400: ICD Main Body, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian Vein, 5406: Superior Vena Cava, 5500: Information Terminal, 5510: Housing, 5511: Display Unit, 5700: Automobile, 5800: Electric Refrigerator-Freezer, 5801: Housing, 5802: Refrigerator Door, 5803: Freezer Door, 5900: Information Terminal, 5901: Housing, 5902: Display Unit, 5903: Operation Button, 5904: Operator, 5905: Band,6240: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation button, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation key, 6305: Lens, 6306: Connection part, 7520: Main body, 7522: Controller, 9600: Computer, 9610: Rack, 9620: Computer, 9621: PC card, 9622: Board, 9623: Connection terminal, 9624: Connection terminal, 9625: Connection terminal, 9626: Semiconductor device, 9627: Semiconductor device, 9628: Semiconductor device, 9629: Connection terminal, 9630: Motherboard, 9631: Slot

Claims

1. An information processing apparatus having an arithmetic processing unit, a storage device, and a plurality of wirings, wherein the storage device has a plurality of strings, wherein one of the plurality of strings is an operation method of an information processing apparatus electrically connected to the arithmetic processing unit via one of the plurality of wirings, converting first data input by serial transmission into a plurality of second data, distributing the plurality of second data for each of the plurality of wirings, and simultaneously supplying the plurality of second data to the plurality of strings in response to a trigger signal.

2. An information processing apparatus having an arithmetic processing unit, a storage device, and a plurality of wirings, wherein the storage device has a plurality of strings, wherein one of the plurality of strings is an operation method of an information processing apparatus electrically connected to the arithmetic processing unit via one of the plurality of wirings, converting first data input by serial transmission into a plurality of second data, distributing the plurality of second data for each of the plurality of wirings, simultaneously supplying the plurality of second data to the plurality of strings in response to a trigger signal, wherein the string has a plurality of memory cells, wherein the memory cell has a transistor, and wherein the transistor has an oxide semiconductor in a channel formation region.

3. The operation method of the information processing apparatus according to claim 1 or claim 2, wherein the storage device is a NAND type storage device.

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