Silicon carbide semiconductor device, method of manufacturing silicon carbide semiconductor device, and semiconductor circuit device

Abstract

To provide a silicon carbide semiconductor device that can be improved in reliability and also improved in yield, a method of manufacturing the silicon carbide semiconductor device, and a semiconductor circuit device.SOLUTION: For each chip region 51 in a plane of a semiconductor wafer 50, one or more of respective parts (an n-type current diffusion region, a p+ type region on a trench bottom for electric field relaxation, and a p+ type region between mutually adjacent trenches) are properly changed in width to have different element structure patterns, and respective chip regions 51 are adjusted in JFET resistance. At this time, the respective chip regions 51 are adjusted in JFET resistance based upon a thickness distribution and an impurity density distribution of an n- type drift region 2 in a plane of the semiconductor wafer 50 so that all the chip regions 51 in the plane of the semiconductor wafer 50 are all substantially equal in total of JFET resistance and drift resistance, and in the chip regions 51 in the plane of the semiconductor wafer 50, ON voltages of SiC-MOSFETs are set substantially equal.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device, a method for manufacturing a silicon carbide semiconductor device, and a semiconductor circuit device.

Background Art

[0002] Conventionally, in a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulating gate composed of a three-layer structure of metal-oxide-semiconductor) using silicon carbide (SiC) as a semiconductor material, the same structure (the same insulating gate structure) is formed in all chip regions within the plane of the semiconductor wafer. The chip region is a region that becomes an individual semiconductor chip (SiC chip) when the semiconductor wafer is cut (diced) along the dicing line and separated into individual pieces.

[0003] The on-voltage Von of the SiC-MOSFET is measured in all chip regions within the plane of the semiconductor wafer, and the semiconductor chips are ranked based on these measurement results. The rank of a semiconductor chip is an index indicating the possible variation range (the possible variation width) of the on-voltage Von of the semiconductor chip to be incorporated into a predetermined semiconductor module. The possible variation width of the on-voltage Von of the semiconductor chip varies depending on the module structure of the semiconductor module. Each semiconductor chip is sorted into each rank so as to satisfy the possible variation width of the on-voltage Von based on the measurement result of the on-voltage Von, and the semiconductor module that can be incorporated is determined.

[0004] The allowable variation range of the on-voltage Von of semiconductor chips incorporated in each semiconductor module is determined in advance by calculating the heat generation amount of the semiconductor chips when incorporated in each semiconductor module, and calculating the range (variation range) of the on-voltage Von that can ensure a predetermined power cycle tolerance for each semiconductor module based on the heat generation amount of the semiconductor chips. The power cycle tolerance is the thermal fatigue life measured by turning the device on and off at a predetermined cycle and alternately repeating the rise and fall of the junction temperature of the device (the temperature of the pn junction that is the main junction of the device).

[0005] As a conventional manufacturing method of SiC-MOSFET, a method has been proposed to reduce the variation in the on-voltage Von between each chip region in the plane of the semiconductor wafer by optimizing the FSR (Field Stabilize Region) based on the local characteristics of the semiconductor wafer (see, for example, Non-Patent Document 1 below). In Non-Patent Document 1 below, the width of the JFET (Junction FET) region is made wider than 2 μm to reduce the on-resistance, and an FSR is provided on the source side of the JFET region to suppress dielectric breakdown due to the high electric field caused by making the width of the JFET region wider than 2 μm.

[0006] As a conventional trench gate structure SiC-MOSFET, a device has been proposed in which a p + -type high-concentration region facing the trench bottom and p + -type high-concentration regions between adjacent trenches are connected near the trench bottom (see, for example, Patent Document 1 below). In Patent Document 1 below, the electric field applied to the trench bottom is relaxed by the p + -type high-concentration region to increase the breakdown voltage, and by connecting the adjacent p + -type high-concentration regions to each other, holes (positive holes) generated when avalanche breakdown occurs at the pn junction (main junction) between the p + -type high-concentration region and the n - -type drift region are efficiently evacuated to the source electrode to reduce the on-resistance.

Prior Art Documents

Patent Documents

[0007] [Patent Document 1] International Publication No. 2017 / 064949 [Non-Patent Document]

[0008] [Non-Patent Document 1] T. Suto, et al., Field Stabilizing Trench-Etched DMOS for Suppression of Performance Variation, International Conference on Silicon Carbide and Related Materials 2019:ICSCRM2019, September 29, 2019 - October 4, 2019, Tu-2A-03 [Summary of the Invention] [Problems to be Solved by the Invention]

[0009] In the conventional manufacturing method of SiC-MOSFETs, the following problems occur. A semiconductor wafer made of silicon carbide is produced by epitaxially growing one or more epitaxial layers of a predetermined conductivity type on a starting wafer made of silicon carbide as a semiconductor material. The n-type drift region is composed of an n-type epitaxial layer epitaxially grown on the starting wafer, and the impurity concentration difference and thickness difference of the n-type drift region within the semiconductor wafer surface and between different semiconductor wafers are large. And the on-voltage Von of the SiC-MOSFET is easily affected by the impurity concentration and thickness of the n-type drift region. - The n-type drift region is composed of an n-type epitaxial layer epitaxially grown on the starting wafer. - The impurity concentration difference and thickness difference of the n-type drift region within the semiconductor wafer surface and between different semiconductor wafers are large. - The on-voltage Von of the SiC-MOSFET is easily affected by the impurity concentration and thickness of the n-type drift region. -

[0010] Therefore, between semiconductor chips (SiC chips) cut from within a semiconductor wafer surface and between semiconductor chips cut from different semiconductor wafers, the impurity concentration difference and thickness difference of the n - type drift region are large, resulting in a large variation in the on-voltage Von. When semiconductor chips with a large difference in on-voltage Von are mixed in the same semiconductor module, the power cycle tolerance of the semiconductor module decreases due to heat concentration on some of the semiconductor chips. For this reason, as described above, a semiconductor module is assembled using semiconductor chips with similar on-voltages Von ranked based on the measurement results of the on-voltage Von.

[0011] However, when the variation in the on-voltage Von between semiconductor chips increases, the number of ranks of the semiconductor chips increases, so the number of semiconductor chips (chip count) in the same rank decreases. When the chip count in each rank decreases, there will be a fractional number that is not enough to be incorporated into the semiconductor module in each rank, resulting in a decrease in the number of products (semiconductor modules). Also, when the variation in the on-voltage Von between a plurality of semiconductor chips incorporated in the same semiconductor module increases, the maximum value of the on-voltage Von of the product specification increases, so there is a risk that it will be difficult to apply to a predetermined application with a low on-voltage Von.

[0012] An object of the present invention is to provide a silicon carbide semiconductor device, a method for manufacturing a silicon carbide semiconductor device, and a semiconductor circuit device that can improve reliability and yield in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0013] In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a deposition step is performed to produce a semiconductor wafer by epitaxially growing a first conductivity type epitaxial layer on one main surface of a starting wafer made of silicon carbide. Next, an element structure forming step is performed to form a silicon carbide semiconductor device having a predetermined element structure in each of a plurality of chip regions that are separated from the semiconductor wafer and become semiconductor chips. The element structure forming step includes first to seventh steps. In the first step, a second conductivity type first high concentration region and a second conductivity type second high concentration region are selectively formed separately from each other in a surface region of the first conductivity type epitaxial layer, and a first conductivity type first current diffusion region having an impurity concentration higher than that of the first conductivity type epitaxial layer is formed between the first high concentration region and the second high concentration region, and a portion of the first conductivity type epitaxial layer excluding the first high concentration region, the second high concentration region, and the first current diffusion region is defined as a first conductivity type first semiconductor region.

[0014] In the second step, after the first step, a second conductivity type epitaxial layer having an impurity concentration lower than those of the first high concentration region and the second high concentration region and in contact with the second high concentration region and separated from the first high concentration region is epitaxially grown on the first conductivity type epitaxial layer to make the thickness of the semiconductor wafer a predetermined thickness. In the third step, a first conductivity type third semiconductor region is formed in a surface region of the second conductivity type epitaxial layer, leaving a second conductivity type second semiconductor region in contact with the second high concentration region inside the second conductivity type epitaxial layer. In the fourth step, a trench is formed that is separated from the second high concentration region, penetrates the third semiconductor region and the second semiconductor region in the depth direction to reach the first current diffusion region, and has a bottom surface facing the first high concentration region. In the fifth step, a gate electrode is formed inside the trench via a gate insulating film. In the sixth step, a first electrode electrically connected to the third semiconductor region and the second semiconductor region is formed. In the seventh step, a second electrode is formed on the other main surface of the starting wafer.

[0015] Before the element structure forming step, it further includes first and second acquisition steps. In the first acquisition step, the thickness distribution and impurity concentration distribution of the first semiconductor region in the plane of the semiconductor wafer are acquired. In the second acquisition step, based on the thickness and impurity concentration of the first semiconductor region for each chip region in the plane of the semiconductor wafer acquired in the first acquisition step, the sum of the JFET resistance of the portion between the adjacent first high-concentration region and the second high-concentration region and the drift resistance of the first semiconductor region is the same in all the chip regions in the plane of the semiconductor wafer. The width of the first current diffusion region that can adjust the JFET resistance, the width of the first high-concentration region, and the width of the second high-concentration region are acquired for each chip region in the plane of the semiconductor wafer. In the first step, by forming the first high-concentration region, the second high-concentration region, and the first current diffusion region with the predetermined widths acquired in the second acquisition step respectively, a plurality of chip regions in which the widths of any one or more of the first high-concentration region, the second high-concentration region, and the first current diffusion region are different from each other are formed to be mixed in the plane of the semiconductor wafer.

[0016] Also, in the manufacturing method of the silicon carbide semiconductor device according to this invention, in the above-described invention, in the second acquisition step, a mask pattern for forming the first high-concentration region, the second high-concentration region, and the first current diffusion region is acquired respectively. In the first step, a step of forming a mask with the mask patterns different for each exposure range and a step of performing ion implantation using the mask are repeated as a set of steps to form the first high-concentration region, the second high-concentration region, and the first current diffusion region respectively.

[0017] Also, in the manufacturing method of the silicon carbide semiconductor device according to this invention, in the above-described invention, after the deposition step, it further includes a mark forming step of forming a predetermined mark on the first main surface of the semiconductor wafer for each chip region. The predetermined mark is a mark for specifying the design values of the width of the first current diffusion region, the width of the first high-concentration region, and the width of the second high-concentration region for each chip region respectively.

[0018] Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, after the deposition step, the method further includes a mark forming step of forming a predetermined mark on the first main surface of the semiconductor wafer for each chip region. The predetermined mark is a mark for specifying the mask pattern for each chip region.

[0019] Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the element structure forming step is performed in the active region of the chip region. In the mark forming step, the predetermined mark is formed outside the active region of the chip region.

[0020] Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the element structure forming step further includes a step of forming a second current diffusion region of the first conductivity type having an impurity concentration lower than that of the first current diffusion region between the first current diffusion region and the second high-concentration region in the surface region of the first conductivity type epitaxial layer before the second step.

[0021] Also, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the first step, the second high-concentration region is formed by dividing it into a relatively deep lower part and a relatively shallow upper part and connecting them in the depth direction. The first current diffusion region is formed by dividing it into a relatively deep lower part and a relatively shallow upper part and connecting them in the depth direction. In the second acquisition step, as the width of the second high-concentration region, the width of the lower part of the second high-concentration region and the width of the upper part of the second high-concentration region are acquired. As the width of the first current diffusion region, the width of the lower part of the first current diffusion region and the width of the upper part of the first current diffusion region are acquired. In the first step, by forming the first high-concentration region, the lower part of the second high-concentration region, the upper part of the second high-concentration region, the lower part of the first current diffusion region, and the upper part of the first current diffusion region with the predetermined widths acquired in the second acquisition step, a plurality of the chip regions in which any one or more of the widths of the first high-concentration region, the lower part of the second high-concentration region, the upper part of the second high-concentration region, the lower part of the first current diffusion region, and the upper part of the first current diffusion region are different from each other are formed to be mixed in the plane of the semiconductor wafer.

[0022] Also, in order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. The semiconductor chip is formed by epitaxially growing an epitaxial layer on one main surface of a starting substrate made of silicon carbide, with the surface of the epitaxial layer being the first main surface and the other main surface of the starting substrate being the second main surface. A first semiconductor region of a first conductivity type is provided inside the epitaxial layer. In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor chip and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor chip and the second semiconductor region. A first current diffusion region of a first conductivity type is selectively provided between the second semiconductor region and the first semiconductor region. The first current diffusion region has a higher impurity concentration than the first semiconductor region. The trench penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first current diffusion region. The gate electrode is provided inside the trench via a gate insulating film.

[0023] A first high-concentration region of a second conductivity type is selectively provided between the second semiconductor region and the first semiconductor region. The first high-concentration region faces the bottom surface of the trench. The first high-concentration region has a higher impurity concentration than the second semiconductor region. A second high-concentration region of a second conductivity type is selectively provided between the second semiconductor region and the first semiconductor region. The second high-concentration region is in contact with the second semiconductor region in the depth direction and faces the trench and the first high-concentration region across the first current diffusion region in a direction parallel to the first main surface of the semiconductor chip. The second high-concentration region has a higher impurity concentration than the second semiconductor region. The first electrode is electrically connected to the third semiconductor region and the second semiconductor region. The second electrode is provided on the second main surface of the semiconductor chip. A predetermined mark is formed on the first main surface of the semiconductor chip outside the active region. The predetermined mark is a mark for specifying the design values of the width of the first current diffusion region, the width of the first high-concentration region, and the width of the second high-concentration region, respectively.

[0024] Further, the silicon carbide semiconductor device according to the present invention further includes a termination region in which a predetermined breakdown voltage structure is disposed between the active region and an end portion of the semiconductor chip in the above-described invention. The predetermined mark is formed on the first main surface of the semiconductor chip in the termination region.

[0025] Further, the silicon carbide semiconductor device according to the present invention further includes a termination region and a dicing line in the above-described invention. In the termination region, a predetermined breakdown voltage structure is disposed between the active region and an end portion of the semiconductor chip. The dicing line serves as a cut-off when dicing the semiconductor chip from a semiconductor wafer, remaining between the termination region and the end portion of the semiconductor chip. The predetermined mark is formed on the first main surface of the semiconductor chip in the dicing line.

[0026] Also, in order to solve the above-described problems and achieve the object of the present invention, a semiconductor circuit device according to the present invention is a semiconductor circuit device in which a semiconductor chip on which a silicon carbide semiconductor device having a predetermined element structure is mounted, and has the following features. The semiconductor chip is formed by epitaxially growing an epitaxial layer on one main surface of a starting substrate made of silicon carbide, with the surface of the epitaxial layer being the first main surface and the other main surface of the starting substrate being the second main surface. The silicon carbide semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first current diffusion region of the first conductivity type, a trench, a gate electrode, a first high-concentration region of the second conductivity type, a second high-concentration region of the second conductivity type, a first electrode, and a second electrode. The first semiconductor region is provided inside the epitaxial layer. The second semiconductor region is provided between the first main surface of the semiconductor chip and the first semiconductor region in the active region. The third semiconductor region is selectively provided between the first main surface of the semiconductor chip and the second semiconductor region. The first current diffusion region is selectively provided between the second semiconductor region and the first semiconductor region. The first current diffusion region has a higher impurity concentration than the first semiconductor region. The trench penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first current diffusion region. The gate electrode is provided inside the trench via a gate insulating film.

[0027] The first high-concentration region is selectively provided between the second semiconductor region and the first semiconductor region. The first high-concentration region faces the bottom surface of the trench. The first high-concentration region has a higher impurity concentration than the second semiconductor region. The second high-concentration region is selectively provided between the second semiconductor region and the first semiconductor region. The second high-concentration region is in contact with the second semiconductor region in the depth direction and faces the trench and the first high-concentration region with the first current diffusion region sandwiched therebetween in a direction parallel to the first main surface of the semiconductor chip. The second high-concentration region has a higher impurity concentration than the second semiconductor region. The first electrode is electrically connected to the third semiconductor region and the second semiconductor region. The second electrode is provided on the second main surface of the semiconductor chip. A plurality of the semiconductor chips are mixed and mounted, wherein the thickness or the impurity concentration, or both, of the first semiconductor region are different, and the widths of any one or more of the first current diffusion region, the first high-concentration region, and the second high-concentration region are different from each other. The sum of the JFET resistance of the portion between the first high-concentration region and the second high-concentration region adjacent to each other among all the semiconductor chips and the drift resistance of the first semiconductor region is the same. The sum of the amounts of the main currents flowing through all the semiconductor chips connected in parallel is defined as the maximum current amount.

[0028] According to the above-described invention, the on-voltage of the silicon carbide semiconductor device is set to be substantially the same in all chip regions within the plane of the semiconductor wafer. Therefore, all semiconductor chips diced from the same semiconductor wafer or even from a plurality of semiconductor wafers can be mounted and incorporated into the same semiconductor circuit device without ranking. The variation in the on-voltage between all semiconductor chips incorporated into the same semiconductor circuit device can be eliminated or minimized as much as possible. For this reason, heat concentration does not occur in some semiconductor chips within the semiconductor circuit device, the power cycle tolerance can be maintained, and the reliability can be improved. In addition, since all semiconductor chips diced from the same semiconductor wafer or even from a plurality of semiconductor wafers can be incorporated into the same semiconductor circuit device, it is difficult to have a fraction less than the number of chips to be incorporated into the semiconductor circuit device, and the yield can be improved.

Advantages of the Invention

[0029] According to the silicon carbide semiconductor device, the method for manufacturing the silicon carbide semiconductor device, and the semiconductor circuit device of the present invention, the effect of improving the reliability and the yield can be achieved.

Brief Description of the Drawings

[0030]

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Mode for Carrying Out the Invention

[0031] Hereinafter, with reference to the accompanying drawings, preferred embodiments of a silicon carbide semiconductor device, a method for manufacturing a silicon carbide semiconductor device, and a semiconductor circuit device according to the present invention will be described in detail. In this specification and the accompanying drawings, in a layer or region preceded by n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than a layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0032] (Embodiment) FIG. 1 is an explanatory diagram showing the state of a semiconductor wafer on which a silicon carbide semiconductor device according to an embodiment is manufactured (fabricated). FIG. 1(a) is a layout of the semiconductor wafer 50 viewed from the front side, and FIG. 1(b) is a cross-sectional structure at the cutting lines X1-X2 and Y1-Y2 of the semiconductor wafer 50. The cutting lines X1-X2 and Y1-Y2 in FIG. 1(a) are cutting lines parallel to the X-axis and Y-axis in FIG. 2(c), respectively. In FIG. 1(b), the n - -type epitaxial layers 58 (58a, 58b) are shown with a uniform thickness t4, but actually the thickness t4 of the n - -type epitaxial layer 58 varies within the plane of the semiconductor wafer 50.

[0033] FIG. 2 is an explanatory diagram showing the thickness distribution and impurity concentration distribution of the drift region within the plane of the semiconductor wafer of FIG. 1. In FIGS. 2(a) and 2(b), the thickness t2 distribution and impurity concentration distribution of the portion that becomes the n - -type drift region 2 in the n - -type epitaxial layer 58 within the plane of the semiconductor wafer 50 are shown. The horizontal axes in FIGS. 2(a) and 2(b) are distances in a direction parallel to the front surface of the semiconductor wafer 50, which are directions parallel to the X-axis and Y-axis in FIG. 2(c). The vertical axes in FIGS. 2(a) and 2(b) are the thickness t2 and impurity concentration of the n - -type drift region 2, respectively.

[0034] 0 [mm] on the horizontal axis in FIGS. 2(a) and 2(b) is the origin (0, 0) in FIG. 2(c). In FIG. 2(c), the coordinate plane within the plane of the semiconductor wafer 50 is shown by the X-axis and Y-axis perpendicular to each other. The origin (0, 0) in FIG. 2(c) is the center (center of the circle) O of the semiconductor wafer 50. FIG. 3 is a plan view showing the layout of the semiconductor chip cut from the semiconductor wafer of FIG. 1 viewed from the front side. FIG. 3 shows the state of the chip region 51 of the semiconductor wafer 50 of FIG. 1 after cutting. FIGS. 4 and 5 are cross-sectional views showing examples of the cross-sectional structure of the active region of the semiconductor chip of FIG. 3. The cross-sectional structure outside the active region 41 is not shown.

[0035] The silicon carbide semiconductor device 10 according to the embodiment shown in FIGS. 3 to 5 is manufactured (fabricated) in each chip region 51 (see FIG. 1) of a semiconductor wafer 50 using silicon carbide (SiC) as a semiconductor material, and is a SiC-MOSFET obtained by singulating the chip region 51 into individual semiconductor chips (semiconductor substrates) 30. The semiconductor wafer 50 is an n + -type starting wafer 57 (the portion that becomes the n + -type starting substrate 31) on which an n - -type drift region (first semiconductor region) 2 and p-type base region (second semiconductor region) 4 are epitaxially grown in this order as epitaxial layers (first and second conductivity type epitaxial layers) 58, 59 (the portions that become the epitaxial layers 32, 33 in FIGS. 4 and 5).

[0036] The semiconductor wafer 50 may have, for example, an orientation flat (OF: Orientation Flat, a linear notch provided at a part of the edge end) 55 or a notch (a V-shaped notch provided at a part of the edge end: not shown) indicating the plane orientation. In FIG. 2(c), the direction parallel to the orientation flat is taken as the direction parallel to the X axis. The thickness t4 and impurity concentration of the n - -type epitaxial layer 58 of the semiconductor wafer 50 vary within the plane of the semiconductor wafer 50 according to the process variations in the epitaxial growth of the n - -type epitaxial layers 58a, 58b.

[0037] Within the plane of the semiconductor wafer 50, the thickness (hereinafter referred to as the thickness of the n - -type drift region 2) t2 and impurity concentration of the portion of the n - -type epitaxial layer 58a that becomes the n - -type drift region 2 vary in substantially the same ratio as the variations in the thickness t1 and impurity concentration of the n - -type epitaxial layer 58a. The thickness t2 of the n - -type drift region 2 is from the thickness t1 of the n - -type epitaxial layer 58a to the said n -It is the thickness obtained by subtracting the thickness t3 (see FIG. 10) of the lower part 3a of the n-type current diffusion region 3, which is formed by ion implantation in the surface region of the p-type epitaxial layer 58a, from the thickness t1 (t2 = t1 - t3). As will be described later, for example, the FT-IR method can be used to measure the film thickness (thickness) of each part in the semiconductor wafer 50, and the Hg-CV method can be used to measure the impurity concentration.

[0038] Specifically, for the n- - type drift region 2 of the semiconductor wafer 50 (60), the thickness t2 and the impurity concentration depend on the epitaxial growth method of the p-type epitaxial layer 58a. For example, in the plane of the semiconductor wafer 50, the thickness and the impurity concentration are substantially the same at the portions on the concentric circles with the center O (= 0 mm) of the semiconductor wafer 50 as the reference. Substantially the same thickness and substantially the same impurity concentration mean that the thickness and the impurity concentration are the same to such an extent that the SiC-MOSFETs having the same element structure formed in the chip region 51 have the same various characteristics (for example, on-voltage characteristics) within a range including a predetermined allowable error. - More specifically, the thickness t2 of the n-

[0039] type drift region 2 of the semiconductor wafer 50 becomes thinner as it goes outward concentrically from the center O of the semiconductor wafer 50 (toward the end portion side of the semiconductor wafer 50). The thickness t2 of the n- - type drift region 2 may be partially different at the portions on the concentric circles with the center O of the semiconductor wafer 50 as the reference. FIG. 2(a) shows a case where the thickness t2 of the n- - type drift region 2 is substantially the same at any distance from the center O of the semiconductor wafer 50. - type drift region 2 is substantially the same at any distance from the center O of the semiconductor wafer 50.

[0040] The impurity concentration of the n- - type drift region 2 of the semiconductor wafer 50 becomes lower as it goes outward concentrically from the center O of the semiconductor wafer 50. The impurity concentration of the n- - type drift region 2 may be partially different at the portions on the concentric circles with the center O of the semiconductor wafer 50 as the reference. FIG. 2(b) shows a case where the impurity concentration of the n-- This shows the case where the impurity concentrations in the type drift regions 2 are substantially the same.

[0041] The semiconductor wafer 50 is singulated into individual semiconductor chips (SiC chips) 30 by cutting (dicing) each chip region 51 along the dicing line 52. The dicing line 52 may remain on the semiconductor chip 30 so as to surround the periphery of the semiconductor chip 30. The chip region 51 has a substantially rectangular planar shape and a plurality of them are arranged in a matrix on the central side of the semiconductor wafer 50. The outer peripheral portion (the portion outside the substantially circle of the broken line 53c) 53a from the end of the semiconductor wafer 50 to the inside by a predetermined width d is an invalid region 53 not used as the chip region 51, and for example, it comes into contact with and is held by the conveying means during the conveyance of the semiconductor wafer 50.

[0042] The portion 53b between the outer peripheral portion 53a of the semiconductor wafer 50 and the outermost chip region 51 is an invalid region 53 not used as the chip region 51 because the predetermined surface area of the chip region 51 cannot be secured in a substantially rectangular shape. The SiC-MOSFETs formed in each chip region 51 are respectively at the position (coordinates) of the chip region 51 in the plane of the semiconductor wafer 50. - Depending on the thickness t2 and impurity concentration of the n-type drift region 2, the widths w1, w2, w3, w11, w21, w22 (see FIGS. 4 and 5) of one or more of the n-type current diffusion regions 3 (3a, 3b) and the p + type regions 21, 22 (22a, 22b) are appropriately set.

[0043] As a result, the SiC-MOSFETs are set to have the same on-voltage Von or an on-voltage Von as close as possible (hereinafter, referred to as substantially the same on-voltage Von) in all the chip regions 51 in the plane of the semiconductor wafer 50 (furthermore, in a plurality of semiconductor wafers 50). Substantially the same on-voltage Von means that the variation in the on-voltage Von of the SiC-MOSFETs in the plane of the semiconductor wafer 50 (furthermore, in a plurality of semiconductor wafers 50) is within a range of, for example, ±25% or less with respect to the average value, and the current capabilities (the amount of the main current) of the SiC-MOSFETs are substantially the same in all the semiconductor chips 30 (the chip regions 51 after singulation) connected in parallel.

[0044] Specifically, in all chip regions 51 in the plane of the semiconductor wafer 50, the JFET resistance and the drift resistance (the internal resistance of the n - type drift region 2) are adjusted so that the sum (the combined resistance value) thereof becomes substantially equal. The JFET resistance is the internal resistance of the portion between adjacent p + type regions 21 and 22. The JFET resistance of the chip region 51 is adjusted by changing one or more of the widths w1, w2, w3, w11, w21, and w22 of the n - type current diffusion regions 3 (3a, 3b) and the p + type regions 21, 22 (22a, 22b) according to the thickness t2 and the impurity concentration of the n

[0045] type drift region 2 at its own position. + The n-type current diffusion regions 3 (3a, 3b) and the p - type regions 21, 22 (22a, 22b) are diffusion regions selectively formed by ion implantation in the surface region of the n + type epitaxial layer 58. Therefore, in order to change one or more of the widths w1, w2, w3, w11, w21, and w22 of the n-type current diffusion regions 3 (3a, 3b) and the p - type regions 21, 22 (22a, 22b) in each chip region 51 in the plane of the semiconductor wafer 50, a plurality of mask patterns of the ion implantation mask for forming these regions may be prepared.

[0046] Specifically, for each chip region 51 in the plane of the semiconductor wafer 50 or for each exposure range (hereinafter referred to as a shot) 56 at a time, the mask pattern of the ion implantation mask for forming the n-type current diffusion regions 3 (3a, 3b) and the p + type regions 21, 22 (22a, 22b) is changed. As a result, in each chip region 51 in the plane of the semiconductor wafer 50, the n-type current diffusion regions 3 (3a, 3b) and the p +One or more widths w1, w2, w3, w11, w21, w22 of the type regions 21, 22 (22a, 22b) can be changed to form a SiC-MOSFET with substantially the same on-voltage Von.

[0047] In this way, in the plane of the semiconductor wafer 50, the n-type current diffusion regions 3 (3a, 3b) and p + Chip regions 51 of a plurality of patterns (hereinafter referred to as element structure patterns) in which the mask pattern of the ion implantation mask for forming the type regions 21, 22 (22a, 22b) is appropriately changed to form the element structure are mixed. The element structure patterns of the chip regions 51 in the plane of the semiconductor wafer 50 may be different for each chip region 51 or may be different for each predetermined shot 56. In Fig. 1(a), the unit of the shot 56 is shown by a thick line as a square in which four chip regions 51 arranged in a matrix and adjacent to each other are taken as a set.

[0048] For example, the chip regions 51 located on concentric circles with respect to the center O of the semiconductor wafer 50 in the plane of the semiconductor wafer 50 are n - Since the type drift regions 2 have substantially the same thickness t2 and substantially the same impurity concentration, they have the same element structure pattern. Therefore, the chip regions 51 on the concentric circles with respect to the center O of the semiconductor wafer 50 in the plane of the semiconductor wafer 50 may be regarded as one shot 56. Instead of some of the chip regions 51 in the plane of the semiconductor wafer 50, PCMs (Process Control Monitors) 54 (hatched portions) for verifying the legitimacy of each process may be arranged. Furthermore, one mask with different widths for each chip region 51 may be used based on the distribution of the thickness t2 and the impurity concentration distribution of the n - type drift region 2.

[0049] The dicing line 52 (the thin solid line in FIG. 1) is provided in a grid pattern surrounding the plurality of chip regions 51 arranged in a matrix within the plane of the semiconductor wafer 50. The dicing line 52 is a cut that surrounds the periphery of the chip region 51 along the four sides of the chip region 51 having a substantially rectangular planar shape, and is composed of, for example, grooves formed on the front surface of the semiconductor wafer 50 (the surface on the side of the p-type epitaxial layer 59). In the dicing line 52, for example, marks (position identification marks: not shown) for specifying positions (coordinates) in a direction parallel to the front surface of the semiconductor wafer 50 are formed.

[0050] The position identification mark is a mark for specifying the position etc. of each chip region 51. The position identification mark is, for example, a convex or concave portion having a predetermined planar shape (for example, a cross shape) formed by etching within the dicing line 52. The position identification mark may be provided in the invalid region 53 of the semiconductor wafer 50. The invalid region 53 is a portion that is not used as the chip region 51 between the outermost chip region 51 of the semiconductor wafer 50 and the end of the semiconductor wafer 50. As the position identification mark, an alignment mark for aligning each part of the element structure formed in the chip region 51 may be used.

[0051] The silicon carbide semiconductor device 10 according to the embodiment shown in FIGS. 3 to 5 is an n-channel vertical MOSFET having a trench gate structure provided with an active region 41 and an edge termination region 42 in a semiconductor chip 30 made of silicon carbide. The active region 41 is a region where the main current (drift current) flows when the silicon carbide semiconductor device 10 (MOSFET) is in the on state, and a plurality of unit cells (functional units of the element) having the same structure of the MOSFET are arranged adjacent to each other. FIGS. 4 and 5 show two adjacent unit cells of the MOSFET. The active region 41 is arranged, for example, at the center of the semiconductor chip 30 (chip center), and is surrounded by the edge termination region 42.

[0052] On the front surface of the semiconductor chip 30 in the active region 41, a source electrode (first electrode) 12 and a gate pad (electrode pad) 13 are arranged apart from each other. The source electrode 12 has substantially the same surface area as the active region 41. The portion of the source electrode 12 exposed at the opening of the passivation film (not shown) functions as a source pad (electrode pad). FIG. 3 shows a source electrode 12 having a substantially rectangular planar shape with a recess recessed toward the center of the chip so as to surround three sides of the gate pad 13 having a substantially rectangular planar shape, but the planar shapes of these portions are set as appropriate. The gate pad 13 may be arranged in the edge termination region 42.

[0053] The edge termination region 42 is a region between the active region 41 and the end portion (chip end portion) of the semiconductor chip 30. The edge termination region 42 has a function of relaxing the electric field on the front surface side of the semiconductor chip 30 and maintaining the breakdown voltage. The breakdown voltage is the limit voltage at which the leakage current does not increase excessively and the silicon carbide semiconductor device 10 does not malfunction or break down. In the edge termination region 42, a breakdown voltage structure (not shown) such as a field limiting ring (FLR) structure or a junction termination extension (JTE) structure is arranged.

[0054] On the front surface of the semiconductor chip 30 in the edge termination region 42, one or more (two in FIG. 3) Vernier patterns (predetermined marks) 14 are arranged. The Vernier pattern 14 is a scale pattern (Vernier) for visually measuring the misalignment of the position of the ion implantation mask pattern through, for example, a monitor (not shown), and is composed of, for example, convex or concave portions formed by etching. Further, the Vernier pattern 14 is a mark such as a symbol or a character string for specifying the design values of the element structure patterns (the widths w1, w2, w3, w11, w21, w22 of the n-type current diffusion regions 3 (3a, 3b) and the p + type regions 21, 22 (22a, 22b)) of each chip region 51 (see FIG. 1) of the semiconductor wafer 50.

[0055] As the Vernier pattern 14 for specifying the element structure pattern of the chip region 51, for example, a character string combining the mask name of the ion implantation mask used for forming the n-type current diffusion regions 3 (3a, 3b) and the p + type regions 21, 22 (22a, 22b) and their branch numbers, or a recipe name that can specify the conditions of the ion implantation performed using the ion implantation mask (such as dopant, dose amount, acceleration energy, etc.) may be used. A dicing line 52 may remain between the edge termination region 42 and the chip end. In this case, the Vernier pattern 14 may be arranged on the dicing line 52.

[0056] The trench gate structure is composed of a p-type base region 4, an n + type source region (third semiconductor region) 5, a p ++ type contact region 6, a trench 7, a gate insulating film 8, and a gate electrode 9. The semiconductor chip 30 is formed by epitaxially growing n + type epitaxial layers 32 and 33 that will become the n - type drift region 2 and the p-type base region 4 in this order on the front surface of the n + type starting substrate 31. The semiconductor chip 30 is formed by singulating the chip region 51 of the semiconductor wafer 50. The semiconductor chip 30 has the main surface on the p-type epitaxial layer 33 side as the front surface and the main surface on the n + type starting substrate 31 side (the back surface of the n

[0057] n + type starting substrate 31 is an n + type drain region 1. Between the n + type starting substrate 31 and the n - type epitaxial layer 32, an n + type drain region 1 and an n -An n-type epitaxial layer serving as an n-type buffer region (not shown) may be provided in contact with the n-type drift region 2. The n-type buffer region has a function of preventing minority carriers (holes) generated at the interface of the pn junction from reaching the n-type starting substrate 31 when the parasitic diode (body diode) formed by the main junction (pn junction) of the SiC-MOSFET conducts, and causing them to recombine with electrons in the n-type buffer region and disappear. +

[0058] n - The n-type drift region 2 is provided in contact with the p-type base region 4 and the n + -type drain region 1. Between the p-type base region 4 and the n + -type drain region 1, an n-type current diffusion region (first current diffusion region) 3, p - -type regions 21, 22 (first and second high-concentration regions) and an n-type region 23 are selectively provided, respectively. + The n-type drift region 2 is the portion of the n - -type epitaxial layer 32 excluding the n-type current diffusion region 3, p - -type regions 21, 22 and the n-type region 23. The n-type current diffusion region 3, p + -type regions 21, 22 and the n-type region 23 are provided at positions deeper than the bottom surface of the trench 7 on the n + -type drain region 1 side. +

[0059] The n-type current diffusion region 3 is a so-called current spreading layer (CSL: Current Spreading Layer) that reduces the spreading resistance of carriers. The n-type current diffusion region 3 is in contact with the p-type base region 4 on the upper surface (the surface on the n + -type source region 5 side) and in contact with the n + -type drift region 2 on the lower surface (the surface on the n - -type drain region 1 side). As will be described later, the n-type current diffusion region 3 is formed by forming the portion on the n + -type drain region 1 side (hereinafter referred to as the lower portion) 3a and the portion on the n + -type source region 5 side (hereinafter referred to as the upper portion) 3b in different ion implantation processes and connecting them to each other in the depth direction.​

[0060] The n-type current diffusion region 3 is in contact with the gate insulating film 8 on the inner wall of the trench 7. When the p + -type region 21 reaches the bottom surface of the trench 7, the lower portion 3a of the n-type current diffusion region 3 is not in contact with the gate insulating film 8. The n-type current diffusion region 3 only needs to be in contact with the p + -type region 21, and may extend in a direction parallel to the front surface of the semiconductor chip 30 and be in contact with the p + -type region 22 (see FIG. 4), or may be separated from the p + -type region 22 (see FIG. 5). The n-type current diffusion region 3 covers the periphery of the p + -type region 21. When the p + -type region 21 is separated from the bottom surface of the trench 7, the upper portion 3b of the n-type current diffusion region 3 is not in contact with the p + -type region 21.

[0061] When the n-type current diffusion region 3 is in contact with the p + -type region 22, the width w1 of the lower portion 3a of the n-type current diffusion region 3 is the width between adjacent p + -type regions 22, and the width w2 of the upper portion 3b of the n-type current diffusion region 3 is the width between the adjacent p + -type region 22 and the trench 7. When the n-type current diffusion region 3 is separated from the p + -type region 22, n-type current diffusion regions (second current diffusion regions) 3c and 3d are respectively arranged between the lower portion 3a and the upper portion 3b of the n-type current diffusion region 3 and the p + -type region 22 in contact with these regions. The widths of the n - -type current diffusion regions 3c and 3d are, for example, substantially the same. Substantially the same width means the same width within a range including the tolerance due to process variations. - The impurity concentrations of the n-type current diffusion regions 3c and 3d are lower than the impurity concentration of the n-type current diffusion region 3. For example, the n-type epitaxial layer 58a (n

[0062] -type drift region 2: see FIGS. 9 and 10) grown epitaxially to fabricate the semiconductor wafer 50, or the n - -type current diffusion regions 3c and 3d are formed by doping the semiconductor wafer 50 with a lower concentration of impurities than the n-type current diffusion region 3. - -type epitaxial layer 58a (n - -type drift region 2: see FIGS. 9 and 10), or the n -It is the same as the impurity concentration of the epitaxial layer 58b (see FIG. 11). The lower part 3a of the n-type current diffusion region 3 is separated from the p + type region 22, and only the upper part 3b of the n-type current diffusion region 3 may be in contact with the p + type region 22 (not shown). In this case, an n - type current diffusion region 3c is provided, and a configuration is adopted in which the n - type current diffusion region 3d is not provided.

[0063] p + type regions 21, 22 and the n-type region 23 have a function of relaxing the electric field applied to the gate insulating film 8 on the bottom surface of the trench 7. The p + type region 21 is provided separately from the p-type base region 4 and faces the bottom surface of the trench 7 in the depth direction. The p + type region 21 may reach the bottom surface of the trench 7. The p + type region 21 may be electrically connected to the source electrode 12 at a location not shown in the figure. The width w11 of the p + type region 21 is preferably wider than the width of the trench 7. Thereby, the p + type region 21 can relax the electric field applied to the gate insulating film 8 at the bottom corner portion of the trench 7 (the boundary between the bottom surface and the side wall of the trench 7).

[0064] p + type regions 22 are provided between adjacent trenches 7, separated from the p + type region 21 and the trench 7. The p + type region 22 is in contact with the p-type base region 4 on the upper surface (the upper surface of the upper part 22b of the p + type region 22 to be described later). As will be described later, the p + type region 22 includes a portion (hereinafter referred to as the lower part) 22a on the n + type drain region 1 side and a portion (hereinafter referred to as the upper part) 22b on the n + type source region 5 side, which are formed by different ion implantation processes and connected to each other in the depth direction. The widths w21, w22 of the lower part 22a and the upper part 22b of the p + type region 22 may be, for example, substantially the same or different.

[0065] The JFET resistance is n - Depending on the thickness t2 and impurity concentration of the n-type drift region 2, the lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, p + type region 21, p + the lower part 22a of the type region 22 and p + One or more of the widths w1, w2, w3, w11, w21, w22 of the upper part 22b of the type region 22 are appropriately set and adjusted. In particular, the part between the mutually adjacent p + type regions 21, 22 (the lower part 3a of the n-type current diffusion region 3 in FIG. 4, the lower part 3a of the n-type current diffusion region 3 and n in FIG. 5 - the width w3 and impurity concentration of the type current diffusion region 3c) greatly affect the JFET resistance.

[0066] n - The thickness t2 of the n-type drift region 2 is n - from the thickness t1 of the n-type epitaxial layer 32a, to the thickness t3 of the lower part 3a of the n-type current diffusion region 3 formed by ion implantation on the surface region of the n - type epitaxial layer 32a subtracted (t2 = t1 - t3). That is, n - The thickness t2 of the n-type drift region 2 is the length from the n-type current diffusion region 3 to the n + type drain region 1 in the depth direction. n - The thickness t2 and impurity concentration of the n-type drift region 2 vary depending on the position in the plane of the semiconductor wafer 50 of the chip region 51 before singulation of the semiconductor chip 30 (see FIGS. 2(a) and 2(b)).

[0067] The n-type region 23 is p + between the lower part 22a of the type region 22 and the n - type drift region 2, and is provided in contact with these regions. The n-type region 23 reaches, for example, a deeper position on the n + type drain region 1 side than the lower part 3a of the n-type current diffusion region 3. The width of the n-type region 23 may be, for example, substantially the same as the width w21 of the lower part 22a of the p + type region 22. The n-type region 23 may not be provided. When the n-type region 23 is not provided, p +The p-type region 22 is in contact with the n-type current diffusion region 3 on the bottom surface, and is surrounded by the n-type current diffusion region 3 or is in contact with the n - -type drift region 2. The depth positions of the bottom surfaces of the p + -type regions 21 and 22 are substantially the same.

[0068] The p-type base region 4 is provided between the front surface of the semiconductor chip 30 and the n - -type drift region 2. The p-type base region 4 is the portion of the p-type epitaxial layer 33 excluding the n + -type source region 5 and the p ++ -type contact region 6. The n + -type source region 5 and the p ++ -type contact region 6 are selectively provided between the front surface of the semiconductor chip 30 and the p-type base region 4, respectively. The n + -type source region 5 and the p ++ -type contact region 6 are in contact with the p-type base region 4 and make ohmic contact with the source electrode 12 at the contact hole of the interlayer insulating film 11 described later.

[0069] p ++ -type contact region 6 may not be provided. When the p ++ -type contact region 6 is not provided, instead of the p ++ -type contact region 6, the p-type base region 4 reaches the front surface of the semiconductor chip 30 and makes ohmic contact with the source electrode 12. These n-type current diffusion region 3, p + -type regions 21 and 22, n-type region 23, n + -type source region 5 and p ++ -type contact region 6 are diffusion regions formed by ion implantation and are selectively provided inside the epitaxial layers 32 and 33. The trench 7 penetrates through the n + -type source region 5 and the p-type base region 4 and reaches the n-type current diffusion region 3.

[0070] Inside the trench 7, a gate electrode 9 is provided via a gate insulating film 8. The gate electrode 9 is electrically connected to a gate pad 13 (see FIG. 3). The interlayer insulating film 11 covers the gate electrode 9. The source electrode 12 makes an ohmic contact with the front surface of the semiconductor chip 30 at the contact hole of the interlayer insulating film 11, and is connected to the p-type base region 4, n + -type source region 5 and p ++ -type contact region 6. The drain electrode (second electrode) 15 is provided on the entire back surface (the back surface of the n + -type starting substrate 31) of the semiconductor chip 30, and is electrically connected to the n + -type drain region 1.

[0071] A semiconductor circuit device incorporating the silicon carbide semiconductor device 10 according to the embodiment shown in FIGS. 3 to 5 described above will be described. FIG. 6 is a cross-sectional view schematically showing the structure of a semiconductor circuit device incorporating the silicon carbide semiconductor device according to the embodiment. The semiconductor circuit device 80 according to the embodiment shown in FIG. 6 incorporates two or more (four in FIG. 6) semiconductor chips 30 (hatched portions) in which the silicon carbide semiconductor device 10 according to the above-described embodiment is formed on an insulating substrate 70, and connects them in parallel. The semiconductor module has the total amount of the main current flowing through all the semiconductor chips 30 connected in parallel as the maximum current amount. The insulating substrate 70 is formed by joining a copper (Cu) plate 72 and a heat sink 73 to both main surfaces of an insulating plate 71, respectively.

[0072] On the copper plate 72 on the front surface of the insulating substrate 70, the thickness t2 or the impurity concentration of the n - -type drift region 2, or both are different, and among the respective parts of the JFET section (the lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, p + -type region 21, the lower part 22a of the p + -type region 22, and the upper part 22b of the p + -type region 22), semiconductor chips 30 having a plurality of element structure patterns in which one or more of the widths w1, w2, w3, w11, w21, w22 are different from each other are mixed and mounted. All the semiconductor chips 30 mounted on the insulating substrate 70 are p +The JFET resistance of the portion between the p-type region 21 and the p + -type region 22 and the drift resistance of the n - -type drift region 2 are the same in total.

[0073] The drain pad (drain electrode 15: see FIGS. 4 and 5) on the back surface of the semiconductor chip 30 is joined to the copper plate 72 on the front surface of the insulating substrate 70 via the solder layer 74a, and is electrically connected to the external electrode terminal 77a via the copper plate 72. A plurality of implant pins (conductive posts) 75 or bonding wires (not shown) are joined to the source pad (source electrode 12: see FIGS. 4 and 5) of each semiconductor chip 30 via the solder layer 74b. The source pads of all the semiconductor chips 30 are connected in parallel via the source pad (not shown) of the printed circuit board 79, the implant pins 75 or the bonding wires.

[0074] The implant pin 76 or a bonding wire (not shown) is joined to the gate pad 13 (see FIG. 3) of the semiconductor chip 30 via the solder layer 74b. The gate pads 13 of all the semiconductor chips 30 are connected in parallel via the gate pad (not shown) of the printed circuit board 79, the implant pin 76 or the bonding wire. The implant pins 75 and 76 are directly joined to a predetermined electrode pad (not shown) on the main surface opposite to the semiconductor chip 30 side of the printed circuit board 79 facing the front surface of the semiconductor chip 30, or are electrically connected to the predetermined electrode pad via a circuit pattern (not shown).

[0075] As described above, the source pads on the front surfaces of all the semiconductor chips 30 on the insulating substrate 70 are electrically connected to the source pads of the printed circuit board 79 by the implant pins 75, and the drain pads on the back surfaces of all the semiconductor chips 30 are joined to the copper plate 72 of the insulating substrate 70. The maximum current amount (current capacity) of the semiconductor circuit device 80 is the sum of the current amounts of a plurality of semiconductor chips 30 (silicon carbide semiconductor devices 10) mounted on the insulating substrate 70 and connected in parallel. One end of the external electrode terminal 77a is joined to the copper plate 72 on the front surface of the insulating substrate 70. One end of the external electrode terminal 77b is joined to a circuit pattern (not shown) of the printed circuit board 79.

[0076] The external electrode terminals 77a and 77b project outward from the encapsulant 78 described later at the other ends, and draw out the potentials of the respective electrodes (drain electrode 15, source electrode 12, and gate electrode 9) to which they are connected to the outside. The insulating substrate 70, semiconductor chips 30, implant pins 75 and 76, printed circuit board 79, and external electrode terminals 77a and 77b are encapsulated by the encapsulant 78. The heat sink 73 on the back surface of the insulating substrate 70 is joined to a cooler (not shown) via a heat conductive paste. During the operation of the semiconductor circuit device 80, the heat generated in the electrode pads and circuit patterns of the semiconductor chips 30 and the printed circuit board 79 is conducted from the insulating substrate 70 to the cooler and dissipated, thereby cooling the semiconductor chips 30 and the printed circuit board 79.

[0077] Next, a method for manufacturing the silicon carbide semiconductor device 10 and the semiconductor circuit device 80 according to the embodiment will be described. FIG. 7 is a flowchart showing an outline of a method for manufacturing a silicon carbide semiconductor device and a semiconductor circuit device according to the embodiment. FIG. 8 is an explanatory diagram schematically showing the measurement positions of the process of step S2 in FIG. 7. In FIG. 8, the coordinate plane in the plane of the semiconductor wafer 60 has the center of the semiconductor wafer 60 (the center of the circle) set to 0.0 mm for both the horizontal axis and the vertical axis. FIGS. 9 to 14 are cross-sectional views showing the states during the manufacture of the semiconductor device according to the embodiment.

[0078] First, as shown in FIG. 9, a semiconductor wafer (SiC wafer) 60 that is part of a semiconductor wafer 50 (see FIG. 1) made of silicon carbide as a semiconductor material is prepared (step S1: deposition process). The semiconductor wafer 60 is an n + -type starting wafer 57 with an n - -type drift region 2 formed by epitaxially growing (depositing) an n - -type epitaxial layer 58a (58). In the process of step S1, an n + -type starting wafer 57 made of silicon carbide may be prepared to fabricate the semiconductor wafer 60, or the semiconductor wafer 60 itself may be purchased.

[0079] Next, for the n - -type epitaxial layer 58a, the thickness t2 distribution and impurity concentration distribution of the portion that becomes the n - -type drift region 2 are obtained (step S2: first acquisition process). The n - -type epitaxial layer 58a has, for example, substantially the same thickness t1 and substantially the same impurity concentration in a portion on a concentric circle based on the center (0 mm, 0 mm) of the semiconductor wafer 60. Therefore, the measurement positions 61 (▲ marks) of the thickness t1 and impurity concentration of the n - -type epitaxial layer 58a are set, for example, on a cross (on two straight lines perpendicular to each other) passing through the center of the semiconductor wafer 60 (FIG. 8).

[0080] Then, on the concentric circles where the measurement positions 61 are on the circumference with the center of the semiconductor wafer 60 as a reference, it is regarded that the thickness t1 and impurity concentration of the n - -type epitaxial layer 58a are the same. The thickness t1 and impurity concentration of the n - -type epitaxial layer 58a at the middle between adjacent measurement positions 61 may be, respectively, the average value of the thickness t1 and the average value of the impurity concentration at the adjacent measurement positions 61. The measurement positions 61 may be set only on one straight line passing through the center of the semiconductor wafer 60 to reduce the number of measurement positions 61.

[0081] At each of these multiple measurement positions 61 in the plane of the semiconductor wafer 60, respectively, n -Obtain the thickness t1 and impurity concentration of the n-type epitaxial layer 58a. At each measurement position 61, the n - From the thickness t1 of the n-type epitaxial layer 58a, subtract the thickness t3 (see FIG. 10) of the lower part 3a of the n-type current diffusion region 3 formed in a later process, and use the resulting thickness as the thickness t2 of the n - type drift region 2 within the plane of the semiconductor wafer 60. At each measurement position 61, the n - Impurity concentration of the n-type epitaxial layer 58a is obtained as the impurity concentration of the n - type drift region 2 within the plane of the semiconductor wafer 60.

[0082] Assume that the thickness t2 and impurity concentration of the n - type drift region 2 are the same on concentric circles where the measurement position 61 is on the circumference with respect to the center of the semiconductor wafer 60. Arrange the chip regions 51, for example, in a matrix shape inside a portion with a predetermined width d from the end of the semiconductor wafer 50 toward the inside (a substantially circular shape of the broken line 53c). As a result, as shown in FIGS. 2(a) and 2(b), the thickness t2 distribution and impurity concentration distribution of the n - type drift region 2 in each chip region 51 within the plane of the semiconductor wafer 60 can be obtained.

[0083] n - The thickness t1 of the n-type epitaxial layer 58a is calculated based on, for example, the absorbance of the infrared spectrum measured using the Fourier Transform Infrared Spectroscopy (FT-IR) method. The n - Impurity concentration of the n-type epitaxial layer 58a is measured, for example, by the capacitance-voltage measurement method (Hg-CV method) using mercury (Hg) as the gate electrode, and the impurity concentration is calculated based on the resistivity of the n - type epitaxial layer 58.

[0084] Next, the n within the plane of the semiconductor wafer 60 obtained in the process of step S2 -Based on the thickness t2 distribution and impurity concentration distribution of the portion that becomes the p-type drift region 2, a mask pattern (not shown) of an ion implantation mask for forming each part of the JFET section is acquired for each shot 56 (see FIG. 1) (step S3: second acquisition step). As described above, since the chip regions 51 of a plurality of element structure patterns are mixed in the plane of the semiconductor wafer 60, a plurality of mask patterns are formed in the ion implantation mask that covers the entire surface of the semiconductor wafer 60 used in the ion implantation described later.

[0085] Each part of the JFET section is an area that is arranged between the p-type base region 4 and the p - type drift region 2 and whose impurity concentration and width affect the JFET resistance value. Specifically, each part of the JFET section is the lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, the n - type current diffusion regions 3c, 3d, the p + type region 21, the p + type region 22's lower part 22a and the p + type region 22's upper part 22b (see FIGS. 4 and 5). In the process of step S3, a mask pattern of an ion implantation mask for forming the n-type region 23 may also be acquired.

[0086] For example, the mask patterns of the ion implantation mask for forming the p + type region 21 and the lower part 22a of the p + type region 22 formed simultaneously, the ion implantation mask for forming the lower part 3a of the n-type current diffusion region 3, the p + type region 22's upper part 22b for forming the ion implantation mask, and the ion implantation mask for forming the upper part 3b of the n-type current diffusion region 3 are acquired. When providing the n - type current diffusion regions 3c, 3d, the mask pattern of the ion implantation mask for forming the n - type current diffusion regions 3c, 3d is further acquired.

[0087] p + type region 22's directly below (n +In the case where an n-type region 23 is provided on the side of the n-type drain region 1, the mask pattern of the ion implantation mask for forming the n-type region 23 is, for example, + The width of the n-type region 23 may be obtained based on the width w21 of the lower portion 22a of the n-type region 22. + The width w21 may be approximately the same as the width w21 of the lower portion 22a of the mold region 22, or may be adjacent to the p + It may be narrower than the width w21 of the lower portion 22a of the mold region 22.

[0088] n - In the case where the n-type current diffusion regions 3c and 3d are not provided, the ion implantation mask for forming the lower portion 3a of the n-type current diffusion region 3 and the ion implantation mask for forming the upper portion 3b of the n-type current diffusion region 3 are ion implantation masks that open the entire area of the active region 41. In order to obtain these multiple mask patterns, the lower portion 3a of the n-type current diffusion region 3, the upper portion 3b of the n-type current diffusion region 3, + type region 21, p + The lower portions 22a and p of the mold region 22 + The widths w1, w2, w3, w11, w21, and w22 of the upper portion 22b of the mold region 22 are determined.

[0089] Specifically, when the sum of the JFET resistance and drift resistance of the SiC-MOSFET (see FIGS. 3 to 5) formed in the chip region 51 (semiconductor chip 30) becomes a predetermined value, the lower portion 3a of the n-type current diffusion region 3, the upper portion 3b of the n-type current diffusion region 3, and the p + type region 21, p + The lower portions 22a and p of the mold region 22 + The combination of the widths w1, w2, w3, w11, w21, and w22 of the upper portion 22b of the mold region 22 is defined as n - The thickness t2 of the drift region 2 and n - The impurity concentration of the type drift region 2 is a variable that is obtained in advance by simulation, experiment, or the like.

[0090] This previously acquired data and the n -Based on the thickness t2 distribution and impurity concentration distribution of the n-type drift region 2, the lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, p + -type region 21, p + the lower part 22a of the p + -type region 22, and the upper part 22b of the p

[0091] At this time, the sum of the JFET resistance and the drift resistance (internal resistance determined by the thickness t2 and impurity concentration of the n-type drift region 2) of the SiC-MOSFET is substantially equal in all chip regions 51 in the plane of the semiconductor wafer 50 (60). The lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, p - -type region 21, p + -type region 22, the lower part 22a of the p + -type region 22, and the upper part 22b of the p + -type region 22 are appropriately changed to adjust the JFET resistance of each chip region 51.

[0092] For example, the JFET resistance can also be adjusted by the impurity concentration of the n-type current diffusion region 3, but the impurity concentration of the n-type current diffusion region 3 also affects the gate threshold voltage. To adjust the JFET resistance without affecting other characteristics of the SiC-MOSFET, it is preferable to change the widths w1, w2, w3, w11, w21, w22 of the lower part 3a of the n-type current diffusion region 3, the upper part 3b of the n-type current diffusion region 3, p + -type region 21, p + -type region 22, the lower part 22a of the p + -type region 22, and the upper part 22b of the p

[0093] In particular, since the width w3 between adjacent p + -type regions 21 and 22 has the greatest influence on the JFET resistance, the width w21 of the lower part 22a of the p + -type region 22 is adjusted so that adjacent p +It is advisable to change the width w3 between the p-type regions 21 and 22. For example, p + Regarding the width w21 of the lower part 22a of the p-type region 22, p + Since there is a lower limit value for obtaining the electric field relaxation effect by the p-type region 22, p + Adjust the width w21 of the lower part 22a of the p-type region 22 in the widening direction so that the p-type regions 21 and 22 adjacent to each other p + Narrow the width w3 between the p-type regions 21 and 22 to increase the JFET resistance.

[0094] Specifically, for example, in a predetermined chip region 51 in the plane of the semiconductor wafer 60, if n - the thickness t2 of the n-type drift region 2 is relatively thin, the drift resistance is relatively low. Therefore, set the JFET resistance of the predetermined chip region 51 high so that the combined resistance value of the JFET resistance and the drift resistance is approximately the same as that of other chip regions 51. To increase the JFET resistance in the predetermined chip region 51, p + widen the width w21 of the lower part 22a of the p-type region 22 so that the p-type regions 21 and 22 adjacent to each other p + narrow the width w3 between them.

[0095] For example, in a predetermined chip region 51 in the plane of the semiconductor wafer 60, if n - the impurity concentration of the n-type drift region 2 is relatively high, the drift resistance is relatively low. Therefore, set the JFET resistance of the predetermined chip region 51 high so that the combined resistance value of the JFET resistance and the drift resistance is approximately the same as that of other chip regions 51. To increase the JFET resistance in the predetermined chip region 51, p + set the width w21 of the lower part 22a of the p-type region 22 wide so that the p-type regions 21 and 22 adjacent to each other p + narrow the width w3 between them.

[0096] Therefore, within the plane of the semiconductor wafer 60, the widths w1, w2, w3, w11, w21, w22 of each part of the JFET section in one chip region 51 serving as a reference are obtained. Compared with this reference chip region 51, any one or more of the widths w1, w2, w3, w11, w21, w22 of each part of the JFET section in other chip regions 51 within the plane of the same semiconductor wafer 60 may be changed to a width that allows the JFET resistance to be adjusted so that a predetermined combined resistance value of the JFET resistance and the drift resistance can be obtained as described above.

[0097] In this way, for all chip regions 51 within the plane of the semiconductor wafer 60, the widths w1, w2, w3, w11, w21, w22 of each part of the JFET section are determined respectively. As a result, a mask pattern for ion implantation for forming each part of the JFET section with different widths w1, w2, w3, w11, w21, w22 for each chip region 51 can be obtained for each chip region 51 within the plane of the semiconductor wafer 60 so that the on-voltage Von of the SiC-MOSFET becomes substantially the same.

[0098] If the impurity concentration of any one or more of each part of the JFET section is appropriately changed for each chip region 51 within the plane of the semiconductor wafer 60, the JFET resistance of each chip region 51 can also be adjusted respectively. In this case, the element structure patterns can be made the same for all chip regions 51 within the plane of the semiconductor wafer 60. However, the ion implantation conditions (dose amount, acceleration energy, number of steps) of each part of the JFET section need to be changed for each chip region 51, resulting in an increase in the number of mask patterns and the number of ion implantation times, and low mass productivity.

[0099] On the one hand, as described above, by appropriately changing any one or more of the widths w1, w2, w3, w11, w21, w22 of each part of the JFET section for each chip region 51 in the plane of the semiconductor wafer 60, the JFET resistance of each chip region 51 is adjusted respectively, so that each part of the JFET section can be simultaneously formed under the same ion implantation conditions in all the chip regions 51 in the plane of the semiconductor wafer 60. Therefore, compared with the case of adjusting the JFET resistance by changing the impurity concentration of each part of the JFET section, the number of ion implantation times can be reduced, and the mass productivity is high.

[0100] Next, as shown in FIGS. 10 and 11, each part of the JFET section is formed by photolithography and ion implantation (step S4: element structure formation step). Specifically, a resist film (not shown) serving as a mask for ion implantation is formed on the surface of the n - type epitaxial layer 58a. Next, the surface of the n - type epitaxial layer 58a is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed, so that all the chip regions 51 open the portions corresponding to the formation regions of the p + type region 21 and the lower part 22a of the p + type region 22.

[0101] Next, as shown in FIG. 10, p-type impurities are ion implanted using the resist film as a mask for ion implantation, and the p - type region 21 and the lower part 22a of the p + type region 22 are selectively formed in the surface region of the n + type epitaxial layer 58a respectively. As a result, in each chip region 51 in the plane of the semiconductor wafer 60, the p + type region 21 and the lower part 22a of the p + type region 22 are formed at a predetermined interval (= w3) apart from each other and with predetermined widths w11, w21. Then, the resist film used for forming the p + type region 21 and the lower part 22a of the p + type region 22 is removed.

[0102] Also, n -A resist film (not shown) serving as a mask for ion implantation is newly formed on the surface of the p-type epitaxial layer 58a. Next, n - The surface of the n-type epitaxial layer 58a is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed, and the portions corresponding to the formation regions of the n-type regions 23 are opened in all the chip regions 51. Next, using this resist film as a mask for ion implantation, n-type impurities are ion implanted, and n - In the surface region of the n-type epitaxial layer 58a, an n-type region 23 is formed at a position deeper than the lower portion 22a of the p + type region 22. Then, the resist film used for forming the n-type region 23 is removed.

[0103] Also, n - A resist film (not shown) serving as a mask for ion implantation is newly formed on the surface of the n-type epitaxial layer 58a. Next, n - The surface of the n-type epitaxial layer 58a is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed, and the portions corresponding to the formation regions of the lower portions 3a of the n-type current diffusion regions 3 are opened in all the chip regions 51. Next, using this resist film as a mask for ion implantation, n-type impurities are ion implanted, and n - In the surface region of the n-type epitaxial layer 58a, the lower portions 3a of the n-type current diffusion regions 3 are formed with a predetermined width w1 between the adjacent lower portions 22a of the p + type regions 22. Then, the resist film used for forming the lower portions 3a of the n-type current diffusion regions 3 is removed.

[0104] Also, n - A resist film (not shown) serving as a mask for ion implantation is newly formed on the surface of the n-type epitaxial layer 58a. Next, n - The surface of the n-type epitaxial layer 58a is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed, and n - the portions corresponding to the formation regions of the n-type current diffusion regions 3c (see FIG. 5) are opened in all the chip regions 51. Next, using this resist film as a mask for ion implantation, n-type impurities are ion implanted, and n- In the surface region of the p-type epitaxial layer 58a, p + An n-type current diffusion region 3c is formed between the lower part 22a of the p-type region 22 and the lower part 3a of the n-type current diffusion region 3 (not shown in FIGS. 10 to 14). Then, the resist film used for forming the n-type current diffusion region 3c is removed. - type current diffusion region 3c is formed (not shown in FIGS. 10 to 14). Then, the resist film used for forming the n - type current diffusion region 3c is removed.

[0105] If the n-type current diffusion region 3c is not arranged in all the chip regions 51 in the plane of the semiconductor wafer 60, the resist film with the entire active region 41 opened is used as a mask for ion implantation to implant n-type impurities, so that the n-type current diffusion region 3c is formed over the entire surface of the active region 41. - type current diffusion region 3c is not arranged, an n-type impurity is ion-implanted using a resist film with the entire active region 41 opened as a mask for ion implantation, so that the lower part 3a of the n-type current diffusion region 3 is formed in the surface region of the n-type epitaxial layer 58a over the entire active region 41. As a result, the lower part 3a of the n-type current diffusion region 3 is formed in contact with the p - type epitaxial layer 58a. Thus, the lower part 3a of the n-type current diffusion region 3 is formed in contact with the p + type region 21 and the lower part 22a of the p + type region 22 over the entire area between the lower parts 22a of the adjacent p + type regions 22.

[0106] p + type region 21, p + type region 22, the lower part 22a of the n-type region 23, the lower part 3a of the n-type current diffusion region 3, and the n - type current diffusion region 3c can be formed in any order. The p + type region 21 and the p + type region 22, the lower part 22a thereof, may be formed in different processes. The n - type epitaxial layer 58a, the p + type region 21, p + type region 22, the lower part 22a thereof, the n-type region 23, the lower part 3a of the n-type current diffusion region 3, and the n - type current diffusion region 3c, the part on the n + type starting wafer 57 side becomes the n - type drift region 2. In each chip region 51 in the plane of the semiconductor wafer 60, the n - type drift region 2 remains with the thickness t2 obtained in the process of step S2.

[0107] Next, as shown in FIG. 11, further n - -type epitaxial layer 58a (on semiconductor wafer 60) is epitaxially grown with an n - -type epitaxial layer 58b to increase the thickness of the semiconductor wafer 50 by increasing the thickness of the n - -type epitaxial layer 58 (58a, 58b) to a predetermined thickness t4. Next, a resist film (not shown) serving as a mask for ion implantation is formed on the surface of the n - -type epitaxial layer 58b. The impurity concentration of the n - -type epitaxial layer 58b may be the same as the impurity concentration of the n - -type current diffusion region 3d (see FIG. 5). In this case, the step of forming the n - -type current diffusion region 3d can be omitted.

[0108] Next, the surface of the n - -type epitaxial layer 58b is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed to open in all chip regions 51 the portion corresponding to the formation region of the upper part 22b of the p + -type region 22. Next, using this resist film as a mask for ion implantation, p-type impurities are ion-implanted into the n - -type epitaxial layer 58b (the portion where the thickness of the n - -type epitaxial layer 58 is increased) to form the upper part 22b of the p + -type region 22 with a predetermined width w22. Then, the resist film used for forming the upper part 22b of the p + -type region 22 is removed.

[0109] Also, a resist film (not shown) serving as a mask for ion implantation is newly formed on the surface of the n - -type epitaxial layer 58b. Next, the surface of the n - -type epitaxial layer 58b is scanned, and the predetermined mask pattern obtained in step S3 is transferred to the resist film for each shot 56 and developed to open in all chip regions 51 the portion corresponding to the formation region of the upper part 3b of the n-type current diffusion region 3. Next, using this resist film as a mask for ion implantation, n-type impurities are ion-implanted into the n -On the surface region of the p-type epitaxial layer 58b, between the upper portions 22b of the p-type regions 22 adjacent to each other + Form the upper portion 3b of the n-type current diffusion region 3 having a predetermined width w2 (see FIG. 13) from the trench 7 to be formed later between the upper portions 22b of the p-type regions 22. Then, remove the resist film used for forming the upper portion 3b of the n-type current diffusion region 3.

[0110] Also, on the surface of the n - type epitaxial layer 58b, newly form a resist film (not shown) serving as a mask for ion implantation. Next, scan the surface of the n - type epitaxial layer 58b and transfer the predetermined mask pattern obtained in step S3 to the resist film for each shot 56 and develop it, and open in all chip regions 51 the portion corresponding to the formation region of the n - type current diffusion region 3d. Next, use this resist film as a mask for ion implantation to implant n-type impurities, and in the surface region of the n - type epitaxial layer 58b, between the upper portion 22b of the p + type region 22 and the upper portion 3b of the n-type current diffusion region 3, form an n - type current diffusion region 3d (not shown in FIGS. 11 to 14). Then, remove the resist film used for forming the n - type current diffusion region 3d.

[0111] If the n - type current diffusion region 3d is not arranged in all chip regions 51 in the plane of the semiconductor wafer 50, use the resist film with the entire active region 41 opened as a mask for ion implantation to implant n-type impurities, so that over the entire active region 41, form the upper portion 3b of the n - type epitaxial layer 58b on the surface region. As a result, between the upper portions 22b of the p + type regions 22 adjacent to each other, over the entire area, the upper portion 3b of the n-type current diffusion region 3 is formed in contact with the upper portions 22b of these p + type regions 22.

[0112] The upper portion 22b of the p + type region 22, the upper portion 3b of the n-type current diffusion region 3, and the n -The p-type current diffusion regions 3d are each p in the depth direction + formed at the lower portions 22a of the p-type regions 22, the lower portions 3a of the n-type current diffusion regions 3, and positions facing the n - type current diffusion regions 3c, and are each p in the depth direction + formed at the lower portions 22a of the p-type regions 22, the lower portions 3a of the n-type current diffusion regions 3, and positions facing the n - type current diffusion regions 3c and connected thereto. The p + type regions 22 at the upper portions 22b, the upper portions 3b of the n-type current diffusion regions 3, and the n - type current diffusion regions 3d can be formed in a replaceable order (first step).

[0113] Next, Vernier patterns 14 (see FIG. 3) are formed in each chip region 51 in the plane of the semiconductor wafer 50 (step S5: mark formation step). Further, a position identification mark (not shown) is formed on the semiconductor wafer 50 at the dicing line 52 (see FIG. 1). When the dicing line 52 is not formed on the semiconductor wafer 50, the dicing line 52 may be formed on the front surface of the semiconductor wafer 50 and then the position identification mark may be formed. These Vernier patterns 14 and position identification marks only need to be formed by the process of step S7 described later.

[0114] Next, the remaining various processes for forming the remaining element structure of the SiC-MOSFET are performed (step S6). Specifically, as shown in FIG. 12, on the n - type epitaxial layer 58, a p-type epitaxial layer 59 that becomes the p-type base region 4 is epitaxially grown to thicken the semiconductor wafer 50 to the product thickness (second step). By the steps up to here, on the front surface of the n + type starting wafer 57, a semiconductor wafer 50 with the epitaxial layers 58 and 59 laminated in order with the product thickness is fabricated (manufactured).

[0115] Next, in each chip region 51 in the plane of the semiconductor wafer 50, the portion of the edge termination region 42 of the p-type epitaxial layer 59 is removed, and the lower layer n of the p-type epitaxial layer 59 is formed in the edge termination region 42 -Expose the type epitaxial layer 58. Next, by a general method, in each chip region 51 in the plane of the semiconductor wafer 50, a predetermined breakdown voltage structure is formed on the surface region of the n - type epitaxial layer 58 (not shown).

[0116] Next, photolithography and ion implantation are repeatedly performed under different conditions, and in the active region 41 of each chip region 51 in the plane of the semiconductor wafer 50, an n + type source region 5 and a p ++ type contact region 6 are selectively formed respectively. The portion of the p-type epitaxial layer 59 on the n + type source region 5 and the p ++ type contact region 6 and closer to the n - type epitaxial layer 58 side becomes the p-type base region 4 (third step).

[0117] Next, for all the diffusion regions (p + type regions 21, 22, n-type region 23, n-type current diffusion regions 3, n - type current diffusion regions 3c, 3d, n + type source region 5 and p ++ type contact region 6) formed in the epitaxial layers 58 and 59 by ion implantation, a heat treatment for impurity activation is performed. Instead of performing the heat treatment for impurity activation collectively for all the diffusion regions, it may be performed each time a diffusion region is formed by ion implantation.

[0118] Next, as shown in FIG. 13, by photolithography and etching, in each chip region 51 in the plane of the semiconductor wafer 50, a trench 7 is formed that penetrates the n + type source region 5 and the p-type base region 4 in the depth direction from the front surface (the surface of the p-type epitaxial layer 59) of the semiconductor wafer 50 and reaches the lower portion 3a of the n-type current diffusion region 3 (fourth step). The bottom surface of the trench 7 may end inside the p + type region 21.

[0119] Next, as shown in FIG. 14, a gate electrode 9 is formed inside the trench 7 via a gate insulating film 8 by a general method (fifth step). Next, an interlayer insulating film 11 covering the gate electrode 9 is formed on the front surface of the semiconductor wafer 50 by a general method. Next, a source electrode 12 and a drain electrode 15 are formed on the front and back surfaces of the semiconductor wafer 50, respectively, in each chip region 51 in the plane of the semiconductor wafer 50 by a general method (sixth and seventh steps).

[0120] Next, the semiconductor wafer 50 is diced (cut) into individual semiconductor chips 30 (step S7), and the SiC-MOSFET (silicon carbide semiconductor device 10) shown in FIGS. 3 to 5 is completed. By going through the processes of steps S2 to S4 described above, the on-voltage Von of the SiC-MOSFET is substantially the same for all the semiconductor chips 30 diced from the same semiconductor wafer 50.

[0121] Next, by mounting and sealing a plurality of semiconductor chips 30 (SiC chips), wirings, etc. on the front surface of the insulating substrate 70 by a general assembling process (step S8), the semiconductor module (semiconductor circuit device 80) shown in FIG. 6 is completed. Since the on-voltage Von of the SiC-MOSFET is substantially the same for all the semiconductor chips 30 connected in parallel in the semiconductor module, local heat concentration does not occur in some of the semiconductor chips 30 in the semiconductor module.

[0122] Note that the manufacturing methods of the silicon carbide semiconductor device 10 and the semiconductor circuit device 80 described in this embodiment can be realized by executing a pre-prepared program on a computer such as a personal computer or a workstation, a database server, or a web server. Further, this program may be a transmission medium that can be distributed via a network such as the Internet.

[0123] The information obtained through this program and the processes of steps S2 and S3 is recorded on a computer-readable recording medium such as a solid state drive (SSD), hard disk, Blu-ray (registered trademark) Disc, flexible disk, USB flash memory, CD-ROM, MO, DVD, etc., and is used or executed by being read from the recording medium by a computer or server.

[0124] As described above, according to the embodiment, for each chip region in the plane of the semiconductor wafer, one or more widths of each part of the JFET part are appropriately changed to adjust the JFET resistance of each chip region. At this time, based on the thickness distribution and impurity concentration distribution of the n-type drift region in the plane of the semiconductor wafer (furthermore, a plurality of semiconductor wafers), the JFET resistance of each chip region is adjusted so that the sum (synthetic resistance value) of the JFET resistance and the drift resistance is substantially the same in all chip regions in the plane of the semiconductor wafer. - By mixing chip regions with a plurality of element structure patterns in which one or more widths of each part of the JFET part are different from each other in the plane of the semiconductor wafer in this way, the on-voltage of the SiC-MOSFET is set to be substantially the same in all chip regions in the plane of the semiconductor wafer.

[0125] Therefore, all semiconductor chips diced from the same semiconductor wafer and furthermore a plurality of semiconductor wafers can be incorporated into the same semiconductor module without sorting. The variation in the on-voltage between all semiconductor chips incorporated into the same semiconductor module can be made non-existent or as small as possible. For this reason, heat concentration on some semiconductor chips in the semiconductor module does not occur, the power cycle tolerance can be maintained, and the reliability can be improved. Also, since all semiconductor chips diced from the same semiconductor wafer and furthermore a plurality of semiconductor wafers can be incorporated into the same semiconductor module, it is difficult to have a fraction less than the number of chips to be incorporated into the semiconductor module, and the yield can be improved.

[0126] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Further, the present invention is similarly applicable even when the conductivity type (n-type, p-type) is reversed.

Industrial Applicability

[0127] As described above, the silicon carbide semiconductor device, the method of manufacturing a silicon carbide semiconductor device, and the semiconductor circuit device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Signs

[0128] 1 n + Type drain region 2 n - Type drift region 3 n-type current diffusion region Lower part of 3a n-type current diffusion region Upper part of 3b n-type current diffusion region 4 p-type base region 5 n + Type source region 6 p ++ Type contact region 7 Trench 8 Gate insulating film 9 Gate electrode 10 Silicon carbide semiconductor device 11 Interlayer insulating film 12 Source electrode 13 Gate pad 14 Vernier pattern 15 Drain electrode 21 p-type region facing the bottom of the trench + Type region 22 p-type region between trenches + Type region 22a Lower part of the p-type region between trenches + Type region 22b Upper part of the p-type region between trenches + Type region 23 n-type region 30 Semiconductor chip 31,57 n+ Type starting substrate 32, 32a, 58, 58a, 58b n - Type epitaxial layer 33, 59 p-type epitaxial layer 41 Active region 42 Edge termination region 50, 60 Semiconductor wafer 51 Chip region of semiconductor wafer 52 Dicing line of semiconductor wafer 53, 53a, 53b Inactive region of semiconductor wafer 54 PCM 55 Orientation flat of semiconductor wafer 56 Exposure range (shot) of semiconductor wafer per exposure 61 Measurement position of thickness and impurity concentration of semiconductor wafer 70 Insulating substrate 71 Insulating board constituting the insulating substrate 72 Copper plate on the front surface of the insulating substrate 73 Heat sink on the back surface of the insulating substrate 74a, 74b Solder layer 75, 76 Implant pins 77a, 77b Terminals for external electrodes 78 Sealing material 79 Printed circuit board 80 Semiconductor circuit device O Center of semiconductor wafer t1, t4 n - Thickness of the type epitaxial layer t2 n - Thickness of the type drift region t3 Thickness of the lower part of the n-type current diffusion region w1 Width of the lower part of the n-type current diffusion region, w2 Width of the upper part of the n-type current diffusion region w3 Width between the p-type region facing the trench bottom and the p + type region between the trench and the p + type region w11 Width of the p-type region facing the trench bottom + Width of the type region w21 Width of the lower part of the p-type region between the trenches + Width of the lower part of the type region p between the w22 trenches + Upper width of the type region

Claims

1. A deposition step of manufacturing a semiconductor wafer by epitaxially growing a first conductivity type epitaxial layer on one main surface of a starting wafer made of silicon carbide; An element structure forming step of forming a silicon carbide semiconductor device having a predetermined element structure in each of a plurality of chip regions that are separated from the semiconductor wafer to form semiconductor chips; comprising: The element structure forming step includes: On the surface region of the first conductivity type epitaxial layer, a second conductivity type first high-concentration region and a second conductivity type second high-concentration region are selectively formed separately from each other, and between the first high-concentration region and the second high-concentration region, a first conductivity type first current diffusion region having a higher impurity concentration than the first conductivity type epitaxial layer is formed, and a portion of the first conductivity type epitaxial layer excluding the first high-concentration region, the second high-concentration region, and the first current diffusion region is used as a first conductivity type first semiconductor region in a first step; After the first step, on the first conductivity type epitaxial layer, a second conductivity type epitaxial layer having a lower impurity concentration than the first high-concentration region and the second high-concentration region, which is in contact with the second high-concentration region and separated from the first high-concentration region, is epitaxially grown to make the thickness of the semiconductor wafer a predetermined thickness in a second step; A third step of forming a first conductivity type third semiconductor region in the surface region of the second conductivity type epitaxial layer, leaving a second conductivity type second semiconductor region in the second conductivity type epitaxial layer that is in contact with the second high-concentration region; A fourth step of forming a trench that is separated from the second high-concentration region, penetrates the third semiconductor region and the second semiconductor region in the depth direction to reach the first current diffusion region, and has a bottom surface facing the first high-concentration region; A fifth step of forming a gate electrode in the trench via a gate insulating film; A sixth step of forming a first electrode electrically connected to the third semiconductor region and the second semiconductor region; A seventh step of forming a second electrode on the other main surface of the starting wafer; comprising: Before the element structure forming step, A first acquisition step of acquiring the thickness distribution and impurity concentration distribution of the first semiconductor region in the plane of the semiconductor wafer; Based on the thickness and impurity concentration of the first semiconductor region for each chip region in the plane of the semiconductor wafer obtained in the first acquisition step, the sum of the JFET resistance of the portion between the adjacent first high-concentration region and the second high-concentration region and the drift resistance of the first semiconductor region is the same for all the chip regions in the plane of the semiconductor wafer. A second acquisition step of acquiring the width of the first current diffusion region, the width of the first high-concentration region, and the width of the second high-concentration region that can adjust the JFET resistance for each chip region in the plane of the semiconductor wafer, is further included. In the first step, by forming the first high-concentration region, the second high-concentration region, and the first current diffusion region with the predetermined widths obtained in the second acquisition step, respectively, a plurality of chip regions in which the widths of any one or more of the first high-concentration region, the second high-concentration region, and the first current diffusion region are different from each other are formed to be mixed in the plane of the semiconductor wafer. A method for manufacturing a silicon carbide semiconductor device, characterized in that.

2. In the second acquisition step, a mask pattern for forming the first high-concentration region, the second high-concentration region, and the first current diffusion region is acquired respectively. In the first step, a step of forming a mask with the mask patterns different for each exposure range and a step of performing ion implantation using the mask are repeated as a set of steps to form the first high-concentration region, the second high-concentration region, and the first current diffusion region respectively. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that.

3. After the deposition step, a mark forming step of forming a predetermined mark on the first main surface of the semiconductor wafer for each chip region is further included. The predetermined mark is a mark for specifying the design value of the width of the first current diffusion region, the width of the first high-concentration region, and the width of the second high-concentration region for each chip region. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, characterized in that.

4. After the deposition step, a mark forming step of forming a predetermined mark on the first main surface of the semiconductor wafer for each chip region is further included. The predetermined mark is a mark for specifying the mask pattern for each chip region. The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that.

5. The element structure forming step is performed in the active region of the chip region. In the mark formation step, the method for manufacturing a silicon carbide semiconductor device according to claim 3 or 4, characterized in that the predetermined mark is formed outside the active region of the chip region.

6. The element structure formation step further includes, before the second step, a step of forming a second current diffusion region of the first conductivity type having an impurity concentration lower than that of the first current diffusion region between the first current diffusion region and the second high-concentration region in the surface region of the first conductivity type epitaxial layer. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5, characterized in that.

7. In the first step, The second high-concentration region is formed by dividing it into a relatively deep lower part and a relatively shallow upper part and connecting them in the depth direction. The first current diffusion region is formed by dividing it into a relatively deep lower part and a relatively shallow upper part and connecting them in the depth direction. In the second acquisition step, As the width of the second high-concentration region, the width of the lower part of the second high-concentration region and the width of the upper part of the second high-concentration region are acquired. As the width of the first current diffusion region, the width of the lower part of the first current diffusion region and the width of the upper part of the first current diffusion region are acquired. In the first step, by forming the first high-concentration region, the lower part of the second high-concentration region, the upper part of the second high-concentration region, the lower part of the first current diffusion region, and the upper part of the first current diffusion region with the predetermined widths acquired in the second acquisition step, respectively, a plurality of the chip regions in which one or more widths of the first high-concentration region, the lower part of the second high-concentration region, the upper part of the second high-concentration region, the lower part of the first current diffusion region, and the upper part of the first current diffusion region are different from each other are formed to be mixed in the plane of the semiconductor wafer. The method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized in that.

8. An epitaxial layer is epitaxially grown on one main surface of a starting substrate made of silicon carbide, and a semiconductor chip having the surface of the epitaxial layer as the first main surface and the other main surface of the starting substrate as the second main surface. A first semiconductor region of the first conductivity type provided inside the epitaxial layer. A second semiconductor region of the second conductivity type provided between the first main surface of the semiconductor chip and the first semiconductor region in the active region. A third semiconductor region of the first conductivity type selectively provided between the first main surface of the semiconductor chip and the second semiconductor region. A first current diffusion region of a first conductivity type, which is selectively provided between the second semiconductor region and the first semiconductor region and has a higher impurity concentration than the first semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first current diffusion region, A gate electrode provided in the trench via a gate insulating film, A first high-concentration region of a second conductivity type, which is selectively provided between the second semiconductor region and the first semiconductor region and faces the bottom surface of the trench and has a higher impurity concentration than the second semiconductor region, A second high-concentration region of a second conductivity type, which is selectively provided between the second semiconductor region and the first semiconductor region, contacts the second semiconductor region in the depth direction, and faces the trench and the first high-concentration region across the first current diffusion region in a direction parallel to the first main surface of the semiconductor chip and has a higher impurity concentration than the second semiconductor region, A first electrode electrically connected to the third semiconductor region and the second semiconductor region, A second electrode provided on the second main surface of the semiconductor chip, A predetermined mark formed on the first main surface of the semiconductor chip outside the active region, Comprising, The predetermined mark is a mark for specifying design values of the width of the first current diffusion region, the width of the first high-concentration region, and the width of the second high-concentration region, respectively. A silicon carbide semiconductor device characterized by this.

9. Further comprising a termination region in which a predetermined breakdown voltage structure is arranged between the active region and an end portion of the semiconductor chip, The silicon carbide semiconductor device according to claim 8, wherein the predetermined mark is formed on the first main surface of the semiconductor chip in the termination region.

10. A termination region in which a predetermined breakdown voltage structure is arranged between the active region and an end portion of the semiconductor chip, and A dicing line that serves as a switching point when dicing the semiconductor chip from a semiconductor wafer, remaining between the termination region and the end portion of the semiconductor chip, Further comprising, The silicon carbide semiconductor device according to claim 8, wherein the predetermined mark is formed on the first main surface of the semiconductor chip at the dicing line.

11. A semiconductor circuit device in which a semiconductor chip on which a silicon carbide semiconductor device having a predetermined element structure is formed is mounted, The semiconductor chip is formed by epitaxially growing an epitaxial layer on one main surface of a starting substrate made of silicon carbide, with the surface of the epitaxial layer being the first main surface and the other main surface of the starting substrate being the second main surface. The silicon carbide semiconductor device a first semiconductor region of a first conductivity type provided inside the epitaxial layer; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor chip and the first semiconductor region in the active region; a third semiconductor region of a first conductivity type selectively provided between the first main surface of the semiconductor chip and the second semiconductor region; a first current diffusion region of a first conductivity type selectively provided between the second semiconductor region and the first semiconductor region and having a higher impurity concentration than the first semiconductor region; a trench penetrating through the third semiconductor region and the second semiconductor region in the depth direction and reaching the first current diffusion region; a gate electrode provided inside the trench via a gate insulating film; a first high-concentration region of a second conductivity type selectively provided between the second semiconductor region and the first semiconductor region and facing the bottom surface of the trench and having a higher impurity concentration than the second semiconductor region; a second high-concentration region of a second conductivity type selectively provided between the second semiconductor region and the first semiconductor region, in contact with the second semiconductor region in the depth direction, and facing the trench and the first high-concentration region across the first current diffusion region in a direction parallel to the first main surface of the semiconductor chip and having a higher impurity concentration than the second semiconductor region; a first electrode electrically connected to the third semiconductor region and the second semiconductor region; a second electrode provided on the second main surface of the semiconductor chip, and a plurality of the semiconductor chips in which the thickness or impurity concentration, or both, of the first semiconductor region are different, and the widths of any one or more of the first current diffusion region, the first high-concentration region, and the second high-concentration region are different from each other are mixed and mounted, the sum of the JFET resistance of the portion between the first high-concentration region and the second high-concentration region adjacent to each other in all the semiconductor chips and the drift resistance of the first semiconductor region is the same, A semiconductor circuit device characterized in that the total amount of the main current flowing through all the semiconductor chips connected in parallel is defined as the maximum current amount.

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