Stacked memory

Abstract

To provide a stacked memory for constructing a low power memory structure and improving yields of the stacked memory in the stacked memory having a plurality of bank groups each including a plurality of banks and through electrode groups provided per each bank group.SOLUTION: A stacked memory includes: a plurality of four or more memory dies stacked on each other and each including a plurality of banks; a plurality of through electrode groups each including a plurality of through electrodes penetrating the plurality of memory dies; and a plurality of bank groups including the bank arranged on two or more of the memory dies and respectively connecting to either of the plurality of through electrode groups. Each of the plurality of memory dies includes one of the plurality of bank groups.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a stacked memory.

Background Art

[0002] The storage capacity of memory devices such as DRAM (Dynamic Random Access Memory) used in systems tends to increase, and the data transfer rate of the systems also tends to increase. As a memory device that can increase the storage capacity and increase the data transfer rate without increasing the size of the memory device, a stacked memory having a plurality of memory dies stacked on each other and through electrodes penetrating the memory dies is known.

[0003] For example, in this type of stacked memory, a plurality of banks, which are units activated during memory access, are arranged in each memory die, and the banks facing each other between the memory dies are connected to the input / output buffer of the stacked memory via a common through electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] For example, in the case of Patent Document 1 and Patent Document 2, a plurality of sub-memory arrays or banks are provided in each memory die of the stacked memory, and the sub-memory arrays or banks at the same position in each memory die are connected by one or more through electrodes. Since all the through electrodes are connected to all the memory dies, when the number of stacked memory dies increases, the parasitic capacitance connected to the through electrodes increases due to the capacitance of the memory cells or the switches provided between the through electrodes and the memory cells. For this reason, the power for transmitting signals through the through electrodes increases.

[0006] In addition, a fixed number of sub-memory arrays or banks, such as one or four, are connected to the through electrodes. Therefore, if there is a defect in a certain sub-memory array or bank, the entire stacked memory will become defective. As the number of stacked memory dies increases, the defect rate increases exponentially.

[0007] Also, the bank realizes high-speed access by accessing memory cells with slow response characteristics in parallel with a time shift. In order to increase the speed, if the number of banks connected to each through electrode is increased and the number of banks arranged in the memory die is increased, the die size of each stacked memory die also increases. The larger the die size, the lower the yield of the memory die, and the lower the yield of the stacked memory.

[0008] Therefore, an object of the present invention is to construct a low-power memory structure and improve the yield of a stacked memory in a stacked memory having a plurality of bank groups each including a plurality of banks and a through electrode group provided for each bank group.

Means for Solving the Problems

[0009] A stacked memory according to one embodiment of the present invention includes a plurality of four or more memory dies stacked on each other and each including a plurality of banks, a plurality of through electrode groups each including a plurality of through electrodes penetrating the plurality of memory dies, a plurality of bank groups including the banks disposed in two or more of the memory dies, and each connected to one of the plurality of through electrode groups. Each of the plurality of memory dies includes one of the plurality of bank groups.

Advantages of the Invention

[0010] According to the present invention, in a stacked memory having a plurality of bank groups each including a plurality of banks and a through electrode group provided for each bank group, a low-power memory structure can be constructed and the yield of the stacked memory can be improved.

Brief Description of the Drawings

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[0012] Hereinafter, embodiments will be described with reference to the drawings. In each drawing, the same reference numerals are assigned to the same components, and redundant descriptions may be omitted. The reference numerals indicating signal names are also used as reference numerals indicating signal line names. A single signal line may be composed of a plurality of lines.

[0013] (First Embodiment) FIG. 1 is an exploded perspective view showing an example of a stacked memory according to the first embodiment of the present invention. The stacked memory MEM1 shown in FIG. 1 has eight memory dies MD (MD0-MD7) sequentially stacked on a base die BD. For example, each memory die MD has a memory cell of a DRAM.

[0014] Each of the even-numbered memory dies MD0, MD2, MD4, and MD5 has eight banks BK0-BK7. The odd-numbered memory dies MD1, MD3, MD5, and MD7 have eight banks BK8-BK15. For example, a bank BK is a unit activated by an active command received from the outside during memory access, and one of the banks BK0-BK15 is selected by a bank address assigned to 4 bits of the memory address.

[0015] In this embodiment, the banks BK0 - BK15 included in the memory dies MD0 and MD1 belong to the bank group BG0 of the channel CH0. The banks BK0 - BK15 included in the memory dies MD2 and MD3 belong to the bank group BG1 of the channel CH1. The banks BK0 - BK15 included in the memory dies MD4 and MD5 belong to the bank group BG2 of the channel CH2. The banks BK0 - BK15 included in the memory dies MD6 and MD7 belong to the bank group BG3 of the channel CH3.

[0016] Note that the number of memory dies MD mounted on the stacked memory MEM1 is not limited to 8. The number of banks BK included in each memory die MD is not limited to 8. The number of banks BK belonging to each bank group BG is not limited to 16. The number of bank groups BG assigned to the stacked memory MEM1 may be a plurality, and is not limited to 4. Also, the number of memory dies MD to which one bank group BG is assigned may be 2 or more.

[0017] Each channel CH (CH0 - CH3) corresponds to a group of data lines DT that connect the external data terminals of the stacked memory MEM (i.e., the data lines of the base die BD) and each bank BK. For example, each bank BK of the channel CH0 is connected to the external data terminal of the channel CH0 via the group of data lines DT of the channel CH0. Each bank BK of the channel CH1 is connected to the external data terminal of the channel CH1 via the group of data lines DT of the channel CH1. The groups of data lines DT of the channels CH0 - CH3 can transfer data independently of each other. Hereinafter, the group of data lines DT is also simply referred to as the data line DT.

[0018] In FIG. 1, the rectangular regions CH0 - CH3 shown in the central part of each memory die MD indicate the regions where the TSVs (Through - Silicon Vias) of each channel CH are formed. The TSVs penetrate each rectangular region CH0 - CH3 of each memory die MD and are connected to the base die BD. The TSV is an example of a through - electrode. The TSVs will be described with reference to FIG. 2.

[0019] FIG. 2 is a diagram showing an example of the wiring of the data line DT of the stacked memory MEM1 in FIG. 1. FIG. 2 shows an overview of the arrangement of the banks BK of each memory die MD and the wiring of the data line DT connecting each bank BK and the TSV, by fusing a plan view and a cross-sectional view.

[0020] In FIG. 2, each of the reference numerals TSV0 - TSV3 indicates a TSV group including, for example, 128 TSVs. The TSV groups TSV0 - TSV3 are an example of a through - electrode group, and the TSVs included in the TSV groups TSV0 - TSV3 are an example of through - electrodes. Hereinafter, the TSV groups TSV0 - TSV3 are also referred to as group TSV0 - TSV3 or TSV groups.

[0021] Each bank BK0 - BK15 of the memory dies MD0, MD1 of channel CH0 is connected to group TSV0 via a common data line DT wired to each of the memory dies MD0, MD1. Each bank BK0 - BK15 of the memory dies MD2, MD3 of channel CH1 is connected to group TSV1 via a common data line DT wired to each of the memory dies MD2, MD3.

[0022] Each bank BK0 - BK15 of the memory dies MD4, MD5 of channel CH2 is connected to group TSV2 via a common data line DT wired to each of the memory dies MD4, MD5. Each bank BK0 - BK15 of the memory dies MD6, MD7 of channel CH3 is connected to group TSV3 via a common data line DT wired to each of the memory dies MD6, MD7. As shown in FIG. 2, each bank group BG (that is, each channel CH) is connected to one of the TSV groups (TSV0 - TSV3).

[0023] For example, the data lines DT of each memory die MD are 128 in number, which is the same as the number of TSVs in the TGV group. And each data line DT is connected to the corresponding TSV. In this embodiment, since different TSV groups are independently connected to each channel CH, the stacked memory MEM1 can simultaneously input or output data to any one of the 16 banks BK of each channel CH. When multiplexed data is transmitted on the data lines DT, the number of TSVs in each TSV group can be set to one-half or one-fourth of the number of data lines DT.

[0024] FIG. 3 is a diagram showing an example of the connection between each bank BK and the TSV group in FIG. 2. Also in FIG. 3, similar to FIG. 2, a plan view and a cross-sectional view are shown in combination. In FIG. 3, for ease of explanation, the bank BK of each memory die MD is arranged on one side of the group TSV0-TSV3. However, the bank BK of each memory die MD is arranged on both sides of the group TSV0-TSV3, similar to FIG. 2.

[0025] The data lines DT connected to each bank in each memory die MD are connected to the TSV group corresponding to its own channel CH via a multiplexer MUX. The multiplexer MUX connects the data line ST connected to the bank BK indicated by the bank address to the TSV group.

[0026] For example, in the bank group BG2 of channel CH2, when inputting data to any one of banks BK0-BK7 or outputting data from any one of banks BK0-BK7, the multiplexer MUX of memory die MD5 is set to high impedance. Similarly, in the bank group BG2 of channel CH2, when inputting data to any one of banks BK8-BK15 or outputting data from any one of banks BK8-BK15, the multiplexer MUX of memory die MD4 is set to high impedance.

[0027] Each group of TSVs TSV0 - TSV3 is connected to the base die BD through the memory dies MD0 - MD7 and is connected to each data line group DTG (DTG0 - DTG3) on the base die BD. Each data line group DTG0 - DTG3 includes a plurality of data lines. For example, the plurality of data lines in each data line group DTG0 - DTG3 are connected to different external data terminals (not shown). And for each group of TSVs TSV0 - TSV3, a data signal can be independently supplied to the bank BK from outside the stacked memory MEM1 through the external data terminals, and a data signal from the bank BK can be independently output from each group of TSVs TSV0 - TSV3 to the external data terminals.

[0028] Although not particularly limited, for example, the number of bits of the data line DT of each channel CH and the number of TSVs included in the TSV group may be an integer multiple of the number of bits of the external data terminal. Alternatively, the number of bits of the data line DT of each channel CH and the number of TSVs included in the TSV group may be an integer multiple of the number obtained by adding the number of bits for ECC (Error - Correcting Code) to the number of bits of the external data terminal.

[0029] FIG. 4 is a diagram showing an example of the die sizes of the memory die MD7 of the stacked memory MEM1 in FIG. 1 and the memory dies MD of other stacked memories. In the stacked memory MEM1 shown in FIGS. 1 to 3, the banks BK0 - BK15 of one channel CH are distributed and arranged in two memory dies MD. Therefore, compared with other stacked memories in which the banks BK0 - BK15 of one channel CH are arranged in one memory die MD, the size of the memory die MD can be reduced.

[0030] For example, when the banks BK are arranged in two columns on both lateral sides of the rectangular region CH0 - CH3 where the TSVs are arranged, assuming that the distance from the center of the rectangular region CH0 - CH3 to the lateral end of the stacked memory MEM1 is L1. In this case, the distance L1 can be made approximately half of the distance L2 from the center of the rectangular region CH0 - CH3 to the lateral end of the other stacked memory shown in FIG. 4, and the die size can also be made approximately half.

[0031] Since the size of the memory die MD can be reduced, the yield of the memory die MD can be improved. Here, semiconductor integrated circuits such as the memory die MD manufactured using a semiconductor substrate have a higher yield, which is the good product rate, as the chip size is smaller. By improving the yield of the memory die MD, the yield of the stacked memory MEM1 in which a plurality of memory dies MD are stacked can also be improved.

[0032] Also, by dispersing and arranging the bank BK of one channel CH among a plurality of memory dies MD, the wiring length of the data line DT can be shortened. As a result, compared with the case where the bank BK of one channel CH is arranged in one memory die MD, the wiring capacitance of the data line DT can be reduced, and the power consumption of the memory die MD can be reduced.

[0033] FIG. 5 is a diagram showing an example of a cross section of the stacked memory MEM1 of FIG. 1 and other stacked memories. For example, the stacked memory MEM1 is manufactured bump-free using a WOW (Wafer on Wafer) process. The thickness of the stacked memory MEM1 having eight memory dies MD0-MD7 manufactured by the WOW process is T1. On the other hand, in other stacked memories such as HBM (High-Bandwidth Memory) that connect the memory die MD via microbumps BP or the like, the thickness when eight memory dies MD0-MD7 are stacked becomes T2, which is six times or more of T1. Also, when the WOW process is used, the capacitance of the TSV can be made about 1 / 20 of the capacitance of the TSV of the existing structure in the case of connecting the memory die MD via microbumps BP or the like.

[0034] For example, by dispersing and arranging a bank BK of one channel CH across two memory dies MD, the number of stacked layers of the memory die MD is doubled. In the bump-less WOW structure shown in FIG. 5, the wiring capacitance of the TSV corresponds to the capacitance of wiring with a length of 30 μm within each memory die MD. Therefore, the sum of the wiring capacitance within each memory die MD of the stacked memory MEM1 and the wiring capacitance of the TSV can be made smaller than the sum of the wiring capacitance within each memory die MD and the wiring capacitance of the TSV when a bank BK of one channel CH is arranged in one memory die MD.

[0035] As described above, in this embodiment, the plurality of banks BK arranged in the plurality of memory dies MD are assigned to any one of the bank groups BG (channels CH). Also, each bank group BG is connected to any one of the group of TSVs 0 - TSV3 connected to different data terminal groups DTG. Thereby, compared to the case where one bank group BG is arranged in one memory die MD, the size of the memory die MD can be reduced, and the yield of the memory die MD and the yield of the stacked memory MEM1 can be improved.

[0036] Also, by dispersing and arranging a bank BK of one channel CH across a plurality of memory dies MD, the wiring length of the data line DT can be shortened. Thereby, compared to the case where one bank group BG is arranged in one memory die MD, the wiring capacitance of the data line DT can be reduced, and the power consumption of the memory die MD can be reduced.

[0037] (Second Embodiment) FIG. 6 is a diagram showing an example of a stacked memory according to the second embodiment of the present invention. For elements similar to those in the above-described embodiment, the same reference numerals are given, and detailed description thereof is omitted. The stacked memory MEM2 shown in FIG. 6 has a plurality of memory dies MD (MD0 - MD7) sequentially stacked on the base die BD, similar to the stacked memory MEM1 in FIG. 1. The stacked memory MEM2 may be manufactured, for example, by a WOW process, similar to the stacked memory MEM1.

[0038] Similar to FIG. 2, each of the even-numbered memory dies MD0, MD2, MD4, and MD5 has banks BK0 - BK7. The odd-numbered memory dies MD1, MD3, MD5, and MD7 have banks BK8 - BK15. However, each memory die MD has eight bank blocks BKBLK each including a rectangular region CH0 - CH3 where eight banks BK and TSVs of group TSV0 - TSV3 of each memory die MD of the stacked memory MEM1 in FIG. 1 are arranged.

[0039] By using the WOW process, it is possible to easily manufacture a stacked memory MEM2 that has a plurality of bank blocks BKBLK and has a larger die size than the stacked memory MEM1 in FIG. 2. Also, since design data such as circuit data and layout data of each bank block BKBLK is common, the degree of freedom in selecting the number of mounted bank blocks BKBLK can be improved. As a result, it is possible to easily design a stacked memory MEM2 according to the required memory capacity.

[0040] By mounting a plurality of bank blocks BKBLK on the stacked memory MEM2, for example, the size of each bank BK can be made the same as the bank BK shown in FIG. 2. For this reason, in each bank block BKBLK, the distance from the center of the rectangular regions CH0 - CH3 to the lateral end of the bank block BKBLK can be made the same as L1 in FIG. 4. Note that the die size of the stacked memory MEM2 is about eight times the die size of the stacked memory MEM1 in FIG. 2.

[0041] FIG. 7 is a diagram showing an example of the wiring of data lines of the stacked memory in FIG. 6. For elements similar to those in FIG. 2, the same reference numerals are given and detailed descriptions are omitted. FIG. 7 shows an example in which each bank BK is connected to the TSV group via a data line DT at a cut along the line A - A' in FIG. 6. Examples of the connection between each bank BK and the TSV group at cuts along the lines B - B', C - C', and D - D' in FIG. 6 are also the same as in FIG. 7.

[0042] The configuration at each notch is the same as that in FIG. 2, except that the data line DT is routed through two bank blocks BKBLK shown in FIG. 6, and there are two sets of group TSV0 - TSV3. Two TSV groups with the same number at each notch are commonly connected to any of the data line groups DTG (DTG0 - DTG3) of the base die BD. And each TSV of each group TSV0 - TSV3 is connected to a common external data terminal of the stacked memory MEM2 via the base die BD.

[0043] In this way, at each notch, each of the two bank blocks BKBLK of each memory die MD is connected to two common TSV groups (either TSV0 - TSV3). At the four notches shown in FIG. 6, each of the eight bank blocks BKBLK of each memory die MD is connected to eight common TSV groups (either TSV0 - TSV3).

[0044] FIG. 8 is a diagram showing an example of the bank arrangement of another stacked memory. Each memory die MD0 - MD7 of the other stacked memory shown in FIG. 8 has four bank blocks BKBLK each containing 16 banks BK and rectangular regions CH0 - CH3 of the memory die MD of the other stacked memory shown in FIG. 4. The distance from the center of the rectangular regions CH0 - CH3 to the lateral ends of each bank block BKBLK is L2 as in FIG. 4.

[0045] Therefore, also in this embodiment, the distance L1 of the stacked memory MEM2 can be made approximately half of the distance L2 of the other stacked memory, and the wiring length of the data line DT can be shortened. Thereby, compared with the case where the banks BK of one channel CH (that is, the bank group BG) are arranged in one memory die MD, the wiring capacitance of the data line DT can be reduced, and the power consumption of the memory die MD can be reduced.

[0046] As described above, in this embodiment as well, the same effects as those of the above-described embodiment can be obtained. Furthermore, in this embodiment, a plurality of bank blocks BKBLK are arranged in each memory die MD. As a result, even in the stacked memory MEM2 with a large die size, the wiring length L1 of the data line DT can be made the same as that of the data line DT of the stacked memory MEM1 with an 8-fold smaller die size. Therefore, the power consumption of the memory die MD can be reduced.

[0047] (Third Embodiment) FIG. 9 is a diagram showing an example of a stacked memory according to the third embodiment of the present invention. The same elements as those in the above-described embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. In the stacked memory MEM3 shown in FIG. 9, each of the bank groups BG (BG3 - BG0) of each channel CH (CH3 - CH0) has a redundant memory die MD(R) including a redundant bank for remedying a defect of the bank BK. That is, the redundant memory die MD(R) is provided for each of a plurality of memory dies MD. The stacked memory MEM3 may be manufactured, for example, by the WOW process, similarly to the stacked memory MEM1.

[0048] In FIG. 9 as well, for the sake of easy understanding of the description, the bank BK is arranged on one side of the group of TSV0 - TSV3, similarly to FIG. 3. However, the arrangement of the bank BK of each memory die MD and each redundant memory die MD(R) is the same as that in FIG. 2.

[0049] The stacked memory MEM3 has memory dies MD0, MD1, MD3, MD4, MD6, MD7, MD9, MD10 corresponding to the eight memory dies MD0 - MD7 in FIG. 1, and four redundant memory dies MD2(R), MD5(R), MD8(R), MD11(R). Note that the total number of the memory dies MD and the redundant memory dies MD(R) mounted on the stacked memory MEM3 is not limited to 12.

[0050] The configuration and functions of the redundant memory die MD(R) are the same as those of a normal memory die MD. The bank BK mounted on the redundant memory die MD(R) is an example of a redundant bank that operates in place of a defective bank BK included in the memory die MD. Hereinafter, when the normal memory die MD and the redundant memory die MD(R) are described without distinction, they are simply also referred to as the memory die MD.

[0051] Each memory die MD and each redundant memory die MD(R) have a multiplexer MUX that selects a bank BK according to a bank address. The multiplexer MUX provided in the memory die MD is an example of a connection part. The multiplexer MUX provided in the redundant memory die MD(R) is an example of a redundant connection part.

[0052] In FIG. 9, the channels CH are numbered in the multiplexer MUX. The eight inputs of the multiplexer MUX are respectively connected to the data terminals of the eight banks BK. The output of the multiplexer MUX is connected to the TSV group corresponding to the channel CH. Note that the number of banks BK arranged in each memory die MD is not limited to eight. The bank BK marked with an X indicates that it is defective.

[0053] The multiplexer MUX of the memory die MD for each channel CH connects the normally operating bank BK among the eight banks BK of each memory die MD to the TSV group, and cuts off the connection between the defective bank BK that does not operate normally and the TSV group. Then, the multiplexer MUX of the redundant memory die MD(R) remedies the defective bank BK by connecting any one of the normal banks BK of the redundant memory die MD(R) to the TSV group in place of the defective bank BK.

[0054] For example, in the bank group BG2 of channel CH2, when data is input to any one of banks BK0, BK2 - BK5, BK7, or when data is output from any one of banks BK0, BK2 - BK5, BK7, the multiplexer MUX2 of memory dies MD7, MD8(R) is set to high impedance. Similarly, in the bank group BG2 of channel CH2, when data is input to any one of banks BK8 - BK13, BK15, or when data is output from any one of banks BK8 - BK13, BK15, the multiplexer MUX2 of memory dies MD6, MD8(R) is set to high impedance. Similarly, in the bank group BG2 of channel CH2, when data is input to any one of the salvaged banks BK1, BK6, BK14, or when data is output from any one of the salvaged banks BK1, BK6, BK14, the multiplexer MUX2 of memory dies MD6, MD7 is set to high impedance.

[0055] In FIG. 9, the data line DT indicated by the solid line shows that it is connected to the TSV group for use in memory access, and the data line DT indicated by the dashed line shows that it is not connected to the TSV group because it is not used in memory access. In the redundant memory die MD(R), the bank BK without a bank number indicates that it is not used. In this embodiment, as described above, defective banks BK can be salvaged after stacking a plurality of memory dies MD. As a result, defects occurring after the stacking of the memory dies MD can be salvaged.

[0056] As described above, in this embodiment as well, the same effects as those of the above-described embodiments can be obtained. For example, by dispersing and arranging the banks BK0 - BK15 of each channel CH in two memory dies MD, the size of the memory die MD can be reduced, and the yield of the memory die MD and the stacked memory MEM3 can be improved.

[0057] Furthermore, in this embodiment, by providing a redundant memory die MD(R) for each channel CH, it is possible to salvage the defective bank BK of the memory die MD, and improve the yield of the stacked memory MEM3. When manufacturing the stacked memory MEM3 using the WOW process, the operation test for each memory die MD can be omitted. Therefore, a decrease in the test efficiency of the stacked memory MEM2 can be suppressed. As a result, the test cost can be reduced, and the manufacturing cost of the stacked memory MEM2 can be reduced.

[0058] (Fourth Embodiment) FIG. 10 is a diagram showing an example of a stacked memory according to the fourth embodiment of the present invention. For elements similar to those in the above-described embodiments, the same reference numerals are given, and detailed descriptions are omitted. The stacked memory MEM4 shown in FIG. 10 may be manufactured by the WOW process, similarly to the stacked memory MEM1.

[0059] In this embodiment, the stacked memory MEM4 has a redundant memory die MD2(R) shared by the bank groups BG0 and BG1, and a redundant memory die MD7(R) shared by the bank groups BG2 and BG3. That is, the redundant memory die MD(R) is provided for each of a plurality (two in this example) of bank groups BG.

[0060] Therefore, the stacked memory MEM4 has memory dies MD0, MD1, MD3, MD4, MD5, MD6, MD8, MD9 corresponding to the eight memory dies MD0 - MD7 in FIG. 1, and two redundant memory dies MD2(R) and MD7(R). Note that the total number of the memory dies MD and the redundant memory dies MD(R) mounted on the stacked memory MEM4 is not limited to ten.

[0061] The bank BK (redundant bank) of the redundant memory die MD2(R) is used to salvage the defective banks BK of bank groups BG0 and BG1. The bank BK (redundant bank) of the redundant memory die MD7(R) is used to salvage the defective banks BK of bank groups BG2 and BG3. By sharing the redundant memory die MD(R) among a pair of bank groups BG, the number of redundant memory dies MD(R) mounted on the stacked memory MEM4 can be minimized, and defective banks BK can be salvaged.

[0062] Similar to FIG. 9, the bank BK marked with an X indicates that it is defective. In the redundant memory die MD(R), the bank BK without a bank number indicates that it is not used. Also, in the redundant memory die MD(R), the channel number attached below the bank number indicates the channel CH to which the defective bank BK belongs.

[0063] FIG. 11 is a diagram showing an example of salvaging a defective bank BK in the stacked memory MEM4 of FIG. 10. For elements similar to those in FIG. 9, the same reference numerals are used, and detailed descriptions are omitted. In FIG. 11, examples of bank groups BG2 and BG3 (memory dies MD5, MD6, MD7(R), MD8, MD9) of FIG. 10 are shown, but the examples of bank groups BG0 and BG1 are the same as in FIG. 11.

[0064] The circuit configuration of a normal memory die MD (MD5, MD6, etc.) is the same as the circuit configuration of the memory die MD in FIG. 9. The redundant memory die MD7(R) has eight selectors SEL whose inputs are respectively connected to the data terminals of eight banks BK. Also, the redundant memory die MD7(R) has a multiplexer MUX2 whose output is connected to the group TSV2 and a multiplexer MUX3 whose output is connected to the group TSV3.

[0065] The eight inputs of multiplexer MUX2 are respectively connected to one of the outputs of the eight selectors SEL. The eight inputs of multiplexer MUX3 are respectively connected to one of the outputs of the eight selectors SEL. Each selector SEL connects the data terminal of bank BK to the input of multiplexer MUX2 when the bank address of the rescued bank BK indicates bank group BG2 (= CH2). Each selector SEL connects the data terminal of bank BK to the input of multiplexer MUX3 when the bank address of the rescued bank BK indicates bank group BG3 (= CH3).

[0066] Multiplexers MUX2, MUX3 and selector SEL are an example of a redundant connection part. Multiplexers MUX2, MUX3 are an example of a first redundant connection part respectively connected to groups TSV2, TSV3. Selector SEL is an example of a second redundant connection part that connects the redundant bank BK to either multiplexer MUX2 or MUX3.

[0067] For example, in bank group BG2 of channel CH2, when data is input to any of banks BK0, BK2 - BK5, BK7, or when data is output from any of banks BK0, BK2 - BK5, BK7, the multiplexer MUX2 of memory dies MD6, MD7(R) is set to high impedance. Similarly, in bank group BG2 of channel CH2, when data is input to any of banks BK8 - BK13, BK15, or when data is output from any of banks BK8 - BK13, BK15, the multiplexer MUX2 of memory dies MD5, MD7(R) is set to high impedance. Similarly, in bank group BG2 of channel CH2, when data is input to any of the rescued banks BK1, BK6, BK14, or when data is output from any of the rescued banks BK1, BK6, BK14, the multiplexer MUX2 of memory dies MD5, MD6 is set to high impedance.

[0068] As described above, in this embodiment as well, the same effects as those of the above-described embodiments can be obtained. Further, in this embodiment, by sharing the redundant memory die MD(R) among two bank groups BG, the number of redundant memory dies MD(R) mounted on the stacked memory MEM4 can be minimized, and defective banks BK can be recovered. By reducing the number of stacked memory dies MD, the yield of the stacked memory MEM4 can be improved.

[0069] Note that the circuit configuration of each memory die MD may be the same as that of the redundant memory die MD7(R). In this case, design data such as circuit data and layout data of the memory die MD and each redundant memory die MD(R) can be shared, and design costs and manufacturing costs can be reduced.

[0070] (Fifth Embodiment) FIG. 12 is a diagram showing an example of a stacked memory according to the fifth embodiment of the present invention. The same elements as those in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The stacked memory MEM5 shown in FIG. 12 may be manufactured by a WOW process, similarly to the stacked memory MEM3 in FIG. 9.

[0071] In this embodiment, the stacked memory MEM5 has three redundant memory dies MD2(R), MD4(R), MD6(R). The redundant memory die MD2(R) is shared by the R bank groups BG0 and BG1. The redundant memory die MD4(R) is shared by the bank groups BG1 and BG2. The redundant memory die MD6(R) is shared by the bank groups BG2 and BG3. The redundant memory die MD4(R) is provided in place of the memory dies MD4 and MD5 in FIG. 10. Thereby, each redundant memory die MD(R) can be used to recover the memory dies MD adjacent in the layer direction.

[0072] For example, memory dies MD0, MD1, and MD3 respectively correspond to the memory dies MD0, MD1, and MD2 in FIG. 1. The redundant memory die MD4(R) corresponds to the memory dies MD3 and MD4 in FIG. 1. Memory dies MD5, MD7, and MD8 respectively correspond to the memory dies MD5, MD6, and MD7 in FIG. 1.

[0073] By arranging the redundant memory die MD4(R) in place of the memory dies MD3 and MD4 in FIG. 1 and using it to remedy the defects of bank groups BG1 and BG2, the number of stacked memory dies MD in the stacked memory MEM5 can be reduced by one compared to the stacked memory MEM4 in FIG. 10. By reducing the number of stacked layers, the yield of the stacked memory MEM5 can be improved. Note that the total number of memory dies MD and redundant memory dies MD(R) mounted on the stacked memory MEM5 is not limited to nine.

[0074] FIG. 13 is a diagram showing an example of remedying a defective bank in the stacked memory SEM5 of FIG. 12. The same elements as in FIG. 11 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. In this embodiment, the circuit configuration of each memory die MD is the same as the configuration of the redundant memory die MD7(R) in FIG. 11.

[0075] That is, each memory die MD and each redundant memory die MD(R) have eight selectors SEL respectively connected to the data terminals of eight banks BK with eight inputs. Also, each memory die MD and each redundant memory die MD(R) have a multiplexer MUX (MUX2 or MUX3) to which the outputs of the selectors SEL are respectively connected to the corresponding TSV group. By making the circuit configurations of each memory die MD and each redundant memory die MD(R) the same as each other, design data such as circuit data and layout data can be shared, and the design cost and manufacturing cost can be reduced.

[0076] The multiplexer MUX of each memory die MD is an example of a first connection part, and the selector SEL of each memory die MD is an example of a second connection part. The multiplexer MUX of each redundant memory die MD(R) is an example of a first redundant connection part, and the selector SEL of each redundant memory die MD(R) is an example of a second redundant connection part.

[0077] Note that since the memory die MD7 including the bank BK of the bank group BG3 corresponds to the group TSV3, one of the two multiplexers MUX3 is not used. The output of the unused multiplexer MUX3 does not have to be connected to any of the TSV groups. Similarly, one of the two multiplexers MUX2 of the memory die MD5 does not have to be connected to any of the TSV groups.

[0078] For example, in the bank group BG2 of the channel CH2, when inputting data to any of the banks BK4 - BK9, BK10, or when outputting data from any of the banks BK4 - BK9, BK10, the multiplexer MUX2 of the memory die MD6(R) is set to high impedance. Similarly, in the bank group BG2 of the channel CH2, when inputting data to any of the banks BK11 - BK15, or when outputting data from any of the banks BK11 - BK15, the multiplexer MUX2 of the memory die MD5 is set to high impedance.

[0079] As described above, also in this embodiment, the same effects as those of the above-described embodiment can be obtained. Further, in this embodiment, by arranging the redundant memory die MD4(R) instead of a plurality of normal memory dies MD, the stacking number of the memory dies MD of the stacked memory MEM5 can be reduced, and the yield of the stacked memory MEM5 can be improved.

[0080] Also, by making the circuit configurations of each memory die MD and each redundant memory die MD(R) the same as each other, design data can be shared, and design costs and manufacturing costs can be reduced.

[0081] (Embodiment 6) FIG. 14 is a diagram showing an example of a stacked memory according to the sixth embodiment of the present invention. The same elements as those in the above-described embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. The stacked memory MEM6 shown in FIG. 14 may be manufactured by the WOW process in the same manner as the stacked memory MEM3 in FIG. 9.

[0082] In this embodiment, the stacked memory MEM6 has one redundant memory die MD8(R) common to all the memory dies MD0-MD7 mounted on the stacked memory MEM6. The redundant memory die MD8(R) has eight selectors SEL corresponding to each of the eight banks BK, and five multiplexers MUX corresponding to each of the four TSV groups.

[0083] The input of each selector SEL is connected to the data terminal of the corresponding bank BK. The four outputs of each selector SEL are respectively connected to any of the eight inputs of the multiplexers MUX0, MUX1, MUX2, and MUX3. The outputs of the multiplexers MUX0-MUX3 are connected to the inputs of the corresponding groups TSV0-TSV3. Thereby, the defective bank BK of all the memory dies MD can be rescued by one redundant memory die MD8(R).

[0084] For example, in the bank group BG3 of channel CH3, when data is input to any of banks BK0 - BK4, BK6, BK7, or when data is output from any of banks BK0 - BK4, BK6, BK7, the multiplexer MUX of memory die MD7 and the multiplexer MUX3 of memory die MD8(R) are set to high impedance. Similarly, in the bank group BG3 of channel CH3, when data is input to any of banks BK8, BK9, BK11 - BK15, or when data is output from any of banks BK8, BK9, BK11 - BK15, the multiplexer MUX of memory die MD6 and the multiplexer MUX3 of memory die MD8(R) are set to high impedance. Similarly, in the bank group BG3 of channel CH3, when data is input to any of banks BK5, BK10 rescued by channel CH3, or when data is output from any of banks BK5, BK10 rescued by channel CH3, the multiplexers MUX of memory dies MD6 and MD7 are set to high impedance.

[0085] As described above, in this embodiment as well, the same effects as those of the above-described embodiment can be obtained. Further, in this embodiment, all defective banks BK of the memory dies MD can be rescued by one redundant memory die MD8(R). Also, by mounting a minimum number of redundant memory dies MD8(R) in the stacked memory MEM6, the stacking number of the memory dies MD in the stacked memory MEM6 can be reduced, and the yield of the stacked memory MEM6 can be improved.

[0086] Note that the circuit configuration of each memory die MD may be made the same as that of the redundant memory die MD8(R). In this case, design data such as circuit data and layout data of the memory die MD and each redundant memory die MD(R) can be shared, and the design cost and manufacturing cost can be reduced.

[0087] Although the present invention has been described based on each embodiment above, the present invention is not limited to the requirements shown in the above embodiments. Regarding these points, it can be changed without departing from the gist of the present invention, and can be appropriately determined according to its application form.

Explanation of Signs

[0088] BD Base Die BK Bank BKBLK Bank Block BG Bank Group BP Microbump CH Channel DT Data Line DTG Data Line Group MD Memory Die MD(R) Redundant Memory Die MEM1, MEM2, MEM3 Stacked Memory MEM4, MEM5, MEM6 Stacked Memory MUX Multiplexer SEL Selector TSV0 - TSV3 TSV Group

Claims

1. a plurality of four or more memory dies stacked on one another and each including a plurality of banks; a plurality of through - electrode groups each including a plurality of through - electrodes penetrating the plurality of memory dies; a plurality of bank groups including the banks disposed in two or more of the memory dies and each connected to one of the plurality of through - electrode groups; and having each of the plurality of memory dies includes one of the plurality of bank groups A stacked memory characterized by that.

2. a plurality of the bank groups provided in each of the two or more memory dies; a plurality of the through - electrode groups provided corresponding to each of the plurality of bank groups; and having each of the bank groups provided in each of the memory dies is connected to one of the corresponding plurality of through - electrode groups The stacked memory according to claim 1, characterized by that.

3. having a redundant memory die having a redundant bank that operates in place of the defective bank included in the memory die The stacked memory according to claim 1 or claim 2, characterized by that.

4. The redundant memory die is provided for each of the plurality of memory dies to which the bank group is assigned The stacked memory according to claim 3, characterized by that.

5. The redundant memory die is shared by a plurality of the memory dies to which different bank groups are respectively assigned The stacked memory according to claim 3, characterized by that.

6. The redundant memory die is provided in common for all of the memory dies The stacked memory according to claim 3, characterized by that.

7. each of the plurality of memory dies has a connection part that connects a normally operating bank in the bank group assigned to the self - memory die to the corresponding through - electrode group according to a bank address; The redundant memory die has a redundant connection part that connects the redundant bank to the through - electrode group corresponding to the bank address of the defective bank The stacked memory according to any one of claims 3 to 6, characterized by that.

8. The connection part includes a predetermined number of first connection parts each connected to a corresponding one of the predetermined number of through - electrode groups; a second connection part that connects the bank to one of the predetermined number of first connection parts; and having The redundant connection part includes a predetermined number of first redundant connection parts each connected to a corresponding one of the predetermined number of through - electrode groups; A second redundant connection portion that connects the redundant bank to any one of the predetermined number of first redundant connection portions The stacked memory according to claim 7, characterized in that

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