Semiconductor memory device including a capacitor

Abstract

To provide a semiconductor memory device.SOLUTION: A semiconductor memory device according to some embodiments includes a peripheral logic structure disposed on a substrate and including a peripheral circuit, a horizontal semiconductor layer on the peripheral logic structure, a laminate structure in which a mold layer and an electrode pad are stacked alternately in a first direction on the horizontal semiconductor layer, electrode separation regions extending in the first direction and a second direction, separating the laminate structure, and connected to the horizontal semiconductor layer, and penetration structures penetrating the laminate structure with the peripheral logic structure in the first direction and having one side connected to a penetration channel contact. Each electrode pad can form a capacitor with at least one of the electrode separation regions or at least one of the penetration structures.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a three-dimensional semiconductor memory device including a capacitor and having improved reliability and integration density.

Background Art

[0002] In order to meet the excellent performance and low cost required by consumers, it is required to increase the integration density of semiconductor devices. In the case of semiconductor devices, since the integration density is an important factor determining the product price, an increased integration density is particularly desired. In the case of two-dimensional or planar semiconductor devices, the integration density is mainly determined by the area occupied by a unit memory cell, and thus is greatly affected by the level of micro-patterning technology.

[0003] However, since ultra-high-cost equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor devices is increasing but still limited. Therefore, memory devices including memory cells arranged three-dimensionally have been proposed.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device including a vertical channel structure with improved reliability and integration density.

[0005] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] One aspect according to some embodiments of the semiconductor memory device of the present invention for solving the above problems is a peripheral logic structure disposed on a substrate and including a plurality of peripheral circuits, a horizontal semiconductor layer disposed on the upper surface of the peripheral logic structure, a plurality of stacked structures in which a mold layer and an electrode pad are alternately stacked in a first direction on the horizontal semiconductor layer, a plurality of electrode separation regions extending in the first direction and the second direction and separating the plurality of stacked structures and coupling to the horizontal semiconductor, a plurality of through structures penetrating the plurality of stacked structures in the first direction in a peripheral region and having one side coupled to a through channel contact, and each electrode pad may form a capacitance with at least one of the plurality of electrode separation regions or at least one of the plurality of through structures.

[0007] One aspect according to some embodiments of the semiconductor memory device of the present invention for solving the above problems is a plurality of stacked structures including a memory cell array region and a peripheral region in which a mold layer and an electrode pad are alternately stacked in a first direction on a horizontal semiconductor layer, a plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures, and a plurality of through structures penetrating the stacked structures in the first direction in a peripheral region between at least two adjacent electrode separation regions and having one side coupled to a through channel contact, and the plurality of stacked structures in the peripheral region may be stacked with the same width in the second direction and the third direction.

[0008] One aspect according to some embodiments of the semiconductor memory device of the present invention for solving the above problems is at least one peripheral region in which a mold layer and an electrode pad are alternately arranged on a horizontal semiconductor layer, a plurality of electrode separation regions each extending in a word line direction and vertically in the peripheral region and spaced apart from each other, a mold region disposed between two adjacent electrode separation regions among the plurality of electrode separation regions, and a plurality of through structures each vertically penetrating the mold region, and each electrode pad may form a capacitor with at least one of the plurality of through structures or at least one of the plurality of electrode separation regions.

[0009] Specific contents of other embodiments are included in the detailed description and the drawings.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5a

Figure 5b

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Figure 7

Figure 8a

Figure 8b

Figure 9a

Figure 9b

Figure 10a

Figure 10b

Figure 10c

Figure 11

Figure 12

DETAILED DESCRIPTION OF THE INVENTION

[0011] FIG. 1 is a block diagram showing a semiconductor memory device according to some embodiments.

[0012] Referring to FIG. 1, a semiconductor memory device 10 according to some embodiments may include a memory cell array 20 and a peripheral circuit 30. The semiconductor memory device 10 may include, for example, a NAND flash memory (NAND Flash Memory), a vertical NAND flash memory (Vertical NAND; VNAND), a NOR flash memory (NOR Flash Memory), a resistive random access memory (Resistive Random Access Memory: RRAM), a phase change memory (Phase-Change Memory: PRAM), a magnetoresistive random access memory (Magneto resistive Random Access Memory: MRAM), a ferroelectric random access memory (Ferroelectric Random Access Memory: FRAM), a spin transfer torque random access memory (Spin Transfer Torque Random Access Memory: STT-RAM), etc., but the embodiments are not limited to such examples.

[0013] Hereinafter, the case where the semiconductor device 10 is a vertical NAND flash memory (VNAND) will be taken as an example to describe the technical idea of the present invention, but the embodiments according to the technical idea of the present invention are not limited to such examples. That is, the embodiments according to the technical idea of the present invention are applicable to any of the non-volatile memories described above.

[0014] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell blocks BLK1 to BLKn may be coupled to the peripheral circuit 30 via bit lines BL, word lines WL, at least one string selection line SSL, and at least one ground selection line GSL.

[0015] Specifically, the memory cell blocks BLK1 to BLKn may be coupled to the row decoder 33 via word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. Also, the memory cell blocks BLK1 to BLKn may be coupled to the page buffer 35 via bit lines BL.

[0016] The peripheral circuit 30 can receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and can transmit and receive data DATA with a device outside the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35.

[0017] Although not shown in the drawings, the peripheral circuit 30 may further include various sub - circuits such as an input / output circuit, a voltage generation circuit that generates various voltages necessary for the operation of the semiconductor memory device 10, and an error correction circuit for correcting an error in the data DATA read from the memory cell array 20.

[0018] The control logic 37 may be coupled to the row decoder 33, the voltage generator, and the input / output circuit. The control logic 37 can control the overall operation of the semiconductor memory device 10. The control logic 37 can generate various internal control signals used within the semiconductor memory device 10 in response to the control signal CTRL.

[0019] The control logic 37 may include a processing circuit such as hardware including a logic circuit, a hardware / software combination such as a processor on which software is executed, or a combination unit thereof. For example, more specifically, the processing circuit may include a CPU (Central Processing Unit), an ALU (Arithmetic Logic Unit), a digital signal processor, a microcomputer, an FPGA (Field Programmable Gate Array), a SoC (System on Chip), a programmable logic unit, a microprocessor, an ASIC (Application-Specific Integrated Circuit), etc. The load decoder 33 and the page 35 may also include a processing circuit.

[0020] The control logic 37 can operate in response to a control signal CTRL, a command (CMD), or an instruction input from an external source (e.g., a host, not shown), and here it can access the memory cell array 20 and control the operation of the semiconductor memory device 10.

[0021] For example, the control logic 37 can adjust the voltage levels provided to the word line WL and the bit line BL when executing a memory operation such as a program operation or an erase operation.

[0022] The load decoder 33 can select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and can select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell blocks BLK1 to BLKn. The load decoder 33 can transmit a voltage for executing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn. The page buffer 35 can be coupled to the memory cell array 20 via the bit lines BL. The page buffer 35 can operate as a writer driver or a sense amplifier. Specifically, during a program operation, the page buffer 35 can operate as a writer driver to apply a voltage due to data to be stored in the memory cell array 20 to the bit lines BL. During a read operation, the page buffer 35 can operate as a sense amplifier to sense the data stored in the memory cell array 20.

[0023] FIG. 2 is a perspective view schematically showing a semiconductor memory device according to some embodiments.

[0024] Referring to FIG. 2, a semiconductor memory device according to some embodiments may include a peripheral logic structure PS and a cell array structure CS. The cell array structure CS may be stacked on the peripheral logic structure PS. That is, the peripheral logic structure PS and the cell array structure CS may overlap in a planar view. A semiconductor memory device according to some embodiments may have a COP (Cell Over Peri) structure.

[0025] For example, the cell array structure CS may include the memory cell array 20 of FIG. 1. The peripheral logic structure PS may include the peripheral circuit 30 of FIG. 1.

[0026] The cell array structure CS may include a plurality of memory cell blocks (BLK1 to BLKn) arranged on the peripheral logic structure PS.

[0027] FIG. 3 is a circuit diagram showing one of the plurality of memory cell blocks included in a semiconductor memory device according to some embodiments.

[0028] Referring to FIG. 3, a memory cell block according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0029] A plurality of cell strings CSTR may be coupled in parallel to each of the bit lines BL0 - BL2. The plurality of cell strings CSTR may be commonly coupled to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL0 - BL2 and one common source line CSL. The common source lines CSL may be arranged two-dimensionally in plurality. Here, the same voltage can be electrically applied to the common source lines CSL, or each of the common source lines CSL can also be electrically controlled.

[0030] For example, each cell string CSTR can be composed of serially connected string selection transistors SST1, SST2, serially connected memory cells MCT, and a ground selection transistor GST. Also, each memory cell MCT includes a data storage element.

[0031] As an example, each cell string CSTR may include serially connected first and second string selection transistors SST1, SST2. The second string selection transistor SST2 may be connected to the bit lines BL0 - BL2, and the ground selection transistor GST may be connected to the common source line CSL. The memory cell MCT may be serially connected between the first string selection transistor SST1 and the ground selection transistor GST.

[0032] Furthermore, each cell string CSTR may further include a dummy cell DMC coupled between the first string selection transistor SST1 and the memory cell MCT. Although not shown in the drawings, the dummy cell DMC may also be coupled between the ground selection transistor GST and the memory cell MCT. As another example, in each cell string CSTR, the ground selection transistor GST may also be composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors SST1 and SST2. As yet another example, each cell string CSTR may include one string selection transistor.

[0033] According to some embodiments, the first string selection transistor SST1 can be controlled by the first string selection line SSL1, and the second string selection transistor SST2 can be controlled by the second string selection line SSL2. The memory cell MCT can be controlled by a plurality of word lines WL0-WLn, and the dummy cell DMC can be controlled by the dummy word line DWL. Also, the ground selection transistor GST can be controlled by the ground selection line GSL. The common source line CSL can be commonly coupled to the source of the ground selection transistor GST.

[0034] One cell string CSTR can be composed of a plurality of memory cells MCT with different distances from the common source line CSL. And a plurality of word lines (WL0-WLn, DWL) can be arranged between the common source line CSL and the bit lines BL0-BL2.

[0035] The gate electrodes of the memory cells MCT arranged at substantially the same distance from the common source line CSL can be commonly coupled to one of the word lines WL0-WLn, DWL and be in an equipotential state. In contrast, the gate electrodes of the memory cells MCT can be arranged at substantially the same level from the common source line CSL, arranged in different rows or columns, and can be independently controlled.

[0036] The ground selection lines GSL0 - GSL2 and the string selection lines SSL1, SSL2 can extend in the same direction as, for example, the word lines WL0 - WLn, DWL. The ground selection lines GSL0 - GSL2 and the string selection lines SSL1, SSL2, which are arranged at substantially the same level from the common source line CSL, can be electrically separated from each other.

[0037] FIG. 4 is a layout diagram showing a semiconductor memory device according to some embodiments, and FIGS. 5a and 5b are plan views showing a part of the plurality of stacked structures shown in FIG. 4 according to some embodiments. FIG. 6 is a plan view showing any one of the stacked structures shown in FIG. 4, and FIG. 7 is a cross-sectional view taken along A - A' shown in FIG. 6.

[0038] The semiconductor device 10 according to some embodiments may include a peripheral logic structure PS and a cell array structure CS.

[0039] The peripheral logic structure PS may include at least one or more peripheral circuits TR and a plurality of lower connection wiring bodies 116. The peripheral circuit TR can be formed on the substrate. According to some embodiments, the peripheral circuit TR can also be included in the page buffer of FIG. 1 and can also be included in the row decoder. Exemplary embodiments of the peripheral circuit TR will be described more specifically in FIG. 11.

[0040] The substrate 100 can be bulk silicon or SOI (silicon - on - insulator). Alternatively, the substrate 100 can be a silicon substrate, or can include other substances, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, but is not limited thereto.

[0041] The peripheral logic insulating film 110 can be formed on the substrate 100. The peripheral logic insulating film 110 can include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0042] The lower connection wiring body 116 can be formed within the peripheral logic insulating film 110. The lower connection wiring body 116 can include a plurality of wiring lines. The lower connection wiring body 116 can include a plurality of layers each having at least one wiring line disposed therein. The lower connection wiring body 116 can be connected to the peripheral circuit TR.

[0043] The cell array structure CS can include a plurality of horizontal semiconductor layers 150 on the peripheral logic structure PS, and a plurality of stacked structures ST0, ST1, ST2, ST3 on each of the horizontal semiconductor layers 150.

[0044] The plurality of horizontal semiconductor layers 150 can be disposed on the peripheral logic structure PS. Each of the horizontal semiconductor layers 150 can extend along the upper surface of the peripheral logic structure PS.

[0045] Each of the horizontal semiconductor layers 150 can include a lower support semiconductor layer LSB and a common source plate CSP on the lower support semiconductor layer LSB. The horizontal semiconductor layer 150 can include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The horizontal semiconductor layer 150 can have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline.

[0046] The common source plate CSP can serve as the common source line CSL in FIG. 3.

[0047] Unlike what is shown, each of the horizontal semiconductor layers 150 can be an overall common source plate CSP without the lower support semiconductor layer LSB.

[0048] Also, unlike what is shown, instead of a two-dimensional planar common source plate, a common source line in the form of a line extending long in the D2 direction can be formed within the horizontal semiconductor layer 150.

[0049] The filling insulating film can be formed on the peripheral logic structure PS. The filling insulating film can fill between the respective horizontal semiconductor layers 150. The filling insulating film can include, for example, but is not limited to, silicon oxide.

[0050] A plurality of stacked structures ST0, ST1, ST2, ST3 can be arranged on each horizontal semiconductor layer 150. The plurality of stacked structures ST0, ST1, ST2, ST3 can be arranged spaced apart from each other along the D1 direction.

[0051] In FIG. 4, the case where there are four stacked structures arranged on each horizontal semiconductor layer 150 is shown for the convenience of explanation and is not limited thereto. In a semiconductor device according to some embodiments, two or more stacked structures can be arranged on each horizontal semiconductor layer 150.

[0052] On each horizontal semiconductor layer 150, the stacked structures ST0, ST1, ST2, ST3 can include a memory cell array region MCR and a peripheral region FR. The memory cell array region MCR corresponds to the memory cell array 20 in FIG. 1, and the peripheral region FR can be a capacitance region where a capacitor used for the peripheral circuit 30 is formed.

[0053] According to some embodiments, a stacked structure can include one memory cell array region MCR0, MCR1 and at least one peripheral region FR0, FR1 in one stacked structure ST0, ST1 as shown in FIG. 5a.

[0054] The peripheral regions FR0, FR1 can extend in the D2 direction (word line direction) and be arranged spaced apart by a predetermined distance D in the D1 direction (bit line direction) in the memory cell array regions MCR0, MCR1.

[0055] In the present exemplary embodiment, the peripheral regions FR0 and FR1 can be electrically connected to the peripheral circuits for the memory cell array regions MCR0 and MCR1 by forming capacitors with a desired and / or preset capacitance as an alternative.

[0056] According to some embodiments, the stacked structure, as shown in FIG. 5b, the stacked structure ST0 includes one memory cell array region MCR0, MCR1, MCR2, and may include at least one peripheral region FR1, FR2 between each memory region.

[0057] The peripheral regions FR1 and FR2 can extend in the D2 direction (word line direction) and be arranged at a predetermined distance in the D1 direction (bit line direction) from the memory cell array region MCR.

[0058] In the present exemplary embodiment, the peripheral regions FR1 and FR2 can be electrically connected to the peripheral circuits for at least two memory cell array regions MCR0, MCR1, MCR2 by forming capacitors with a desired and / or preset capacitance. That is, according to some embodiments, the memory cell array region MCR0 and the memory cell array region MCR1 can be electrically connected to the capacitors of the peripheral region FR0 respectively and used exclusively with each other.

[0059] In the present exemplary embodiment, the peripheral region FR1 can be electrically connected to the peripheral circuits for at least two memory cell array regions MCR1 and MCR2 by forming capacitors with a desired and / or preset capacitance. That is, according to some embodiments, the memory cell array region MCR1 and the memory cell array region MCR2 can be electrically connected to the capacitors of the peripheral region FR1 respectively and used exclusively with each other.

[0060] Although not shown in the drawings, a plurality of peripheral regions FR may be included per memory cell region MCR. As an exemplary embodiment, assuming that two peripheral regions are spaced apart adjacent to one memory cell region, one memory cell region MCR includes a first peripheral region FR A having a first capacitance and a second peripheral region FR B having a second capacitance. The lower peripheral circuit 30 of the memory cell region MCR can be coupled to the first peripheral region FR A with a required capacitor capacitance, can also be connected to the second peripheral region FR B, and can be combined and coupled (such as in series connection or parallel connection) to the first peripheral region FR A and the second peripheral region FR B.

[0061] The following description of the three-dimensional semiconductor device according to the present invention with reference to FIGS. 6 and 7 will be centered on the first stacked structure ST1. It is self-evident that the description of the first stacked structure ST1 is applicable to the second stacked structure ST2, the third stacked structure ST3, and the fourth stacked structure ST0.

[0062] The stacked structure includes a memory cell array region MCR and a peripheral region FR. The stacked structure ST, that is, each of the memory cell array region MCR and the peripheral region FR may include a plurality of electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 stacked in the D3 direction. The first stacked structure ST1 may include an interelectrode insulating film ILD disposed between the plurality of electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7. The case where the first stacked structure ST1 includes seven electrode pads is shown for convenience of explanation and is not limited thereto.

[0063] In the memory cell array region MCR, the plurality of electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 stacked in the D3 direction may include gate electrodes included in the string selection transistors SST1, SST2 and the ground selection transistor GST described in FIG. 3. Also, the plurality of electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 stacked in the D3 direction may include word lines of the memory cell MCT.

[0064] For example, the first stacked structure ST1 may include a fourth electrode pad EP4 and a fifth electrode pad EP5 that are adjacent to each other in the D3 direction. The fifth electrode pad EP5 may be disposed on the fourth electrode pad EP4.

[0065] The fourth electrode pad EP4 may protrude in the D1 direction from the fifth electrode pad EP5. That is, the first side wall of the fourth electrode pad EP4 facing the second stacked structure ST2 and the first side wall of the fifth electrode pad EP5 may be separated by a width that is desired and / or preset as an alternative in the D1 direction.

[0066] The fourth electrode pad EP4 may protrude in the D2 direction from the fifth electrode pad EP5. In the D2 direction, the second side wall of the fourth electrode pad EP4 and the second side wall of the fifth electrode pad EP5 may be separated by a width that is desired and / or preset as an alternative.

[0067] In some embodiments, the width in the D1 direction - the width between the first side walls of the fourth electrode pad EP4 and the fifth electrode pad EP5 - and the width in the D2 direction - the width between the second side walls of the fourth electrode pad EP4 and the fifth electrode pad EP5 - may be the same or different.

[0068] The first stacked structure ST1 may include a cell region CR and a first cell extension region CER1 extending from the cell region CR in the D1 direction. Also, the first stacked structure ST1 may include a second cell extension region CER2 extending from the cell region CR in the D2 direction.

[0069] A plurality of electrode separation regions WLC may be disposed in the first stacked structure ST1. Each electrode separation region WLC may extend in the D2 direction.

[0070] The first stacked structure ST1 may include a plurality of electrode separation trenches EST. Each electrode separation region WLC may be capable of filling each electrode separation trench EST.

[0071] As an example, each electrode separation region WLC may include an insulating material that fills the electrode separation trench EST. The electrode separation region WLC may include, for example, silicon oxide.

[0072] As another example, the electrode separation region WLC may also include a liner formed along the sidewall of the electrode separation trench EST and a filling film on the liner that fills the electrode separation trench EST. As an example, the liner may include an insulating material, and the filling film may include a conductive material. As another example, the liner may include a conductive material, and the filling film may include an insulating material.

[0073] As an example, each electrode separation region WLC may not include an insulating material that fills the electrode separation trench EST. Each electrode separation region WLC may be filled with a conductive material in the electrode separation trench EST.

[0074] The electrode separation region WLC may not be disposed within the first cell extension region CER1. The electrode separation trench EST in which the electrode separation region WLC is formed is used in a replacement process for forming a word line (WLn in FIG. 3). That is, a part of the mold film is removed using the electrode separation trench EST, and a word line is formed in the portion where the mold film is removed.

[0075] In the memory cell region MCR, when the mold film is removed using the electrode separation trench EST, not all of the mold film in the first cell extension region CER1 is removed. Therefore, a remaining mold film that is not removed remains in the first cell extension region CER1. The first cell extension region CER1 includes a first mold region EP_M1 that extends in the D2 direction. That is, the first stacked structure ST1 includes the first mold region EP_M1 disposed on both sides of the cell region CR in the D1 direction.

[0076] In the memory cell array region MCR of a semiconductor memory device according to some embodiments, each of the electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 may include an electrode region EP_E and a first mold region EP_M1. The electrode region EP_E may include, for example, tungsten (W), but is not limited thereto.

[0077] For example, each electrode pad EP may include an electrode region EP_E and a first mold region EP_M1 disposed on both sides of the electrode region EP_E in the D1 direction. The electrode region EP_E can be separated by a plurality of electrode separation regions WLC extending in the D2 direction. The first mold region EP_M1 may extend in the D1 direction from the electrode region EP_E.

[0078] The plurality of electrode separation regions WLC may include a first electrode separation region and a second electrode separation region spaced apart from each other in the D1 direction. At this time, the electrode region EP_E may be disposed between the first electrode separation region and the second electrode separation region. A part of the electrode region EP_E may be located in a region other than between the first electrode separation region and the second electrode separation region.

[0079] In the memory cell array region, the width of the first mold region EP_M1 included in each of the electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 in the D1 direction may decrease as it moves away in the D3 direction in the peripheral logic structure PS. For example, the width of the first mold region EP_M1 in the D1 direction included in the fourth electrode pad EP4 is larger than the width of the first mold region EP_M1 in the D1 direction included in the fifth electrode pad EP.

[0080] For example, in the memory cell array region MCR, the first mold region EP_M1 included in the fourth electrode pad EP4 may protrude by a desired and / or preset width in the D1 direction from the first mold region EP_M1 included in the fifth electrode pad EP5.

[0081] The side walls of the first mold region EP_M1 included in the fourth electrode pad EP4 facing the second stacked structure ST2 in the memory cell array region MCR and the side walls of the first mold region EP_M1 included in the fifth electrode pad EP5 can be separated by a desired width and / or a preset width as an alternative in the D1 direction.

[0082] In the memory cell array region MCR, the side wall profiles of the stepped structure of the first stacked structure ST0 can be defined by the first mold region EP_M1 included in each of the electrode pads EP1, EP2, EP3, EP4, EP5, EP6, and EP7.

[0083] In the memory cell array region MCR, the second cell extension region CER2 can include the second mold region EP_M2. For example, the second mold region EP_M2 included in the fourth electrode pad EP4 can protrude by a desired width and / or a preset width as an alternative in the D2 direction from the second mold region EP_M2 included in the fifth electrode pad EP5.

[0084] The side walls of the second mold region EP_M2 included in the fourth electrode pad EP4 and the side walls of the second mold region EP_M2 included in the fifth electrode pad EP5 in the memory cell array region MCR can be separated by a desired width and / or a preset width as an alternative in the D2 direction.

[0085] The first mold region EP_M2 and the second mold region EP_M2 can each include, for example, silicon nitride, but are not limited thereto.

[0086] In the memory cell array region MCR, a plurality of vertical structures VS penetrating the first stacked structure ST1 can be arranged between adjacent electrode separation regions WLC. Each vertical structure VS can be coupled to the horizontal semiconductor layer 150.

[0087] For example, the vertical structure VS used as the channel region of the memory cell among the vertical structures VS can be electrically connected to the common source plate CSP included in the horizontal semiconductor layer 150.

[0088] The vertical structure VS may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), or a mixture thereof. Alternatively, the vertical structure VS may include a metal oxide semiconductor material. Each of the vertical structures VS may further include a blocking insulating film BIL, a charge storage film CIL, and a tunnel insulating film TIL. The blocking insulating film BIL, the charge storage film CIL, and the tunnel insulating film TIL can be separated at the lower part of the vertical structure VS. A contact support film CSB may be disposed between the separated blocking insulating film BIL, charge storage film CIL, and tunnel insulating film TIL. The contact support film CSB can electrically connect the common source plate CSP and the vertical structure VS. The contact support film CSB may include a semiconductor material such as, for example, silicon (Si), germanium (Ge), or a mixture thereof.

[0089] In the peripheral region of a semiconductor memory device according to some embodiments, each of the electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 may include an electrode region EP_E and a third mold region. The electrode region EP_E may include, for example, tungsten (W), but is not limited thereto.

[0090] The peripheral region FR may be disposed at a distance D desired and / or preset as an alternative in the D1 direction (bit line direction) from the memory cell array region MCR.

[0091] Unlike the memory cell array region MCR, the peripheral region FR does not have to have the same structure as the second cell extension region CER1 and the second cell extension region CER2. As shown in FIG. 7, the side walls of the stacked electrode pads do not have to have a stepped structure (stiar) in the D3 direction. For example, the side wall of the fourth electrode pad EP4 and the side wall of the fifth electrode pad EP5 can be separated in the D2 direction and have the same length. Therefore, the length in the D2 direction of the peripheral region FR, i.e., the width W1, may be narrower than the total length in the D2 direction (CER2 + CR + CER2) of the memory cell array region MCR. The length in the D1 direction of the peripheral region FR, i.e., the width W2, may be narrower than the total length in the D1 direction (CER1 + CR + CER1) of the memory cell array region MCR. In other words, the word line direction length (length) of the peripheral region FR can have a length equal to or less than the word line direction length of the memory cell region MCR.

[0092] The peripheral region FR may include at least two electrode separation regions WLC. The spacing between the electrode separation regions WLC in the peripheral region FR is wider than the spacing between the electrode separation regions WLC when there is no through structure THV. According to one embodiment, adjacent electrode separation regions WLC in the peripheral region FR can be separated by a spacing that is three times or more the spacing between the electrode separation regions WLC when there is no through structure THV. The spacing between the electrode separation regions WLC when there is no through structure THV can be the same as, for example, the spacing S1 when a vertical structure VS is arranged.

[0093] The peripheral region FR may include a plurality of through structures THV between adjacent electrode separation regions WLC. According to some embodiments, the plurality of through structures THV can be separated in the D2 direction and arranged in at least one or more rows, and according to some embodiments, they can also be separated in the D1 direction and arranged in at least one or more columns. Or, according to some embodiments, they can be separated in the D1 direction and the D2 direction respectively and arranged in at least two or more rows and columns.

[0094] The process method for forming the through structure THV may include a method of forming a first structure in which the through structure THV is generated prior to the replacement process, and a method of forming a second structure in which the through structure THV is generated after the replacement process.

[0095] The first structure is a structure generated by first forming a through trench THV_T between adjacent electrode isolation regions WLC, depositing an oxide in the trench, injecting a conductive material to generate a through structure, and then performing a replacement process. The second structure is a structure in which, after the replacement process for each of the adjacent electrode isolation regions WLC, a through trench THV_T is formed, and a conductive material is injected into the through trench THV_T to generate a through structure THV.

[0096] The interval between adjacent electrode isolation regions WLC in the second structure is wider than the interval between adjacent electrode isolation regions WLC in the first structure. Since the interval between adjacent electrode isolation regions WLC according to the second structure is wide, even when the replacement process proceeds, there may be a mold region in a part between the electrode isolation regions WLC where the conductive material is not filled.

[0097] In the peripheral region FR, the through structure THV can be generated by the second structure. That is, the electrode isolation region WLC can be used in the replacement process, and the through structure THV can be generated after the replacement process in the electrode isolation region WLC in the peripheral region FR. The through structure THV can be disposed to penetrate the mold layer between adjacent electrode isolation regions WLC. The mold layer is disposed to extend in the D2 direction between adjacent electrode isolation regions WLC.

[0098] The first interlayer insulating film 151 can be formed on the horizontal semiconductor layer 150. The first interlayer insulating film 151 can cover the stacked structures ST1 and ST2 in the memory cell array region MCR and the peripheral region FR. The first interlayer insulating film 151 can include, for example, silicon oxide, but is not limited thereto.

[0099] The second interlayer insulating film 152 and the third interlayer insulating film 153 can be sequentially formed on the first interlayer insulating film 151. A part of the electrode separation region WLC can extend up to the second interlayer insulating film 152.

[0100] The bit line BL and the through-channel contact line TH_L can be arranged on the stacked structure ST1. The bit line BL can extend long in the D1 direction. The bit line BL can be electrically connected to at least one of a plurality of vertical structures VS in the D1 direction.

[0101] The through-channel contact line TH_L can extend long in the D1 direction and can be electrically connected to at least one of a plurality of through-structures THV1 belonging to the first stacked structure ST0 and at least one of a plurality of through-structures THV1 belonging to the second stacked structure ST1.

[0102] The bit line BL and the through-channel contact line TH_L can be formed on the third interlayer insulating film 153. The bit line BL can be electrically connected to the vertical structure VS via the bit line pad BL_PAD and the bit line plug BL_PG.

[0103] Although not shown in the drawings, a plurality of through vias THV_PB can be arranged between the first stacked structure ST0 and the second stacked structure ST1. The plurality of through vias THV_PB can be arranged at intervals along the D1 direction.

[0104] The through via can be electrically connected to the peripheral circuit TR of the peripheral logic structure PS. The through via can be connected to the bit line BL via the through via connection wiring.

[0105] The through via THV_PB does not penetrate the first stacked structure ST0 and the second stacked structure ST1. In a semiconductor memory device according to some embodiments, the through via THV_PB can pass through the space between the first stacked structure ST0 and the second stacked structure ST1 and be electrically connected to the peripheral circuit TR.

[0106] Figures 8a to 10c are diagrams showing an enlarged view of the Y portion of FIG. 6 in the peripheral region FR.

[0107] FIG. 8a is a drawing specifically showing the peripheral region according to some embodiments, and FIG. 8b is a cross-sectional view taken along B1 - B1' shown in FIG. 8a. For the sake of convenience of explanation, a through structure THV is shown spaced at regular intervals in one row in the D1 direction between the electrode separation regions WLC, but this is only an exemplary explanation and can also be applied to the case where a plurality of rows of vertical through structures THV are arranged between adjacent electrode separation regions WLC.

[0108] Referring to FIGS. 8a and 8b, a semiconductor memory device according to some embodiments may include at least two electrode separation regions WLC in the peripheral region FR and a plurality of through structures THV spaced apart from each other in the D2 direction between adjacent electrode separation regions WLC.

[0109] The peripheral region FR may include an electrode separation region WLC and a plurality of through structures THV. A conductive pattern and a spacer WLCI surrounding both side surfaces of the conductive pattern may be formed in the electrode separation region WLC. The electrode separation region WLC may extend in the D3 direction and the D2 direction and be spaced apart by W3 in the D1 direction. One side of the conductive pattern in the electrode separation region may be coupled to the electrode separation region contact line WLCL via the electrode separation region plug WLC_PG and the electrode separation pad WLC_PD, and the other side may be coupled to the common electrode plate CSP.

[0110] The through structure THV may be arranged in at least one row at a constant interval at a desired and / or preset interval in the D2 direction between adjacent electrode separation regions WLC. The through structure THV may be spaced apart by W4 in the D1 direction in each electrode separation region WLC. One side of the through structure THV may be coupled to the through channel contact line TH_L, and the other side may be coupled to the wiring line 116 in the peripheral logic structure PS. When a first voltage is applied through the through-channel contact line TH_L, each of the electrode pads EP1 to EP7 is joined to a through-structure THV without a through-insulating film THI, so that the first voltage is also applied to the electrode pads EP1 to EP7. According to an exemplary embodiment, the first voltage can be an input power supply voltage (Power, VDD) or a ground voltage GND.

[0111] Since the electrode separation region WLC is electrically isolated from the electrode pads EP1 to EP7 by the spacer WLCI, a second voltage is applied through the electrode separation region contact line WLCL. According to an exemplary embodiment, the second voltage can be a ground voltage or an input power supply voltage.

[0112] The first voltage and the second voltage are different from each other. When the first voltage and the second voltage are applied respectively, a capacitor is formed between the electrode pads EP1 to EP7 and the conductive pattern WLC of the electrode separation region with respect to the spacer WLCI. The capacitance of the capacitor can increase by the number of stacked electrode pads. The capacitor can be coupled to a peripheral circuit through a wiring line 116.

[0113] FIG. 9a is a drawing specifically showing a peripheral region according to some embodiments, and FIG. 9b is a cross-sectional view taken along B2 - B2' shown in FIG. 9a.

[0114] Referring to FIGS. 9a and 9b, a semiconductor memory device according to some embodiments may include at least two electrode separation regions WLC in a peripheral region FR and a plurality of through-structures THV that are spaced apart from each other in the D2 direction between adjacent electrode separation regions WLC.

[0115] The peripheral region FR may include an electrode separation region WLC and a plurality of through structures THV. A conductive pattern may be formed in the electrode separation region WLC. The electrode separation region WLC may extend in the D3 direction and the D2 direction and be arranged at a distance of W3 in the D1 direction. One side of the conductive pattern of the electrode separation region is coupled to the electrode separation region contact line WLCL via the electrode separation region plug WLC_PG and the electrode separation pad WLC_PD, and the other side may be coupled to the common electrode plate CSP.

[0116] The through structures THV may be arranged in at least one row at a constant interval in the D2 direction between adjacent electrode separation regions WLC and be spaced apart by W4 in the D1 direction in each electrode separation region WLC. One side of the through structure THV may be coupled to the through channel contact line TH_L, and the other side may be coupled to the wiring line 116 in the peripheral logic structure PS. Different from the embodiments of FIGS. 8a and 8b, the through structure includes a conductive region THV and a through insulating film THI surrounding the conductive region.

[0117] When a first voltage is applied to the through channel contact line TH_L and a second voltage different from the first voltage is applied to the electrode separation region contact line WLCL, a capacitor is formed between the electrode pads EP1 to EP7 and the conductive pattern WLC of the electrode separation region with respect to the through insulating film THI. The capacitance of the capacitor can increase by the number of stacked electrode pads. The capacitor may be coupled to the peripheral circuit via the wiring line 116.

[0118] FIG. 10a is a drawing specifically showing a peripheral region according to some embodiments, FIG. 10b is a cross-sectional view taken along B3 - B3' shown in FIG. 10a according to some embodiments, and FIG. 10c is a cross-sectional view taken along B3 - B3' shown in FIG. 10a according to some embodiments.

[0119] Referring to FIGS. 10a and 10b, a semiconductor memory device according to some embodiments may include a plurality of through structures THV that are spaced apart from each other in the D1 direction and the D2 direction between adjacent electrode separation regions WLC in the peripheral region FR.

[0120] The plurality of through-structures may include a first through-structure THV1 including a conductive region and a through-insulating film THI surrounding the conductive region, and a second through-structure THV including only the conductive region. The first through-structure THV1 and the second through-structure THV2 may be alternately arranged with each other.

[0121] According to some embodiments, as shown in the drawings, they may be spaced apart in the D1 direction, such as the first through-structure THV1 in the first column, the second through-structure THV2 in the second column, the first through-structure THV1 in the third column, and the second through-structure THV2 in the fourth column, and the first through-structure THV1 and the second through-structure THV2 may be alternately arranged.

[0122] Although not shown in the drawings, according to some embodiments, the first through-structure THV1 and the second through-structure THV2 may also be alternately arranged with multiple rows alternating with each other. According to an exemplary embodiment, two rows of the first through-structure THV1 and two rows of the second through-structure THV2 may be alternately arranged.

[0123] Although not shown in the drawings, according to some embodiments, the first through-structure THV1 and the second through-structure THV2 may each be arranged in at least one column and alternately arranged with each other.

[0124] The electrode separation region WLC may have a wider interval than the interval between adjacent electrode separation regions and the embodiment W3 shown in FIG. 8a or FIG. 9a.

[0125] The conductive pattern of the electrode separation region may be coupled to the electrode separation region contact line WLCL through the electrode separation region plug WLC_PG and the electrode separation pad WLC_PD on one side, and coupled to the common electrode plate CSP on the other side.

[0126] In FIG. 10b, according to some embodiments, the through-vias THV can be arranged in at least one row and at least one column, spaced evenly at a predetermined interval in the D2 direction between adjacent electrode separation regions WLC. The through-vias THV can be arranged spaced apart at a predetermined interval in the D1 direction in each electrode separation region WLC. The first through-via THV1 and the second through-via THV2 can each have one side coupled to the first through-channel contact line TH_L1 and the second through-channel contact line TH_L2, and the other side can be coupled to the wiring line 116 in the peripheral logic structure PS.

[0127] When a first voltage is applied to the first through-channel contact line TH_L1 and a second voltage different from the first voltage is applied to the second through-channel contact line TH_L2, the second voltage is applied to the electrode pads EP1 - EP7 stacked via the second through-channel contact line TH_L2. That is, a capacitor can be formed between the electrode pads EP1 - EP7 and the first through-via respectively based on the through-insulating film THI. The capacitor formed between the electrode pad and the first through-via can be coupled to the peripheral circuit via the wiring line 116.

[0128] In FIG. 10c, according to some embodiments, the through-vias THV can be arranged in at least one row and at least one column, spaced evenly at a desired and / or alternatively a preset interval in the D2 direction between adjacent electrode separation regions WLC. The through-vias THV can be arranged spaced apart at a desired and / or alternatively a preset interval in the D1 direction in each electrode separation region WLC. The first through-via THV1 and the second through-via THV2 can each have one side coupled to the first through-channel contact line TH_L1 and the second through-channel contact line TH_L2, and the other side can be coupled to the common electrode plate CSP.

[0129] When a first voltage is applied to the first through-channel contact line TH_L1 and a second voltage different from the first voltage is applied to the second through-channel contact line TH_L2, the second voltage is applied to the electrode pads EP1 to EP7 stacked via the second through-channel contact line TH_L2. That is, a capacitor can be formed between each of the electrode pads EP1 to EP7 and the first through-structure with reference to the through-insulating film THI. Further, a capacitor can be additionally formed between the common source plate CSP, the interlayer dielectric ILD at the lowermost layer of the stacked structure. The capacitor formed between the electrode pad and the through-structure can be coupled to the peripheral circuit via the common source plate CSP.

[0130] Although not shown in the drawings, a semiconductor memory device according to some embodiments includes a plurality of electrode separation regions WLC in a peripheral region FR. The electrode separation region WLC includes a first electrode separation region including a conductive pattern and a spacer surrounding the sidewall of the conductive pattern, and a second electrode separation region including a conductive pattern. The first electrode separation region and the second electrode separation region can be alternately arranged with each other in the D1 direction.

[0131] According to some embodiments, one side of the first electrode separation region WLC1 is coupled to the first electrode separation region contact line WLCL1 and the other side is coupled to the common source plate CSP. One side of the second electrode separation region WLC2 is coupled to the second electrode separation region contact line WLCL2 and the other side can be coupled to the wiring line 116. When a first voltage and a second voltage different from each other are applied to the first electrode separation region contact line WLCL1 and the second electrode separation region contact line WLCL2, respectively, the second voltage is applied to each electrode pad via the second electrode separation region WLC2. Therefore, a capacitor can be formed between the first electrode separation region WCL1 and each of the electrode pads EP1 to EP7 with reference to the spacer, and can be used as a capacitor in the peripheral circuit via the wiring line 116.

[0132] According to some embodiments, one side of the first electrode separation region WLC1 is coupled to the first electrode separation region contact line WLCL1, and the other side is coupled to the common source plate CSP. One side of the second electrode separation region WLC2 can be coupled to the second electrode separation region contact line WLCL2, and the other side can be coupled to the common source plate CSP. When different first and second voltages are applied to the first electrode separation region contact line WLCL1 and the second electrode separation region contact line WLCL2 respectively, each electrode pad has the second voltage applied thereto via the second electrode separation region WLC2. Therefore, a capacitor can be formed between the first electrode separation region WCL1 and each of the electrode pads EP1 - EP7 with respect to the spacer, and it can be used as a capacitor in the peripheral circuit via the common source plate CSP.

[0133] FIG. 11 is a diagram showing an exemplary embodiment of the peripheral circuit shown in FIG. 1.

[0134] In some embodiments, the capacitor formed between at least a part of the through - structure or at least a part of the electrode separation region and the electrode pattern of the stacked structure can function as at least one capacitor of the peripheral circuit included in the memory device (10 in FIG. 1). For example, at least a part of the through - structure or at least a part of the electrode separation region can be one electrode of the capacitor, and the electrode pattern of the stacked structure can be the other electrode of the capacitor.

[0135] Referring to FIG. 11, an exemplary peripheral circuit 300 is illustrated.

[0136] According to some embodiments, the capacitor generated between at least several through - structures (or at least several electrode separation regions) and the electrode pattern of the stacked structure can provide a capacitor for the peripheral circuit 30 included in the semiconductor memory device 10 of FIG. 1. For example, at least several through - structures (or at least several electrode separation regions) can be configured as the first electrode of the capacitor, and the electrode pattern of the stacked structure can be configured as the second electrode of the capacitor.

[0137] The peripheral circuit 300 may include a column logic 310, an internal voltage generation unit 321, a high voltage generation unit 322, a pre-decoder 330, a temperature sensor 360, a command decoder 340, an address decoder 370, a moving zone control unit 350, a scheduler 380, and a test / measurement circuit 390. The column logic 310, the internal voltage generation unit 321, the high voltage generation unit 322, the pre-decoder 330, the temperature sensor 360, the command decoder 340, the address decoder 370, the moving zone control unit 350, the scheduler 380, and the test / measurement circuit 390 may include a processing circuit such as hardware, a hardware / software combination such as a processor on which software is executed, or a combined unit thereof. For example, more specifically, the processing circuit may be implemented as a CPU (Central Processing Unit), an ALU (Arithmetic Logic Unit), a digital signal processor, a microcomputer, an FPGA (Field Programmable Gate Array), an SoC (System on Chip), a programmable logic unit, a microprocessor, an ASIC (Application-Specific Integrated Circuit), or the like. The column logic 310 can operate according to a control signal, a command (CMD), or an instruction input from an external source (e.g., a host, not shown), can access the semiconductor memory device 10 and / or the peripheral circuit 300 in FIG. 1, can also control the operation of the semiconductor memory device 10 and / or the peripheral circuit 300 in FIG. 1, and can also convert the column logic 310 into a special-purpose column logic 310.

[0138] The components of the peripheral circuit 300 shown in FIG. 11 are merely illustrative, and according to the exemplary embodiments of the present disclosure, the peripheral circuit 300 may further include components not shown, and may also include components different from those shown. Hereinafter, FIG. 11 will be described with reference to FIG. 1.

[0139] The column logic 310 can generate signals for driving the page buffer 35. The pre-decoder 330 can generate signals for determining the timing of signals for driving the row decoder 33. The internal voltage generation unit 321 can generate voltages used inside the memory device 10, such as voltages applied to word lines and bit lines, a reference voltage, and a power supply voltage. The high voltage generation unit 322 can include a charge pump, a regulator, etc., and can generate a high voltage used to program and erase the memory cells of the memory cell array 20. The temperature sensor 360 can sense the temperature of the memory device 10 and output a signal corresponding to the sensed temperature.

[0140] The command decoder 340 can latch and decode the command signal CMD received from outside the memory device 10, and can set the operation mode of the memory device according to the decoded command. The address decoder 370 can latch and decode the address signal ADDR received from outside the memory device 10, and can activate the memory block selected by the decoded address. The moving zone control unit 350 can control the operation of applying various voltages to the strings included in the memory cell array 20, and the scheduler 380 can include a processor or a state machine and can generate a plurality of control signals at appropriate timings according to the mode set by the command. The test / measurement circuit 390 can test and measure the characteristics of the memory device 10 for the purpose of providing information for grasping the characteristics of the memory device 10 during the manufacturing process of the memory device 10. Also, the test / measurement circuit 390 can operate according to the command signal CMD received from outside the memory device 10, and the system including the memory device 10 can use the test / measurement circuit 390 to obtain information regarding the characteristics of the memory device 10 at the initial stage of operation.

[0141] In an exemplary embodiment, the circuit corresponding to the components of the peripheral circuit 300 shown in FIG. 11 may be arranged in the peripheral logic structure PS of FIG. 2 together with the load decoder 33 and the page buffer 35 of FIG. 1.

[0142] FIG. 12 is a diagram showing a memory device including a three-dimensional semiconductor device according to some embodiments.

[0143] Referring to FIG. 12, according to some embodiments, the memory device may be an SSD (Solid State Drive) system.

[0144] The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can transmit and receive signals to and from the host 1100 via a signal connector and can receive power supply via a power connector.

[0145] The SSD 1200 may include an SSD controller 1210, an auxiliary power supply device (1220, for example, a power supply circuit), and a plurality of memory devices 1230, 1240, 1250. The SSD controller 1210 may include a processing circuit such as hardware, a hardware / software combination such as a processor on which software is executed, or a combined unit thereof. For example, more specifically, the processing circuit can be implemented as a CPU (Central Processing Unit), an ALU (Arithmetic Logic Unit), a digital signal processor, a microcomputer, an FPGA (Field Programmable Gate Array), a SoC (System on Chip), a programmable logic unit, a microprocessor, an ASIC (Application-Specific Integrated Circuit), etc. The SSD controller 1210 can operate according to control signals, commands (CMD), or instructions input from an external source (for example, a host, not shown), and can control the overall operation of the SSD 1200. Each of the plurality of memory devices 1230, 1240, 1250 may be a vertical NAND flash memory device and can be realized according to the embodiments described above with reference to FIGS. 1 to 11. Therefore, each of the memory devices 1230, 1240, 1250 can have a high integration degree.

[0146] Those skilled in the art can understand that many variations and modifications can be made to the presented embodiments without substantially departing from the principles of the concept of the present invention. Therefore, the presented embodiments are described only in an inclusive and illustrative sense and not for the purpose of limitation.

Explanation of Reference Numerals

[0147] 10: Semiconductor Memory Device 30: Peripheral Circuit 33: Loader Decoder 35: Page Buffer 37: Control Logic CS: Cell Array Structure PS: Peripheral Logic Structure

Claims

1. a substrate; a peripheral logic structure on the substrate including a plurality of peripheral circuits; a horizontal semiconductor layer on the peripheral logic structure; a memory cell array region on the horizontal semiconductor layer and at least one capacitance region spaced apart from the memory cell array region; a plurality of stacked structures in which a mold layer and electrode pads are alternately stacked in a first direction on the capacitance region; a plurality of electrode separation regions extending in the first direction and a second direction different from the first direction, separating the plurality of stacked structures and coupling to the horizontal semiconductor layer; a through-channel contact; a plurality of through-structures that are the peripheral logic structure; a capacitor formed by each of the electrode pads and at least one of the plurality of electrode separation regions or at least one of the plurality of through-structures in the capacitance region, and including: the plurality of through-structures penetrate the plurality of stacked structures in the first direction, and one side of each through-structure is coupled to a corresponding side of the through-channel contact; a three-dimensional semiconductor memory device in which the capacitor formed in the capacitance region is electrically connected to at least one of the plurality of peripheral circuits in the memory cell array region.

2. a substrate; a peripheral logic structure on the substrate including a plurality of peripheral circuits; a horizontal semiconductor layer on the peripheral logic structure; a plurality of stacked structures in which a mold layer and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layer; a plurality of electrode separation regions extending in the first direction and a second direction different from the first direction, separating the plurality of stacked structures and coupling to the horizontal semiconductor layer; a through-channel contact; a plurality of through-structures that are the peripheral logic structure; a capacitor formed by each of the electrode pads and at least one of the plurality of electrode separation regions or at least one of the plurality of through-structures, and including: the plurality of through-structures penetrate the plurality of stacked structures in the first direction, and one side of each through-structure is coupled to a corresponding side of the through-channel contact; each of the plurality of electrode separation regions, includes a conductive pattern and a spacer surrounding a side surface of the conductive pattern; each of the plurality of through-structures, A three-dimensional semiconductor memory device including a conductive region that is coupled to a corresponding one of the electrode pads of the plurality of stacked structures. **Claim 3** A substrate, a peripheral logic structure on the substrate including a plurality of peripheral circuits, a horizontal semiconductor layer on the peripheral logic structure, a plurality of stacked structures in which a mold layer and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layer, a plurality of electrode separation regions extending in the first direction and a second direction different from the first direction, separating the plurality of stacked structures and coupling to the horizontal semiconductor layer, through-channel contacts, a plurality of through-structures that are the peripheral logic structure, a capacitor formed by each of the electrode pads and at least one of the plurality of electrode separation regions or at least one of the plurality of through-structures, and the plurality of through-structures penetrate the plurality of stacked structures in the first direction, and one side of each through-structure is coupled to a corresponding side of the through-channel contact, each of the plurality of electrode separation regions, includes a conductive pattern coupled to a corresponding one of the electrode pads of the plurality of stacked structures, each of the plurality of through-structures, A three-dimensional semiconductor memory device including a conductive region and a through-insulating film surrounding a side surface of the conductive region. **Claim 4** A substrate, a peripheral logic structure on the substrate including a plurality of peripheral circuits, a horizontal semiconductor layer on the peripheral logic structure, a plurality of stacked structures in which a mold layer and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layer, a plurality of electrode separation regions extending in the first direction and a second direction different from the first direction, separating the plurality of stacked structures and coupling to the horizontal semiconductor layer, through-channel contacts, a plurality of through-structures that are the peripheral logic structure, a capacitor formed by each of the electrode pads and at least one of the plurality of electrode separation regions or at least one of the plurality of through-structures, and the plurality of through-structures penetrate the plurality of stacked structures in the first direction, and one side of each through-structure is coupled to a corresponding side of the through-channel contact, the plurality of electrode separation regions, include a first electrode separation region and a second electrode separation region, The first electrode separation region includes a conductive pattern and a spacer surrounding a side surface of the conductive pattern, and each electrode pad of a corresponding one of the plurality of stacked structures is insulated from the conductive pattern. The second electrode separation region includes a conductive pattern and is coupled to each electrode pad of a corresponding one of the plurality of stacked structures. Each of the through structures includes a conductive region coupled to each electrode pad of a corresponding one of the plurality of stacked structures, a three-dimensional semiconductor memory device. **Claim 5** A substrate, A peripheral logic structure on the substrate including a plurality of peripheral circuits, A horizontal semiconductor layer on the peripheral logic structure, A plurality of stacked structures in which a mold layer and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layer, A plurality of electrode separation regions extending in the first direction and a second direction different from the first direction, separating the plurality of stacked structures and coupled to the horizontal semiconductor layer, A through-channel contact, A plurality of through structures that are the peripheral logic structure, A capacitor formed by each of the electrode pads and at least one of the plurality of electrode separation regions or at least one of the plurality of through structures, and includes, The plurality of through structures penetrate the plurality of stacked structures in the first direction, and one side of each through structure is coupled to a corresponding side of the through-channel contact. Each of the plurality of through structures, Includes a first through structure and a second through structure, The first through structure, Includes a first conductive region and a through insulating film surrounding a side surface of the first conductive region, The second through structure includes a second conductive region and is coupled to each of the stacked structures, The first through structure and the second through structure are alternately arranged with each other between at least two of the plurality of electrode separation regions, a three-dimensional semiconductor memory device. **Claim 6** Each of the plurality of through structures, The other side is coupled to the horizontal semiconductor layer, the three-dimensional semiconductor memory device according to claim 1. **Claim 7** The peripheral logic structure includes wiring lines, Each of the plurality of through structures, The other side is coupled to any one of the wiring lines in the peripheral logic structure, the three-dimensional semiconductor memory device according to claim 1. **Claim 8** The plurality of through structures, Includes a third through structure and a fourth through structure, One side of the third through structure is coupled to the horizontal semiconductor layer. One side of the fourth through-structure is coupled to any one of the wiring lines in the peripheral logic structure, The three-dimensional semiconductor memory device according to claim 1, wherein the third through-structure and the fourth through-structure are alternately arranged with each other.

9. The intervals between the plurality of electrode separation regions include a first electrode separation region and a second electrode separation region, The interval between two adjacent first electrode separation regions among the first electrode separation regions is equal to or greater than the interval between two adjacent second electrode separation regions among the second electrode separation regions, The three-dimensional semiconductor memory device according to claim 1, wherein the plurality of through-structures include a structure having a through-structure between two adjacent first electrode separation regions and a structure having no through-structure between two adjacent second electrode separation regions.

10. The three-dimensional semiconductor memory device according to claim 9, wherein the interval between the first electrode separation regions is three times or more greater than the interval between the second electrode separation regions.

11. A horizontal semiconductor layer, A plurality of stacked structures on the horizontal semiconductor layer, wherein the plurality of stacked structures are alternately stacked with a mold layer and an electrode pad in a first direction, the plurality of stacked structures include through-channel contacts, the plurality of stacked structures include a memory cell array region and a capacitance region spaced apart from the memory cell array region, and the plurality of stacked structures are stacked in the capacitance region with the same width in a second direction and a third direction different from the first direction, a plurality of stacked structures, A plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures in the capacitance region, A three-dimensional semiconductor memory device including a plurality of through-structures in the capacitance region that penetrate the plurality of stacked structures in the capacitance region in a first direction, extend between at least two adjacent electrode separation regions, and one side of which is coupled to a corresponding one of the through-channel contacts.

12. The plurality of through-structures, The three-dimensional semiconductor memory device according to claim 11, wherein the other side is coupled to the horizontal semiconductor layer or a wiring line under the horizontal semiconductor layer.

13. A horizontal semiconductor layer, A plurality of stacked structures on the horizontal semiconductor layer, wherein the plurality of stacked structures have a mold layer and electrode pads alternately stacked in a first direction, the plurality of stacked structures include through-channel contacts, the plurality of stacked structures include a memory cell array region and a peripheral region, and in the peripheral region, the plurality of stacked structures are stacked with the same width in a second direction and a third direction different from the first direction, a plurality of stacked structures; A plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures; A plurality of through-structures that penetrate the stacked structures in a first direction in the peripheral region, extend between at least two adjacent ones of the electrode separation regions, and have one side coupled to a corresponding one of the through-channel contacts; Each of the plurality of electrode separation regions; Includes a conductive pattern penetrating the plurality of stacked structures in a first direction and a spacer surrounding a side surface of the conductive pattern; Each of the plurality of through-structures includes a conductive region that couples to a corresponding one of the electrode pads in one of the plurality of stacked structures, a three-dimensional semiconductor memory device.

14. A horizontal semiconductor layer; A plurality of stacked structures on the horizontal semiconductor layer, wherein the plurality of stacked structures have a mold layer and electrode pads alternately stacked in a first direction, the plurality of stacked structures include through-channel contacts, the plurality of stacked structures include a memory cell array region and a peripheral region, and in the peripheral region, the plurality of stacked structures are stacked with the same width in a second direction and a third direction different from the first direction, a plurality of stacked structures; A plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures; A plurality of through-structures that penetrate the stacked structures in a first direction in the peripheral region, extend between at least two adjacent ones of the electrode separation regions, and have one side coupled to a corresponding one of the through-channel contacts; Each of the plurality of electrode separation regions; Includes a conductive pattern that couples to each of the electrode pads while penetrating the plurality of stacked structures in a first direction; Each of the plurality of through-structures includes a conductive region and a through-insulating film surrounding a side surface of the conductive region and is insulated from each of the electrode pads, a three-dimensional semiconductor memory device.

15. A horizontal semiconductor layer; A plurality of stacked structures on the horizontal semiconductor layer, wherein the plurality of stacked structures have a mold layer and electrode pads alternately stacked in a first direction, the plurality of stacked structures include through-channel contacts, the plurality of stacked structures include a memory cell array region and a peripheral region, and in the peripheral region, the plurality of stacked structures are stacked in a second direction and a third direction different from the first direction with the same width. A plurality of stacked structures; A plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures; A plurality of through structures that penetrate the stacked structures in a first direction in the peripheral region, extend between at least two adjacent ones of the electrode separation regions, and are coupled to a corresponding one of the through-channel contacts on one side; The plurality of electrode separation regions include: A first electrode separation region including a conductive pattern and a spacer surrounding the side surface of the conductive pattern and insulated from each of the stacked structures; A second electrode separation region including a conductive pattern and coupled to each of the electrode pads; A three-dimensional semiconductor memory device in which the first electrode separation region and the second electrode separation region are alternately arranged in a third direction in the peripheral region.

16. A horizontal semiconductor layer; A plurality of stacked structures on the horizontal semiconductor layer, wherein the plurality of stacked structures have a mold layer and electrode pads alternately stacked in a first direction, the plurality of stacked structures include through-channel contacts, the plurality of stacked structures include a memory cell array region and a peripheral region, and in the peripheral region, the plurality of stacked structures are stacked in a second direction and a third direction different from the first direction with the same width. A plurality of stacked structures; A plurality of electrode separation regions extending in a second direction and spaced apart from each other in a third direction to separate the plurality of stacked structures; A plurality of through structures that penetrate the stacked structures in a first direction in the peripheral region, extend between at least two adjacent ones of the electrode separation regions, and are coupled to a corresponding one of the through-channel contacts on one side; Each of the plurality of through structures includes: A first through structure including a conductive region and a through insulating film surrounding the side surface of the conductive region and insulated from each of the electrode pads, and a second through structure including a conductive region and connected to each of the stacked structures; A three-dimensional semiconductor memory device in which the first through-hole structure and the second through-hole structure are alternately arranged with each other between at least two of the electrode separation regions.

17. The plurality of through-hole structures include a peripheral logic structure including wiring lines, a first through-hole structure having the other side coupled to the horizontal semiconductor layer, and a second through-hole structure having the other side coupled to any one of the wiring lines in the peripheral logic structure, and The three-dimensional semiconductor memory device according to claim 11, wherein the first through-hole structure and the second through-hole structure are alternately arranged with each other.

18. Each of the plurality of through-hole structures is arranged to penetrate through the mold layer that extends in a second direction between the electrode separation regions adjacent to each other, and the electrode pads are arranged to extend in the second direction between each of the electrode separation regions and the mold layer. The three-dimensional semiconductor memory device according to claim 11.

19. On a horizontal semiconductor layer, at least one capacitance region spaced apart from the memory cell region and having the mold layer and the electrode pads alternately arranged, at least one stacked structure including the capacitance region, a plurality of electrode separation regions each extending in a word line direction and a bit line direction in the capacitance region and spaced apart from each other, a mold region arranged between two adjacent ones of the plurality of electrode separation regions, and a plurality of through-hole structures each penetrating the mold region vertically, and The electrode pads of the capacitance region each form a capacitor with at least one of the plurality of through-hole structures or at least one of the plurality of electrode separation regions. A three-dimensional semiconductor memory device.

20. The capacitance region is the three-dimensional semiconductor memory device according to claim 19, wherein the electrode pads and the mold layer are stacked on the horizontal semiconductor layer with the same length in the word line direction and the bit line direction, respectively.

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