Semiconductor device and electronic system including the same

Abstract

To provide a semiconductor device having improved degrees of integration and reliability and an electronic system including the semiconductor device.SOLUTION: A semiconductor device includes: an understructure including a peripheral circuit; a lamination structure 29 that extends from a memory cell array region to a stair region on the understructure and includes a plurality of insulator lamination regions 29I arranged in a first direction away from the memory cell array region in a gate lamination region 29G and the stair region; a capping insulation structure on the lamination structure; and isolation structures 71m, 71s that penetrate the gate lamination region and extend in the capping insulation structure. The lamination structure includes interlayer insulation layers and horizontal layers that are alternately and repeatedly laminated in the memory cell array region and extend in the stair region. The horizontal layers include a gate horizontal layer and an insulation horizontal layer. The gate lamination region includes the gate horizontal layer. Each insulator lamination region includes the insulation horizontal layer. In the stair region, the lamination structure includes a first stair region IS1, a coupled stair region CS, and a second stair region IS2.SELECTED DRAWING: Figure 2b

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic system including the same.

Background Art

[0002] In an electronic system that requires data storage, there is a need for a semiconductor device capable of storing a large amount of data. For this reason, measures to increase the data storage capacity of semiconductor devices have been studied. For example, as one method of increasing the data storage capacity of a semiconductor device, a semiconductor device including three-dimensionally arranged memory cells has been proposed instead of two-dimensionally arranged memory cells.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor device with improved integration and reliability. Another object of the present invention is to provide an electronic system including the semiconductor device.

Means for Solving the Problems

[0005] A semiconductor device according to one aspect of the present invention made to achieve the above object includes a lower structure including a peripheral circuit and a peripheral pad electrically connected to the peripheral circuit, and a memory cell array region on the lower structure extending from the memory cell array region to a stepped region adjacent to the memory cell array region, and a stacked structure including a plurality of insulator stacked regions having a gate stacked region and side surfaces surrounded by the gate stacked region, a capping insulating structure on the stacked structure, a memory vertical structure penetrating the gate stacked region of the stacked structure within the memory cell array region, a separation structure penetrating the gate stacked region of the stacked structure and extending into the capping insulating structure, and a peripheral contact structure penetrating at least one of the insulator stacked regions of the stacked structure and extending into the capping insulating structure. The stacked structure includes an interlayer insulating layer and a horizontal layer alternately and repeatedly stacked within the memory cell array region and formed in a stepped shape within the stepped region while extending into the stepped region within the memory cell array region. The horizontal layer includes a gate horizontal layer and an insulating horizontal layer. The gate stacked region includes the gate horizontal layer. Each of the insulator stacked regions includes the insulating horizontal layer. Within the stepped region, the stacked structure includes a first stepped region, a connecting stepped region, and a second stepped region arranged in order in a first direction away from the memory cell array region. Each of the first and second stepped regions is stepped with a first height difference in the first direction and becomes lower. The upper surface of the connecting stepped region has a flat shape in the first direction or a shape having a height difference smaller than the first height difference in the first direction. The plurality of insulator stacked regions are separated in the first direction within the connecting stepped region. The separation structure includes a pair of main separation structures parallel to each other and a dummy separation structure between the pair of main separation structures. The plurality of insulator stacked regions are arranged between the pair of main separation structures. The dummy separation structure penetrates the connecting stepped region of the stacked structure and is separated from the plurality of insulator stacked regions.

[0006] A semiconductor device according to another aspect of the present invention made to achieve the above object includes a lower structure including a peripheral circuit, and a stacked structure that extends from a memory cell array region to a staircase region adjacent to the memory cell array region on the lower structure, and includes a plurality of insulator stacked regions arranged in a first direction away from the memory cell array region within a gate stack region and the staircase region. The semiconductor device also includes a capping insulating structure on the stacked structure, and a separation structure that penetrates the gate stack region of the stacked structure and extends into the capping insulating structure. The stacked structure includes an interlayer insulating layer and a horizontal layer that are alternately and repeatedly stacked within the memory cell array region, and are formed in a staircase shape within the staircase region while extending into the staircase region within the memory cell array region. The horizontal layer includes a gate horizontal layer and an insulating horizontal layer. The gate stack region includes the gate horizontal layer, each of the insulator stacked regions includes the insulating horizontal layer, the stacked structure within the staircase region includes a first staircase region, one or more connecting staircase regions, and a second staircase region. Each of the first and second staircase regions has a staircase shape that decreases in the first direction with a first height difference. Each of the one or more connecting staircase regions has a flat shape in the first direction or a shape having a height difference smaller than the first height difference in the first direction. A plurality of insulator stacked regions that are sequentially arranged while being separated from each other in the first direction among the plurality of insulator stacked regions are arranged within any one of the one or more connecting staircase regions.

[0007] An electronic system according to one aspect of the present invention made to achieve the above object includes a main board, a semiconductor device on the main board, a connection structure electrically connecting the semiconductor device and the main board, and a controller electrically connected to the semiconductor device on the main board. The semiconductor device includes a lower structure including a peripheral circuit, a stacked structure extending from a memory cell array region to a stepped region adjacent to the memory cell array region on the lower structure, and including a plurality of insulator stacked regions arranged in a first direction away from the memory cell array region in a gate stacked region and in the stepped region, a capping insulating structure on the stacked structure, and a separation structure penetrating the gate stacked region of the stacked structure and extending into the capping insulating structure. The stacked structure includes an interlayer insulating layer and a horizontal layer alternately and repeatedly stacked in the memory cell array region, formed in a stepped shape in the stepped region while extending into the stepped region in the memory cell array region, the horizontal layer includes a gate horizontal layer and an insulating horizontal layer, the gate stacked region includes the gate horizontal layer, each of the insulator stacked regions includes the insulating horizontal layer, the stacked structure in the stepped region includes a first stepped region, one or more connected stepped regions, and a second stepped region, each of the first and second stepped regions is stepped down with a first height difference in the first direction, each of the one or more connected stepped regions is flat in the first direction or has a shape with a height difference smaller than the first height difference in the first direction, and a plurality of insulator stacked regions arranged in order while being separated from each other in the first direction among the plurality of insulator stacked regions are arranged in any one of the connected stepped regions among the one or more connected stepped regions.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide a device with improved integration density and reliability.

[0009] The various and significant advantages and effects of the present invention are not limited to the above-described content, and are more easily understood in the process of explaining specific embodiments of the present invention.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, specific examples of embodiments for carrying out the present invention will be described with reference to the drawings.

[0012] First, referring to FIGS. 1 to 5, a semiconductor device according to an embodiment of the present invention will be described. FIG. 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. FIG. 2a is a partial enlarged plan view of the portion indicated as "A" in FIG. 1, and FIG. 2b is a partial enlarged plan view of the portion indicated as "B" in FIG. 1. FIG. 3a is a cross-sectional view schematically showing a region cut along the line I-I' of FIGS. 1, 2a, and 2b, FIG. 3b is a cross-sectional view schematically showing a region cut along the line II-II' of FIGS. 1, 2a, and 2b, and FIG. 3c is a cross-sectional view schematically showing a region cut along the lines III-III' and IV-IV' of FIG. 2b. FIG. 4 is a partial enlarged view of the portion indicated as "C" in FIG. 3a, and FIG. 5 is a partial enlarged view of the portions indicated as "D1" and "D2" in FIG. 3b.

[0013] Referring to FIGS. 1 to 5, a semiconductor device 1 according to an embodiment of the present invention includes a lower structure 3, a stacked structure 29 extending from a memory cell array region MCA to a staircase region SA on the lower structure 3, a capping insulating structure 82 on the stacked structure 29, a plurality of vertical structures (47m, 47b, 47d1, 47d2) penetrating the stacked structure 29 and extending into the capping insulating structure 82, and separation structures (71m, 71s) penetrating the stacked structure 29 and extending into the capping insulating structure 82.

[0014] The stacked structure 29 includes a gate stack region 29G and a plurality of insulator stack regions 29I.

[0015] The semiconductor device 1 according to an embodiment of the present invention further includes a dam structure 65 adjacent to the plurality of insulator stack regions 29I.

[0016] The lower structure 3 includes a substrate 5, peripheral elements 7 on the substrate 5, peripheral wirings 9 electrically connected to the peripheral elements 7, a plurality of peripheral pads (11a, 11b) electrically connected to the peripheral wirings 9, a lower insulating layer 13 covering the peripheral elements 7, peripheral wirings 9, and the plurality of peripheral pads (11a, 11b) on the substrate 5, a pattern structure 15 having an opening 15a on the lower insulating layer 13, an intermediate insulating layer 26a covering the outer surface of the pattern structure 15, and a gap-fill insulating layer 26b filling the opening 15a. The substrate 5 is a semiconductor substrate. The peripheral elements 7 include transistors having surrounding source / drains 7a and peripheral gates 7b. For example, the peripheral gate 7b is disposed on an active region 6a defined by an element isolation layer 6s on the substrate 5, and the peripheral source / drains 7a are disposed within the active region 6a on both sides of the peripheral gate 7b.

[0017] The pattern structure 15 includes a lower pattern layer 18, a first intermediate pattern layer 20 and a second intermediate pattern layer 21 spaced apart from each other on the lower pattern layer 18, and an upper pattern layer 23 covering the first and second intermediate pattern layers (20, 21) on the lower pattern layer 18.

[0018] In one example, the upper pattern layer 23 contacts the lower pattern layer 18 between the first and second intermediate pattern layers (20, 21). The upper pattern layer 23 penetrates the first intermediate pattern layer 20, divides the first intermediate pattern layer 20 into a plurality of parts, and contacts the lower pattern layer 18. The portion where the upper pattern layer 23 contacts the lower pattern layer 18 is referred to as a support base portion (23s in FIG. 2a).

[0019] In one example, each of the lower pattern layer 18, the upper pattern layer 23, and the second intermediate pattern layer 21 includes a polysilicon layer. For example, in one example, the lower pattern layer 18, the upper pattern layer 23, and the second intermediate pattern layer 21 are polysilicon layers having an N-type conductivity type. The first intermediate pattern layer 20 includes a first layer (20a in FIG. 5), a second layer (20b in FIG. 5), and a third layer (20c in FIG. 5) stacked in sequence.

[0020] The stacked structure 29 extends from the memory cell array region MCA to the stepped region SA adjacent to the memory cell array region MCA on the lower structure 3.

[0021] The stacked structure 29 includes an interlayer insulating layer and a horizontal layer that are alternately and repeatedly stacked. The stacked structure 29 includes a lower stacked structure 29L and an upper stacked structure 29U on the lower stacked structure 29L. For example, the lower stacked structure 29L includes a lower interlayer insulating layer 32 and a lower horizontal layer 33 that are alternately and repeatedly stacked, and the upper stacked structure 29U includes an upper interlayer insulating layer 39 and an upper horizontal layer 41 that are alternately and repeatedly stacked.

[0022] The stacked structure 29 is formed in a stepped shape within the stepped region SA. For example, within the stepped region SA, the stacked structure 29 includes an upper stepped region US, an intermediate stepped region IS, and a lower stepped region LS that are arranged in order in a first direction X away from the memory cell array region MCA.

[0023] In the stacked structure 29, the upper stepped region US includes a first upper stepped region US1 and a second upper stepped region US2 that are arranged in order in the first direction X, and the lower stepped region LS includes a first lower stepped region LS1 and a second lower stepped region LS2 that are arranged in order in the first direction X. In the stacked structure 29, the intermediate stepped region IS includes a first intermediate stepped region IS1, a connecting stepped region CS, and a second intermediate stepped region IS2 that are arranged in order in the first direction X.

[0024] In one example, in the stacked structure 29, each of the first and second intermediate stepped regions (IS1, IS2) becomes lower with a first height difference in the first direction X (i.e., along the first direction X).

[0025] In one example, in the stacked structure 29, the connecting stepped region CS has a flat shape in the first direction X or a shape having a height difference smaller than the first height difference in the first direction X.

[0026] In one example, in the stacked structure 29, the first and second intermediate staircase regions (IS1, IS2) and the connecting staircase region CS are lowered or raised with a second height difference smaller than the first height difference in a second direction Y perpendicular to the first direction X. The first direction X and the second direction Y are parallel to the upper surface of the substrate 5.

[0027] In one example, in the stacked structure 29, the first upper staircase region US1 and the second lower staircase region LS2 are stepped down with a first height difference in the first direction X and have the same height as each other in the second direction Y. The second upper staircase region US2 in the stacked structure 29 is stepped up with the first height difference, and the first lower staircase region LS1 is stepped down with the first height difference.

[0028] In one example, the stacked structure 29 includes a gate stacked region 29G and a plurality of insulator stacked regions 29I. The plurality of insulator stacked regions 29I are disposed in a part of the stacked structure 29 of the connecting staircase region CS, and the remaining part of the stacked structure 29 is the gate stacked region 29G.

[0029] The lower horizontal layer 33 includes a lower gate horizontal layer 33G and a lower insulating horizontal layer 33I, and the upper horizontal layer 41 includes an upper gate horizontal layer 41G and an upper insulating horizontal layer 41I. In one example, each of the lower gate horizontal layer 33G and the upper gate horizontal layer 41G includes a first gate layer 29a and a second gate layer 29b. The first gate layer 29a covers the upper and lower surfaces of the second gate layer 29b and covers a part of the side surfaces of the second gate layer 29b. In one example, the first gate layer 29a is formed of a high dielectric such as aluminum oxide, and the second gate layer 29b is formed of a conductive material.

[0030] The lower gate horizontal layer 33G and the upper gate horizontal layer 41G are disposed within the gate stacking region 29G of the stacked structure 29, and the lower insulating horizontal layer 33I and the upper insulating horizontal layer 41I are disposed within the insulator stacking region 29I of the stacked structure 29. Accordingly, in the stacked structure 29, the gate stacking region 29G includes the interlayer insulating layers (32, 39) and the gate horizontal layers (33G, 41G) that are alternately and repeatedly stacked, and each of the insulator stacking regions 29I includes the interlayer insulating layers (32, 39) and the insulating horizontal layers (33I, 41I) that are alternately and repeatedly stacked.

[0031] The capping insulating structure 82 includes a first capping insulating layer 35 that covers the lower stacked structure 29L, a second capping insulating layer 44 that covers the upper stacked structure 29U, and third, fourth, and fifth capping insulating layers (60, 75, 81) that are sequentially stacked on the second capping insulating layer 44. The capping insulating structure 82 includes silicon oxide.

[0032] In one example, a portion 35a of the first capping insulating layer 35 that overlaps the upper stacked structure 29U is referred to as an interlayer insulating layer.

[0033] In another example, the lower stacked structure 29L and the first capping insulating layer 35 can be omitted, and the stacked structure 29 includes the upper stacked structure 29U.

[0034] In one embodiment, a buffer region BA is disposed between the memory cell array region MCA and the staircase region SA. The buffer region BA is understood to be a region included in the staircase region SA.

[0035] The plurality of vertical structures (47m, 47b, 47d1, 47d2) include a memory vertical structure 47m that penetrates the stacked structure 29 within the memory cell array region MCA, a first dummy vertical structure 47d1 that penetrates the stacked structure 29 within the staircase region SA, a second dummy vertical structure 47d2 that penetrates the stacked structure 29 within the memory cell array region MCA and is electrically isolated, and a buffer vertical structure 47b that penetrates the stacked structure 29 within the buffer region BA.

[0036] Each of the plurality of vertical structures (47m, 47b, 47d1, 47d2) includes a core insulation pattern (55 in FIG. 4), a channel layer (53 in FIG. 4) covering the side and bottom surfaces of the core insulation pattern (55 in FIG. 4), and an information storage structure (49 in FIG. 4) covering the outer side and bottom surfaces of the channel layer (53 in FIG. 4). The channel layer 53 is formed of a semiconductor material layer. For example, the channel layer 53 is formed of a silicon layer. The core insulation pattern 55 includes silicon oxide or a low-k dielectric. The core insulation pattern 55 includes silicon oxide with voids formed therein or a low-k dielectric with voids formed therein.

[0037] The information storage structure 49 includes a first dielectric layer 51a, a second dielectric layer 51c, and an information storage layer 51b between the first dielectric layer 51a and the second dielectric layer 51c. The second dielectric layer 51c contacts the channel layer 53. The first dielectric layer 51a includes silicon oxide or silicon oxide doped with impurities. The second dielectric layer 51c includes at least one of silicon oxide and a high dielectric. The information storage layer 51b includes a region for storing information in a semiconductor device such as a NAND flash memory element. For example, the information storage layer 51b includes a material for trapping charge, such as silicon nitride.

[0038] The information storage layer 51b of the memory vertical structure 47m among the plurality of vertical structures (47m, 47b, 47d1, 47d2) traps charge to store information, and the information storage layers 51b of the other vertical structures (47b, 47d1, 47d2) are dummies that do not store information.

[0039] The upper pattern layer 23 of the pattern structure 15 penetrates the information storage structure 49 of each memory vertical structure 47m, divides the information storage structure 49 into a lower information storage structure 49L and an upper information storage structure 49U, and contacts the channel layer 53.

[0040] The isolation structures (71m, 71s) penetrate the stacked structure 29 in the vertical direction Z and extend into the capping insulation structure 82. For example, the isolation structures (71m, 71s) penetrate the third capping insulation layer 60 and extend downward to penetrate the stacked structure 29. The isolation structures (71m, 71s) include a main isolation structure 71m and auxiliary isolation structures 71s. The isolation structures (71m, 71s) are formed of the same material as each other. For example, the isolation structures (71m, 71s) are formed of an insulating material such as silicon oxide. In another example, each of the isolation structures (71m, 71s) includes a conductive pattern and an insulating pattern on the side surface of the conductive pattern. The isolation structures (71m, 71s) have substantially the same cross-sectional structure in the second direction Y.

[0041] The main isolation structure 71m penetrates the stacked structure 29 of the memory cell array region MCA, the buffer region BA, and the staircase region SA and extends into the capping insulation structure 82. The main isolation structure 71m is linear and extends in the first direction X and is adjacent in the second direction Y.

[0042] A plurality of auxiliary isolation structures 71s penetrate a part of the stacked structure 29 between a pair of main isolation structures that are adjacent to each other and parallel to each other among the main isolation structures 71m and extend into the capping insulation structure 82.

[0043] The plurality of auxiliary isolation structures 71s include a first auxiliary isolation structure 71s1 that penetrates the first intermediate staircase region IS1 of the stacked structure 29, a second auxiliary isolation structure 71s2 that penetrates the second intermediate staircase region IS2 of the stacked structure 29, and dummy isolation structures (71s3a1, 71s3a2, 71s3a3) that penetrate the connection staircase region CS of the stacked structure 29 between the first auxiliary isolation structure 71s1 and the second auxiliary isolation structure 71s2.

[0044] The dummy isolation structures (71s3a1, 71s3a2, 71s3a3) include a first dummy isolation structure 71s3a1 that is parallel to each other, a second dummy isolation structure 71s3a2 that is parallel to each other, and a third dummy isolation structure 71s3a3 that is parallel to each other.

[0045] The insulating laminated region 29I includes a first insulating laminated region 29Ia1 and a second insulating laminated region 29Ia2 that are separated from each other in the first direction X.

[0046] The insulating laminated regions 29I each overlap the gap-fill insulating layer 26b. The insulating laminated regions 29I have a width larger than that of the gap-fill insulating layer 26b.

[0047] The first dummy separation structure 71s3a1 is disposed between the first auxiliary separation structure 71s1 and the first insulating laminated region 29Ia1, the second dummy separation structure 71s3a2 is disposed between the second auxiliary separation structure 71s2 and the second insulating laminated region 29Ia2, and the third dummy separation structure 71s3a3 is disposed between the first and second insulating laminated regions (29Ia1, 29Ia2).

[0048] The first auxiliary separation structure 71s1 and the first dummy separation structure 71s3a1 have end portions facing each other. The second auxiliary separation structure 71s2 and the second dummy separation structure 71s3a2 have end portions facing each other. The first auxiliary separation structure 71s1 extends from the first intermediate staircase region IS1 into the connection staircase region CS. The second auxiliary separation structure 71s2 extends from the second intermediate staircase region IS2 into the connection staircase region CS. Accordingly, the end portion of the first auxiliary separation structure 71s1 facing the end portion of the first dummy separation structure 71s3a1 is disposed in the connection staircase region CS, and the end portion of the second auxiliary separation structure 71s2 facing the end portion of the second dummy separation structure 71s3a2 is disposed in the connection staircase region CS.

[0049] The dam structure 65 includes a first dam structure 65a1 that surrounds the side surface of the first insulating laminated region 29Ia1 and extends into the capping insulating structure 82, and a second dam structure 65a2 that surrounds the side surface of the second insulating laminated region 29Ia2 and extends into the capping insulating structure 82. The dam structure 65 is interposed between the insulating laminated region 29I and the gate laminated region 29G.

[0050] The dam structure 65 and the isolation structures (71m, 71s) have upper surfaces that are arranged at the same height as each other. The dam structure 65 contains a material different from that of the isolation structures (71m, 71s). For example, the isolation structures (71m, 71s) are formed of silicon oxide, and the dam structure 65 contains at least one of silicon nitride and polysilicon.

[0051] In one example, each of the dam structures 65 includes a first material layer 64a, a second material layer 64b, and a third material pattern 64c. For example, the second material layer 64b covers the side and bottom surfaces of the third material pattern 64c, and the first material layer 64a covers the outer and bottom surfaces of the second material layer 64b. In one example, the first material layer 64a is silicon oxide, the second material layer 64b is silicon nitride, and the third material pattern 64c contains polysilicon.

[0052] In contact with the gate pad regions (33p, 41p) of the gate horizontal layers (29G, 41G), electrically connected to the gate horizontal layers (29G, 41G), and extending into the capping insulating structure 82, gate contact structures 86g are arranged. Each of the gate contact structures 86g includes a lower gate contact plug 78g and an upper gate contact plug 84g on the lower gate contact plug 78g.

[0053] Peripheral contact structures 86p are arranged that penetrate the capping structure 82 and the insulator volume layer region 29I in sequence. The peripheral contact structure 86p overlaps the first peripheral pad 11a. The peripheral contact structure 86p extends downward from the portion penetrating the insulator volume layer region 29I, penetrates the gap fill insulating layer 26b, and is electrically connected to the first peripheral pad 11a. Each of the peripheral contact structures 86p includes a lower peripheral contact plug 78p and an upper peripheral contact plug 84p on the lower peripheral contact plug 78p.

[0054] An input / output contact structure 86i penetrates through the capping structure 82 and the intermediate insulating layer 35 in sequence, extends downward, and is disposed to be electrically connected to the second peripheral pad 11b. Each of the input / output contact structures 86i includes a lower input / output contact plug 78i and an upper input / output contact plug 84i on the lower input / output contact plug 78i.

[0055] A bit line contact plug 86b contacts the memory vertical structure 47m on the memory vertical structure 47m, extends upward, and penetrates through the capping structure 82.

[0056] A bit line 91b electrically connected to the bit line contact plug 86b on the capping insulating structure 82, a gate connection wiring 91g electrically connecting the peripheral contact structure 86p and the gate contact structure 86g, and an input / output connection wiring 91i electrically connected to the input / output contact structure 86i are disposed.

[0057] An upper insulating layer 89 covering the bit line 91b, the gate connection wiring 91g, and the input / output connection wiring 91i is disposed on the capping insulating structure 82. An input / output plug 95 penetrating through the upper insulating layer 89 and electrically connected to the input / output connection wiring 91i is disposed.

[0058] An input / output pad 97 is disposed on the upper insulating layer 89. A passivation layer 99 having an opening 99a exposing at least a part of the input / output pad 97 is disposed on the upper insulating layer 89. The upper insulating layer 89 includes at least one of silicon oxide and silicon nitride, and the passivation layer 99 is formed of polyimide or a polyimide-based material.

[0059] In one embodiment, each of the first dummy isolation structures 71s3a1 at the first height level has a first length in the first direction X, each of the second dummy isolation structures 71s3a2 has a second length in the first direction X, each of the third dummy isolation structures 71s3a3 has a third length in the first direction X, the distance between the outer surfaces of the first dam structures 65a1 has a first width in the first direction X, and the distance between the outer surfaces of the second dam structures 65a2 has a second width in the first direction X.

[0060] At the first height level, the first insulating layer region 29Ia1 has a third width in the first direction X, and the second insulating layer region 29Ia2 has a fourth width in the first direction X.

[0061] In one example, the ratio of the sum of the first width and the second width to the length in the first direction X of the connecting staircase region CS is from about 20% to about 40%.

[0062] In one example, the first length and the second length are the same as each other, and the third length is smaller than the first length.

[0063] In one example, the first width and the second width are the same as each other, and each of the first width and the second width is smaller than either the first length or the second length.

[0064] In one example, the third width and the fourth width are substantially the same.

[0065] In one example, the ratio of the first length, the first width, the third length, the second width, and the second length is about 35:about 10:about 10:about 10:about 35.

[0066] Hereinafter, among the components (elements) described in the above-described embodiments, the components (elements) that can be deformed or added will be mainly described. First, with reference to FIGS. 6 and 7, a modification of the semiconductor device according to an embodiment of the present invention will be described. FIG. 6 is a partially enlarged plan view showing a modification of FIG. 2b, and FIG. 7 is a cross-sectional view schematically showing a region cut along the line IIa-IIa' of FIG. 6.

[0067] Referring to FIGS. 6 and 7, an inner dummy vertical structure 47di is disposed which penetrates the insulating layer region 29I and extends into the capping insulating structure 82. The inner dummy vertical structure 47di contains the same material as the first and second dummy vertical structures (47d1, 47d2). The inner dummy structure 47di has a substantially identical cross-sectional structure to the first and second dummy vertical structures (47d1, 47d2).

[0068] The inner dummy vertical structure 47di penetrates the insulating layer region 29I and contacts the pattern structure 15. For example, the inner dummy vertical structure 47di contacts the lower pattern layer 18 of the pattern structure 15.

[0069] Next, referring to FIGS. 8 and 9, another modification of the semiconductor device according to an embodiment of the present invention will be described. FIG. 8 is a partially enlarged plan view showing a modification of FIG. 2b, and FIG. 9 is a cross-sectional view schematically showing a region cut along the line IIb-IIb' of FIG. 8.

[0070] Referring to FIGS. 8 and 9, the insulating layer region 29I includes a first insulating layer region 29Ib1, one or more second insulating layer regions 29Ib2 disposed between the first insulating layer region 29Ib1 and the first intermediate step region IS1, and one or more third insulating layer regions 29Ib3 disposed between the first insulating layer region 29Ib1 and the second intermediate step region IS2. The width of the first insulating layer region 29Ib1 in the first direction X is larger than the width of each of the second and third insulating layer regions (29Ib2, 29Ib3) in the first direction X. The widths of the insulating layer region 29I in the second direction Y are the same as each other.

[0071] Below the first insulating layer region 29Ib1, a gap-fill insulating layer 26b and a part of the pattern structure 15 are disposed. Below each of the second and third insulating layer regions (29Ib2, 29Ib3), the gap-fill insulating layer 26b is not disposed, and the pattern structure 15 is disposed.

[0072] An inner dummy vertical structure 47di having substantially the same cross-sectional structure as the inner dummy vertical structure 47di in FIGS. 6 and 7 is arranged. The inner dummy vertical structure 47di penetrates the insulator stacking regions (29Ib1, 29Ib2, 29Ib3).

[0073] In other examples, the inner dummy vertical structure 47di is omitted.

[0074] The dam structure 65 surrounds the insulator stacking regions (29Ib1, 29Ib2, 29Ib3) respectively. The auxiliary separation structure 71s includes a dummy separation structure 71s3 arranged between the insulator stacking regions 29I adjacent to each other in the first direction X. The length of each dummy separation structure 71s3 in the first direction X is smaller than the width of the first insulator stacking region 29Ib1 in the first direction X. The length of each dummy separation structure 71s3 in the first direction X is smaller than the width of each of the second and third insulator stacking regions (29Ib2, 29Ib3) in the first direction X.

[0075] Next, referring to FIG. 10, a modified example of a semiconductor device according to an embodiment will be described. FIG. 10 is a partially enlarged plan view showing a modified example of FIG. 2b.

[0076] Referring to FIG. 10, the insulator stacking region 29I includes a first insulator stacking region 29Ic1, one or more second insulator stacking regions 29Ic2 arranged between the first insulator stacking region 29Ic1 and the first intermediate staircase region IS1, and one or more third insulator stacking regions 29Ic3 arranged between the first insulator stacking region 29Ic1 and the second intermediate staircase region IS2.

[0077] The width of the first insulator stacking region 29Ic1 in the first direction X is smaller than the width of each of the second and third insulator stacking regions (29Ic2, 29Ic3) in the first direction X. The gap-fill insulating layer 26b is arranged at the lower part of each of the first to third insulator stacking regions (29Ic1, 29Ic2, 29Ic3).

[0078] An inner dummy vertical structure 47di having substantially the same cross-sectional structure as the inner dummy vertical structure 47di in FIGS. 6 and 7 is disposed. The inner dummy vertical structure 47di penetrates the insulator stacking regions (29Ic1, 29Ic2, 29Ic3).

[0079] In other examples, the inner dummy vertical structure 47di is omitted.

[0080] The dam structures 65 surround the respective insulator stacking regions (29Ic1, 29Ic2, 29Ic3). The auxiliary separation structure 71s includes a dummy separation structure 71s3' disposed between the insulator stacking regions 29I adjacent to each other in the first direction X.

[0081] Next, referring to FIG. 11, still another modification of the semiconductor device according to an embodiment of the present invention will be described. FIG. 11 is a partially enlarged plan view showing a modification of FIG. 2b.

[0082] Referring to FIG. 11, the insulator stacking region 29I includes a first insulator stacking region 29Id1, one or more second insulator stacking regions 29Id2 disposed between the first insulator stacking region 29Id1 and the first intermediate staircase region IS1, and one or more third insulator stacking regions 29Id3 disposed between the first insulator stacking region 29Id1 and the second intermediate staircase region IS2. The width of the first insulator stacking region 29Id1 in the first direction X is larger than the width of each of the second and third insulator stacking regions (29Id2, 29Id3) in the first direction X. The gap-fill insulating layer 26b is disposed below each of the first to third insulator stacking regions (29Id1, 29Id2, 29Id3).

[0083] An inner dummy vertical structure 47di having substantially the same cross-sectional structure as the inner dummy vertical structure 47di in FIGS. 6 and 7 is disposed. The inner dummy vertical structure 47di penetrates the first to third insulator stacking regions (29Id1, 29Id2, 29Id3). In other examples, the inner dummy vertical structure 47di is omitted.

[0084] The dam structure 65 surrounds each of the first to third insulator volume layer regions (29Id1, 29Id2, 29Id3).

[0085] The auxiliary separation structure 71s includes a dummy separation structure 71s3” disposed between the insulator volume layer regions 29I adjacent to each other in the first direction X.

[0086] Next, referring to FIG. 12, another modification of the semiconductor device according to an embodiment of the present invention will be described. FIG. 12 is a partially enlarged plan view showing a modification of FIG. 2b.

[0087] Referring to FIG. 12, the insulator volume layer region 29I includes a first insulator volume layer region 29Ie1, one or more second insulator volume layer regions 29Ie2 disposed between the first insulator volume layer region 29Ie1 and the first intermediate staircase region IS1, and one or more third insulator volume layer regions 29Ie3 disposed between the first insulator volume layer region 29Ie1 and the second intermediate staircase region IS2. The width of the first insulator volume layer region 29Ie1 in the first direction X is smaller than the width of each of the second and third insulator volume layer regions (29Ie2, 29Ie3) in the first direction X. The gap-fill insulating layer 26b is disposed below each of the second and third insulator volume layer regions (29Ie2, 29Ie3), and the first insulator volume layer region 29Ie1 does not overlap with the gap-fill insulating layer 26b.

[0088] An inner dummy vertical structure 47di having substantially the same cross-sectional structure as the inner dummy vertical structure 47di in FIGS. 6 and 7 is disposed. The inner dummy vertical structure 47di penetrates the insulator volume layer regions (29Ie1, 29Ie2, 29Ie3).

[0089] In other examples, the inner dummy vertical structure 47di is omitted.

[0090] The dam structure 65 surrounds the insulator volume layer regions (29Ie1, 29Ie2, 29Ie3) respectively. The auxiliary separation structure 71s includes a dummy separation structure 71s3d disposed between the insulator volume layer regions (29Ie1, 29Ie2, 29Ie3) adjacent to each other in the first direction X.

[0091] In one example, the length of each of the dummy separation structures 71s3d in the first direction X is greater than the width of the first insulator layer region 29Ie1 in the first direction X.

[0092] Next, referring to FIG. 13, another modification of the semiconductor device according to an embodiment of the present invention will be described. FIG. 13 is a partial enlarged plan view showing a modification of FIG. 2b.

[0093] Referring to FIG. 13, the insulator layer region 29I includes a first insulator layer region 29If1 and a second insulator layer region 29If2. The dam structure 65 surrounds the first and second insulator layer regions (29If1, 29If2), respectively. The auxiliary separation structure 71s includes a dummy separation structure 71s3e disposed between the insulator layer regions 29I adjacent to each other in the first direction X.

[0094] In one example, the length of each of the dummy separation structures 71s3e in the first direction X is different from the width of each of the first and second insulator layer regions (29If1, 29If2) in the first direction X. For example, the length of each of the dummy separation structures 71s3e in the first direction X is greater than the width of each of the first and second insulator layer regions (29If1, 29If2) in the first direction X.

[0095] In another example, the length of each of the dummy separation structures 71s3e in the first direction X is smaller than the width of each of the first and second insulator layer regions (29If1, 29If2) in the first direction X.

[0096] Next, referring to FIG. 14, various examples of the distances between the dam structure 65 and the auxiliary separation structure 71s and the main separation structure 71m will be described. FIG. 14 is a conceptual plan view for explaining a modification of a part of the components of the present invention.

[0097] Referring to FIG. 14, in FIGS. 1 to 13 described above, the dam structure 65 and the auxiliary separation structure 71s are arranged between a pair of main separation structures 71m adjacent to each other. The pair of main separation structures 71m includes any one of the first main separation structures 71m1, and the auxiliary separation structure 71s includes the auxiliary separation structure 71s1a closest to the first main separation structure 71m1. In FIGS. 1 to 13 described above, the distance between the first main separation structure 71m1 and the dam structure 65 is substantially the same as the distance between the first main separation structure 71m1 and the auxiliary separation structure 71s1a.

[0098] In other examples, as shown in FIG. 14, the distance d2 between the first main separation structure 71m1 and the dam structure 65 is greater than the distance d1 between the first main separation structure 71m1 and the auxiliary separation structure 71s1a.

[0099] Next, referring to FIGS. 15 and 16, a modified example of the semiconductor device according to an embodiment of the present invention will be described. FIG. 15 is a plan view showing a modified example of FIG. 2b, and FIG. 16 is a cross-sectional view schematically showing a region cut along the line IIIa-IIIa' of FIG. 15.

[0100] Referring to FIGS. 15 and 16, first to third dummy separation structures (71s3a1, 71s3a2, 71s3a3) substantially the same as those in FIG. 2b are arranged.

[0101] The insulator layer region 29I includes a first insulator layer region 29Ia1' and a second insulator layer region 29Ia2' spaced apart from each other in the first direction X. The first insulator layer region 29Ia1' is arranged between the first dummy separation structure 71s3a1 and the second dummy separation structure 71s3a3, and the second insulator layer region 29Ia2' is arranged between the second dummy separation structure 71s3a3 and the third dummy separation structure 71s3a2.

[0102] The first and second insulating laminated regions (29Ia1', 29Ia2') are closer to either the first or second main separation structure (71m1, 71m2). For example, the first and second insulating laminated regions (29Ia1', 29Ia2') are closer to the second main separation structure 71m2 than to the first main separation structure 71m1.

[0103] A fourth dummy auxiliary separation structure 71s4 is disposed between the first main separation structure 71m1 and the respective first and second insulating laminated regions (29Ia1', 29Ia2'). The first to fourth dummy separation structures (71s3a1, 71s3a2, 71s3a3, 71s4) are formed of the same material and have the same cross-sectional structure.

[0104] The dam structure 65' surrounds the respective first and second insulating laminated regions (29Ia1', 29Ia2').

[0105] Next, with reference to FIGS. 17a and 17b, a modification of the semiconductor device according to another embodiment of the present invention will be described. FIG. 17a is a plan view showing a modification of FIG. 1, and FIG. 17b is a cross-sectional view schematically showing a region cut along the line Ia-Ia' of FIG. 17a. Here, descriptions of components that overlap or are similar to the components described above are omitted. Referring to FIGS. 17a and 17b, a semiconductor device 100 according to another embodiment of the present invention includes a lower structure 3 that is substantially the same as that described in FIGS. 1 to 5.

[0106] A semiconductor device 100 according to another embodiment of the present invention includes a laminated structure 129 that extends from the memory cell array region MCA to the staircase region SA' on the lower structure 3, a capping insulating structure 182 on the laminated structure 129, a plurality of memory vertical structures 147m that penetrate the laminated structure 129 and extend into the capping insulating structure 182, and a separation structure 171 that penetrates the laminated structure 129 and extends into the capping insulating structure 182.

[0107] In this embodiment, a buffer region BA is disposed between the memory cell array region MCA and the staircase region SA'. The buffer region BA is understood to be a region included in the staircase region SA'.

[0108] The stacked structure 129 includes an interlayer insulating layer and a horizontal layer that are alternately and repeatedly stacked. The stacked structure 129 includes a gate stacked region 129G and a plurality of insulator stacked regions 129I.

[0109] The semiconductor device 100 according to this embodiment further includes a dam structure 165 adjacent to the plurality of insulator stacked regions 129I. For example, the dam structure 165 surrounds each of the plurality of insulator stacked regions 129I.

[0110] The stacked structure 129 includes a lower stacked structure 129L that is substantially the same as the lower stacked structure 29L described in FIGS. 1 to 5, a first upper stacked structure 129U1 that is disposed on the lower stacked structure 129L and has substantially the same or similar regularity as the upper stacked structure 29U described in FIGS. 1 to 5, and a second upper stacked structure 129U2 that has substantially the same or similar regularity as the first upper stacked structure 129U1 on the first upper stacked structure 129U1. For example, the lower stacked structure 129L includes lower interlayer insulating layers 132 and lower horizontal layers (133G, 133I) that are alternately stacked, the first upper stacked structure 129U1 includes first upper interlayer insulating layers 139a and first upper horizontal layers (141Ga, 141Ia) that are alternately stacked, and the second upper stacked structure 129U2 includes second upper interlayer insulating layers 139b and second upper horizontal layers (141Gb, 141Ib) that are alternately stacked. A lower capping insulating layer 35 that covers the lower stacked structure 129L, a first upper capping insulating layer 44L that covers the first upper stacked structure 129U1, and a second upper capping insulating layer 44U that covers the second upper stacked structure 129U2 are disposed. The first upper stacked structure 129U1 is disposed on the lower capping insulating layer 35, and the second upper stacked structure 129U2 is disposed on the first upper capping insulating layer 44L. The lower horizontal layers (133G, 133I) include a lower gate horizontal layer 133G and a lower insulating horizontal layer 133I, the first upper horizontal layers (141Ga, 141Ia) include a first upper gate horizontal layer 141Ga and a first upper insulating horizontal layer 141Ia, and the second upper horizontal layers (141Gb, 141Ib) include a second upper gate horizontal layer 141Gb and a second upper insulating horizontal layer 141Ib.

[0111] In the stacked structure 129, the gate stacked region 129G includes gate horizontal layers (133G, 141Ga, 141Gb), and the plurality of insulator stacked regions 129I include insulating horizontal layers (129I, 141Ia, 141Ib).

[0112] In other examples, the lower stacked structure 129L is omitted.

[0113] The stacked structure 129 is formed in a stepped shape within the stepped region SA'. For example, within the stepped region SA', each of the first and second stacked structures (129U1, 129U2) includes an upper stepped region (USa, USb), an intermediate stepped region (ISa, ISb), and a lower stepped region (LS1a, LS1b) arranged in order in a first direction X away from the memory cell array region MCA.

[0114] In each of the first and second upper stacked structures (129U1, 129U2), the stepped shape of the upper stepped region (USa, USb) is substantially the same as or similar to the shape of the upper stepped region US in FIG. 1. The stepped shape of the lower stepped region (LS1a, LS1b) is substantially the same as or similar to the shape of the first lower stepped region LS1 in FIG. 1.

[0115] The separation structure 171 includes a main separation structure 171m and an auxiliary separation structure 171s corresponding to the main separation structure 71m and the auxiliary separation structure 71s described in FIGS. 2b, 6, 8, 10, 11, 12, 13, and 15, respectively. The main separation structure 171m includes a first main separation structure 171m1 and a second main separation structure 171m2 adjacent to each other.

[0116] In one example, in each of the first and second upper stacked structures (129U1, 129U2), the stepped shape of the intermediate stepped region (ISa, ISb) is substantially the same as or similar to the stepped shape of the intermediate stepped region SA in FIGS. 1 to 5. For example, in each of the first and second upper stacked structures (129U1, 129U2), the stepped shape of the intermediate stepped region (ISa, ISb) includes a first intermediate stepped region (IS1a, IS1b) corresponding to the first intermediate stepped region (IS1 in FIG. 2b) of FIG. 2b, a connecting stepped region (CSa, CSb) corresponding to the connecting stepped region (CS in FIG. 2b) of FIG. 2b, and a second intermediate stepped region (IS2a, IS2b) corresponding to the second intermediate stepped region (IS2 in FIG. 2b) of FIG. 2b.

[0117] A peripheral contact structure 186p and a gate contact structure 186g corresponding to the above-described peripheral contact structure (86p in FIG. 3a) and gate contact structure (86g in FIG. 3a) are disposed, respectively.

[0118] A plurality of insulating volume layer regions 129I are disposed in the connection staircase regions (CSa, CSb). In the respective connection staircase regions (CSa, CSb) of the first and second upper stacked structures (129U1, 129U2), the plurality of insulating volume layer regions 129I are in the same planar shape as the plurality of insulating volume layer regions 29I described in FIG. 2b, and among the separation structures (171m, 171s), the auxiliary separation structure 171s is in the same planar shape as the auxiliary separation structure 71s described in FIG. 2b.

[0119] In other examples, in the respective connection staircase regions (CSa, CSb) of the first and second upper stacked structures (129U1, 129U2), the plurality of insulating volume layer regions 129I are deformed into the same planar shape as the plurality of insulating volume layer regions 29I in FIGS. 8, 10, 11, 12, 13 or the plurality of insulating volume layer regions 29I in FIG. 15, and the auxiliary separation structure 171s is deformed into the same planar shape as the auxiliary separation structure 71s in FIGS. 8, 10, 11, 12, 13, and 15. In one example, similar to the dummy vertical structures (47d1, 47d2) described in FIGS. 2b, 6, 8, 10, 11, 12, 13, and 15, dummy vertical structures penetrating the stacked structure 129 are disposed. Hereinafter, various examples of the schematic cross-sectional structures of the dummy vertical structure 147d, the memory vertical structure 47m, the separation structure 171, and the dam structure 165 penetrating the stacked structure 129 will be described with reference to FIGS. 18a, 18b, and 18c, respectively. In FIGS. 18a, 18b, and 18c, HL1 means the height level of the upper surface of the lower structure 3 in FIG. 17b, HL2 means the height level of the lower surface of the second upper stacked structure 129U2, HL3 means the height level of the upper surface of the second upper stacked structure 129U2, HL4 means the height level of the upper surface of the second upper capping insulating layer 44U, and HL5 means the height level of the upper surface of the first upper insulating layer 60 disposed on the second upper capping insulating layer 44U.

[0120] Referring to FIG. 18a, the memory vertical structure 147m includes a core insulation pattern 155, a channel layer 153, an information storage structure 149, and a pad pattern 157 corresponding to the core insulation pattern (55 in FIG. 4), the channel layer (53 in FIG. 4), the information storage structure (49 in FIG. 4), and the pad pattern (57 in FIG. 4) of the memory vertical structure (47m in FIG. 4) described above, respectively. The information storage structure 149 includes a first dielectric layer 151a, a second dielectric layer 151c, and an information storage layer 151b corresponding to the first dielectric layer 51a, the second dielectric layer 51c, and the information storage layer 51b of the information storage structure (49 in FIG. 4), respectively. The information storage structure 149 includes a lower information storage structure 149L and an upper information storage structure 149U corresponding to the lower information storage structure 49L and the upper information storage structure 49U of the information storage structure (49 in FIG. 4) described above, respectively.

[0121] The dummy vertical structure 147d includes a dummy core insulation pattern 155', a dummy channel layer 153' covering the side and bottom surfaces of the dummy core insulation pattern 155', a dummy information storage structure 149' covering the outer side and bottom surfaces of the dummy channel layer 153', and a dummy pad pattern 157' on the dummy core insulation pattern 155'. The dummy storage structure 149' includes a first dummy dielectric layer 151a', a second dummy dielectric layer 151c', and a dummy information storage layer 151b' corresponding to the first dielectric layer 51a, the second dielectric layer 51c, and the information storage layer 51b of the information storage structure (49 in FIG. 4), respectively.

[0122] The memory vertical structure 147m and the dummy vertical structure 147d have bent portions (147Va, 147Vd) where at least a part of the side surface bends in a region adjacent to the second height level HL2 or in a region immediately below the second height level HL2.

[0123] The separation structure 171 is formed of silicon oxide. The dam structure 165 includes a first material layer 164a, a second material layer 164b, and a third material pattern 164c corresponding to the first material layer 64a, the second material layer 64b, and the third material pattern 64c of the dam structure (65 in FIG. 5) described above, respectively.

[0124] Referring to FIG. 18b, the dummy vertical structure 147d in FIG. 18a is deformed into a dummy vertical structure 147da having a side surface without a bent portion (147Vd in FIG. 18a). The dummy vertical structure 147da may not include at least one of the materials (e.g., polysilicon and silicon nitride) of the channel layer 153, the information storage layer 151b, and the pad pattern 157 of the memory vertical structure 147m. For example, the dummy vertical structure 147da is formed of silicon oxide. The upper surface of the dummy vertical structure 147da is located at a height level higher than the upper surface of the memory vertical structure 147m and lower than the upper surface of the separation structure 171.

[0125] Referring to FIG. 18c, the separation structure 171 and the dam structure 165 in FIG. 18a are deformed into a separation structure 171a and a dam structure 165a each including a side surface having a bent portion (171V, 165V). For example, the separation structure 171a includes a lower separation portion 171L in a region lower than the second height level HL2 and an upper separation portion 171U in a region higher than the second height level HL2, and the dam structure 165a includes a lower dam portion 165L in a region lower than the second height level HL2 and an upper dam portion 165U in a region higher than the second height level HL2. The separation structure 171a includes a bent portion 171V between the side surface of the lower separation portion 171L and the side surface of the upper separation portion 171U. The dam structure 165a includes a bent portion 165V between the side surface of the lower dam portion 165L and the side surface of the upper dam portion 165U.

[0126] With reference to FIGS. 19a to 20b, an example of a method for forming a semiconductor device according to an embodiment of the present invention will be described. In FIGS. 19a to 20b, FIGS. 19a and 20a are cross-sectional views showing regions cut along the line I-I' in FIG. 1, and FIGS. 19b and 20b are cross-sectional views showing regions cut along the lines III-III' and IV-IV' in FIG. 2b.

[0127] Referring to FIGS. 1, 2b, 19a, and 19b, a lower structure 3 is formed. The step of forming the lower structure 3 includes forming peripheral elements 7 on a substrate 5, peripheral wiring 9 that electrically connects the peripheral elements 7, a plurality of peripheral pads (11a, 11b) that electrically connect the peripheral wiring 9, and a lower insulating layer 13 that covers the peripheral wiring 9 and the plurality of peripheral pads (11a, 11b); forming a pattern structure 15 having an opening 15a on the lower insulating layer 13; and forming an intermediate insulating layer 26a that covers the outer surface of the pattern structure 15 and a gap-fill insulating layer 26b that fills the opening 15a of the pattern structure 15. The pattern structure 15 includes a lower pattern layer 18, an intermediate pattern layer 20 patterned on the lower pattern layer 18, and an upper pattern layer 23 that covers the intermediate pattern layer 20.

[0128] A preliminary lower stacked structure 29L’ and a first capping insulating layer 35 that covers the preliminary lower stacked structure 29L’ are formed on the lower structure 3. The preliminary lower stacked structure 29L’ includes lower interlayer insulating layers 32 and preliminary lower horizontal layers 33a that are alternately and repeatedly stacked. A preliminary upper stacked structure 29U’ and a second capping insulating layer 44 that covers the preliminary upper stacked structure 29U’ are formed on the lower structure 3. The preliminary upper stacked structure 29U’ includes upper interlayer insulating layers 39 and upper horizontal layers 41a that are alternately and repeatedly stacked.

[0129] The lower and upper interlayer insulating layers (32, 39) are formed of silicon oxide, and the preliminary lower and upper horizontal layers (33a, 41a) are formed of the lower and upper interlayer insulating layers (32, 39) and other insulating or conductive materials.

[0130] The preliminary lower stacked structure 29L’ and the preliminary upper stacked structure 29U’ constitute a preliminary stacked structure 29P. Since the shape of the preliminary stacked structure 29P is the same as the shape of the stacked structure 29 described in FIGS. 1 to 5, a detailed description of the shape of the preliminary stacked structure 29P is omitted.

[0131] Vertical structures (47m, 47d1, 47b) that penetrate the preliminary stacked structure 29P and the second capping insulating layer 44 are formed.

[0132] Referring to FIGS. 20a and 20b, a third capping insulating layer 60 is formed on the second capping insulating layer 44. Trenches are formed at positions where the separation structures (71m, 71s) and the dam structure 65 described in FIGS. 1 to 5 are disposed. For example, the trenches penetrate the third capping insulating layer 60, the second capping insulating layer 44, the stacked structure 29, and the first capping insulating layer 35.

[0133] The trenches include separation trenches formed at positions where the separation structures (71m, 71s) described in FIGS. 1 to 5 are disposed and dam trenches formed at positions where the dam structure 65 described in FIGS. 1 to 5 is disposed. The shape of the trenches can be variously deformed so as to correspond to various modifications of the separation structures (71m, 71s) and the dam structure 65 described above.

[0134] A dam separation structure 65 is formed in the dam trench.

[0135] The intermediate pattern layer 20 exposed by the separation trench is removed. Here, the intermediate pattern layer 20 remaining in the step region SA is referred to as a first intermediate pattern layer. While removing the intermediate pattern layer exposed by the separation trench, a part of the information storage structure of the memory vertical structure 47m in the memory cell array region MCA is removed to expose the channel layer, and a second intermediate pattern layer 21 is formed in the space where the intermediate pattern layer exposed by the separation trench has been removed.

[0136] Subsequently, the horizontal layer of the stacked structure 29 exposed by the separation trench is removed to form an opening, and a gate horizontal layer (33G, 41G) that fills the opening is formed. The horizontal layer surrounded by the dam structure 65 is referred to as an insulating horizontal layer (33I, 41G). Therefore, the stacked structure 29 is formed of a stacked structure 29 including a gate horizontal layer (33G, 41G) and an insulating horizontal layer (33I, 41G).

[0137] Subsequently, a contact and wiring process is performed to form contact structures (86p, 86g, 86i), a gate connection wiring 91g, a bit line 91b, and an input / output pad 97 as described with reference to FIGS. 1 to 5.

[0138] FIG. 21 is a diagram schematically showing an electronic system including a semiconductor device according to an embodiment of the present invention.

[0139] Referring to FIG. 21, an electronic system 1000 according to an embodiment of the present invention includes a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 is a storage device including the semiconductor device 1100, or an electronic device including the storage device. For example, the electronic system 1000 is a solid state drive device (SSD device) including the semiconductor device 1100, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device.

[0140] The semiconductor device 1100 is a semiconductor device according to any one of the above-described embodiments with reference to FIGS. 1 to 20b. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is disposed beside the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F includes the circuit element 7, the peripheral wiring 9, and the first peripheral pad 11a of the lower structure 3 described above.

[0141] The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0142] The above-described pattern structure 15 includes a silicon layer having an N-type conductivity type, and the silicon layer having the N-type conductivity type is a common source line CSL.

[0143] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to the common source line CSL, upper transistors (UT1, UT2) adjacent to the bit line BL, and a plurality of memory cell transistors MCT arranged between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of the lower transistors (LT1, LT2) and the number of the upper transistors (UT1, UT2) vary diversely depending on the embodiment.

[0144] In one embodiment, the upper transistors (UT1, UT2) include string selection transistors, and the lower transistors (LT1, LT2) include ground selection transistors. The gate lower lines (LL1, LL2) are gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is a gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are gate electrodes of the upper transistors (UT1, UT2), respectively.

[0145] The above-described gate horizontal layer constitutes the gate lower lines (LL1, LL2), the word line WL, and the gate upper lines (UL1, UL2).

[0146] In one embodiment, the lower transistors (LT1, LT2) include a lower erasure control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erasure control transistor UT2 connected in series. At least one of the lower erasure control transistor LT1 and the upper erasure control transistor UT1 is used for an erasure operation to erase data stored in the memory cell transistor MCT by utilizing the Gate Induce Drain Leakage (GIDL) phenomenon.

[0147] The common source line CSL, the first and second gate lower lines (LL1, LL2), the word line WL, and the first and second gate upper lines (UL1, UL2) are electrically connected to the decoder circuit 1110 via a first connection wiring 1115 that extends to the second structure 1100S within the first structure 1100F.

[0148] The first connection wiring 1115 is composed of the gate contact structure, the gate connection wiring, and the peripheral contact structure described above.

[0149] The bit line BL is electrically connected to the page buffer 1120 via a second connection wiring 1125 that extends to the second structure 1100S within the first structure 1100F.

[0150] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by the logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 via the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 via an input / output connection wiring 1135 that extends to the second structure 1100S within the first structure 1100F.

[0151] The input / output connection wiring 1135 includes the above-described input / output contact structure and input / output connection wiring.

[0152] The input / output pad 1101 corresponds to the above-described input / output pad.

[0153] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. According to one embodiment, the electronic system 1000 includes a plurality of semiconductor devices 1100, and in this case, the controller 1200 controls the plurality of semiconductor devices 1000.

[0154] The processor 1210 controls the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 operates according to a predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100 via the NAND interface 1221, data to be recorded in the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transferred. The host interface 1230 provides a communication function between the electronic system 1000 and an external host. When a control command is received from the external host via the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0155] FIG. 22 is a perspective view schematically showing an electronic system including a semiconductor device according to an embodiment of the present invention.

[0156] Referring to FIG. 22, an electronic system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are interconnected to the controller 2002 by a wiring pattern 2005 formed on the main board 2001.

[0157] The main board 2001 includes a connector 2006 including a plurality of pins coupled to an external host. In the connector 2006, the number and arrangement of the plurality of pins vary depending on the communication interface between the electronic system 2000 and the external host. In one embodiment, the electronic system 2000 communicates with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In one embodiment, the electronic system 2000 operates by power supplied from the external host through the connector 2006. The electronic system 2000 further includes a PMIC (Power Management Integrated Circuit) that distributes the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0158] The controller 2002 records data in the semiconductor package 2003, reads data from the semiconductor package 2003, and improves the operating speed of the electronic system 2000.

[0159] The DRAM 2004 is a buffer memory for alleviating the speed difference between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 also operates as a kind of cache memory and provides a space for temporarily storing data in the control operation for the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 further includes a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0160] The semiconductor package 2003 includes first and second semiconductor packages (2003a, 2003b) separated from each other. The first and second semiconductor packages (2003a, 2003b) are semiconductor packages each including a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 includes a semiconductor device according to any one of the above-described embodiments with reference to FIGS. 1 to 20b.

[0161] Each of the first and second semiconductor packages (2003a, 2003b) includes a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 for electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0162] The package substrate 2100 is a printed circuit board including package upper pads 2130. Each of the semiconductor chips 2200 includes input / output pads 2210.

[0163] The input / output pads 2210 are the input / output pads 1101 in FIG. 21 and the input / output pads 97 in FIG. 3a described above.

[0164] In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the input / output pads 2210 and the package top pads 2130. Therefore, the semiconductor chips 2200 in the respective first and second semiconductor packages (2003a, 2003b) are electrically connected to each other by a bonding wire method and are electrically connected to the package top pads 2130 of the package substrate 2100. Based on the embodiment, the semiconductor chips 2200 in the respective first and second semiconductor packages (2003a, 2003b) are electrically connected to each other by a connecting structure including through-silicon vias (TSVs) instead of the bonding wire type connecting structure 2400.

[0165] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 are connected to each other by wirings formed on the interposer substrate.

[0166] As described above, the embodiments of the present invention have been described with reference to the drawings. However, those having ordinary knowledge in the technical field to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea and essential features. Therefore, the embodiments described above are illustrative in all respects and not restrictive.

Explanation of Reference Numerals

[0167] 1, 100, 1100 Semiconductor device 3 Lower structure 5 Substrate 6a Active region 6s Element isolation layer 7 Peripheral element 7a Surrounding source / drain 7b Peripheral gate 9 Peripheral wiring 11a, 11b (First, second) peripheral pads 13 Lower insulating layer 15 Pattern structure 15a, 99a Opening 18 Lower pattern layer 20 (First) intermediate pattern layer 21 Second intermediate pattern layer 23 Upper pattern layer 23s Support base part 26a Intermediate insulating layer 26b Gap-fill insulating layer 29, 129 Stacked structure 29a, 29b (First, second) gate layer 29G, 129G Gate stacked region 29I, 129I Insulator stacked region 29Ia1, 29Ia1’, 29Ib1, 29Ic1, 29Id1, 29Ie1, 29If1 First insulator stacked region 29Ia2, 29Ia2’, 29Ib2, 29Ic2, 29Id2, 29Ie2, 29If2 Second insulator stacked region 29Ib3, 29Ic3, 29Id3, 29Ie3 Third insulator stacked region 29L, 129L Lower stacked structure 29L’ Preliminary lower stacked structure 29P Preliminary stacked structure 29U Upper stacked structure 29U’ Preliminary upper stacked structure 32 First interlayer insulating layer (lower interlayer insulating layer) 33 First horizontal layer 33a Preliminary lower horizontal layer 33G First gate horizontal layer 33I First insulating horizontal layer 33p, 41p Gate pad region 35 First capping insulating layer (lower capping insulating layer) 39 Second interlayer insulating layer (upper interlayer insulating layer) 41 Upper horizontal layer (second horizontal layer) 41a Upper horizontal layer 41G Second gate horizontal layer 41I Upper insulating horizontal layer 42I Second insulating horizontal layer 44 Second capping insulating layer 44L First upper capping insulating layer 44U Second upper capping insulating layer 47b Buffer vertical structure 47d1, 47d2 (First, second) dummy vertical structures 47di Inner dummy vertical structure 47m, 147m Memory vertical structures 49, 149 Information storage structures 49L, 149L Lower information storage structures 49U, 149U Upper information storage structures 51a, 151a First dielectric layer 51b, 151b Information storage layer 51c, 151c Second dielectric layer 53, 153 Channel layer 55, 155 Core insulation pattern 57, 157 Pad pattern 60 Third capping insulating layer (first upper insulating layer) 64a, 164a First material layer 64b, 164b Second material layer 64c, 164c Third material pattern 65, 165, 165a, 165b Dam structures 65a1 First dam structure 65a2 Second dam structure 71, 171, 171a Separation structures 71m, 171m Main separation structures 71m1, 71m2 (First, second) main separation structures 71s, 171s, 71s1a Auxiliary separation structures 71s1 First auxiliary separation structure 71s2 Second auxiliary separation structure 71s3, 71s3’, 71s3”, 71s3d, 71s3e Dummy separation structures 71s3a1 First dummy separation structure 71s3a2 Second dummy separation structure 71s3a3 Third dummy separation structure 71s4 Fourth dummy auxiliary separation structure 75, 81 (Fourth, Fifth) capping insulating layers 78g Lower gate contact plug 78i Lower input / output contact plug 78p Lower peripheral contact plug 82, 182 Capping insulating structures 84g Upper gate contact plug 84i Upper input / output contact plug 84p Upper peripheral contact plug 86b Bit line contact plug 86g, 186g Gate contact structures 86i Input / output contact structures 86p, 186p Peripheral contact structures 89 Upper insulating layer 91b Bit line 91g Gate connection wiring 91i, 1135 Input / output connection wiring 95 Input / output plug 97, 1101, 2210 Input / output pads 99 Passivation layer 129U1 First upper stacked structure 129U2 Second upper stacked structure 132 Lower interlayer insulating layer 133G Lower gate horizontal layer 133I Lower insulating horizontal layer 139a First upper interlayer insulating layer 139b Second upper interlayer insulating layer 141Ga First upper gate horizontal layer 141Ia First upper insulating horizontal layer 141Gb Second upper gate horizontal layer 141Ib Second upper insulating horizontal layer 147d, 147da Dummy vertical structures 147Va, 147Vd, 165V, 171V Bends 149’ Dummy information storage structure 151a’ First dummy dielectric layer 151b’ dummy information storage layer 151c’ second dummy dielectric layer 153’ dummy channel layer 155’ dummy core insulation pattern 157’ dummy pad pattern 165L lower dam portion 165U upper dam portion 171L lower separation portion 171U upper separation portion 1000 electronic system 1100F first structure 1100S second structure 1110 decoder circuit 1115 first connection wiring 1120 page buffer 1125 second connection wiring 1130 logic circuit 1200, 2002 controller 1210 processor 1220 NAND controller 1221 NAND interface 1230 host interface 2000 electronic system 2001 main substrate 2003 semiconductor package 2003a first semiconductor package 2003b second semiconductor package 2004 DRAM 2005 wiring pattern 2006 connector 2100 package substrate 2120 package substrate main body portion 2125 lower pad 2130 package upper pad 2135 internal wiring 2200 semiconductor chip 2300 adhesive layer 2400 connection structure 2500 molding layer BA buffer area CS, CSa, CSb Linking Stage Region IS, Isa, ISb Intermediate Stage Region IS1, IS1a, IS1b First Intermediate Stage Region IS2, IS2a, IS2b Second Intermediate Stage Region LS, LS1a, LS1b Lower Stage Region MCA Memory Cell Array Region SA, SA’ Stage Region US, USa, USb Upper Stage Region

Claims

1. A lower structure including a peripheral circuit and a peripheral pad electrically connected to the peripheral circuit, A stacked structure extending from a memory cell array region to a stepped region adjacent to the memory cell array region on the lower structure, including a gate stack region and a plurality of insulator stack regions whose sides are surrounded by the gate stack region, A capping insulating structure on the stacked structure, A memory vertical structure penetrating the gate stack region of the stacked structure within the memory cell array region, A separation structure penetrating the gate stack region of the stacked structure and extending into the capping insulating structure, Including a peripheral contact structure penetrating at least one of the insulator stack regions of the stacked structure and extending into the capping insulating structure, The stacked structure includes an interlayer insulating layer and a horizontal layer alternately and repeatedly stacked within the memory cell array region and extending into the stepped region within the memory cell array region, The horizontal layer includes a gate horizontal layer and an insulating horizontal layer, The gate stack region includes the gate horizontal layer, Each of the insulator stack regions includes the insulating horizontal layer, Within the stepped region, the stacked structure includes a first stepped region, a connecting stepped region, and a second stepped region arranged in order in a first direction away from the memory cell array region, Each of the first and second stepped regions is stepped and becomes lower with a first height difference in the first direction, The upper surface of the connecting stepped region is flat in the first direction or has a shape with a height difference smaller than the first height difference in the first direction, The plurality of insulator stack regions are spaced apart in the first direction within the connecting stepped region, The separation structure includes a pair of main separation structures parallel to each other and a dummy separation structure between the pair of main separation structures, The plurality of insulator stack regions are arranged between the pair of main separation structures, The dummy separation structure penetrates the connecting stepped region of the stacked structure and is spaced apart from the plurality of insulator stack regions, The semiconductor device, wherein the peripheral contact structure is electrically connected to the peripheral pad.

2. Further including a dam structure, The plurality of insulator stack regions include a first insulator stack region and a second insulator stack region spaced apart from each other in the first direction, The dam structure includes a first dam structure surrounding the first insulator volume layer region and extending into the capping insulation structure, and a second dam structure surrounding the second insulator volume layer region and extending into the capping insulation structure. The dummy separation structure includes a first dummy separation structure between the first step region and the first dam structure, a second dummy separation structure between the second step region and the second dam structure, and a third dummy separation structure between the first insulator volume layer region and the second insulator volume layer region. At the first height level, the first dummy separation structure has a first length in the first direction. At the first height level, the second dummy separation structure has a second length in the first direction. At the first height level, the third dummy separation structure has a third length in the first direction. At the first height level, the first dam structure has a first width in the first direction. At the first height level, the second dam structure has a second width in the first direction. The first width of the first dam structure is the distance between the outer surfaces of the first dam structure in the first direction. The semiconductor device according to claim 1, wherein the second width of the second dam structure is the distance between the outer surfaces of the second dam structure in the first direction.

3. The semiconductor device according to claim 2, wherein the ratio of the sum of the first width and the second width to the length in the first direction of the connecting step region is 20% to 40%.

4. The first width and the second width are the same as each other. The semiconductor device according to claim 2, wherein each of the first width and the second width is smaller than either the first length or the second length.

5. The first width and the second width are the same as each other. The semiconductor device according to claim 2, wherein the third length is smaller than each of the first length and the second length.

6. The semiconductor device according to claim 2, wherein the distance between any one of the main separation structures of the main separation structures and the dam structure at the first height level is greater than the distance between the one main separation structure and the dummy separation structure closest to the one main separation structure.

7. The plurality of insulator volume layer regions include a first insulator volume layer region and a second insulator volume layer region spaced apart from each other in the first direction. The dummy isolation structure includes a first dummy isolation structure between the first stepped region and the first insulating layer region, a second dummy isolation structure between the second stepped region and the second insulating layer region, and a third dummy isolation structure between the first insulating layer region and the second insulating layer region. At the first height level, the first dummy isolation structure has a first length in the first direction. At the first height level, the second dummy isolation structure has a second length in the first direction. At the first height level, the third dummy isolation structure has a third length in the first direction. At the first height level, the first insulating layer region has a first width in the first direction. The semiconductor device according to claim 1, wherein at the first height level, the second insulating layer region has a second width in the first direction.

8. The first length and the second length are the same as each other. The third length is smaller than the first length. The semiconductor device according to claim 7, wherein the first width and the second width are the same as each other.

9. Within the stepped region, the stacked structure includes an upper stepped region, an intermediate stepped region, and a lower stepped region arranged in order in the first direction. The intermediate stepped region includes the first stepped region, the connecting stepped region, and the second stepped region. In the first direction, the upper stepped region and the lower stepped region are stepped so as to be lower with a height difference smaller than the height difference of the first height. The semiconductor device according to claim 1, wherein in a second direction perpendicular to the first direction, the connecting stepped region is stepped so as to be lower with a height difference smaller than the height difference of the first height.

10. The isolation structure further includes a plurality of auxiliary isolation structures arranged between the pair of main isolation structures. The plurality of auxiliary isolation structures include a first auxiliary isolation structure penetrating the first stepped region and extending into the connecting stepped region, and a second auxiliary isolation structure penetrating the second stepped region and extending into the connecting stepped region. The semiconductor device according to claim 1, wherein the first and second auxiliary isolation structures are separated from the dummy isolation structure and the plurality of insulating layer regions.

11. The pair of main isolation structures includes a first main isolation structure and a second main isolation structure. A part of the dummy separation structure is arranged in the first direction with the plurality of insulator volume layer regions, and the rest of the dummy separation structure is arranged between the first main separation structure and the plurality of insulator volume layer regions. The semiconductor device according to claim 1, characterized in that.

12. A lower structure including a peripheral circuit, A stacked structure extending from the memory cell array region on the lower structure to a stepped region adjacent to the memory cell array region, and including a plurality of insulator volume layer regions arranged in a first direction away from the memory cell array region in the gate stack region and the stepped region, A capping insulating structure on the stacked structure, A separation structure penetrating the gate stack region of the stacked structure and extending into the capping insulating structure, The stacked structure is alternately and repeatedly stacked in the memory cell array region, and includes an interlayer insulating layer and a horizontal layer extending into the stepped region in the memory cell array region, The horizontal layer includes a gate horizontal layer and an insulating horizontal layer, The gate stack region includes the gate horizontal layer, Each of the insulator volume layer regions includes the insulating horizontal layer, In the stepped region, the stacked structure includes a first stepped region, one or more connected stepped regions, and a second stepped region, Each of the first and second stepped regions is stepped down with a first height difference in the first direction, Each of the one or more connected stepped regions is flat in the first direction or has a height difference smaller than the first height difference in the first direction, Among the plurality of insulator volume layer regions, the plurality of insulator volume layer regions arranged in sequence while being separated from each other in the first direction are arranged in any one of the one or more connected stepped regions, The semiconductor device further includes a peripheral contact structure that penetrates at least one of the plurality of insulator volume layer regions, extends into the capping insulating structure, and is electrically connected to a peripheral pad connected to the peripheral circuit.

13. There are a plurality of the one or more connected stepped regions, The semiconductor device according to claim 12, wherein the plurality of insulator volume layer regions are arranged separately from each other in the first direction in each of the plurality of connected stepped regions.

14. Further including a dam structure, The separation structure includes a pair of main separation structures parallel to each other and a dummy separation structure between the pair of main separation structures. The plurality of insulating volume layer regions are arranged between the pair of main separation structures. The dummy separation structure penetrates the connection staircase region of the stacked structure and is separated from the plurality of insulating volume layer regions. The dam structure surrounds each of the plurality of insulating volume layer regions, separates the gate stacked region and the plurality of insulating volume layer regions from each other, and extends into the capping insulating structure. The semiconductor device according to claim 12, characterized in that.

15. The lower structure further includes a substrate, peripheral pads on the substrate, a pattern structure on the substrate, and one or more gap-fill insulating layers penetrating the pattern structure. The pattern structure includes a silicon layer. At least a part of the peripheral circuit is arranged between the substrate and the pattern structure. The peripheral pads are arranged between the one or more gap-fill insulating layers and the substrate. The semiconductor device according to claim 12, characterized in that the insulating volume layer region includes one or more first insulating volume layer regions overlapping the one or more gap-fill insulating layers.

16. The semiconductor device according to claim 15, characterized in that the insulating volume layer region further includes a dummy insulating volume layer region that does not overlap the one or more gap-fill insulating layers.

17. The semiconductor device according to claim 16, further comprising a dummy vertical structure penetrating at least one of the insulating volume layer regions of the insulating volume layer region.

18. A main substrate, A semiconductor device on the main substrate, A connection structure electrically connecting the semiconductor device and the main substrate, A controller electrically connected to the semiconductor device on the main substrate, and includes, The semiconductor device is A lower structure including a peripheral circuit, A stacked structure extending from the memory cell array region to the staircase region adjacent to the memory cell array region on the lower structure, and including a plurality of insulating volume layer regions arranged in a first direction away from the memory cell array region in the gate stacked region and the staircase region. A capping insulating structure on the stacked structure, A separation structure penetrating the gate stacked region of the stacked structure and extending into the capping insulating structure, and includes. The stacked structure is alternately and repeatedly stacked within the memory cell array region, and includes an interlayer insulating layer and a horizontal layer that are extended into the staircase region within the memory cell array region. The horizontal layer includes a gate horizontal layer and an insulating horizontal layer. The gate stack region includes the gate horizontal layer. Each of the insulator stack regions includes the insulating horizontal layer. Within the staircase region, the stacked structure includes a first staircase region, one or more connecting staircase regions, and a second staircase region. Each of the first and second staircase regions has a stepped shape that decreases with a first height difference in the first direction. Each of the one or more connecting staircase regions has a flat shape in the first direction or a shape having a height difference smaller than the first height difference in the first direction. An electronic system, wherein a plurality of insulator stack regions arranged in sequence while being spaced apart from each other in the first direction among the plurality of insulator stack regions are disposed within any one of the one or more connecting staircase regions.

19. The main substrate further includes a wiring pattern that electrically connects the semiconductor device and the controller. The semiconductor device further includes a dam structure. The lower structure further includes a substrate, a pattern structure on the substrate, and one or more gap-fill insulating layers penetrating the pattern structure. The pattern structure includes a silicon layer. At least a part of the peripheral circuit is disposed between the substrate and the pattern structure. The dam structure surrounds each of the plurality of insulator stack regions, separates the gate stack region and the plurality of insulator stack regions from each other, extends into the capping insulating structure, and contacts the pattern structure. The electronic system according to claim 18.

20. The first staircase region, one of the one or more connecting staircase regions, and the second staircase region are arranged in sequence in the first direction. The separation structure includes a pair of main separation structures parallel to each other and a dummy separation structure between the pair of main separation structures. The plurality of insulator stack regions are disposed between the pair of main separation structures. The dummy separation structure penetrates the connecting staircase region of the stacked structure and is separated from the plurality of insulator stack regions. The electronic system according to claim 18, characterized in that, within the one connecting staircase region, the plurality of insulator layer regions are spaced apart in the first direction.

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