Contact Pad of Three-Dimensional Memory Device and Method for Manufacturing the Same

Abstract

A three-dimensional (3D) NAND memory device and method are provided. In one aspect, a manufacturing method includes providing a substrate, forming memory cells on the substrate, depositing a first dielectric layer to cover the memory cells, forming at least one contact pad on the substrate, depositing a second dielectric layer over the at least one contact pad, forming a first connection pad on the second dielectric layer, coupling the first connection pad to a second connection pad of a peripheral structure, and exposing the at least one contact pad from a back surface of the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to three-dimensional (3D) memory devices and methods of manufacturing the same.

Background Art

[0002] Not-AND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. With the increasing demand for consumer electronics, cloud computing, and big data, there is a constant need for high-capacity and high-performance NAND memory. As conventional two-dimensional (2D) NAND memory approaches its physical limits, three-dimensional (3D) NAND memory plays an important role. 3D NAND memory uses multiple stacked layers on a single die to achieve high density, high capacity, high-speed performance, low power consumption, and excellent cost efficiency.

[0003] When manufacturing contact pads for 3D NAND structures, a metal layer is deposited and plasma processing is often used during the process. Plasma processing can cause plasma-induced damage (PID) to complementary-metal-oxide-semiconductor (CMOS) circuits. For example, stress can be generated by an unintentional high electric field, and the gate oxide of a metal-oxide-semiconductor (MOS) transistor can deteriorate during plasma processing. Additionally, the insulator of a metal-insulator-metal (MIM) capacitor can also deteriorate or be damaged. The disclosed devices and methods are aimed at solving one or more of the above problems and other problems.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect of the present disclosure, a method of manufacturing a 3D memory device includes preparing a substrate for the 3D memory device, forming memory cells of the 3D memory device on a first portion of a surface of the substrate, depositing a first dielectric layer covering the memory cells and the substrate, forming at least one contact pad on a second portion of the surface of the substrate, depositing a second dielectric layer on the at least one contact pad and the first dielectric layer, forming a first connection pad on the second dielectric layer and connected to the at least one contact pad and the memory cells, coupling the first connection pad to a second connection pad of a peripheral structure, and exposing the at least one contact pad from a back surface of the substrate.

[0005] In another aspect of the present disclosure, a 3D memory device includes an array device, a peripheral device, and an opening. The array device and the peripheral device are coupled face-to-face. The array device includes an insulating layer, one or more contact pads, and memory cells between a first portion of the insulating layer and the peripheral device. The opening is formed through a second portion of the insulating layer to expose one or more contact pads disposed at a bottom of the opening from a back surface of the array device. The bottom of the opening is disposed at a level between the insulating layer and the peripheral device.

[0006] Other aspects of the present disclosure will be understood by those skilled in the art in light of the description, claims, and drawings of the present disclosure.

Brief Description of the Drawings

[0007]

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DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, with reference to the accompanying drawings, the technical solutions in the embodiments of the present disclosure will be described. As much as possible, the same reference numerals are used throughout the drawings to refer to the same or similar components. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all of them. The functions of various embodiments can be exchanged and / or combined. Other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present disclosure shall be within the scope of the present disclosure.

[0009] FIGS. 1 to 13 schematically show the manufacturing process of an exemplary 3D array device 100 according to an embodiment of the present disclosure. The 3D array device 100 is part of a memory device and is sometimes referred to as a 3D memory structure. In the figures, the top view is in the X-Y plane and the cross-sectional view is in the Y-Z plane.

[0010] As shown in the cross-sectional view of FIG. 1, the 3D array device 100 may include a substrate 110. In some embodiments, the substrate 110 can include a single crystal silicon layer. The substrate 110 may also include semiconductor materials such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), polycrystalline silicon, or group III-V compounds such as gallium arsenide (GaAs) and indium phosphide (InP). The substrate 110 may include a non-conductive material such as glass, plastic material, or ceramic material. When the substrate 110 includes a glass, plastic, or ceramic material, the substrate 110 may further include a thin layer of polysilicon deposited on the glass, plastic, or ceramic material. In this case, the substrate 110 can be treated like a polysilicon substrate. As an example, the substrate 110 includes an undoped or lightly doped single crystal silicon layer in the following description.

[0011] In some embodiments, the upper portion of the substrate 110 can be doped with an n-type dopant by ion implantation and / or diffusion to form a doped region 111. The dopant in the doped region 111 can include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). As shown in FIG. 1, a cover layer 120 can be deposited on the doped region 111. The cover layer 120 is a sacrificial layer and can include a single layer or multiple layers. For example, the cover layer 120 can include one or more of a silicon oxide layer and a silicon nitride layer. The cover layer 120 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some other embodiments, the cover layer 120 can include another material such as aluminum oxide.

[0012] Furthermore, a sacrificial layer 130 can be deposited on the cover layer 120. The sacrificial layer 130 can include a dielectric material, a semiconductor material, or a conductive material. An exemplary material for the sacrificial layer 130 is polysilicon.

[0013] After the polysilicon sacrificial layer 130 is deposited, a layer stack 140 can be formed. The layer stack 140 includes, for example, a plurality of pairs of stacked layers including a first dielectric layer 141 and a second dielectric layer 142 alternately stacked on top of each other. The layer stack can include 64 pairs, 128 pairs, or more than 128 pairs of the first and second dielectric layers 141 and 142.

[0014] In some embodiments, the first dielectric layer 141 and the second dielectric layer 142 may be made of different materials. For example, the different materials may include silicon oxide and silicon nitride. In the following description, the first dielectric layer 141 may illustratively include a silicon oxide layer that can be used as a separation stack layer, and the second dielectric layer 142 may illustratively include a silicon nitride layer that can be used as a sacrificial stack layer. The sacrificial stack layer can then be etched away and replaced with a conductor layer. The first dielectric layer 141 and the second dielectric layer 142 may be deposited by CVD, PVD, ALD, or a combination thereof.

[0015] FIG. 2 shows a schematic cross-sectional view of a 3D array device 100 according to an embodiment of the present disclosure. As shown in FIG. 2, after the layer stack 140 is formed, a stair-forming process may be performed to trim a part of the layer stack 140 into a stair structure. In the stair-forming process, any suitable etching process including a dry etching and / or a wet etching process can be used. For example, the height of the stair structure may increase stepwise along the Y direction. The dielectric layer 121 may be deposited to cover the stair structure. As shown in FIG. 2, the layer stack 140, the sacrificial layer 130, and the cover layer 120 may be removed in the side surface of the stair structure, for example, in the region on the left side of the stair structure. This region can be regarded as a contact region where contact pads can be formed. The contact region is covered by the dielectric layer 121 during the stair-forming process. In some embodiments, the cover layer 120 may not be etched away in the stair-forming process, and a part of the cover layer 120 may be embedded by the dielectric 121 within the contact region.

[0016] Figures 3 and 4 show schematic top and cross-sectional views of a 3D array device 100 after a channel hole 150 is formed and then filled with a layer structure according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 4 is taken along line A-A' of FIG. 3. The amount, dimensions, and arrangement of the channel holes 150 shown in FIGS. 3 and 4, as well as in other figures of the present disclosure, are exemplary and for illustrative purposes, but any suitable amount, dimensions, and arrangement can be used in the disclosed 3D array device 100 according to various embodiments of the present disclosure.

[0017] As shown in FIGS. 3 and 4, the channel holes 150 extend in the Z direction or a direction substantially perpendicular to the substrate 110 and are arranged to form an array of a predetermined pattern (not shown) in the X-Y plane. The channel holes 150 can be formed, for example, by a dry etching process or a combination of a dry etching process and a wet etching process. Other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and / or chemical mechanical polishing (CMP). The channel holes 150 may have a cylindrical or pillar shape that penetrates the layer stack 140, the sacrificial layer 130, and the cover layer 120 and partially penetrates the doped region 111. After the channel holes 150 are formed, the functional layer 151 can be deposited on the sidewalls and the bottom of the channel holes. The functional layer 151 may include a blocking layer 152 that blocks the outflow of charges on the sidewalls and the bottom of the channel holes, a charge trapping layer 153 that stores charges during the operation of the 3D array element 100 on the surface of the blocking layer 152, and a tunnel insulating layer 154 on the surface of the charge trapping layer 153. The blocking layer 152 can include one or more layers that can include one or more materials. The material of the blocking layer 152 can include high-k dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide, or another wide bandgap material. The charge trapping layer 153 can include one or more layers that can include one or more materials. The material of the charge trapping layer 153 can include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, or another wide bandgap material. The tunnel insulating layer 154 can include one or more layers that can include one or more materials. The material of the tunnel insulating layer 154 may include high-k dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide, or another wide bandgap material.

[0018] In some embodiments, the functional layer 151 may include an oxide-nitride-oxide (ONO) structure. Optionally, the functional layer 151 may have a structure different from the ONO configuration. When the ONO structure is exemplified in the following description, the functional layer 151 may include a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. That is, the blocking layer 152 may be a silicon oxide layer deposited on the sidewall of the channel hole 150, the charge trap layer 153 may be a silicon nitride layer deposited on the blocking layer 152, and the tunnel insulating layer 154 may be another silicon oxide layer deposited on the charge trap layer 153.

[0019] Furthermore, a channel layer 155 may be deposited on the tunnel insulating layer 154. The channel layer 155 is also referred to as a "semiconductor channel" and may include polysilicon in some embodiments. Alternatively, the channel layer 155 may include amorphous silicon. Similar to the channel hole, the channel layer 155 also extends into the doped region 111 through the layer stack 140. The blocking layer 152, the charge trap layer 153, the tunnel insulating layer 154, and the channel layer 155 may be deposited, for example, by CVD, PVD, ALD, or a combination of two or more of these processes. After the channel layer 155 is formed, the channel hole 150 may be filled with an oxide material 156. The functional layer 151 and the channel layer 155 formed in the channel hole 150 can be regarded as a channel hole structure.

[0020] In the above process, the channel hole 150 is etched after the staircase structure is formed. The channel hole 150 may be formed before the staircase forming process. For example, after the layer stack 140 is manufactured as shown in FIG. 1, the channel hole 150 is formed, and then the functional layer 151 and the channel layer 155 may be deposited. After the channel hole 150 is filled with the oxide material 156, a staircase forming process may be performed to form a staircase structure.

[0021] Figures 5 and 6 show a schematic top view and a schematic cross-sectional view of the 3D array device 100 after the gate line slit 160 is formed according to an embodiment of the present disclosure. The cross-sectional view shown in FIG. 6 is taken along the line B-B' in FIG. 5. The gate line slit is also referred to as a gate line slit structure. The 3D array device 100 may have a number of channel holes 150 disposed in a memory plane (not shown). Each memory plane may be divided into a memory block (not shown) and a memory finger by a gate line slit. For example, the configuration of the channel holes 150 as shown in FIG. 5 may reflect the memory fingers between the gate line slits 160.

[0022] The gate line slit 160 can be formed by a dry etching process or a combination of a dry etching process and a wet etching process. As shown in FIGS. 5 and 6, the gate line slit 160 extends horizontally, for example, in the X direction, extends through the layer stack 140, and reaches or partially penetrates the sacrificial layer 130 in the Z direction or a direction substantially perpendicular to the substrate 110. Thus, the sacrificial layer 130 is exposed at the bottom of the gate line slit 160. Next, a spacer layer (not shown) may be deposited on the sidewalls and the bottom of the gate line slit 160 by CVD, PVD, ALD, or a combination of two or more of these processes. The spacer layer is configured to protect the first and second dielectric layers 141 and 142 and may include, for example, silicon oxide and silicon nitride.

[0023] After the spacer layer is deposited, selective etching may be performed such that a portion of the spacer layer at the bottom of the gate line slit 160 is removed by dry etching or a combination of dry etching and wet etching. The sacrificial layer 130 is exposed again. Subsequently, a selective etching process, for example, a selective wet etching process, may be performed to remove the sacrificial layer 130. When the sacrificial layer 130 is removed, a cavity is formed, and the bottoms of the cover layer 120 and the blocking layer 152 formed in the channel hole 150 are exposed. Further, a plurality of selective etching processes, for example, a plurality of selective wet etching processes, may be performed to continuously remove the exposed portions of the blocking layer 152, the charge trap layer 153, and the tunnel insulating layer 154, and expose the bottom surface portion of the channel layer 155.

[0024] When the cover layer 120 is silicon oxide and / or silicon nitride, the cover layer 120 can be removed when the bottom of the functional layer 151 is etched away. In certain embodiments, the cover layer 120 can include materials other than silicon oxide or silicon nitride, and the cover layer 120 can be removed by one or more additional selective etching processes. When the cover layer 120 is removed, the top surface of the doped region 111 is exposed.

[0025] After the etching process, the doped region 111 and the sides of the channel layer 155 near the bottom of the channel hole 150 can be exposed within the cavity left by etching away the sacrificial layer 130 and the cover layer 120. The cavity can be filled with a semiconductor material such as polysilicon to form the semiconductor layer 131, for example, by a CVD and / or PVD deposition process. The semiconductor layer 131 is n-doped and formed on the exposed surface of the doped region 111 and on the sidewalls or sides of the channel layer 155, and may be electrically connected to the doped region 111 and the channel layer 155.

[0026] Selective epitaxial growth can be performed such that, if necessary, a single-crystalline silicon layer grows on the exposed surface of the doped region 111 and a polysilicon layer grows on the exposed surface of the channel layer 155. Thus, the semiconductor layer 131 can include adjacent layers of single-crystalline silicon and polysilicon.

[0027] When the bottom of the functional layer 151 and the cover layer 120 are etched, some of the spacer layers may be etched away, and the remaining spacer layers may remain on the sidewalls of the gate line slit 160 and protect the first and second dielectric layers 141, 142. After the semiconductor layer 131 is formed, the remaining spacer layers can be removed by a selective etching process, such as a selective wet etching process, to expose the side surfaces of the second dielectric layer 142 around the gate line slit 160. In some embodiments, the innermost spacer layer in contact with the sidewalls is silicon nitride. Since the second dielectric layer 142 is also a silicon nitride layer, the innermost spacer layer and the second dielectric layer 142 are removed together during the etching process, leaving a cavity 143 between the first dielectric layers 141 as shown in FIG. 7. Thus, the layer stack 140 is changed to the layer stack 144.

[0028] Furthermore, a conductive material such as tungsten (W) can be grown to fill the cavity 143 left by the removal of the second dielectric layer 142, and a conductor layer 145 can be formed between the first dielectric layers 141. After the conductor layer 145 is manufactured, the layer stack 144 is converted to the layer stack 146 as shown in FIG. 8. The layer stack 146 includes the first dielectric layers 141 and the conductor layer 145 stacked alternately on top of each other. The functional layer 151 and the channel layer 155 in the channel hole 150 can be regarded as a channel structure. Each channel structure extends into the doped region 111 through the layer stack 146 and the conductor layer 145 as shown in FIG. 8.

[0029] In some embodiments, a dielectric layer (not shown) of a high-k dielectric material such as aluminum oxide may be deposited before metal W is deposited in cavity 143, followed by deposition of a layer of a conductive material such as titanium nitride (TiN) (not shown). Further, metal W may be deposited to form conductor layer 145. CVD, PVD, ALD, or a combination of two or more of these processes can be used in the deposition process. Alternatively, conductor layer 145 can be formed using another conductive material such as cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), doped silicon, or any combination thereof.

[0030] Referring to FIG. 8, a portion of each functional layer 151 within channel hole 150 is between a portion of one of conductor layers 145 and a portion of channel layer 155 within channel hole 150. Each conductor layer 145 is configured to electrically connect rows of NAND memory cells in the X-Y plane and is configured as a word line of 3D array device 100. Channel layer 155 formed within channel hole 150 is configured to electrically connect columns or strings of NAND memory cells along the Z direction and is configured as a bit line of 3D array device 100. Thus, as part of the NAND memory cell, a portion of functional layer 151 within channel hole 150 in the X-Y plane is disposed between conductor layer 145 and channel layer 155, i.e., between the word line and the bit line. Functional layer 151 can also be considered to be disposed between channel layer 155 and layer stack 146. A portion of conductor layer 145 surrounding a portion of channel hole 150 functions as a control gate or gate electrode of the NAND memory cell. 3D array device 100 can be considered to include a 2D array of strings of NAND cells (such strings are also referred to as "NAND strings"). Each NAND string includes a plurality of NAND memory cells and extends perpendicularly toward substrate 110. The NAND strings form a 3D array of NAND memory cells.

[0031] In the case of the substrate 110, the bottom surface is also referred to as the back surface, and the top surface, i.e., the surface having the doped region 111, may be referred to as the front surface or the surface. As shown in FIG. 8, the NAND memory cells are formed on a part of the surface of the substrate 110.

[0032] After growing the conductor layer 145 in the cavity 143, a dielectric layer (e.g., a silicon oxide layer) can be deposited on the sidewalls and the bottom surface of the gate line slit 160 by CVD, PVD, ALD, or a combination thereof. A dry etching process, or a combination of a dry etching process and a wet etching process, can be performed to remove the dielectric layer at the bottom of the gate line slit and expose a part of the semiconductor layer 131. The gate line slit can be filled with a conductive material 161 (e.g., doped polysilicon) and a conductive plug 162 (e.g., metal W). As shown in FIG. 9, the conductive material 161 in the gate line slit can extend through the layer stack 146 and be in electrical contact with the semiconductor layer 131. The filled gate line slit can become the array common source of the 3D array device 100. In some embodiments, the step of forming the array common source in the gate line slit may include depositing an insulating layer, a conductive layer (such as TiN, W, Co, Cu, or Al), and then a conductive material such as doped polysilicon. Optionally, some of the gate line slits may be filled with a dielectric. In these cases, some other gate line slits can be filled with a conductive material that functions as the common source of the array.

[0033] Figures 10 to 13 show schematic cross-sectional views of a 3D array device 100 at a stage after contacts and vias are formed according to an embodiment of the present disclosure. After the gate line slit 160 is filled and the array common source is formed, the opening for the word line contact 171 is formed, for example, by a dry etching process, or a combination of a dry etching process and a wet etching process, to form an interconnection for the 3D array device 100. The opening of the contact 171 is then filled with a conductive material by CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The conductive material of the contact 171 can include W, Co, Cu, Al, or a combination thereof. Optionally, when the contact 171 is manufactured, a layer of a conductive material (e.g., TiN) may be deposited as a contact layer before another conductive material is deposited.

[0034] Furthermore, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) to form a dielectric layer covering the substrate 110, the contact 171, and the NAND memory cells. The newly deposited dielectric layer is added to the dielectric layer 121, and thus the dielectric layer 121 becomes thicker. The opening for the via 172 can be formed by a dry etching process, or a combination of a dry etching process and a wet etching process. Subsequently, as shown in FIG. 10, the opening can be filled with a conductive material such as W, Co, Cu, Al, or a combination thereof to form the via 172. CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof may be performed. The via 172 can be electrically connected to the word line contact 171, the upper end of the corresponding NAND string, and the plug 162 of the array common source. Optionally, a layer of a conductive material (e.g., TiN) may be deposited first before filling the opening to form the via 172.

[0035] Furthermore, the metal layers 173 and 174 for interconnection can be grown by CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof. The metal layer 173 is deposited on the via 172 and is in electrical contact with the via 172. The metal layer 174 is an interconnection for the contact pad and is located in the contact region on the side of the stepped structure. The metal layers 173 and 174 may include a conductive material such as W, Co, Cu, Al, or a combination thereof.

[0036] Similar to the formation of the via 172, vias 175 and 176 can be formed on the metal layers 173 and 174. For example, as shown in FIG. 11, a dielectric material may be deposited to cover the metal layers 173 and 174 and to make the dielectric layer 121 thicker, openings for the vias 175 and 176 can be formed, and subsequently the openings can be filled with a conductive material to form the vias 175 and 176.

[0037] Referring now to FIG. 12, CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof can be performed to grow metal layers 177 and 178 on vias 175 and 176, respectively. Optionally, a single metal layer 178 (not shown) may be formed on via 176 instead of multiple metal layers 178. In the following description, multiple metal layers 178 are exemplarily used. As shown in FIG. 12, while NAND memory cells are formed on a part of the surface of substrate 110, metal layer 178 is formed on another part of the surface of substrate 110. Metal layers 177 and 178 are formed simultaneously of the same material and are formed at approximately the same level with respect to doping region 111 and substrate 110. The level used herein refers to the X-Y plane along the Z-axis. The level of metal layer 178 refers to the X-Y plane passing through metal layer 178. The height of the level, i.e., the height of the X-Y plane of the level, is measured with respect to the Z-axis. Metal layers 177 and 178 may include a conductive material such as W, Co, Cu, Al, or any combination thereof. Metal layer 177 is electrically connected to layer stack 146 or the NAND memory cell through metal layer 173 and via 175. Metal layer 178 is configured as a contact pad and is connected to metal layer 174 through via 176.

[0038] Furthermore, the CVD or PVD process may be performed again to deposit a dielectric material (e.g., silicon oxide or silicon nitride) to cover the metal layers 177 and 178 and form a dielectric layer that further thickens the dielectric layer 121. Similar to the formation of vias 172 and 175, openings can be formed and then filled with a conductive material to form via 179. Via 179 is deposited on and electrically connected to metal layer 177. Further, a dielectric material may be deposited to fill via 179 and further thicken dielectric layer 121. Openings may be formed and then filled to form connection contacts 170 that function as interconnections with peripheral devices. As shown in FIG. 13, connection pads 170 are each electrically connected to metal layer 177 via via 179. Connection pads 170 may include W, Co, Cu, Al, or a combination of two or more of these materials. Optionally, a contact layer of a conductive material (e.g., TiN) may first be deposited before filling the openings to form connection pads 170.

[0039] FIG. 14 shows a schematic cross-sectional view of a peripheral device 180 according to an embodiment of the present disclosure. The peripheral device 180 is part of a memory device and may also be referred to as a peripheral structure. The peripheral device 180 may include a substrate 181 that can include single-crystalline silicon, Ge, SiGe, SiC, SOI, GOI, polysilicon, or a group III-V compound such as GaAs or InP. A peripheral CMOS circuit (e.g., a control circuit) (not shown) may be fabricated on the substrate 181 and used to facilitate the operation of the memory device. For example, the peripheral CMOS circuit may include metal-oxide-semiconductor field-effect transistors (MOSFETs) and can provide functional devices such as page buffers, sense amplifiers, column decoders, and row decoders. A dielectric layer 182 may be deposited on the substrate 181 and the CMOS circuit. Connection pads and vias such as connection pad 183 may be formed within the dielectric layer 182. The dielectric layer 182 can include one or more dielectric materials such as silicon oxide and silicon nitride. The connection pad 183 is configured as an interconnection with the 3D array device 100 and can include a conductive material such as W, Co, Cu, Al, or a combination thereof.

[0040] FIGS. 15 to 17 schematically illustrate a manufacturing process of an exemplary 3D memory device 190 according to an embodiment of the present disclosure. The cross-sectional views of FIGS. 15 to 17 are in the Y-Z plane. The 3D memory device 190 may include the 3D array device 100 shown in FIG. 13 and the peripheral device 180 shown in FIG. 14. The peripheral device 180 is configured to control the array device 100.

[0041] As shown in FIG. 15, the 3D array device 100 and the peripheral device 180 are bonded by flip-chip bonding to form a 3D memory device 190. In some embodiments, the 3D array device 100 may be turned over vertically so that it is upside down, and the upper surface of the connection pads 170 may face downward in the Z direction. The two devices may be arranged together such that the 3D array device 100 is on top of the peripheral device 180. For example, after alignment such as the connection pads 170 may be aligned with the connection pads 183 respectively, the 3D array device 100 and the peripheral device 180 may be bonded and joined together. The layer stack 146 and the peripheral CMOS circuits may be sandwiched between the substrates 110 and 181, or between the doped region 111 and the substrate 181. In some embodiments, solder or a conductive adhesive may be used to bond the connection pads 170 to the connection pads 183 respectively. Thus, the connection pads 170 are electrically connected to the connection pads 183 respectively. The 3D array device 100 and the peripheral device 180 are in an electrically communicative state after the flip-chip bonding process is completed. For example, the contact pad 178 may be electrically connected to the peripheral device 180 via the connection pads 170 and 183.

[0042] In the case of the 3D array device 100 and the peripheral device 180, the bottom surface of the substrate 110 or 181 can be referred to as the back surface, and the side having the connection pads 170 or 183 can be referred to as the front surface or the surface. As shown in FIG. 15, after the flip-chip bonding process, the 3D array device 100 and the peripheral device 180 are bonded facing each other.

[0043] Thereafter, from the back side (after flip-chip bonding), the substrate 110 of the 3D array device 100 can be thinned by a thinning process such as wafer grinding, dry etching, wet etching, CMP, or a combination thereof. In some embodiments, the substrate 110 may be removed by a thinning process that exposes the doped region 111. The dielectric layer 112 can be grown over the doped region 111 by a deposition process (e.g., a CVD or PVD process). The opening 113 can be formed by a dry etching process or a combination of a dry etching process and a wet etching process. As shown in FIG. 16, the opening 113 can penetrate through the dielectric layer 112, the doped region 111, and the dielectric layer 121 to expose the metal layer 178. The exposed metal layer 178 that is vertically adjacent to the peripheral device 180 and beside the staircase structure and the layer stack 146 can be used as a contact pad of the 3D memory device 190. For example, bonding wires that can connect the 3D memory device 190 to other devices may be bonded onto the metal layer 178. As shown in FIG. 16, the staircase structure may illustratively be between the metal layer 178 and the layer stack 146. As described above, the metal layers 177 and 178 may be formed simultaneously of the same conductive material at the same level. Thus, the metal layers 177 and 178 are at substantially the same level with respect to the doped region 111, the connection pad 183, or the peripheral device 180 after the bonding process. In the vertical direction, the metal layer 177 is between the layer stack 146 and the connection pad 183, the peripheral CMOS circuit, or the peripheral device 180.

[0044] Furthermore, a dielectric material may be deposited to form a dielectric layer 114 on the dielectric layer 112 and on the sidewalls and bottom of the opening 113. The dielectric layer 114 can function as a passivation layer containing materials such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), or combinations thereof. The dielectric layer 114 may be formed by a deposition process such as CVD or PVD. Next, as shown in FIG. 17, a dry etching process or a dry and wet etching process may be performed to remove a portion of the dielectric layer 114 at the bottom of the opening 113. The metal layer 178 is exposed again and becomes a contact pad or a part of the contact pad of the 3D memory device 190.

[0045] The dielectric layers 112 and 114 can be regarded together as an upper insulating layer. As shown in FIG. 17, the layer stack 146 and the NAND memory cells may be disposed between a part (e.g., the first part) of the upper insulating layer and the peripheral device 180, and the metal layer 178 may be disposed between another part (e.g., the second part) of the upper insulating layer and the peripheral device 180. The opening 113 is formed through the second part of the upper insulating layer to expose the metal layer 178 disposed at the bottom of the opening 113 from the back surface of the array device 100. The metal layer 178 and the bottom of the opening 113 can be disposed at a level between the upper insulating layer and the peripheral device 180. Furthermore, the metal layer 178 can be disposed at a level between the NAND memory cells and the peripheral device 180.

[0046] Thereafter, other manufacturing steps or processes may be performed to complete the manufacture of the 3D memory device 190. For simplicity, the details of other manufacturing steps or processes are omitted.

[0047] When the contact pads of the 3D memory device 190 are formed after the 3D array device 100 and the peripheral device 180 are coupled, since plasma processing is used several times during the formation of the contact pads, PID may occur in the peripheral CMOS circuits of the peripheral device 180, causing yield and reliability problems. As shown in FIGS. 15 to 17, the metal layer 178 becomes the contact pads of the 3D memory device 190 after the flip-chip bonding process. That is, instead of after the 3D array device 100 and the peripheral device 180 are coupled, several plasma processing steps are performed during the manufacture of the 3D array device 100. Since the formation of the contact pads is performed before the flip-chip bonding process, the peripheral device 180 is subjected to fewer plasma processing steps after being coupled to the 3D array device 100, and thus the PID occurring in the peripheral CMOS circuits can be reduced. Therefore, the manufacture of the metal layer 178 can reduce the influence of PID and improve the yield and reliability of the 3D memory device 190.

[0048] FIG. 18 shows a schematic flowchart 200 for manufacturing a 3D memory device according to an embodiment of the present disclosure. At 211, a sacrificial layer may be deposited on the upper surface of a substrate for a 3D array device. The substrate may include a semiconductor substrate such as a single-crystalline silicon substrate. In some embodiments, a cover layer may be grown on the substrate before depositing the sacrificial layer. The cover layer may include a single layer or multiple layers grown sequentially on the substrate. For example, the cover layer may include silicon oxide, silicon nitride, and / or aluminum oxide. In some other embodiments, the sacrificial layer can be deposited without first depositing a cover layer on the substrate. The sacrificial layer can include single-crystalline silicon, polysilicon, silicon oxide, or silicon nitride.

[0049] On the sacrificial layer, a layer stack of a 3D array device can be formed. The layer stack may include a first stack layer and a second stack layer that are alternately stacked. The first stack layer includes a first dielectric layer, and the second stack layer may include a second dielectric layer different from the first dielectric layer. In some embodiments, one of the first and second dielectric layers is used as a sacrificial stack layer.

[0050] In 212, a staircase forming process may be performed to convert a part of the layer stack into a staircase structure. The staircase forming process may include a plurality of etchings used to trim a part of the layer stack into a staircase structure. A deposition process of depositing a dielectric layer covering the staircase structure may be performed. A part of the dielectric layer on the side surface of the staircase structure may be used as a contact region where a contact pad may be formed.

[0051] In 213, a channel hole extending through the layer stack and the sacrificial layer may be formed to expose a part of the substrate. A functional layer and a channel layer may be deposited on the sidewall and the bottom surface of each channel hole. The step of forming the functional layer may include the step of depositing a blocking layer on the sidewall of the channel hole, the step of depositing a charge trap layer on the blocking layer, and the step of depositing a tunnel insulating layer on the charge trap layer. The channel layer deposited on the tunnel insulating layer functions as a semiconductor channel and may include a polysilicon layer.

[0052] In 214, a gate line slit of the 3D array device may be formed. Along the vertical direction, the gate line slit may penetrate the layer stack. After the gate line slit is etched, a part of the sacrificial layer is exposed.

[0053] In 215, the sacrificial layer may be etched away and a cavity may be created on the substrate. The cavity exposes the bottom of the blocking layer of the functional layer within the cavity. When a cover layer is deposited on the substrate, the cover layer is also exposed within the cavity. The layers of the functional layer that are sequentially exposed within the cavity, including the blocking layer, the charge trap layer, and the tunnel insulating layer, are each etched away, for example, by one or more selective etching processes. As a result, a part of the functional layer close to the substrate may be removed within the cavity. When deposited, the cover layer is also etched away during the process, and the part of the functional layer may be etched or etched by another selective etching process. Accordingly, a part of the substrate and a part of the channel layer are exposed within the cavity.

[0054] Thereafter, a deposition process for growing a semiconductor layer such as a polysilicon layer within the cavity may be performed. The semiconductor layer is in electrical contact with the channel layer and the substrate.

[0055] In some embodiments, the layer stack may include two dielectric stack layers, and one of the stack layers is sacrificial. The sacrificial stack layer can be etched away at 216 to leave a cavity, and thereafter, the cavity can be filled with a conductive material to form a conductor layer. The conductive material may include a metal such as W, Co, Cu, Al, Ti, or Ta.

[0056] In 217, a dielectric layer such as an oxide layer may be deposited on the sidewalls and bottom surface of the gate line slit. A part of the dielectric layer on the bottom surface may be selectively etched to expose the semiconductor layer. A conductive material such as TiN, W, Cu, Al, and / or doped polysilicon may be deposited on the gate line slit to form an array common source in electrical contact with the semiconductor layer. Further, etching and deposition processes may be performed to form word line contacts, a first metal layer for interconnection, and vias.

[0057] At 218, a conductive material such as W, Co, Cu, Al, or a combination thereof may be deposited to form a second metal layer. Some of the second metal layers can be used as contact pads, and some of the other second metal layers can be used for interconnection. The second metal layer may be covered by a dielectric layer. Further, etching and deposition processes may be performed to form vias and connection pads. The connection pads are configured for connection between the 3D array device and the peripheral device.

[0058] At 219, a flip-chip bonding process may be performed to bond the 3D array device and the peripheral device or to fix the 3D array device to the peripheral device to create a 3D memory device. In some embodiments, the 3D array device may be turned upside down and placed on top of the peripheral device. The connection pads of the 3D array device and the peripheral device can be aligned and then bonded. The substrate of the 3D array device may be thinned. An etching process may be performed to expose the second metal layer configured as a contact pad within the contact region. The contact pads can be used to connect the 3D memory device to another device.

[0059] FIGS. 19-23 schematically illustrate the manufacturing process of an exemplary 3D array device 300 according to an embodiment of the present disclosure. In FIGS. 19-23, the cross-sectional views are in the Y-Z plane.

[0060] As shown in FIG. 19, the 3D array device 300 may include a substrate 310. The substrate 310 may include a single-crystalline silicon layer or may include another semiconductor material such as Ge, SiGe, SiC, SOI, GOI, polysilicon, GaAs, or InP. In the following description, by way of example, the substrate 310 includes an undoped or lightly doped single-crystalline silicon layer.

[0061] In some embodiments, the upper portion of the substrate 310 may be doped with an n-type dopant to form a doped region 311. As shown in FIG. 19, a cover layer 320 may be deposited on the doped region 311. The cover layer 320 is a sacrificial layer and may include a single layer or multiple layers. For example, the cover layer 320 can include one or more of a silicon oxide layer and a silicon nitride layer. The cover layer 320 may be deposited by CVD, PVD, ALD, or a combination thereof. Alternatively, the cover layer 320 may include another material such as aluminum oxide.

[0062] A sacrificial layer 330 may be deposited on the cover layer 320. The sacrificial layer 330 may include a semiconductor material or a dielectric material. In the following description, as an example, the sacrificial layer 330 is a polysilicon layer. After the sacrificial layer 330 is formed, a layer stack 340 may be formed. The layer stack 340 includes a plurality of pairs of stack layers 341 and 342. That is, the stack layers 341 and 342 are alternately laminated.

[0063] In some embodiments, the stack layers 341 and 342 may include a first dielectric layer and a second dielectric layer different from the first dielectric layer. The alternating stack layers 341 and 342 may be deposited by CVD, PVD, ALD, or any combination thereof. In the description, the materials of the stack layers 341 and 342 (that is, the materials of the first and second dielectric layers) are silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as a separation stack layer, and the silicon nitride layer may be used as a sacrificial stack layer.

[0064] Furthermore, a staircase forming process may be performed to trim a part of the layer stack 340 into a staircase structure within the channel hole region 332. The staircase structure may be covered with a dielectric material such as silicon oxide that forms the dielectric layer 321. During the staircase forming process, the stack layers 341 and 342 of the contact region 333, the cover layer 320, and the sacrificial layer 330 may remain unchanged. The contact region 333 may be configured for a contact pad. As shown in FIG. 20, the stack layers 341 and 342 of the contact region 333 may form a layer stack 347 on top of the remaining sacrificial layer 330 and the remaining cover layer 320. The layer stack 347 includes the stack layers 341 and 342. That is, the first and second dielectric layers are alternated. Horizontally, the layer stack 347 may be on the side surface of the staircase structure, for example, on the left side of the staircase structure, and the staircase structure may be between the layer stacks 340 and 347. The staircase structure and the layer stack 347 may be separated by a part of the dielectric layer 321 deposited on the doped region 311.

[0065] FIGS. 21, 22, and 23 show schematic cross-sectional views of the 3D array device 300 at a certain stage according to embodiments of the present disclosure. After the layer stack 340 is formed, a channel hole 350 may be formed. The amount, dimensions, and arrangement of the channel holes 350 shown in FIGS. 21-23 are exemplary for the description of the structure and manufacturing method.

[0066] The channel hole 350 has a cylindrical or pillar shape extending through the layer stack 340, the sacrificial layer 330, and the cover layer 320 and may partially penetrate the doped region 311. After the channel hole 350 is formed, a functional layer 351 may be deposited on the sidewalls and bottom of the channel hole. The functional layer 351 may include a blocking layer on the sidewalls and bottom of the channel hole, a charge trap layer on the surface of the blocking layer, and a tunnel insulating layer on the surface of the charge trap layer.

[0067] In some embodiments, the functional layer 351 may include the ONO structure used in the following description. For example, a silicon oxide layer may be deposited as a blocking layer on the sidewalls of the channel hole 350. A silicon nitride layer may be deposited as a charge trapping layer on the blocking layer. Another silicon oxide layer may be deposited as a tunnel insulating layer on the charge trapping layer. A polysilicon layer may be deposited as the channel layer 355 on the tunnel insulating layer. Similar to the channel hole, the channel layer 355 may also extend into the doped region 311 through the layer stack 340. After the channel layer 355 is formed, the channel hole 350 may be filled with an oxide material. The channel hole 350 may include a conductive material (e.g., metal W) and may be sealed by a plug that can be in electrical contact with the channel layer 355.

[0068] Furthermore, the gate line slit 360 may be formed by a dry etching process or a combination of dry and wet etching processes. The gate line slit 360 may extend through the layer stack 340 and reach the sacrificial layer 330 or may partially penetrate in the Z direction. Thus, at the bottom of the gate line slit 360, a part of the sacrificial layer 330 is exposed. A spacer layer (not shown) may be deposited on the sidewalls and the bottom of the gate line slit 360, and a part of the spacer layer at the bottom of the slit 360 may be removed by etching to expose the sacrificial layer 330 again. The sacrificial layer 330 may be etched. When the sacrificial layer 330 is removed, a cavity is formed, and the bottom of the cover layer 320 and the bottom of the blocking layer formed in the channel hole 350 are exposed. A part of the blocking layer, the charge trapping layer, and the tunnel insulating layer may be removed by etching, and the bottom of the channel layer 355 is exposed. The cover layer 320 may be removed when the bottom of the functional layer 351 is removed by etching or deleted in an additional selective etching process, and may also be removed when the upper surface of the doped region 311 is exposed.

[0069] The cavity may be filled with a semiconductor material such as polysilicon to form the semiconductor layer 331. The semiconductor layer 331 may be deposited on the surfaces of the exposed portions of the doped region 311 and the channel layer 355. Further, the sacrificial stack layer 342 may be removed by etching and replaced by a conductor layer 345 containing a conductive material such as W. As shown in FIG. 21, after the conductor layer 345 is formed, the layer stack 340 becomes the layer stack 346.

[0070] Each conductor layer 345 is configured to electrically connect one or more rows of NAND memory cells along the Y direction or the X - Y plane and is configured as a word line of the 3D array device 300. The channel layer 355 formed within the channel hole 350 is configured to electrically connect NAND strings along the Z direction and is configured as a bit line of the 3D array device 300.

[0071] As shown in FIG. 22, the gate line slit 360 may be filled with a conductive material 361 (e.g., doped polysilicon) and a conductive plug 362 (e.g., conductive material W). In some embodiments, the filled gate line slit may become a source common to the array of the 3D array device 300.

[0072] Thereafter, an opening of the word line contact 371 may be formed. The opening is filled with a conductive material (W, Co, Cu, Al, or a combination thereof) for forming the contact 371. Further, a CVD or PVD process may be performed to deposit a dielectric material (e.g., silicon oxide or silicon nitride) on the 3D array device 300. The dielectric layer 321 becomes thicker. Further, an opening for the via 372 may be formed and subsequently filled with a conductive material such as W, Co, Cu, or Al. Some vias 372 are electrically connected to the word line contact 371. Some vias 372 are electrically connected to the plug 362 and the upper end of the corresponding NAND string.

[0073] Furthermore, metal layers 373 and 374 for interconnection may be deposited. Metal layer 373 is electrically contacted with via 372 respectively. Metal layer 374 is in contact region 333 and is configured to interconnect with contact pads. Metal layers 373 and 374 may include a conductive material such as W, Co, Cu, Al, or a combination thereof.

[0074] Furthermore, metal layers 373 and 374 may be covered by a dielectric material that makes dielectric layer 321 thicker. Similar to the formation of via 372, vias 375 and 376 may be formed on metal layers 373 and 374 respectively as shown in FIG. 22 and may contact metal layers 373 and 374.

[0075] Furthermore, CVD, PVD, ALD, electroplating, electroless plating, or a combination thereof may be performed to grow metal layers 377 and 378 on vias 375 and 376 respectively. Metal layers 377 and 378 can be formed simultaneously with the same material and can be arranged at approximately the same level with respect to layer stacks 346 and 347, doped region 311, or substrate 310. Metal layers 377 and 378 may include a conductive material such as W, Co, Cu, Al, or any combination thereof. Metal layer 377 may be electrically connected to the NAND memory cell via layer stack 346 or metal layer 373 and vias 372 and 375. Metal layer 378 is configured as a contact pad and may be connected to metal layer 374 via via 376. Metal layer 378 can be arranged on a dielectric region including a part of dielectric layer 321 and layer stack 347.

[0076] Furthermore, a CVD or PVD process may be performed again to deposit a dielectric material to cover the metal layers 377 and 378 and thicken the dielectric layer 321. Similar to the formation of vias 372 and 375, an opening can be formed and then filled with a conductive material to form a via 379 that contacts the metal layer 377. Further, a dielectric material may be deposited to cover the via 379 and further thicken the dielectric layer 321. An opening is made and filled to form a connection pad 370 that serves to connect to a peripheral device. The connection pad 370 is in electrical contact with the via 379, respectively, as shown in FIG. 23. The connection pad 370 may include W, Co, Cu, Al, or a combination thereof.

[0077] FIG. 24 schematically shows a peripheral device 380 in cross section according to an embodiment of the present disclosure. The peripheral device 380 may include a semiconductor substrate 381 (e.g., a single crystal silicon substrate). A peripheral CMOS circuit (e.g., a control circuit) (not shown) may be fabricated on the substrate 381 and used to facilitate the operation of the 3D array device 300. A dielectric layer 382 including one or more dielectric materials is deposited on the substrate 381. Connection pads and vias, such as connection pad 383, may be formed in the dielectric layer 382. The connection pad 383 is configured to connect to the 3D array device 300 and may include a conductive material (e.g., W, Co, Cu, Al, or any combination thereof).

[0078] Figures 25 and 26 illustrate the schematic manufacturing process of an exemplary 3D memory device 390 according to an embodiment of the present disclosure. The cross-sectional views of FIGS. 25-26 are in the Y-Z plane. The 3D memory device 390 is formed by flip-chip bonding a 3D array device 300 and a peripheral device 380. In some embodiments, the 3D array device 300 may be turned upside down such that the upper surface of the connection pads 370 faces downward in the Z direction. The 3D array device 300 may be placed and aligned on top of the peripheral device 380. For example, the connection pads 370 can be aligned with the connection pads 383 respectively. Next, as shown in FIG. 25, the 3D array device 300 and the peripheral device 380 can be bonded together with their surfaces in contact. The connection pads 370 are electrically connected to the connection pads 383 respectively. Thus, the metal layer 378 can be electrically connected to the peripheral device 380 via the connection pads 370 and 383.

[0079] Thereafter, the substrate 310 of the 3D array device 300 can be thinned, and the dielectric layer 312 can be grown over the doped region 311 by a deposition process. The opening 313 can be formed by a dry etching process, or a combination of a dry etching and a wet etching process. The opening 313 penetrates through the dielectric layer 312, the doped region 311, the remaining cover layer 320, the remaining sacrificial layer 330, the layer stack 347, and the dielectric layer 321 to expose the metal layer 378. After the opening 313 is formed, a part of the layer stack 347 is removed by etching. The remaining portion of the layer stack 347 can be regarded as a layer stack including alternating first and second dielectric layers (i.e., stack layers 341 and 342). In some embodiments, the opening 313 may be completely surrounded by the remaining layer stack 347 in the X-Y plane. Optionally, the opening 313 may be partially surrounded by the remaining layer stack 347 in the X-Y plane. For example, in the latter scenario, a part of the opening 313 may pass through the layer stack 347, and another part of the opening 313 may pass through the dielectric region 321 in the X-Y plane. In the vertical direction (e.g., the Z direction), the metal layer 378 is either under the remaining layer stack 347 or between the remaining layer stack 347 and the peripheral device 380. Further, a dielectric layer 314 can be formed as a passivation layer on the sidewalls of the dielectric layer 312 and the opening 313.

[0080] The exposed metal layer 378 beside the staircase structure and the layer stack 346 can be used as a contact pad of the 3D memory device 390. For example, bonding wires can be bonded onto the metal layer 378 for connection with another device. As described above, the metal layer 377 and the metal layer 378 (i.e., the contact pad) are formed simultaneously with the same material. After the flip-chip bonding process, the metal layer 377 is between the layer stack 346 and the peripheral device 380, or between the layer stack 346 and the connection pad 383. The metal layers 377 and 378 are disposed at approximately the same level with respect to the layer stacks 346 and 347, the doped region 311, the connection pad 383, or the peripheral device 380.

[0081] Thereafter, other manufacturing steps or processes may be performed to complete the manufacture of the 3D memory device 390. Details of the other manufacturing procedures or processes are omitted for simplicity.

[0082] Since the contact pads (i.e., the metal layer 378) are formed prior to the flip-chip bonding process, the peripheral device 380 can experience fewer plasma processing steps after being bonded to the 3D array device 300. Accordingly, the PID occurring in the peripheral CMOS circuits can be reduced. The influence of the PID can be reduced, and the yield and reliability of the 3D memory device 390 can be improved.

[0083] The principles and implementations of the present disclosure are illustrated herein by using specific embodiments, but the foregoing description of the embodiments is only intended to assist in the understanding of the present disclosure. Further, features of the foregoing different embodiments can be combined to form additional embodiments. Those skilled in the art can make changes to specific implementations and the scope of application in accordance with the idea of the present disclosure. Therefore, the content of the specification should not be construed as a limitation to the present disclosure.

Description of Reference Numerals

[0084] 100, 300 Three-dimensional (3D) array device 110, 181, 310 Substrate 111, 311 Doped region 112, 114, 121, 182, 312, 321, 382 Dielectric layer 170, 183, 188, 193, 194, 195 Connection pad 120, 320 Cover layer 113, 171, 313 Opening 130, 330 Sacrificial layer 131, 331 Semiconductor layer 140, 144, 146, 340, 346, 347 Layer stack 141 First dielectric layer 142 Second dielectric layer 143 cavities 145 conductor layer 150, 350 channel holes 151, 351 functional layers 152 blocking layer 153 charge trap layer 154 tunnel insulating layer 155, 355 channel layers 156 oxide material 160, 360 gate line slits 161, 361 conductive materials 162, 362 conductive plugs 171, 371 word line contacts 172, 175, 176, 179, 372, 375, 376, 379 vias 173, 174, 177, 178, 373, 374, 377, 378 metal layers 180, 380 peripheral devices 190, 390 3D memory devices 333 contact region 341, 342 alternating stack layers

Claims

【Claim 1】 A method for manufacturing a three-dimensional (3D) memory device, comprising: preparing a substrate for the 3D memory device; forming a plurality of memory cells of the 3D memory device on a first portion of a surface of the substrate; depositing a first dielectric layer covering the plurality of memory cells and the substrate; forming at least one contact pad on a second portion of the surface of the substrate; depositing a second dielectric layer on the at least one contact pad and the first dielectric layer; forming a plurality of first connection pads on the second dielectric layer and connected to the at least one contact pad and the plurality of memory cells; coupling the plurality of first connection pads to a plurality of second connection pads of a peripheral structure; exposing the at least one contact pad from a back surface of the substrate, the step of exposing the at least one contact pad including forming an opening penetrating the substrate and the first dielectric layer to expose the at least one contact pad; forming a layer stack between the second portion of the surface of the substrate and the at least one contact pad, the layer stack including two different types of dielectric layers alternately stacked on each other, and the opening passing through the layer stack; comprising: the step of forming the plurality of memory cells of the 3D memory device comprising: forming a first layer stack including a plurality of first dielectric stack layers and a plurality of conductive stack layers alternately stacked on top of each other; forming the plurality of memory cells through the first layer stack; comprising: the step of forming the plurality of memory cells through the first layer stack comprising: forming a plurality of channel structures extending through the first layer stack, each of the channel structures including a functional layer and a channel layer, the functional layer being between the channel layer and the first layer stack; Forming a semiconductor layer disposed between the first layer stack and the substrate, wherein the channel layer extends within the semiconductor layer and sidewalls of the channel layer are connected to the semiconductor layer; Method. **Claim 2** The method according to claim 1, wherein the semiconductor layer includes one or more doped layers. **Claim 3** The method according to claim 1, further comprising forming a plurality of conductive layers for interconnection on the first dielectric layer. **Claim 4** The method according to claim 3, wherein the at least one contact pad and the plurality of conductive layers include the same material and are disposed at the same level with respect to the substrate. **Claim 5** The step of exposing the at least one contact pad The method according to claim 4, further comprising thinning or removing the substrate before forming the opening to expose the at least one contact pad. **Claim 6** Forming a second layer stack, wherein the second layer stack is disposed between the second portion of the surface of the substrate and the at least one contact pad and includes a plurality of second dielectric stack layers and a plurality of third dielectric stack layers stacked alternately on top of each other; the method according to claim 1, further comprising the step. **Claim 7** An array device and a peripheral device coupled to face each other, wherein The array device includes An insulating layer; One or more contact pads; A plurality of memory cells between the first portion of the insulating layer and the peripheral device; A first layer stack including a plurality of first dielectric stack layers and a plurality of conductive stack layers stacked alternately on top of each other, wherein the plurality of memory cells include a plurality of channel structures and the plurality of conductive stack layers, each of the channel structures includes a functional layer and a channel layer, the functional layer is between the channel layer and the first layer stack, and each of the channel structures extends through the plurality of conductive stack layers; a first layer stack; A semiconductor layer disposed between the insulating layer and the first layer stack, wherein the channel layer extends within the semiconductor layer and sidewalls of the channel layer are connected to the semiconductor layer; a semiconductor layer; An array device and a peripheral device including An opening formed through a second portion of the insulating layer, exposing the one or more contact pads disposed at the bottom of the opening from the back surface of the array device, and the bottom of the opening being disposed at a level between the insulating layer and the peripheral device. A layer stack between the second portion of the insulating layer and the one or more contact pads, the layer stack including two different types of dielectric layers stacked alternately with each other. Comprising A three-dimensional (3D) memory device. **Claim 8** The 3D memory device according to claim 7, further comprising a plurality of conductive layers between the insulating layer and the peripheral device and connected to the plurality of memory cells. **Claim 9** The 3D memory device according to claim 8, wherein the one or more contact pads and the plurality of conductive layers contain the same material and are disposed at the same level with respect to the peripheral device. **Claim 10** The 3D memory device according to claim 7, further comprising a second layer stack disposed between the second portion of the insulating layer and the one or more contact pads. **Claim 11** The 3D memory device according to claim 10, wherein the second layer stack includes a plurality of second dielectric stack layers and a plurality of third dielectric stack layers stacked alternately on top of each other. **Claim 12** The 3D memory device according to claim 7, wherein the one or more contact pads are disposed at a level between the insulating layer and the peripheral device. **Claim 13** The 3D memory device according to claim 12, wherein the one or more contact pads are disposed at a level between the plurality of memory cells and the peripheral device.

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