Method for calibrating driving time of voltage supply circuit

Abstract

To provide a method for calibrating the drive time of a boost circuit in order to supply a target gradation voltage to a load using the boost circuit. [Solution] A method for calibrating a boost circuit according to the present technology includes: (a) resetting a load to a reference voltage; (b) supplying a charging voltage to the load via the boost circuit for a drive time so that charge sharing occurs in the load; (c) comparing the voltage of the load after charge sharing with a target voltage; and (d) adjusting the drive time according to the result of (c).

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority and benefit of Korean Patent Application No. 10 - 2020 - 0038874, filed on March 31, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to a method for calibrating the driving time of a voltage supply circuit.

Background Art

[0003] In a display device, a switch connected to a pixel is turned on via a gate driver, and a voltage corresponding to a gray level to be represented by the pixel is supplied using a source driver including a buffer. As the area, resolution, and frame rate of the display device increase, the resistance and capacitance of the load driven by the buffer increase, and at the same time, the time required to drive the load decreases.

Summary of the Invention

Problems to be Solved by the Invention

[0004] As the area and frame rate of the display device increase, there is a need for a boost circuit that is driven before driving the buffer in order to drive a load including pixels at high speed.

[0005] However, since the deviation that occurs during the process of forming the source driver and the magnitude of the load that appears in the output of the source driver change according to the display position, it is necessary to calibrate the boost circuit in order to supply a desired gradation voltage to the load using the boost circuit.

[0006] An object of the present invention is to provide a method for calibrating the driving time of a boost circuit in order to supply a target gradation voltage to a load using the boost circuit.

Means for Solving the Problems

[0007] The description of the present invention is merely an embodiment for structural and / or functional description. The scope of the present invention should not be construed as being limited to the embodiments described in the context. That is, the embodiments are capable of various modifications, and the scope of the present invention should be construed to include equivalents that implement the technical idea thereof.

[0008] The meanings of the terms described in this application should be construed as follows.

[0009] Terms such as "first" and "second" are used to distinguish one element from another, and the scope of the present invention should not be limited by these terms. For example, the first element can be named the second element. Similarly, the second element can be called the first element.

[0010] Expressions used in the singular form include the plural form as long as they do not have clearly different meanings in the context, and terms such as "including" and "having" are intended to indicate the existence of the features, numbers, steps, operations, components, parts, or combinations thereof disclosed in this specification, and it should be understood that the existence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof is not excluded.

[0011] The expression "and / or" is used to refer to all or one of the identified items when describing embodiments of the present invention. For example, the expression "A and / or B" should be understood as "A", "B", and "A and B".

[0012] In addition, in the description of the embodiments of the present invention, unless otherwise specified, single lines, differential lines, and buses are described without distinction. However, when it is necessary to distinguish single lines, differential lines, and buses, they are described separately.

[0013] According to one aspect of the present invention, there is provided a method for calibrating a boost circuit, including: (a) resetting a load to a reference voltage; (b) supplying a charging voltage to the load via a boost circuit during a driving time so that charge sharing occurs in the load; (c) comparing the voltage of the load after charge sharing with a target voltage; and (d) adjusting the period of the driving time according to the result of (c).

[0014] According to another aspect of the present invention, there is provided a display device for displaying an image, including: a buffer configured to supply a reference voltage to a load including a pixel; a boost circuit configured to supply a charging voltage to the load including the pixel; a calibration unit configured to control the boost circuit to supply the charging voltage to the load during a driving time and control the driving time according to a difference between a target voltage and a voltage formed after charge sharing occurs in the load to which the charging voltage is supplied.

[0015] According to still another aspect of the present invention, there is provided a method for calibrating driving times of a plurality of boost circuits, including: dividing a data line driver including a plurality of boost circuits into a plurality of groups; performing driving time calibration on one or more boost circuits among the boost circuits divided into the plurality of groups; and performing driving time calibration on the remaining boost circuits.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10A

Figure 10B

Figure 10C

Figure 11

Figure 12

Figure 13A

Figure 13B

Figure 13C

Figure 14

Figure 15A

Figure 15B

Figure 15C

Embodiments for Carrying Out the Invention

[0017] Hereinafter, with reference to the drawings, the display device and the calibration method of the booster circuit according to this embodiment will be described. FIG. 1 is a schematic diagram showing the display device according to this embodiment. Referring to FIG. 1, the display device 1 according to this embodiment includes a display panel, a gate driver 14, a source driver 10, and a timing controller that changes the characteristics of the screen source applied from the outside or adjusts the driving time according to the resolution and characteristics of the display system.

[0018] In one embodiment, a data line driver D (see FIG. 2) described later may be included in the source driver 10, and a calibration unit 100 (see FIG. 2) may be included in the timing controller 12 or the source driver 10.

[0019] FIG. 2 is a schematic diagram showing a booster circuit 300 (also referred to as a voltage supply circuit), a buffer 200, a data line driver D including a calibration unit 100, and a load L according to this embodiment. Referring to FIG. 2, the booster circuit 300 includes a first boost switch M1 that is turned on to output a first driving voltage V HIGH and a second boost switch M2 that is turned on to output a second driving voltage V LOW In the illustrated embodiment, the first boost switch M1 is a p-channel metal oxide semiconductor (PMOS) transistor, and the second boost switch M2 is an n-channel metal oxide semiconductor (NMOS) transistor. In an embodiment not shown, the first boost switch M1 and the second boost switch M2 may be semiconductor switches whose conduction and / or interruption of the first electrode and the second electrode are controlled based on a signal supplied to the control electrode. As an example, the first boost switch M1 and the second boost switch M2 may be transistors such as bipolar junction transistors (BJTs), respectively.

[0020] In one embodiment, the first driving voltage V HIGH supplied to the boosting unit 300 is a voltage higher than the highest gradation voltage among the gradation voltages supplied to the pixels, and the second driving voltage V LOWIt may be a voltage lower than the lowest gradation voltage supplied to the pixel. In other embodiments, the first driving voltage V HIGH and the second driving voltage V LOW may be the driving voltage VDD and the ground voltage VSS supplied to the source driver 10 (see FIG. 1) and the timing controller 12 (see FIG. 1), respectively.

[0021] The buffer 200 may include an operational amplifier 210. The operational amplifier 210 may be connected in the form of a unity-gain buffer having a feedback loop or a comparator having an open loop so as to control the first and second switches SW1 and SW2 to be turned on or off.

[0022] In one embodiment, the buffer 200 includes a first switch SW1 connected between the output node Y of the operational amplifier 210 and the output node X of the buffer. The on and off of the first switch SW1 are controlled based on the first switch control signal SWa. The buffer 200 includes a second switch SW2 connected between the output node X of the buffer 200 and the inverting input terminal of the operational amplifier 210. The on and off of the second switch SW2 are controlled based on the second switch control signal SWb. V supplied from the calibration unit 100 p may be supplied to the non-inverting input terminal of the operational amplifier 210.

[0023] In one embodiment, each of the first switch SW1 and the second switch SW2 may include a control electrode, a first electrode, and a second electrode, and the on and off of the first electrode and the second electrode may be controlled based on a signal supplied to the control electrode, and may be a semiconductor switch. The first switch SW1 and the second switch SW2 may be transistors such as, for example, an NMOS transistor, a PMOS transistor, an NPN (negative-positive-negative) BJT, a PNP (positive-negative-positive) BJT, etc.

[0024] Hereinafter, an example will be described in which the first switch SW1 and the second switch SW2 are semiconductor switches that are turned on when they receive a control signal of a logic high state. However, this is for the sake of simplicity, and a person skilled in the art can easily realize the first switch SW1 and the second switch SW2 as semiconductor switches that are turned on when they receive a control signal of a logic high state.

[0025] In one embodiment, the calibration unit 100 receives the comparison result signal DN (see FIG. 8) output by the operational amplifier 210. In another embodiment, the calibration unit 100 receives the comparison result signal DN (see FIG. 9) output by the comparator 400. The calibration unit 100 receives first and second switch control signals SWa and SWb for controlling the first and second switches SW1 and SW2, and a first boost switch control signal P for controlling the first boost switch M1 included in the boost circuit 300. UP and a second boost switch control signal P for controlling the second boost switch M2. DN and the signal V supplied to the non-inverting input terminal of the operational amplifier 210. P The calibration unit 100 also outputs the target voltage V TARGET or the calibration section 100 may output a signal for controlling a multiplexer included in the signal selection section 500 (see FIGS. 13A to 13C and 15A to 15C).

[0026] Referring again to Fig. 2, the load L is driven by the data line driver D. The load L includes a data line that transmits a grayscale voltage and a plurality of pixels connected to the data line, and displays an image by receiving the grayscale voltage. As shown in Fig. 2, the load L can be equivalently modeled through a connection part of a resistor Rp and a capacitor Cp.

[0027] 2 shows a load L connected to one data line, one data line driver D, and a boost circuit 300 and one buffer 200 included in the data line driver D. The source driver 10 includes a plurality of data line drivers D1, D2, ..., D nIt may include (see FIGS. 12 and 14).

[0028] FIG. 3 is a schematic flowchart showing a method for calibrating the driving time of the boost circuit 300 according to this embodiment, and FIG. 4 is a timing diagram when the boost circuit 300 is calibrated by the calibration method of the boost circuit 300 according to this embodiment. FIG. 5 is an equivalent circuit diagram in the reset stage S100. Referring to FIGS. 3 to 5, in the reset stage S100, the load L is reset to the reference voltage V1.

[0029] In one embodiment, the calibration unit 100 supplies a signal SWa in a logic high state to turn on the first switch SW1, and supplies a signal SWb in a logic high state to turn on the second switch SW2.

[0030] The calibration unit 100 supplies the reference voltage V1 to the non-inverting input terminal of the operational amplifier 210. In one embodiment, the reference voltage V1 is lower than the first driving voltage V of the boost unit 300 HIGH and higher than the second driving voltage V LOW It may also be a voltage higher than the ground voltage GND.

[0031] The calibration unit 100 outputs a signal P in a logic high state and a signal P in a logic low state so that the first boost switch M1 and the second boost switch M2 of the boost unit 300 are both turned off. UP and a signal P in a logic low state DN to output.

[0032] Hereinafter, the case where the target voltage V formed on the load L via the boost unit 300 TARGET is higher than the reference voltage V1 will be described. This is merely an example, and from the following description, those skilled in the art can easily implement the second switch M2 included in the boost circuit 300 so that it is driven when the target voltage V supplied via the boost circuit 300 TARGET is lower than the reference voltage V1.

[0033] The reset stage S100 is maintained for a sufficient time so that the voltage of the entire load L is reset to the reference voltage V1 supplied to the output node X of the buffer. Accordingly, the voltage of the load L including the voltage of the output node X of the buffer 200, the voltage of the first node A of the load, and the voltage of the end node B of the load is maintained at the reference voltage V1.

[0034] The charging stage S200 may include a first step of supplying a charging voltage V CHARGE to the load L, in which the boosting unit 300 is driven for a time T drive and a second step of performing charge sharing in the load L by the charging voltage V CHARGE . In the first step, the boosting unit 300 is driven for a time T CHARGE to supply the charging V drive to the load L. CHARGE

[0035] FIG. 6 is a schematic equivalent circuit diagram in the first step of the charging stage. Referring to FIGS. 3, 4, and 6, in the first step, the calibration unit 100 outputs first and second switch control signals SWa and SWb so that both the first and second switches SW1 and SW2 are turned off. The first and second switches SW1 and SW2 are turned off to prevent time delays due to unnecessary charging of the output node of the operational amplifier 210 and the feedback path of the operational amplifier 210.

[0036] The calibration unit 100 supplies first and second switch control signals P HIGH so that the second boosting switch M2 is turned off and the first driving voltage V CHARGE is supplied to the load L as the charging voltage V UP through the first boosting switch M1. DN

[0037] Since the charging voltage V CHARGE is supplied from the boosting circuit 300, in FIG. 4, the voltage V A of the first node A of the load L indicated by the solid line and the voltage V B of the end node B of the load L indicated by the broken line increase. The voltage V of the end point B of the load LB is formed as a voltage lower than the voltage V by the resistance Rp and the capacitor Cp of the load L. A

[0038] FIG. 7 is a schematic equivalent circuit diagram in the second step of the charging stage. Referring to FIGS. 3, 4, and 7, in the second step, the calibration unit 100 outputs a first switch control signal SWa, a second switch control signal SWb, a first boost switch control signal P UP and a second boost switch control signal P DN to turn off all of the first switch SW1, the second switch SW2, the first boost switch M1, and the second boost switch M2. Therefore, the load L is not connected to the data line driver D.

[0039] In the second step, charge sharing occurs between the capacitors Cp of the load L. The voltage of the first node A of the load and the voltage of the terminal node B of the load are made equal as the voltage V S by charge sharing. After charge sharing, the magnitude of the voltage V S formed across the load may be smaller than the magnitude of the voltage V A formed at node A, or may be larger than the magnitude of the voltage V B formed at node B in the first step.

[0040] As will be described later, the calibration unit 100 controls the driving T drive at which the first boost switch M1 and / or the second boost switch M2 is turned on to supply a voltage to the load and controls the voltage V S formed after charge sharing.

[0041] As an example, the voltage within the first node A of the load may be detected. However, since the terminal node B of the load is the final pixel node of the display panel, it may not be possible to detect the voltage at the end of the display panel. Therefore, the second step may be executed for a sufficient time until the same voltage is formed across the entire load.

[0042] FIG. 8 is a schematic circuit diagram of the first embodiment in the comparison stage S300. Referring to FIGS. 3, 4, and 8, in the comparison stage, the voltage V of the load after charge sharing S and the target voltage V TARGET are compared. In one embodiment, the calibration unit 100 supplies the target V TARGET to the non-inverting input terminal of the operational amplifier 210. Further, the calibration unit 100 outputs the second switch control signal SWb after charge sharing, and turns on the second switch SW2 so that V S is supplied to the inverting input terminal of the operational amplifier 210.

[0043] After charge sharing, the voltage V formed at the load L is supplied to the inverting input terminal of the operational amplifier 210 S , and the target voltage V TARGET is supplied to the non-inverting input terminal. The operational amplifier 210 compares the voltage V S formed at the load L after charge sharing with the target voltage V TARGET in order to output the comparison result as the comparison result DN.

[0044] In one embodiment, when the target voltage V TARGET supplied to the non-inverting input terminal is higher than the voltage V S formed at the load, the operational amplifier 210 outputs a logic high signal as the comparison result signal DN. When the voltage V of the load supplied to the inverting input terminal after charge sharing S is higher than the target voltage V TARGET , the operational amplifier 210 outputs a logic low signal as the comparison result signal DN.

[0045] In the embodiment shown in FIG. 8, when the first switch SW1 is turned on, the output signal of the operational amplifier 210 may be supplied to the output node X of the buffer. Thereby, the calibration unit 100 outputs the first switch control signal SWa so that the first switch SW1 is turned off.

[0046] When the display device is driven, the operational amplifier 210 of the present embodiment functions as a component of a buffer that supplies a gradation voltage to the pixel. However, when the booster circuit 300 is calibrated, as described above, the operational amplifier 210 can function as a comparator for comparing the voltage formed in the load L with the target voltage.

[0047] FIG. 9 is a schematic circuit diagram of the second embodiment in the comparison stage. Referring to FIG. 9, in the second embodiment of the comparison stage, the comparator 400 has a target voltage V TARGET and the voltage V formed in the load after charge sharing S may be compared.

[0048] In the second embodiment of the comparison stage, the calibration unit 100 supplies the first switch control signal SWa and the second switch control signal SWb so that both the first switch and the second switch are off. After charge sharing, the V of the load S is supplied to one input of the comparator 400. The target V supplied from the calibration unit 100 TARGET may be supplied to the other input of the comparator 400. The comparator 400 compares the target voltage V TARGET with the charge sharing - stored voltage V of the load S and supplies a comparison result signal DN corresponding to the comparison result to the calibration unit 100.

[0049] For example, when the target voltage V TARGET is higher than the voltage V formed in the load after charge sharing S , the comparator 400 outputs a logic high signal as the comparison result signal DN. When the voltage V formed in the load after charge sharing S is higher than the target voltage V TARGET , the comparator 400 outputs a logic low signal as the comparison result signal DN.

[0050] In another example, when the target voltage V TARGET is higher than the voltage V formed in the load after charge sharing S , the comparator 400 outputs a logic low. Conversely, when the voltage V formed in the load after charge sharing S is higher than the target voltage V TARGETIf it is higher, the comparator 400 outputs a logic high signal as the comparison result signal DN.

[0051] In one embodiment, the comparator 400 can be a comparator that converts an analog signal supplied as one or more inputs into a digital signal, compares the supplied signals, and outputs the result. In another embodiment, the comparator 400 may be a comparator that converts a digital signal supplied as one or more inputs into an analog signal, compares the supplied signals, and outputs the result.

[0052] For example, the comparator 400 converts the charge sharing voltage V of the load supplied as one input into a digital code, and compares this digital code with the target voltage V, which is the digital code supplied by the calibration unit 100 as the other input, and outputs a comparison result signal DN. S TARGET

[0053] In another example, the comparator 400 converts the digital code supplied as the other input of the calibration unit 100 into the target voltage V, which is an analog voltage, and compares this target voltage V with the charge shared voltage V of the load supplied as one input, and outputs a comparison result signal DN. TARGET TARGET S

[0054] In the calibration step S400, the calibration unit 100 adjusts the driving time of the boost circuit 300. FIG. 10A is a schematic diagram showing the configuration of the driving time setting unit 110 of the calibration unit 100. FIG. 10B is a graph for explaining the operation of the driving time setting unit 110. FIG. 10C is a diagram showing the schematic shapes of the first boost switch control signal P UP and the second boost switch control signal P DN output by the driving time setting unit 110. FIG. 11 is a diagram for explaining the process of the control unit 112 calibrating the driving time T drive of the boost unit.

[0055] ​​​​​Referring to FIG. 10A, the driving time setting unit 110 included in the calibration unit 100 includes a counter 114 that receives a clock signal CLK, counts the number of pulses included in the clock signal CLK, and outputs a count result, and a count result signal CNT output by the counter 114 and a driving time control code D output by the control unit 112 BST A comparator 116 that compares the above, and a first boost switch control signal P having a desired driving time from the comparison result of the comparator 116 UP Or a second boost switch control signal P DN A control signal forming unit 118 that forms the above, and a first boost switch control signal P UP Or a second boost switch control signal P DN And a control unit 112 that outputs a driving time control code D corresponding to the driving time of the above, supplies the clock signal CLK, and calibrates the boost circuit 300 BST Including

[0056] Referring to FIGS. 10A and 10B, the counter 114 counts the number of pulses included in the clock signal CLK output from the control unit 112 and outputs a count result. In one embodiment, the count result output by the counter 114 may be the sum of X bits of [X-1~0], and the counter 114 may output a count result signal CNT that increases one by one as the number of pulses included in the clock signal CLK is counted

[0057] The comparator 116 compares the magnitude of the count result signal CNT output from the counter 114 and the driving time control code D output from the control unit 112 BST And outputs a comparison signal comp corresponding to the comparison result. The driving time control code D BST May have the same number of bits [X-1~0] as the count result of the counter 114

[0058] The upper part of FIG. 10B shows a count result signal CNT that increases when the counter 114 counts the number of pulses of the clock signal CLK, and a driving time control code D supplied from the control unit 112 BSTshows the relationship with. During driving, the comparator 116 maintains the comparison signal comp in the logic high state, and when the value of the count result signal CNT is equal to or greater than the value corresponding to the driving time control code D BST the comparator 116 converts the logic high state to the logic low state to form and output the comparison signal comp. Therefore, as shown in the lower graph of FIG. 10B, the comparison signal comp has a pulse width corresponding to the time until the count result signal CNT crosses from 0 to the driving time control code D BST .

[0059] In an embodiment not shown, the comparator 116 maintains the comparison signal comp in the logic low state during the first drive, and when the value of the count result signal CNT is equal to or greater than the value corresponding to the driving time control code D BST the comparator 116 may convert the logic low state to the logic high state to form and output the comparison signal.

[0060] The control signal forming unit 118 receives the comparison signal comp and outputs the first boost switch control signal P UP or the second boost switch control signal P DN . In this embodiment, the calibration unit 100 calibrates the driving time T drive of the first boost switch M1. Thereby, the control unit 112 inverts the comparison signal comp and turns off the second boost switch M2 and turns on the first boost switch M1 to form and output the first boost switch control signal P drive having a pulse width corresponding to the desired driving time T UP (see the upper part of FIG. 10C). In other embodiments, when calibrating the driving time T drive of the second boost switch M2, the control unit 112 turns off the first boost switch M1 and turns on the second boost switch M2 to form and output the second boost switch control signal P drive having a pulse width corresponding to the desired driving time T DN (see the lower part of FIG. 10C).

[0061] Hereinafter, the calibration step S400 will be described with reference to FIGS. 10A to 10C and FIG. 11. FIG. 11 shows the voltage V of the load after charge sharing Sand the drive time control code D input to the counter 114 BST represents the voltage error Error corresponding to the difference from the target voltage V TARGET . In FIG. 11, when the voltage error Error is a negative value, it corresponds to the case where the voltage V S of the load after charge sharing is lower than the target voltage V TARGET , and when the voltage error Error is a positive value, it corresponds to the case where the voltage V S of the load after charge sharing is higher than the target voltage V TARGET .

[0062] Referring to FIGS. 10A to 10C and FIG. 11, the control unit 112 supplies the drive time control code D drive corresponding to the drive time T BST of the boosting unit 300 to the comparison unit 116. When starting the calibration of the boosting unit 300, the control unit 112 supplies the initial value of the drive time control code D BST to the comparison unit 116. The drive time setting unit 110 drives the boosting unit 300 based on the drive time T BST corresponding to the first value of the input drive time control code D drive .

[0063] In one embodiment, the first value of the drive time control code D BST may be the median value (2X - 1) of the values corresponding to the sum of all X bits of [X - 1 to 0] of the drive time control code. As an example, when the drive time control code includes a total of 10 bits, the drive time control code may be a code corresponding to the median value [0000 111 11] from [0000 0000 00] to [1111 1111 11].

[0064] When the comparison result signal DN supplied to the calibration unit 100 corresponds to the case where the voltage V S of the load after charge sharing is higher than the target voltage V TARGET , the calibration unit 100 supplies the drive time control code D BST after reducing it so that the drive time of the boosting circuit 300 becomes shorter. As the drive time control code D BST decreases, the drive time T drivedecreases.

[0065] When the comparison result signal DN supplied to the calibration unit 100 corresponds to the voltage V of the load after charge sharing being S lower than the target voltage V TARGET the calibration unit 100 supplies the drive time control code D so that the drive time of the boost circuit 300 becomes longer. As the drive time control code D BST increases, the drive time T BST of the boost circuit 300 increases. drive increases.

[0066] In the load L after charge sharing, an embodiment of adjusting the drive time of the second boost switch M2 to form a target voltage V TARGET lower than the reference voltage V1 (see FIG. 4) may be executed as follows. The calibration unit 100 determines that the voltage V S formed on the load after charge sharing is lower than the target voltage V TARGET and supplies the drive time control code D so that the drive time of the second boost switch M2 decreases. When the comparison result signal DN indicates that the voltage V BST formed on the load after charge sharing is higher than the target voltage V S the calibration unit 100 supplies the drive time control code D so that the drive time of the second boost switch M2 increases. TARGET When corresponding to BST the calibration unit 100 supplies the drive time control code D so that the drive time of the second boost switch M2 increases.

[0067] The comparison stage is executed again from the comparison result signal DN detected in the comparison stage following the calibration stage, and the data values after that are increased or decreased by half of the previous variation amount. When the drive time control code is composed of X bits and the drive time of the boost circuit is calibrated X times, the difference between the target voltage V TARGET and the voltage V S is calibrated within a predetermined range.

[0068] In the embodiment shown in FIG. 11, as the initial value of the drive time control code D BST 2 X-1 which is the median value of the sum of X bits, is supplied, and after that, the voltage error Error in the initial comparison stage is the voltage VS corresponds to when it is lower than the target voltage V TARGET In the next calibration step (1), the control unit 112 increases the drive time control code D BST by Δ.

[0069] The drive time setting unit 110 controls the boost unit 300 by outputting a signal with a pulse width corresponding to the drive time control code D BST in which the variation amount Δ is reflected. In one embodiment, the variation amount Δ of the counter input may correspond to 2 X-2 which is half of the first value supplied to the counter.

[0070] In the subsequent comparison steps, since the voltage error Error corresponds to the voltage V S being higher than the target voltage V TARGET in the calibration step (2), the control unit 112 decreases the input to the counter 114 by Δ / 2 which is half of the previous variation amount and outputs it to the counter. The drive time setting unit 110 outputs a signal with a corresponding pulse width to control the boost circuit 300.

[0071] In the subsequent comparison steps, since the voltage error Error corresponds to the voltage V S being lower than the target voltage V TARGET in the calibration step (3), the control unit 112 increases the input to the counter 114 by Δ / 4 which is half of the previous variation amount and outputs it to the counter 114. The drive time setting unit 110 outputs a signal with a corresponding pulse width to control the boost circuit 300.

[0072] In the subsequent comparison steps, since the voltage error corresponds to the voltage V S being lower than the target voltage V TARGET in the calibration step (4), the control unit 112 increases the input to the counter 114 by Δ / 8 which is half of the previous variation amount and outputs it to the counter 114. The drive time setting unit 110 outputs a signal with a corresponding pulse width to control the boost circuit 300.

[0073] In one embodiment, the calibration unit 100 is the drive time control code D BSTBy performing a calibration process including a reset stage, a charging stage, a comparison stage, and a calibration stage for the number of bits included in BST , the calibration of the boost circuit 300 included in the corresponding data line driver D is completed. For example, if the drive time control code D

[0074] includes a total of X bits from [X-1~0], the calibration process may be performed X times. S As described above, by performing drive time calibration with half of the previous variation amount added or subtracted, the calibration unit 100 can adjust the charging common voltage V of the load TARGET and the target voltage V BST to have a minimum error corresponding to the value of the least significant bit (LSB) of the drive time control code D.

[0075] The display panel (see FIG. 1) includes a plurality of pixels connected to a plurality of data lines. In the manufacturing process, errors may occur in the plurality of data lines and the plurality of pixels, and their electrical characteristics may be different due to the errors. Therefore, the boost circuits driving the plurality of data lines may be adjusted to be different from each other. Hereinafter, the process of calibrating the boost circuits included in the plurality of data line drivers will be described with reference to FIGS. 12 to 15C.

[0076] FIG. 12 is a schematic diagram showing a plurality of data line drivers D1, D2,..., D n included in the source driver 10 in the first embodiment, and FIGS. 13A to 13C are schematic diagrams showing a signal selection unit 500 including a plurality of multiplexers MUX1, MUX2,..., MUXj in the embodiment shown in FIG. 12.

[0077] Referring to FIGS. 12 and 13A to 13C, n data line drivers D1, D2, and D n may be divided into j groups, and each group may include k data line drivers. If the number of data line drivers included in the source driver 10 is n, it can be expressed as n = j × k (n, j, k are natural numbers).

[0078] In the embodiments shown in FIGS. 12 and 13A to 13C, data line drivers D1, D2, and D n are the first group of D1, D2, …, and D k , D k+1 , D k+2 , …, and D 2k may be divided into the second group of D n-k+1 , D n-k+2 , …, and D n and the j-th group of D

[0079] The signal selection unit 500 may include multiplexers MUX1, MUX2, …, MUXj as many as the number of groups. The calibration unit 100 can output a multiplexer control signal (not shown) and execute control to select and output the signals input to the multiplexers MUX1, MUX2, …, and MUXj.

[0080] In the embodiment shown in FIG. 13A, the comparison signals DN1, DN2, and DN k output by D1, D2, and D belonging to the first group are input to the first multiplexer MUX1. The data line drivers D k belonging to the second group, D k+1 , D k+2 , and D 2k output the comparison signals DN k+1 , DN k+2 , and DN 2k which are input to the second multiplexer MUX2. Similarly, the data line drivers D n-k+1 , D n-k+2 , and D n belonging to the j-th group output the comparison signals DN n-k+1 , DN n-k+2 , and DN n which are input to the j-th multiplexer MUXj. For all the groups to which the data line drivers D1, D2, …, and D n belong, the comparison signals DN1, DN2, …, and DN n output by the data line drivers D1, D2, …, D nis supplied to multiplexers MUX1, MUX2, …, and MUXj.

[0081] The first multiplexer MUX1 outputs, as a selection signal sel1, one of the comparison signals DN1, DN2, …, DN k input in response to a control signal (not shown) output by the calibration unit 100, and each of the plurality of multiplexers outputs, as a selection signal, one of the comparison signals input in response to the control signal output by the calibration unit 100.

[0082] According to an embodiment not shown, the multiplexer can output a plurality of selection signals, and the calibration unit can output a control signal so that the multiplexer outputs a plurality of selection signals.

[0083] The calibration unit 100 can perform boost circuit calibration on a selected number of data line drivers for each group, and can sequentially perform boost circuit calibration on the remaining data line drivers belonging to the group. For example, the calibration unit 100 selects data line drivers D1, data line drivers D k+1 , …, data line drivers D n-k+1 from the first group, the second group, …, the jth group, and performs calibration on the boost circuits included in the corresponding data line drivers. After the calibration of the selected data line drivers is completed, the data line drivers D2 of the first group, the data line drivers D k+2 , …, the data line drivers D n-k+2 included in the jth group may perform boost circuit calibration in parallel for each group in the same manner as the method of performing calibration on the boost circuits included in.

[0084] In an embodiment not shown, boost circuit calibration may be performed for each group. As an example, the calibration unit 100 may perform calibration by first completing calibration on the boost circuit included in the data line drivers belonging to one of the plurality of groups, and then performing calibration on the boost circuit belonging to another group.

[0085] In the embodiment shown in FIG. 13B, one representative data line driver selected from among the data line drivers belonging to the first group, the second group, ···, the j-th group supplies the comparison result signals DN r1 , DN r2 , ···, DN rj to the signal selection unit 500. The calibration unit 100 performs calibration on the booster circuits included in the representative data line drivers of each group. After the calibration on the booster circuits of the representative data line drivers is completed, the calibration unit 100 can collectively calibrate the booster circuits 300 included in the corresponding group using the booster circuit calibration results. According to another embodiment (not shown), the calibration may be performed on two or more representative data line drivers for each group, and calibration may be performed on the booster circuits belonging to the corresponding group using the calibration results.

[0086] In the embodiment shown in FIG. 13C, the data line drivers D1, D2, …, and D n output the comparison result signals DN1, DN2, …, and DN n . The calibration unit 100 can control the signal selection unit 500 to sequentially calibrate the booster circuits included in the plurality of data line drivers D1, D2, …, D n . In the embodiment shown in FIG. 13C, calibration is performed on the booster circuit included in one of the plurality of data line drivers D1, D2, …, D n . Subsequently, the calibration is sequentially performed on the booster circuits included in the remaining data line drivers.

[0087] However, according to another embodiment (not shown), the multiplexer MUX may perform booster circuit calibration by supplying the comparison result signals supplied by two or more data line drivers to the calibration unit 100.

[0088] FIG. 14 is a schematic diagram for describing the drive time calibration on the booster circuits included in the plurality of data line drivers shown in FIG. 9, and FIGS. 15A to 15C are schematic diagrams showing the signal selection unit 500 and the comparison unit 600 of FIG. 14.

[0089] In the embodiments shown in FIGS. 14 and 15A to 15C, data line drivers D1, D2, …, and D n are, as in the above-described embodiments, D1, D2, …, and D k in the first group, D k+1 , D k+2 , …, and D 2k in the second group, and D n-k+1 , D n-k+2 , …, and D n can belong to the j-th group.

[0090] The signal selection unit 500 can include multiplexers MUX1, MUX2, …, MUXj as many as the number of groups. The calibration unit 100 can output a multiplexer control signal (not shown) and perform control such that the signals input to the multiplexers MUX1, MUX2, .., and MUXj are selected and output.

[0091] In the embodiment shown in FIG. 15A, for each group to which the data line drivers D1, D2, …, D k belong, the load voltages V k output by all the data line drivers D1, D2, …, D S,1 , V S,2 , …, and the V S,k after charge sharing are supplied to the multiplexers MUX1, MUX2, …, MUXj.

[0092] Each of the multiplexers MUX1, MUX2, …, and MUXj is controlled based on a control signal (not shown) supplied by the calibration unit 100 so as to output one load voltage after the charge sharing ring in response to a control signal (not shown) such as selection signals sel1, sel2, …, or selj.

[0093] According to an embodiment not shown, the multiplexer can output a plurality of selection signals, and the calibration unit can output a control signal so that the multiplexer outputs a plurality of selection signals.

[0094] The comparison unit 600 may include comparators 400 corresponding to the number of signals output by the multiplexer. As described above, the target potential V output by the calibration unit 100 TARGET is input as one input of the comparator, and the selection signals sel1, sel2, …, selj output by the multiplexer are input as the other input.

[0095] The comparison unit 600 compares the magnitude of the target potential V supplied as one input with the magnitudes of the selection signals sel1, sel2, …, selj supplied as the other input, and outputs comparison result signals DN1, DN2, …, DN TARGET corresponding to the comparison results to the calibration unit 100. j

[0096] As described above, the calibration unit 100 can perform calibration on the selected number of data line drivers for each group, and can sequentially perform calibration on the remaining data line drivers belonging to the group. In an embodiment not shown, each of the multiplexers MUX1, MUX2, .., and MUXj included in the signal selection unit 500 may output two or more selection signals. The calibration unit 100 may control the signal selection unit 500 so that the multiplexer outputs two or more selection signals to the comparison unit 600. Therefore, the calibration unit 100 can select two data line drivers for each group in order to perform calibration on the boost circuits included in each data line driver.

[0097] In an embodiment not shown, calibration may be continuously performed for each group. As an example, the calibration unit 100 may perform calibration by first completing calibration on the boost circuit belonging to the data line drivers belonging to one of the plurality of groups, and then performing calibration on the boost circuit belonging to another group.

[0098] In the embodiment shown in FIG. 15B, one representative data line driver selected from among a plurality of data line drivers for each group has a load voltage V after charge sharing S,r1 V S,r2 …, or V​S,rj is supplied to the signal selection unit 500. The calibration unit 100 charge-shares the load voltage V S,1 , V S,2 , …, V S,k to the multiplexer MUX included in the signal selection unit 500, and outputs a control signal (not shown) so that any one of them is output as the selection signal sel.

[0099] The comparison unit 600 compares the magnitude of the selection signal sel with the magnitude of the target voltage V TARGET , and provides a comparison result signal corresponding to the comparison result to the calibration unit 100 to perform calibration processing. After calibration on the boost circuit of a typical data line driver is completed, the calibration unit 100 can collectively calibrate the boost circuits 300 included in the corresponding group using the calibration result.

[0100] In the embodiment shown in FIG. 15B, calibration may be performed on the corresponding group using one representative data line driver for each group. However, according to another embodiment not shown, calibration may be performed on the corresponding group using two or more representative data line drivers for each group.

[0101] In the embodiment shown in FIG. 15C, after the data line drivers perform charge sharing, they respectively output D1, D2, ···, and D n output load voltages V S,1 , V S,2 , ···, V S,n to D1, D2. The calibration unit 100 can control the signal selection unit 500 to sequentially calibrate the boost circuits included in the plurality of data line drivers D1, D2, …, D n . However, according to another embodiment not shown, the multiplexer MUX may perform boost circuit calibration by supplying the comparison result signals supplied by two or more data line drivers to the calibration unit 100.

[0102] The method of calibrating the above boost circuit may be executed when the display device is manufactured, then shipped, and also executed when the power of the display device is turned off and restarted.

[0103] According to the present embodiment, there is provided an advantage that the driving time of the boost circuit can be calibrated in order to drive the display device according to the high frame rate of the large area display.

[0104] The embodiments shown in the drawings are described as references to assist in the understanding of the present invention. However, the above embodiments are merely examples for the purpose of implementation, and it should be understood by those skilled in the art that various modifications and equivalent embodiments can be made. Therefore, the scope of the present invention should be defined by the appended claims.

Claims

1. A method for calibrating the driving times of a plurality of voltage supply circuits, comprising: dividing a data line driver including the plurality of voltage supply circuits into a plurality of groups; performing driving time calibration on one or more of the voltage supply circuits among the voltage supply circuits divided into the plurality of groups; performing driving time calibration on the remaining voltage supply circuits; a method including: each of the plurality of voltage supply circuits provides a boosted driving voltage and a reference voltage to a pixel of a display device; the driving time calibration calibrates the time during which the boosted driving voltage and the reference voltage are supplied to the pixel; the remaining voltage supply circuits are similarly calibrated using the calibration results of the one or more voltage supply circuits; a method.

2. Performing the driving time calibration on one or more of the voltage supply circuits among the voltage supply circuits divided into the plurality of groups means executing the driving time calibration on one or more voltage supply circuits selected from the plurality of groups; Performing the driving time calibration on the remaining voltage supply circuits means executing the driving time calibration on one or more other voltage supply circuits not selected from the plurality of groups; The method according to Claim 1.

3. In performing the driving time calibration on one or more of the voltage supply circuits among the voltage supply circuits divided into the plurality of groups, the driving time calibration is formed for the voltage supply circuits of any one of the groups; In performing the driving time calibration on the remaining voltage supply circuits, the driving time calibration is executed for the other voltage supply circuits of any one group; The method according to Claim 1.

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