Semiconductor device

Abstract

To provide a semiconductor device with improved reliability.SOLUTION: A semiconductor device comprises: a substrate including first and second regions; a plurality of gate electrodes laminated apart from each other in a first direction perpendicular to the substrate in the first region and forming stepwise pad regions extended to respectively different lengths in a second direction perpendicular to the first direction in the second region; interlayer insulation layers alternately arranged with the gate electrodes; a channel structure arranged so as to penetrate the gate electrodes in the first region, extended in the first direction, and including a channel layer; a separation region arranged so as to penetrate the gate electrodes in the first and second regions and extend in the second direction; an etching stop layer arranged on the uppermost gate electrode among the gate electrodes forming the pad region in the second region so as not to overlap the first region and the separation region; a cell region insulation layer covering the gate electrodes and the etching stop layer; and a contact plug arranged so as to penetrate the cell region insulation layer and the etching stop layer from the top of the second region and connected to the gate electrodes in the pad region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a vertical transistor structure capable of improving reliability.

Background Art

[0002] While the volume of semiconductor devices is gradually decreasing, they require large-capacity data processing. Therefore, it is necessary to increase the integration degree of semiconductor elements constituting such semiconductor devices. Thus, as one method for improving the integration degree of semiconductor devices, a semiconductor device having a vertical transistor structure instead of the conventional planar transistor structure has been proposed.

[0003] However, when having a vertical transistor structure, as the structure becomes more complex, ensuring the quality and reliability of the device has always been a problem.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the conventional semiconductor device having a vertical transistor structure, and an object of the present invention is to provide a semiconductor device with improved reliability.

Means for Solving the Problems

[0005] To achieve the above object, a semiconductor device according to the present invention includes a substrate having a first region and a second region, a plurality of gate electrodes stacked in the first region at intervals along a first direction and forming a stepped pad region extending in different lengths along a second direction in the second region, an interlayer insulating layer arranged alternately with the gate electrodes, in the first region, a channel structure including a channel layer arranged to penetrate the gate electrode and extending along the first direction, a separation region arranged to penetrate the gate electrode in the first region and the second region and extending in the second direction, and the gate electrode forming the pad region in the second region so as not to overlap with the first region and the separation region above an etching stop layer arranged in the gate electrode, a cell region insulating layer covering the gate electrode and the etching stop layer, and a contact plug arranged to penetrate the cell region insulating layer and the etching stop layer from above in the second region and connected to the gate electrode in the pad region and the etching stop layer extends in contact with the upper surface of the gate electrode forming the pad region from the upper surface of the uppermost gate electrode among the gate electrodes, and in the etching stop layer, both ends are positioned at a distance from the side surface of the isolation region characterized by this

[0006] Also, a semiconductor device according to the present invention made to achieve the above object is perpendicular to the upper surface of the substrate a plurality of gate electrodes stacked at intervals along a first direction and forming a stepped pad region extending in different lengths along a second direction, a separation region arranged to penetrate the gate electrode and extending in the second direction, and the gate electrode forming the pad region above an etching stop layer arranged in the gate electrode, and a contact plug arranged to penetrate the etching stop layer and connected to the gate electrode in the pad region and the etching stop layer extends in contact with the upper surface of the gate electrode forming the pad region from the upper surface of the uppermost gate electrode among the gate electrodes The etching stop layer is characterized by being separated from the side surface of the separation region

[0007] Also, a semiconductor device according to the present invention made to achieve the above object includes a substrate having a first region and a second region, a plurality of gate electrodes laminated in the first region so as to be separated from each other along a first direction and forming a stepped pad region by extending to different lengths along a second direction in the second region, a channel structure disposed so as to penetrate the gate electrodes in the first region and extending along the first direction and including a channel layer, a separation region disposed so as to penetrate the gate electrodes in the first region and the second region and extending in the second direction, an etching stop layer disposed on the gate electrodes forming the pad region in the second region, and a contact plug disposed so as to penetrate the etching stop layer and connected to the gate electrodes in the pad region. The etching stop layer extends in contact with the upper surface of the gate electrodes forming the pad region from the upper surface of the uppermost gate electrode among the gate electrodes, and in the etching stop layer, a first end along the second direction is located at the boundary between the first region and the second region, a third direction orthogonal to the first direction and the second direction both ends along [the second direction] are characterized by being located at a distance from the separation region.

Advantages of the Invention

[0008] According to the semiconductor device of the present invention, by selectively disposing the etching stop layer in a partial region, a semiconductor device with improved reliability can be provided.

Brief Description of the Drawings

[0009]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0010] Next, a specific example of a mode for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0011] FIG. 1 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views showing a partial schematic configuration of the semiconductor device according to an embodiment of the present invention. FIGS. 2A to 2C show cross-sections cut along cutting lines I-I', II-II', and III-III' of FIG. 1, respectively.

[0012] Referring to FIGS. 1 to 2C, the semiconductor device 100 includes a substrate 101 having a first region A and a second region B, a gate electrode 130 stacked on the substrate 101, a channel structure CH disposed so as to penetrate the gate electrode 130 in the first region A, an isolation region MS extending through the gate electrode 130 in the first region A and the second region B, an etching stop layer 160 disposed on the uppermost gate electrode 130 among the gate electrodes 130 in a part of the second region B, and a contact plug 180 penetrating the etching stop layer 160 and connected to the gate electrode 130.

[0013] Each of the channel structures CH includes an epitaxial layer 105, a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155. The semiconductor device 100 further includes an interlayer insulating layer 120 alternately laminated with the gate electrode 130 on the substrate 101, an upper isolation region SS penetrating a part of the gate electrode 130 disposed at the top, and a cell region insulating layer 190.

[0014] The first region A of the substrate 101 is a region where the gate electrodes 130 are vertically laminated and the channel structures CH are disposed, and is a region where memory cells are disposed. The second region B is a region where the gate electrodes 130 extend to different lengths from each other, and corresponds to a region for circuit elements in a peripheral circuit region for driving the memory cells and for electrically connecting the memory cells. The second region B is disposed at at least one end of the first region A in at least one direction, for example, the X direction.

[0015] The substrate 101 has an upper surface extending in the X direction and the Y direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a III-V compound semiconductor, or a II-VI compound semiconductor. As an example, the group IV semiconductor can include silicon, germanium, or silicon-germanium. The substrate 101 can also be provided as a bulk wafer or an epitaxial layer.

[0016] The gate electrode 130 is alternately laminated with the interlayer insulating layer 120 to form a laminated structure GS. The gate electrode 130 includes a lower gate electrode 130L forming a ground selection transistor, a memory cell gate electrode 130M forming a memory cell, and an upper gate electrode 130U forming a string selection transistor in sequence from the substrate 101. The number of the memory cell gate electrodes 130M can be determined according to the capacity of the semiconductor device 100. Depending on the embodiment, the lower gate electrode 130L and the upper gate electrode 130U may each be one or more than two, and may have the same or different structures from the memory cell gate electrode 130M. In one embodiment of the present invention, the upper gate electrode 130U is disposed above the string selection transistor, and further includes an upper gate electrode 130U that forms an erase transistor used for an erase operation using a Gate Induced Drain Leakage (GIDL) phenomenon. In one embodiment of the present invention, some of the gate electrodes 130, for example, the memory cell gate electrode 130M adjacent to the lower gate electrode 130L and the upper gate electrode 130U, may be dummy gate electrodes.

[0017] The gate electrodes 130 are vertically stacked and spaced apart from each other on the first region A, and extend to different lengths from each other in the second region B to form a pad region PAD having a stepped structure. In this specification, the pad region PAD is used as a term referring to the entire stepped region in which the lower gate electrode 130 extends longer than the upper gate electrode 130 and the end portion is exposed. As shown in FIG. 2a, in at least some of the gate electrodes 130 excluding the lower gate electrode 130L and the upper gate electrode 130U, a certain number of gate electrodes 130, for example, 1, 2, 4, or 6 gate electrodes 130 form one gate group, and a stepped structure is formed between the gate groups along the X direction. As shown in FIGS. 1 and 2c, the gate electrodes 130 forming one of the gate groups may be arranged to have a stepped structure with each other in the Y direction. Alternatively, the gate electrodes 130 forming one of the gate groups may be arranged to have a stepped structure with each other only in the X direction.

[0018] As shown in FIG. 1, the gate electrodes 130 are separated and arranged from the adjacent gate electrodes 130 in the Y direction by a pair of separation regions MS extending in the X direction. The gate electrode 130 between the pair of isolation regions MS can form one memory block, but the range of the memory block is not limited to this. A part of the gate electrode 130, for example, the memory cell gate electrode 130M, forms one layer within one memory block. The gate electrode 130 can include a semiconductor material, for example, polycrystalline silicon (Si).

[0019] The interlayer insulating layer 120 is disposed between the gate electrodes 130. The interlayer insulating layer 120 is also arranged to be separated from each other in the direction perpendicular to the upper surface of the substrate 101 and extended in the X direction, similar to the gate electrode 130. The interlayer insulating layer 120 can include an insulating material such as silicon oxide or silicon nitride.

[0020] The isolation region MS is arranged to penetrate the gate electrode 130 in the first region A and the second region B and extend along the X direction. The isolation regions MS are arranged parallel to each other. The isolation region MS penetrates the entire gate electrode 130 laminated on the substrate 101 and is connected to the substrate 101. However, in the embodiment, the arrangement position, the number, etc. of the isolation regions MS are not limited to those shown in FIG. 1.

[0021] As shown in FIGS. 2b and 2c, a conductive layer 110 and an isolation insulating layer 107 are arranged in the isolation region MS. The conductive layer 110 is separated from the gate electrode 130 by the isolation insulating layer 107. The conductive layer 110 functions as a common source line of the semiconductor device 100 or a contact plug connected to the common source line.

[0022] The upper isolation region SS extends in the X direction between the isolation regions MS. The upper isolation region SS is disposed in a part of the second region B and the first region A so as to penetrate through a part of the gate electrodes 130 including the uppermost gate electrode 130 within the gate electrodes 130. As shown in FIG. 2b, the upper isolation region SS separates, for example, a total of three gate electrodes 130 from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper isolation region SS can be variously changed according to the embodiment. The upper isolation region SS includes the upper insulating layer 103.

[0023] Each of the channel structures CH forms one memory cell string and is arranged on the first region A in rows and columns, separated from each other. The channel structures CH can be arranged to form a lattice pattern or can be arranged in a zigzag shape in one direction. The channel structures CH have a columnar shape and have side surfaces that are inclined so that the width becomes narrower as they approach the substrate 101 depending on the aspect ratio. In one embodiment of the present invention, the channel structure CH disposed at the end of the first region A adjacent to the second region B can be a dummy channel. Also, the channel structure CH overlapping with the upper isolation region SS can also be a dummy channel. In this case, the dummy channel can have the same or a similar structure as the channel structure CH, but may not perform a substantial function within the semiconductor device 100.

[0024] Referring to the enlarged view of FIG. 2b, a channel layer 140 is disposed within the channel structure CH. The channel layer 140 within the channel structure CH can be formed in an annular shape surrounding the internal channel insulating layer 150, but depending on the embodiment, it can also have a columnar shape such as a cylinder or a prism without the channel insulating layer 150. The channel layer 140 is connected to the epitaxial layer 105 at the lower part. The channel layer 140 can include a semiconductor material such as polycrystalline silicon or single-crystalline silicon, and the semiconductor material may be an undoped material or a material containing p-type or n-type impurities.

[0025] The gate dielectric layer 145 is disposed between the gate electrode 130 and the channel layer 140. The gate dielectric layer 145 extends perpendicularly to the upper surface of the substrate 101 along the channel layer 140. Although not specifically shown, the gate dielectric layer 145 includes a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140. The tunneling layer tunnels charges to the charge storage layer and can include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer is a charge trap layer or a floating gate conductive layer. The blocking layer can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

[0026] The epitaxial layer 105 is disposed on the substrate 101 at the lower end of the channel structure CH and is disposed on the side surface of at least one gate electrode 130. The epitaxial layer 105 is disposed in the recessed region of the substrate 101. The height of the upper surface of the epitaxial layer 105 may be higher than the upper surface of the lowermost gate electrode 130 and lower than the lower surface of the upper gate electrode 130, but is not limited to that shown in the figure. In one embodiment of the present invention, the epitaxial layer 105 can also be omitted. In this case, the channel layer 140 is directly connected to the substrate 101.

[0027] A channel pad 155 is disposed on the upper part of the channel layer 140 in the channel structure CH. The channel pad 155 covers the upper surface of the channel insulating layer 150 and is arranged to be electrically connected to the channel layer 140. The channel pad 155 can include, for example, doped polycrystalline silicon. The channel structure CH arranged linearly in the Y direction between the isolation region MS and the upper isolation region SS is connected to different bit lines respectively according to the arrangement of the upper wiring structure connected to the channel pad 155.

[0028] The etching stop layer 160 is arranged on the upper surface of the uppermost gate electrode 130 within the gate electrode 130 forming the pad region PAD. The etching stop layer 160 is a layer for controlling the etching depth when forming the contact plug 180. The etching stop layer 160 extends downward in a stepped manner along the pad region PAD from the upper part. Specifically, the etching stop layer 160 covers the exposed upper surface and side surfaces of the uppermost gate electrode 130 and extends covering the side surfaces of the interlayer insulating layer 120.

[0029] The etching stop layer 160 is arranged in a region within the second region B where the isolation region MS is not arranged. Thereby, as shown in FIG. 1, the etching stop layer 160 does not overlap with the first region A and the isolation region MS on the plan view. The etching stop layer 160 is arranged as one layer between a pair of isolation regions MS. The etching stop layer 160 is positioned at a distance of the first distance D1 from the channel structure CH closest to the second region B. The etching stop layer 160 is arranged to be in contact with the side surface of the isolation region MS as shown in FIG. 2c. Thereby, the whole of the etching stop layer 160 is arranged to overlap with the gate electrode 130 forming the pad region PAD and the substrate 101 outside the gate electrode 130.

[0030] The first end along the X direction in the etching stop layer 160 is positioned at the boundary between the first region A and the second region B, or adjacent to the boundary. The second end along the X direction in the etching stop layer 160 is arranged to be in contact with the substrate 101 on the upper surface of the substrate 101. However, in one embodiment of the present invention, the second end of the etching stop layer 160 may not extend on the upper surface of the substrate 101 and may be located on the lowermost gate electrode 130. Both ends along the Y direction in the etching stop layer 160 are positioned to be in contact with the side surface of the isolation region MS. The etching stop layer 160 has a rectangular shape in the plan view of FIG. 1 by the above-mentioned ends.

[0031] The etching stop layer 160 can include a substance different from the gate electrode 130 and the cell region insulating layer 190. The etching stop layer 160 can include a metal oxide. For example, the etching stop layer 160 is aluminum oxide (Al x O y ), hafnium oxide (Hf x O y ), tantalum oxide (Ta x O y ), titanium oxide (Ti x O y ), yttrium oxide (Y x O y ), zirconium oxide (Zr x O y ), lanthanum oxide (La x O y ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y ), and any one of praseodymium oxide (Pr2O3).

[0032] Since the etching stop layer 160 is disposed only in the pad region PAD of the gate electrode 130 where the contact plug 180 is disposed, the etching process can be easily performed during the formation of the channel structure CH and the isolation region MS. Further, the isolation region MS is formed such that the position of the lower end of the isolation region MS is maintained at substantially the same height level along the X direction.

[0033] The cell region insulating layer 190 is disposed to cover the substrate 101, the gate electrode 130, and the etching stop layer 160. In one embodiment of the present invention, the cell region insulating layer 190 may include a plurality of insulating layers. The cell region insulating layer 190 may include an insulating material such as silicon oxide or silicon nitride.

[0034] The contact plug 180 penetrates through the cell region insulating layer 190 and a part of the etching stop layer 160 from above, and is connected to the uppermost gate electrode 130 among the gate electrodes 130 forming the pad region PAD, respectively. The contact plug 180 recesses a part of the gate electrode 130 and is connected to the gate electrode 130. The contact plug 180 is connected to the wiring line 170 at the upper part. The contact plug 180 electrically connects the gate electrode 130 to the circuit elements in the peripheral circuit region. In one embodiment of the present invention, the arrangement position, number, and shape of the contact plug 180 can be variously changed. For example, the contact plug 180 can also be connected to each gate electrode 130 one by one. The contact plug 180 and the wiring line 170 may include a conductive material, and for example, may include tungsten (W), copper (Cu), aluminum (Al), or the like.

[0035] FIG. 3a is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 3b is a cross-sectional view showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 3b shows a cross-section taken along the cutting line III-III' of FIG. 3a.

[0036] Referring to FIGS. 3a and 3b, in the semiconductor device 100a, the etching stop layer 160a is separated not only by a first distance D1 along the X direction from the channel structure CH, but also by a second distance D2 along the Y direction from the isolation region MS. The second distance D2 is smaller than a third distance D3 between the isolation region MS and the contact plug 180 adjacent thereto. Specifically, the etching stop layer 160a is separated from both side surfaces along the Y direction of the isolation region MS. In the separated region, the uppermost gate electrode 130 is exposed upward from the etching stop layer 160a and contacts the cell region insulating layer 190.

[0037] In the present embodiment, a preliminary etching stop layer 160P (see FIGS. 11a and 11b) forming the etching stop layer 160a, which is formed prior to the isolation region MS, is removed in a region relatively wider than the isolation region MS including the region where the isolation region MS is formed, thereby forming the etching stop layer 160a. Thereby, the isolation region MS is stably formed within the region where the etching stop layer 160a is not formed.

[0038] FIG. 4 is a cross-sectional view showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 4 shows a region corresponding to FIG. 2a. Referring to FIG. 4, in the semiconductor device 100b, the gate electrode 130 has an end region RR with an increased thickness so as to be stably connected to the contact plug 180 in the pad region PAD. The contact plug 180 is connected to the gate electrode 130 in the end region RR of the gate electrode 130. In this case, even when the depth at which the contact plug 180 recesses the gate electrode 130 is relatively deep, it is stably connected to the gate electrode 130.

[0039] Figures 5a and 5b are cross-sectional views showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. Figure 5a shows a region corresponding to Figure 2a, and Figure 5b shows a region corresponding to Figure 2b. Referring to Figures 5a and 5b, the semiconductor device 100c further includes first and second horizontal conductive layers (102, 104) disposed between the substrate 101 and the lowermost interlayer insulating layer 120 on the upper surface of the substrate 101. Also, the semiconductor device 100c has a different structure of the channel structure CHc from the embodiment shown in FIGS. 1 to 2c, and the separation region MSc is composed of a separation insulating layer 107.

[0040] At least a part of the first and second horizontal conductive layers (102, 104) functions as a part of the common source line of the semiconductor device 100c, and can also function as a common source line together with the substrate 101. As shown in the enlarged view of Figure 5b, the first horizontal conductive layer 102 is directly connected to the channel layer 140 around the channel layer 140.

[0041] The first and second horizontal conductive layers (102, 104) can contain a semiconductor material, for example, can contain polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a doped layer, and the second horizontal conductive layer 104 may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. The channel structure CHc does not include the epitaxial layer 105 (see Figure 2a), and has a structure in which the channel layer 140 extends to the lower end and is connected to the first horizontal conductive layer 102.

[0042] Figure 6a is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention, and Figure 6b is a cross-sectional view showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. Figure 6b shows a cross-section taken along the cutting line I-I' of Figure 6a.

[0043] Referring to FIGS. 6A and 6B, the semiconductor device 100d is different from the embodiments of FIGS. 1 to 2C in the material of the gate electrode 130d and the structure of the gate dielectric layer 145d. The semiconductor device 100d further includes first and second isolation regions (MS1, MS2) that extend along the X direction through the gate electrode 130d, and further includes a dummy channel structure DCH disposed in the second region B.

[0044] The gate electrode 130d can include a metal material, for example, tungsten (W). In one embodiment of the present invention, the gate electrode 130d further includes a diffusion barrier. For example, the diffusion barrier can include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0045] The gate dielectric layer 145d includes first and second dielectric layers (145A, 145B). The first dielectric layer 145A extends horizontally along the gate electrode 130d to surround the gate electrode 130d. The second dielectric layer 145B extends perpendicularly to the upper surface of the substrate 101 along the channel structure CH.

[0046] The first and second isolation regions (MS1, MS2) are arranged parallel to each other. The first and second isolation regions (MS1, MS2) are connected to the substrate 101 through the entire gate electrode 130 stacked on the substrate 101. The first isolation region MS1 extends integrally along the first region A and the second region B, and the second isolation region MS2 is intermittently arranged in the first region A and the second region B. However, in one embodiment of the present invention, the arrangement order, number, etc. of the first and second isolation regions (MS1, MS2) can be variously changed. The first and second isolation regions (MS1, MS2) include a conductive layer 110 and an isolation insulating layer 107, like the isolation region MS in FIGS. 1 to 2C.

[0047] The dummy channel structure DCH is regularly arranged in the second region B of the substrate 101. The dummy channel structure DCH has the same internal structure as the channel structure CH and has the same or different sizes and shapes as the channel structure CH.

[0048] In the semiconductor device 100d, the etching stop layer 160 is arranged so as not to overlap with the first and second separation regions (MS1, MS2). The etching stop layer 160 is in contact with the side surfaces of the first and second separation regions (MS1, MS2) or is spaced apart from the side surfaces. In one embodiment of the present invention, when the dummy channel structure DCH is formed before the etching stop layer 160, the etching stop layer 160 is formed on the upper surface of the dummy channel structure DCH. Or, in one embodiment of the present invention, when the etching stop layer 160 is formed before the dummy channel structure DCH, the dummy channel structure DCH is arranged so as to penetrate the etching stop layer 160.

[0049] The semiconductor device 100d can be manufactured by a manufacturing method different from that of the semiconductor device 100 of FIGS. 1 to 2c, which will be described later with reference to FIGS. 10a to 15b. Specifically, first, the gate sacrificial layer is alternately laminated with the interlayer insulating layer 120, and after the gate sacrificial layer is removed through an opening formed in the region where the first and second separation regions (MS1, MS2) are arranged, the first dielectric layer 145A and the gate electrode 130d are formed. During the removal process of the gate sacrificial layer, in addition to the first separation region MS1, the second separation region MS2 is further formed in order to easily remove the gate sacrificial layer. Also, during the removal process of the gate sacrificial layer, the dummy channel structure DCH is formed in order to stably support the laminated structure of the interlayer insulating layer 120.

[0050] FIG. 7 is a cross-sectional view showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 7 shows the region corresponding to FIG. 2a. Referring to FIG. 7, in the semiconductor device 100e, the stacked structure of the gate electrode 130 includes a vertically stacked lower and upper stacked structures (ST1, ST2), and the channel structure CHe includes vertically stacked first and second channel structures (CH1, CH2). Such a structure of the channel structure CHe can be introduced to stably form the channel structure CHe when the number of relatively stacked gate electrodes 130 is large.

[0051] The channel structure CHe has a form in which the lower first channel structure CH1 and the upper second channel structure CH2 are connected, and has a bent portion due to a difference in width in the connection region. Between the first channel structure CH1 and the second channel structure CH2, the channel layer 140, the gate dielectric layer 145, and the channel insulating layer 150 are connected to each other. The channel pad 155 is disposed only at the upper end of the upper second channel structure CH2. However, in an embodiment of the present invention, the first channel structure CH1 and the second channel structure CH2 each include a channel pad 155. In this case, the channel pad 155 of the first channel structure CH1 is connected to the channel layer 140 of the second channel structure CH2.

[0052] The gate electrode 130 forms a stepped pad region PAD with a stepped structure in the lower stacked structure ST1 and the upper stacked structure ST2, respectively. The cell region insulating layer 190e includes a first insulating layer 192 covering the lower stacked structure ST1 and a second insulating layer 194 covering the upper stacked structure ST2.

[0053] The etching stop layer 160e includes a first etching stop layer 160A on the gate electrode 130 of the lower stacked structure ST1 and a second etching stop layer 160B on the gate electrode 130 of the upper stacked structure ST2. The first etching stop layer 160A and the second etching stop layer 160B are arranged to be vertically separated from each other.

[0054] FIG. 8 is a plan view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 8, in the semiconductor device 100f, the substrate 101 further has a third region C in addition to the first region A and the second region B. The third region C is located outside the second region B facing away from the first region A.

[0055] The third region C is a peripheral circuit region where circuit elements 220 electrically connected to the gate electrode 130 are arranged. Each of the circuit elements 220 includes an active region 205 and a circuit gate electrode 225. A circuit gate insulating layer is interposed between the circuit gate electrode 225 and the active region 205. In an embodiment of the present invention, the circuit elements 220 can have various sizes and arrangement forms.

[0056] The etching stop layer 160 is not arranged in the third region C and is arranged only in the region of the second region B excluding the separation region MS. Thereby, in the etching stop layer 160, the first end along the X direction is located at or adjacent to the boundary between the first region A and the second region B, and the other second end is located at or adjacent to the boundary between the second region B and the third region C. For example, the etching stop layer 160 can extend from the boundary between the first region A and the second region B to the boundary between the second region B and the third region C. In the etching stop layer 160, both ends along the Y direction are in contact with the side surface of the separation region MS or are separated from the side surface of the separation region MS.

[0057] FIG. 9 is a cross-sectional view showing a partial schematic configuration of a semiconductor device according to an embodiment of the present invention. FIG. 9 shows a region corresponding to FIG. 2a. Referring to FIG. 9, the semiconductor device 100g includes a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL is disposed at the upper end of the peripheral circuit region PERI. In one embodiment of the present invention, the cell region CELL can also be disposed at the lower end of the peripheral circuit region PERI.

[0058] The memory cell region CELL includes a substrate 101, a gate electrode 130, a channel structure CH, a separation region MS, an etching stop layer 160, and a contact plug 180, as described above with reference to FIGS. 1 to 2c. The memory cell region CELL can have a structure according to various embodiments as described above with reference to FIGS. 3a to 7. The peripheral circuit region PERI includes a base substrate 201, circuit elements 220g disposed on the base substrate 201, circuit contact plugs 270, and circuit wiring lines 280.

[0059] The base substrate 201 has an upper surface extending in the X and Y directions. A separate element isolation layer is formed on the base substrate 201 to define an active region. A source / drain region 205 containing impurities is disposed in a part of the active region. The base substrate 201 can include a semiconductor material, for example, a group-IV semiconductor, a group-III-V compound semiconductor, or a group-II-VI compound semiconductor.

[0060] The circuit elements 220g include planar transistors. Each circuit element 220g includes a circuit gate insulating layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 are disposed in the base substrate 201 on both sides of the circuit gate electrode 225.

[0061] A peripheral region insulating layer 290 is disposed on the circuit elements 220g on the base substrate 201. The circuit contact plug 270 penetrates the peripheral region insulating layer 290 and is connected to the source / drain region 205. An electrical signal is applied to the circuit element 220g via the circuit contact plug 270. In a region not shown in the figure, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit wiring line 280 is connected to the circuit contact plug 270 and is arranged in a plurality of layers. The gate electrode 130 of the memory cell region CELL is connected to the circuit element 220g in the peripheral circuit region PERI via a separate through region that penetrates the peripheral circuit region PERI and a through via in the through region in a region not shown in the figure.

[0062] In the semiconductor device 100g, after the peripheral circuit region PERI is first manufactured, the substrate 101 of the memory cell region CELL is formed on top of it, and the memory cell region CELL is manufactured. The substrate 101 can have the same size as the base substrate 201 or can be formed smaller than the base substrate 201.

[0063] Figs. 10a to 15b are schematic plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figs. 10a and 10b, the gate electrode 130 and the interlayer insulating layer 120 are alternately laminated on the substrate 101, and a top separation region SS is formed by removing a part of the gate electrode 130 and the interlayer insulating layer 120 so that the gate electrodes 130 extend in different lengths in the X direction.

[0064] The gate electrode 130 and the interlayer insulating layer 120 are alternately deposited by a deposition process to form a stacked structure GS. In an embodiment of the present invention, the thicknesses of the interlayer insulating layers 120 of the stacked structure GS may not all be the same. For example, the lowermost interlayer insulating layer 120 may be formed relatively thin, and the uppermost interlayer insulating layer 120 may be formed relatively thick. The thicknesses of the interlayer insulating layer 120 and the gate electrode 130 and the number of films constituting them can be variously changed from those shown in the figures.

[0065] In the second region B of the substrate 101, the photolithography process and the etching process for the gate electrode 130 are repeatedly performed so that the upper gate electrode 130 extends shorter than the lower gate electrode 130. As a result, the gate electrode 130 forms a stepped pad region PAD. In one embodiment of the present invention, the gate electrode 130 can have a stepped shape only in the X direction or in both the X and Y directions. In the case of the embodiment of FIG. 4, a substance forming the gate electrode 130 is further vapor-deposited on the region where the gate electrode 130 extends longer and is exposed than the upper gate electrode 130, so that the gate electrode 130 has a relatively thick thickness in the end region RR.

[0066] The upper isolation region SS is formed by exposing the region where the upper isolation region SS is formed using a separate mask layer and removing a predetermined number of gate electrodes 130 and interlayer insulating layers 120 from the uppermost part. The upper isolation region SS extends below the upper gate electrode 130U, as shown in FIG. 2b. An insulating substance is vapor-deposited on the region where the gate electrode 130 and the interlayer insulating layer 120 are removed to form the upper insulating layer 103. The upper insulating layer 103 can be made of, for example, the same substance as the interlayer insulating layer 120.

[0067] Referring to FIGS. 11a and 11b, a preliminary etching stop layer 160P covering the stacked structure GS is formed. The preliminary etching stop layer 160P is formed over the entire substrate 101. The preliminary etching stop layer 160P is formed so as to cover the upper surface of the uppermost gate electrode 130 in the stacked structure GS.

[0068] The preliminary etching stop layer 160P covers the side surfaces of the gate electrode 130 and the interlayer insulating layer 120 along the profile of the gate electrode 130 in the pad region PAD and is formed in a stepped shape. The preliminary etching stop layer 160P is formed to cover the upper separation region SS in addition to the upper surface of the gate electrode 130 in the first region A of the substrate 101.

[0069] The preliminary etching stop layer 160P contains a substance different from the gate electrode 130 and the cell region insulating layer 190 (see FIG. 2a) formed subsequently. The preliminary etching stop layer 160P is made of a substance having an etching selectivity with respect to the gate electrode 130 and the cell region insulating layer 190. For example, the gate electrode 130 contains polycrystalline silicon, the cell region insulating layer 190 contains silicon oxide or silicon nitride, and the preliminary etching stop layer 160P contains a metal oxide. When the preliminary etching stop layer 160P contains a metal oxide, it can be easily removed through wet etching under specific etching conditions, and may not be easily removed by dry etching under specific etching conditions.

[0070] Referring to FIGS. 12a and 12b, the preliminary etching stop layer 160P is patterned to form the etching stop layer 160. The preliminary etching stop layer 160P is patterned through a photolithography process and a photomask layer thereby.

[0071] The preliminary etching stop layer 160P is removed in the region where the separation region MS (see FIG. 1) is formed in the first region A and the second region B. The removal process is performed, for example, through a wet etching process. Thereby, the etching stop layer 160 remains only in the region excluding the region where the separation region MS is formed in the second region B. In the case of the embodiments of FIGS. 3A and 3B, at this stage, the etching stop layer 160a is formed by removing the preliminary etching stop layer 160P in a region wider than the region where the separation region MS is formed, including the region where the separation region MS is formed.

[0072] In one embodiment of the present invention, a heat treatment step for the etching stop layer 160 is further performed. By the heat treatment step, the etching stop layer 160 can be hardened to have the characteristics of a relatively hard film.

[0073] Referring to FIGS. 13A and 13B, a channel structure CH penetrating the stacked structure GS is formed. First, a cell region insulating layer 190 covering the upper part of the stacked structure GS is formed.

[0074] The channel structure CH is formed by anisotropically etching the gate electrode 130 and the interlayer insulating layer 120 to form a channel hole in the shape of a hole and then filling it. Due to the height of the stacked structure GS, the sidewalls of the channel structure CH are not perpendicular to the upper surface of the substrate 101. The channel structure CH is formed so as to recess a part of the substrate 101. Since the channel hole is formed in a region where the etching stop layer 160 is not disposed, the forming process can be easily performed.

[0075] Next, an epitaxial layer 105, a gate dielectric layer 145, a channel layer 140, a channel insulating layer 150, and a channel pad 155 are sequentially formed in the channel hole. The epitaxial layer 105 is formed using a selective epitaxial growth (SEG) process. The epitaxial layer 105 can be composed of a single layer or a plurality of layers. The epitaxial layer 105 can include doped or undoped polycrystalline silicon, single-crystalline silicon, polycrystalline germanium, or single-crystalline germanium.

[0076] The gate dielectric layer 145 is formed to have a uniform thickness using Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The channel layer 140 is formed on the gate dielectric layer 145 within the channel structure CH. The channel insulating layer 150 is formed to fill the channel structure CH and can be an insulating material. However, depending on the embodiment, the space between the channel layers 140 can also be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 can be made of a conductive material, for example, it can be made of polycrystalline silicon.

[0077] Referring to FIGS. 14a and 14b, a separation region MS is formed through the stacked structure GS. First, a mask layer is formed using a photolithography process, and the stacked structure GS is anisotropically etched to form an opening in the region where the separation region MS is to be formed. Before forming the opening, a cell region insulating layer 190 is further formed on the channel structure CH for protecting the lower structure. Next, a conductive layer 110 and a separation insulating layer 107 are formed in the opening to form the separation region MS.

[0078] In this stage, since the etching stop layer 160 is not disposed in the region where the separation region MS is formed, the opening formation process can be easily performed. Specifically, since the gate electrodes 130 in the second region B form the pad region PAD, the uppermost gate electrodes 130 are located at different heights from each other. Thus, it is necessary to etch the stacked structure GS including the gate electrodes 130 arranged at different heights from each other to form openings. However, also in this case, since the etching stop layer 160 that acts as a barrier for the etching process is not arranged in the region where the separation region MS is formed, the position of the lower end of the opening is formed substantially constant along the X direction.

[0079] Referring to FIGS. 15a and 15b, contact holes PH are formed to expose the gate electrodes 130 that form the pad region PAD through the cell region insulating layer 190. The step of forming the contact holes PH is performed using a two-step etching process. In the first etching step, the contact holes PH are extended from above to penetrate the cell region insulating layer 190 so that the etching stop layer 160 is exposed.

[0080] The contact holes PH are formed by partially recessing the etching stop layer 160. The first etching step is performed, for example, through a dry etching process. In the second etching step, the etching stop layer 160 exposed by the contact holes PH is removed, and the uppermost gate electrode 130 is exposed at the lower part. The contact holes PH are formed by partially recessing the gate electrodes 130. The second etching step is performed, for example, through a wet etching process, and the etching stop layer 160 is selectively removed.

[0081] In this stage, since the etching stop layer 160 is arranged on the uppermost gate electrode 130, contact holes PH having different depths from each other can be simultaneously formed in the pad region PAD with the minimum number of times, for example, by one photolithography process. Next, referring again to FIGS. 1 to 2c, contact plugs 180 and wiring lines 170 are formed. First, the contact holes PH are filled with a conductive material to form the contact plugs 180. Thereafter, a wiring line 170 connected to the contact plug 180 is formed.

[0082] Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical scope of the present invention.

Explanation of Reference Numerals

[0083] 100 Semiconductor device 101 Substrate 102 First horizontal conductive layer 103 Upper insulating layer 104 Second horizontal conductive layer 105 Epitaxial layer 107 Isolation insulating layer 110 Conductive layer 120 Interlayer insulating layer 130 Gate electrode 130L Lower gate electrode 130M Memory cell gate electrode 130U Upper gate electrode 140 Channel layer 145 Gate dielectric layer 150 Channel insulating layer 155 Channel pad 160 Etching stop layer 170 Wiring line 180 Contact plug 190 Cell region insulating layer CH Channel structure GS Stacked structure MS Separation region SS Upper separation region PAD Pad region RR End region

Claims

1. A substrate having a first region and a second region, A plurality of gate electrodes stacked at intervals along a first direction in the first region and extending to different lengths along a second direction in the second region to form a stepped pad region, An interlayer insulating layer arranged alternately with the gate electrodes, In the first region, a channel structure including a channel layer arranged to penetrate the gate electrode and extending along the first direction, A separation region arranged to penetrate the gate electrode in the first region and the second region and extending in the second direction, An etching stop layer arranged on the gate electrode forming the pad region in the second region so as not to overlap with the first region and the separation region, A cell region insulating layer covering the gate electrode and the etching stop layer, In the second region, a contact plug arranged to penetrate the cell region insulating layer and the etching stop layer from above and connected to the gate electrode in the pad region, The etching stop layer extends in contact with the upper surface of the uppermost gate electrode among the gate electrodes to the upper surface of the gate electrode forming the pad region, A semiconductor device, characterized in that both ends of the etching stop layer are spaced apart from the side surface of the separation region.

2. The semiconductor device according to claim 1, wherein the etching stop layer is spaced apart from the side surface of the channel structure.

3. The semiconductor device according to claim 1, wherein the etching stop layer is spaced apart from the side surface of the separation region in a third direction perpendicular to the first direction and the second direction.

4. The semiconductor device according to claim 1, wherein the etching stop layer extends continuously in a stepped manner along the pad region.

5. The semiconductor device according to claim 1, wherein the etching stop layer contains a metal oxide.

6. The semiconductor device according to claim 1, wherein the gate electrode contains a semiconductor material.

7. The semiconductor device according to claim 1, wherein the gate electrode contains a metal.

8. The semiconductor device according to claim 7, further comprising a dummy channel structure arranged to penetrate the gate electrode in the second region and extending along the first direction and including the channel layer.

9. The semiconductor device according to claim 1, wherein the isolation region includes a conductive layer and an isolation insulating layer disposed between the conductive layer and the gate electrode.

10. The semiconductor device according to claim 1, further comprising at least one horizontal conductive layer disposed horizontally below the gate electrode and the interlayer insulating layer on the substrate and in direct contact with the channel layer.

11. The semiconductor device according to claim 1, wherein one end of the etching stop layer is in contact with the upper surface of the substrate.

12. The gate electrode and the interlayer insulating layer form a first stacked structure and a second stacked structure stacked along the first direction, The semiconductor device according to claim 1, wherein the etching stop layer includes a first etching stop layer and a second etching stop layer disposed on the respective upper portions of the first stacked structure and the second stacked structure in the pad region.

13. The substrate further has a third region located outside the second region where circuit elements are disposed, The semiconductor device according to claim 1, wherein the etching stop layer extends from the boundary between the first region and the second region to the boundary between the second region and the third region.

14. A plurality of gate electrodes stacked at intervals along a first direction perpendicular to the upper surface of the substrate and forming a stepped pad region extending in different lengths along a second direction; An isolation region disposed to penetrate the gate electrode and extending in the second direction; An etching stop layer disposed on the gate electrode forming the pad region; A contact plug disposed to penetrate the etching stop layer and connected to the gate electrode in the pad region, and The etching stop layer extends in contact with the upper surface of the gate electrode forming the pad region from the upper surface of the uppermost gate electrode among the gate electrodes, The semiconductor device, wherein the etching stop layer is spaced apart from the side surface of the isolation region.

15. The semiconductor device according to claim 14, further comprising a channel structure disposed to penetrate the gate electrode and extending along the first direction and including a channel layer.

16. The substrate has a first region and a second region located on at least one side of the first region, The semiconductor device according to claim 15, wherein the channel structure is disposed in the first region and the etching stop layer is disposed in a part of the second region.

17. The semiconductor device according to claim 14, further comprising a base substrate disposed apart from the substrate along the first direction and providing circuit elements.

18. A substrate having a first region and a second region, a plurality of gate electrodes stacked apart from each other along a first direction in the first region and extending to different lengths along a second direction in the second region to form a stepped pad region, a channel structure disposed to penetrate the gate electrode in the first region, extending along the first direction and including a channel layer, a separation region disposed to penetrate the gate electrode in the first region and the second region and extending in the second direction, an etching stop layer disposed on the gate electrode forming the pad region in the second region, and a contact plug disposed to penetrate the etching stop layer and connected to the gate electrode in the pad region. The etching stop layer extends in contact with the upper surface of the gate electrode forming the pad region from the upper surface of the uppermost gate electrode among the gate electrodes. In the etching stop layer, a first end along the second direction is located at a boundary between the first region and the second region, and both ends along a third direction orthogonal to the first direction and the second direction are located apart from the separation region. A semiconductor device characterized by this.

19. The semiconductor device according to claim 18, wherein a second end of the etching stop layer facing the first end along the second direction is located on the upper surface of the substrate.

20. The semiconductor device according to claim 18, wherein the etching stop layer has a rectangular shape in a plan view.

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