Multilayer electronic component

Abstract

To provide a multilayer electronic component that can be downsized with an increased Q value of each inductor.SOLUTION: An electronic component 1 includes a stack 50 and inductors L11, L12, L21, and L22. The inductor L12 is disposed after the inductor L11 in a -Y direction. The inductor L21 and the inductor L22 are respectively disposed after the inductor L11 and the inductor L12 in a -X direction. Two or more through hole columns are connected in parallel to a part near each end of a conductor layer portion in each of the inductor L11 and the inductor L22 in a longitudinal direction. One through hole column is connected to a part near each end of a conductor layer portion in each of the inductor L12 and the inductor L21 in a longitudinal direction.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present invention relates to a multilayer electronic component including a plurality of inductors.

Background Art

[0002] In small mobile communication devices, a configuration is widely used in which an antenna commonly used in a plurality of applications having different systems and operating frequency bands is provided, and a plurality of signals transmitted and received by this antenna are separated using a diplexer.

[0003] Generally, a diplexer that separates a first signal having a frequency within a first frequency band and a second signal having a frequency within a second frequency band higher than the first frequency band includes a common port, a first signal port, a second signal port, a first filter provided in a first signal path from the common port to the first signal port, and a second filter provided in a second signal path from the common port to the second signal port. As the first and second filters, for example, an LC resonator configured using an inductor and a capacitor is used.

[0004] As a diplexer, as disclosed in Patent Document 1, a diplexer using a laminate including a plurality of laminated dielectric layers is known. Further, as an inductor used in an LC resonator, as disclosed in Patent Document 1, an inductor in which via hole conductors are connected to both ends of a conductor layer, or as disclosed in Patent Document 2 an inductor in which one or two via hole conductors are connected to both ends of a conductor layer is known.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] In recent years, miniaturization and space saving of small mobile communication devices have been demanded by the market, and miniaturization of a diplexer used in such communication devices has also been required. When an inductor is miniaturized along with the miniaturization of the diplexer, the Q value of the inductor may become small. On the other hand, in Patent Document 2, the Q value of the inductor is increased by connecting a plurality of via hole conductors to one end of a conductor layer. However, when a plurality of via hole conductors are connected to one end of all the inductors included in the diplexer like the inductor described in Patent Document 2, Waveguide the diplexer becomes large-sized.

[0007] The above problem is not limited to the diplexer, but applies to all multilayer electronic components including a plurality of inductors.

[0008] The present invention has been made in view of such problems, and an object thereof is to provide a multilayer electronic component that can be miniaturized while increasing the Q value of an inductor.

Means for Solving the Problems

[0009] The multilayer electronic component of the present invention includes a laminate including a plurality of stacked dielectric layers, a first inductor integrated with the laminate and wound around a first axis orthogonal to the stacking direction of the plurality of dielectric layers, a second inductor integrated with the laminate and wound around a second axis orthogonal to the stacking direction, a third inductor integrated with the laminate and wound around a third axis orthogonal to the stacking direction, and a fourth inductor integrated with the laminate and wound around a fourth axis orthogonal to the stacking direction. The second inductor is disposed ahead of the first inductor in a first direction orthogonal to the stacking direction. The third inductor and the fourth inductor are each disposed ahead of the first inductor and the second inductor in a second direction orthogonal to the stacking direction and the first direction.

[0010] Each of the first inductor and the fourth inductor includes a plurality of first through-hole rows and at least one first conductor layer portion. Each of the second inductor and the third inductor includes a plurality of second through-hole rows and at least one second conductor layer portion. Each of the plurality of first through-hole rows and the plurality of second through-hole rows is formed by connecting two or more through-holes in series. Each of the at least one first conductor layer portion and the at least one second conductor layer portion includes at least one conductor layer. In portions near both longitudinal ends of the at least one first conductor layer portion, two or more of the plurality of first through-hole rows are connected in parallel. In portions near both longitudinal ends of the at least one second conductor layer portion, one of the plurality of second through-hole rows is connected respectively.

[0011] In the multilayer electronic component of the present invention, the first axis and the fourth axis may be parallel to each other.

[0012] Also, in the multilayer electronic component of the present invention, the direction parallel to the second axis and the direction parallel to the fourth axis may be perpendicular to each other.

[0013] Also, in the multilayer electronic component of the present invention, the first inductor may include one conductor portion wound less than once around the first axis. Also, the fourth inductor may include a plurality of first conductor portions each wound less than once around the fourth axis and at least one first connection portion connecting the plurality of first conductor portions in series.

[0014] Also, in the multilayer electronic component of the present invention, the second inductor may include a plurality of second conductor portions each wound less than once around the second axis and at least one second connection portion connecting the plurality of second conductor portions in series.

[0015] Also, in the multilayer electronic component of the present invention, the third axis and the fourth axis may be parallel to each other. In this case, the area of the region obtained by vertically projecting the first space including the third axis and surrounded by the third inductor onto a virtual plane perpendicular to the third axis may be larger than the area of the region obtained by vertically projecting the second space including the fourth axis and surrounded by the fourth inductor onto a virtual plane perpendicular to the fourth axis.

[0016] Further, the multilayer electronic component of the present invention may further include a common port, a first signal port, a second signal port, a first inductor, and a second inductor, and is provided between the common port and the first signal port and selectively passes a first signal having a frequency within a first passband. A first filter, including a third inductor and a fourth inductor, provided between the common port and the second signal port, and selectively passing a second signal having a frequency within a second passband. A second filter. In this case, the first inductor may be provided at a position closer to the first signal port than the second inductor in terms of circuit configuration. Also, in the pass attenuation characteristic of the first filter, the attenuation pole formed by the first inductor may be closer to the first passband than the attenuation pole formed by the second inductor. Also, in this case, the fourth inductor may be provided at a position closer to the common port than the third inductor in terms of circuit configuration. Also, in the pass attenuation characteristic of the second filter, the attenuation pole formed by the fourth inductor may be closer to the second passband than the attenuation pole formed by the third inductor.

Advantages of the Invention

[0017] In the laminated electronic component of the present invention, the second inductor is disposed ahead of the first inductor in the first direction. The third inductor and the fourth inductor are each disposed ahead of the first inductor and the second inductor in the second direction. Further, in the present invention, two or more first through-hole rows are connected in parallel to portions near both longitudinal ends of the first conductor layer portion in each of the first inductor and the fourth inductor. One second through-hole row is connected to portions near both longitudinal ends of the second conductor layer portion in each of the second inductor and the third inductor. Thus, according to the present invention, there is an effect that the laminated electronic component can be miniaturized while increasing the Q value of the inductor.

Brief Description of the Drawings

[0018]

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Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, referring to FIG. 1, an outline of the configuration of a stacked electronic component (hereinafter simply referred to as an electronic component) 1 according to an embodiment of the present invention will be described. FIG. 1 shows a diplexer as an example of the electronic component 1. The diplexer includes a first filter 10 that selectively passes a first signal having a frequency within a first passband, and a second filter 20 that selectively passes a second signal having a frequency within a second passband higher than the first passband.

[0020] The electronic component 1 further includes a common port 2, a first signal port 3, a second signal port 4, a first signal path 5 connecting the common port 2 and the first signal port 3, and a second signal path 6 connecting the common port 2 and the second signal port 4. The first filter 10 is provided between the common port 2 and the first signal port 3 in terms of circuit configuration. The second filter 20 is provided between the common port 2 and the second signal port 4 in terms of circuit configuration. The first signal path 5 is a path from the common port 2 through the first filter 10 to the first signal port 3. The second signal path 6 is a path from the common port 2 through the second filter 20 to the second signal port 4.

[0021] The first signal having a frequency within the first passband selectively passes through the first signal path 5 provided with the first filter 10. The second signal having a frequency within the second passband selectively passes through the second signal path 6 provided with the second filter 20. In this way, the electronic component 1 separates the first signal and the second signal.

[0022] Next, with reference to FIG. 1, an example of the configuration of the first filter 10 will be described. The first filter 10 includes inductors L11, L12, L13 and capacitors C11, C12, C13, C14, C15, C16. The inductors L11, L12 are provided on the first signal path 5 in terms of circuit configuration. Also, the inductor L11 is provided at a position closer to the first signal port 3 than the inductor L12 in terms of circuit configuration. One end of the inductor L11 is connected to the first signal port 3. The other end of the inductor L11 is connected to one end of the inductor L12. The other end of the inductor L12 is connected to the common port 2.

[0023] The capacitor C11 is connected in parallel to the inductor L11. The capacitor C12 is connected in parallel to the inductor L12. One end of the capacitor C13 is connected to one end of the inductor L11. The other end of the capacitor C13 is connected to the other end of the inductor L12.

[0024] One end of the capacitor C14 is connected to one end of the inductor L11. One end of the capacitor C15 is connected to the connection point between the inductor L11 and the inductor L12. The other ends of the capacitors C14, C15 are connected to one end of the inductor L13. The other end of the inductor L13 is connected to the ground. The capacitor C16 is connected in parallel to the inductor L13. The inductor L13 is provided between the first signal path 5 and the ground in terms of circuit configuration.

[0025] Next, with reference to FIG. 2, an example of the configuration of the second filter 20 will be described. The second filter 20 includes inductors L21, L22 and capacitors C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31. One end of the capacitor C21 is connected to the second signal port 4. The other end of the capacitor C21 is connected to one end of the capacitor C22. The other end of the capacitor C22 is connected to one end of the capacitor C23. The other end of the capacitor C23 is connected to the common port 2.

[0026] One end of capacitor C24 is connected to one end of capacitor C21. The other end of capacitor C24 is connected to the other end of capacitor C22. One end of capacitor C25 is connected to the connection point between capacitor C22 and capacitor C23.

[0027] Inductor L21 is provided between the second signal path 6 and the ground in terms of circuit configuration. Inductor L21 includes inductor portions 211 and 212. One end of inductor portion 211 is connected to the connection point between capacitor C21 and capacitor C22. The other end of inductor portion 211 is connected to one end of inductor portion 212. The other end of inductor portion 212 is connected to the ground.

[0028] Inductor L22 is provided between the second signal path 6 and the ground in terms of circuit configuration. Also, inductor L22 is provided at a position closer to common port 2 than inductor L21 in terms of circuit configuration. Inductor L22 includes inductor portions 221 and 222. One end of inductor portion 221 is connected to the other end of capacitor C25. The other end of inductor portion 221 is connected to one end of inductor portion 222. The other end of inductor portion 222 is connected to the ground.

[0029] The inductor portion 211 of inductor L21 and the inductor portion 221 of inductor L22 are magnetically coupled to each other. The inductor portion 212 of inductor L21 and the inductor portion 222 of inductor L22 are not magnetically coupled to each other.

[0030] Capacitor C26 is connected in parallel to the inductor portion 211 of inductor L21. Capacitor C27 is connected in parallel to the inductor portion 212 of inductor L21. One end of capacitor C28 is connected to one end of the inductor portion 211. The other end of capacitor C28 is connected to the other end of the inductor portion 212.

[0031] Capacitor C29 is connected in parallel to the inductor portion 221 of inductor L22. Capacitor C30 is connected in parallel to the inductor portion 222 of inductor L22. One end of capacitor C31 is connected to one end of the inductor portion 221. The other end of capacitor C31 is connected to the other end of the inductor portion 222.

[0032] Next, with reference to FIG. 3, other configurations of the electronic component 1 will be described. FIG. 3 is a perspective view showing the appearance of the electronic component 1.

[0033] The electronic component 1 further includes a laminate 50 including a plurality of stacked dielectric layers and a plurality of conductors. The laminate 50 is for integrating the common port 2, the first signal port 3, the second signal port 4, inductors L11, L12, L13, L21, L22 and capacitors C11 to C16, C21 to C31. The first filter 10 and the second filter 20 are each configured using a plurality of conductors.

[0034] The laminate 50 has a bottom surface 50A and an upper surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the bottom surface 50A and the upper surface 50B. The side surfaces 50C and 50D face opposite sides, and the side surfaces 50E and 50F also face opposite sides. The side surfaces 50C to 50F are perpendicular to the upper surface 50B and the bottom surface 50A.

[0035] Here, as shown in FIG. 3, the X direction, the Y direction, and the Z direction are defined. The X direction, the Y direction, and the Z direction are perpendicular to each other. In the present embodiment, one direction parallel to the stacking direction T is defined as the Z direction. Also, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction.

[0036] As shown in FIG. 3, the bottom surface 50A is located at the -Z direction end of the laminate 50. The upper surface 50B is located at the Z direction end of the laminate 50. The shape of each of the bottom surface 50A and the upper surface 50B is a rectangular shape that is long in the X direction. The side surface 50C is located at the -X direction end of the laminate 50. The side surface 50D is located at the X direction end of the laminate 50. The side surface 50E is located at the -Y direction end of the laminate 50. The side surface 50F is located at the Y direction end of the laminate 50.

[0037] The planar shape of the laminate 50 when viewed from the Z direction, that is, the shape of the bottom surface 50A (the shape of the upper surface 50B), is rectangular. The long side of this rectangle is parallel to the X direction, and the short side of this rectangle is parallel to the Y direction.

[0038] The electronic component 1 further includes signal terminals 112, 113, 114 provided on the bottom surface 50A of the laminate 50, and ground terminals 111, 115, 116, 117, 118, 119 connected to the ground. The ground terminal 111 is disposed in the vicinity of the corner where the bottom surface 50A, the side surface 50D, and the side surface 50E intersect. The signal terminal 113 is disposed in the vicinity of the corner where the bottom surface 50A, the side surface 50D, and the side surface 50F intersect. The signal terminal 114 is disposed in the vicinity of the corner where the bottom surface 50A, the side surface 50C, and the side surface 50F intersect. The ground terminal 115 is disposed in the vicinity of the corner where the bottom surface 50A, the side surface 50C, and the side surface 50E intersect.

[0039] The signal terminal 112 is disposed between the ground terminal 111 and the ground terminal 115. The ground terminal 116 is disposed between the ground terminal 111 and the signal terminal 113. The ground terminal 117 is disposed between the signal terminal 113 and the signal terminal 114. The ground terminal 118 is disposed between the signal terminal 114 and the ground terminal 115. The ground terminal 119 is disposed at the center of the bottom surface 50A.

[0040] The signal terminal 112 corresponds to the common port 2, the signal terminal 113 corresponds to the first signal port 3, and the signal terminal 114 corresponds to the second signal port 4. Therefore, the common port 2, the first signal port 3, and the second signal port 4 are provided on the bottom surface 50A of the laminate 50.

[0041] Next, with reference to FIGS. 4(a) to 9(b), an example of a plurality of dielectric layers and a plurality of conductors constituting the laminate 50 will be described. In this example, the laminate 50 has 24 dielectric layers laminated thereon. Hereinafter, these 24 dielectric layers will be referred to as the first to 24th dielectric layers in order from the bottom. Also, the first to 24th dielectric layers are denoted by reference numerals 51 to 74.

[0042] In FIGS. 4(a) to 8(c), a plurality of circles represent a plurality of through holes. A plurality of through holes are formed in each of the dielectric layers 51 to 72. The plurality of through holes are each formed by filling a hole for a through hole with a conductive paste. Each of the plurality of through holes is connected to a conductive layer or another through hole.

[0043] FIG. 4(a) shows the pattern formation surface of the first dielectric layer 51. Terminals 111 to 119 are formed on the pattern formation surface of the dielectric layer 51. FIG. 4(b) shows the pattern formation surface of the second dielectric layer 52. Conductive layers 521, 522, 523, 524, 525 are formed on the pattern formation surface of the dielectric layer 52.

[0044] FIG. 4(c) shows the pattern formation surface of the third dielectric layer 53. Conductive layers 531, 532, 533, 534, 535, 536, 537, 538, 539, 5310, 5311, 5312 are formed on the pattern formation surface of the dielectric layer 53. One end of the conductive layer 531 is connected to the conductive layer 5311. The other end of the conductive layer 531 is connected to the conductive layer 5312. In FIG. 4(c), the boundaries between the conductive layer 531 and the conductive layer 5311 and between the conductive layer 531 and the conductive layer 5312 are indicated by dotted lines.

[0045] Fig. 5(a) shows the pattern formation surface of the fourth dielectric layer 54. On the pattern formation surface of the dielectric layer 54, conductor layers 541, 542, 543, 544, 545, 546, 547, and 548 are formed. The conductor layers 541 and 543 are connected to the conductor layer 542. Fig. 5(b) shows the pattern formation surface of the fifth dielectric layer 55. On the pattern formation surface of the dielectric layer 55, conductor layers 551, 552, 553, and 554 are formed. The conductor layer 554 is connected to the conductor layer 553. Fig. 5(c) shows the pattern formation surface of the sixth dielectric layer 56. On the pattern formation surface of the dielectric layer 56, conductor layers 561 and 562 are formed.

[0046] Fig. 6(a) shows the pattern formation surface of the seventh dielectric layer 57. On the pattern formation surface of the dielectric layer 57, conductor layers 571 and 572 are formed. The conductor layer 572 is connected to the conductor layer 571. Fig. 6(b) shows the pattern formation surface of the eighth dielectric layer 58. No conductor layer is formed on the pattern formation surface of the dielectric layer 58. Fig. 6(c) shows the pattern formation surface of the ninth dielectric layer 59. On the pattern formation surface of the dielectric layer 59, a conductor layer 591 is formed.

[0047] Fig. 7(a) shows the pattern formation surface of the tenth dielectric layer 60. On the pattern formation surface of the dielectric layer 60, a conductor layer 601 is formed. Fig. 7(b) shows the pattern formation surface of the eleventh dielectric layer 61. No conductor layer is formed on the pattern formation surface of the dielectric layer 61. Fig. 7(c) shows the pattern formation surface of the twelfth dielectric layer 62. On the pattern formation surface of the dielectric layer 62, conductor layers 621 and 622 are formed. The shapes of the conductor layers 621 and 622 may be the same when viewed from a direction (Z direction) parallel to the stacking direction T.

[0048] FIG. 8(a) shows the pattern formation surface of the 13th dielectric layer 63. Conductor layers 631 and 632 are formed on the pattern formation surface of the dielectric layer 63. The shapes of the conductor layers 631 and 632 when viewed from a direction (Z direction) parallel to the stacking direction T may be the same. FIG. 8(b) shows the pattern formation surfaces of the 14th to 21st dielectric layers 64 to 71. No conductor layer is formed in the dielectric layers 64 to 71. FIG. 8(c) shows the pattern formation surface of the 22nd dielectric layer 72. Conductor layers 721, 722, 723, 724, 725, 726, and 727 are formed on the pattern formation surface of the dielectric layer 72. The shapes of the conductor layers 722, 723, and 724 when viewed from a direction (Z direction) parallel to the stacking direction T may be the same. The shapes of the conductor layers 726 and 727 when viewed from a direction (Z direction) parallel to the stacking direction T may be the same.

[0049] FIG. 9(a) shows the pattern formation surface of the 23rd dielectric layer 73. Conductor layers 731, 732, 733, 734, 735, 736, and 737 are formed on the pattern formation surface of the dielectric layer 73. The shapes of the conductor layers 732, 733, and 734 when viewed from a direction (Z direction) parallel to the stacking direction T may be the same. The shapes of the conductor layers 736 and 737 when viewed from a direction (Z direction) parallel to the stacking direction T may be the same. FIG. 9(b) shows the pattern formation surface of the 24th dielectric layer 74. A mark 741 made of a conductor layer is formed on the pattern formation surface of the dielectric layer 74.

[0050] In the laminate 50 shown in FIG. 2, the 1st to 24th dielectric layers 51 to 74 are stacked such that the pattern formation surface of the 1st dielectric layer 51 becomes the bottom surface 50A of the laminate 50, and the surface on the opposite side of the pattern formation surface of the 24th dielectric layer 74 becomes the top surface 50B of the laminate 50.

[0051] Each of the plurality of through-holes shown in FIGS. 4(a) to 8(c) is connected to a conductor layer overlapping in the stacking direction T or another through-hole overlapping in the stacking direction T when the dielectric layers 51 to 72 of the first layer to the twenty-second layer are stacked. Further, among the plurality of through-holes shown in FIGS. 4(a) to 8(c), the through-holes located within the terminal or within the conductor layer are connected to that terminal or that conductor layer.

[0052] FIGS. 10 and 11 show the inside of a stacked body 50 formed by stacking dielectric layers 51 to 74 of the first layer to the twenty-fourth layer. As shown in FIGS. 10 and 11, inside the stacked body 50, a plurality of conductor layers and a plurality of through-holes shown in FIGS. 4(a) to 9(a) are stacked. Note that in FIGS. 10 and 11, the mark 741 is omitted.

[0053] The stacked body 50 is manufactured, for example, by a low-temperature co-firing method using ceramics as the materials of the dielectric layers 51 to 74. In this case, first, a plurality of ceramic green sheets that will later become the dielectric layers 51 to 74 are manufactured. A plurality of pre-firing conductor layers that will later become a plurality of conductor layers and a plurality of pre-firing through-holes that will later become a plurality of through-holes are formed in each ceramic green sheet. Next, the plurality of ceramic green sheets are stacked to manufacture a green sheet stacked body. Next, this green sheet stacked body is cut to manufacture a pre-firing stacked body. Next, the ceramics and conductors in this pre-firing stacked body are fired by a low-temperature co-firing process to complete the stacked body 50.

[0054] Next, with reference to FIGS. 4(a) to 15, the configurations of inductors L11, L12, L13, L21, and L22 will be described in detail. FIGS. 12 to 15 are side views showing a part inside the laminate 50. FIG. 12 shows a part inside the laminate 50 as viewed from the side 50D side, mainly showing inductors L11, L12, and L13. FIG. 13 shows a part inside the laminate 50 as viewed from the side 50E side, mainly showing inductors L12, L13, and L22. FIG. 14 shows a part inside the laminate 50 as viewed from the side 50C side, mainly showing inductors L21 and L22. FIG. 15 shows a part inside the laminate 50 as viewed from the side 50F side, mainly showing inductors L11 and L21.

[0055] Inductors L11, L12, L13, L21, and L22 are each integrated with the laminate 50. As will be described later, each of inductors L11, L12, L21, and L22 includes a plurality of through-hole rows. Each of the plurality of through-hole rows is configured by connecting two or more through-hole rows arranged in the stacking direction T in series.

[0056] First, the configuration of inductor L11 will be described. As shown in FIGS. 12 and 15, inductor L11 is wound around an axis A11 in a direction orthogonal to the stacking direction T. Parallel In particular, in the present embodiment, axis A11 extends in a direction parallel to the Y direction.

[0057] Also, inductor L11 includes one conductor portion wound less than once around axis A11. The conductor portion of inductor L11 includes a conductor layer portion 11C1 (see FIGS. 10 and 11). Conductor layer portion 11C1 has a shape that is long in a direction parallel to the X direction. Conductor layer portion 11C1 includes conductor layers 721 and 731 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through-holes. Each of conductor layers 721 and 731 extends in a direction parallel to the X direction.

[0058] The conductor portion of inductor L11 further includes two through-hole rows 11T1 and two through-hole rows 11T2 (see FIGS. 10 and 11). Near one end in the longitudinal direction of the conductor layer portion 11C1, the two through-hole rows 11T1 are connected in parallel. Near the other end in the longitudinal direction of the conductor layer portion 11C1, the two through-hole rows 11T2 are connected in parallel.

[0059] Next, the configuration of inductor L12 will be described. As shown in FIGS. 12 and 13, inductor L12 is wound around an axis A12 parallel to the direction orthogonal to the stacking direction T. In particular, in this embodiment, axis A12 extends in a direction parallel to the X direction. Further, inductor L12 includes conductor portions L12A, L12B, L12C each wound less than once around axis A12, a connection portion L12D connecting conductor portions L12A and L12B in series, and a connection portion L12E connecting conductor portions L12B and L12C in series.

[0060] Conductor portions L12A, L12B, L12C each include conductor layer portions 12C1, 12C2, 12C3 (see FIGS. 10 and 11). Each of the conductor layer portions 12C1, 12C2, 12C3 has a shape long in a direction parallel to the Y direction.

[0061] Conductor layer portion 12C1 includes conductor layers 722, 732 (see FIGS. 8(c) and 9(a)) arranged at different positions in the stacking direction T and connected in parallel by two through-holes. Conductor layer portion 12C2 includes conductor layers 723, 733 (see FIGS. 8(c) and 9(a)) arranged at different positions in the stacking direction T and connected in parallel by two through-holes. Conductor layer portion 12C3 includes conductor layers 724, 734 (see FIGS. 8(c) and 9(a)) arranged at different positions in the stacking direction T and connected in parallel by two through-holes. Each of the conductor layers 722 - 724, 732 - 734 extends in a direction parallel to the Y direction.

[0062] The conductor portion L12A further includes through-hole rows 12T1 and 12T2 (see FIGS. 10 and 11). The through-hole row 12T1 is connected to a portion near one end in the longitudinal direction of the conductor layer portion 12C1. The through-hole row 12T2 is connected to a portion near the other end in the longitudinal direction of the conductor layer portion 12C1.

[0063] The conductor portion L12B further includes through-hole rows 12T3 and 12T4 (see FIGS. 10 and 11). The through-hole row 12T3 is connected to a portion near one end in the longitudinal direction of the conductor layer portion 12C2. The through-hole row 12T3 is connected to a portion near the other end in the longitudinal direction of the conductor layer portion 12C2.

[0064] The conductor portion L12C further includes through-hole rows 12T5 and 12T6 (see FIGS. 10 and 11). The through-hole row 12T5 is connected to a portion near one end in the longitudinal direction of the conductor layer portion 12C3. The through-hole row 12T6 is connected to a portion near the other end in the longitudinal direction of the conductor layer portion 12C3.

[0065] The connection portion L12D connects the through-hole row 12T2 of the conductor portion L12A and the through-hole row 12T3 of the conductor portion L12B. Further, the connection portion L12D includes a conductor layer portion 12C4 (see FIG. 10). The conductor layer portion 12C4 includes conductor layers 621 and 631 (see FIGS. 7(c) and 8(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through-holes.

[0066] The connection portion L12E connects the through-hole row 12T4 of the conductor portion L12B and the through-hole row 12T5 of the conductor portion L12C. Further, the connection portion L12E includes a conductor layer portion 12C5 (see FIG. 10). The conductor layer portion 12C5 includes conductor layers 622 and 632 (see FIGS. 7(c) and 8(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through-holes.

[0067] The conductor layers 542 and 552 shown in FIGS. 5(a) and 5(b) are arranged at different positions from each other in the stacking direction T and are connected in parallel by three through holes. The conductor layers 542 and 552 connect the through hole rows 11T3 and 11T4 of the conductor portion of the inductor L11 and the through hole row 12T1 of the conductor portion L12A of the inductor L12.

[0068] Next, the configuration of the inductor L13 will be described. The inductor L13 is wound around an axis A13 parallel to the stacking direction T. The inductor L13 is constituted by a conductor layer 531 (see FIG. 4(c)).

[0069] Next, the configuration of the inductor L21 will be described. As shown in FIGS. 14 and 15, the inductor L21 is wound around an axis A21 parallel to the direction orthogonal to the stacking direction T. In particular, in the present embodiment, the axis A21 extends in a direction parallel to the Y direction.

[0070] Further, the inductor L21 includes one conductor portion wound less than once around the axis A21. The conductor portion of the inductor L21 includes a conductor layer portion 21C1 (see FIGS. 10 and 11). The conductor layer portion 21C1 includes conductor layers 725 and 735 (see FIGS. 8(c) and 9(a)) arranged at different positions from each other in the stacking direction T and connected in parallel by two through holes. Each of the conductor layers 725 and 735 includes a first portion extending in the X direction and a second portion extending in the Y direction.

[0071] The conductor portion of the inductor L21 further includes through hole rows 21T1 and 21T2 (see FIGS. 10 and 11). The through hole row 21T1 is connected to a portion near one longitudinal end of the conductor layer portion 21C1. The through hole row 21T2 is connected to a portion near the other longitudinal end of the conductor layer portion 21C1.

[0072] The inductor L21 further includes conductor layer portions 21C2 and 21C3 (see FIG. 11). The conductor layer portion 21C1 connects one end of the through-hole row 21T1 and one end of the through-hole row 21T2. The conductor layer portion 21C2 is connected to the other end of the through-hole row 21T1 and extends so as to approach the other end of the through-hole row 21T2. The conductor layer portion 21C3 is connected to the other end of the through-hole row 21T2 and extends so as to approach the other end of the through-hole row 21T1.

[0073] The conductor layer portion 21C2 includes conductor layers 561 and 571 (see FIGS. 5(c) and 6(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through-holes. The conductor layer portion 21C3 includes conductor layers 544 and 553 (see FIGS. 5(a) and 5(b)) that are arranged at different positions in the stacking direction T and are connected in parallel by two through-holes.

[0074] The conductor layer portions 21C1 and 21C2 and the through-hole rows 21T1 and 21T2 constitute the inductor portion 211 of the inductor L21. The conductor layer portion 21C3 constitutes the inductor portion 212 of the inductor L21. The conductor layer portion 21C3 (conductor layers 544 and 553) is connected to the ground terminal 117 via the conductor layers 526 and 5310 (see FIGS. 4(b) and 4(c)) and a plurality of through-holes.

[0075] Next, the configuration of the inductor L22 will be described. As shown in FIGS. 13 and 14, the inductor L22 is wound around an axis A22 parallel to a direction orthogonal to the stacking direction T. In particular, in the present embodiment, the axis A22 extends in a direction parallel to the Y direction. The inductor L22 also includes conductor portions L22A and L22B that are each wound around the axis A22 less than once, and a connection portion L22C that connects the conductor portions L22A and L22B in series.

[0076] The conductor portions L22A and L22B each include conductor layer portions 22C1 and 22C2 (see FIGS. 10 and 11). Each of the conductor layer portions 22C1 and 22C2 has a shape that is long in a direction parallel to the X direction.

[0077] The conductor layer portion 22C1 includes conductor layers 726 and 736 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through holes. The conductor layer portion 22C2 includes conductor layers 727 and 737 (see FIGS. 8(c) and 9(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through holes. Each of the conductor layers 726, 727, 736, and 737 extends in a direction parallel to the X direction.

[0078] The conductor portion L22A further includes two through hole rows 22T1 and two through hole rows 22T2 (see FIGS. 10 and 11). The two through hole rows 22T1 are connected in parallel to a portion near one longitudinal end of the conductor layer portion 22C1. The two through hole rows 22T2 are connected in parallel to a portion near the other longitudinal end of the conductor layer portion 22C1.

[0079] The conductor portion L22B further includes two through hole rows 22T3 and two through hole rows 22T4 (see FIGS. 10 and 11). The two through hole rows 22T3 are connected in parallel to a portion near one longitudinal end of the conductor layer portion 22C2. The two through hole rows 22T4 are connected in parallel to a portion near the other longitudinal end of the conductor layer portion 22C2.

[0080] The connection portion L22C connects the two through hole rows 22T2 of the conductor portion L22A and the two through hole rows 22T3 of the conductor portion L22B. The connection portion L22C also includes a conductor layer portion 22C3 (see FIGS. 10 and 11). The conductor layer portion 22C3 includes conductor layers 591 and 601 (see FIGS. 6(c) and 7(a)) that are arranged at different positions in the stacking direction T and are connected in parallel by four through holes.

[0081] The conductor portion L22A constitutes the inductor portion 221 of the inductor L22. The conductor portion L22B constitutes the inductor portion 222 of the inductor L22. The conductor portion L22B is provided between the conductor portion L22A and the ground in terms of circuit configuration. The two through-hole rows 22T4 of the conductor portion L22B are connected to the ground terminals 115 and 118 via the conductor layers 525 and 539 (see FIGS. 4(b) and 4(c)) and a plurality of through-holes.

[0082] Next, the correspondence between the capacitors C11 to C16, C21 to C31 and the internal components of the laminate 50 shown in FIGS. 4(a) to 9(b) will be described. The capacitor C11 is composed of the conductor layers 521, 532, 541, 551 shown in FIGS. 4(b) to 5(a), FIGS. 8(c) and 9(a), and the dielectric layers 52, 53, 54 between these conductor layers. The capacitor C12 is composed of the conductor layers 621, 622, 631, 632, 722 to 724, 732 to 734 shown in FIGS. 7(c), 8(a), 8(c) and 9(a), and the dielectric layers 62, 72 between these conductor layers. The capacitor C13 is composed of the conductor layers 721 to 724, 731 to 734.

[0083] The capacitor C14 is composed of the conductor layers 5311 and 532 shown in FIG. 4(c). The capacitor C15 is composed of the conductor layer 5311, the conductor layer 542 shown in FIG. 5(a), and the dielectric layer 53 between these conductor layers. The capacitor C16 is composed of the conductor layers 5312 and 543 shown in FIGS. 4(c) and 5(a), and the dielectric layer 53 between these conductor layers.

[0084] Capacitor C21 is composed of the conductor layers 533 and 545 shown in FIGS. 4(c) and 5(a), and the dielectric layer 53 between these conductor layers. Capacitor C22 is composed of the conductor layers 534 and 545 shown in FIGS. 4(c), 5(a) and 5(c), and the dielectric layer 53 between these conductor layers. Capacitor C23 is composed of the conductor layers 535 and 546 shown in FIGS. 4(c) and 5(a), and the dielectric layer 53 between these conductor layers. Capacitor C24 is composed of the conductor layers 533 and 534. Capacitor C25 is composed of the conductor layers 536, 546 and 547 shown in FIGS. 4(c), 5(a) and 5(c), and the dielectric layer 53 between these conductor layers.

[0085] Capacitor C26 is composed of the conductor layers 561, 571, 725 and 735 shown in FIGS. 5(c), 6(a), 8(c) and 9(a), and the dielectric layers 56 and 72 between these conductor layers. Capacitor C27 is composed of the conductor layers 544 and 553 shown in FIGS. 5(a) and 5(b), and the dielectric layer 54 between these conductor layers. Capacitor C28 is composed of the conductor layers 554 and 572 shown in FIGS. 5(b) and 6(a), and the dielectric layers 55 and 56 between these conductor layers.

[0086] Capacitor C29 is composed of the conductor layers 591, 601, 726 and 736 shown in FIGS. 6(c), 7(a), 8(c) and 9(a), and the dielectric layers 59 and 72 between these conductor layers. Capacitor C30 is composed of the conductor layers 591 and 601, and Conductor layer 727 and 737 shown in FIGS. 8(c) and 9(a), and the dielectric layers 59 and 72 between these conductor layers. Capacitor C31 is composed of the conductor layers 537 and 548 shown in FIGS. 4(c) and 5(a), and the dielectric layer 53 between these conductor layers.

[0087] Next, referring to FIGS. 10 to 17, the structural features of the electronic component 1 according to the present embodiment will be described. FIGS. 16 and 17 are plan views showing a part inside the laminate 50 shown in FIGS. 10 and 11.

[0088] As shown in FIGS. 10 to 15, the inductor L12 is arranged ahead of the inductor L11 in one direction orthogonal to the stacking direction T, that is, in the -Y direction. The inductors L21 and L22 are respectively arranged ahead of the inductors L11 and L12 in one direction orthogonal to the stacking direction T, that is, in the +X direction.

[0089] In FIGS. 12 and 15, the region surrounded by the broken line marked with S11 indicates the space including the axis A11 and surrounded by the inductor L11. Also, in FIGS. 12 and 13, the region surrounded by the broken line marked with S12 indicates the space including the axis A12 and surrounded by the inductor L12. Further, in FIGS. 14 and 15, the region surrounded by the broken line marked with S21 indicates the space including the axis A21 and surrounded by the inductor L21. Also, in FIGS. 13 and 14, the region surrounded by the broken line marked with S22 indicates the space including the axis A22 and surrounded by the inductor L22.

[0090] In FIG. 15, the region surrounded by the broken line marked with S11 is also a region obtained by vertically projecting the space S11 onto a virtual plane (XZ plane) perpendicular to the axis A11. Hereinafter, this region will be referred to as the projection region of the space S11. The area of the projection region of the space S11 corresponds to the opening area of the inductor L11.

[0091] Also, in FIG. 12, the region surrounded by the broken line marked with S12 is also a region obtained by vertically projecting the space S12 onto a virtual plane (YZ plane) perpendicular to the axis A12. Hereinafter, this region will be referred to as the projection region of the space S12. The area of the projection region of the space S12 corresponds to the opening area of the inductor L12.

[0092] In addition, in FIG. 15, the region surrounded by the broken line labeled S21 is also the region obtained by perpendicularly projecting the space S21 onto a virtual plane (XZ plane) perpendicular to the axis A21. Hereinafter, this region will be referred to as the projection region of the space S21. The area of the projection region of the space S21 corresponds to the opening area of the inductor L21.

[0093] In addition, in FIG. 13, the region surrounded by the broken line labeled S22 is also the region obtained by perpendicularly projecting the space S22 onto a virtual plane (XZ plane) perpendicular to the axis A22. Hereinafter, this region will be referred to as the projection region of the space S22. The area of the projection region of the space S22 corresponds to the opening area of the inductor L22.

[0094] As shown in FIGS. 12 and 15, the area of the projection region of the space S11 is larger than that of the projection region of the space S12. Also, as shown in FIGS. 12 and 15, the area of the projection region of the space S21 is larger than that of the projection region of the space S12. Further, as shown in FIGS. 12 and 13, the area of the projection region of the space S22 is larger than that of the projection region of the space S12.

[0095] Also, as shown in FIGS. 13 and 15, the area of the projection region of the space S21 and the area of the projection region of the space S22 are different from each other. In particular, in this embodiment, the area of the projection region of the space S21 is larger than the area of the projection region of the space S22. Also, the dimension of the projection region of the space S21 in the stacking direction T is larger than the dimension of the projection region of the space S22 in the stacking direction T.

[0096] The inductor L11 is arranged such that when viewed from one direction (Y direction) parallel to the axis A11, a part of the space S11 overlaps at least a part of the space S12.

[0097] The inductor L12 is arranged such that when viewed from one direction (X direction) parallel to the axis A12, at least a part of the space S12 overlaps with the space S22. Also, the inductor L12 is arranged such that the axis A12 is parallel to the long side of the bottom surface 50A (long side of the upper surface 50B) of the stacked body 50.

[0098] The inductor L13 is arranged such that its axis A13 does not intersect the spaces S11, S21, S22 but intersects the space S12. In other words, the inductor L13 is arranged to overlap the inductor L12 when viewed from the Z direction. Between the inductor L12 and the inductor L13, specifically, between the conductor layer 531 (see FIG. 4(c)) and the conductor layers 621, 622 (see FIG. 7(c)), there is no conductor layer for a capacitor used to form a capacitor.

[0099] The inductor L21 is arranged such that when viewed from a direction parallel to the axis A21 (the Y direction), a part of the space S21 overlaps at least a part of the space S22. In other words, the inductor L22 is arranged such that when viewed from a direction parallel to the axis A22 (the Y direction), at least a part of the space S22 overlaps a part of the space S21.

[0100] The conductor layer portion 21C3 of the inductor L21 is arranged between the conductor layer portion 21C1 of the inductor L21 and the bottom surface 50A. When viewed from a direction parallel to the stacking direction T (the Z direction), the conductor layer portion 21C3 extends across the signal terminal 114. Also, the inductor L21 is electrically connected to the ground terminal 117. The inductor L22 is electrically connected to the ground terminals 115, 118.

[0101] The inductor L22 includes a conductor portion L22A that forms the inductor portion 221 of the inductor L22, an L22B that forms the inductor portion 222 of the inductor L22, and a connection portion L22C that connects the conductor portions L22A, L22B in series. The conductor portion L22A (inductor portion 221) magnetically couples with the conductor layer portions 21C1, 21C2 and the via hole rows 21T1, 21T2 that form the inductor portion 211 of the inductor L21 among the inductor L21.

[0102] FIG. 17 shows two conductor layers 721 and 731 that constitute the conductor layer portion 11C1 of the inductor L11. As shown in FIG. 17, the area of the conductor layer 721 is larger than the area of the conductor layer 731. The conductor layer 731 is disposed inside the outer edge of the conductor layer 721 when viewed from one direction (Z direction) parallel to the stacking direction T. The shape of the conductor layer 731 when viewed from the Z direction is similar to the shape of the conductor layer 721 when viewed from the Z direction. The conductor layer 721 is disposed between the conductor layer 731 and the axis A11.

[0103] The above description of the conductor layers 721 and 731 also applies to the sets of conductor layers 72x and 73x (where x is an integer from 2 to 7). If the conductor layers 721 and 731 in the above description of the conductor layers 721 and 731 are replaced with the conductor layers 72x and 73x respectively, it becomes the description of the conductor layers 72x and 73x. In the case of the description of the set of conductor layers 72x and 73x that constitute the inductor L12, the axis A11 in the above description is replaced with the axis A12. Also, in the case of the description of the set of conductor layers 725 and 735 that constitute the inductor L21, the axis A11 in the above description is replaced with the axis A21. Further, in the case of the description of the set of conductor layers 72x and 73x that constitute the inductor L22, the axis A11 in the above description is replaced with the axis A22.

[0104] FIG. 16 shows two conductor layers 621 and 631 that constitute the conductor layer portion 12C4 of the inductor L12. As shown in FIG. 16, the area of the conductor layer 631 is larger than the area of the conductor layer 621. The conductor layer 621 is disposed inside the outer edge of the conductor layer 631 when viewed from one direction (Z direction) parallel to the stacking direction T. The shape of the conductor layer 621 when viewed from the Z direction is similar to the shape of the conductor layer 631 when viewed from the Z direction. The conductor layer 631 is disposed between the conductor layer 621 and the axis A12.

[0105] The above description of the conductor layers 621 and 631 also applies to the sets of conductor layers 622 and 632, the sets of conductor layers 561 and 571, the sets of conductor layers 543 and 553, and the sets of conductor layers 591 and 601. If the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 622 and 632 respectively, it will become the description of the conductor layers 622 and 632.

[0106] Also, if the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 561 and 571 or the conductor layers 543 and 553 respectively, and the axis A12 in the above description of the conductor layers 621 and 631 is replaced with the axis A21, it will become the description of the conductor layers 561 and 571 or the conductor layers 543 and 553.

[0107] Also, if the conductor layers 621 and 631 in the above description of the conductor layers 621 and 631 are replaced with the conductor layers 591 and 601 respectively, and the axis A12 in the above description of the conductor layers 621 and 631 is replaced with the axis A22, it will become the description of the conductor layers 591 and 601.

[0108] Next, an example of the characteristics of the electronic component 1 according to the present embodiment is shown. FIG. 18 is a characteristic diagram showing the passing attenuation characteristics between the common port 2 and the first signal port 3, that is, the passing attenuation characteristics of the first filter 10. FIG. 19 is a characteristic diagram showing the passing attenuation characteristics between the common port 2 and the second signal port 4, that is, the passing attenuation characteristics of the second filter 20. In FIGS. 18 and 19, the horizontal axis represents the frequency, and the vertical axis represents the attenuation amount.

[0109] In FIG. 18, reference numeral 91 indicates an attenuation pole formed by inductor L11, and reference numeral 92 indicates an attenuation pole formed by inductor L12. Inductor L12 forms attenuation pole 92 on the high-frequency side of the first passband in the passband attenuation characteristic of the first filter 10. Inductor L11 forms attenuation pole 91 between the first passband and attenuation pole 92 in the passband attenuation characteristic of the first filter 10. That is, in the passband attenuation characteristic of the first filter 10, attenuation pole 91 formed by inductor L11 is closer to the first passband than attenuation pole 92 formed by inductor L12.

[0110] In FIG. 19, reference numeral 93 indicates an attenuation pole formed by inductor L21, and reference numeral 94 indicates an attenuation pole formed by inductor L22. Inductor L23 forms attenuation pole 93 on the low-frequency side of the second passband in the passband attenuation characteristic of the second filter 20. Inductor L22 forms attenuation pole 94 between attenuation pole 93 and the second passband in the passband attenuation characteristic of the second filter 20. That is, in the passband attenuation characteristic of the second filter 20, attenuation pole 94 formed by inductor L22 is closer to the second passband than attenuation pole 93 formed by inductor L21.

[0111] Hereinafter, an example of the inductance and Q value of each of inductors L11, L12, L13, L21, and L22 will be described. In one example, the inductance of inductor L11 is 0.8 nH. The Q value of inductor L11 is 125. The inductance of inductor L12 is 3.4 nH. The Q value of inductor L12 is 113. The inductance of inductor L13 is 0.81 nH. The Q value of inductor L13 is 53. The inductance of inductor L21 is 1.5 nH. The Q value of inductor L21 is 73. The inductance of inductor L22 is 2.0 nH. The Q value of inductor L22 is 127.

[0112] Next, the operation and effects of the electronic component 1 according to the present embodiment will be described. In the present embodiment, in the inductor L11, two through-hole rows are connected in parallel to the portions near both ends in the longitudinal direction of the conductor layer portion 11C1, respectively. In the inductor L22, two through-hole rows are connected in parallel to the portions near both ends in the longitudinal direction of the conductor layer portion 22C1, respectively, and two through-hole rows are connected in parallel to the portions near both ends in the longitudinal direction of the conductor layer portion 22C2, respectively.

[0113] In the inductor L12, one through-hole row is connected to the portions near both ends in the longitudinal direction of the conductor layer portion 12C1, one through-hole row is connected to the portions near both ends in the longitudinal direction of the conductor layer portion 12C2, and one through-hole row is connected to the portions near both ends in the longitudinal direction of the conductor layer portion 12C3, respectively. In the inductor L21, one through-hole row is connected to the portions near both ends in the longitudinal direction of the conductor layer portion 21C1, respectively.

[0114] As described above, in the present embodiment, in each of the inductors L11 and L22, a plurality (two) of through-hole rows are connected in parallel to one end of the conductor layer portion. Thus, according to the present embodiment, the Q value of each of the inductors L11 and L22 can be increased.

[0115] On the other hand, in the present embodiment, in each of the inductors L12 and L21, one through-hole row is connected to one end of the conductor layer portion. Thus, according to the present embodiment, the electronic component 1 can be made smaller as compared with the case where a plurality of through-hole rows are connected in parallel to one end of the conductor layer portion in all of the inductors L11, L12, L21, and L22.

[0116] In the first filter 10, it is preferable to increase the Q value of the inductor L11 that forms the attenuation pole 91 closest to the first passband. Also, in the second filter 20, it is preferable to increase the Q value of the inductor L22 that forms the attenuation pole 94 closest to the second passband. In the present embodiment, from such a viewpoint, in each of the inductors L11 and L22, a plurality (two) of through-hole rows are connected in parallel to one end of the conductor layer portion to increase the Q value of each of the inductors L11 and L22.

[0117] Also, in the present embodiment, the inductor L12 is disposed ahead in the -Y direction with respect to the inductor L11, and the inductors L21 and L22 are respectively disposed ahead in the -X direction with respect to the inductors L11 and L12. That is, in the present embodiment, the inductors L11 and L12 are arranged in a row, and the inductors L21 and L22 are arranged in a row at a position different from that of the inductors L11 and L12. Thereby, according to the present embodiment, compared with the case where the inductors L11 and L22 are arranged in a row and the inductors L12 and L21 are arranged in a row at a position different from that of the inductors L11 and L22, the useless space generated in the laminate 50 can be reduced, and as a result, the electronic component 1 can be miniaturized.

[0118] From the above, according to the present embodiment, the electronic component 1 can be miniaturized while increasing the Q value of each of the inductors L11 and L22.

[0119] Also, in the present embodiment, the axis A11 around which the inductor L11 is wound and the axis A22 around which the inductor L22 is wound are parallel to each other. In particular, in the present embodiment, both the axes A11 and A22 extend in a direction parallel to the Y direction. Also, in each of the inductors L11 and L22, the conductor layer portion has a shape that is long in the X direction. Therefore, according to the present embodiment, the dimension of the laminate 50 in the Y direction can be reduced compared with the case where the axis A11 and the axis A22 are orthogonal to each other.

[0120] Also, in the present embodiment, the direction parallel to the axis A12 and the direction parallel to the axis A22 are orthogonal to each other. In particular, in the present embodiment, the direction parallel to the axis A12 is the direction parallel to the X direction, and the direction parallel to the axis A22 is the direction parallel to the Y direction. Further, in the present embodiment, the inductor L12 is wound around the axis A12 parallel to the X direction about three times. As described above, in the inductor L22, the conductor layer portion has a shape that is long in the X direction. Therefore, according to the present embodiment, compared with the case where the axis A22 is parallel to the X direction and the conductor layer portion of the inductor L22 has a shape that is short in the X direction, when the inductor L12 is wound around the axis A12 a plurality of times, the wasted space generated can be reduced.

[0121] Next, other effects in the present embodiment will be described. In the present embodiment, the area of the projection region of the space S11 corresponding to the opening area of the inductor L11 is larger than the area of the projection region of the space S12 corresponding to the opening area of the inductor L12. That is, in the present embodiment, the area of the projection region of the space S12 corresponding to the opening area of the inductor L12 is smaller than the area of the projection region of the space S11 corresponding to the opening area of the inductor L11. Thereby, a space for arranging other inductors can be formed in the vicinity of the inductor L12. In the present embodiment, the inductor L13 is arranged in the above space. As described above, the inductor L13 is arranged such that the axis A13 intersects the space S12 but does not intersect the space S11. In the present embodiment, further, the inductors L11, L12, and L13 are wound around axes parallel to different directions from each other. In particular, in the present embodiment, the axes A11, A12, and A13 are orthogonal to each other. From these facts, according to the present embodiment, the electronic component 1 can be miniaturized while suppressing the electromagnetic field coupling between the inductors L11, L12, and L13.

[0122] In addition, in the present embodiment, when viewed from one direction parallel to the axis A11, the inductor L11 is arranged such that a part of the space S11 overlaps at least a part of the space S12. According to this embodiment, compared with the case where the space S11 and the space S12 do not overlap with each other, the electronic component 1 can be miniaturized.

[0123] Further, according to the present embodiment, the first filter 10 includes inductors L11, L12, and L13. According to the present embodiment, due to the above characteristics of the inductors L11, L12, and L13, the area of the region of the first filter 10 in the laminate 50 can be reduced, and as a result, the electronic component 1 can be miniaturized.

[0124] In addition, in the present embodiment, the area of the projection region of the space S12 corresponding to the opening area of the inductor L12 is smaller than the area of the projection region of the space S22 corresponding to the opening area of the inductor L22. In the present embodiment, further, the inductors L12, L13, and L22 are wound around axes parallel to each other in different directions. In particular, in the present embodiment, the axes A12, A13, and A22 are orthogonal to each other. From these facts, according to the present embodiment, the electronic component 1 can be miniaturized while suppressing the electromagnetic field coupling between the inductors L12, L13, and L22.

[0125] In addition, in the present embodiment, when viewed from one direction parallel to the axis A12, the inductor L12 is arranged such that a part of the space S12 overlaps at least a part of the space S22. According to this embodiment, compared with the case where the space S12 and the space S22 do not overlap with each other, the electronic component 1 can be miniaturized.

[0126] In addition, in the present embodiment, no capacitor conductor layer is interposed between the inductor L12 and the inductor L13. According to this embodiment, compared with the case where a capacitor conductor layer is interposed between the inductor L12 and the inductor L13, the electronic component 1 can be miniaturized.

[0127] Also, in the present embodiment, the first filter 10 includes inductors L12 and L13, and the second filter 20 includes an inductor L22. According to the present embodiment, due to the above characteristics of the inductors L12, L13, and L22, the first filter 10 and the second filter 20 can be brought closer to each other, and as a result, the electronic component 1 can be miniaturized.

[0128] By the way, since the area of the projection region of the space S12 corresponding to the opening area of the inductor L12 is small, the inductance of the inductor L12 is relatively small. On the other hand, in the present embodiment, the inductor L12 includes conductor portions L12A, L12B, and L12C that are each wound less than once around the axis A12. That is, in the present embodiment, the inductor L12 is wound approximately three times around the axis A12. Thereby, according to the present embodiment, the inductance of the inductor L12 can be increased. Also, according to the present embodiment, the dimension in the direction parallel to the axis A12 of the inductor L12 (the direction parallel to the X direction) can be increased. Thereby, according to the present embodiment, the space for arranging the inductor L13 can be increased.

[0129] Also, in the present embodiment, the inductor L12 is arranged such that the axis A12 is parallel to the long side of the bottom surface 50A of the laminate 50 (the long side of the upper surface 50B). Thereby, according to the present embodiment, while arranging another inductor, specifically the inductor L22, in the direction parallel to the axis A12, the inductor L12 can be wound a plurality of times around the axis A12.

[0130] Also, in the present embodiment, inductors L11 and L12 are provided on the first signal path 5 in terms of circuit configuration, and inductor L13 is provided between the first signal path 5 and the ground in terms of circuit configuration. Inductor L13 may have a smaller Q value than inductors L11 and L12. As described above, in one example, the Q value of inductor L11 is 125, the Q value of inductor L12 is 113, and the Q value of inductor L13 is 53. In the present embodiment, inductors L11 and L12, which preferably have a relatively large Q value, are formed as inductors wound around an axis orthogonal to the stacking direction T, and inductor L13, which may have a relatively small Q value, is formed as an inductor wound around an axis parallel to the stacking direction T. Then, inductor L13, which may have a relatively small Q value, is arranged in a space formed in the vicinity of inductor L12.

[0131] Also, in the present embodiment, inductor L21 is arranged such that when viewed from one direction (Y direction) parallel to axis A21, a part of space S21 overlaps at least a part of space S22. In other words, inductor L22 is arranged such that when viewed from one direction (Y direction) parallel to axis A22, at least a part of space S22 overlaps a part of space S22. In particular, in the present embodiment, axis A21 and axis A22 are parallel. Therefore, in the present embodiment, inductors L21 and L22 are arranged such that the openings of inductor L21 and inductor L22 face each other and inductors L21 and L22 overlap when viewed from the Y direction.

[0132] Here, consider adjusting the magnetic coupling between inductor L21 and and inductor L22. For example, the magnetic coupling can be adjusted by shifting one of inductors L21 and L22 in the X direction or the -X direction. However, if this is done, a wasted space will be generated in the laminate 50, and the planar shape (shape viewed from the Z direction) of the electronic component 1 will become large.

[0133] In contrast, in the present embodiment, the area of the projection region of the space S21 and the area of the projection region of the space S22 are made different from each other. According to the present embodiment, by this, the magnetic coupling can be adjusted without shifting one of the inductors L21 and L22 in the X direction or the -X direction.

[0134] By the way, in order to adjust the area of the projection region of the space S21, it is conceivable to increase the dimension in the stacking direction T of the inductor L21. In this case, the distance from the bottom surface 50A of the laminate 50 to the inductor L21 becomes small. If a ground terminal is provided in the vicinity of the inductor L21, a parasitic capacitance may occur between the inductor L21 and the ground terminal, and it may be impossible to obtain desired characteristics.

[0135] In contrast, in the present embodiment, the inductor L21 includes a conductor layer portion 21C2 connected to the other end of the through-hole row 21T1 and extending so as to approach the other end of the through-hole row 21T2, and a conductor layer portion 21C3 connected to the other end of the through-hole row 21T2 and extending so as to approach the other end of the through-hole row 21T1. According to the present embodiment, at least one of the conductor layer portions 21C2 and 21C3 can be arranged so that the inductor L21 does not overlap the ground terminal when viewed from one direction (Z direction) parallel to the stacking direction T. In particular, in the present embodiment, when viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer portion 21C3 extends so as to cross the signal terminal 114. According to the present embodiment, by this, the dimension of the inductor L21 in the stacking direction T can be increased to adjust the area of the projection region of the space S21.

[0136] From the above, according to the present embodiment, the electronic component 1 can be miniaturized while adjusting the electromagnetic field coupling between the inductors L21 and L22.

[0137] Also, in the present embodiment, the electronic component 1 includes a second filter 20 including inductors L21 and L22, and a first filter 10 not including inductors L21 and L22. In order to increase the isolation between the first filter 10 and the second filter 20, it is conceivable to provide a ground terminal at a position sandwiched between the first filter 10 and the second filter 20. In the present embodiment, the conductor layer portion 21C3 is connected to a ground terminal 117 provided at a position sandwiched between the first filter 10 and the second filter 20. That is, according to the present embodiment, while increasing the isolation between the first filter 10 and the inductor L21, the inductor L21 can be connected to the ground terminal 117 by the conductor layer portion 21C3.

[0138] Also, in the present embodiment, the inductor L22 includes conductor portions L22A and L22B. The conductor portion L22A is magnetically coupled to the inductor L21. That is, in the present embodiment, a part of the inductor L22 is magnetically coupled to the inductor L21. According to the present embodiment, by configuring the inductor as described above, the magnetic coupling between the inductor L21 and the inductor L22 can be adjusted.

[0139] Also, in the present embodiment, the conductor layer portion 11C1 of the inductor L11 includes two conductor layers 721 and 731. As described above, in the manufacturing process of the laminate 50, a ceramic green sheet on which a plurality of pre-firing conductor layers that will later become a plurality of conductor layers and a plurality of pre-firing through-holes that will later become a plurality of through-holes are formed is laminated. If the conductor layer 721 and the conductor layer 731 are displaced from each other due to displacement of the ceramic green sheet or a plurality of pre-firing conductor layers, etc., the characteristics of the inductor L11 will change.

[0140] In contrast, in the present embodiment, the area of the conductor layer 721 is larger than the area of the conductor layer 731. Therefore, even if the conductor layer 731 is displaced relative to the conductor layer 721, when the amount of displacement is smaller than a certain magnitude, when viewed from one direction (Z direction) parallel to the stacking direction T, the conductor layer 731 does not protrude from the conductor layer 721. Thus, according to the present embodiment, it is possible to suppress fluctuations in the characteristics of the inductor L11 caused by the displacement of the conductor layer 721 and the conductor layer 731 relative to each other.

[0141] The above description of the conductor layers 721 and 731 also applies to the sets of conductor layers 72x and 73x (where x is an integer from 2 to 7), the set of conductor layers 621 and 631, the set of conductor layers 622 and 632, the set of conductor layers 561 and 571, the set of conductor layers 543 and 553, and the set of conductor layers 591 and 601. Therefore, according to the present embodiment, it is possible to suppress fluctuations in the characteristics of each of the first filter 10 and the second filter 20 caused by displacement of the ceramic green sheet or a plurality of pre-fired conductor layers, etc., and as a result, it is possible to suppress fluctuations in the characteristics of the electronic component 1.

[0142] Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, the number of inductors included in each of the first filter 10 and the second filter 20 may be three or more.

[0143] Also, the axis A11 and the axis A12 may intersect at an angle other than 90°. Similarly, the axis A21 and the axis A22 may intersect at an angle other than 90°.

[0144] Also, in each of the inductors L11 and L22, three or more through-hole rows may be connected in parallel to one end of the conductor layer portion.

[0145] Also, in each of the inductors L11, L12, L21, and L22, the conductor layer portion may include three or more conductor layers that are arranged at different positions in the stacking direction T and are connected in parallel. When the conductor layer portion includes three conductor layers, the conductor layer with the smallest area among the three conductor layers may be interposed between the other two conductor layers. Alternatively, the conductor layer portion may be constituted by one conductor layer.

Description of Reference Numerals

[0146] 1... Electronic component, 2... Common port, 3... First signal port, 4... Second signal port, 5... First signal path, 6... Second signal path, 10... First filter, 20... Second filter, 50... Stacked body, 50A... Bottom surface, 50B... Top surface, 50C to 50F... Side surfaces, 51 to 74... Dielectric layers, 111, 115 to 119... Ground terminals, 112 to 114... Signal terminals, C11 to C16, C21 to C31... Capacitors, L11, L12, L13, L21, L22... Inductors, S11, S12, S21, S22... Spaces.

Claims

1. A laminate including a plurality of stacked dielectric layers, a first inductor integrated with the laminate and wound around a first axis orthogonal to the stacking direction of the plurality of dielectric layers, a second inductor integrated with the laminate and wound around a second axis orthogonal to the stacking direction, a third inductor integrated with the laminate and wound around a third axis orthogonal to the stacking direction, a fourth inductor integrated with the laminate and wound around a fourth axis orthogonal to the stacking direction, wherein the second inductor is disposed ahead of the first inductor in a first direction orthogonal to the stacking direction, the third inductor and the fourth inductor are each disposed ahead of the first inductor and the second inductor in a second direction orthogonal to the stacking direction and the first direction, each of the first inductor and the fourth inductor includes a plurality of first through-hole rows and at least one first conductor layer portion, each of the second inductor and the third inductor includes a plurality of second through-hole rows and at least one second conductor layer portion, each of the plurality of first through-hole rows and the plurality of second through-hole rows is formed by connecting two or more through-holes in series, each of the at least one first conductor layer portion and the at least one second conductor layer portion includes a conductor layer, in a portion near one longitudinal end of the conductor layer of the at least one first conductor layer portion, two or more of the plurality of first through-hole rows are connected in parallel, in a portion near the other longitudinal end of the conductor layer of the at least one first conductor layer portion, the other two or more of the plurality of first through-hole rows are connected in parallel, in a portion near one longitudinal end of the conductor layer of the at least one second conductor layer portion, only one of the plurality of second through-hole rows is connected, and in a portion near the other longitudinal end of the conductor layer of the at least one second conductor layer portion, only the other one of the plurality of second through-hole rows is connected. A multilayer electronic component characterized by this.

2. The multilayer electronic component according to claim 1, wherein the first axis and the fourth axis are parallel to each other.

3. The laminated electronic component according to claim 1 or 2, wherein the direction parallel to the second axis and the direction parallel to the fourth axis are orthogonal to each other.

4. The first inductor includes one conductor portion wound less than once around the first axis, The fourth inductor includes a plurality of first conductor portions each wound less than once around the fourth axis, and at least one first connection portion connecting the plurality of first conductor portions in series. The laminated electronic component according to any one of claims 1 to 3, characterized in that

5. The second inductor includes a plurality of second conductor portions each wound less than once around the second axis, and at least one second connection portion connecting the plurality of second conductor portions in series. The laminated electronic component according to any one of claims 1 to 4, characterized in that

6. The laminated electronic component according to any one of claims 1 to 5, wherein the third axis and the fourth axis are parallel to each other.

7. The area of the region obtained by vertically projecting the first space including the third axis and surrounded by the third inductor onto a virtual plane perpendicular to the third axis is larger than the area of the region obtained by vertically projecting the second space including the fourth axis and surrounded by the fourth inductor onto a virtual plane perpendicular to the fourth axis. The laminated electronic component according to claim 6, characterized in that

8. Furthermore, a common port, a first signal port, a second signal port, a first filter including the first inductor and the second inductor, provided between the common port and the first signal port, and selectively passing a first signal having a frequency within a first passband; A second filter including the third inductor and the fourth inductor, provided between the common port and the second signal port, and selectively passing a second signal having a frequency within a second passband. The laminated electronic component according to any one of claims 1 to 7, characterized in that it is provided with

9. The laminated electronic component according to claim 8, wherein the first inductor is provided closer to the first signal port than the second inductor in terms of circuit configuration.

10. In the pass attenuation characteristic of the first filter, the attenuation pole formed by the first inductor is closer to the first pass band than the attenuation pole formed by the second inductor. The laminated electronic component according to claim 8 or 9.

11. The fourth inductor is provided at a position closer to the common port than the third inductor in terms of circuit configuration. The laminated electronic component according to any one of claims 8 to 10.

12. In the pass attenuation characteristic of the second filter, the attenuation pole formed by the fourth inductor is closer to the second pass band than the attenuation pole formed by the third inductor. The laminated electronic component according to any one of claims 8 to 11.

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