Indicating device

Abstract

To provide a logic circuit using a resistor element and a thin film transistor manufactured using an oxide semiconductor layer with the electric characteristics controlled, and a semiconductor device using the logic circuit.SOLUTION: In a semiconductor device, on an oxide semiconductor layer 905 used for a resistor element 354, a silicon nitride layer 910 is provided in direct contact by a plasma CVD method using gas containing a hydrogen compound such as SiH4 and NH3. In an oxide semiconductor layer 906 used for a thin film transistor 355, a silicon nitride layer 910 is provided through a silicon oxide layer 909 functioning as a barrier layer. Therefore, in the oxide semiconductor layer 905, hydrogen is introduced at higher concentration than in the oxide semiconductor layer 906. As a result, a resistance value of the oxide semiconductor layer 905 used for the resistor element 354 is lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a drive circuit composed of elements formed using a metal oxide exhibiting semiconductor characteristics, and a semiconductor device using the drive circuit. Note that the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and display devices, semiconductor circuits, and electronic devices are all semiconductor devices.

Background Art

[0002] Metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as a transparent electrode material required for liquid crystal displays and the like.

[0003] Some metal oxides exhibit semiconductor characteristics. Metal oxides exhibiting semiconductor characteristics are a type of compound semiconductor. A compound semiconductor is a semiconductor formed by bonding two or more kinds of atoms by ionic bonds. Generally, metal oxides are insulators. However, depending on the combination of elements constituting the metal oxide, it is known that the electrostatic attraction is weak and it becomes a semiconductor. For example, among metal oxides, tungsten oxide, tin oxide, indium oxide, and zinc oxide are known to exhibit semiconductor characteristics. A thin film transistor having a transparent semiconductor layer made of such a metal oxide as a channel formation region has been disclosed (Patent Documents 1 to 4,

[0004] Non-Patent Document 1).

[0005] By the way, metal oxides are known not only as single-component oxides but also as multi-component oxides. For example, , InGaO3(ZnO) having a homologous phase m (m: natural number) is a known material ( Non-patent documents 2 to 4).

[0006] The In-Ga-Zn oxide is used as the channel forming region of a thin film transistor. It has been confirmed that the above-mentioned method can be applied to the following areas (Patent Document 5, Non-Patent Documents 5 and 6). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] JP 2000-150900 A [Patent Document 5] JP 2004-103957 A [Non-patent literature]

[0008] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0009] A thin film transistor using a metal oxide showing semiconductor characteristics (hereinafter also referred to as an oxide semiconductor) is being considered for application to an active matrix type display device (liquid crystal display, electroluminescence display, or electronic paper, etc.). The active matrix type display device has hundreds of thousands to millions of pixels arranged in a matrix and a driving circuit for inputting a pulse signal to the pixels.

[0010] In an active matrix type display device, the thin film transistor is provided for each pixel and functions as a switching element that switches on and off when a pulse signal from the driving circuit is input, enabling the display of an image. Further, the thin film transistor is also used as an element constituting the driving circuit.

[0011] The driving circuit for driving the pixel portion is composed of elements such as thin film transistors, capacitive elements, and resistive elements.

[0012] One aspect of the present invention aims to provide a logic circuit composed of active elements and passive elements manufactured using an oxide semiconductor and a semiconductor device having the logic circuit.

Means for Solving the Problem

[0013] One aspect of the present invention has an enhancement type thin film transistor and a resistive element. The thin film transistor and the resistive element are formed using an oxide semiconductor layer. Further, the hydrogen concentration of the oxide semiconductor layer applied to the thin film transistor is made lower than the hydrogen concentration of the oxide semiconductor layer applied to the resistive element. Thereby, the resistance value of the oxide semiconductor layer applied to the resistive element ​​​​​​​​​is characterized by being lower than the resistance value of the oxide semiconductor layer applied to the thin film transistor do.

[0014] One aspect of the present invention is a thin film transistor and a resistance element formed using an oxide semiconductor layer having, on the oxide semiconductor layer applied to the resistance element, a silicon nitride layer formed by a plasma CVD method using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3), and provided so that the silicon nitride layer is in direct contact, and on the oxide semiconductor layer applied to the thin film transistor, via a silicon oxide layer functioning as a barrier layer, the above-mentioned silicon nitride layer is provided. Therefore, hydrogen is introduced into the oxide semiconductor layer applied to the resistance element at a higher concentration than the oxide semiconductor layer applied to the thin film transistor. As a result, the resistance value of the oxide semiconductor layer applied to the resistance element is characterized by being lower than the resistance value of the oxide semiconductor layer applied to the thin film transistor. That is, one aspect of the present invention is a resistance element in which a first oxide semiconductor layer is applied to a resistance component, a thin film transistor in which a second oxide semiconductor layer having a lower hydrogen concentration than the first oxide semiconductor layer is applied to a channel formation region, a silicon oxide layer provided on the second oxide semiconductor layer, and a silicon nitride layer provided on the first oxide semiconductor layer and the silicon oxide layer. is a logic circuit having.

[0015] Furthermore, a configuration in which a low-resistance oxide semiconductor layer is provided between the resistance component of the resistance element and the oxide semiconductor layer applied to the channel formation region of the thin film transistor and the wiring which is a conductor is also one aspect of the present invention. is also one aspect of the present invention. is a logic circuit having. do.

[0016] is also one aspect of the present invention. is also one aspect of the present invention. do.

[0017] That is, one aspect of the present invention is, in the above configuration, one terminal or the other terminal of the resistive element and a third oxide semiconductor layer in contact with the first oxide semiconductor layer, a first terminal of the thin film transistor, and a fourth oxide semiconductor layer in contact with the second oxide semiconductor layer, and a second terminal of the thin film transistor and a fifth oxide semiconductor layer in contact with the second oxide semiconductor layer, wherein the third to fifth oxide semiconductor layers have a lower resistance value than the second oxide semiconductor layer, and it is a logic circuit. And a fourth oxide semiconductor layer in contact with the first terminal of the thin film transistor and the second oxide semiconductor layer, and a fifth oxide semiconductor layer in contact with the second terminal of the thin film transistor and the second oxide semiconductor layer, and a fourth oxide semiconductor layer in contact with the first terminal of the thin film transistor and the second oxide semiconductor layer, and a fifth oxide semiconductor layer in contact with the second terminal of the thin film transistor and the second oxide semiconductor layer, and a fifth oxide semiconductor layer in contact with the second terminal of the thin film transistor and the second oxide semiconductor layer, and the third to fifth oxide semiconductor layers have a lower resistance value than the second oxide semiconductor layer, and it is a logic circuit. That is, one aspect of the present invention is a logic circuit.

[0018] Also, one aspect of the present invention has a resistive element and a thin film transistor formed using an oxide semiconductor layer containing nitrogen at a high concentration. Further, a silicon oxide layer that functions as a barrier layer is provided on the thin film transistor. At this stage, a heat treatment at 200°C to 600°C, typically a heat treatment at 250°C to 500°C, is performed in an atmosphere containing a substance that serves as a source of hydrogen atoms. Nitrogen in the oxide semiconductor layer inhibits the atoms constituting the oxide semiconductor layer from being densely packed in the film and has the effect of promoting the diffusion and solid solution of hydrogen into the film. Therefore, by this heat treatment, hydrogen is introduced into the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element at a higher concentration than the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. As a result, the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element becomes lower than the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. Also, one aspect of the present invention has a resistive element and a thin film transistor formed using an oxide semiconductor layer containing nitrogen at a high concentration. Further, a silicon oxide layer that functions as a barrier layer is provided on the thin film transistor. At this stage, a heat treatment at 200°C to 600°C, typically a heat treatment at 250°C to 500°C, is performed in an atmosphere containing a substance that serves as a source of hydrogen atoms. Nitrogen in the oxide semiconductor layer inhibits the atoms constituting the oxide semiconductor layer from being densely packed in the film and has the effect of promoting the diffusion and solid solution of hydrogen into the film. Therefore, by this heat treatment, hydrogen is introduced into the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element at a higher concentration than the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. As a result, the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element becomes lower than the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. Also, one aspect of the present invention has a resistive element and a thin film transistor formed using an oxide semiconductor layer containing nitrogen at a high concentration. Further, a silicon oxide layer that functions as a barrier layer is provided on the thin film transistor. At this stage, a heat treatment at 200°C to 600°C, typically a heat treatment at 250°C to 500°C, is performed in an atmosphere containing a substance that serves as a source of hydrogen atoms. Nitrogen in the oxide semiconductor layer inhibits the atoms constituting the oxide semiconductor layer from being densely packed in the film and has the effect of promoting the diffusion and solid solution of hydrogen into the film. Therefore, by this heat treatment, hydrogen is introduced into the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element at a higher concentration than the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. As a result, the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistive element becomes lower than the resistance value of the oxide semiconductor layer containing nitrogen at a high concentration applied to the thin film transistor. That is, one aspect of the present invention is a resistive element in which a first oxide semiconductor layer containing nitrogen at a high concentration is applied as a resistive component, and a thin film transistor in which the hydrogen concentration is lower than that of the first oxide semiconductor layer and which contains nitrogen at a high concentration. That is, one aspect of the present invention is a resistive element in which a first oxide semiconductor layer containing nitrogen at a high concentration is applied as a resistive component, and a thin film transistor in which the hydrogen concentration is lower than that of the first oxide semiconductor layer and which contains nitrogen at a high concentration. That is, one aspect of the present invention is a resistive element in which a first oxide semiconductor layer containing nitrogen at a high concentration is applied as a resistive component, and a thin film transistor in which the hydrogen concentration is lower than that of the first oxide semiconductor layer and which contains nitrogen at a high concentration.

[0019] That is, one aspect of the present invention is a resistive element in which a first oxide semiconductor layer containing nitrogen at a high concentration is applied as a resistive component, and a thin film transistor in which the hydrogen concentration is lower than that of the first oxide semiconductor layer and which contains nitrogen at a high concentration. That is, one aspect of the present invention is a resistive element in which a first oxide semiconductor layer containing nitrogen at a high concentration is applied as a resistive component, and a thin film transistor in which the hydrogen concentration is lower than that of the first oxide semiconductor layer and which contains nitrogen at a high concentration. A thin film transistor having a second oxide semiconductor layer containing therein applied to a channel formation region is a logic circuit to be described below.

[0020] Note that the oxide semiconductor layer containing nitrogen at a high concentration means that the ratio of nitrogen (N) to oxygen (O) (N / O) is in the range of 0.05 or more and 0.8 or less, preferably 0.1 or more and 0.5 or less. This refers to the oxide semiconductor layer.

[0021] Furthermore, a configuration in which a silicon nitride layer formed by a plasma CVD method using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided so as to be in direct contact with the oxide semiconductor layer containing nitrogen at a high concentration applied to the resistance element is also one aspect of the present invention.

[0022] That is, one aspect of the present invention is a logic circuit having a silicon oxide layer provided on the second oxide semiconductor layer, and a silicon nitride layer provided on the first oxide semiconductor layer and the silicon oxide layer, in the above-described configuration.

[0023] In this document (specification, claims, drawings, etc.), the "film" refers to a film formed on the entire surface of the substrate, which is in a state before being processed into a desired shape by a photolithography process or the like later. And the "layer" refers to a layer formed by processing into a desired shape by a photolithography process or the like from the "film", and a layer intended to be formed on the entire surface of the substrate.

[0024] In this document (specification, claims, drawings, etc.), when A and B are connected, it means that in addition to A and B being directly connected, those that are electrically connected. ​​​​​​​​​​​It is assumed to include. Here, when A and B are electrically connected, it means that when there is an object having any electrical action between A and B, A and B are generally the same node through the object. It is assumed to represent the case where they become.

[0025] Specifically, when A and B are connected through a switching element such as a transistor, and A and B become substantially the same potential due to the conduction of the switching element, or when A and B are connected through a resistance element, and the potential difference generated at both ends of the resistance element does not affect the operation of the circuit including A and B, etc., when considering the circuit operation, it represents the case where A and B can be regarded as the same node without any problem.

[0026] Note that since the source terminal and the drain terminal of the thin film transistor change depending on the structure of the thin film transistor, the operating conditions, etc., it is difficult to specify which is the source terminal or the drain terminal. Therefore, in this document (specification, claims, drawings, etc.), one of the source terminal and the drain terminal is denoted as the first terminal, and the other of the source terminal and the drain terminal is denoted as the second terminal and distinguished.

Advantages of the Invention

[0027] According to one aspect of the present invention, the hydrogen concentration of the oxide semiconductor layer applied to the resistance component of the resistance element can be made higher than the hydrogen concentration of the oxide semiconductor layer applied to the channel formation region of the thin film transistor. Therefore, the resistance value of the oxide semiconductor layer can be selectively reduced. As a result, there is no need to separately provide a manufacturing process for the thin film transistor and a manufacturing process for the resistance element, and a logic circuit with a reduced manufacturing process, and a semiconductor device including the logic circuit ​​​​​​​​A setting can be provided.

Brief Description of the Drawings

[0028]

Figure 1

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Figure 11

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Figure 20

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Figure 22

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Figure 28

Embodiments for Carrying Out the Invention

[0029] Embodiments of the invention disclosed below will be exemplified with reference to the drawings. However, the disclosed invention is not limited to the following embodiments, and those skilled in the art can easily understand that the forms and details thereof can be variously changed without departing from the spirit and scope of the invention. Therefore, the disclosed invention should not be construed as being limited to the description of the embodiments shown below. In the embodiments exemplified below, the same reference numerals may be used commonly among different drawings when referring to the same thing.

[0030] (Embodiment 1) In this embodiment, an example of a display device including a driving circuit manufactured using an oxide semiconductor will be described with reference to FIGS. 1 to 16. Specifically, a pixel portion of the display device is driven ​As an example of a source line drive circuit and a gate line drive circuit which are drive circuits for it, a drive circuit having an inverter (hereinafter referred to as an ER MOS circuit) formed by combining an enhancement type thin film transistor and a resistance element will be described. In the present embodiment, as a thin film transistor constituting a unipolar drive circuit, an example in which an n-channel type thin film

[0031] transistor is applied is shown. Note that the display device refers to a device having a display element such as a light emitting element or a liquid crystal element. The display device may include a peripheral drive circuit for driving a plurality of pixels. Further, the peripheral drive circuit for driving a plurality of pixels is formed on the same substrate as the plurality of pixels. Further, the display device may include a flexible print circuit (Flexible Print Circuit: F PC). Furthermore, the display device may include a printed wiring board (PWB) connected via a flexible print circuit board (FPC) or the like, to which an IC chip, a resistance element, a capacitance element, an inductor, a transistor, etc. are attached. Furthermore, the display device may include an optical

[0032] sheet such as a polarizing plate or a retardation plate, a lighting device, a housing, an audio input / output device, or a photosensor, etc. In FIG. 1, an overall view of the display device is shown. On a substrate 100, a source line drive circuit 101, a first gate line drive circuit 102A, a second gate line drive circuit 102B, and a pixel portion 103 are integrally formed. In the pixel portion 103, a portion surrounded by a dotted line frame In the pixel of the display device, the display element is controlled by a thin film transistor. The source line drive circuit 101, the first gate line drive circuit 102A, and the second gate line drive circuit 102 B are driven by signals (such as a clock signal and a start pulse), which are input from the outside through the flexible printed circuit boards (Flexible Print Circuit: FPC) 104A and 104B.

[0033] The source line drive circuit and the gate line drive circuit for driving the pixel portion have logic circuits such as an inverter circuit composed of thin film transistors, capacitive elements, resistive elements, etc. and are configured using them. When forming an inverter circuit using unipolar thin film transistors, there are cases of forming it by combining an enhancement type thin film transistor and a depletion type thin film transistor (hereinafter referred to as an EDMOS circuit), forming it by enhancement type thin film transistors (hereinafter referred to as an EEMOS circuit), and an ERMOS circuit. When the threshold voltage of an n-channel type thin film transistor is positive, it is defined as an enhancement type transistor, and when the threshold voltage of an n-channel type thin film transistor is negative, it is defined as a depletion type transistor, and this definition shall be followed throughout this specification. When an enhancement type transistor with a positive threshold voltage is applied as the thin film transistor provided in the pixel portion, the current flowing due to the voltage applied between the gate terminal and the source terminal can be made smaller than that of a depletion type transistor, and low power consumption can be achieved. Also, as the thin film transistor used in the drive circuit for driving the pixel portion

[0034] ​​​​​​​​It is preferable to use an enhancement-type thin-film transistor that is the same as the pixel portion. In using an enhancement-type thin-film transistor as the thin-film transistor of the inverter circuit By doing so, since the type of transistor when manufacturing the pixel portion and the drive circuit becomes one type, The manufacturing process can be reduced. Note that the enhancement-type transistor uses an oxide semiconductor, and its electrical characteristics are such that the on / off ratio is 10 or more when the gate voltage is from -20V to 20V. Therefore, the leakage current between the source terminal and the drain terminal is small, 9 and low-power consumption driving can be realized.

[0035] Note that the oxide semiconductor used in this document (specification, claims, drawings, etc.) is I nMO3(ZnO) m (m>0) to form a thin film, and a semiconductor element is manufactured using the thin film. Note that M represents one metal element or a plurality of metal elements selected from gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and cobalt (Co). For example, in addition to the case where M is gallium (Ga), there may be cases where gallium (Ga) and nickel (Ni) or gallium (Ga) and iron (Fe) are included, i.e., cases where metal elements other than gallium (Ga) are included. Also, in the above oxide semiconductor, in addition to the metal elements included as M, as impurity elements, iron (Fe), nickel (Ni), other transition metal elements, or oxides of the transition metals may be included. In addition, the sodium (Na) contained in the above oxide semiconductor is 5×10 or less (atoms / cm ), preferably 1×10 1 (atoms / cm ). 18 (atoms / cm 3 ) or less, preferably 1×10 1 8 (atoms / cm 3 ​)It is assumed as follows. In this document (specification, claims, or drawings, etc.), this thin film is also referred to as an In-Ga-Zn-O-based non-single crystal film.

[0036] Typical measurement examples by Inductively Coupled Plasm a Mass Spectrometry (ICP-MS analysis) are shown in Table 1. A target with a molar ratio of In2O3:Ga2O3:ZnO = 1:1:1 (In:Ga:Zn = 1:1:0.5) was used, and the oxide semiconductor film obtained under Condition 1 with a pressure of 0.4 Pa, a DC power supply of 5 00 W, an argon gas flow rate of 10 sccm, and oxygen of 5 sccm is InGa Zn O 0.94 Zn 0.40 O 3.31 . Also, the oxide semiconductor film obtained under Condition 2 in which only the film formation atmosphere conditions were changed from the above conditions to an argon gas flow rate of 40 sccm and oxygen of 0 sccm is InGa Zn O 0.95 Zn 0.41 O 3.33 .

[0037]

Table 1

[0038] Also, the results of quantification with the measurement method changed to Rutherford Backsc attering Spectrometry (RBS analysis) are shown in Table 2.

[0039]

Table 2

[0040] As a result of measuring the sample of Condition 1 by RBS analysis, the oxide semiconductor film is InGa0.92 Zn 0.45 O 3.86 It is. Further, as a result of measuring the sample of Condition 2 by RBS analysis, the oxide semi conductor film is InGa 0.93 Zn 0.44 O 3.49 It is.

[0041] The crystal structure of the In-Ga-Zn-O based non-single crystal film, after film formation by the sputtering method, even when heat treatment is performed at 200 °C ~500 °C, typically 300~400 °C for 10 minutes to 100 minutes, an amorphous structure is observed by XRD (X-ray diffraction) analysis. Also, the electrical characteristics of the thin film transistor also have an on-off ratio of 10 when the gate voltage is from -20V to 20V 9 or more, and the mobility is 10 or more can be fabricated. A thin film transistor fabricated using an oxide semiconductor layer having such electrical characteristics has a higher mobility than a thin film trans istor fabricated using amorphous silicon, and can drive a drive circuit composed of a shift register at high speed It can be done. Next, a circuit diagram of a gate line drive circuit and a source line drive circuit using an ERMOS circuit will be shown and explained with an example.

[0042] First, the configuration of a source line drive circuit using an ERMOS circuit as an inverter circuit will be explained.

[0043] First, the configuration of a source line drive circuit using an ERMOS circuit as an inverter circuit will be explained.

[0044] FIG. 2 is a diagram showing the configuration of the source line drive circuit 101 in the display device shown in FIG. 1 The source line drive circuit includes a clock signal level shifter 201, a start pulse level shifter 202, a pulse output circuit 203 that constitutes a shift register 251, a NAND circuit 2 04. It has a buffer 205 and a sampling switch 206, and the signals input from the outside are the first clock signal (CLK1), the second clock signal (CLK2), the start pulse (SP), and the analog video signal (Video). Among these, regarding the first clock signal (CLK1), the second clock signal (CLK2), and the start pulse (SP), immediately after being input as a signal with a low voltage amplitude from the outside, they undergo amplitude conversion by the level shifter 201 or 2 02 and are input to the drive circuit as signals with a high voltage amplitude.

[0045] In addition, the source line drive circuit in the display device of this embodiment is such that the sampling pulse output from one stage of the pulse output circuit in the shift register drives the sampling switch 206, simultaneously sampling the analog video signals for 12 columns of the source signal lines. Hereinafter, an example will be described. In addition, it may also be configured to input a scan direction switching signal or the like for switching the scan direction. Also, in this embodiment, an example is shown in which the drive is performed by two-phase clock signals, the first clock signal (CLK1) and the second clock signal (CLK2), as the clock signals, but it may also be configured to drive the drive circuit by inputting clock signals other than two-phase.

[0046] Figs. 3(A) and (B) show the configuration of a plurality of pulse output circuits 203 included in the shift register 251. The pulse output circuit 300 includes a first switch 301 connected to the terminal to which the start pulse SP is input, a first inverter circuit 302 that inverts and outputs the signal input through the first switch 301, and the signal output from the first inverter circuit 302 A second inverter circuit 303 and a third inverter circuit 305 that invert and output, and the first A second switch 304 connected to a terminal to which a signal output from the second inverter circuit 303 is input. It consists of

[0047] In the circuit diagram shown in Fig. 3(A), the block indicated by the dotted line is a pulse output circuit 350 that outputs one stage of sampling pulses. The shift register in Fig. 3(A) is composed of N stages (N is a natural number) of pulse output circuits. Output signals out1 to outN are output from the output terminals of the respective third inverter circuits 305. In the pulse output circuit of the next stage after the first stage described above, between the first switch 3 01 and the second switch 304, the wiring for inputting the input first clock signal and the second clock signal is switched and connected. From the third stage onwards, the wiring for alternately inputting the first clock signal and the second clock signal is alternately switched and connected between the first switch 301 and the second switch 304.

[0048] Fig. 3(B) shows the circuit configuration of the pulse output circuit in detail. The pulse output circuit body has thin film transistors 351, 353, 355, 356, 358, and resistor elements 35 2, 354, 357. Also, the pulse output circuits 331 of odd stages and the pulse output circuits 332 of even stages are connected to a wiring 359 for supplying the first clock signal (CLK1) and a wiring 360 for supplying the second clock signal (CLK2). Below Taking the pulse output circuit 331 of the first stage as an example, the specific connection relationship of the semiconductor elements will be described.

[0049] ​​​ The first terminal of the thin film transistor 351 is connected to the terminal to which the start pulse SP is input, and the gate terminal is connected to the wiring 359. One terminal of the resistor element 352 is connected to the wiring (also referred to as the high power supply potential line) to which the high power supply potential VDD is supplied.

[0050] One terminal of the resistor element 352 is connected to the wiring (also referred to as the high power supply potential line) to which the high power supply potential VDD is supplied. One terminal of the resistor element 352 is connected to the wiring (also referred to as the high power supply potential line) to which the high power supply potential VDD is supplied.

[0051] The first terminal of the thin film transistor 353 is connected to the other terminal of the resistor element 352, the gate terminal is connected to the second terminal of the thin film transistor 351, and the second terminal is connected to the wiring (also referred to as the low power supply potential line) to which the low power supply potential VSS is supplied. The first terminal of the thin film transistor 353 is connected to the other terminal of the resistor element 352, the gate terminal is connected to the second terminal of the thin film transistor 351, and the second terminal is connected to the wiring (also referred to as the low power supply potential line) to which the low power supply potential VSS is supplied. The first terminal of the thin film transistor 353 is connected to the other terminal of the resistor element 352, the gate terminal is connected to the second terminal of the thin film transistor 351, and the second terminal is connected to the wiring (also referred to as the low power supply potential line) to which the low power supply potential VSS is supplied.

[0052] One terminal of the resistor element 354 is connected to the high power supply potential line.

[0053] The first terminal of the thin film transistor 355 is connected to the other terminal of the resistor element 354, the gate terminal is connected to the other terminal of the resistor element 352 and the first terminal of the thin film transistor 353, and the second terminal is connected to the low power supply potential line. The first terminal of the thin film transistor 355 is connected to the other terminal of the resistor element 354, the gate terminal is connected to the other terminal of the resistor element 352 and the first terminal of the thin film transistor 353, and the second terminal is connected to the low power supply potential line. The first terminal of the thin film transistor 355 is connected to the other terminal of the resistor element 354, the gate terminal is connected to the other terminal of the resistor element 352 and the first terminal of the thin film transistor 353, and the second terminal is connected to the low power supply potential line.

[0054] The first terminal of the thin film transistor 356 is connected to the other terminal of the resistor element 354 and the first terminal of the thin film transistor 355, the gate terminal is connected to the wiring 360, and the second terminal is connected to the second terminal of the thin film transistor 351 and the gate terminal of the thin film transistor 353. The first terminal of the thin film transistor 356 is connected to the other terminal of the resistor element 354 and the first terminal of the thin film transistor 355, the gate terminal is connected to the wiring 360, and the second terminal is connected to the second terminal of the thin film transistor 351 and the gate terminal of the thin film transistor 353. The first terminal of the thin film transistor 356 is connected to the other terminal of the resistor element 354 and the first terminal of the thin film transistor 355, the gate terminal is connected to the wiring 360, and the second terminal is connected to the second terminal of the thin film transistor 351 and the gate terminal of the thin film transistor 353. One terminal of the resistor element 357 is connected to the high power supply potential line, and the other terminal is connected to the first terminal of the thin film transistor 351 in the second-stage pulse output circuit 332.

[0055] One terminal of the resistor element 357 is connected to the high power supply potential line, and the other terminal is connected to the first terminal of the thin film transistor 351 in the second-stage pulse output circuit 332. One terminal of the resistor element 357 is connected to the high power supply potential line, and the other terminal is connected to the first terminal of the thin film transistor 351 in the second-stage pulse output circuit 332.

[0056] The first terminal of the thin film transistor 358 is connected to the other terminal of the resistor element 357 and the second-stage pulse is connected to the first terminal of the thin film transistor 351 in the S output circuit 332, and the gate terminal is , the other terminal of the resistance element 352, the first terminal of the thin film transistor 353, and the thin film trans is connected to the gate terminal of the star 355, and the second terminal is connected to the low power supply potential line.

[0057] The connection of the wiring 359 and the wiring 360 of the second-stage pulse output circuit is also the same as that of the first-stage pulse output circuit , except that it is reversed. The odd-stage pulse output circuits 331 and the even-stage pulse output circuits 332 are also sequentially connected according to this.

[0058] In FIG. 3(B), the thin film transistor 351 corresponds to the first switch 301 shown in FIG. 3(A). The resistance element 352 and the thin film transistor 353 correspond to the first inverter circuit 302 shown in FIG. 3(A), and the first inverter circuit 302 is an ERMOS circuit . The resistance element 354 and the thin film transistor 355 correspond to the second inverter circuit 303 shown in FIG. 3(A), and the second inverter circuit 303 is an ERMOS circuit. The thin film trans istor 356 corresponds to the second switch 304 shown in FIG. 3(A). The resistance element 3 57 and the thin film transistor 358 correspond to the third inverter circuit 305 shown in FIG. 3(A) , and the third inverter circuit 305 is an ERMOS circuit.

[0059] Note that the thin film transistors 351 and 356 are preferably composed of enhancement type transistors in the same manner as the thin film transistors 353, 355, and 358 . By using an enhancement type transistor as the switch, the off-current of the transistor can be reduced , so that low power consumption can be achieved and the manufacturing process can be reduced . It is.

[0060] Here, referring to the timing chart shown in FIG. 4, the circuit operation of the circuits shown in FIGS. 3(A) and (B) will be described. For the sake of explanation in FIG. 4, in the first-stage pulse output circuit as a node in the circuit shown in FIG. 3(B), the second terminal of the thin-film transistor 351 is the node A (shown as A in FIGS. 3(B) and 4), the other terminal of the resistance element 352 is the node B (shown as B in FIGS. 3 (B) and 4), the other terminal of the resistance element 354 is the node C (shown as C in FIGS. 3(B) and 4), and the other terminal of the resistance element 357 is the node out1 (shown as out1 in FIGS. 3(B) and 4).

[0061] Also, as a node in the circuit shown in FIG. 3(B), in the second-stage pulse output circuit, the second terminal of the thin-film transistor 351 is the node D (shown as D in FIGS. 3(B) and 4), the other terminal of the resistance element 352 is the node E (shown as E in FIGS. 3(B) and 4), the other terminal of the resistance element 354 is the node F (shown as F in FIGS. 3(B) and 4), and the other terminal of the resistance element 357 is the node out2 (shown as out2 in FIGS. 3(B) and 4). Also, as a node in the circuit shown in FIG. 3(B ), in the third-stage pulse output circuit, the second terminal of the thin-film transistor 35 1 is the node G (shown as G in FIGS. 3(B) and 4).

[0062] In FIG. 4, during the period T1, the operation when the start pulse SP is at the H level, the first clock signal (CLK1 ) is at the H level, and the second clock signal (CLK2) is at the L level will be described .

[0063] When the first clock signal (CLK1) becomes at the H level, the first-stage pulse output circuit's​ The thin film transistor 351 turns on.

[0064] Then, the H level, which is the voltage level of the start pulse, raises the voltage level of node A to the H level.

[0065] Then, as the voltage level of node A rises to the H level, the thin film transistor 353 of the first-stage pulse output circuit turns on.

[0066] Then, the L level, which is the voltage level of the low power supply potential, lowers the voltage level of node B to the L level.

[0067] Then, as the voltage level of node B drops to the L level, the thin film transistors 355 and 358 of the first-stage pulse output circuit turn off.

[0068] Then, as the thin film transistor 355 of the first-stage pulse output circuit turns off, the H level, which is the voltage level of the high power supply potential, raises the voltage level of node C to the H level. Also, as the thin film transistor 358 of the first-stage pulse output circuit turns off, the H level, which is the voltage level of the high power supply potential, raises the voltage level of node out1 to the H level.

[0069] Note that since the second clock signal (CLK2) is at the L level, the thin film transistors 356 of the first-stage pulse output circuit and 351 of the second-stage pulse output circuit are off.

[0070] Next, in FIG. 4, during period T2, the start pulse SP is at the L level, the first clock signal (CL ​​​​​​​​​​The operation when the first clock signal is at the L level and the second clock signal is at the H level will be described.

[0071] When the first clock signal becomes the L level, the thin-film transistor 351 of the first-stage pulse output circuit turns off. On the other hand, since the second clock signal (CLK2) is at the H level, the thin-film transistor 356 of the first-stage pulse output circuit turns on. Therefore, depending on the voltage level of node C that was at the H level during period T1, the voltage level of node A will hold the H level. And each node of the first-stage pulse output circuit will hold the same level as during period T1.

[0072]

[0073] On the other hand, when the second clock signal (CLK2) becomes the H level, the thin-film transistor 351 of the second-stage pulse output circuit turns on.

[0074] And the H level, which is the voltage level of node out1, raises the voltage level of node D to the H level.

[0075] And when the voltage level of node D rises to the H level, the thin-film transistor 353 of the second-stage pulse output circuit turns on.

[0076] And the L level, which is the voltage level of the low power supply potential, lowers the voltage level of node E to the L level.

[0077] And when the voltage level of node E drops to the L level, the thin-film transistors 355 and 358 of the second-stage pulse output circuit turn off.

[0078] ​​​​​​​​​​ Then, when the thin film transistor 355 of the second-stage pulse output circuit turns off, the H level, which is the voltage level of the high power supply potential, raises the voltage level of node F to the H level. Also, when the thin film transistor 358 of the second-stage pulse output circuit turns off, the H level, which is the voltage level of the high power supply potential, raises the voltage level of node out2 to the H level.

[0079] Since the first clock signal (CLK1) is at the L level, the thin film transistors 356 of the second-stage pulse output circuit and 351 of the third-stage pulse output circuit are in the off state.

[0080] Next, in FIG. 4, during period T3, the operation when the start pulse SP is at the L level, the first clock signal (CLK1) is at the H level, and the second clock signal is at the L level will be described.

[0081] When the first clock signal becomes the H level, the thin film transistor 351 of the first-stage pulse output circuit turns on. On the other hand, since the second clock signal (CLK2) is at the L level, the thin film transistor 356 of the first-stage pulse output circuit is in the off state. Therefore, the voltage level of node A will drop to the L level.

[0082] Then, when the voltage level of node A drops to the L level, the thin film transistor 353 of the first-stage pulse output circuit turns off.

[0083] And the H level, which is the voltage level of the high power supply potential, raises the voltage level of node B to the H level.

[0084] Then, as the voltage level of Node B rises to the H level, a first-stage pulse output The thin-film transistor 355 of the circuit and the thin-film transistor 358 of the first-stage pulse output circuit become in the on state.

[0085] Then, as the thin-film transistor 355 of the first-stage pulse output circuit becomes in the on state the L level, which is the voltage level of the low power supply potential, causes the voltage level of Node C to drop to the L level and as the thin-film transistor 358 of the first-stage pulse output circuit becomes in the on state, the L level, which is the voltage level of the low power supply potential, causes the voltage level of Node out1 to drop to the L level and decrease it.

[0086] Note that since the second clock signal (CLK2) is at the L level, the thin-film transistor 356 of the first-stage pulse output circuit is in the off state.

[0087] Also, similar to the first-stage pulse output circuit during period T2, when the second clock signal becomes at the L level the thin-film transistor 351 of the second-stage pulse output circuit becomes in the off state. On the other hand, since the first clock signal (CLK1) is at the H level, the thin-film transistor 356 of the second-stage pulse output circuit is in the on state. Therefore, due to the voltage level of Node F that was at the H level during period T2 the voltage level of Node D will be maintained at the H level.

[0088] And each node of the second-stage pulse output circuit will maintain the same level as during period T2 and become so.

[0089] On the other hand, as the first clock signal (CLK1) becomes at the H level, the thin-film transistor 351 of the third-stage pulse output circuit becomes in the on state.

[0090] Then, the H level, which is the voltage level of node out2, raises the voltage level of node G to the H level.

[0091] Then, as the voltage level of node G rises to the H level, the thin-film transistor 353 of the third-stage pulse output circuit turns on.

[0092] Hereinafter, by sequentially controlling the on and off of the transistors, it can be driven as a shift register.

[0093] In addition, in the pulse output circuit described with reference to FIGS. 3(A) and 3(B), a configuration is shown in which a thin-film transistor 356 (second switch 304) is provided between node A and node C. This is because it is considered that the voltage level of node C drops from the high voltage potential VDD due to the resistance element 354. By disconnecting and driving the connection between node A and node C by the thin-film transistor 356 (second switch 304), it is preferable because the driving ability of the thin-film transistor 353 by the potential of node A can be enhanced. Even if the configuration does not include the thin-film transistor 356 (second switch 304), the circuit of the present embodiment can be driven.

[0094] In addition, in the configuration of the source line driving circuit, a negative logic product (NAND) of the signals output from each pulse output circuit is taken to generate a signal for driving each source line. Therefore, in the source line driving circuit, it is preferable to provide a pulse output circuit having a number more than the number of source lines and configure it to generate a signal for outputting to the source line.

[0095] ​​​​​​​​​FIG. 5(A) shows a configuration example of the clock signal level shifter 201 shown in FIG. 2. . In FIG. 5(A), since the configurations of the level shifter for the first clock signal (CLK1) and the level shifter for the second clock signal (CLK2) are the same, only the level shifter for the first clock signal (C LK1) is shown. In FIG. 5(A), the first clock signal (CL K1) is amplitude-converted by the ERMOS circuit (Stage1), and buffer stages (S tage2, Stage3) are provided thereafter.

[0096] The operation of the circuit shown in FIG. 5(A) will be described. Here, the potential of the power supply used is three potentials of VSS, VDD0, and VDD, and VSS < VDD0 < VDD. The amplitude of the first clock signal (CLK1) is level-shifted at the source line drive circuit input section, and by doing so, low power consumption and noise reduction can be achieved.

[0097] From the signal input section (CLK in1), the first input clock signal (CLK1) having an amplitude of L level / H level = VSS / VDD0 is input.

[0098] When the first input clock signal is at the H level, the thin film transistor 602 is turned on. . Here, the on-resistance of the thin film transistor 602 is designed to be sufficiently lower than the resistance value of the resistance element 601. Therefore, the node α becomes the L level.

[0099] When the node α is at the L level, the thin film transistor 604 is turned off. Here, the off-resistance of the thin film transistor 604 is designed to be sufficiently higher than the resistance value of the resistance element 603. Therefore, the node β becomes the H level, and the H level becomes approximately the same as VDD. As described above, Thus, the amplitude conversion is completed.

[0100] The level shifter described with reference to FIG. 5(A) provides a buffer stage (Stage2, S tage3) after the level shifter circuit (Stage1) in consideration of the load on the pulse after amplitude conversion. Through similar operations in Stage2 and Stage3, a pulse is finally output to the signal output section.

[0101] Note that FIG. 5(A) shows the level shifter for the first clock signal (CLK1), and the level shifter for the start pulse (SP) has the same configuration.

[0102] FIG. 5(B) shows the state of amplitude conversion of the clock signal. The amplitude of the input signal is , L level / H level = VSS / VDD0, and the amplitude of the output signal is L level / H level = VSS / VDD.

[0103] FIG. 5(C) shows the state of amplitude conversion of the start pulse (SP). The amplitude of the input signal is the same as that of the clock signal, L level / H level = VSS / VDD0, and the amplitude of the output signal is L level / H level = VSS / VDD.

[0104] FIG. 6(A) shows the two-input NAND circuit 204 shown in FIG. 2. The configuration of the NAND circuit 204 is similar to that of the ERMOS circuit. Specifically, the signal input section in the ERMOS circuit has two inputs, and the difference lies in the fact that the thin film transistors 702 and 703 are arranged in series. When both H levels are input to the signal input section (In1) and the signal input section (In2),

[0105] ​​​​​​, since the thin film transistors 702 and 703 are in the on state, an L level appears at the signal output part (Out).

[0106] On the other hand, when an L level is input to either one or both of the signal input part (In1) and the signal input part (In2), an H level of the potential VDD appears at the signal output part (Out).

[0107] FIG. 6(B) shows the buffer 205 shown in FIG. 2. The buffer 205 is composed of an ERMO S circuit (Stage1~4). Regarding the operation of the ERMOS circuit, it has been described in the section of the level shifter circuit, so the above description is incorporated herein.

[0108] FIG. 6(C) shows the sampling switch 206 shown in FIG. 2. The sampling switch 206 receives a sampling pulse from the signal input part (25), and 12 thin film transistors 731 arranged in parallel are simultaneously controlled. An analog video signal is input to the input electrodes (1)~(12) of the 12 thin film transistors 731, and it functions to write the potential of the video signal when the sampling pulse is input to the source signal line.

[0109] FIG. 7 is a diagram showing the circuit configuration of the gate line driving circuit in the display device shown in FIG. 1 . It has a level shifter 751 for a clock signal, a level shifter 752 for a start pulse, a pulse output circuit 753, a NAND circuit 754, and a buffer 755 that constitute a shift register 781. has.

[0110] The gate line driving circuit receives a first clock signal (CLK1), a second clock signal (CL K2), and a start pulse (SP). These input signals are low voltage oscillations from the outside Immediately after being input as a signal of amplitude, it is subjected to amplitude conversion by the level shifter 751 for the clock signal and the level shifter 752 for the start pulse, and is input to the drive circuit as a signal of high voltage amplitude.

[0111] Note that regarding the configuration and operation of the level shifter 751 for the clock signal, the level shifter 752 for the start pulse, the pulse output circuit 753, the NAND circuit 754, and the buffer 755, they are the same as those used in the source line drive circuit, so the above description is incorporated herein.

[0112] Next, examples of the layout diagrams of the pulse output circuits shown in Fig. 3(B) are shown in Figs. 8 to 10. Note that Figs. 8 to 10 show the pulse output circuit corresponding to the first stage among the pulse output circuits formed in multiple stages.

[0113] The pulse output circuits in Figs. 8 to 10 are composed of a power supply line 801, a power supply line 802, a control signal line 803, a control signal line 804, a control signal line 805, thin film transistors 351, 353, 355, 356, 358, and resistance elements 352, 354, 357.

[0114] In Figs. 8 to 10, an oxide semiconductor layer 806, a first wiring layer 807, a second wiring layer 808, and a contact hole 809 are shown. Note that the first wiring layer 807 is a layer including the gate terminal of the thin film transistor, and the second wiring layer 808 is a layer including the source terminal and the drain terminal (the first terminal and the second terminal) of the thin film transistor.

[0115] Also, regarding the connection relationship of each circuit element in Figs. 8 to 10, it is the same as that in Fig. 3(B). ​​​​​​​​​​​​That is, the power supply line 801 is a wiring to which the high power supply potential VDD is supplied (also referred to as a high power supply potential line). The power supply line 802 is a wiring to which the low power supply potential VSS is supplied (also referred to as a low power supply potential line). The control signal line 803 is a wiring to which a start pulse (SP) is supplied. The control signal line 804 is a wiring to which the first clock signal is supplied. The control signal line 805 is a wiring to which the second clock signal is supplied.

[0116] For the resistance elements 352, 354, and 357 of the ERMOS circuit shown in FIG. 8, a rectangular oxide semiconductor layer is applied. Therefore, the resistance elements 352, 354, and 357 shown in FIG. 8 are resistance elements with a wide current path width and high current driving ability. For the resistance elements 352, 354, and 357 of the ERMOS circuit shown in FIGS. 9 and 10, a meander shape (serpentine shape) of oxide semiconductor layer is applied. By making it in a meander shape, it is possible to increase the resistance values of the resistance elements 352, 3 54, and 357.

[0117] In the layout diagrams of the pulse output circuits in FIGS. 8 to 10, the channel regions of the thin film transistors 3 51, 353, 355, 356, and 358 may be U-shaped. Also, in FIG. 8, the sizes of the thin film transistors are shown to be the same size, but the sizes of the thin film transistors may be appropriately changed according to the size of the load in the subsequent stage.

[0118] Next, the structure of the inverter circuit composed of the resistance element 354 and the thin film transistor 355 in the layout diagrams described in FIGS. 8 to 10 will be described with reference to FIGS. 11(A) to (C). Note that the resistance element 354 and the thin film transistor shown in FIGS. 11(A) to (C) 355 will be described using FIGS. 11(A) to (C). ​​​The resistor 355 shows cross-sectional views corresponding to the dotted lines A-B and C-D in FIGS. 8 to 10, respectively. This will be described below.

[0119] FIG. 11(A) is a cross-sectional view corresponding to the dotted lines A-B and C-D in FIG. 8. In FIG. 11( A), the resistor element 354 uses the first oxide semiconductor layer 905 as a resistance component. One end of the first oxide semiconductor layer 905 is connected to the first wiring 901 included in the first wiring layer 807 through the contact hole 904 provided in the insulating layer 903, and the other end is connected to the second wiring 907 included in the second wiring layer 808.

[0120] In FIG. 11(A), the thin film transistor 355 includes a gate terminal 902 on a substrate, an insulating layer 903 on the gate terminal 902 that functions as a gate insulating layer, a second oxide semiconductor layer 906 on the insulating layer 903 that serves as a channel formation region, a second wiring 907 and a third wiring 908 on the second oxide semiconductor layer 906 that function as a source terminal and a drain terminal (a first terminal and a second terminal). Note that the first wiring 901 is one terminal for the resistor element 354. Also, the second wiring 907 is the other terminal for the resistor element 354, is the first terminal for the thin film transistor 355, and is also the wiring connecting the two. Similarly, the third wiring 90

[0121] 8 is the second terminal for the thin film transistor 355 and is also the wiring to which the low power supply potential VSS is supplied (also referred to as a low voltage potential line). In other words, a part of the connection wiring and the low (high) power supply potential line is used as the first terminal or the second terminal of each thin film transistor. 8 is the second terminal for the thin film transistor 355 and is also the wiring to which the low power supply potential VSS is supplied (also referred to as a low voltage potential line). That is, a part of the connection wiring and the low (high) power supply potential line is used as the first terminal or the second terminal of each thin film transistor. .

[0122] Also, in FIG. 11(A), the film thicknesses of the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are not uniform. Specifically, the film thicknesses of the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 corresponding to the region overlapping with the second wiring 907 and the third wiring 908 are greater than the film thicknesses of the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 not corresponding to the region. This is because in the etching when forming the second wiring 907 and the third wiring 908, a part of the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 is also etched.

[0123] FIG. 11(B) is a cross-sectional view corresponding to the dotted lines A-B and C-D in FIG. 9. In FIG. 11( B), the resistance element 354 uses the first oxide semiconductor layer 90 5 formed in a meander shape as a resistance component. Also, one end of the first oxide semiconductor layer 905 is connected via a contact hole 904 provided in the first wiring 901 and the insulating layer 903, and the other end is connected to the second wiring 907. Since the structure of the thin film transistor is the same as the thin film transistor described in FIG. 11(A), the above description is incorporated by reference.

[0124] FIG. 11(C) is a cross-sectional view corresponding to the dotted lines A-B and C-D in FIG. 10. In FIG. 11 (C), the resistance element 354 uses the first oxide semiconductor layer 9 05 formed in a meander shape as a resistance component. Also, one end of the first oxide semiconductor layer 905 is connected to the fourth wiring 912 included in the second wiring layer 808, and the other end is connected to the second wiring 907 included in the second wiring layer 808. Since the structure of the thin film transistor is the same as the thin film transistor described in FIG. 11(A), the description is as follows. in FIG. 11(A) is incorporated by reference. Since it is the same as the thin-film transistor described above, the foregoing description is incorporated by reference. As shown in FIG. 11(C) For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring.

[0125] Next, a specific material configuration of the ERMOS circuit shown in FIGS. 11(A) to 11(C) will be described thereof.

[0126] In FIGS. 11(A) to 11(C), a glass substrate such as barium borosilicate glass or aluminoborosilicate glass can be used for the substrate 900. The materials of the first wiring 901 and the gate terminal 902 can be formed of a low-resistance conductive material such as aluminum (Al) or copper (Cu). Further, it can also be formed by combining aluminum (Al) with a heat-resistant conductive material. As the heat-resistant conductive material, an element selected from titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), scandium (Sc), or an alloy containing the above-described elements as components, or an alloy film combining the above-described elements, or a nitride containing the above-described elements as components can be applied. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring.

[0127] The insulating layer 903 can be formed of an insulating film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a tantalum oxide film. Further, it may be formed in a laminated structure composed of these insulating films. Note that the silicon oxynitride film has a composition in which the oxygen content is higher than the nitrogen content, and as a concentration range, oxygen is 55 to 65 atomic%, nitrogen is 1 to 20 atomic%, silicon is 25 to 35 atomic%, and hydrogen is 0 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 Therefore, a good junction can be formed between the first oxide semiconductor layer and the fourth wiring. For the resistance element 354 shown, the fourth wiring 912 is formed directly on the first oxide semiconductor layer 905 .1 to 10 atomic %, each element is contained at an arbitrary concentration so that the total is 100 atomic % is meant. Further, the silicon oxynitride film has a composition in which the nitrogen content is higher than the oxygen content, and as the concentration range, oxygen is 15 to 30 atomic %, nitrogen is 20 to 35 atomic %, Si is 25 to 35 atomic %, and hydrogen is 15 to 25 atomic %. Each element is contained at an arbitrary concentration so that the total is 100 atomic %.

[0128] The first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are formed from a thin film represented by InMO3(ZnO ) m (m>0). Here, M represents one or a plurality of metal elements selected from gallium (Ga), iron (F e), nickel (Ni), manganese (Mn), or cobalt (Co). For example, in the case of M being gallium (Ga), there are cases such as this, and in addition to gallium (Ga) and nickel (Ni), or gallium (Ga) and iron ( Fe), etc., cases where the above metal elements other than gallium (Ga) are included may exist. Further, in the above oxide semiconductor layer, in addition to the metal elements contained as M, iron (Fe) as an impurity element , nickel (Ni) and other transition metal elements, or oxides of the transition metals are included . In addition, the sodium (Na) contained in the above oxide semiconductor layer is 5×10 , nickel (Ni) and other transition metal elements, or oxides of the transition metals are included ( 18 ( atoms / cm 3 ) or less, preferably 1×10 18 (atoms / cm 3 ) or less .

[0129] As the materials for the second wiring 907 and the third wiring 908, aluminum (Al), chrome ​Elements selected from chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten ( W), alloys containing the above-described elements as components, or alloy films formed by combining the above-described elements, etc. may be mentioned. Further, it may be formed as a laminated structure made of these materials.

[0130] The silicon oxide layer 909 is formed from a silicon oxide film formed by a sputtering method. The silicon nitride layer 910 formed over the entire surface of the substrate is formed by a plasma CVD method using a gas containing a hydrogen compound such as silane (SiH4) and ammonia ( NH3). Therefore, the silicon nitride layer 910 contains hydrogen at a high concentration.

[0131] Also, as shown in FIG. 12(A), buffer layers 911a to 9 11c can be provided between the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906, and the second wiring 907 and the third wiring 908.

[0132] The above-described buffer layers 911a to 911c are formed on the basis of an In-Ga-Zn-O-based non-single crystal film formed under film formation conditions different from the film formation conditions for forming the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906, and are low-resistance oxide semiconductor layers. Further, in the following description, for convenience, the oxide semiconductor film on which the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 are formed later is referred to as the first oxide semiconductor film, and the oxide semiconductor film on which the buffer layers 911a to 911c are formed later is referred to as the second oxide semiconductor film. For example, when forming an oxide semiconductor film by a sputtering method, the sputtering used for film formation

[0133] By changing the oxygen concentration of the sputtering gas, the resistance value of the oxide semiconductor film can be changed. Specifically, by increasing the oxygen concentration of the sputtering gas, the resistance value of the oxide semiconductor film can be increased. One of the film formation conditions for the first oxide semiconductor film and the second oxide semiconductor film by the sputtering method is that the argon gas flow rate is 10 sccm and the oxygen gas flow rate is 5 sccm as the sputtering gas used for the formation of the first oxide semiconductor film, and the argon gas flow rate is 40 sccm as the sputtering gas used for the formation of the second oxide semiconductor film. The buffer layers 911a to 911c have an n-type conductivity type and an activation energy (ΔE) of 0.1 eV or less. The buffer layers 911a to 911c formed based on the In-Ga-Zn-O-based non-single crystal film are assumed to contain at least an amorphous component. The buffer layers 911a to 911c may contain crystal grains (nanocrystals) in the amorphous structure. The crystal grains (nanocrystals) in the buffer layers 911a to 911c have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm. By providing the buffer layers 911a to 911c having a lower resistance than the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906, a better junction can be formed between the second wiring 907 which is a conductor and the first oxide semiconductor layer 905, and between the second wiring 907 which is a conductor and the third wiring 908 and the second oxide semiconductor layer 906, as compared with a Schottky junction, and a thermally stable operation can be exhibited. Also, in the thin film transistor 355, by providing the buffer layers 911b and 911c, good mobility can be maintained even at a high drain voltage.

[0134]

[0135] ​​​​​​​​​Further, as shown in FIG. 12(B), buffer layers 911a, 911b, 911c, 911d, 911e can be provided above and below the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906. By providing the buffer layer 911d, a better junction can be formed between the first wiring 901, which is a conductor, and the first oxide semiconductor layer 905 compared to a Schottky junction, and thermally stable operation can be achieved.

[0136]

[0137] Next, thin-film transistors having a structure different from those shown in FIGS. 11(A) to (C) and FIGS. 12(A) and (B) are shown in FIGS. 13(A) and (B) and will be described. In FIGS. 13(A) and (B), cross-sectional structures of a resistance element and a thin-film transistor corresponding to lines A - B and C - D in FIG. 8 are shown, and the same components as those in FIGS. 11(A), (B), and (C) are denoted by the same reference numerals.

[0138] In FIG. 13(A), a channel protection layer 1001, which is a silicon oxide layer, is provided on the second oxide semiconductor layer 906, and a second wiring 907 and a third wiring 908 are provided on the channel protection layer 1001 and the second oxide semiconductor layer 906. Further, a silicon nitride layer 910 is provided on the second wiring 907, the third wiring 908, and the channel protection layer 1001. Also, as shown in FIG. 13(B), buffer layers 911a, 911b, 911c can be provided between the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906 and between the second wiring 907 and the third wiring 908, respectively.

[0139] In FIGS. 11(A) to (C), FIGS. 12(A) and (B), and FIGS. 13(A) and (B), the reverse stagger type thin film transistor has been described, but the structure of the thin film transistor of the present embodiment is not limited to the reverse stagger type. As an example, the same effect is achieved even in a coplanar type thin film transistor. An example of the cross-sectional structure is shown and described in FIGS. 14(A) and (B). In FIGS. 14(A) and (B), the cross-sectional structures of the resistance element and the thin film transistor corresponding to the lines A-B and C-D in FIG. 8 are shown, and those having the same configuration as FIGS. 11(A), (B), and (C) are given the same reference numerals.

[0140] In FIG. 14(A), one end of the first oxide semiconductor layer 905 is provided on the first wiring 901, and the other end of the first oxide semiconductor layer 905 and one end of the second oxide semiconductor layer 906 are provided on the second wiring 907, and the other end of the second oxide semiconductor layer 906 is provided on the third wiring 9 08. Further, a stack of a silicon oxide layer 909 and a silicon nitride layer 910 is provided on the second oxide semiconductor layer 906, and only the silicon nitride layer 910 is provided on the first oxide semiconductor layer 905. Also, as shown in FIG. 14(B), buffer layers 1 010a and 1010b can be provided between the second wiring 907 and the third wiring 908 and the insulating layer 903.

[0141] In FIGS. 11(A) to (C), FIGS. 12(A) and (B), FIGS. 13(A) and (B), and FIGS. 14(A) and (B), a silicon nitride layer 910 formed by a plasma CVD method using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided so as to be in direct contact with the first oxide semiconductor layer 905.

[0142] The ERMOS circuit having the above-mentioned structure has a first oxide layer 910 in direct contact with the silicon nitride layer 910. A resistive element having a resistive component of a nitride semiconductor layer 905 and a silicon oxide layer 909 (channel protection The second oxide semiconductor layer 906 on which the silicon nitride layer 910 is provided is formed through the layer 1001. A thin film transistor having a channel formation region is provided. Hydrogen can be introduced into the layer 905 at a higher concentration than into the second oxide semiconductor layer 906. As a result, the resistance value of the first oxide semiconductor layer 905 is reduced by the resistance value of the second oxide semiconductor layer 906. can be lower than the value.

[0143] Next, the manufacturing process of the ERMOS circuit will be explained using the cross-sectional views of Figures 15(A) to (C). Here, a manufacturing process of the ERMOS circuit shown in FIG.

[0144] A first conductive film is formed on a substrate 900. The first conductive film is formed by a sputtering method, a pure film, or the like. Thin film deposition methods such as air vapor deposition, pulsed laser deposition, and ion plating are used. The material of the first conductive film is a low-resistance conductive material such as aluminum (Al) or copper (Cu). It can be made of aluminum (Al) and a heat-resistant conductive material. The heat-resistant conductive material can be titanium (Ti), tantalum (T a), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), An element selected from scandium (Sc), or an alloy containing the above elements, or Applying an alloy film combining the above elements or a nitride containing the above elements as components. Next, a first photolithography process is performed to apply a resist to the first conductive film. It is formed. Further, using the resist as a mask, the first conductive film is selectively etched, to form the first wiring 901 and the gate terminal 902.

[0145] Next, an insulating film covering the first wiring 901 and the gate terminal 902 is formed. For the formation of the insulating film, thin film deposition methods typified by sputtering, vacuum evaporation, pulsed laser deposition, ion plating, plasma CVD, etc. are used. As the insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a nitrided silicon oxide film, an aluminum oxide film, a tantalum oxide film, etc. can be used. Also, these insulating films may be formed in a laminated structure. Next, a second photolithography process is performed to form a resist on the insulating film. Further, using the resist as a mask, the insulating film is selectively etched to form an insulating layer 903 provided with a contact hole 904 reaching the first wiring. The cross-sectional view at the stage when the above processes are completed corresponds to Fig. 15(A). The cross-sectional view at the stage when the above processes are completed corresponds to Fig. 15(A).

[0146] Next, a second oxide semiconductor film is formed. For the formation of the second oxide semiconductor film, thin film deposition methods typified by sputtering, vacuum evaporation, pulsed laser deposition, ion plating, plasma CVD, etc. are used. When film formation is performed by sputtering, it is preferable to use a target obtained by sintering In2O3, Ga2O3, and ZnO. As the sputtering gas, a noble gas typified by argon is used. One of the film formation conditions by sputtering is to use a target obtained by mixing and sintering In2O3:Ga2O3:ZnO = 1:1:1, with a pressure of 0.4 Pa, a DC (DC) power supply of 500 W, and an argon gas flow rate of 40 sccm.

[0147] Next, a second conductive film is formed. For forming the second conductive film, thin film deposition methods typified by sputtering, vacuum evaporation, , pulsed laser deposition, and ion plating are used. Note that , as materials for the second conductive film, elements selected from aluminum (Al), chromium (Cr), tantalum (T a), titanium (Ti), molybdenum (Mo), tungsten (W), or alloys containing the above-mentioned elements, or alloy films combining the above-mentioned elements, etc. are exemplified. In addition, it may be formed as a laminated structure made of these materials.

[0148] Next, a third photolithography process is performed to form a resist on the second conductive film. Furthermore, using the resist as a mask, the second oxide semiconductor film and the second conductive film are selectively etched to form the second wiring 907, the third wiring 908, and the buffer layers 1010a, 1010b. As an etching method at this time, wet etching or dry etching is used. For example, when an aluminum (Al) film or an aluminum alloy film is used as the second conductive film, wet etching using a solution mixed with phosphoric acid, acetic acid, and nitric acid can be performed. Similarly, when a titanium (Ti) film or a titanium alloy film is used as the second conductive film, wet etching using aqueous ammonia peroxide (hydrogen peroxide: ammonia: water = 5:2:2) can be performed.

[0149] Next, a first oxide semiconductor film is formed. For forming the first oxide semiconductor film, thin film deposition methods typified by sputtering, vacuum evaporation, pulsed laser evaporation, ion plating, etc. are used. The first oxide semiconductor film has a sputtering gas compared to the second oxide semiconductor film. One of the film-forming conditions by sputtering is to form a film under conditions where the oxygen concentration contained therein is high. The film is In2O A target obtained by mixing and sintering 3:Ga2O3:ZnO = 1:1:1 is used, and the pressure is 0.4P a, a DC power supply of 500 W, an argon gas flow rate of 10 sccm, and an oxygen gas flow rate of 5 s ccm.

[0150] Further, before forming the first oxide semiconductor film, an argon gas is introduced to generate plasma and a reverse sputtering process is performed to remove dust adhering to the insulating layer 903, the first wiring 901, the second wiring 907, and the third wiring 908. Further, by performing the reverse sputtering process in an atmosphere in which oxygen is added to argon, the surfaces of the first wiring 90 1, the second wiring 907, and the third wiring 908, which are conductors, are oxidized, and the vicinity of the contact interface with the second oxide semiconductor film can be made highly resistive. Therefore, the value of the off-current of the thin-film transistor formed later can be reduced. Note that the reverse sputtering process is a process method in which a voltage is applied to the substrate side using an RF power supply in an argon atmosphere without applying a voltage to the target side to form plasma on the substrate and modify the surface.

[0151] Next, a fourth photolithography process is performed to form a resist on the first oxide semiconductor film. Further, using the resist as a mask, the first oxide semiconductor film is selectively etched to form the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906. The cross-sectional view at the stage where the processes up to here are completed corresponds to FIG. 15(B).

[0152] Next, a silicon oxide film is formed by sputtering. For example, the silicon oxide film is Forming a film using a sputtering gas containing argon and oxygen with recon as the target This is possible. Also, using silicon oxide as the target and argon as the sputtering gas it is possible to form a silicon oxide film. Next, a fifth photolithography process is performed to form a resist on the silicon oxide film. Further, using the resist as a mask, the sili con film is selectively etched, and a silicon oxide layer 90 9 is formed on the second oxide semiconductor layer 906.

[0153] Next, a silicon nitride layer 910 having a function as a passivation film is formed over the entire surface of the substrate The silicon nitride layer 910 is formed by plasma CVD using a gas containing any hydrogen compound such as silane (SiH4) and ammonia (NH3), and is a silicon nitride layer containing hydrogen at a high concentration

[0154] Next, a heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C. For example it is placed in a furnace and heat-treated at 350°C for 1 hour in a nitrogen atmosphere. The cross-sectional view at this stage after completing the above steps corresponds to FIG. 15(C).

[0155] As described above, the resistor element 354 and the thin film transistor 355 can be fabricated using the oxide semiconductor layer

[0156] Note that the above-described order of steps is an example and is not particularly limited. FIG. 16 shows and describes an example of a manufacturing process different from FIG. 15

[0157] A first conductive film is formed on the substrate 900. Next, a first photolithography process is performed to form a resist on the first conductive film. Further, using the resist as a mask, the first ​​​​​Selectively etch the conductive film to form the first wiring 901 and the gate terminal 902.

[0158] Next, form an insulating film covering the first wiring 901 and the gate terminal 902. Next, the second oxide semiconductor film is formed. Next, the second conductive film is formed. Next, the second pho tolithography process is performed to form a resist on the second conductive film. Further, the resist is used as a mask to selectively etch the second conductive film and the second oxide semiconductor film, and the second wiring 907, the third wiring 908, and the buffer layers 1010a and 1010b are formed. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 16(A).

[0159] Next, the third photolithography process is performed to form a resist on the insulating film. Further more, using the resist as a mask, the insulating film is selectively etched to form the insulating layer 903 provided with the contact hole 904 reaching the first wiring 901.

[0160] Next, the first oxide semiconductor film is formed. Next, the fourth photolithography process is performed to form a resist on the first oxide semiconductor film. Further, using the resist as a mask the first oxide semiconductor film is selectively etched to form the first oxide semiconductor layer 905 and the second oxide semiconductor layer 906. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 16(B ).

[0161] Next, a silicon oxide film is formed by sputtering. Next, the fifth photolitho graphy process is performed to form a resist on the silicon oxide film. Further, using the resist as a ma sk, the silicon oxide film is selectively etched to cover the second oxide semiconductor layer 906. A silicon oxide layer 909 is formed.

[0162] Next, a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is used to form a silicon nitride layer 910 having a function as a passivation film over the entire surface of the substrate by plasma CVD method. The silicon nitride layer 910 is formed.

[0163] Next, a heat treatment is performed at 200°C to 600°C in a nitrogen atmosphere. The cross-sectional view of the step up to this point corresponds to FIG. 16(C).

[0164] As described above, the resistance element 354 and the thin film transistor 355 formed using the oxide semiconductor layer can be manufactured. In addition, in the steps described with reference to FIGS. 16(A) to 16(C), after forming the contact hole 904, the first oxide semiconductor film can be formed. Therefore, the number of steps in which the bottom surface of the contact hole is exposed can be reduced, and the degree of freedom in selecting the material of the first wiring 901 can be increased.

[0165] The resistance element and the thin film transistor described in this embodiment are formed using an oxide semiconductor layer. Therefore, a drive circuit including the resistance element and the thin film transistor has good electrical characteristics. Further, on the first oxide semiconductor layer applied to the resistance element, a silicon nitride layer formed by plasma CVD method using a gas containing a hydrogen compound such as silane (SiH 4) and ammonia (NH3) is provided so as to be in direct contact with the first oxide semiconductor layer, and on the second oxide semiconductor layer applied to the thin film transistor, a silicon nitride layer is provided via a silicon oxide layer serving as a barrier layer. Therefore, nitrogen containing hydrogen at a high concentration is directly in contact with the first oxide semiconductor layer, and on the second oxide semiconductor layer applied to the thin film transistor, a silicon nitride layer is provided via a silicon oxide layer serving as a barrier layer. Therefore, nitrogen containing hydrogen at a high concentration is directly in contact with the first oxide semiconductor layer, and on the second oxide semiconductor layer applied to the thin film transistor, a silicon nitride layer is provided via a silicon oxide layer serving as a barrier layer. Therefore, nitrogen containing hydrogen at a high concentration is directly in contact with the first oxide semiconductor layer, and on the second oxide semiconductor layer applied to the thin film transistor, a silicon nitride layer is provided via a silicon oxide layer serving as a barrier layer. Therefore, nitrogen containing hydrogen at a high concentration In the first oxide semiconductor layer that is in direct contact with the silicon nitride layer, hydrogen is introduced at a higher concentration than in the second oxide semiconductor layer. As a result, the resistance value of the first oxide semiconductor layer can be made lower than that of the second oxide semiconductor layer. This eliminates the need to separately provide a manufacturing process for the thin film transistor and a manufacturing process for the resistance element, and a drive circuit with a reduced manufacturing process can be provided.

[0166] (Embodiment 2) In this embodiment, an example of a resistance element and a thin film transistor different from those in Embodiment 1 will be described with reference to FIG. 17. Note that FIG. 17 shows a cross-sectional structure of a resistance element and a thin film transistor corresponding to lines A-B and C-D in FIG. 8 described in Embodiment 1.

[0167] A first wiring 901 and a gate terminal 902 are provided on a substrate 900. Further, an insulating layer 903 is provided on the first wiring 901 and the gate terminal 902. Note that the materials of the substrate 900, the first wiring 901, the gate terminal 902, and the insulating layer 903 can be the same as those described in Embodiment 1, so the description of Embodiment 1 is incorporated herein by reference in this embodiment.

[0168] On the insulating layer 903, a first oxide semiconductor layer 2001 containing nitrogen at a high concentration and overlapping the first wiring 901, and a second oxide semiconductor layer 2002 containing nitrogen at a high concentration and overlapping the gate terminal 902 are provided. Note that the first wiring 901 is in contact with the first oxide semiconductor layer 2001 containing nitrogen at a high concentration through a contact hole 904 formed in the insulating layer 903.

[0169] Note that the first oxide semiconductor layer 2001 containing nitrogen at a high concentration and the second oxide semiconductor layer containing nitrogen at a high concentration The second oxide semiconductor layer 2002 to be formed is an oxide semiconductor layer formed from an oxide semiconductor film formed under film formation conditions different from those of the first oxide semiconductor film and the second oxide semiconductor film, and has a high nitrogen concentration. Specifically, it is an oxide semiconductor layer in which the ratio (N / O) of nitrogen (N) to oxygen (O) in the oxide semiconductor layer is in the range of 0.05 or more and 0.8 or less, preferably in the range of 0.1 or more and 0.5 or less. For example, when forming an oxide semiconductor film containing nitrogen at a high concentration by sputtering, it may be formed using a sputtering gas containing nitrogen gas. One of the film formation conditions by sputtering is

[0170] to use a target of In2O3:Ga2O3:ZnO = 1:1:1 (In:Ga:Zn = 1:1:0.5), with a pressure of 0.4 Pa, a DC power supply of 500 W, an argon gas flow rate of 35 sccm, and a nitrogen gas flow rate of 5 sccm. Note that it is preferable to use a pulsed DC (D C) power supply because it can reduce dust and make the film thickness distribution uniform. Next, the first oxide semiconductor layer 2001 containing nitrogen at a high concentration and the second oxide semiconductor layer 2002 containing nitrogen at a high concentration are formed from the oxide semiconductor film containing nitrogen at a high concentration by a photolithography process.

[0171] Next, the second wiring 907 and the third wiring 908 are provided. The second wiring 907 covers one end of the first oxide semiconductor layer 2001 containing nitrogen at a high concentration and one end of the second oxide semiconductor layer 2002 containing nitrogen at a high concentration, and the third wiring 908 covers the other end of the second oxide semiconductor layer 2002 containing nitrogen at a high concentration. Note that since the materials described in Embodiment 1 can be applied to the second wiring 907 and the third wiring 908, in this embodiment ​ In this state, the description of Embodiment 1 is incorporated by reference.

[0172] Next, a silicon oxide layer 909 is provided on the second oxide semiconductor layer 2002 containing nitrogen at a high concentration. The silicon oxide layer is formed by selectively etching a silicon oxide film formed by a sputtering method. The silicon oxide film is formed using silicon as a target and a sputtering gas containing argon and oxygen, or by using silicon oxide as a target and argon as a sputtering gas. and the like. and the like. and the like. is possible.

[0173] At this stage, a heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C, in an atmosphere containing a substance that serves as a source of hydrogen atoms. One of the heat treatment conditions is a heat treatment at 350°C for 1 hour. As the atmosphere containing a substance that serves as a source of hydrogen atoms, a mixed atmosphere of hydrogen and a noble gas such as argon can be applied. and the like. and the like. and the like.

[0174] Nitrogen in the oxide semiconductor layer inhibits the atoms constituting the oxide semiconductor layer from being densely packed in the film and has the effect of promoting the diffusion and solid solution of hydrogen into the film. Therefore, hydrogen is introduced into the first oxide semiconductor layer 2001 containing nitrogen at a high concentration by the heat treatment. As a result, the hydrogen concentration of the first oxide semiconductor layer 2001 containing nitrogen at a high concentration becomes higher than the hydrogen concentration of the second oxide semiconductor layer 2002 containing nitrogen at a high concentration. That is, the resistance value of the first oxide semiconductor layer 2001 containing nitrogen at a high concentration can be made lower than the resistance value of the second oxide semiconductor layer 2002 containing nitrogen at a high concentration. and the like. and the like. and the like. and the like. and the like. and the like.

[0175] In addition, hydrogen compounds such as silane (SiH4) and ammonia (NH3) are applied to the entire surface of the substrate. A silicon nitride layer 910 is formed by a plasma CVD method using a gas containing The silicon nitride layer 910 is a silicon nitride containing a high concentration of hydrogen. A first oxide semiconductor layer 200 containing nitrogen at a high concentration in direct contact with a silicon nitride layer 910 It is possible to further increase the hydrogen concentration in 1 and achieve lower resistance.

[0176] As a result, the first oxide semiconductor layer 2001 having low resistance and containing nitrogen at a high concentration was formed. The resistor element 354 used and the second oxide semiconductor containing nitrogen at a high concentration to maintain a high resistance value. A thin film transistor 355 can be formed using the conductor layer 2002 .

[0177] In this embodiment, a cross-sectional structure of a resistance element corresponding to the line AB in FIG. However, as shown in FIG. 9 and FIG. 10, the first oxide semiconductor layer containing nitrogen at a high concentration was It is also possible to make it meandering. It is also possible to form wiring layers on both ends of the nitrogen-containing oxide semiconductor layer at the same time.

[0178] In this embodiment mode, a cross-sectional structure of a channel-etch type thin film transistor is shown. However, it is also possible to use a channel stop type thin film transistor. In the above, an inverted staggered thin-film transistor is shown, but a coplanar thin-film transistor is also shown. It is also possible to use a transistor.

[0179] The resistor element and the thin film transistor described in this embodiment are made of an oxide containing nitrogen at a high concentration. Therefore, the resistor element and the thin film transistor are formed using a nitride semiconductor layer. The driving circuit it has has good driving characteristics. Also, in an atmosphere containing a substance that serves as a source of hydrogen atoms, heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C. By doing so, hydrogen is introduced into the first oxide semiconductor layer containing nitrogen at a high concentration, which is applied to the resistance element. Therefore, hydrogen is introduced into the first oxide semiconductor layer containing nitrogen at a high concentration at a higher concentration than the second oxide semiconductor layer containing nitrogen at a high concentration. As a result, the resistance value of the first oxide semiconductor layer containing nitrogen at a high concentration can be made lower than the resistance value of the second oxide semiconductor layer containing nitrogen at a high concentration. Thereby, it is not necessary to separately provide the manufacturing process of the thin film transistor and the manufacturing process of the resistance element, and a driving circuit with a reduced manufacturing process can be provided.

[0180] (Embodiment 3) In this embodiment, the resistance element and the thin film transistor manufactured using the oxide semiconductor layer described in Embodiment 1 and the oxide semiconductor layer containing nitrogen at a high concentration described in Embodiment 2 will be described with reference to FIGS. 18(A) to (C) and FIGS. 19(A) and (B). FIGS. 18(A) to (C) and FIGS. 19(A) and (B) show cross-sectional structures of the resistance element and the thin film transistor corresponding to the A - B line and the C - D line in FIG. 8.

[0181] Specifically, in this embodiment, a configuration in which the oxide semiconductor layer containing nitrogen at a high concentration described in Embodiment 2 is applied instead of the buffer layer described in Embodiment 1 will be described with reference to FIGS. 18(A) to (C) and FIGS. 19(A) and (B).

[0182] First, a first conductive film is formed on the substrate 900. As the method for forming the first conductive film, sputtering Thin film deposition represented by the sputtering method, vacuum evaporation method, pulsed laser deposition method, and ion plating method is used. Next, a first photolithography process is performed to form a resist on the first conductive film. Furthermore, using the resist as a mask, the first conductive film is selectively etched to form the first wiring 901 and the gate terminal 902. Next, an insulating film covering the first wiring 901 and the gate terminal 902 is formed. For forming the insulating film, thin film deposition methods represented by the sputtering method, vacuum evaporation method, pulsed laser deposition method, ion plating method, plasma CVD method, etc. are used. Next, a second photolithography process is performed to form a resist on the insulating film. Furthermore, using the resist as a mask, the insulating film is selectively etched to form the insulating layer 903 provided with the contact hole 904. Note that the materials of the first wiring 901, the gate terminal 902, and the insulating layer 903 can apply the materials described in Embodiment 1, so the description of Embodiment 1 is incorporated herein in this embodiment. The cross-sectional view at the stage where the above steps are completed corresponds to FIG. 18(A). Next, an oxide semiconductor film 950 is formed. For forming the oxide semiconductor film 950, thin film deposition methods represented by the sputtering method, vacuum evaporation method, pulsed laser deposition method, ion plating method, plasma CVD method, etc. are used. When forming the film by the sputtering method, it is preferable to use a target obtained by sintering In2O3, Ga2O3, and ZnO. One of the film formation conditions by the sputtering method is to use a target obtained by mixing and sintering In2O3:Ga2O3:ZnO = 1:1:1, with a pressure of 0.4 Pa, a DC power supply of 500 W, an argon gas flow rate of 10 sccm, and an oxygen gas flow rate of 5 sccm.

[0183]

[0184] Next, an oxide semiconductor film 951 containing nitrogen at a high concentration is formed. The formation of the oxide semiconductor film 951 containing nitrogen at a high concentration uses a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, etc. When forming a film by the sputtering method, it is preferable to use a target obtained by sintering In2O3, Ga2O3, and ZnO. One of the film formation conditions of the oxide semiconductor film 951 containing nitrogen at a high concentration by the sputtering method is to use a target obtained by mixing and sintering In2O3:Ga2O3:ZnO = 1:1:1, with a pressure of 0.4 Pa, a DC power supply of 500 W, an argon gas flow rate of 35 sccm, and a nitrogen gas flow rate of 5 sccm. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(B). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). At this stage, a heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C, in an atmosphere containing a substance that serves as a source of hydrogen atoms. One of the heat treatment conditions is a heat treatment at 350°C for 1 hour. Note that as the atmosphere containing a substance that serves as a source of hydrogen atoms, hydrogen and Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C).

[0185] Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C).

[0186] At this stage, a heat treatment is performed at 200°C to 600°C, typically 250°C to 500°C, in an atmosphere containing a substance that serves as a source of hydrogen atoms. One of the heat treatment conditions is a heat treatment at 350°C for 1 hour. Note that as the atmosphere containing a substance that serves as a source of hydrogen atoms, hydrogen and Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). Next, a resist is formed on the oxide semiconductor film 951 containing nitrogen at a high concentration by performing a third photolithography process. Further, using the resist as a mask, the oxide semiconductor film 950 and the oxide semiconductor film 951 containing nitrogen at a high concentration are selectively etched to form a stack of the first oxide semiconductor layer 960 and the first oxide semiconductor layer 961 containing nitrogen at a high concentration, and a stack of the second oxide semiconductor layer 962 and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. The cross-sectional view at the stage when the above steps are completed corresponds to FIG. 18(C). An atmosphere mixed with a noble gas such as argon can be applied.

[0187] Nitrogen in the oxide semiconductor layer inhibits the atoms constituting the oxide semiconductor layer from being densely packed in the film, while promoting the diffusion and solid solution of hydrogen into the film. Therefore, by this heat treatment, hydrogen is introduced into the first oxide semiconductor layer 961 containing nitrogen at a high concentration and the second oxide semiconductor layer 963 containing nitrogen at a high concentration. As a result, the resistance values of the first oxide semiconductor layer 961 containing nitrogen at a high concentration and the second oxide semiconductor layer 9 63 containing nitrogen at a high concentration can be reduced.

[0188] Next, a second conductive film is formed. For forming the second conductive film, a thin film deposition method typified by a sputtering method, a vacuum evaporation method, a pulsed laser deposition method, an ion plating method, etc. is used. Next, a fourth photolithography process is performed to form a resist on the second conductive film. Further, using the resist as a mask, the second conductive film is selectively etched to form the second wiring 9 07 and the third wiring 908. Note that since the materials of the second wiring 907 and the third wiring 908 can be the materials described in Embodiment 1, the description of Embodiment 1 is incorporated herein in this embodiment. Also, in the etching process, the oxide semiconductor layer containing nitrogen at a high concentration in the region that does not overlap with the second wiring 907 and the third wiring 908 is etched and removed. Also, a part of the oxide semiconductor layer in the region is etched, and oxide semiconductor layers 964 and 966 and oxide semiconductor layers 965, 967, 9 68 containing nitrogen at a high concentration are formed. A cross-sectional view at the stage where the above steps are completed corresponds to FIG. 19(A).

[0189] ​​​​ Next, a silicon oxide film is formed by sputtering. For example, the silicon oxide film can be formed using a sputtering gas containing argon and oxygen with silicon as a target. Also, a silicon oxide film can be formed using silicon oxide as a target and argon as a sputtering gas. Next, a resist is formed on the silicon oxide film by a fifth photolithography process. Further, using the resist as a mask, the silicon oxide film is selectively etched to form a silicon oxide layer 909.

[0190] Next, a silicon nitride layer 910 having a function as a passivation film is formed. The silicon nitride layer 910 is formed by plasma CVD using a gas containing hydrides such as silane (SiH4) and ammonia (NH3). By the above steps, a resistor element 354 and a thin film transistor 355 are formed. A cross-sectional view at the stage after completing the above steps corresponds to FIG. 19(B).

[0191] In the resistor element 354 and the thin film transistor 355 shown in this embodiment, oxide semiconductor layers 965, 967, and 968 having hydrogen introduced therein and containing nitrogen at a high concentration to reduce the resistance are formed between the oxide semiconductor layer and the wiring layer which is a conductor. Therefore, the junction between the oxide semiconductor layer and the wiring layer becomes a better junction compared to a Schottky junction and can exhibit stable operation thermally. Also, in the thin film transistor 355, by forming oxide semiconductor layers 967 and 968 containing nitrogen at a high concentration, good mobility can be maintained even at a high drain voltage.

[0192] In the above-described manufacturing process, an example was shown in which heat treatment for introducing hydrogen into an oxide semiconductor layer containing nitrogen at a high concentration is performed after the etching process of the oxide semiconductor layer. However, this heat treatment may be performed at any time as long as it is after the formation of the oxide semiconductor film containing nitrogen at a high concentration and before the formation of the second conductive film. For example, it is also possible to perform this heat treatment as a next step after the formation of the oxide semiconductor film containing nitrogen at a high concentration. In addition, in the present embodiment, the cross-sectional structure of the resistance element corresponding to the line A-B in FIG. 8 was shown. However, as shown in FIGS. 9 and 10, it is also possible to make the oxide semiconductor layer into a meander shape (serpentine shape). Further, as shown in FIG. 10, it is also possible to form a wiring layer on both ends of the oxide semiconductor layer containing nitrogen at a high concentration. In addition, in the present embodiment, the cross-sectional structure of the channel-etch type thin film transistor was shown. However, it is also possible to use a channel-stop type thin film transistor. Further, in the present embodiment, the reverse stagger type thin film transistor was shown. However, it is also possible to use a coplanar type thin film transistor. The resistance element and the thin film transistor described in the present embodiment are formed using an oxide semiconductor layer and an oxide semiconductor layer containing nitrogen at a high concentration. Therefore, a drive circuit having the resistance element and the thin film transistor has good driving characteristics. Further, a silicon nitride layer formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is formed on the first oxide semiconductor layer applied to the resistance element.

[0193]

[0194]

[0195] Provided so as to be in direct contact with the oxide semiconductor layer of On the oxide semiconductor layer of a silicon nitride layer is provided via a silicon oxide layer serving as a barrier layer. Therefore, hydrogen is introduced into the first oxide semiconductor layer in direct contact with the silicon nitride layer containing hydrogen at a high concentration at a higher concentration than in the second oxide semiconductor layer. As a result, the resistance value of the first oxide semiconductor layer can be made lower than the resistance value of the second oxide semiconductor layer. Thereby, it is not necessary to separately provide a manufacturing process for a thin film transistor and a manufacturing process for a resistance element, and a drive circuit with a reduced manufacturing process can be provided.

[0196] (Embodiment 4) In the present embodiment, a configuration example of a drive circuit having a shift register configured by a dynamic circuit will be described with reference to FIGS. 20(A) to (C).

[0197] The pulse output circuit 1400 shown in FIG. 20(A) includes an inverter circuit 1401 to which a start pulse (SP) is input from an input terminal, a switch 1402 having one terminal connected to the output terminal of the inverter circuit 1401, and a capacitor element 1403 connected to the other terminal of the switch 1402. The switch 1402 of the pulse output circuit in the odd-numbered stages is controlled to be turned on and off by a first clock signal (CLK1). The switch 1402 of the pulse output circuit in the even-numbered stages is controlled to be turned on and off by a second clock signal (CLK2).

[0198] FIG. 20(B) shows the circuit configuration of the pulse output circuit in detail. The pulse output circuit 1400 includes thin film transistors 1411 and 1413, a resistance element 1412, and a capacitor element 14 It has 14. Also, the pulse output circuit of the odd-numbered stage is connected to a wiring 1415 for supplying a first clock signal (CLK1), and the pulse output circuit of the even-numbered stage is connected to a wiring 1416 for supplying a second clock signal (CLK2). In the pulse output circuit 14 00, the thin film transistor 1411 and the resistance element 1412 correspond to the inverter circuit 1401 shown in FIG. 20(A) and are an ERMOS circuit. Also, the thin film transistor 1 413 corresponds to the switch 1402 shown in FIG. 17(A), and the capacitive element 1414 corresponds to the capacitive element 1403 shown in FIG. 2 0(A). Note that the thin film transistor 1413 is preferably composed of an enhancement-type transistor in the same manner as the thin film transistor 1411. By using an enhancement-type transistor as the switch, the off-current of the transistor can be reduced, so that low power consumption can be achieved and the manufacturing process can be reduced. Here, regarding the circuit operation of the circuits shown in FIGS. 20(A) and (B), a timing chart is shown in FIG. 20(C). In FIG. 20(C), for the sake of explanation, the nodes of the circuit in FIG. 20(B) will be described with reference numerals A to E attached to them. First, the state where the first clock signal (CLK1) is at the H level and the second clock signal (CL K2) is at the L level will be described.

[0199] First, in response to the start pulse (SP), an inverted signal appears at node A. The signal at node B becomes equal to node A because the first clock signal (CLK1) is at the H level. And so on.

[0200] First, the state in which the first clock signal (CLK1) is at the H level and the second clock signal (CL K2) is at the L level will be described.

[0201] In response to the start pulse (SP), an inverted signal appears at node A. The signal at node B is equal to node A because the first clock signal (CLK1) is at the H level. And Then, the signal of node B is inverted by the next-stage inverter circuit, and the inverted signal of node B appears at node C. The signal of node C does not appear at node D because the second clock signal (CLK2) is at the L level and the switch is closed.

[0202] Next, the state where the first clock signal (CLK1) is at the L level and the second clock signal (CLK2) is at the H level will be described.

[0203] The signal of node C transfers to node D, and the signal of node C is reflected and appears at node D. Then, the signal of node D is inverted by the inverter circuit, and the inverted signal of node D appears at node E. By alternately setting the first clock signal (CLK1) and the second clock signal (CLK2) to the H level, it can function as a shift register.

[0204] Note that the shift register including the pulse output circuit shown in this embodiment can be used for a source line drive circuit and a gate line drive circuit. The signal output from the shift register may be output via a logic circuit or the like to obtain a desired signal.

[0205] The dynamic circuit described in this embodiment has an ERMOS circuit. The ERMOS circuit is composed of the resistance elements and thin film transistors described in Embodiments 1 to 3. Therefore, the dynamic circuit has good dynamic characteristics.

[0206] (Embodiment 5) In this embodiment, an example of a display device provided with a protection circuit will be described with reference to FIGS. 21 and 22.

[0207] ​​​​​​​​​ FIG. 21 shows an overall view of the display device. On a substrate 500, a source line driving circuit 501, a first gate line driving circuit 502A, a second gate line driving circuit 502B, and a pixel portion 503 are integrally formed. In the pixel portion 503, a portion surrounded by a dotted line frame 510 is one pixel. In the example of FIG. 21, as the gate line driving circuit, the first gate line driving circuit 502A and the second gate line driving circuit 502B are shown, but only one of them may be used. Also, in the pixels of the display device, the display elements are controlled by thin film transistors. Signals (clock signals, start pulses, etc.) for driving the source line driving circuit 501, the first gate line driving circuit 502A, and the second gate line driving circuit 502B are input from the outside through flexible print circuits (FPC) 504A and 504B.

[0208]

[0209] Next, an example of the specific circuit configuration of the protection circuits 550 and 551 shown in FIG. 21 will be described with reference to FIGS. 22(A) and (B).

[0210] The protection circuit shown in Fig. 22(A) has diode-connected n-type thin film transistors 560 to 567 that function as protection diodes and a resistor element 568. Note that the diode-connected n-type thin film transistor has an anode on the gate terminal and the first terminal side, and a cathode on the second terminal side. The anode of the diode-connected n-type thin film transistor 560 is connected to the wiring to which the low power supply potential VSS is supplied. The anode of the diode-connected n-type thin film transistor 561 is connected to the cathode of the diode-connected n-type thin film transistor 560, and the cathode is connected to the wiring 569. Also, the anode of the diode-connected n-type thin film transistor 562 is connected to the wiring 569. The anode of the diode-connected n-type thin film transistor 563 is connected to the cathode of the diode-connected n-type thin film transistor 562, and the cathode is connected to the high power supply potential VDD. The diode-connected n-type thin film transistors 564 to 567 are connected in the same manner as the diode-connected n-type thin film transistors 560 to 563. The resistor element 568 is connected in series to the terminal to which the input potential Vin is input and the terminal from which the output potential Vout is output. The operation of the protection circuit shown in Fig. 22(A) will be described below. When the input potential Vin from the drive circuit is abnormally high, specifically, when the input potential Vin is higher than the high power supply potential VDD and the forward voltages of the diode-connected n-type thin film transistors 562 and 563

[0211]

[0212]

[0213] ​​​​​​​​​​​​​​When it is higher than the sum of the voltage drops, the diode-connected n-type thin-film transistors 562 and 563 conduct, and the potential of the wiring 569 indicates a potential according to the sum of the forward voltage drops of the high-voltage potential VDD and the diode-connected n-type thin-film transistors 562 and 563.

[0214] On the other hand, when the input potential Vin from the drive circuit is abnormally low, specifically, lower than the forward voltage drops of the diode-connected n-type thin-film transistors 560 and 561 from the low power supply potential VSS, the diode-connected n-type thin-film transistors 560 and 561 conduct, and the potential of the wiring 569 indicates a potential according to the potential reduced by the forward voltage drops of the diode-connected n-type thin-film transistors 560 and 561 from the low voltage potential VSS.

[0215] Therefore, the protection circuit can keep the output potential Vout within a certain range.

[0216] In addition, in this embodiment, diode-connected n-type thin-film transistors 564 to 567, which are connected in the same manner as the diode-connected n-type thin-film transistors 560 to 563, are provided. By providing the diode-connected n-type thin-film transistors 564 to 567, the current path when the input potential Vin from the drive circuit is abnormally high or low can be increased. Therefore, the reliability of the display device can be further improved.

[0217] Also, the resistance element 568 can mitigate the sudden change in the potential of the wiring 569 and prevent the deterioration or breakdown of the semiconductor elements in the pixel portion. ​

[0218] The protection circuit shown in FIG. 22(B) includes a resistor element 570, a resistor element 571, and an n-type thin film transistor 572 connected in diode connection. The resistor element 570, the resistor element 571, and the n-type thin film transistor 572 connected in diode connection are connected in series to a wiring 573.

[0219] The resistor elements 570 and 571 can mitigate a rapid change in the potential of the wiring 573 and prevent deterioration or breakdown of the semiconductor elements in the pixel portion. Also, the n-type thin film transistor 572 connected in diode connection can prevent a reverse-biased current from flowing through the wiring 573 due to a change in potential.

[0220] When only resistor elements are connected in series to the wiring, a rapid change in the potential of the wiring can be mitigated, and deterioration or breakdown of the semiconductor elements in the pixel portion can be prevented. Also, when only an n-type thin film transistor connected in diode connection is connected in series to the wiring, a reverse-biased current flowing through the wiring due to a change in potential can be prevented.

[0221] Note that the protection circuit of the present embodiment is not limited to the configurations shown in FIGS. 22(A) and (B). Design changes can be made as appropriate as long as the circuit configuration has the same function.

[0222] The protection circuit described in the present embodiment includes the resistor elements and thin film transistors described in Embodiments 1 to 3. Therefore, the protection circuit has good operating characteristics.

[0223] (Embodiment 6) In the present embodiment, it has the resistor elements and thin film transistors shown in Embodiments 1 to 3. As a semiconductor device, an example of a light-emitting display device is shown. Here, a light-emitting display device having a light-emitting element that utilizes electroluminescence is shown. The light-emitting element that utilizes electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element. For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The configuration of applicable pixels and the operation of the pixels will be described. Here, a pixel including an n-channel thin-film transistor in which an oxide semiconductor layer is applied to a channel formation region is shown.

[0224] For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element. For the organic EL element, by applying a voltage to the light-emitting element, electrons and positive holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when these carriers (electrons and positive holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0225] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation. The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. The dispersed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, the organic EL element is used as the light-emitting element for explanation.

[0226] The configuration of applicable pixels and the operation of the pixels will be described. Here, a pixel including an n-channel thin-film transistor in which an oxide semiconductor layer is applied to a channel formation region is shown. The configuration of applicable pixels and the operation of the pixels will be described. Here, a pixel including an n-channel thin-film transistor in which an oxide semiconductor layer is applied to a channel formation region is shown.

[0227] FIG. 23 is a diagram showing an example of a pixel configuration. Pixel 6400 in FIG. 23 includes thin film transistors 6401 and 6402, and a light emitting element 6403. The gate terminal of thin film transistor 640 1 is connected to gate line 6406, and the first terminal is connected to source line 6405 . The gate terminal of thin film transistor 6402 is connected to the second terminal of thin film transistor 6401, the first terminal is connected to power supply line 6407, and the second terminal is connected to the first electrode (pixel electrode) of light emitting element 6403. A high power supply potential VDD is set for power supply line 6407 .

[0228] The second electrode of light emitting element 6403 corresponds to common electrode 6408. Common electrode 6408 is electrically connected to a common potential line formed on the same substrate. A low power supply potential VSS is set for the second electrode (common electrode 6408) of light emitting element 6403. For example, GND, 0 V, etc. can be set as the low power supply potential VSS. Also, in order to apply the potential difference between the high power supply potential VDD set for power supply line 6407 and the low power supply potential VSS set for the second electrode to light emitting element 6403 to cause a current to flow and make light emitting element 6403 emit light, the respective potentials are set so that the potential difference between high power supply potential VDD and low power supply potential VSS is equal to or greater than the forward threshold voltage of light emitting element 6403 . Next, the configuration of the light emitting element will be described with reference to FIG. 24. In this embodiment, an example is shown in which the thin film transistor shown in FIG. 12(A) is applied as the thin film transistor of the light emitting display device. However, any of the thin film transistors shown in Embodiments 1 to 3 can be applied to the thin film transistor of the light emitting display device shown in this embodiment.

[0229] Next, the configuration of the light emitting element will be described with reference to FIG. 24. In this embodiment, an example is shown in which the thin film transistor shown in FIG. 12(A) is applied as the thin film transistor of the light emitting display device. However, any of the thin film transistors shown in Embodiments 1 to 3 can be applied to the thin film transistor of the light emitting display device shown in this embodiment. Although an example is shown in which the thin film transistor shown in FIG. 12(A) is applied as the thin film transistor of the light emitting display device in this embodiment, any of the thin film transistors shown in Embodiments 1 to 3 can be applied to the thin film transistor of the light emitting display device shown in this embodiment.

[0230] For the light-emitting element to extract light, at least one of the anode and the cathode may be transparent. Then, a thin-film transistor and a light-emitting element are formed on a substrate, and light is extracted from the surface opposite to the substrate by top emission, from the surface on the substrate side by bottom emission, or there is a light-emitting element having a double-sided emission structure that extracts light from both the substrate side and the surface opposite to the substrate, and the pixel configuration described in FIG. 23 can be applied to light-emitting elements of any emission structure. The light-emitting element with a top emission structure will be described with reference to FIG. 24(A).

[0231] The light-emitting element with a top emission structure will be described with reference to FIG. 24(A).

[0232] FIG. 24(A) shows a cross-sectional view of a pixel when the thin-film transistor 7001 is of the n-type and the light emitted from the light-emitting element 7002 escapes toward the anode 7005 side. In FIG. 24(A), the cathode 7003 of the light-emitting element 7002 is electrically connected to the thin-film transistor 7001, and a light-emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it has a low work function and reflects light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium stannate, indium zinc oxide, indium stannate added with silicon oxide, etc. Any conductive oxide with light transmittance may be used.

[0233] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in Fig. 24(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow. As shown by the arrow, it is emitted toward the anode 7005 side.

[0234] Next, the light-emitting element with a bottom emission structure will be described with reference to Fig. 24(B). The thin-film transistor 7011 is of the n-type, and the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side. A cross-sectional view of the pixel in this case is shown. In Fig. 24(B), the cathode 7013 of the light-emitting element 7012 is formed on the light-transmissive conductive layer 7017 electrically connected to the thin-film transistor 7011. The light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. Also, when the anode 7015 has light transmittance, a shielding layer 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 24(A). However, its film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, aluminum with a film thickness of 2 0 nm can be used as the cathode 7013. And the light-emitting layer 7014, similar to Fig. 24(A), may be composed of a single layer or may be configured such that a plurality of layers are laminated. The anode 7015 does not necessarily need to transmit light, but similar to Fig. 24(A), it can be formed using a light-transmissive conductive material. However, its film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, aluminum with a film thickness of 2 0 nm can be used as the cathode 7013. And the light-emitting layer 7014, similar to Fig. 24(A), may be composed of a single layer or may be configured such that a plurality of layers are laminated. The anode 7015 does not necessarily need to transmit light, but similar to Fig. 24(A), it can be formed using a light-transmissive conductive material. It doesn't need to be light-transmissive, but similar to Fig. 24(A), it can be formed using a light-transmissive conductive material. It doesn't need to be light-transmissive, but similar to Fig. 24(A), it can be formed using a light-transmissive conductive material. And the shielding layer 7016 can be made of, for example, a metal that reflects light, but is not limited to metal. For example, a resin added with a black pigment can also be used. For example, a resin added with a black pigment can also be used.

[0235] In the cathode 7013 and the anode 7015, the region sandwiching the light-emitting layer 7014 corresponds to the light-emitting element 701 2. In the case of the pixel shown in Fig. 24(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0236] Next, the light-emitting element with a double-sided emission structure will be described with reference to Fig. 24(C). In Fig. 24(C ), the cathode 7023 of the light-emitting element 7022 is formed on the light-transmissive conductive layer 7027 electrically connected to the thin-film transistor 7021 . On the cathode 7023, the light-emitting layer 70 24 and the anode 7025 are sequentially laminated. The cathode 7023 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of Fig. 24(A). However, the film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023 . And the light-emitting layer 7024 can be either a single layer or a structure composed of multiple laminated layers, similar to Fig. 24(A). The anode 7025 can be formed using a light-transmissive conductive material that transmits light, similar to Fig. 24(A) . The anode 7025 can be formed using a light-transmissive conductive material that transmits light, similar to Fig. 24(A) .

[0237] The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7 022. In the case of the pixel shown in Fig. 24(C), the light emitted from the light-emitting element 7022 is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrow.

[0238] Here, although the organic EL element has been described as the light-emitting element, it is also possible to provide an inorganic EL element as the light-emitting element.

[0239] Next, the appearance and cross-section of a light-emitting display panel (also referred to as a light-emitting panel) corresponding to one form of the display device will be described with reference to FIG. 25. FIG. 25(A) is a top view of the panel in which the thin-film transistors and the light-emitting elements formed on the first substrate are sealed with a sealing material between the second substrate, and FIG. 25(B) corresponds to the cross-sectional view taken along E-F in FIG. 25(A).

[0240] A sealing material 45 05 is provided so as to surround the pixel portion 4502, the source line drive circuits 4503a, 4 503b, and the gate line drive circuits 4504a, 4504b provided on the first substrate 4501. Further, a second substrate 4506 is provided on the pixel portion 4502, the source line drive circuits 4503a, 4503b , and the gate line drive circuits 4504a, 4504b. Therefore, the pixel portion 4502, the source line drive circuits 4503a, 4503b, and the gate line drive circuits 4504a, 4504b are sealed together with the filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506. In this way, it is highly airtight so as not to be exposed to the outside air, and it is preferable to package (enclose) it with a protective film (laminated film, ultraviolet-cured resin film, etc.) with little outgassing or a cover material.

[0241] Also, the pixel portion 4502 provided on the first substrate 4501 has thin-film transistors fabricated using an oxide semiconductor, similar to the source line drive circuits 450 3a, 4503b and the gate line drive circuits 4504a, 4504b. In FIG. 25(B), the pixel portion 4502 The thin film transistors 4510 included and the thin film transistors 4509 included in the source line drive circuit 4503a are exemplified. are illustrated.

[0242] Note that, for the thin film transistors 4509 and 4510, examples of applying the thin film transistor having the structure shown in Fig. 12(A) are shown, but any of the thin film transistors shown in Embodiments 1 to 3 can be applied to the thin film transistors of the light-emitting display device shown in this embodiment. Note that, for the thin film transistors 4509 and 4510, examples of applying the thin film transistor having the structure shown in Fig. 12(A) are shown, but any of the thin film transistors shown in Embodiments 1 to 3 can be applied to the thin film transistors of the light-emitting display device shown in this embodiment. are applicable.

[0243] Also, 4511 corresponds to a light-emitting element, and the first electrode layer 4517, which is the pixel electrode of the light-emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. are electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode layer 4517, the electroluminescent layer 4512, and the second electrode layer 4513, but is not limited to the structure shown in this embodiment. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. is not limited. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. is not limited. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like. The structure of the light-emitting element 4511 can be appropriately changed according to the direction of light extracted from the light-emitting element 4511 and the like.

[0244] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, it is preferable to use a photosensitive material to form an opening on the first electrode layer 4517 and form it so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0245] The electroluminescent layer 4512 may be composed of a single layer or may be composed of a plurality of layers stacked. either way is acceptable.

[0246] A protective film may be formed on the second electrode layer 4513 and the partition wall 4520 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4511. As the protective film, silicon nitride can be used. An n-layer, a silicon oxynitride layer, a DLC layer, etc. can be formed.

[0247] Also, various signals and potentials applied to the source line drive circuits 4503a and 4503b, the gate line drive circuits 4504a and 45 04b, or the pixel section 4502 are supplied from the FPCs 4518a and 4 518b.

[0248] In this embodiment, the connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511, and the terminal electrode 4516 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the thin film transistors 4509 and 4510.

[0249] The connection terminal electrode 4515 is electrically connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519.

[0250] The second substrate located in the light extraction direction of the light from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0251] As the filling material 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filling material.

[0252] Also, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be appropriately provided. Also, an antireflection film may be provided on the polarizing plate or circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface irregularities and reduce the reflection.

[0253] The source line drive circuits 4503a, 4503b and the gate line drive circuits 4504a, 4504 b may be mounted on drive circuits formed on a separately prepared substrate. Also, only the source line drive circuit, or a part thereof, or only the gate line drive circuit, or a part thereof may be separately formed and mounted, and the present embodiment is not limited to the configuration of FIG. 25.

[0254] The light-emitting display device shown in the present embodiment has the resistance elements and thin film transistors shown in Embodiments 1 to 3. Therefore, the light-emitting display device has good driving characteristics.

[0255] (Embodiment 7) In the present embodiment, an example of an electronic paper is shown as a semiconductor device having the resistance elements and thin film transistors shown in Embodiments 1 to 3.

[0256] FIG. 26 shows an active matrix type electronic paper. The electronic paper in FIG. 26 uses a twist ball display method. The twist ball display method is a method in which spherical particles painted white and black are used as display elements, and are arranged between a first electrode layer and a second electrode layer which are electrode layers, and a potential difference is generated between the first electrode layer and the second electrode layer to control the orientation of the spherical particles, thereby performing display.

[0257] The thin film transistor 581 provided on the first substrate 580 has a bottom gate structure thin film tra It is a transistor, and is in contact with and electrically connected to the first electrode layer 587 through the first terminal or the second terminal and an opening formed in the insulating layer 585. There are a black region 590a and a white region 590b between the first electrode layer 587 and the second electrode layer 5 88, and a spherical particle 589 including a cavity 594 filled with a liquid around it is provided between the first substrate 580 and the second substrate 596, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin ( Refer to FIG. 26.). In the present embodiment, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode.

[0258] Also, instead of the twist ball, it is also possible to use an electrophoresis element. A transparent liquid and microcapsules with a diameter of about 10 μm to 2 00 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. The microcapsules provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoresis display element, which is generally called electronic paper. Since the electrophoresis display element has a higher reflectance than a liquid crystal display element, an auxiliary light is not required, and also has low power consumption, and it is possible to recognize the display portion even in a dim place. Also, even when no power is supplied to the display portion, it is possible to hold an image once displayed. Therefore, even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is separated from the radio wave transmission source, the displayed image can be saved.

[0259] The electronic paper shown in this embodiment has the resistance elements and thin films shown in Embodiments 1 to 3. Therefore, the electronic paper has good dynamic characteristics.

[0260] (Embodiment 8) In this embodiment, an example of an electronic device will be described as a semiconductor device having the resistance elements and thin film transistors shown in Embodiments 1 to 3.

[0261] Fig. 27(A) shows a portable game machine, which can have a housing 9630, a display unit 9631, a speaker 963 2, operation keys 9633, connection terminals 9634, a recording medium reading unit 9635, etc. The portable game machine shown in Fig. 27(A) can have a function of reading a program or data recorded on a recording medium and displaying it on the display unit, a function of performing wireless communication with other portable game machines and sharing information, etc. Note that the functions of the portable game machine shown in Fig. 27(A) are not limited to these, and it can have various functions.

[0262] Fig. 27(B) shows a digital camera, which can have a housing 9640, a display unit 9641, a speaker 96 42, operation keys 9643, connection terminals 9644, a shutter button 9645, an imaging unit 964 6, etc. The digital camera with a television reception function shown in Fig. 27(B) can have a function of taking still images, a function of taking moving images, a function of automatically or manually correcting the taken images, a function of acquiring various information from an antenna, a function of saving the taken images or the information acquired from the antenna, a function of displaying the taken images or the information acquired from the antenna on the display unit, etc. Note that the digital camera with a television reception function shown in Fig. 27(B) The functions of the camera are not limited to this, and it can have various functions.

[0263] Figure 27(C) is a television receiver, which can have a housing 9650, a display unit 9651, a speaker 965 2, operation keys 9653, connection terminals 9654, etc. The television receiver shown in Figure 27(C) has a function of processing television radio waves and converting them into image signals, a function of processing image signals and converting them into signals suitable for display, a function of converting the frame frequency of image signals, etc. Note that the functions of the television receiver shown in Figure 27(C) are not limited to this, and it can have various functions.

[0264] Figure 28(A) is a computer, which can have a housing 9660, a display unit 9661, a speaker 966 2, operation keys 9663, connection terminals 9664, a pointing device 9665, an external connection port 9666, etc. The computer shown in Figure 28(A) has a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a function of controlling processing by various software (programs), a communication function such as wireless communication or wired communication, a function of connecting to various computer networks using the communication function, a function of transmitting or receiving various data using the communication function, etc. Note that the functions of the computer shown in Figure 28(A) are not limited to this, and it can have various functions.

[0265] Next, Figure 28(B) is a mobile phone, which can have a housing 9670, a display unit 9671, a speaker 96 72, operation keys 9673, a microphone 9674, etc. The mobile phone shown in Figure 28(B ) has a function of displaying various information (still images, moving images, text images, etc.) , a function of displaying a calendar, date, time, etc. on a display unit, operating or editing the information displayed on the display unit, a function of controlling processing by various software (programs), etc. can be provided. Note that the functions of the mobile phone shown in Fig. 28(B) are not limited to this, and it can have various functions.

[0266] The electronic device shown in this embodiment has the resistance elements and thin film transistors shown in Embodiments 1 to 3. Therefore, the electronic device has good operating characteristics.

Explanation of Reference Numerals

[0267] 100 Substrate 101 Source Line Driving Circuit 102A Gate Line Driving Circuit 102B Gate Line Driving Circuit 103 Pixel Section 104A FPC 104B FPC 201 Level Shifter for Clock Signal 202 Level Shifter for Start Pulse 203 Pulse Output Circuit 204 NAND Circuit 205 Buffer 206 Sampling Switch 251 Shift Register 300 Pulse Output Circuit 301 Switch 302 Inverter Circuit 303 Inverter Circuit 304 Switch 305 Inverter Circuit 331 Pulse Output Circuit 332 Pulse Output Circuit 350 Pulse Output Circuit 351 Thin Film Transistor 352 Resistance Element 353 Thin Film Transistor 354 Resistance Element 355 Thin Film Transistor 356 Thin Film Transistor 357 Resistive Element 358 Thin Film Transistor 359 Wiring 360 Wiring 500 Substrate 501 Source Line Drive Circuit 502A Gate Line Drive Circuit 502B Gate Line Drive Circuit 503 Pixel Section 504A FPC 504B FPC 550 Protection Circuit 551 Protection Circuit 560 Thin Film Transistor 561 Thin Film Transistor 562 Thin Film Transistor 563 Thin Film Transistor 564 Thin Film Transistor 565 Thin Film Transistor 566 Thin Film Transistor 567 Thin Film Transistor 568 Resistive Element 569 Wiring 570 Resistive Element 571 Resistive Element 572 Thin Film Transistor 573 Wiring 580 Substrate 581 Thin Film Transistor 585 Insulating Layer 587 Electrode Layer 588 Electrode Layer 589 Spherical Particles 590a Black Region 590b White Region 594 Cavity 595 Filling Material 596 Substrate 601 Resistive Element 602 Thin Film Transistor 603 Resistive Element 604 Thin Film Transistor 605 Resistive Element 606 Thin film transistor 607 Resistive element 608 Thin film transistor 701 Resistive element 702 Thin film transistor 703 Thin film transistor 730 Capacitive element 731 Thin film transistor 721 Thin film transistor 751 Level shifter for clock signal 752 Level shifter for start pulse 753 Pulse output circuit 754 NAND circuit 755 Buffer 781 Shift register 801 Power supply line 802 Power supply line 803 Control signal line 804 Control signal line 805 Control signal line 806 Oxide semiconductor layer 807 Wiring layer 808 Wiring layer 809 Contact hole 900 Substrate 901 First wiring 902 Gate terminal 903 Insulating layer 904 Contact hole 905 Oxide semiconductor layer 906 Oxide semiconductor layer 907 Wiring 908 Wiring 909 Silicon oxide layer 910 Silicon nitride layer 911a Buffer layer 911b Buffer layer 911c Buffer layer 911d Buffer layer 911e Buffer layer 912 Wiring 950 Oxide semiconductor film 951 Oxide semiconductor film 960 Oxide semiconductor layer 961 Oxide semiconductor layer 962 Oxide semiconductor layer 963 Oxide semiconductor layer 964 Oxide semiconductor layer 965 Oxide semiconductor layer 966 Oxide semiconductor layer 967 Oxide semiconductor layer 968 Oxide semiconductor layer 1001 Channel protection layer 1010a Buffer layer 1010b Buffer layer 1400 Pulse output circuit 1401 Inverter circuit 1402 Switch 1403 Capacitor element 1411 Thin film transistor 1412 Resistor element 1413 Thin film transistor 1414 Capacitor element 1415 Wiring 1416 Wiring 2001 Oxide semiconductor layer 2002 Oxide semiconductor layer 4501 Substrate 4502 Pixel section 4503a Source line drive circuit 4503b Source line drive circuit 4504a Gate line drive circuit 4504b Gate line drive circuit 4505 Sealing material 4506 Substrate 4507 Filling material 4509 Thin film transistor 4510 Thin film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic Conductive Film 4520 Partition Wall 6400 Pixel 6401 Thin Film Transistor 6402 Thin Film Transistor 6403 Light Emitting Element 6405 Source Line 6406 Gate Line 6407 Power Supply Line 6408 Common Electrode 7001 Thin Film Transistor 7002 Light Emitting Element 7003 Cathode 7004 Light Emitting Layer 7005 Anode 7011 Thin Film Transistor 7012 Light Emitting Element 7013 Cathode 7014 Light Emitting Layer 7015 Anode 7016 Shielding Layer 7017 Conductive Layer 7021 Thin Film Transistor 7022 Light Emitting Element 7023 Cathode 7024 Light Emitting Layer 7025 Anode 7027 Conductive Layer 9630 Housing 9631 Display Unit 9632 Speaker 9633 Operation Key 9634 Connection Terminal 9635 Recording Medium Reading Unit 9640 Housing 9641 Display Unit 9642 Speaker 9643 Operation Key 9644 Connection Terminal 9645 Shutter Button 9646 Image Receiving Unit 9650 Housing 9651 Display Unit 9652 Speaker 9653 Operation Key 9654 Connection Terminal 9660 Housing 9661 Display Unit 9662 Speaker 9663 Operation Key 9664 Connection Terminal 9665 Pointing Device 9666 External Connection Port 9670 Housing 9671 Display Unit 9672 Speaker 9673 Operation Key 9674 Microphone

Claims

1. A resistor element and a transistor, wherein the resistor element has a first oxide semiconductor layer, the transistor has a second oxide semiconductor layer, one terminal of the resistor element is always electrically connected to one of the source or drain of the transistor, a substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer are provided, the first conductive layer has a region in contact with the upper surface of the substrate, the second conductive layer has a region in contact with the upper surface of the substrate, the first insulating layer has a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the second conductive layer, the first oxide semiconductor layer has a region in contact with the upper surface of the first insulating layer, the second oxide semiconductor layer has a region in contact with the upper surface of the first insulating layer, the third conductive layer has a region in contact with the upper surface of the first oxide semiconductor layer, the fourth conductive layer has a region in contact with the upper surface of the first oxide semiconductor layer, the fifth conductive layer has a region in contact with the upper surface of the second oxide semiconductor layer, the second insulating layer has a region in contact with the upper surface of the third conductive layer, a region in contact with the upper surface of the fourth conductive layer, and a region in contact with the upper surface of the fifth conductive layer, the third conductive layer has a region in contact with the upper surface of the first conductive layer, the third conductive layer functions as the other terminal of the resistor element, the fourth conductive layer functions as one terminal of the resistor element, the second conductive layer functions as the gate electrode of the transistor, the first insulating layer functions as the gate insulating layer of the transistor, the fourth conductive layer functions as one of the source electrode or drain electrode of the transistor, the fifth conductive layer functions as the other of the source electrode or drain electrode of the transistor, in plan view, the first oxide semiconductor layer has a meander shape, in plan view, the first conductive layer does not overlap with the first oxide semiconductor layer, a display device.

2. A resistor element and a transistor, wherein the resistor element has a first oxide semiconductor layer, the transistor has a second oxide semiconductor layer, one terminal of the resistor element is always electrically connected to one of the source or drain of the transistor, A substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, and a second insulating layer are provided. The first conductive layer has a region in contact with the upper surface of the substrate. The second conductive layer has a region in contact with the upper surface of the substrate. The first insulating layer has a region in contact with the upper surface of the first conductive layer and a region in contact with the upper surface of the second conductive layer. The first oxide semiconductor layer has a region in contact with the upper surface of the first insulating layer. The second oxide semiconductor layer has a region in contact with the upper surface of the first insulating layer. The third conductive layer has a region in contact with the upper surface of the first oxide semiconductor layer. The fourth conductive layer has a region in contact with the upper surface of the first oxide semiconductor layer. The fifth conductive layer has a region in contact with the upper surface of the second oxide semiconductor layer. The second insulating layer has a region in contact with the upper surface of the third conductive layer, a region in contact with the upper surface of the fourth conductive layer, and a region in contact with the upper surface of the fifth conductive layer. The third conductive layer has a region in contact with the upper surface of the first conductive layer. The third conductive layer functions as the other terminal of the resistance element. The fourth conductive layer functions as one terminal of the resistance element. The second conductive layer functions as the gate electrode of the transistor. The first insulating layer functions as the gate insulating layer of the transistor. The fourth conductive layer functions as one of the source electrode or the drain electrode of the transistor. The fifth conductive layer functions as the other of the source electrode or the drain electrode of the transistor. In plan view, the first oxide semiconductor layer has a meandering shape. In plan view, the first conductive layer does not overlap with the first oxide semiconductor layer, a display device.

3. In Claim 1 or 2, The second insulating layer has a silicon nitride layer, a display device.

Images