Printed Wiring Board

Abstract

This printed wiring board comprises a base film having a major surface, and an electrically conductive pattern disposed on the major surface. The normal to the major surface is along a first direction. The electrically conductive pattern has a plurality of wiring portions that are arranged at intervals along a second direction orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion that are at both ends in the second direction, and a plurality of third wiring portions that are between the first wiring portion and the second wiring portion in the second direction. In the second direction, the width of the first wiring portion and the width of the second wiring portion are each 1.1 to 4.0 times an average value of the widths of the plurality of third wiring portions.

Description

Technical Field

[0001] The present disclosure relates to a printed wiring board. This application claims priority based on Japanese Patent Application No. 2022-095738, filed on June 14, 2022. All the descriptions described in the Japanese patent application are incorporated herein by reference.

Background Art

[0002] For example, Japanese Unexamined Patent Application Publication No. 2019-197851 (Patent Document 1) describes a printed wiring board. The printed wiring board described in Patent Document 1 has a base film having a main surface and a conductive pattern disposed on the main surface.

[0003] The conductive pattern has a plurality of wiring portions. The plurality of wiring portions are arranged along a second direction orthogonal to a first direction in a cross-sectional view orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion at both ends in the second direction, and a plurality of third wiring portions between the first wiring portion and the second wiring portion. The conductive pattern has a seed layer disposed on the main surface, an electroless plating layer disposed on the seed layer, and an electrolytic plating layer disposed on the electroless plating layer.

[0004] In the manufacturing method of the printed wiring board described in Patent Document 1, first, electroless plating is performed on the seed layer to form an electroless plating layer. Second, a resist pattern is formed on the electroless plating layer. The resist pattern has an opening formed therethrough in the thickness direction. Third, electrolytic plating is performed to form an electrolytic plating layer on the electroless plating layer exposed from the opening of the resist pattern. Fourth, the electroless plating layer and the seed layer exposed from between the portions of the electrolytic plating layer adjacent to each other with a space therebetween are removed by etching.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2019-197851 [Summary of the Invention]

[0006] The printed wiring board of the present disclosure includes a base film having a main surface and a conductive pattern disposed on the main surface. The normal line of the main surface is along a first direction. The conductive pattern has a plurality of wiring portions arranged at intervals along a second direction orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion at both ends in the second direction, and a plurality of third wiring portions between the first wiring portion and the second wiring portion in the second direction. In the second direction, the widths of the first wiring portion and the second wiring portion are 1.1 times or more and 4.0 times or less the average value of the widths of the plurality of third wiring portions. [Brief Description of the Drawings]

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

[0008] [Problems to be Solved by the Present Disclosure] In the method for manufacturing a printed wiring board described in Patent Document 1, when etching for removing the electroless plating layer and the seed layer is performed, the first wiring portion and the second wiring portion may peel off from the base film.

[0009] The present disclosure provides a printed wiring board capable of suppressing peeling of a conductive pattern from a base film.

[0010] [Effects of the Present Disclosure] According to the printed wiring board of the present disclosure, peeling of the conductive pattern from the base film can be suppressed.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0012] (1) The printed wiring board according to the embodiment includes a base film having a main surface and a conductive pattern disposed on the main surface. The normal line of the main surface is along the first direction. The conductive pattern has a plurality of wiring portions arranged at intervals along a second direction orthogonal to the first direction. The plurality of wiring portions include a first wiring portion and a second wiring portion at both ends in the second direction, and a plurality of third wiring portions between the first wiring portion and the second wiring portion in the second direction. In the second direction, the widths of the first wiring portion and the second wiring portion are 1.1 times or more and 4.0 times or less the average value of the widths of the plurality of third wiring portions.

[0013] According to the printed wiring board of (1) above, peeling of the conductive pattern from the base film can be suppressed.

[0014] (2) In the printed wiring board of (1) above, the conductive pattern may have a seed layer disposed on the main surface, an electroless plating layer disposed on the seed layer, and an electrolytic plating layer disposed on the electroless plating layer. The electroless plating layer and the electrolytic plating layer may be formed of copper.

[0015] According to the printed wiring board of (2) above, it is possible to suppress the peeling of the conductive pattern from the base film.

[0016] (3) In the printed wiring board of (2) above, the width of the first wiring portion and the width of the second wiring portion may be 5 μm or more and 60 μm or less.

[0017] According to the printed wiring board of (3) above, even when the width of the conductive pattern is small and the conductive pattern is likely to peel off from the base film, it is possible to suppress the peeling of the conductive pattern from the base film.

[0018] (4) In the printed wiring board of (2) or (3) above, the thickness of the conductive pattern may be 5 μm or more and 150 μm or less.

[0019] In the printed wiring board of (4) above, even when the conductive pattern is thickly formed, it is possible to suppress the peeling of the conductive pattern from the base film.

[0020] (5) In the printed wiring board of (2) to (4) above, the void density at the interface between the electroless plating layer and the electroplating layer may be 5.5 μm 2 / μm or less.

[0021] In the printed wiring board of (5) above, even when many voids are generated at the interface between the electroless plating layer and the electroplating layer, it is possible to suppress the peeling of the conductive pattern from the base film.

[0022] (6) In the printed wiring board of (2) to (5) above, the distance between two adjacent ones in the second direction among the plurality of wiring portions may be 20 μm or less.

[0023] In the printed wiring board of (6) above, even when side etching is likely to occur at the interface between the electroless plating layer and the electroplating layer, it is possible to suppress the peeling of the conductive pattern from the base film.

[0024] (7) In the printed wiring boards of (1) to (5) above, the conductive pattern may be wound in a spiral shape in a plan view to form a coil. The first wiring portion may be at the innermost circumference of the coil. The second wiring portion may be at the outermost circumference of the coil.

[0025] [Details of Embodiments of the Present Disclosure] Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and repeated descriptions will not be repeated. The printed wiring board according to the embodiment is denoted as the printed wiring board 100.

[0026] (Configuration of Printed Wiring Board 100) The configuration of the printed wiring board 100 will be described below.

[0027] FIG. 1 is a plan view of the printed wiring board 100. FIG. 2 is a bottom view of the printed wiring board 100. FIG. 2 shows the printed wiring board 100 viewed from the side opposite to FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1. As shown in FIGS. 1 to 3, the printed wiring board 100 has a base film 10, a first conductive pattern 20, and a second conductive pattern 30.

[0028] The base film 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end surfaces in the thickness direction of the base film 10. The second main surface 10b is the opposite surface of the first main surface 10a. The normal direction of the first main surface 10a (the normal direction of the second main surface 10b) is defined as the first direction DR1. The base film 10 is formed of a flexible material having electrical insulation properties. The base film 10 is formed of, for example, polyimide, liquid crystal polymer, fluororesin, or the like.

[0029] The first conductive pattern 20 is wound in a spiral shape in plan view. That is, the first conductive pattern 20 forms a coil. The first conductive pattern 20 has a plurality of wiring portions 21. The plurality of wiring portions 21 are arranged at intervals along the second direction DR2. The second direction DR2 is orthogonal to the first direction DR1. In the portion where the first conductive pattern 20 extends linearly, the second direction DR2 is a direction orthogonal to the extending direction of the portion. In the portion where the first conductive pattern 20 extends in a curved shape, the second direction DR2 is a direction orthogonal to the tangent direction of the portion.

[0030] The first conductive pattern 20 has a land 20a at one end and a land 20b at the other end. The land 20a and the land 20b are located at the outermost periphery and the innermost periphery of the first conductive pattern 20 wound in a spiral shape, respectively.

[0031] The plurality of wiring portions 21 include a first wiring portion 21a, a second wiring portion 21b, and a plurality of third wiring portions 21c. The first wiring portion 21a and the second wiring portion 21b are respectively at both ends in the second direction DR2. From another perspective, the first wiring portion 21a and the second wiring portion 21b are portions at the innermost periphery and the outermost periphery of the first conductive pattern 20 wound in a spiral shape, respectively. The third wiring portion 21c is between the first wiring portion 21a and the second wiring portion 21b in the second direction DR2. The "plurality of third wiring portions 21c" includes cases where the number of the third wiring portions 21c is 2 or more and cases where the number of the third wiring portions 21c is 3 or more.

[0032] Let the width of the first wiring portion 21a in the second direction DR2 and the width of the second wiring portion 21b in the second direction DR2 be width W1 and width W2, respectively. The width W1 is measured at the position where the width of the first wiring portion 21a in the second direction DR2 is the maximum in the thickness direction, and the width W2 is measured at the position where the width of the second wiring portion 21b in the second direction DR2 is the maximum in the thickness direction. The width W1 and the width W2 are obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image.

[0033] Let the width of the third wiring portion 21c in the second direction DR2 be width W3. The width W3 is measured at the position where the width of the third wiring portion 21c in the second direction DR2 is maximum in the thickness direction. The width W3 is obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image. The width W1 and the width W2 are 1.1 times or more and 4.0 times or less of the average value of the width W3 for a plurality of third wiring portions 21c. The width W1 and the width W2 may be 1.5 times or more of the average value of the width W3 for a plurality of third wiring portions 21c. The width W1 and the width W2 may be, for example, 5 μm or more and 60 μm or less.

[0034] Let the distance in the second direction DR2 between two adjacent wiring portions 21 be distance DIS1. The distance DIS1 is measured at the position where the distance in the second direction DR2 between two adjacent wiring portions 21 is minimum in the thickness direction. The distance DIS1 is 5 μm Above It may be 20 μm or less.

[0035] Let the thickness of the first conductive pattern 20 be thickness T1. The thickness T1 is measured at the position where the thickness of the first conductive pattern 20 is maximum in the width direction. The thickness T1 is obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image. The thickness T1 is, for example, 5 μm or more and 150 μm or less. The thickness T1 may be 30 μm or more and 100 μm or less. In particular, since the first conductive pattern 20 is likely to peel off when the thickness T1 is large, the thickness T1 may be 40 μm or more. The thickness T1 may be 60 μm or more.

[0036] The second conductive pattern 30 is wound in a spiral shape in a plan view. That is, the second conductive pattern 30 forms a coil. The second conductive pattern 30 has a plurality of wiring portions 31. The plurality of wiring portions 31 are arranged at intervals along the second direction DR2. In the portion where the second conductive pattern 30 extends linearly, the second direction DR2 is a direction orthogonal to the extending direction of the portion. In the portion where the second conductive pattern 30 extends in a curved shape, the second direction DR2 is a direction orthogonal to the tangent direction of the portion.

[0037] The second conductive pattern 30 has a land 30a at one end and a land 30b at the other end. The land 30a and the land 30b are located at the innermost circumference and the outermost circumference of the second conductive pattern 30 wound in a spiral shape, respectively. Note that the land 30a overlaps the land 20b in a plan view.

[0038] The plurality of wiring portions 31 includes a first wiring portion 31a, a second wiring portion 31b, and a plurality of third wiring portions 31c. The first wiring portion 31a and the second wiring portion 31b are respectively at both ends in the second direction DR2. In other words, from another perspective, the first wiring portion 31a and the second wiring portion 31b are portions at the innermost circumference and the outermost circumference of the second conductive pattern 30 wound in a spiral shape, respectively. The third wiring portion 31c is between the first wiring portion 31a and the second wiring portion 31b in the second direction DR2. The "plurality of third wiring portions 31c" includes the case where the number of the third wiring portions 31c is 2 or more and the case where the number of the third wiring portions 31c is 3 or more.

[0039] Let the width of the first wiring portion 31a in the second direction DR2 and the width of the second wiring portion 31b in the second direction DR2 be a width W4 and a width W5, respectively. The width W4 is measured at a position where the width of the first wiring portion 31a in the second direction DR2 is the maximum in the thickness direction, and the width W5 is measured at a position where the width of the second wiring portion 31b in the second direction DR2 is the maximum in the thickness direction. The width W4 and the width W5 are obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image.

[0040] Let the width in the second direction DR2 of the third wiring portion 31c be width W6. The width W6 is measured at the position where the width of the third wiring portion 31c in the second direction DR2 is the maximum in the thickness direction. The width W6 is obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image. The widths W4 and W5 are 1.1 times or more and 4.0 times or less of the average value of the widths W6 for a plurality of the third wiring portions 31c. The widths W4 and W5 may be 1.5 times or more of the average value of the widths W6 for a plurality of the third wiring portions 31c. The widths W4 and W5 may be, for example, 5 μm or more and 60 μm or less.

[0041] Let the distance in the second direction DR2 between two adjacent wiring portions 31 be distance DIS2. The distance DIS2 is measured at the position where the distance in the second direction DR2 between two adjacent wiring portions 31 is the minimum in the thickness direction. The distance DIS2 may be 5 μm or more and 20 μm or less.

[0042] Let the thickness of the second conductive pattern 30 be thickness T2. The thickness T2 is measured at the position where the thickness of the second conductive pattern 30 is the maximum in the width direction. The thickness T2 is obtained by acquiring a cross-sectional image along the second direction DR2 and measured on the cross-sectional image. The thickness T2 is, for example, 5 μm or more and 150 μm or less. The thickness T2 may be 30 μm or more and 100 μm or less. In particular, since the second conductive pattern 30 is likely to peel off when the thickness T2 is large, the thickness T2 may be 40 μm or more. The thickness T2 may be 60 μm or more.

[0043] Each of the first conductive pattern 20 and the second conductive pattern 30 has a seed layer 41, an electroless plating layer 42, and an electrolytic plating layer 43.

[0044] The seed layer 41 is disposed on the main surfaces (the first main surface 10a and the second main surface 10b) of the base film 10. The seed layer 41 is, for example, a sputter layer (a layer formed by sputtering). The seed layer 41 has, for example, a first layer 41a and a second layer 41b. The first layer 41a is disposed on the main surfaces (the first main surface 10a and the second main surface 10b) of the base film 10. The second layer 41b is disposed on the first layer 41a. The first layer 41a may be a sputter layer containing a nickel-chromium alloy. The second layer 41b may be a sputter layer containing copper.

[0045] The electroless plating layer 42 is a layer formed by electroless plating. The electroless plating layer 42 is disposed on the seed layer 41. The electroless plating layer 42 is formed of, for example, copper.

[0046] Although not shown, through holes 10c are formed in the base film 10. The through holes 10c penetrate the base film 10 in the thickness direction. The through holes 10c overlap the lands 20b and 30a in plan view. The electroless plating layer 42 is also formed on the inner wall surfaces of the through holes 10c.

[0047] The electroplating layer 43 is a layer formed by electroplating. The electroplating layer 43 is disposed on the electroless plating layer 42. The electroplating layer 43 is formed of, for example, copper. Although not shown, the electroplating layer 43 is also embedded in the through holes 10c. The electroplating layer 43 embedded in the through holes 10c electrically connects the first conductive pattern 20 and the second conductive pattern 30 to each other. Thereby, when a voltage is applied between the land 20a and the land 30b, a current flows in a spiral shape through the first conductive pattern 20 and the second conductive pattern 30, and this current generates a magnetic field.

[0048] The void density at the interface between the electroless plating layer 42 and the electroplating layer 43 is, for example, 5.5 μm 2It is 0 / μm or less. The void density at the interface between the electroless plating layer 42 and the electroplating layer 43 may be 0.01 / μm 2 or more. The void density at the interface between the electroless plating layer 42 and the electroplating layer 43 may be more than 0.01 / μm 2 or more than 0.01 / μm. The void density at the interface between the electroless plating layer 42 and the electroplating layer 43 may be 0.05 / μm 2 or more. The void density at the interface between the electroless plating layer 42 and the electroplating layer 43 is a value obtained by dividing the total area of the voids existing at the interface between the electroless plating layer 42 and the electroplating layer 43 within the range of a predetermined observation length in a cross-sectional view by the observation length. More specifically, the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 is measured by the following method.

[0049] First, in a cross-section parallel to the first direction DR1, an SEM (Scanning Electron Microscope) image of the interface between the electroless plating layer 42 and the electroplating layer 43 is taken. The magnification of this SEM image is set to be 10,000 times or more and 50,000 times or less. Second, by performing image processing on this SEM image, the area of each of a plurality of voids existing at the interface between the electroless plating layer 42 and the electroplating layer 43 is calculated. This image processing is performed by binarizing using software such as the GNU Image Manipulation Program so that the voids become black.

[0050] Third, the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 is obtained by calculating a value obtained by dividing the total area of a plurality of voids existing at the interface between the electroless plating layer 42 and the electroplating layer 43 having a predetermined length by the predetermined length.

[0051] Note that the width of the electrolytic plating layer 43 at the interface with the electroless plating layer 42 is defined as the grounding width. The grounding widths in the first wiring portion 21a, the second wiring portion 21b, and the third wiring portion 21c are the grounding widths W11, W21, and W31, respectively. The grounding widths in the first wiring portion 31a, the second wiring portion 31b, and the third wiring portion 31c are the grounding widths W41, W51, and W61, respectively.

[0052] (Manufacturing method of the printed wiring board 100) The manufacturing method of the printed wiring board 100 will be described below.

[0053] FIG. 4 is a process diagram showing the manufacturing method of the printed wiring board 100. As shown in FIG. 4, the manufacturing method of the printed wiring board 100 includes a preparation step S1, an electroless plating step S2, a resist pattern formation step S3, an electrolytic plating step S4, and an etching step S5.

[0054] FIG. 5 is a cross-sectional view for explaining the preparation step S1. As shown in FIG. 5, in the preparation step S1, the base film 10 is prepared. A seed layer 41 is formed on the main surfaces (the first main surface 10a and the second main surface 10b) of the base film 10 prepared in the preparation step S1.

[0055] FIG. 6 is a cross-sectional view for explaining the electroless plating step S2. As shown in FIG. 6, in the electroless plating step S2, electroless plating is performed to form an electroless plating layer 42 on the seed layer 41. Although not shown, by this electroless plating, the electroless plating layer 42 is also formed on the through hole 10c.

[0056] FIG. 7 is a cross-sectional view for explaining the resist pattern forming step S3. As shown in FIG. 7, in the resist pattern forming step S3, a resist pattern 50 is formed. The resist pattern 50 has a plurality of openings 51. The openings 51 penetrate the resist pattern 50 in the thickness direction. The electroless plating layer 42 is partially exposed from the openings 51. The openings 51 are formed at positions where the electrolytic plating layer 43 is to be formed. When trying to increase the thicknesses T1 and T2, a thicker resist pattern 50 is formed accordingly.

[0057] In forming the resist pattern 50, first, a dry film resist is attached onto the electroless plating layer 42. Second, the dry film attached onto the electroless plating layer 42 is exposed and developed. As a result, the dry film resist is partially removed to form the resist pattern 50 having the openings 51. Third, the surface of the electroless plating layer 42 exposed from the openings 51 is cleaned by, for example, plasma or the like.

[0058] FIG. 8 is a cross-sectional view for explaining the electrolytic plating step S4. In the electrolytic plating step S4, as shown in FIG. 8, electrolytic plating is performed by applying current to the seed layer 41 and the electroless plating layer 42, so that an electrolytic plating layer 43 is formed on the electroless plating layer 42 exposed from the openings 51. At this time, the electrolytic plating layer 43 is also embedded in the through hole 10c. The resist pattern 50 is removed after the electrolytic plating layer 43 is formed.

[0059] In the etching step S5, the electroless plating layer 42 and the seed layer 41 exposed between the adjacent portions of the electrolytic plating layer 43 are removed by etching. As a result, the printed wiring board 100 having the structure shown in FIGS. 1 to 3 is manufactured.

[0060] Note that, as shown in FIG. 4, after the etching step S5 is performed, a resin coating step S6 is performed on the printed wiring board 100. In the resin coating step S6, the first main surface 10a is resin-coated so as to cover the first conductive pattern 20, and the second main surface 10b is resin-coated so as to cover the second conductive pattern 30. Although not shown, after the etching step S5 is performed and before the resin coating step S6 is performed, an electrolytic plating step different from the electrolytic plating step S4 may be performed. As a result, the seed layer 41, the electroless plating layer 42, and the electrolytic plating layer 43 will be covered with an electrolytic plating layer different from the electrolytic plating layer 43.

[0061] (Effect of the printed wiring board 100) The effect of the printed wiring board 100 will be described below.

[0062] When the etching step S5 is being performed, the etching solution flows more easily around the first wiring portions 21a and 21b (the first wiring portions 31a and 31b) than around the third wiring portion 21c (the third wiring portion 31c), and etching progresses more easily.

[0063] As a result, when the first conductive pattern 20 (the second conductive pattern 30) is designed such that the widths W1 and W2 (the widths W4 and W5) are the same as the width W3 (the width W6), the widths W1 and W2 (the widths W4 and W5) become smaller than the width W3 (the width W6), and the first conductive pattern 20 (the second conductive pattern 30) is likely to peel off from the base film 10 at the first wiring portions 21a and 21b (the first wiring portions 31a and 31b). This becomes more apparent as the width of the first conductive pattern 20 (the second conductive pattern 30) becomes smaller.

[0064] Outside the first wiring portion 21a and the second wiring portion 21b (the first wiring portion 31a and the second wiring portion 31b), due to the flow of the etching solution, the vicinity of the boundary between the electroless plating layer 42 and the electroplating layer 43 is likely to be etched. Therefore, in the printed wiring board 100, the widths W1 and W2 (widths W4 and W5) are 1.1 times or more and 4.0 times or less the average value of the width W3 (width W6). As a result, the value obtained by dividing the ground width W11 by the average value of the ground width W31 and the value obtained by dividing the ground width W21 by the average value of the ground width W31 (the value obtained by dividing the ground width W41 by the average value of the ground width W61 and the ground width W51 of ground width W61 the average value divided by the value) are often 1.0 or more. When the resin coating step S6 is performed, a force is more likely to be applied to the first wiring portion 21a and the second wiring portion 21b (the first wiring portion 31a and the second wiring portion 31b) compared to the third wiring portion 21c (the third wiring portion 31c). However, in the printed wiring board 100, since the ground widths W11 and W21 (ground widths W41 and W51) are ensured, a part of the first conductive pattern 20 (the second conductive pattern 30) is suppressed from peeling off from the base film 10 in the first wiring portion 21a and the second wiring portion 21b (the first wiring portion 31a and the second wiring portion 31b).

[0065] If the thickness T1 (thickness T2) is increased (more specifically, made 40 μm or more), it is necessary to increase the thickness of the resist pattern 50. When the thickness of the resist pattern 50 increases, the depth of the opening 51 increases, so the plasma during cleaning hardly reaches the surface of the electroless plating layer 42, and the residue of the dry film resist is likely to remain on the surface of the electroless plating layer 42. As a result, voids are likely to occur at the interface between the electroless plating layer 42 and the electroplating layer 43.

[0066] Void present at the interface between the electroless plating layer 42 and the electroplating layer 43 is a factor that reduces the adhesion between the electroless plating layer 42 and the electroplating layer 43. Further, when a void exists at the interface between the electroless plating layer 42 and the electroplating layer 43, in the etching step S5, side etching along the interface between the electroless plating layer 42 and the electroplating layer 43 tends to proceed. From another perspective, when a void exists at the interface between the electroless plating layer 42 and the electroplating layer 43, in the etching step S5, a notch is likely to be formed at the interface between the electroless plating layer 42 and the electroplating layer 43. This notch can be a starting point for the peeling of the first conductive pattern 20 (second conductive pattern 30).

[0067] In addition, when the distance DIS1 (distance DIS2) becomes small (more specifically, when it becomes 20 μm or less), it becomes difficult for the etching solution to enter between adjacent portions of the electroplating layer 43, and the etching step S5 requires a long time, so the above side etching is more likely to occur.

[0068] In the printed wiring board 100, the width W1 and the width W2 (width W4 and width W5) are each 1.1 times or more and 4.0 times or less the average value of the width W3 (width W6), and the area of the interface between the electroless plating layer 42 and the electroplating layer 43 in the first wiring portion 21a and the second wiring portion 21b (first wiring portion 31a and second wiring portion 31b) can be ensured. Therefore, even if there is a decrease in adhesion due to the above voids and the occurrence of the above notches, the peeling of the first conductive pattern 20 (second conductive pattern 30) from the base film 10 in the first wiring portion 21a and the second wiring portion 21b (first wiring portion 31a and second wiring portion 31b) is suppressed.

[0069] (Example) Samples 1 to 7 were prepared to evaluate the influence of the ratios of widths W1 and W2 to the average value of width W3 on the peeling of the first conductive pattern 20. Ten samples each were prepared from Samples 1 to 7. The details of Samples 1 to 7 are shown in Table 1. In Samples 1 to 7, the average values of widths W1, W2, and W3, the thickness T1, and the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 were varied.

[0070] The peeling occurrence rates in Table 1 were evaluated in three levels: "A", "B", and "C". Note that "A" in Table 1 indicates that no peeling occurred in the first conductive pattern 20 (peeling occurrence rate 0 percent). "B" and "C" in Table 1 indicate that peeling occurred in at least a part of the first conductive pattern 20. More specifically, "B" and "C" in Table 1 indicate that the peeling occurrence rates are more than 0 percent and less than or equal to 20 percent, and more than 20 percent and less than or equal to 100 percent, respectively. The presence or absence of peeling of the first conductive pattern 20 was observed visually or using a microscope.

[0071]

Table 1

[0072] In Samples 1 to 7, the values obtained by dividing width W1 by the average value of width W3 and the values obtained by dividing width W2 by the average value of width W3 were varied. In Sample 1, the values obtained by dividing width W1 by the average value of width W3 and the values obtained by dividing width W2 by the average value of width W3 were less than 1.1, while in Samples 2 to 7, the values obtained by dividing width W1 by the average value of width W3 and the values obtained by dividing width W2 by the average value of width W3 were in the range of 1.1 or more and 4.0 or less.

[0073] In Sample 1, the value obtained by dividing the ground width W11 by the average value of the ground width W31 and the value obtained by dividing the ground width W21 by the average value of the ground width W31 were less than 1.0. On the other hand, in Samples 2 to 7, the value obtained by dividing the ground width W11 by the average value of the ground width W31 and the value obtained by dividing the ground width W21 by the average value of the ground width W31 were 1.0 or more. Also, in Sample 1, the evaluation of the peeling rate of the first conductive pattern 20 was C. On the other hand, in Samples 2 to 7, the evaluation of the peeling rate of the first conductive pattern 20 was B or more. From this, it became clear that by setting the width W1 and the width W2 to be 1.1 times or more and 4.0 times or less the average value of the width W3, the ground widths W11 and W21 can be made equal to or greater than the ground width W31, and partial peeling of the first conductive pattern 20 in the first wiring portion 21a and the second wiring portion 21b can be suppressed.

[0074] In Samples 2 to 6, the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 was 5.5 μm 2 / μm or less. In Sample 7, the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 was more than 5.5 μm 2 / μm. In Samples 2 to 6, the evaluation of the peeling rate of the first conductive pattern 20 was A. On the other hand, in Sample 7, the evaluation of the peeling rate of the first conductive pattern 20 was B. From this, it became clear that by setting the void density at the interface between the electroless plating layer 42 and the electroplating layer 43 to 5.5 μm 2 / μm or less, further suppression of partial peeling of the first conductive pattern 20 in the first wiring portion 21a and the second wiring portion 21b can be achieved.

[0075] (Modified Example) In the above description, the case where the printed wiring board 100 has both the first conductive pattern 20 and the second conductive pattern 30 has been described. However, the printed wiring board 100 may not have either the first conductive pattern 20 or the second conductive pattern 30. Also, in the above description, the case where the first conductive pattern 20 and the second conductive pattern 30 are wound in a spiral shape has been described. However, the first conductive pattern 20 and the second conductive pattern 30 may not be wound in a spiral shape.

[0076] In the above description, the case where the first conductive pattern 20 and the second conductive pattern 30 are formed by the semi-additive method (that is, the case where the first conductive pattern 20 and the second conductive pattern 30 have the seed layer 41, the electroless plating layer 42, and the electroplating layer 43) has been described. However, the first conductive pattern 20 and the second conductive pattern 30 may be formed by the subtractive method.

[0077] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the above embodiments, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Explanation of Reference Numerals

[0078] 10 Base film, 10a First main surface, 10b Second main surface, 10c Through hole, 20 First conductive pattern, 20a, 20b Lands, 21 Wiring portion, 21a First wiring portion, 21b Second wiring portion, 21c Third wiring portion, 30 Second conductive pattern, 30a, 30b Lands, 31 Wiring portion, 31a First wiring portion, 31b Second wiring portion, 31c Third wiring portion, 41 Seed layer, 41a First layer, 41b Second layer, 42 Electroless plating layer, 43 Electroplating layer, 50 Resist pattern, 51 Opening, 100 Printed wiring board, DIS1 Distance, DIS2 Distance, DR1 First direction, DR2 Second direction, S1 Preparation process, S2 Electroless plating process, S3 Resist pattern formation process, S4 Electroplating process, S5 Etching process, S6 Resin coating process, T1, T2 Thickness, W1, W2, W3, W4, W5, W6 Width, W11, W21, W31, W41, W51, W61 Ground width.

Claims

1. A base film having a main surface, and a conductive pattern disposed on the main surface, wherein the normal line of the main surface is along a first direction, the conductive pattern has a plurality of wiring portions arranged at intervals along a second direction orthogonal to the first direction, the conductive pattern has a seed layer disposed on the main surface, an electroless plating layer disposed on the seed layer, and an electrolytic plating layer disposed on the electroless plating layer, and the void density at the interface between the electroless plating layer and the electrolytic plating layer is more than 0.01 μm² / μm, the plurality of wiring portions include a first wiring portion and a second wiring portion at both ends in the second direction, and a plurality of third wiring portions between the first wiring portion and the second wiring portion in the second direction, in the second direction, the widths of the first wiring portion and the second wiring portion are 1.1 times or more and 4.0 times or less the average value of the widths of the plurality of third wiring portions, in the second direction, the widths of the seed layer and the electroless plating layer of each of the first wiring portion and the second wiring portion are larger than the widths of the seed layer and the electroless plating layer of each of the plurality of third wiring portions, the conductive pattern is wound in a spiral shape in a plan view to form a coil, the first wiring portion is at the innermost circumference of the coil, the second wiring portion is at the outermost circumference of the coil, a printed wiring board.

2. The printed wiring board according to claim 1, wherein the electroless plating layer and the electrolytic plating layer are formed of copper.

3. The printed wiring board according to claim 1, wherein the widths of the first wiring portion and the second wiring portion are 5 μm or more and 60 μm or less.

4. The printed wiring board according to claim 1, wherein the thickness of the conductive pattern is 5 μm or more and 150 μm or less.

5. The void density at the interface between the electroless plating layer and the electrolytic plating layer is 5.5 µm ２ / μm or less. The printed wiring board according to claim 1

6. The printed wiring board according to claim 1, wherein the distance between two adjacent ones of the plurality of wiring portions in the second direction is 20 μm or less.

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