Integrated Circuit and Power Supply Circuit

Abstract

To provide an integrated circuit and a power supply circuit capable of improving a power factor in response to a state of a load irrespective of a phase of a voltage of an AC power supply.SOLUTION: An AC-DC converter includes a first inductor, an MOS transistor, and a power-factor improvement IC for controlling the transistor. The power-factor improvement IC comprises: a comparison circuit 40 for detecting whether or not an inductor current reaches a first predetermined value on the basis of a first voltage Vzcd corresponding to the inductor current; a signal output circuit operated in a first mode for outputting a signal to turn on the transistor when the inductor current reaches the first predetermined value or a second mode for outputting the signal when the inductor current reaches the first predetermined value and a first period of time elapses; a control circuit for allowing the signal output circuit to operate in the first mode when an amplitude of the first voltage after the inductor current reaches the first predetermined value is less than a second predetermined value, and allowing the signal output circuit to operate in the first mode or the second mode when the amplitude is larger than the second predetermined value; and a drive circuit for turning on / off the transistor.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a power supply circuit.

Background Art

[0002] Conventionally, in a power supply circuit that outputs a DC voltage of a target level from an AC power supply to a load, an integrated circuit that controls a switching element to improve the power factor has been provided (see, for example, Patent Documents 1 and 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such an integrated circuit, generally, when the load is in a light load state, there is a circuit that performs an operation of reducing the switching frequency in order to reduce the switching loss. Specifically, the integrated circuit lengthens the standby period from when the switching element is turned off until the inductor current becomes zero until the switching element is turned on.

[0005] However, when the voltage of the AC power supply reaches a high phase angle, the standby period is not appropriately set inside the integrated circuit, and the switching element may be turned on with a standby period longer than desired by the restart timer. In this case, noise may occur in the output current, and the power factor may deteriorate.

[0006] The present invention provides an integrated circuit and a power supply circuit capable of improving the power factor regardless of the phase of the voltage of the AC power supply.

Means for Solving the Problems

[0007] In order to solve the above problems, in a first aspect of the present invention, there is provided an integrated circuit that controls the switching of a transistor of a power supply circuit that includes a first inductor to which a rectified voltage corresponding to an AC voltage is applied and a transistor that controls an inductor current flowing through the first inductor, and generates an output voltage of a target level from the AC voltage. The integrated circuit includes a first detection circuit that detects whether or not the inductor current has reached a first predetermined value based on a first voltage corresponding to the inductor current, a signal output circuit that operates in a first mode in which a signal for turning on the transistor is output when the inductor current reaches the first predetermined value, or a second mode in which the signal is output when the inductor current reaches the first predetermined value and a first period has elapsed, a control circuit that operates the signal output circuit in the first mode when an amplitude of the first voltage after the inductor current has reached the first predetermined value is smaller than a second predetermined value, and operates the signal output circuit in the first mode or the second mode when the amplitude is larger than the second predetermined value, and a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage. When the amplitude is larger than the second predetermined value, the signal output circuit operates in a mode corresponding to a state of a load of the power supply circuit among the first mode and the second mode.

[0008] A second aspect of the present invention provides a power supply circuit that generates an output voltage of a target level from an AC voltage. The power supply circuit includes a first inductor to which a rectified voltage corresponding to the AC voltage is applied, a transistor that controls the inductor current, and an integrated circuit that controls switching of the transistor. The integrated circuit includes: a first detection circuit that detects whether the inductor current reaches a first predetermined value based on a first voltage corresponding to the inductor current; a signal output circuit that operates in a first mode that outputs a signal to turn on the transistor when the inductor current flowing through the first inductor reaches the first predetermined value, or in a second mode that outputs the signal when a first period has elapsed since the inductor current reached the first predetermined value; a control circuit that operates the signal output circuit in the first mode when the amplitude of the first voltage after the inductor current reaches the first predetermined value is smaller than a second predetermined value, and that operates the signal output circuit in the first mode or the second mode when the amplitude is greater than the second predetermined value; and a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage. When the amplitude is greater than the second predetermined value, the signal output circuit operates in one of the first mode and the second mode, depending on the state of the load on the power supply circuit. [Effects of the Invention]

[0009] It is possible to provide an integrated circuit and a power supply circuit that can improve the power factor regardless of the phase of the voltage of the AC power supply.

[0010] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

[0012] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0013] In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrical connection." In this specification, when a voltage or signal has a high logic level, it is referred to as an "H" level, and when the logic level is a low logic level, it is referred to as an "L" level.

[0014] FIG. 1 shows an example of the configuration of a general AC-DC converter 10a. The AC-DC converter 10a is a boost chopper type power supply circuit that generates an output voltage Vout at a target level from the AC voltage Vac of the AC power supply 11. The AC-DC converter 10a drives the load 12 with the output voltage Vout.

[0015] Here, the AC power supply 11 is a commercial AC power supply for supplying the AC voltage Vac to the AC-DC converter 10a. The AC voltage Vac is, for example, a voltage of 100 to 277 V and a frequency of 50 to 60 Hz. Also, the load 12 is, for example, a DC-DC converter or an electronic device that operates with a DC voltage.

[0016] <<Configuration of AC-DC Converter 10a>> The AC-DC converter 10a includes an inductor 21, capacitors 22, 24, 28, 36, 37, a full-wave rectifier circuit 23, a transformer 25, resistors 26, 31 to 35, a diode 27, a power factor correction IC 29a, and a MOS transistor 30.

[0017] ==Input to Full-Wave Rectifier Circuit 23== The inductor 21 and the capacitor 22 remove noise from the voltage Vac and the current supplied from the AC power supply 11 to the full-wave rectifier circuit 23. From the AC power supply 11 through the inductor 21 and the capacitor 22, a voltage with noise removed from the voltage Vac and an input current Iin are supplied to the full-wave rectifier circuit 23.

[0018] ==Configuration from Full-Wave Rectifier Circuit 23 to Load 12== The full-wave rectifier circuit 23 full-wave rectifies a predetermined AC voltage Vac with noise removed and applies it as a rectified voltage Vrec to the capacitor 24 and the primary coil L1 of the transformer 25.

[0019] The capacitor 24 smoothes the rectified voltage Vrec supplied from the full-wave rectifier circuit 23.

[0020] The transformer 25 includes a main coil L1 and an auxiliary coil L2 magnetically coupled to the main coil L1. Note that the auxiliary coil L2 of this embodiment is wound such that the polarity of the voltage generated in the auxiliary coil L2 is opposite to the polarity of the voltage generated in the main coil L1.

[0021] The auxiliary coil L2 is connected to the terminal ZCD of the power factor improvement IC 29a (described later) via a resistor 26. Since a current corresponding to the inductor current IL flowing through the main coil L1 flows through the auxiliary coil L2, a voltage Vzcd corresponding to the inductor current IL is applied to the terminal ZCD.

[0022] The main coil L1 of the transformer 25 forms a boost chopper circuit together with a diode 27 and a capacitor 28. As a result, the charging voltage of the capacitor 28 is boosted to the DC output voltage Vout and supplied to the load 12.

[0023] The power factor improvement IC 29a is an integrated circuit that controls the switching of the MOS transistor 30 so as to improve the power factor of the AC-DC converter 10a and make the level of the output voltage Vout reach a target level (for example, 400V). The power factor improvement IC 29a drives the MOS transistor 30 based on the inductor current IL flowing through the main coil L1 and the output voltage Vout.

[0024] The power factor improvement IC 29a includes terminals CS, COMP, FB, RT, OUT, and ZCD. Note that the power factor improvement IC 29a has terminals other than the terminals CS, COMP, FB, RT, OUT, and ZCD (for example, a power supply terminal, a GND terminal, etc.), but other terminals in the figure are omitted.

[0025] The MOS transistor 30 is a power transistor for controlling the power supplied to the load 12 of the AC-DC converter 10a. Specifically, the MOS transistor 30 controls the inductor current IL flowing through the main coil L1 of the transformer 25.

[0026] In this embodiment, the MOS transistor 30 is an N-type MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. That is, the MOS transistor 30 may be any transistor that can control power, and may be, for example, a bipolar transistor. Here, the gate electrode of the MOS transistor 30 is connected to the terminal OUT of the power factor correction IC 29a.

[0027] 2, a voltage Vdr is applied from a power factor correction IC 29a to the gate electrode of the MOS transistor 30. The power factor correction IC 29a controls the power to the load 12 by controlling the timing at which the voltage level of the voltage Vdr is changed.

[0028] Resistor 31 generates a voltage Vcs according to the drain-source current of MOS transistor 30. Since the drain-source current of MOS transistor 30 changes according to inductor current IL, the inductor current IL can be detected by detecting voltage Vcs generated across resistor 31. One end of resistor 31 is connected to the source electrode of MOS transistor 30, and the other end is grounded. The voltage Vcs generated across resistor 31 is applied to terminal CS.

[0029] The resistor 32 is a resistor for adjusting the oscillation frequency of the oscillation circuit 44 (described later in FIG. 2). The resistor 32 is connected to the terminal RT, and the oscillation frequency is adjusted according to the resistance value of the resistor 32.

[0030] Resistors 33 and 34 generate a feedback voltage Vfb according to the output voltage Vout, which is used to switch the MOS transistor 30. A voltage divider circuit formed by the resistors 33 and 34 applies the divided voltage Vfb as a feedback voltage to a terminal FB of the power factor correction IC 29a.

[0031] Resistor 35 and capacitors 36 and 37 are phase compensation elements used for feedback control. Resistor 35 and capacitor 36 are connected in series between terminal COMP and ground. Capacitor 37 is connected in parallel to resistor 35 and capacitor 36.

[0032] ==Configuration of Power Factor Correction IC29b== 2 shows an example of the configuration of a general power factor correction IC 29a. The power factor correction IC 29a includes a comparison circuit 40, a signal output circuit 41a, a restart timer 42, a drive circuit 43, an oscillation circuit 44, an error amplifier circuit 45, and comparison circuits 46 to 48.

[0033] The comparator circuit 40 detects whether the inductor current IL has become "0" based on the voltage Vzcd applied to the terminal ZCD. Because the auxiliary coil L2 is electromagnetically coupled to the main coil L1, the voltage Vzcd applied to the terminal ZCD is a voltage that corresponds to the inductor current IL flowing through the main coil. Here, "0" (zero) means "almost zero," and hereinafter, "almost zero" will be referred to simply as "0" (zero) where appropriate.

[0034] Specifically, the comparator circuit 40 compares the voltage Vzcd with the threshold value Vthl when the inductor current IL indicates 0. When the inductor current IL becomes 0, the comparator circuit 40 outputs a signal Vcomp1 at an “H” level.

[0035] Here, after the MOS transistor 30 is turned off and the inductor current IL indicates 0, it oscillates sinusoidally due to resonance between the inductance of the transformer 25 and the parasitic capacitance of the circuit, including the MOS transistor 30. As a result, the voltage Vzcd also oscillates sinusoidally after the MOS transistor 30 is turned off and the voltage Vzcd indicates the threshold value Vthl.

[0036] In the power factor improvement IC 29a, the comparison circuit 40 is a hysteresis comparator. That is, the comparison circuit 40 has, in addition to the threshold voltage Vthl, a different threshold voltage Vthh determined according to hysteresis in response to the applied voltage Vhc. The comparison circuit 40 also performs a comparison based on the threshold voltage Vthh for the oscillation of the voltage Vzcd. The threshold voltage Vthl and the threshold voltage Vthh will be described in detail later with reference to FIGS. 5 and 6.

[0037] The comparison circuit 40 compares the voltage Vzcd with the threshold voltage Vthh, and outputs a signal Vcomp1 corresponding to the comparison result to the signal output circuit 41a and the restart timer 42.

[0038] After the inductor current IL becomes 0, the signal output circuit 41a outputs a signal Von for turning on the MOS transistor 30 in any one of the critical mode, the bottom skip mode, or the operation mode of the restart timer 42.

[0039] The restart timer 42 outputs a signal for turning on the MOS transistor 30, for example, when the load 12 becomes a light load state and the comparison circuit 40 can no longer detect that the voltage Vzcd exceeds the threshold voltage Vthh. The operation of the restart timer 42 will be described in detail later with reference to FIG. 6.

[0040] Note that the "light load state" of the load 12 is, for example, a state in which the current flowing through the load 12 becomes equal to or less than a predetermined value (for example, 100 mA). In this case, the state that is not the "light load state" refers to a state in which the current flowing through the load 12 becomes greater than 100 mA. Further, the "heavy load state" of the load 12 is a state in which the current flowing through the load 12 becomes equal to or greater than a different predetermined value (for example, 1.0 A).

[0041] Specifically, the restart timer 42 measures the period after the inductor current IL becomes 0 based on the signal Vcomp1. Then, when the "H" level signal Vcomp1 continues to be output for a period exceeding Trst (for example, 10 to 20 μs), the restart timer 42 outputs a signal for turning on the MOS transistor 30.

[0042] Based on the signal Von output by the signal output circuit 41a, the drive circuit 43 turns on the MOS transistor 30, and as will be described later, based on the feedback voltage Vfb corresponding to the output voltage Vout, for example, turns off the MOS transistor 30. Specifically, when turning on the MOS transistor 30, the drive circuit 43 applies a voltage Vdr of "H" level to the terminal OUT, and when turning off the MOS transistor 30, applies a voltage Vdr of "L" level to the terminal OUT. The drive circuit 43 includes an OR circuit 52, an RS flip-flop 53, and a buffer circuit 54.

[0043] The oscillation circuit 44 outputs a ramp wave Vr with an oscillation frequency corresponding to the resistance value of the resistor 31 to the comparison circuit 46.

[0044] The error amplification circuit 45 is a transconductance amplifier and outputs a current Ie corresponding to the difference between the feedback voltage Vfb and the reference voltage Ve. As a result, the capacitors 36 and 37 connected to the terminal COMP are charged by the current Ie. Here, the reference voltage Ve is a voltage determined according to the output voltage Vout at the target level. Also, let the voltage of the terminal COMP to which the output of the error amplification circuit 45 is connected be the voltage Vcmp.

[0045] The comparison circuit 46 compares the ramp wave Vr output by the oscillation circuit 44 with the voltage Vcmp applied to the terminal COMP. When the level of the ramp wave Vr is lower than the voltage Vcmp, the comparison circuit 46 outputs a signal Vcomp2 of "L" level to the drive circuit 43, and when the level of the ramp wave Vr becomes higher than the voltage Vcmp, outputs a signal Vcomp2 of "H" level for turning off the transistor to the OR circuit 52.

[0046] The comparison circuit 47 determines whether or not the output voltage Vout has become an overvoltage based on the feedback voltage Vfb. Specifically, the comparison circuit 46 compares the feedback voltage Vfb corresponding to the output voltage Vout with a threshold voltage Vov indicating that the output voltage Vout is in an overvoltage state.

[0047] When the feedback voltage Vfb is higher than the threshold voltage Vov, the comparison circuit 47 determines that it is an overvoltage and outputs an "H"-level signal Vcomp3 that turns off the MOS transistor 30 to the OR circuit 52. Also, when the feedback voltage Vfb is lower than the threshold voltage Vov, the comparison circuit 46 determines that it is not an overvoltage and outputs an "L"-level signal Vcomp3 to the OR circuit 52.

[0048] The comparison circuit 48 determines whether or not the inductor current IL has become an overcurrent based on the voltage Vcs. Specifically, the comparison circuit 47 compares the voltage Vcs with a threshold voltage Voc indicating that the inductor current IL is in an overcurrent state.

[0049] When the voltage Vcs is higher than the threshold voltage Voc, the comparison circuit 48 determines that it is an overcurrent and outputs an "H"-level signal Vcomp4 that turns off the MOS transistor 30. Also, when the feedback voltage Vfb is lower than the threshold voltage Voc, the comparison circuit 46 determines that it is not an overcurrent and outputs an "L"-level signal Vcomp4.

[0050] ==Configuration of the signal output circuit 41a== Furthermore, the internal configuration of the signal output circuit 41a will be described. The signal output circuit 41a includes a frequency reduction circuit 50a and an OR circuit 51.

[0051] After the inductor current IL becomes 0, the frequency reduction circuit 50a outputs a signal that turns on the MOS transistor 30 in the critical mode or the bottom skip mode to the OR circuit 51. For a more specific configuration of the frequency reduction circuit 50a, refer to FIG. 3 which will be described later.

[0052] When a signal from either the frequency reduction circuit 50a or the restart timer 42 becomes an "H"-level, the OR circuit 51 outputs an "H"-level signal Von for turning on the MOS transistor 30 to the RS flip-flop 53 of the drive circuit 43.

[0053] ==Details of the drive circuit 43== When any of the signals Vcomp2, Vcomp3, and Vcomp4 is at the "H" level, the OR circuit 52 supplies an "H" level signal for turning off the MOS transistor 30 to the R input of the RS flip-flop 53.

[0054] When an "L" level signal is input to the R input of the RS flip-flop 53, the RS flip-flop 53 outputs a signal Vq1 for turning on and off the MOS transistor 30 from the Q output according to the level of the signal input to the S input. On the other hand, when an "H" level signal for turning off the MOS transistor 30 is input to the R input of the RS flip-flop 53, the RS flip-flop 53 outputs an "L" level signal Vq1 for turning off the MOS transistor 30 from the Q output.

[0055] The buffer circuit 54 turns on and off the MOS transistor 30 according to the level of the signal Vq1 output from the RS flip-flop 53. Specifically, based on the "H" level signal Vq1, the buffer circuit 54 changes the voltage Vdr to the "H" level to turn on the MOS transistor 30. On the other hand, based on the "L" level signal Vq1, the buffer circuit 54 changes the voltage Vdr to the "L" level to turn off the MOS transistor 30.

[0056] As a result, the drive circuit 43 changes the voltage Vdr to make the output voltage Vout the target level, and turns off the MOS transistor 30 when an abnormality such as an overcurrent is detected.

[0057] ==Details of the Frequency Reduction Circuit 50a== FIG. 3 shows an example of the configuration of the frequency reduction circuit 50a. The frequency reduction circuit 50a includes a load state determination circuit 60 and an output circuit 61.

[0058] The load state determination circuit 60 determines whether the load 12 is in a light load state based on the period from when the MOS transistor 30 is turned on until the inductor current IL becomes 0.

[0059] Here, when the load 12 is in a light load state, the power consumed by the load 12 decreases. In this case, the power sent from the full-wave rectifier circuit 23 to the load 12 via the transformer 25 and the boost chopper circuit decreases. Therefore, the inductor current IL flowing through the main coil L1 in the transformer 25 also decreases.

[0060] That is, when the load 12 is in a light load state, the peak of the inductor current IL becomes low. Therefore, from the timing when the MOS transistor 30 is turned on, the MOS transistor 30 is turned off, and the period until the inductor current IL becomes 0 is shortened. Therefore, when the load 12 is in a light load state, the switching frequency of the MOS transistor 30 increases.

[0061] Conversely, when the load 12 is in a heavy load state, the peak of the inductor current IL becomes high. Therefore, when the load 12 is in a heavy load state, the period from the timing when the MOS transistor 30 is turned on to the timing when the inductor current IL becomes 0 after the MOS transistor 30 is turned off becomes long. The load state determination circuit 60 determines the state of the load 12 by detecting this period.

[0062] ===Details of the Load State Determination Circuit 60 === The load state determination circuit 60 includes a timing detection circuit 70, a timing circuit 71, and a D flip-flop 72.

[0063] The timing detection circuit 70 detects the timing when the inductor current IL indicates 0 after the MOS transistor 30 is turned off.

[0064] Specifically, the timing detection circuit 70 outputs a low-level signal to the D input of the D flip-flop 72 in response to a high-level signal Vq1 indicating the timing at which the MOS transistor 30 turns on. After that, the timing detection circuit 70 changes the signal output to the D input of the D flip-flop 72 to high level based on a high-level signal Vcomp1 indicating the timing at which the inductor current IL becomes zero after the MOS transistor 30 turns off.

[0065] After the MOS transistor 30 is turned on, the timing circuit 71 measures a period Ta for determining whether the load 12 is in a light load state. Specifically, the timing circuit 71 starts timing from the timing when the signal Vq1 becomes "H" level, and outputs an "H" level signal to the CK input of the D flip-flop 72. Thereafter, when a predetermined period Ta for determining the state of the load 12 has elapsed, the timing circuit 71 changes the signal output to the CK input of the D flip-flop 72 to "L" level.

[0066] The D flip-flop 72 determines whether the period during which the inductor current IL becomes 0 after the MOS transistor 30 is turned on is longer than the period Ta, and whether this is earlier than the timing for determining whether the load 12 is in a light load state.

[0067] Specifically, when the signal output from the timer circuit 71 to the CK input changes to the "L" level, the D flip-flop 72 outputs from its Q output a signal corresponding to the level of the signal output from the timing detection circuit 70 to its D input. Therefore, the state of the load 12 can be determined based on the level of the signal output from the Q output of the D flip-flop 72.

[0068] As a result, the load state determination circuit 60 compares the period from the timing when the MOS transistor 30 turns on to the timing when the inductor current IL becomes 0 with the period Ta. When the period Ta is longer, the load state determination circuit 60 determines that the load 12 is in a light load state. When the period Ta is shorter, the load state determination circuit 60 determines that the load 12 is not in a light load state.

[0069] ==Output Circuit 61== The output circuit 61 detects that the inductor current IL flowing through the main coil L1 has become 0 based on the signal Vcomp1. Thereafter, when the load state determination circuit 60 outputs a determination result indicating that the load 12 is in a light load state, the output circuit 61 outputs a signal to turn on the MOS transistor 30 in the bottom skip mode. On the other hand, when the load state determination circuit 60 outputs a determination result indicating that the state of the load 12 is not a light load state, the output circuit 61 outputs a signal to turn on the MOS transistor 30 in the critical mode.

[0070] ===Critical Mode=== Here, the "critical mode" is a mode in which when the voltage Vzcd becomes the voltage Vthl indicating that the inductor current IL is 0 after the MOS transistor 30 turns off, the output circuit 61 outputs a signal to turn on the MOS transistor 30. As a result, in the critical mode, the period during which the inductor current IL becomes discontinuous is substantially zero.

[0071] Note that when the load is not in a light load state, the output circuit 61 of the AC-DC converter 10a outputs a signal to turn on the MOS transistor 30 in the critical mode. Hereinafter, the details of the critical mode will be described with reference to FIG. 4.

[0072] Here, the description starts from the time t1 when the drive circuit 43 outputs a signal Vq1 of "H" level to turn on the MOS transistor 30 after the MOS transistor 30 turns off.

[0073] At time t1, the signal output circuit 41a in Fig. 2 outputs a pulse-like signal Von to turn on the MOS transistor 30 in Fig. 1. This causes the RS flip-flop 53 in the drive circuit 43 to output a high-level signal Vq1. When the MOS transistor 30 turns on, the inductor current IL begins to rise.

[0074] When the MOS transistor 30 is turned on, a current flows between the drain and source of the MOS transistor 30, causing the voltage across the main coil L1 of the transformer 25 to rise. Meanwhile, the voltage across the auxiliary coil L2, which has the opposite polarity to that of the main coil L1, drops. This also causes the voltage Vzcd applied to the terminal ZCD to drop below the threshold voltage Vthl. Therefore, at time t1, the comparator circuit 40 changes the level of the signal Vcomp1 to the "H" level.

[0075] Furthermore, the oscillation circuit 44 outputs a ramp wave Vr whose voltage level gradually increases from the timing when the MOS transistor 30 is turned on.

[0076] At time t2, the level of the ramp wave Vr output by the oscillation circuit 44 becomes higher than the voltage Vcmp applied to the terminal COMP. In this case, the comparator circuit 46 outputs a signal Vcomp2 at the "H" level.

[0077] In response to the high-level signal Vcomp2, the RS flip-flop 53 of the drive circuit 43 can output a low-level signal Vq1 to turn on the MOS transistor 30. In addition, the buffer circuit 54 reduces the voltage Vdr.

[0078] Therefore, at time t2, the MOS transistor 30 is turned off. Because the MOS transistor 30 is turned off, the voltage of the main coil L1 of the transformer 25 decreases, and the voltage Vzcd having the opposite polarity increases.

[0079] At time t3, when the inductor current IL flowing through the main coil L1 decreases, a current flows through the circuit due to resonance between the inductance of the main coil and the parasitic capacitance of the circuit such as the parasitic capacitance of the MOS transistor 30. In this case, the voltage across both ends of the main coil L1 increases and the voltage Vzcd decreases.

[0080] At time t4, the comparison circuit 40 determines that the voltage Vzcd applied to the terminal ZCD has become equal to or lower than the threshold voltage Vthl. As a result, it is detected that the inductor current IL flowing through the main coil L1 has become zero. In response to the detection result, the comparison circuit 40 changes the level of the output signal Vcomp1 from the "L" level to the "H" level.

[0081] In the critical mode, when it is detected that the inductor current IL flowing through the main coil has become zero, the signal output circuit 41a outputs an "H" level signal Von for turning on the MOS transistor 30.

[0082] In response to this, the RS flip-flop 53 outputs an "H" level signal Vq1. Also, the buffer circuit 54 raises the voltage Vdr applied to the gate electrode of the MOS transistor 30.

[0083] At time t4, similar to time t1, the drive circuit 43 turns on the MOS transistor 30. After time t4, the same operation as the period from time t1 to time t4 is repeated. Since the load 12 is not in a light load state, in the figure, the period from time t1 to time t4 (the period after turning on the MOS transistor 30 until turning off the MOS transistor 30 and the inductor current IL becomes zero) is shown to be longer than the period Ta.

[0084] ===Bottom Skip Mode=== First, the case where the output circuit 61 in FIG. 3 operates in the bottom skip mode will be described with reference to FIG. 5. The "bottom skip mode" is a mode in which after turning off the MOS transistor 30, when the voltage Vzcd becomes the voltage Vthl at which the inductor current IL indicates 0, after waiting for a certain period, the output circuit 61 outputs a signal to turn on the MOS transistor 30.

[0085] That is, in the bottom skip mode, after the MOS transistor 30 is turned off, the inductor current IL indicates 0, and the timing at which the MOS transistor 30 is turned on again is after the timing of the first minimum value (bottom) shown by the oscillation of the voltage Vzcd.

[0086] Note that since the inductor current IL, the signal Von, and the ramp wave Vr are the same as those in FIG. 4, they are not shown in the waveform diagrams after FIG. 5. Also, the operation waveform diagram is for the purpose of explanation, and there are differences in dimensions such as the time direction between FIG. 4 and the figures after FIG. 5.

[0087] When the load state determination circuit 60 determines that the load 12 is in a light load state, the output circuit 61 operates in the bottom skip mode. That is, it is the operation of the load state determination circuit 60 when the period from the timing of turning on the MOS transistor 30 to the timing of turning off the MOS transistor 30 until the inductor current IL becomes 0 is shorter than the period Ta.

[0088] Here, the operation of the output circuit 61 from the time t11 when the MOS transistor 30 is turned on to the time t12 when the MOS transistor 30 is turned off and the voltage Vzcd indicates the threshold value Vthl is common to FIG. 4. Below, the operation of the circuit included in the power factor improvement IC29a after the time t12 will be described.

[0089] At time t12, the comparison circuit 40 determines that the voltage Vzcd applied to the terminal ZCD has become smaller than the threshold voltage Vthl. As a result, it is detected that the inductor current IL flowing through the main coil L1 has become zero. According to the detection result, the comparison circuit 40 changes the level of the output signal Vcomp1 from the "L" level to the "H" level.

[0090] In the bottom skip mode, after turning off the MOS transistor 30 and detecting that the inductor current IL has become zero by the comparison circuit 40, after waiting for a predetermined period Tbs, the signal output circuit 41a outputs a signal Von for turning on the MOS transistor 30.

[0091] After time t12, the inductor current IL and the voltage Vzcd oscillate sinusoidally after the inductor current IL becomes zero due to resonance caused by the inductance of the transformer 25 and the parasitic capacitance of the circuit by the MOS transistor 30 and the like. Note that the amplitude of the voltage Vzcd depends on the boost ratio in the boost chopper circuit composed of the main coil L1, the diode 27, and the capacitor 28. The amplitude of the voltage Vzcd becomes larger as the boost ratio is larger, and becomes smaller as the boost ratio is smaller.

[0092] Here, since the amplitude of the voltage Vzcd is larger than |threshold Vthh - threshold Vthl|, the comparison circuit 40 detects that after the voltage Vzcd indicates the threshold Vthl, the voltage Vzcd oscillates and indicates the threshold Vzcdh. When the comparison circuit 40 detects what the voltage Vzcd indicates, it changes the level of the output signal Vcomp1 to the "L" level.

[0093] That is, the comparison circuit 40 outputs a signal Vcomp1 at the "H" level while the voltage Vzcd is below the threshold Vthl and above the threshold Vthh. On the other hand, the comparison circuit 40 outputs a signal Vcomp1 at the "L" level while the voltage Vzcd is above the threshold Vthh and then below the threshold Vthl again.

[0094] At time t13, in response to the voltage Vzcd indicating the threshold value Vthh, the comparison circuit 40 changes the signal Vcomp1 it outputs to the "L" level.

[0095] After it is detected that the inductor current IL has become 0, the signal output circuit 41a waits until the number of times the voltage Vzcd becomes the threshold value Vthl after becoming the threshold value Vthh due to the oscillation of the voltage Vzcd reaches a predetermined number of times.

[0096] That is, in the bottom skip mode of the signal output circuit 41a, the predetermined period Tbs during which the signal output circuit 41a waits after the inductor current IL becomes 0 is based on the number of times the voltage Vzcd becomes the threshold value Vthl after becoming the threshold value Vthh. In the example of FIG. 5, an example where the predetermined number of times is 1 is shown, and the period from time t11 to time t13 corresponds to the period Tbs. This number of times can be set to a larger number if it is desired to further reduce the switching frequency during light load.

[0097] At time t14, the signal output circuit 41a outputs a signal Von for turning on the MOS transistor 30. As a result, the RS flip-flop 53 of the drive circuit 43 outputs a signal Vq1 of the "H" level. Also, at time t16, the comparison circuit 40 changes the level of the signal Vcomp1 to the "H" level.

[0098] At time t14, the MOS transistor 30 turns on. After time t14, the operations from time t11 to time t14 are repeated. Since the load 12 is in a light load state, in the figure, it is shown that the period from time t11 to time t12 (the period after the MOS transistor 30 is turned on until the MOS transistor 30 is turned off and the inductor current IL becomes 0) is shorter than the period Ta.

[0099] In the bottom skip mode, the output circuit 61 lengthens the period from the timing when the MOS transistor 30 turns on, after turning off the MOS transistor 30, to the timing when the MOS transistor 30 turns on again. As a result, the output circuit 61 reduces the switching frequency and reduces the switching loss.

[0100] ==Operation of restart timer 42== FIG. 6 shows an example of the operation waveforms of the restart timer 42 and the frequency reduction circuit 50a. In FIG. 6, similar to FIG. 5, the signal output circuit 41a attempts to operate in the bottom skip mode.

[0101] Here, after the MOS transistor 30 is turned off, the amplitudes of the inductor current IL and the voltage Vzcd increase as the boost ratio in the boost chopper circuit increases, and decrease as the boost ratio decreases. In FIG. 6, the case where the boost ratio decreases and the amplitude of the voltage Vzcd decreases is described.

[0102] When the signal output circuit 41a operates in the bottom skip mode, if the "H" level signal Vcomp1 continues to be output for a period longer than the period Trst, the restart timer 42 outputs a signal Vq1 to turn on the MOS transistor 30.

[0103] Here, the operation of the output circuit 61 from the time t21 when the MOS transistor 30 is turned on to the time t22 when the MOS transistor 30 is turned off and the voltage Vzcd shows the threshold value Vthl is common to FIG. 5. Below, the operation of the circuit included in the power factor improvement IC 29a after the time t22 will be described.

[0104] At the time t22, the comparison circuit 40 determines that the voltage Vzcd applied to the terminal ZCD has become smaller than the threshold voltage Vthl. As a result, it is detected that the inductor current IL flowing through the main coil L1 has become zero. According to the detection result, the comparison circuit 40 changes the level of the output signal Vcomp1 from the "L" level to the "H" level.

[0105] After the inductor current IL becomes zero, the voltage Vzcd oscillates sinusoidally. However, when the boost ratio of the boost chopper circuit is small, the amplitude of the voltage Vzcd becomes smaller than |threshold value Vthh - threshold value Vthl|.

[0106] For example, in the range where the phase angle of the input current Iin to the full-wave rectifier circuit 23 is a high phase angle, the boost ratio of the boost chopper circuit becomes small. Therefore, in the range where the phase angle of the input current Iin is a high phase angle, the amplitude of the oscillation of the voltage Vzcd may fall below |threshold value Vthh - threshold value Vthl|.

[0107] Note that the phase angles of the input current Iin and the AC voltage Vac being "high phase angles" means that the angles are in the range of, for example, 90 ± 10 + 180n degrees, that is, in the range of (80~100) + 180n degrees. On the other hand, "low phase angles" means that the angles are in the range of, for example, 0 ± 10 + 180n degrees, that is, in the range of (-10~+10) + 180n degrees. Here, n is an integer.

[0108] In the case of the bottom skip mode similar to FIG. 5, after it is detected that the inductor current IL has become zero, the signal output circuit 41a waits until the number of times the voltage Vzcd becomes the threshold value Vthl after becoming the threshold value Vthh due to the oscillation of the voltage Vzcd reaches a predetermined number of times.

[0109] However, when the amplitude of the oscillation of the voltage Vzcd is less than |threshold value Vthh - threshold value Vthl|, the voltage Vzcd may not exceed the threshold value Vthh no matter how much time elapses after time t22. In this case, the signal output circuit 41a does not output a signal to turn on the MOS transistor 30 no matter how much time elapses after time t22. Also, after time t22, the comparison circuit 40 continues to output a signal at the "H" level.

[0110] Therefore, the restart timer 42 measures the period from when the comparator circuit 40 starts to output the "H" level signal Vcomp1. If the comparator circuit 40 continues to output the "H" level signal Vcomp1 for the period Trst, the restart timer 42 outputs a signal to turn on the MOS transistor 30.

[0111] That is, at time t23, when the period Trst has elapsed since time t22, the restart timer 42 outputs a signal to turn on the MOS transistor 30. As a result, the MOS transistor 30 is turned on at time t23.

[0112] After time t23, the operation from time t21 to time t23 is repeated. Note that, since the load 12 is in a light load state, as in Fig. 5, the period from time t21 to time t22 (the period from when the MOS transistor 30 is turned on until the MOS transistor 30 is turned off and the inductor current IL becomes 0) is shown to be shorter than the period Ta.

[0113] ===Effect of restart timer 42 operation on input current Iin=== When the load 12 is in a light load state, the signal output circuit 41a operates in the bottom skip mode. With reference to Fig. 7, the influence of the operation of the restart timer 42 on the input current Iin when the load 12 is in a light load state will be described.

[0114] In the AC-DC converter 10a, when the phase angle between the AC voltage Vac and the input current Iin is high, the instantaneous value of the AC voltage Vac becomes large, thereby reducing the boost ratio of the boost chopper circuit. Therefore, in the range where the phase angle between the AC voltage Vac and the input current Iin is high, the amplitude of the voltage Vzcd after the inductor current IL flowing through the main coil L1 becomes zero becomes small.

[0115] When the amplitude of the oscillation of the voltage Vzcd is lower than |threshold value Vthh - threshold value Vthl|, after the inductor current IL becomes 0, no matter how much time elapses, the voltage Vzcd will not exceed the threshold value Vthh. Therefore, due to the operation of the restart timer 42 described in FIG. 6, the MOS transistor 30 is turned on.

[0116] In this case, since the period Trst is long as a standby period, the OFF period of the MOS transistor 30 becomes long. Therefore, when the load 12 is in a light load state, as shown in FIG. 7, in the range where the AC voltage Vac input current Iin is at a high phase angle, the input current Iin is distorted from a sine wave. As a result, in the AC-DC converter 10a, the power factor may deteriorate.

[0117] <<Embodiment>> ==Configuration of AC-DC Converter 10b== FIG. 8 shows an example of the configuration of the AC-DC converter 10b in the embodiment. In FIG. 8, the configurations with the same reference numerals as those in the AC-DC converter 10a in FIG. 1 correspond to the same configurations.

[0118] The AC-DC converter 10b includes a choke coil 21, capacitors 22, 24, 28, 36, 37, a full-wave rectifier circuit 23, a transformer 25, resistors 26, 31 to 35, diodes 27, 38, 39, a power factor correction IC 29a, and a MOS transistor 30. That is, the AC-DC converter 10b is different from the AC-DC converter 10a in that it includes a power factor correction IC 29b instead of the power factor correction IC 29a and further includes diodes 38, 39.

[0119] The power factor correction IC 29b has terminals CS, COMP, FB, RT, OUT, VH, ZCD. That is, the power factor correction IC 29b has a terminal VH in addition to the terminals of the power factor correction IC 29a. Note that the power factor correction IC 29b has other terminals (for example, a power supply terminal, a GND terminal, etc.) similar to the power factor correction IC 29a, but other terminals in the figure are omitted.

[0120] Diodes 38 and 39 apply a voltage Vh corresponding to the AC voltage Vac to the terminal VH of the power factor improvement IC 29b. Diodes 38 and 39 constitute a full-wave rectifier circuit in front of the full-wave rectifier circuit 23. Since diodes 38 and 39 are provided in front of the full-wave rectifier circuit 23, the voltage Vh is not affected by the capacitor 24. As a result, it becomes possible to accurately detect the phase angle of the voltage Vh.

[0121] In this embodiment, the AC-DC converter 10b corresponds to a "power supply circuit". Also, the main coil L1 corresponds to a "first inductor", and the auxiliary coil L2 corresponds to a "second inductor". Also, the MOS transistor 30 corresponds to a "transistor".

[0122] The terminal VH corresponds to a "first terminal", and the voltage Vh applied to the terminal VH corresponds to a "second voltage". Also, the terminal ZCD corresponds to a "second terminal". Also, the voltage Vzcd applied to the terminal ZCD corresponds to a "first voltage".

[0123] ==Configuration of the power factor improvement IC 29b== FIG. 9 shows an example of the configuration of the power factor improvement IC 29b in the embodiment. In FIG. 9, the configurations with the same reference numerals as those in the power factor improvement IC 29b in FIG. 2 correspond to the same configurations.

[0124] The power factor improvement IC 29b includes a comparison circuit 40, a signal output circuit 41b, a restart timer 42, a drive circuit 43, an oscillation circuit 44, an error amplification circuit 45, comparison circuits 46 to 48, a voltage division circuit 80, a comparison circuit 81, and a control circuit 82. The power factor improvement IC 29b is different from the power factor improvement IC 29a in that it includes a signal output circuit 41b instead of the signal output circuit 41a, and further includes a voltage division circuit 80, a comparison circuit 81, and a control circuit 82.

[0125] ===Voltage division circuit 80 and comparison circuit 81=== The voltage division circuit 80 and the comparison circuit 81 are connected to the terminal VH.

[0126] The voltage dividing circuit 80 divides the voltage Vh applied to the terminal VH, and supplies the voltage Vhdiv to the comparison circuit 81. The voltage dividing circuit 80 includes resistors 91 and 92.

[0127] The comparator circuit 81 compares the voltage Vhdiv with the reference voltage Vref to determine whether the AC voltage Vac has a high phase angle. The comparator circuit 81 outputs a signal Vcomp5 according to the determination result to the control circuit 82.

[0128] The comparator circuit 81 outputs a signal Vcomp5 at an "L" level when the AC voltage Vac is at a high phase angle, and outputs a signal Vcomp5 at an "H" level when the AC voltage Vac is not at a high phase angle.

[0129] ===Outline of the Control Circuit 82 and the Signal Output Circuit 41b=== The control circuit 82 controls the signal output circuit 41b when the AC voltage Vac has a high phase angle. In particular, when the load 12 is in a light load state and the AC voltage Vac has a high phase angle such that the amplitude of the voltage Vzcd is smaller than |voltage Vthh-voltage Vthl|, the control circuit 82 controls the signal output circuit 41b to operate in the critical mode.

[0130] On the other hand, when the amplitude of the voltage Vzcd is larger than |Voltage Vthh-Voltage Vthl|, the control circuit 82 causes the signal output circuit 41b to operate in the critical mode or the bottom skip mode.

[0131] The signal output circuit 41b includes a frequency reduction circuit 50b and an OR circuit 51. Unlike the frequency reduction circuit 50a, the frequency reduction circuit 50b includes an AND circuit 73 to which the signal Vctr output from the control circuit 82 is input. The AND circuit 73 will be described later with reference to FIG.

[0132] Here, the value of 0 (or substantially 0) of the inductor current IL corresponds to the "first predetermined value", and the threshold value Vthl of the comparison circuit 40 at that time corresponds to the "first threshold value". Further, the comparison circuit 40 corresponds to the "first detection circuit" that detects that the inductor current has become 0.

[0133] Also, regarding the amplitude of the voltage Vzcd, |threshold value Vthh - threshold value Vthl| corresponds to the "second predetermined value". Together with the threshold value Vthl, the threshold value Vthh that determines |threshold value Vthh - threshold value Vthl| corresponds to the "second threshold value".

[0134] Also, the critical mode corresponds to the "first mode", and the bottom skip mode corresponds to the "second mode". The period Tbs during which the signal output circuit 41b waits in the bottom skip mode corresponds to the "first period".

[0135] The restart timer 42 corresponds to the "second timing circuit", and the period Trst measured by the restart timer 42 corresponds to the "third period".

[0136] The comparison circuit 81 corresponds to the "second detection circuit", and the fact that the AC voltage Vac is in the high phase angle range corresponds to the fact that the AC voltage Vac is within the "predetermined range".

[0137] ==Details of the frequency reduction circuit 50b and the control circuit 82== FIG. 10 shows an example of the configuration of the frequency reduction circuit 50b and the control circuit 82. In the frequency reduction circuit 50b of FIG. 10, the configurations with the same reference numerals as those in the frequency reduction circuit 50a of FIG. 3 correspond to the same configurations.

[0138] ===Control circuit 82=== The control circuit 82 operates on the assumption that the AC voltage Vac is at a high phase angle when the comparison circuit 81 in FIG. 9 outputs a signal Vcomp5 at the "L" level. The control circuit 82 outputs a signal Vctr according to the determination result of the amplitude of the oscillation of the voltage Vzcd and controls the operation of the frequency reduction circuit 50b. The control circuit 82 includes an amplitude determination circuit 63, an RS flip-flop 64, and an inverter 65.

[0139] ====Amplitude determination circuit 63==== Based on the signal Vcomp1, the amplitude determination circuit 63 determines whether the amplitude of the oscillation of the voltage Vzcd after the inductor current IL flowing through the main coil L1 becomes 0 is greater than |threshold value Vthh - threshold value Vthl|. If the amplitude is greater than |threshold value Vthh - threshold value Vthl|, it outputs a signal of "L" level, and if the amplitude is less than |threshold value Vthh - threshold value Vthl|, it outputs a signal of "H" level.

[0140] The amplitude determination circuit 63 includes an inverter 75, a delay circuit 76, a timing circuit 77, and a D flip - flop 78. The amplitude determination circuit 63 determines whether the amplitude of the voltage Vzcd is greater than |threshold value Vthh - threshold value Vthl| based on the signal Vcomp1 output by the comparison circuit 40 in FIG. 9.

[0141] After the MOS transistor 30 turns off and the inductor current IL becomes 0, the voltage Vzcd drops below the threshold value Vthl, and the comparison circuit 40 outputs a signal Vcomp1 of "H" level. After that, due to the oscillation of the voltage Vzcd, as described in FIGS. 5 and 6, when the voltage Vzcd exceeds the threshold value Vthh, the comparison circuit 40 outputs a signal Vcomp1 of "L" level. Also, when the voltage Vzcd drops below the threshold value Vthl again after the voltage Vzcd exceeds the threshold value Vthh, the comparison circuit 40 outputs a signal Vcomp1 of "H" level.

[0142] The inverter 75 inverts the level of the signal Vcomp1. That is, it inverts the "H" - level signal Vcomp1 output when the voltage Vzcd drops below the threshold value Vthl to the "L" level. Also, the inverter 75 inverts the "L" - level signal Vcomp1 output when the voltage Vzcd exceeds the threshold value Vthh to the "H" level.

[0143] The delay circuit 76 delays the signal output from the inverter 75. As a result, the signal input to the timing circuit 77 is delayed, and the signal that the timing circuit 77 outputs to the CLK input of the D flip - flop 78 is also delayed.

[0144] After the inductor current IL becomes 0, the timer circuit 77 measures the period during which the level of the voltage Vzcd is smaller than the threshold value Vthh. Specifically, when the delay circuit 76 outputs a signal based on the "L" level from the inverter 75, the timer circuit 77 starts timing and outputs a "H" level signal Vtimer. Thereafter, the timer circuit 77 measures a period Tb, and when the time-counting of the period Tb ends, the timer circuit 77 changes the signal Vtimer to the "L" level.

[0145] Here, the period Tb is set to a period shorter than the period Trst (for example, 10 to 20 μs) measured by the restart timer 42.

[0146] As described above, in the bottom skip mode, the signal output circuit 41b waits until the number of times that the voltage Vzcd reaches the threshold Vthl after reaching the threshold Vthh reaches a predetermined number of times.

[0147] The period Tb is set to be longer than (predetermined number of times) x (typical period of oscillation) with respect to the typical period of oscillation of the voltage Vzcd. For example, if the preset number is 1 and the typical period is 2 μs, the period Tb may be set to 1.5 periods (3 μs) or 2 periods (4 μs).

[0148] At the timing when the signal output to the CK input by the timer circuit 77 changes to the "L" level, the D flip-flop 78 outputs from its Q output a signal Vd that corresponds to the level of the signal Vcomp1 output to its D input from the comparator circuit 40. Therefore, based on the level of the signal Vd that the D flip-flop 78 outputs from its Q output, it can be determined whether the period during which the amplitude of the voltage Vzcd is smaller than |threshold value Vthh-threshold value Vthl| is longer than the period Tb.

[0149] If the signal Vd output from the Q output of the D flip-flop 78 is at the "H" level, the period during which the "H" level signal Vcomp1 is output will be longer than the period Tb. This means that the period during which the amplitude of the voltage Vzcd is smaller than |threshold Vthh - threshold Vthl| is longer than the period Tb.

[0150] Therefore, if the signal Vd output from the D flip-flop 78 is at the "H" level, it can be determined that the amplitude of the oscillation of the voltage Vzcd is smaller than |threshold Vthh - threshold Vthl|. On the other hand, if the signal Vd is at the "H" level, it can be determined that the amplitude of the oscillation of the voltage Vzcd is larger than |threshold Vthh - threshold Vthl|.

[0151] Note that due to the provision of the delay circuit 76, the timing circuit 77 measures the period Tb from a timing slightly later than the timing when the inductor current becomes 0 and the signal Vcomp1 changes to the "H" level. Therefore, even when the rising edge of the signal Vcomp1 is input to the D input exactly at the timing when the period Tb has elapsed from the timing when the signal Vcomp1 changed to the "H" level, the "L" level signal Vd is output.

[0152] That is, at the timing when the period Tb has elapsed from the timing when the inductor current became 0, the level of the signal Vcomp1 input to the D input will be surely reflected in the signal Vd.

[0153] Also, depending on the level of the signal Vcomp5 output by the comparison circuit 81 with respect to the R input of the D flip-flop 78, the D flip-flop 78 operates when the AC voltage Vac is at the high phase angle.

[0154] Specifically, with respect to the R input of the D flip-flop 78, when the AC voltage Vac is at the high phase angle, the comparison circuit 81 outputs the "L" level signal Vcomp5. In this case, the D flip-flop 78 reflects the level of the D input in the Q output at the timing when the level of the CK input changes.

[0155] ===RS Flip-Flop 64 and Inverter 65=== Here, return to the description of the configuration of the control circuit 82. The RS flip-flop 64 holds the determination result of the amplitude determination circuit 63 when the amplitude determination circuit 63 determines that the amplitude of the oscillation of the voltage Vzcd is smaller than |threshold value Vthh - threshold value Vthl|.

[0156] The RS flip-flop 64 latches the "H" level signal Vd output from the amplitude determination circuit 63. Once it is determined that the amplitude of the voltage Vzcd is smaller than |threshold value Vthh - threshold value Vthl|, the RS flip-flop 64 continues to output a "H" level signal from the Q output until a "H" level signal Vcomp5 is input to the R input.

[0157] As a result, when the input voltage Vac approaches the high phase angle and in the boundary region where the amplitude of the oscillation of the voltage Vzcd exceeds or does not exceed |threshold value Vthh - threshold value Vthl|, once the operation of the signal output circuit 41b is switched to the critical mode, it will continue to operate in the critical mode. That is, in the boundary region where the amplitude of the oscillation of the voltage Vzcd exceeds or does not exceed |threshold value Vthh - threshold value Vthl|, it is possible to prevent frequent switching between the bottom skip mode and the critical mode.

[0158] In addition, when the AC voltage Vac is not at the high phase angle, or when a "H" level signal Vcomp5 is output from the comparison circuit 81 to the R input of the RS flip-flop 64, a "L" level signal is output from the Q output of the RS flip-flop 64.

[0159] The inverter 65 inverts the level of the signal output from the Q output of the RS flip-flop 64. That is, when the AC voltage Vac is at the high phase angle and the amplitude determination circuit 63 determines that the amplitude of the oscillation of the voltage Vzcd is smaller than |threshold value Vthh - threshold value Vthl|, a "L" level signal Vctr is output from the inverter 65.

[0160] As a result, once a signal of "L" level is output from the inverter 65 of the control circuit 82, the control circuit 82 will continue to output a signal Vctr of "L" level. When a signal Vcomp5 of "H" level is output from the comparison circuit 81 to the R input of the RS flip-flop 64, its state is released, and the magnitude of the amplitude of the oscillation of the voltage Vzcd is determined.

[0161] Also, when the AC voltage Vac is at a high phase angle and the amplitude determination circuit 63 determines that the amplitude of the oscillation of the voltage Vzcd is greater than |threshold value Vthh - threshold value Vthl|, a signal Vctr of "H" level is output from the inverter 65. On the other hand, when it is determined that the AC voltage Vac is not at a high phase angle, a signal Vctr of "L" level is output.

[0162] ===Frequency reduction circuit 50b=== The frequency reduction circuit 50b includes a load state determination circuit 60 and a drive signal output circuit 62. The frequency reduction circuit 50b is different from the frequency reduction circuit 50a in that it includes a drive signal output circuit 62 instead of the output circuit 61 of the frequency reduction circuit 50a.

[0163] Also, the drive signal output circuit 62 includes an AND circuit 73 and an output circuit 74. Here, the output circuit 74 is the same circuit as the output circuit 61 in the frequency reduction circuit 50a. As a result, the frequency reduction circuit 50b is different from the frequency reduction circuit 50a in that it includes an AND circuit 73 in front of the output circuit 74.

[0164] The AND circuit 73 outputs a signal for operating the output circuit 74 in the bottom skip mode when it is shown that the load 12 is in a light load state and the amplitude of the voltage Vzcd after the inductor current IL becomes 0 is greater than |threshold value Vthh - threshold value Vthl|.

[0165] That is, the AND circuit 73 calculates the logical product of the signal Vb from the D flip-flop 72 and the signal Vctr from the control circuit 82. Therefore, when both the signal Vb from the D flip-flop 72 of the load state determination circuit 60 and the signal Vctr from the control circuit 82 are at the "H" level, the AND circuit 73 outputs a signal at the "H" level to the output circuit 74. When either of the input signal levels is at the "L" level, the AND circuit 73 outputs a signal at the "L" level to the output circuit 74.

[0166] When the output of the AND circuit 73 is at the "H" level, the output circuit 74 outputs a signal for turning on the MOS transistor 30 in the bottom skip mode. On the other hand, when the output of the AND circuit 73 is at the "L" level, the output circuit 74 outputs a signal for turning on the MOS transistor 30 in the critical mode.

[0167] While the output circuit 74 is operating in the bottom skip mode, when the output of the AND circuit 73 changes to the "L" level, the output circuit 74 outputs a signal for turning on the MOS transistor 30. Thereby, when the signal Vctr from the control circuit 82 changes from the "H" level to the "L" level, the MOS transistor 30 is immediately turned on.

[0168] Here, the amplitude determination circuit 63 corresponds to the "first determination circuit", and the determination result by the amplitude determination circuit 63 as to whether the voltage Vzcd is greater than |threshold value Vthh - threshold value Vthl| and the corresponding level of the signal Vd correspond to the "first determination result".

[0169] The timing circuit 77 corresponds to the "first timing circuit", the D flip-flop 78 corresponds to the "first output circuit". Also, the period Tb during which the timing circuit 77 times corresponds to the "second period". Furthermore, the RS flip-flop 64 corresponds to the "holding circuit".

[0170] Also, the load state determination circuit 60 corresponds to the "second determination circuit", and the determination result as to whether the state of the load 12 is a light load state and the corresponding level of the signal Vb correspond to the "second determination result".

[0171] Also, the drive signal output circuit 62 corresponds to the "second output circuit".

[0172] ===Main waveform diagram of the power factor improvement IC29b=== FIG. 11 is a diagram showing the main waveforms in the operation of the power factor improvement IC29b. The operations of the circuits in FIGS. 8 to 10 will be described with reference to the waveforms.

[0173] In the figure, waveforms from the time when the load 12 is in the light load state and Vcomp5 is at the "H" level are shown. Also, waveforms when the comparison circuit 81 determines that the AC voltage Vac is at the higher phase angle (Vcomp5 is at the "L" level) are shown.

[0174] Note that waveforms from the point in time when the amplitude of the oscillation of the voltage Vzcd after the inductor current IL becomes 0 is greater than |threshold value Vthh - threshold value Vthl| are shown. Therefore, at the first point in time shown in the figure, the amplitude determination circuit 63 outputs a signal Vd at the "L" level, and the control circuit 82 outputs a signal Vctr at the "H" level.

[0175] Furthermore, in the figure, for the sake of convenience of display, there are places where the timing of the change in the level of the signal Vtimer output by the timing circuit 77 is drawn in the same way as the timing of the change in the level of the signal Vcomp1. However, in the control circuit 82 of the present embodiment, since the delay circuit 76 is provided, the timing at which the level of the signal Vtimer changes is actually slightly delayed with respect to the timing at which the level of the signal Vcomp1 changes.

[0176] At time t31, since the load 12 is in the light load state, the load state determination circuit 60 outputs a signal Vb at the "H" level. When the drive circuit 43 turns on the MOS transistor 30, the voltage Vzcd applied to the terminal ZCD also decreases.

[0177] Thereafter, the MOS transistor 30 is turned off, and at time t32, the comparator circuit 40 determines that the voltage Vzcd has fallen below the threshold Vthl. In response to the low-level signal Vd, the signal output circuit 41b operates in bottom-skip mode. At time t33, the signal output circuit 41b outputs a signal Von that turns on the MOS transistor 30. Therefore, during the period from time t31 to time t33, the same operations as those performed during the period from time t11 to time t14 in FIG. 5 are performed.

[0178] At time t33, the drive circuit 43 turns on the MOS transistor 30. The operation from time t33 to time t34 when the voltage Vzcd falls below the threshold Vthl after the MOS transistor 30 is turned off is the same as the operation from time t31 to time t32.

[0179] At time t34, the comparator circuit 40 determines that the voltage Vzcd has fallen below the threshold voltage Vthl, thereby detecting that the inductor current IL flowing through the main coil L1 has become zero.

[0180] The comparator circuit 40 changes the level of the signal Vcomp1 it outputs to the "H" level, and the timer circuit 77 changes the level of the signal Vtimer to the "H" level.

[0181] In the figure, the change in amplitude of the oscillation of the voltage Vzcd after the inductor current IL falls below 0 is exaggerated for convenience. In the oscillation after time t34, the amplitude of the voltage Vzcd becomes smaller than |threshold Vthh−threshold Vthl|. Therefore, the comparator circuit 40 continues to output the “H” level signal Vcomp1.

[0182] At time t35, a period Tb has elapsed since the comparator circuit 40 started to output the "H" level signal Vcomp1 at time t34, and the timer circuit 77 changes the level of the signal Vtimer to the "L" level.

[0183] Since the signal Vcomp5 at the D input of the D flip-flop 78 is at the “H” level, the amplitude determination circuit 63 determines that the amplitude of the voltage Vzcd is smaller than |threshold Vthh−threshold Vthl|, and changes the level of the signal Vd that it outputs to the “H” level.

[0184] Furthermore, the RS flip-flop 64 latches the level of the Q output at the “H” level as long as the signal Vcomp5 is at the “L” level. Furthermore, the control circuit 82 changes the level of the signal Vctr that it outputs to the “L” level.

[0185] The drive signal output circuit 62 operates in the critical mode because the "L" level signal Vctr is input to the AND circuit 73. Accordingly, the drive signal output circuit 62 outputs a signal that turns on the MOS transistor 30.

[0186] The operation from time t35 until time t36, when the voltage Vzcd falls below the threshold Vthl after the drive circuit 43 turns off the MOS transistor 30, is the same as the operation from time t33 to time t34.

[0187] At time t36, the inductor current IL becomes 0, and the voltage Vzcd falls below the threshold Vthl. Because the control circuit 82 outputs the signal Vctr at the "L" level, the signal output circuit 41b outputs the signal Von that turns on the MOS transistor 30 in the critical mode. Therefore, from time t36, the drive circuit 43 turns on the MOS transistor 30.

[0188] At time t37, after the signal output circuit 41b has continued to operate in the critical mode for a certain period of time, the comparator circuit 81 determines that the AC voltage Vac is no longer at a high phase angle, causing the comparator circuit 81 to change the level of the signal Vcomp5 to the “H” level.

[0189] Therefore, the D flip-flop 78 and the RS flip-flop 64 change the level of the signal Vd output from the Q output to the "L" level. As a result, the control circuit 82 outputs a signal Vctr of the "H" level.

[0190] Also at time t37, the load 12 is a light load, and the load state determination circuit 60 outputs a signal Vb of the "H" level. Therefore, after time t37, the signal output circuit 41 operates in the bottom skip mode in the same manner as from time t31 to time t33.

[0191] ==Waveform of the input current Iin in the AC-DC converter 10b== FIG. 12 shows an example of the waveform of the input current Iin of the AC-DC converter 10b. Similar to FIG. 7, an example of the waveform in the AC-DC converter 10b when the signal output circuit 41b operates in the bottom skip mode when the load 12 is in a light load state is shown.

[0192] In the present embodiment, when the amplitude of the oscillation of the voltage Vzcd after the inductor current IL flowing through the main coil L1 indicates 0 is less than |threshold value Vthh - threshold value Vthl|, the control circuit 82 operates the signal output circuit 41b in the critical mode.

[0193] As a result, in the AC-DC converter 10b, even when the input voltage Vac and the input current Iin have a high phase angle, the startup of the MOS transistor 30 after the inductor current IL becomes 0 is accelerated. Therefore, the distortion of the waveform in the input current Iin is eliminated, and the waveform becomes sinusoidal. As a result, the power factor in the power of the AC-DC converter 10b is improved.

[0194] ==Summary== As described above, the AC-DC converter 10b and the power factor improvement IC 29b of the present embodiment have been described.

[0195] The power factor correction IC 29b includes a main coil L1 to which a rectified voltage Vrec corresponding to an AC voltage Vac is applied, and a MOS transistor 30 that controls an inductor current IL flowing through the main coil L1. The power factor correction IC 29b controls the switching of the MOS transistor 30 in an AC-DC converter 10b that generates an output voltage Vout at a target level from the AC voltage Vac. The power factor correction IC 29b includes a comparator circuit 40, a signal output circuit 41b that operates in a critical mode or a bottom-skip mode, a control circuit 82 that operates the signal output circuit 41b in the critical mode when the amplitude of a voltage Vzcd after the inductor current IL becomes zero is smaller than |Voltage Vthh-Voltage Vthl|, and operates the signal output circuit 41b in the critical mode or the bottom-skip mode when the amplitude is greater than |Voltage Vthh-Voltage Vthl|, and a drive circuit 43. When the amplitude is larger than |Voltage Vthh-Voltage Vthl|, signal output circuit 41b operates in either the critical mode or the bottom skip mode, depending on the state of load 12 of AC-DC converter 10b.

[0196] This makes it possible to provide a power factor correction IC 29b that does not deteriorate the power factor even when the AC voltage Vac and the input current Iin have a high phase angle when the load 12 is in a light load state. In particular, when the signal output circuit 41b operates in bottom skip mode, the power factor correction IC 29b can turn on and off the MOS transistor 30 at appropriate timing even if the amplitude of the voltage Vzcd after the inductor current IL becomes zero is smaller than |voltage Vthh−voltage Vthl|.

[0197] The control circuit 82 also includes an amplitude determination circuit 63 that determines whether the amplitude of the voltage Vzcd is greater than |Voltage Vthh−Voltage Vthl|, and an RS flip-flop 64 that holds the determination result of the amplitude determination circuit 63.

[0198] This prevents frequent switching between the bottom skip mode and the critical mode in the boundary region where the amplitude of the oscillation of the voltage Vzcd exceeds |threshold Vthh-threshold Vthl|, thereby stabilizing the operation of the power factor correction IC 29b.

[0199] Further, the power factor improvement IC 29b includes a terminal VH to which a voltage Vh corresponding to the AC voltage Vac is applied, and a comparison circuit 81 that detects whether or not the phase angle of the AC voltage Vac is within a range indicating a high phase angle based on the voltage Vh. The RS flip-flop 64 holds the determination result of the amplitude determination circuit 63 when a determination result indicating that the amplitude is smaller than |voltage Vthh - voltage Vthl| is output from the amplitude determination circuit 63 when the phase angle of the AC voltage Vac is within a range indicating a high phase angle.

[0200] As a result, when it is determined that the amplitude of the voltage Vzcd exceeds |threshold value Vthh - threshold value Vthl|, the phase angle of the AC voltage Vac becomes a low phase angle, and the determination result is held until it is determined that the amplitude of the voltage Vzcd is larger than |voltage Vthh - voltage Vthl|. Therefore, the operation of the power factor improvement IC 29b is stabilized.

[0201] The comparison circuit 40 is a hysteresis comparator that compares the voltage Vzcd with each of a threshold value Vthl indicating 0 and a threshold value Vthh that defines |voltage Vthh - voltage Vthl| together with the threshold value Vthl. The amplitude determination circuit 63 includes a timing circuit 77 that measures the period during which the amplitude of the voltage Vzcd is smaller than |voltage Vthh - voltage Vthl| after the inductor current IL becomes 0, and a D flip-flop 78 that outputs a determination result indicating that the amplitude of the voltage Vzcd is smaller than |voltage Vthh - voltage Vthl| when the period during which the amplitude of the voltage Vzcd is smaller than |voltage Vthh - voltage Vthl| becomes a period Tb.

[0202] As a result, the amplitude determination circuit 63 can determine that the period during which the amplitude of the voltage Vzcd is smaller than |voltage Vthh - voltage Vthl| exceeds the period Tb. Based on the period Tb, the signal output circuit 41b can switch from the bottom skip mode to the critical mode. Therefore, the power factor improvement IC 29b can turn on and off the MOS transistor 30 at an appropriate timing even when the load 12 is in a light load state and the AC voltage Vac and the input current Iin are at a high phase angle.

[0203] Further, the power factor improvement IC 29b includes a restart timer 42 that measures the period after the inductor current IL becomes zero, and the signal output circuit 41b outputs a signal to turn on the MOS transistor 30 when the restart timer 42 measures a period Trst longer than the period Tb.

[0204] Thus, the period Tb is shorter than the period Trst. Therefore, in the power factor improvement IC 29b, when the load 12 is in a light load state and the AC voltage Vac and the input current Iin are in a leading phase angle, the MOS transistor 30 can be turned on and off at a timing earlier than the restart timer 42.

[0205] Also, the signal output circuit 41b includes a load state determination circuit 60 that determines whether the state of the load 12 is a light load state based on the period from when the MOS transistor 30 is turned on until the inductor current IL becomes zero, and a drive signal output circuit 62 that outputs a signal corresponding to the bottom skip mode when the load state determination circuit 60 outputs a determination result indicating that the state of the load 12 is a light load state when the amplitude is greater than |voltage Vthh - voltage Vthl|, outputs a signal corresponding to the critical mode when the load state determination circuit 60 outputs a determination result indicating that the state of the load 12 is not a light load state, and outputs a signal corresponding to the critical mode when the amplitude is less than |voltage Vthh - voltage Vthl|.

[0206] Thereby, the signal output circuit 41b can execute switching not only between the critical mode and the bottom skip mode according to the load state, but also mode switching according to the amplitude of the voltage Vzcd. Therefore, the power factor improvement IC 29b can turn on and off the MOS transistor 30 at an appropriate timing.

[0207] Further, the power factor improvement IC 29b includes a terminal ZCD to which the voltage Vzcd from the auxiliary coil L2 magnetically coupled to the main coil L1 is applied, and the voltage detected by the comparison circuit 40 is the voltage Vzcd applied to the terminal ZCD.

[0208] Accordingly, based on the voltage Vzcd from the auxiliary coil L2, the change in the inductor current IL can be detected with high sensitivity. Therefore, the power factor improvement IC29b can turn on and off the MOS transistor 30 at an appropriate timing.

[0209] An AC-DC converter 10b is provided that generates an output voltage Vout at a target level from an AC voltage Vac. The AC-DC converter 10b includes a main coil L1 to which a rectified voltage Vrec corresponding to the AC voltage Vac is applied, a MOS transistor 30 that controls the inductor current IL flowing through the main coil L1, and a power factor improvement IC29b that controls the switching of the MOS transistor 30. The power factor improvement IC29b includes a comparison circuit 40, a signal output circuit 41b that operates in a critical mode or a bottom skip mode, and a control circuit 82 that operates the signal output circuit 41b in the critical mode when the amplitude of the voltage Vzcd after the inductor current IL becomes 0 is smaller than |voltage Vthh - voltage Vthl|, and operates the signal output circuit 41b in the critical mode or the bottom skip mode when the amplitude is larger than |voltage Vthh - voltage Vthl|, and a drive circuit 43. When the amplitude is larger than |voltage Vthh - voltage Vthl|, the signal output circuit 41b operates in a mode corresponding to the state of the load 12 of the AC-DC converter 10b among the critical mode and the bottom skip mode.

[0210] Accordingly, an AC-DC converter 10b is provided that includes a power factor improvement IC29b that does not deteriorate the power factor even when the load 12 is in a light load state and the AC voltage Vac and the input current Iin are in a high phase angle. Therefore, the power factor of the power provided from the AC-DC converter 10b is improved.

[0211] As described above, the present invention has been described using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the technical scope of the present invention can include forms and equivalents thereof to which such changes or improvements are added without departing from the spirit thereof.

[0212] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0213] 10 AC-DC converter 11 AC power supply 12 Load 21 Choke coil 22,24 Capacitor 23 Full wave rectifier circuit 25 Transformer 26 Resistance 27 Diode 28 Capacitor 29 Power Factor Correction IC 30 MOS transistors 31~35 Resistance 36,37 Capacitor 38,39 Diodes 40,46~48 Comparison circuit 41 Signal output circuit 42 Restart timer 43 Drive circuit 44 Oscillator Circuit 45 Error amplifier circuit 50 Frequency reduction circuit 51,52 OR circuit 53 RS Flip-Flop 54 Buffer circuit 60 Load condition determination circuit 61 Output circuit 62 Drive signal output circuit 63 Amplitude judgment circuit 64 RS flip-flops 65 Inverter 70 Timing Detection Circuit 71 Timing Circuit 72,78 D Flip-Flop 73 AND Circuit 74 Output Circuit 75 Inverter 76 Delay Circuit 77 Timing Circuit 80 Voltage Divider Circuit 81 Comparison Circuit 82 Control Circuit 91,92 Resistor

Claims

1. An integrated circuit for controlling the switching of a transistor in a power supply circuit that includes a first inductor to which a rectified voltage corresponding to an AC voltage is applied and a transistor that controls an inductor current flowing through the first inductor, and generates an output voltage at a target level from the AC voltage, comprising: a first detection circuit that detects whether or not the inductor current has reached a first predetermined value based on a first voltage corresponding to the inductor current; a signal output circuit that operates in a first mode that outputs a signal to turn on the transistor when the inductor current reaches the first predetermined value, or in a second mode that outputs the signal when the inductor current reaches the first predetermined value and a first period has elapsed; a control circuit that operates the signal output circuit in the first mode when an amplitude of the first voltage after the inductor current has reached the first predetermined value is smaller than a second predetermined value, and operates the signal output circuit in the first mode or the second mode when the amplitude is larger than the second predetermined value; a drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; wherein: the signal output circuit: when the amplitude is larger than the second predetermined value, operates in a mode corresponding to a state of a load of the power supply circuit among the first mode and the second mode; Integrated circuit.

2. The integrated circuit according to claim 1, wherein: the control circuit: a first determination circuit that determines whether or not the amplitude is larger than the second predetermined value; a holding circuit that holds a first determination result of the first determination circuit; wherein: Integrated circuit.

3. The integrated circuit according to claim 2, wherein: a first terminal to which a second voltage corresponding to the AC voltage is applied; a second detection circuit that detects whether or not a phase of the AC voltage is within a predetermined range based on the second voltage; wherein: the holding circuit: when the phase of the AC voltage is within the predetermined range, holds the first determination result when the first determination result indicating that the amplitude is smaller than the second predetermined value is output from the first determination circuit; Integrated circuit.

4. The integrated circuit according to claim 2 or 3, wherein: the first detection circuit: is a comparison circuit that compares the first voltage with each of a first threshold indicating the first predetermined value and a second threshold that defines the second predetermined value together with the first threshold; the first determination circuit: a first timer circuit configured to measure a period during which the amplitude is smaller than the second predetermined value after the inductor current reaches the first predetermined value; a first output circuit that outputs the first determination result indicating that the amplitude is smaller than the second predetermined value when the period during which the amplitude is smaller than the second predetermined value becomes a second period; Including, Integrated circuit.

5. 5. An integrated circuit according to claim 4, a second timer circuit configured to measure a period of time after the inductor current reaches the first predetermined value; the signal output circuit outputs the signal when the second timing circuit times a third period longer than the second period. Integrated circuit.

6. An integrated circuit according to any one of claims 1 to 5, The signal output circuit a second determination circuit that determines whether the load state is a light load or not based on a period of time from when the transistor is turned on until when the inductor current reaches the first predetermined value; a second output circuit that outputs the signal corresponding to the second mode when the second determination circuit outputs a second determination result indicating that the load state is a light load if the amplitude is greater than the second predetermined value, outputs the signal corresponding to the first mode when the second determination circuit outputs the second determination result indicating that the load state is not a light load, and outputs the signal corresponding to the first mode when the amplitude is smaller than the second predetermined value; Including, Integrated circuit.

7. An integrated circuit according to any one of claims 1 to 6, a second terminal to which a voltage is applied from a second inductor magnetically coupled to the first inductor; the first voltage is a voltage applied to the second terminal; Integrated circuit.

8. A power supply circuit that generates an output voltage of a target level from an AC voltage, a first inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor for controlling an inductor current flowing through the first inductor; an integrated circuit that controls the switching of the transistor; Equipped with The integrated circuit comprises: a first detection circuit that detects whether the inductor current has reached a first predetermined value based on a first voltage corresponding to the inductor current; a signal output circuit that operates in a first mode to output a signal to turn on the transistor when the inductor current reaches the first predetermined value, or in a second mode to output the signal when the inductor current reaches the first predetermined value and a first period has elapsed; A control circuit that operates the signal output circuit in the first mode when the amplitude of the first voltage after the inductor current reaches the first predetermined value is smaller than a second predetermined value, and operates the signal output circuit in the first mode or the second mode when the amplitude is greater than the second predetermined value; A drive circuit that turns on the transistor based on the signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; comprising; The signal output circuit; When the amplitude is greater than the second predetermined value, it operates in a mode corresponding to the state of the load of the power supply circuit among the first mode and the second mode; Power supply circuit.

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