Liquid crystal display device and method for manufacturing the same

Abstract

To provide a liquid crystal display device and manufacturing method of the liquid crystal display device that can improve reliability.SOLUTION: A liquid crystal display device 1 comprises: a shift register unit 161 that sequentially takes in a video signal of a s-bit width by the number of rows of a plurality of pixels 12; a one-line latch unit 162 that concurrently outputs a plurality of video signals taken in by the shift register unit 161; a comparator part 163 that converts the plurality of video signals output from the one-line latch part 162 to a plurality of analog voltages, respectively; an analog switch part 17 that switches whether the plurality of analog voltages is supplied to a plurality of data lines, respectively. The one-line latch part 162 is arranged in the vicinity of the comparator part 163 so that, among a plurality of bit signals consisting of the video signal, a length of a signal line where the bit signal of a least significant bit propagates is shorter than the signal line where bit signal of at least the most significant bit propagates.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly to a liquid crystal display device and a method for manufacturing the same that are suitable for improving reliability, for example.

Background Art

[0002] The implementation and popularization of the ultra-high-speed fifth-generation communication technology "5G" are underway. To realize 5G, in the field of optical communication, optical communication systems such as an annular optical network system and an optical wavelength division multiplexing communication system that can cope with the rapidly increasing amount of information have been proposed.

[0003] In these optical communication systems, a ROADM (Reconfigurable Optical Add and Drop Multiplexer) device that can branch or insert without converting or relaying an optical signal into an electrical signal is used. As an optical switching device in the ROADM device, a WSS (Wavelength Selective Switch) device is used. As an optical switching element in the WSS device, an LCOS (Liquid Crystal on Silicon; hereinafter referred to as a liquid crystal display device) that utilizes the phase modulation function of liquid crystal is used.

[0004] Techniques related to liquid crystal display devices are disclosed in, for example, Patent Document 1. The liquid crystal display device disclosed in Patent Document 1 includes a plurality of pixels arranged in a matrix, a plurality of data lines provided corresponding to each column of the plurality of pixels, a shift register circuit that sequentially captures a video signal for the number of columns of the plurality of pixels, and a plurality of video signals captured by the shift register circuit that are output all at once. A latching circuit that exerts force, and a plurality of video signals output from the latching circuit are respectively converted into a plurality of analog voltages, a plurality of comparators, and an analog switch unit that switches whether to supply the plurality of analog voltages to a plurality of data lines respectively.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the liquid crystal display device disclosed in Patent Document 1, specific details regarding the wiring of a plurality of signal lines through which each of a plurality of bit signals constituting a video signal having a plurality of bit widths propagates are not disclosed . Therefore, in the signal lines through which the least significant bit signal that frequently changes signals propagates, current leakage from the signal lines to the interlayer insulating film of the wiring may occur, or the wiring resistance may partially increase due to manufacturing defects or the like, resulting in a progressive failure due to long-term continuous use . As a result, the liquid crystal display device disclosed in Patent Document 1 has a problem that the reliability deteriorates . . . .

[0007] The present invention has been made in view of the above points, and an object thereof is to provide a liquid crystal display device and a manufacturing method thereof capable of improving reliability .

Means for Solving the Problems

[0008] The liquid crystal display device according to one aspect of the present embodiment includes a plurality of pixels, and for each column of the plurality of pixels A plurality of data lines provided correspondingly, and a shift register unit that sequentially captures an s-bit width video signal for the number of columns of the plurality of pixels described above, and the plurality of video signals captured by the shift register unit are output all at once by the latch unit, and the plurality of video signals output from the latch unit are respectively converted into a plurality of analog voltages by a plurality of comparators, and an analog switch unit that switches whether or not to supply the plurality of analog voltages to the plurality of data lines respectively. The shift register unit has first to s-th shift register circuits that sequentially capture first to s-th bit signals constituting the s-bit width video signal for the number of columns of the plurality of pixels. The latch unit has first to s-th latch circuits that output all at once the first to s-th bit signals for the number of columns of the plurality of pixels captured by the respective first to s-th shift register circuits. Among the first to s-th latch circuits, the first latch circuit configured to output all at once the plurality of first bit signals that are the least significant bit signals is arranged closer to the plurality of comparators than the s-th latch circuit configured to output all at once the plurality of s-th bit signals that are the most significant bit signals. The first to s-th latch circuits and the plurality of comparators described above are connected by direct wiring. The first to s-th shift register circuits and the first to s-th latch circuits are arranged adjacent to each other corresponding to the first to s-th bit signals. The first to s-th latch circuits for latching each bit signal are respectively arranged between the first to s-th shift register circuits corresponding to each bit signal. The wiring between the first to s-th latch circuits described above and the plurality of comparators is the lowest layer wiring. For the number of columns of the plurality of pixels described above, and a latch unit that outputs all at once the plurality of video signals captured by the shift register unit, and a plurality of comparators that convert the plurality of video signals output from the latch unit into a plurality of analog voltages respectively, and an analog switch unit that switches whether or not to supply the plurality of analog voltages to the plurality of data lines respectively. The shift register unit has first to s-th shift register circuits that sequentially capture first to s-th bit signals constituting the s-bit width video signal for the number of columns of the plurality of pixels. The first to s-th bit signals that constitute the s-bit width video signal are sequentially captured by the first to s-th shift register circuits for the number of columns of the plurality of pixels respectively. The latch unit has first to s-th latch circuits that output all at once the first to s-th bit signals for the number of columns of the plurality of pixels captured by the respective first to s-th shift register circuits. The first to s-th bit signals for the number of columns of the plurality of pixels captured by the respective first to s-th shift register circuits are output all at once by the first to s-th latch circuits respectively. Among the first to s-th latch circuits, the first latch circuit configured to output all at once the plurality of first bit signals that are the least significant bit signals is arranged closer to the plurality of comparators than the s-th latch circuit configured to output all at once the plurality of s-th bit signals that are the most significant bit signals. The first latch circuit is configured to output all at once at least the plurality of s-th bit signals that are the most significant bit signals. The s-th latch circuit is configured to output all at once the plurality of s-th bit signals that are the most significant bit signals. The first to s-th latch circuits and the plurality of comparators described above are connected by direct wiring. The first to s-th shift register circuits and the first to s-th latch circuits are arranged adjacent to each other corresponding to the first to s-th bit signals. The first to s-th shift register circuits and the first to s-th latch circuits are arranged adjacent to each other corresponding to the first to s-th bit signals. The first to s-th latch circuits for latching each bit signal are respectively arranged between the first to s-th shift register circuits corresponding to each bit signal. The first to s-th latch circuits for latching each bit signal are respectively arranged between the first to s-th shift register circuits corresponding to each bit signal. The wiring between the first to s-th latch circuits described above and the plurality of comparators is the lowest layer wiring. .

[0009] A method for manufacturing a liquid crystal display device according to one aspect of the present embodiment includes: A plurality of data lines are provided corresponding to each column of pixels, and an image sensor having a bit width of s (where s is an integer of 2 or more) is provided. a shift register section for sequentially receiving image signals corresponding to the number of columns of the plurality of pixels; a latch unit for simultaneously outputting the plurality of video signals captured by the latch unit; a plurality of converters for converting the plurality of video signals output from the converter into a plurality of analog voltages, respectively; a comparator, and whether or not the plurality of analog voltages are supplied to the plurality of data lines, respectively; and an analog switch unit for switching between the front and rear inputs of the shift register unit. The first to s-th bit signals constituting the video signal are sequentially outputted for the number of columns of the plurality of pixels, respectively. The latch unit includes first to sth shift register circuits for capturing the first to sth shift signals. The first to sth signals corresponding to the number of columns of the plurality of pixels captured by each of the light register circuits are A liquid crystal display device having first to sth latch circuits that simultaneously output bit signals. A manufacturing method, comprising: the first latch circuit configured to simultaneously output a plurality of the first bit signals; , and simultaneously outputting the plurality of s-bit signals, which are at least the most significant bit signals. the s latch circuit configured to the first to s latch circuits are directly connected to the plurality of comparators by wiring, The first to sth shift register circuits and the first to sth latch circuits are The first to second signals are arranged adjacent to each other in correspondence with the s-th bit signal, and correspond to each bit signal. The first to sth latch circuits for latching each bit signal are provided between the sth shift register circuits. The wiring between the first to s latch circuits and the plurality of comparators is This is the lowest layer of wiring. [Effects of the Invention]

[0010] According to the present embodiment, a liquid crystal display device capable of improving reliability and a method for manufacturing the same are provided. can be provided. [Brief explanation of the drawings]

[0011]

Figure 1

Figure 2

Figure 3

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Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0012] <Prior Consideration by the Inventor> Before explaining the liquid crystal display device according to Embodiment 1, the content of the prior consideration by the present inventor will be explained. The content will be explained. (Configuration of the Liquid Crystal Display Device 50 at the Concept Stage) Fig. 1 is a diagram showing a configuration example of an active matrix type liquid crystal display device 50 at the concept stage. As shown in Fig. 1, the liquid crystal display device 50 includes an image display section 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register & level shifter 15, a horizontal driver 56, an analog switch section 17, AND circuits ADA1~ADAn, ADB1~ADBn. The horizontal driver 56, together with the analog switch section 17, constitutes a data line driving circuit, and has a shift register circuit 561, a 1-line latch circuit 562, a comparator section 563, and a gradation counter 564. Note that Fig. 1 also shows a lamp signal generator 2 connected to the liquid crystal display device 50 during normal operation.

[0013] Fig. 2 is a diagram showing in more detail the horizontal driver 56 and the analog switch section 17 provided in the liquid crystal display device 50. The comparator section 563 includes m (m is an integer of 2 or more) comparators 563_1~563_m corresponding to m columns of pixels 12. The analog switch section 17 includes m sets of switch elements SW1+, SW1-~SWm+, SWm- corresponding to m columns of pixels 12. ​​​​​​​​​​

[0014] In the pixel arrangement region of the image display unit 11, there are n scanning lines G1 to Gn (n is an integer of 2 or more) extending in the horizontal direction (X-axis direction) and n read switch selection lines TG1 to TGn, and a set of m data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (Y-axis direction), which are wired. Also, in the pixel arrangement region of the image display unit 11, gate control signal lines S+, S-, and a gate control signal line B are wired.

[0015] The image display unit 11 has a plurality of regularly arranged pixels 12. Here, the plurality of pixels 12 are arranged in a two-dimensional matrix at a total of n×m intersection portions where n scanning lines G1 to Gn extending in the horizontal direction (X direction) and m sets of data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (Y direction) intersect.

[0016] The scanning line Gj (j is an arbitrary integer from 1 to n) and the read switch selection line TGj are commonly connected to each of the m pixels 12 arranged in the j-th row. Also, the data lines Di+, Di- (i is an arbitrary integer from 1 to m) are commonly connected to each of the n pixels 12 arranged in the i-th column. Further, the gate control signal lines S+, S-, and the gate control signal line B are all commonly connected to all the pixels 12. However, the gate control signal lines S+, S-, and the gate control signal line B may all be provided individually for each row.

[0017] Based on the timing signal generated by the timing generator 13, the polarity switching control circuit 14 applies a gate control signal for positive polarity (hereinafter, the gate control signal) to the gate control signal line S+. outputs a control signal S+ (hereinafter referred to as the gate control signal S+), outputs a negative-polarity gate control signal (hereinafter referred to as the gate control signal S-), and further outputs a gate control signal (hereinafter referred to as the gate control signal B) to the gate control signal line B.

[0018] The vertical shift register & level shifter 15 outputs the scanning pulses of n rows from the first row to the nth row in order one by one at the period of one horizontal scanning period HST. The AND circuits ADA1 to AD An respectively control whether to output the scanning pulses of n rows sequentially output one by one from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn based on the mode switching signal MD supplied from the outside. The AND circuits ADB1 to ADBn respectively control whether to output the scanning pulses of n rows sequentially output one by one from the vertical shift register & level shifter 15 to the readout switch selection lines TG1 to TGn based on the mode switching signal MD supplied from the outside. For example, in the case of the operation of writing a video signal to the pixel 12 (image writing operation), an H-level mode switching signal MD is supplied from the outside. In this case, the AND circuits ADA1 to ADA n respectively output the scanning pulses of n rows sequentially output one by one from the vertical shift register & level shifter 15 to the row scanning lines G1 to Gn. On the other hand, the AND circuits ADB1 to ADBn do not output the scanning pulses of n rows sequentially output one by one from the vertical shift register & level shifter 15 to the readout switch selection lines TG1 to TGn. Therefore, all of the readout switch selection lines TG1 to TGn are fixed to the L level.

[0019]

[0020] On the other hand, the operation of reading out the video signal written in the pixel 12 (image reading operation ), a low-level mode switching signal MD is supplied from the outside. In this case, the AND circuit ADB1 to ADBn are each one row from the vertical shift register & level shifter 15. The scan pulses for n rows are sequentially output to the read switch selection lines TG1 to TGn. On the other hand, the AND circuits ADA1 to ADAn are vertical shift registers and level shifters, respectively. The n-row scanning pulses outputted sequentially from the cover 15 one row at a time are outputted to the row scanning lines G1 to Gn. Therefore, all of the row scanning lines G1 to Gn are fixed to the L level. (Specific configuration example of pixel 12) 3 is a diagram showing a specific example of the configuration of the pixel 12. Here, the pixel 12 is arranged in n rows and m columns. The pixel 12 located in the j-th row and the i-th column will be described.

[0021] As shown in FIG. 3, the pixel 12 includes an N-channel MOS transistor (hereinafter simply referred to as a transistor). Tr1, Tr2, Tr5, Tr6, Tr9 and P-channel MOS transistors The transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, and Tr8.

[0022] The transistor Tr1 and the storage capacitor Cs1 receive a positive voltage supplied via the data line Di+. This forms a sample-and-hold circuit that samples and holds the video signal. In the transistor Tr1, the source is connected to one data line Di+ of the data line pair, The drain is connected to the gate of transistor Tr3, and the gate is connected to row scanning line Gj. The storage capacitor Cs1 is connected between the gate of the transistor Tr3 and the ground voltage terminal Vss. It is being used.

[0023] The transistor Tr2 and the holding capacitor Cs2 form a sample-and-hold circuit that samples and holds the negative-polarity video signal supplied via the data line Di-. Specifically, in the transistor Tr2, the source is connected to the other data line Di- of the data line pair, the drain is connected to the gate of the transistor Tr4, and the gate is connected to the horizontal scanning line Gj and is in operation. The holding capacitor Cs2 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss. Note that the holding capacitors Cs1 and Cs2 are provided independently of each other and hold the positive-polarity and negative-polarity video signals in parallel.

[0024] The transistors Tr3 and Tr7 form a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitor Cs1. Specifically, in the source follower transistor Tr3, the drain is connected to the ground voltage line Vss, and the source is connected to the node Na. In the transistor Tr7 used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to the node Na, and the gate is connected to the gate control signal line B.

[0025] The transistors Tr4 and Tr8 form a source follower buffer that outputs the voltage held in the holding capacitor Cs2. Specifically, in the source follower transistor Tr4, the drain is connected to the ground voltage line Vss, and the source is connected to the node Nb. In the transistor Tr8 used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to the node Nb, and the gate is connected to the gate control signal line B.

[0026] Transistors Tr5 and Tr6 constitute a polarity switching switch. Specifically, In transistor Tr5, the source is connected to node Na, the drain is connected to the pixel driving electrode PE is connected, and the gate is connected to one of the gate control signal lines S+ of the gate control signal line pair. In transistor Tr6, the source is connected to node Nb, the drain is connected to the pixel driving electrode PE is connected, and the gate is connected to the other gate control signal line S- of the gate control signal line pair. is.

[0027] The liquid crystal display element LC includes a pixel driving electrode (reflective electrode) PE having a light reflection characteristic, a common electrode CE that is spaced apart from and opposed to the pixel driving electrode and has light transmissivity, and liquid crystal LCM filled in the space region therebetween. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the read switch selection line TGj. electrode, and a common electrode CE having light transmissivity and disposed opposite to the pixel driving electrode with a space therebetween, and liquid crystal LCM filled and sealed in the space region therebetween. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the read switch selection line TGj. sealed liquid crystal LCM. A common voltage Vcom is applied to the common electrode CE. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the read switch selection line TGj. applied. Transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+, and is switched on and off by the read switch selection line TGj. provided, and is switched on and off by the read switch selection line TGj.

[0028] Analog signals with different polarities that are sampled by the analog switch unit 17 are supplied to the data line pair Di+ and Di-. Here, when the scanning pulse output from the vertical shift register & level shifter 15 is supplied to the horizontal scanning line Gj, transistors Tr1 and Tr2 are simultaneously turned on. As a result, voltages of video signals with positive and negative polarities are respectively accumulated and held in the holding capacitors Cs1 and Cs2. are supplied. Here, when the scanning pulse output from the vertical shift register & level shifter 15 is supplied to the horizontal scanning line Gj, transistors Tr1 and Tr2 are simultaneously turned on. As a result, voltages of video signals with positive and negative polarities are respectively accumulated and held in the holding capacitors Cs1 and Cs2. 15 is supplied to the horizontal scanning line Gj, transistors Tr1 and Tr2 are simultaneously turned on. As a result, voltages of video signals with positive and negative polarities are respectively accumulated and held in the holding capacitors Cs1 and Cs2. r2 are simultaneously turned on. As a result, voltages of video signals with positive and negative polarities are respectively accumulated and held in the holding capacitors Cs1 and Cs2. and negative polarities are accumulated and held.

[0029] Note that the input resistances of the source follower buffers on the positive and negative sides are almost infinite. Therefore, the charges accumulated in the holding capacitors Cs1 and Cs2 do not leak. It is held without any change until a new video signal is written after one vertical scanning period has elapsed.

[0030] The transistors Tr5 and Tr6 that constitute the polarity switching switch (selection unit) are turned on and off complementarily according to the gate control signals S+ and S-, and the output voltage of the source follower buffer on the positive electrode side (the voltage of the video signal with positive polarity) and the output voltage of the source follower buffer on the negative electrode side (the voltage of the video signal with negative polarity) are alternately selected and output to the pixel driving electrode PE. As a result, a voltage of a video signal that periodically reverses in polarity is applied to the pixel driving electrode PE. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. and output to the pixel driving electrode PE. As a result, a voltage of a video signal that periodically reverses in polarity is applied to the pixel driving electrode PE. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. and output to the pixel driving electrode PE. As a result, a voltage of a video signal that periodically reverses in polarity is applied to the pixel driving electrode PE. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. and output to the pixel driving electrode PE. As a result, a voltage of a video signal that periodically reverses in polarity is applied to the pixel driving electrode PE. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. and output to the pixel driving electrode PE. As a result, a voltage of a video signal that periodically reverses in polarity is applied to the pixel driving electrode PE. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. In this way, since this liquid crystal display device has a polarity inversion function in the pixel itself, at each pixel, by quickly switching the polarity of the voltage of the video signal supplied to the pixel driving electrode PE, AC driving at a high frequency is possible regardless of the vertical scanning frequency. (Explanation of the AC driving method of pixel 12) FIG. 4 is a timing chart for explaining the AC driving method of pixel 12 by the liquid crystal display device 50. Here, the AC driving method of pixel 12 provided at the j-th row and i-th column among the n×m pixels 12 will be explained. FIG. 4 is a timing chart for explaining the AC driving method of pixel 12 by the liquid crystal display device 50. Here, the AC driving method of pixel 12 provided at the j-th row and i-th column among the n×m pixels 12 will be explained. FIG. 4 is a timing chart for explaining the AC driving method of pixel 12 by the liquid crystal display device 50. Here, the AC driving method of pixel 12 provided at the j-th row and i-th column among the n×m pixels 12 will be explained.

[0031] In FIG. 4, VST represents the vertical synchronization signal that serves as a reference for the vertical scanning of the video signal. B represents the gate control signals supplied to the gates of the transistors Tr7 and Tr8 used as the constant current loads of the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of the transistor Tr5 on the positive electrode side provided in the polarity switching switch. S- represents the gate control signal supplied to the gate of the transistor on the negative electrode side provided in the polarity switching switch. In FIG. 4, VST represents the vertical synchronization signal that serves as a reference for the vertical scanning of the video signal. B represents the gate control signals supplied to the gates of the transistors Tr7 and Tr8 used as the constant current loads of the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of the transistor Tr5 on the positive electrode side provided in the polarity switching switch. S- represents the gate control signal supplied to the gate of the transistor on the negative electrode side provided in the polarity switching switch. In FIG. 4, VST represents the vertical synchronization signal that serves as a reference for the vertical scanning of the video signal. B represents the gate control signals supplied to the gates of the transistors Tr7 and Tr8 used as the constant current loads of the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of the transistor Tr5 on the positive electrode side provided in the polarity switching switch. S- represents the gate control signal supplied to the gate of the transistor on the negative electrode side provided in the polarity switching switch. In FIG. 4, VST represents the vertical synchronization signal that serves as a reference for the vertical scanning of the video signal. B represents the gate control signals supplied to the gates of the transistors Tr7 and Tr8 used as the constant current loads of the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of the transistor Tr5 on the positive electrode side provided in the polarity switching switch. S- represents the gate control signal supplied to the gate of the transistor on the negative electrode side provided in the polarity switching switch. In FIG. 4, VST represents the vertical synchronization signal that serves as a reference for the vertical scanning of the video signal. B represents the gate control signals supplied to the gates of the transistors Tr7 and Tr8 used as the constant current loads of the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of the transistor Tr5 on the positive electrode side provided in the polarity switching switch. S- represents the gate control signal supplied to the gate of the transistor on the negative electrode side provided in the polarity switching switch. VPE represents the gate control signal supplied to the gate of transistor Tr6. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0032] 5 shows the relationship between the positive and negative video signals written to the pixel 12. 5 is a diagram for explaining voltage levels from black to white of a positive polarity video signal. represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. In contrast, a negative video signal represents a white level when its voltage level is at its minimum, The maximum voltage level represents the black level. However, the positive video signal The minimum voltage level represents the white level, and the maximum voltage level represents the black level. Also, a negative video signal represents a black level when the voltage level is minimum, and The dashed line in the figure indicates the positive polarity image. 10 shows the inversion centers of the video signal and the negative video signal.

[0033] In the pixel 12, the transistor Tr9 is turned on when the read switch selection line TGj is at the L level. On the other hand, transistors Tr1 and Tr2 are fixed to the row When a scanning pulse is supplied to the scanning line Gj, the storage capacitor C The voltages of the positive and negative video signals are stored and held in s1 and Cs2, respectively.

[0034] As shown in FIG. 4, during the period when the gate control signal S+ is at the H level, the positive-side transistor At this time, by setting the gate control signal B to L level, the transistor Since start Tr7 is turned on, the source follower buffer on the positive side becomes active. As a result, the pixel driving electrode PE is charged to the voltage level of the positive polarity video signal. By setting the port control signal B to L level, the transistor Tr8 turns on, and the negative polarity The source follower buffer on the positive side is also active. Since the pixel transistor Tr6 is off, the pixel driving electrode PE is at the voltage level of the negative video signal. When the pixel drive electrode PE is fully charged, the gate control Signal B is switched from L level to H level, and gate control signal S+ is switched from H level to This causes the pixel drive electrode PE to be in a floating state. Therefore, a positive drive voltage is maintained in the liquid crystal capacitance.

[0035] On the other hand, while the gate control signal S- indicates the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative side transistor Tr8 turns on, and the negative side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the negative video signal. By setting the control signal B to L level, the transistor Tr7 turns on, The source follower buffer is also active. However, the positive-side transistor T Since r5 is off, the pixel drive electrode PE is charged to the voltage level of the positive polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from L level to H level, and the gate control signal S- is switched from H level to L level. Switch to the bell. As a result, the pixel driving electrode PE becomes floating, so the liquid crystal capacitance retains the driving voltage of the negative polarity.

[0036] By alternately repeating the above operations on the positive electrode side and the negative electrode side, an alternating driving voltage VPE is applied to the pixel driving electrode PE using the voltages of the video signals of the positive and negative polarities respectively. That is, the driving voltage VPE is applied to the pixel driving electrode PE.

[0037] Note that the charges held in the holding capacitances Cs1 and Cs2 are not directly transferred to the pixel driving electrode PE, but are transferred via a source follower buffer. Therefore, even when the charging and discharging of the voltages of the video signals of the positive and negative polarities are repeatedly performed at the pixel driving electrode PE, pixel driving without charge neutralization and without attenuation of the voltage level can be realized. Since the charges held in the holding capacitances Cs1 and Cs2 are not directly transferred to the pixel driving electrode PE, but are transferred via a source follower buffer, even when the charging and discharging of the voltages of the video signals of the positive and negative polarities are repeatedly performed at the pixel driving electrode PE, pixel driving without charge neutralization and without attenuation of the voltage level can be realized. That is, even when the charging and discharging of the voltages of the video signals of the positive and negative polarities are repeatedly performed at the pixel driving electrode PE, pixel driving without charge neutralization and without attenuation of the voltage level can be realized. That is, pixel driving without charge neutralization and without attenuation of the voltage level can be realized.

[0038] Also, as shown in FIG. 4, in synchronization with the switching of the voltage level of the applied voltage VPE to the pixel driving electrode PE, the voltage level of the applied voltage Vcom to the common electrode CE is switched to a level opposite to that of the applied voltage VPE. Note that the applied voltage Vcom to the common electrode CE is inverted with a voltage substantially equal to the inversion reference voltage of the applied voltage VPE to the pixel driving electrode PE as the reference. That is, in synchronization with the switching of the voltage level of the applied voltage VPE to the pixel driving electrode PE, the voltage level of the applied voltage Vcom to the common electrode CE is switched to a level opposite to that of the applied voltage VPE. Note that the applied voltage Vcom to the common electrode CE is inverted with a voltage substantially equal to the inversion reference voltage of the applied voltage VPE to the pixel driving electrode PE as the reference. That is, the applied voltage Vcom to the common electrode CE is inverted with a voltage substantially equal to the inversion reference voltage of the applied voltage VPE to the pixel driving electrode PE as the reference.

[0039] Here, since the substantial AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the applied voltage VPE to the pixel driving electrode PE and the applied voltage Vcom to the common electrode CE, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, by switching the applied voltage Vcom to the common electrode CE in the opposite phase to the applied voltage VPE to the pixel driving electrode PE, the amplitude of the voltage to be applied to the pixel driving electrode PE can be reduced. Therefore, since the substantial AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the applied voltage VPE to the pixel driving electrode PE and the applied voltage Vcom to the common electrode CE, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. That is, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, by switching the applied voltage Vcom to the common electrode CE in the opposite phase to the applied voltage VPE to the pixel driving electrode PE, the amplitude of the voltage to be applied to the pixel driving electrode PE can be reduced. That is, by switching the applied voltage Vcom to the common electrode CE in the opposite phase to the applied voltage VPE to the pixel driving electrode PE, the amplitude of the voltage to be applied to the pixel driving electrode PE can be reduced. This makes it possible to reduce the breakdown voltage and power consumption of the transistors that form the circuit portion of the pixel.

[0040] Let us assume that the current flowing steadily through the source follower buffer per pixel is a minute 1 μA. Even if the current is small, the current that flows steadily through all the pixels of the LCD device cannot be ignored. For example, a full high-definition 2-megapixel LCD display may generate a large current. In this case, the current consumption may reach 2 A. Therefore, in the pixel 12, a constant current load is used. The transistors Tr7 and Tr8 used as loads are not always on, but are connected to the positive poles of the transistors Tr7 and Tr8. And only for a limited period of time during which the negative side transistors Tr5 and Tr6 are on. Therefore, when one of the source follower buffers is operating, The operation of the other source follower buffer can be stopped, preventing an increase in current consumption. It can be suppressed.

[0041] The AC driving frequency of the liquid crystal display element LC is independent of the vertical scanning frequency, and the pixel itself is inverted. For example, the vertical scanning frequency is generally The 60Hz used in television video signals is the number of vertical scanning lines in full high definition. The polarity switching for each pixel is assumed to be 15 line periods. In other words, the number of lines per polarity switching period for each pixel is The number of lines is 30. In this case, the AC driving frequency of the liquid crystal is 60Hz x 1125 / (15×2)=2.25 Hz. In other words, the liquid crystal display device 50 has an AC driving frequency of 150 Hz. This allows the wave number to be dramatically increased, which solves the problem of low AC driving frequencies for liquid crystals. It is possible to significantly improve the reliability, stability, and display quality of the video displayed on the liquid crystal screen that has been the problem. It can be achieved.

[0042] Subsequently, the operations of the liquid crystal display device 50 in each operation mode will be described. (Operation of the liquid crystal display device 50 in the image display mode) First, the operation of the liquid crystal display device 50 in the image display mode will be described with reference to FIG. 6. FIG. 6 is a timing chart showing the operation of the liquid crystal display device 50 in the image display mode.

[0043] As shown in FIG. 6, when the pulse signal of the horizontal synchronization signal HST is supplied, the shift register circuit 561 sequentially captures an m-column video signal with an s-bit width (where s is an integer of 2 or more) in synchronization with the clock signal HCK. The one-line latch circuit 562 outputs the m-column video signal captured by the shift register circuit 561 all at once at the timing when the trigger signal REG_S becomes temporarily active.

[0044] The gradation counter 564 counts the number of rising edges of the clock signal CNT_CK and outputs a gradation signal Cout with a gradation level corresponding to the count value. Here, the gradation counter 564 outputs a gradation signal Cout with the minimum level at the start of one horizontal scanning period (when the horizontal synchronization signal HST rises), increases the gradation level of the gradation signal Cout as the count value increases, and outputs a gradation signal Cout with the maximum level immediately before the next rise of the horizontal synchronization signal HST at the end of one horizontal scanning period. Note that the count value of the gradation counter 564 is initialized to "0" when the reset signal CNT_R becomes active in response to the rise of the horizontal synchronization signal HST, for example.

[0045] The m columns of comparators 563_1 to 563_m provided in the comparator section 563 are The grayscale signal output from the grayscale counter 564 is synchronized with the clock signal CMP_CK. Cout is the m-th row of video signals (line data) output simultaneously from the 1-line latch circuit 562. At the timing that coincides with each of the coincidence signals P1 to Pm, the coincidence signals P1 to Pm are made active (for example, L level). Bell).

[0046] m pairs of switch elements SW1+, SW1- to SWm provided in the analog switch section 17 Among the positive polarity switch elements SW1+ to SWm+, the positive polarity switch elements SW1+ to SWm+ are It is provided between the lines D1+ to Dm+ and the common wiring Dcom+. The switch elements SW1- to SWm- are connected to the data lines D1- to Dm- and the common wiring D com- and m sets of switch elements SW1+, SW1- to SWm+ , SWm- are the match signals P1 to Pm from the comparators 563_1 to 563_m, respectively. Switch on / off with m.

[0047] The common wiring Dcom+ is connected to the positive polarity ramp signal output from the ramp signal generator 2. The reference lamp voltage Ref_R+ is supplied to the common wiring Dcom-. is the reference ramp voltage Re which is a negative ramp signal output from the ramp signal generator 2. f_R- is supplied.

[0048] The reference ramp voltage Ref_R+ is the video level from the start to the end of each horizontal scanning period. is a sweep signal that changes from black level to white level. The reference ramp voltage Ref_R- is A scanning signal in which the image level changes from white to black from the start to the end of the horizontal scanning period. It is a reference signal. Therefore, the reference lamp voltage Ref_R+ with respect to the common voltage Vcom and the reference lamp voltage Ref_R- with respect to the common voltage Vcom are in an inverted relationship with each other.

[0049] The switch elements SW1+, SW1-~SWm+, SWm- are all turned on when the start signal SW_Start becomes active (for example, at the H level) at the start of the horizontal scanning period. After that, the switch elements SW1+, SW1-~SWm+, SWm- are each switched from on to off when the coincidence signals P1~Pm output from the comparators 563_1~563_m become active (for example, at the L level). Note that the start signal SW_Start becomes inactive (for example, at the L level) at the end of the horizontal scanning period.

[0050] In the example of FIG. 6, the waveform indicating the timing for switching the on / off of the switch elements SWq+, SWq- (where q is an integer from 1 to m) provided corresponding to the pixel column where the video signal of the gradation level k is written is shown as the waveform SPk. Referring to FIG. 6, the above-mentioned switch elements SWq+, SWq- are turned on at the rising edge of the start signal SW_Start and then switched from on to off when the coincidence signal Pq becomes active. Here, the switch elements SWq+, SWq- sample the reference lamp voltages Ref_R+, Ref_R- (voltages P, Q in FIG. 6) at the timing of switching from on to off. These sampled voltages P, Q are supplied to the data lines Dq+, Dq-. In other words, the analog voltages P, Q that are the DA conversion results of the video signal of the gradation level k are respectively data ​​​​​​​​​​​​​It is supplied to the lines Dq+ and Dq-.

[0051] In the image display mode, an H-level mode switching signal MD is supplied from the outside. Therefore, the n rows of scanning pulses sequentially output one row at a time from the vertical shift register & level shifter 15 are supplied to the row scanning lines G1 to Gn, respectively. Thereby, for example, the transistors Tr1 and Tr2 provided in each pixel 12 of the j-th row are temporarily turned on when a scanning pulse is supplied to the row scanning line Gj. As a result, the voltages of the video signals of the corresponding positive and negative polarities are accumulated and held in the holding capacitors Cs1 and Cs2 provided in each pixel 12 of the j-th row. On the other hand, the transistor Tr9 provided in each pixel 12 maintains the off state. The AC driving method of each pixel 12 thereafter is as already described.

[0052] As described above, the switch elements SW1+, SW1- to SWm+, SWm- are turned on all at once at the start of each horizontal scanning period, but are turned off at an arbitrary timing according to the gradation level of the image to be displayed on the corresponding pixel 12. That is, the switch elements SW1+, SW1- to SWm+, SWm- may all be turned off at the same time, or may be turned off at different timings. Also, the order of turning off is not fixed.

[0053] In this way, the liquid crystal display device 50 can improve the linearity of the image by DA-converting the video signal using the lamp signal and then writing it to the pixel 12. (Operation of the liquid crystal display device 50 in the pixel inspection mode) Next, the operation of the liquid crystal display device 50 in the pixel inspection mode will be described. In the pixel inspection mode, an inspection device is provided instead of the lamp signal generator 2. ​

[0054] In the pixel inspection mode, first, the writing of the inspection video signal is performed row by row in order from the m pixels 12 in the first row to the m pixels 12 in the nth row. The operation at this time is basically the same as the operation in the pixel display mode. Then, the video signal (pixel drive voltage VPE) written to the pixel 12 to be inspected is read out.

[0055] In the pixel readout operation, the mode switching signal MD supplied from the outside switches from the H level to the L level. Therefore, among the n rows of scanning pulses sequentially output from the vertical shift register & level shifter 15 row by row, the scanning pulse of the jth row to be inspected is supplied to the readout switch selection line TGj. As a result, the transistor Tr9 provided in each pixel 12 of the jth row to be inspected is temporarily turned on when the scanning pulse is supplied to the readout switch selection line TGj. On the other hand, the transistors Tr1, Tr2 provided in each pixel 12 maintain the off state.

[0056] For example, in the pixel 12 provided in the jth row and the ith column, when the transistor Tr9 is turned on, the pixel drive electrode PE and the data line Di+ are in a conductive state, so the voltage of the pixel drive electrode PE is read out to the data line Di+. At this time, the transistors Tr7, Tr8 are activated, and by turning on either of the transistors Tr5, Tr6, the pixel drive electrode PE is in a state driven by a source follower buffer composed of the transistors Tr3, Tr7 or the transistors Tr4, Tr8. Thereby, the drive voltage VPE applied to the pixel drive electrode PE by the source follower buffer is output to the data line Di+. ​​​​​​​​​​​​​is read out.

[0057] The m pixel drive voltages VPE read from the m pixels 12 in the j-th row to be inspected are respectively supplied to the data lines D1+ to Dm+ sequentially by turning on the m sets of SW1+, SW1- to SWm+, SWm- provided in the analog switch section 17, and are sequentially supplied to the common wiring Dcom+. An inspection device (not shown) provided instead of the lamp signal generator 2 detects the presence or absence of failures (pixel defects and characteristic degradation) of the m pixels 12 in the j-th row based on the m pixel drive voltages VPE sequentially supplied via the common wiring Dcom+. Such inspections are performed one row at a time in order from the m pixels 12 in the first row to the m pixels 12 in the n-th row.

[0058] Here, in the pixel 12 to be inspected, since the voltage VPE of the pixel drive electrode PE driven by the source follower buffer with low output impedance is read out as it is, it is possible to accurately and easily detect the defects and characteristic degradation of the pixel 12 to be inspected.

[0059] By the way, in the liquid crystal display device 50, several measures are taken to improve the image display performance.

[0060] First, among the first to s-th bit signals constituting the s-bit width video signal, the period of signal change of the first bit signal, which is the least significant bit signal, is the shortest, and the period of signal change gradually becomes longer from the first bit signal to the first 0-bit signal, and the period of signal change of the first 0-bit signal, which is the most significant bit signal, is the longest (see FIG. 7).

[0061] Therefore, the first bit signal line through which the first bit signal that frequently changes in signal is propagated is different from other bits​​​​​​​​​​​​ In comparison with the ground signal line, it is placed near the ground wiring, which is advantageous for high frequency operation. The first bit signal line, through which the first bit signal, which frequently changes, propagates, is different from the other bit signal lines. In comparison, in order to avoid the influence of noise from the analog switch section 17, They are arranged in an area away from the analog switch section 17. Even if the setting is increased, stable operation is possible, and the afterimage effect of the displayed image is eliminated.

[0062] However, in the liquid crystal display device 50, the first bit signal, which frequently changes, propagates. The length of the first bit signal line (specifically, the length from the 1-line latch circuit 562 to the comparator unit 5 The length of the first bit signal line (up to 63) is longer than the other bit signal lines. Generally, the longer the signal line, the more likely it is that current will leak from the signal line to the inter-wiring film. At the same time, it is subject to the influence of dust due to manufacturing defects and dimensional fluctuations during pattern exposure. This makes it easier for the wiring resistance to increase in parts (see Figure 8). The higher the temperature, the more current leakage and resistance increase, and the more deterioration occurs due to long-term continuous use. Therefore, the first bit signal, which changes frequently, is propagated. The first bit signal line is prone to progressive failure due to long-term continuous use. As a result, the liquid crystal display device 50 has a problem of reduced operational reliability. In addition, the influence of dust due to defects during manufacturing and dimensional fluctuations during pattern exposure may occur during the initial This also caused operational problems in the device, resulting in a decrease in manufacturing yield. .

[0063] Therefore, the liquid crystal display device according to the first embodiment, which can improve reliability and manufacturing yield, is A display device and method for manufacturing the same have been discovered. <First Embodiment> 9 is a block diagram showing a liquid crystal display device 1 according to the first embodiment. 1 is equipped with a horizontal driver 16 instead of a horizontal driver 56, as compared with the liquid crystal display device 50. Other configurations of the liquid crystal display device 1 are the same as those of the liquid crystal display device 50. Therefore, the description thereof will be omitted.

[0064] The horizontal driver 16 includes a shift register section 161, a one-line latch section 162, and a comparator. The shift register unit 161 includes a shift register unit 163 and a gradation counter 164. The latch unit 162, the comparator unit 163, and the gradation counter 164 are shift registers. a register circuit 561, a one-line latch circuit 562, a comparator section 563, and a gradation It corresponds to the counter 564.

[0065] The shift register unit 161, like the shift register circuit 561, receives the clock signal HCK In synchronization with the 1 line, the video signal with a bit width of s (s is an integer of 2 or more) is sequentially captured for m lines. The in-latch unit 162, like the 1-line latch circuit 562, The captured m-row s-bit video signal is temporarily activated when the trigger signal REG_S is When the signal becomes active, it is latched and output all at once.

[0066] The gradation counter 164 counts the number of rising edges of the clock signal CNT_CK. The gray scale signal Cout is output at a gray scale level corresponding to the count value of the gray scale counter. 164 is the minimum level at the start of one horizontal scanning period (at the rising edge of the horizontal sync signal HST). The grayscale signal Cout of the counter is output, and the grayscale level of the grayscale signal Cout increases as the count value increases. At the end of one horizontal scanning period (just before the next rising edge of the horizontal sync signal HST), The gradation signal Cout is output at the maximum level. The value is, for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST. It is initialized to "0" when it becomes active.

[0067] The m columns of comparators 163_1 to 163_m provided in the comparator section 163 are The grayscale signal output from the grayscale counter 164 is synchronized with the clock signal CMP_CK. Cout is m columns of video signals (line data) output simultaneously from the 1-line latch unit 162. ), the coincidence signals P1 to Pm are made active (for example, L level) at the timing that coincides with each of the coincidence signals P1 to Pm. (ru).

[0068] Other configurations and operations of the horizontal driver 16 are the same as those of the horizontal driver 56. Therefore, the description thereof will be omitted. (Specific Configuration Example of Shift Register Unit 161 and Its Peripheral Circuits) FIG. 10 is a block diagram showing a specific example of the configuration of the shift register unit 161 and its peripheral circuits. In the example of FIG. 10, when the bit width of the video signal is 10 bits (s=10), 10, the one-line latch unit 162, the comparator unit 163, and the , a gradation counter 164, and an analog switch section 17 are also shown.

[0069] As shown in FIG. 10, the shift register section 161 has 10 registers corresponding to the bit width of the video signal. The shift register circuits 161_1 to 161_10 are configured as follows. The latch unit 162 has ten one-line latch circuits 162_ corresponding to the bit width of the video signal. It consists of 1~162_10.

[0070] The shift register circuit 161_1 shifts the first to tenth bits constituting a 10-bit wide video signal. The first bit signal, which is the least significant bit signal, is sequentially acquired for m columns of the bit signal. Similarly, the shift register circuits 161_2 to 161_10 are second to tenth shift registers, respectively. The bit signal is sequentially acquired for m columns.

[0071] The one-line latch circuit 162_1 latches the m columns of data captured by the shift register circuit 161_1. The first bit signal of the minute is sent when the trigger signal REG_S becomes temporarily active. Similarly, the one-line latch circuits 162_2 to 162_10 are respectively The second to tenth bits of m columns taken into the shift register circuits 161_2 to 161_10 are The trigger signals are output simultaneously when the trigger signal REG_S becomes temporarily active. To exert effort.

[0072] Here, among the first to tenth bit signals, the first bit signal is the least significant bit signal. The signal change period is the shortest, and gradually changes from the 1st bit signal to the 10th bit signal. The period of signal change becomes longer, and the signal change of the 10th bit signal, which is the most significant bit signal, Therefore, if the signal lines are the same length, the first to tenth Among the 1st to 10th bit signal lines through which the bit signals propagate, The first bit signal line through which the first bit signal propagates has progressive defects due to long-term continuous use. Failures and manufacturing defects are likely to occur.

[0073] Therefore, in this embodiment, among the one-line latch circuits 162_1 to 162_10, the one-line latch circuit 162_1 is arranged closer to the comparator unit 163 than at least the one-line latch circuit 162_10. More preferably, the one-line latch circuit 162 _1 is arranged closer to the comparator unit 163 than the one-line latch circuits 162_2 to 162_10.

[0074] As a result, the length of the first-bit signal line wired from the one-line latch circuit 162_1 to the comparator unit 163 is shorter than the lengths of the second to tenth-bit signal lines wired from each of the one-line latch circuits 162_2 to 162_10 to the comparator unit 163.

[0075]

[0076] The first row in FIG. 11 shows the ideal waveform of the first-bit signal, which is the least significant bit signal. is shown. As shown in FIG. 11, the ideal waveform of the first-bit signal is a rectangular wave.

[0077] The second row of FIG. 11 shows the waveform of the first-bit signal in the liquid crystal display device 1. Specifically the shift register circuits 161_1 and the 1-line latch circuit 162_1 show the waveform of the first-bit signal when they are arranged closer to the analog switch section 17 (that is, the comparator section 163) than other shift register circuits and the 1-line latch circuit.

[0078] The third row of FIG. 11 shows the waveform of the first-bit signal in the liquid crystal display device 50. Specifically the circuits corresponding to the shift register circuits 161_1 and the 1-line latch circuit 162_1 respectively show the waveform of the first-bit signal when they are arranged farther from the analog switch section 17 (that is, the comparator section 563) than other shift register circuits and the 1-line latch circuit.

[0079] Comparing the waveform in the second row of FIG. 11 with the waveform in the third row of FIG. 11, since the wiring length of the signal line through which the first-bit signal propagates (hereinafter referred to as the first-bit signal line) is shorter, the RC time constant becomes smaller , and the distortion of the first-bit signal becomes smaller. On the other hand, for the waveform in the third row of FIG. 11 , since the wiring length of the first-bit signal line is long, the RC time constant becomes large, and the distortion of the first-bit signal becomes large.

[0080] The waveform in the fourth row of FIG. 11 shows the waveform of the coincidence signal Pi corresponding to the first-bit signal shown in the third row of FIG. 11. That is, the waveform in the fourth row of FIG. 11 shows the waveform of the coincidence signal Pi when the wiring length of the first-bit signal line is long. In this case, the distortion of the first-bit signal is large. Since it is large, both the rise and fall of the comparator output lag behind the rise and fall of the ideal first bit signal.

[0081] The waveform of the fifth stage in FIG. 11 shows the case where the circuits corresponding to the shift register circuit 161_1 and the 1-line latch circuit 16 2_1 are arranged farther from the analog switch section 17 (i.e., the comparator section 563) than the other shift register circuits and the 1-line latch circuit. In this case, when the first bit signal line becomes high resistance due to current leakage or manufacturing defects, the waveform of the first bit signal is shown. In this case, since the wiring length of the first bit signal line is long, the RC time constant becomes large, and in addition to the large smear of the first bit signal, due to the influence of current leakage and the increase in the resistance of the wiring, the voltage level of the first bit signal cannot rise above the threshold voltage at which it is determined to be the H level. Therefore, as shown in the sixth stage of FIG. 11, the coincidence signal Pi cannot rise to the H level and remains in the L level state. That is, the liquid crystal display device 50 cannot operate normally.

[0082] On the other hand, in the liquid crystal display device 1 according to the present embodiment, the shift register circuit 161_ 1 and the 1-line latch circuit 162_1 are arranged closer to the analog switch section 17 (i.e., the comparator section 163) than the other shift register circuits and the 1-line latch circuit. Since the wiring length of the first bit signal line is short, the RC time constant becomes small, and the smear of the first bit signal is small. Therefore, the liquid crystal display device 1 can operate normally even when a little current leakage or an increase in the resistance of the wiring occurs.

[0083] ​​​That is, even when the wiring becomes highly resistive due to current leakage or manufacturing defects, the liquid crystal display device 1 according to the present embodiment can operate normally. As a result, reliability and manufacturing yield are improved.

[0084] As described above, in the liquid crystal display device 1 according to the present embodiment, among the plurality of bit signals constituting the video signal, the length of the first bit signal line through which the least significant bit signal that frequently changes in signal is propagated is shorter than the lengths of the second to tenth bit signal lines through which the other bit signals are propagated. Thereby, in the first bit signal line through which the first bit signal that frequently changes in signal is propagated, even when current leakage from the signal line to the interlayer insulating film occurs or the wiring resistance partially increases due to manufacturing defects or the like, the load of the signal line is reduced due to the decrease in the RC time constant caused by the short length of the wiring. As a result, progressive failures caused by long-term continuous use are less likely to occur. As a result, the reliability of the liquid crystal display device 1 is improved. Also, the manufacturing yield is improved.

[0085] The liquid crystal display device 1 according to the present embodiment is used, for example, as an optical switching element of a WSS device mounted in an optical communication system. Here, when the liquid crystal display device 1 is used as an optical switching element of a WSS device, since a high operating frequency is not required as compared with the case of being used for image display, there is no problem even if the one-line latch circuit 162_1 is arranged away from the ground wiring (that is, in the vicinity of the comparator unit 163) in order to shorten the first bit signal line. Also, in this case, since a certain amount of afterimage is allowed as compared with the case of being used for image display, the one-line latch circuit 162_1 is used as an analog switch in order to shorten the first bit signal line. ​ There is no problem even if it is arranged near the chi part 17 (that is, the comparator part 163).

Explanation of symbols

[0086] 1 Liquid crystal display device 2 Lamp signal generator 11 Image display section 12 Pixel 13 Timing generator 14 Polarity switching control circuit 15 Vertical shift register & level shifter 16 Horizontal driver 17 Analog switch section 50 Liquid crystal display device 56 Horizontal driver 161 Shift register section 161_1~161_10 Shift register circuit 162 1-line latch section 163 Comparator section 163_1~163_m Comparator 164 Tone counter 561 Shift register circuit 562 1-line latch circuit 563 Comparator section 563_1~563_m Comparator 564 Tone counter ADA1~ADAn AND circuit ADB1~ADBn AND circuit B Gate control signal line CE Common electrode Cs1,Cs2 Holding capacitor D1+,D1-~Dm+,Dm- Data line Dcom+,Dcom- Common wiring G1~Gn Row scanning line LC Liquid crystal display element LCM Liquid crystal Na,Nb Node PE Pixel drive electrode (reflective electrode) S+,S- Gate control signal line SW1+, SW1- ~ SWm+, SWm- Switch elements TG1+ ~ TGn+ Read switch selection lines TG1- ~ TGn- Read switch selection lines Tr1 ~ Tr9 Transistors

Claims

【Claim 1】 A plurality of pixels; A plurality of data lines provided corresponding to each column of the plurality of pixels; A shift register section that sequentially captures an s (where s is an integer of 2 or more)-bit-width video signal for the number of columns of the plurality of pixels; A latch section that outputs the plurality of video signals captured by the shift register section all at once; A plurality of comparators that convert the plurality of video signals output from the latch section into a plurality of analog voltages respectively; An analog switch section that switches whether or not to supply the plurality of analog voltages to the plurality of data lines respectively; A liquid crystal display device, comprising: The shift register section has first to s-th shift register circuits that sequentially capture first to s-th bit signals constituting the s-bit-width video signal for the number of columns of the plurality of pixels; The latch section has first to s-th latch circuits that output all at once the first to s-th bit signals for the number of columns of the plurality of pixels captured by the first to s-th shift register circuits respectively; Among the first to s-th latch circuits, the first latch circuit configured to output all at once a plurality of the first bit signals that are the least significant bit signals is arranged closer to the plurality of comparators than the s-th latch circuit configured to output all at once a plurality of the s-th bit signals that are the most significant bit signals; the first to s-th latch circuits and the plurality of comparators are connected by direct wiring; The first to s-th shift register circuits and the first to s-th latch circuits are arranged adjacent to each other corresponding to the first to s-th bit signals, and the first to s-th latch circuits for latching each bit signal are arranged between the first to s-th shift register circuits corresponding to each bit signal; The wiring between the first to s-th latch circuits and the plurality of comparators is the lowest layer wiring. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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