Orthogonal Printed Circuit Board Interface

Abstract

A dual polarized PCB array antenna is provided. SOLUTION: The dual polarized PCB array antenna includes one or more PCBs and a radiating antenna array. Each PCB has a PCB mounting surface extending from a first PCB end to an opposing second PCB end. The radiating antenna array includes one or more radiator substrates. Each radiator substrate has a patch mounting surface extending from a first substrate end to an opposing second substrate end. The dual polarized PCB array antenna further includes one or more orthogonal interfaces configured to align the patch mounting surface of a given radiator substrate in an orthogonal position relative to the PCB mounting surface of a given PCB.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Application No. 17 / 200155, filed on March, 12, 2021, which is hereby incorporated by reference in its entirety.

[0002] The present disclosure relates to antennas, and more particularly to phased - array antennas.

[0003] Phased - array antennas (also referred to as "phased arrays") are used in communication, radar, direction - finding systems, and many other multifunctional radio - frequency (RF) systems. A phased - array antenna typically includes an array of individual radiating antenna elements. The selection of the individual radiating elements and the arrangement of such elements affect the ability to efficiently transmit and receive RF signals having multiple polarizations.

[0004] An example of an architecture used to facilitate phased - array antennas is what is referred to as a "PCB array". The PCB - array architecture is so named because it typically implements two separate array packages on opposite surfaces of a relatively long printed - circuit board (PCB). The large surface area that exists over the depth of each individual PCB provides a large area for implementing components and transmit / receive modules, while at the same time dispersing the heat load over a large volume.

Summary of the Invention

[0005] According to a non-limiting embodiment, a dual-polarization PCB array antenna is provided. The dual-polarization PCB array antenna includes a plurality of PCBs and a radiating antenna array. The plurality of PCBs extend along a first axis that defines a PCB width, a second axis that is orthogonal to the first axis and defines a PCB height, and a third axis that is orthogonal to the first and second axes and defines a PCB length. Each PCB has a PCB mounting surface that extends along the second axis from a first PCB end to an opposing second PCB end and along the third axis from a third PCB end to a fourth PCB end. The radiating antenna array includes a plurality of radiator substrates. Each radiator substrate has a patch mounting surface that extends along the first axis from a first substrate end to an opposing second substrate end and along the third axis from a third substrate end to an opposing fourth substrate end. The dual-polarization PCB array antenna further includes a plurality of orthogonal interfaces configured to arrange the patch mounting surfaces of the plurality of radiator substrates in an orthogonal position with respect to the PCB mounting surfaces of the plurality of PCBs.

[0006] According to other non-limiting embodiments, an orthogonal printed circuit board (PCB) interface included in a dual-polarization array antenna is provided. The orthogonal PCB interface includes a PCB and a radiator substrate. The PCB includes a PCB mounting surface that includes a first plurality of conductive elements. The radiator substrate includes a patch mounting surface that includes a second plurality of conductive elements. The second plurality of conductive elements are coupled to the first plurality of conductive elements such that the patch mounting surface of the radiator substrate is arranged in an orthogonal position with respect to the PCB mounting surface of the PCB.

[0007] According to yet another non - limiting embodiment, a shielded channel interface included in a dual - polarized printed circuit board (PCB) array antenna is provided. The shielded channel interface includes a plurality of first conductive elements coupled to the PCB mounting surface of the PCB and a plurality of second conductive elements coupled to the patch mounting surface of the radiator substrate. The plurality of second conductive elements extend perpendicularly from the patch mounting surface to establish electrical connections to the plurality of first conductive elements. At least two of the electrical connections are configured to receive a first signal, at least one of the electrical connections is configured to receive a second signal different from the first signal, and at least one of the second connections is positioned between at least two of the first connections.

[0008] Further features and advantages are realized through the techniques of the present disclosure. In this specification, other embodiments and aspects are described in detail and considered to be part of the claimed disclosure. Refer to the description and drawings to better understand the present disclosure with its advantages and features.

[0009] To understand the present disclosure more fully, reference is now made, in conjunction with the accompanying drawings and detailed description, to the following brief description. Here, like reference numerals represent like parts.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5A

Figure 5B

Figure 6

Figure 7

DETAILED DESCRIPTION OF THE INVENTION

[0011] A ccording to various non - limiting embodiments described herein, an orthogonal printed circuit board (PCB) interface for implementation in a dual - polarized PCB array antenna is provided. The orthogonal printed circuit board (PCB) interface overcomes a technical gap including using only a single PCB and facilitates efficient dual - polarization via dual - polarized patches and stacked - patch radiators integrated on corresponding radiator substrates arranged orthogonally to a mating PCB.

[0012] According to at least one non - limiting embodiment, the orthogonal PCB interface provides a highly efficient connection to a radiator substrate arranged in an orthogonal position with respect to the PCB and completes the functions necessary for signal exchange in a phased - array front - end. In addition, the orthogonal PCB interface provides minimum reflection coefficient performance within an operating frequency range compatible with the latest phased arrays and minimizes interference with electronic circuits and / or components (e.g., amplifiers, switches, or hybrid circuits) included in the radiator substrate and the PCB. The orthogonal PCB interface also establishes a structural interface that provides a sufficient thermal boundary and exchange medium between the radiator substrate and the PCB. In this way, the orthogonal PCB interface can withstand the latest manufacturing processes and the expected stresses during the operation, transportation, and storage of phased arrays.

[0013] Next, referring to FIG. 1, a dual-polarization PCB array antenna 100 according to a non-limiting embodiment is illustrated. The dual-polarization PCB array antenna 100 includes a plurality of individual PCBs 102 and a radiating antenna array 104. The PCBs 102 are arranged side by side along a first axis (e.g., the X-axis) and separated from each other by a gap 106. Each PCB 102 extends along a first axis (e.g., the X-axis) that defines a PCB width (Wst), a second axis (e.g., the Y-axis) that is orthogonal to the first axis and defines a PCB height (Hst), and a third axis (e.g., the Z-axis) that is orthogonal to the X-axis and the Y-axis and defines a PCB length (Lst). The PCBs 102 can be formed from various materials that provide a dielectric constant (k) in the range of, for example, about 2.0 to about 6, a dielectric tangent (tanδ) in the range of, for example, about 0.0005 to about 0.03, and a coefficient of thermal expansion (CTE) in the range of, for example, about 10 ppm / °C to about 220 ppm / °C. In one or more embodiments, the PCBs 102 can be fabricated as printed circuit boards (PCBs) that include various circuits, traces, and / or electrical components.

[0014] Each PCB 102 has a PCB mounting surface 108 that extends from a first PCB end (e.g., the upper end) to an opposing second PCB end (e.g., the lower end) along the Y-axis and from a third PCB end (e.g., the left end) to a fourth PCB end (e.g., the right end) along the Z-axis. The PCB mounting surface 108 includes a plurality of trace groups 109 arranged side by side along the Z-axis. The trace groups 109 serve to facilitate the interface between a given PCB 102 and the radiating antenna array 104, as will be described in detail later.

[0015] The radiating antenna array 104 is disposed at a first PCB end portion of a plurality of PCBs 102 and is arranged orthogonally to the PCB mounting surface 108. The radiating antenna array 104 includes a plurality of individual radiator substrates 110 arranged side by side along the X-axis. In one or more embodiments, the radiator substrate 110 can be fabricated as a printed circuit board (PCB) including various circuits, traces, and / or electrical components.

[0016] Each radiator substrate 110 is disposed at a first end portion of a corresponding PCB 102, extends along a first axis (e.g., the X-axis) to define a substrate width (Ws), extends along a second axis (e.g., the Y-axis) orthogonal to the first axis to define a substrate height (Hs), and extends along a third axis (e.g., the Z-axis) orthogonal to the X-axis and the Y-axis to define a substrate length (Ls). The radiator substrate 110 can be formed from various materials providing, for example, a dielectric constant (k) in the range of about 1 to about 4, a dielectric tangent (tanδ) in the range of about 0.0005 to about 0.03, and a coefficient of thermal expansion (CTE) in the range of about 10 ppm / °C to about 220 ppm / °C. In one or more embodiments, the radiator substrate 110 can be fabricated as a printed circuit board (PCB) including various circuits, traces, and / or electrical components.

[0017] Each radiator substrate 110 has a patch mounting surface 112 extending from a first substrate end portion to an opposing second substrate end portion along the X-axis and an opposing contact surface 114 extending from a third substrate end portion to an opposing fourth substrate end portion along the Z-axis. Thus, the contact surface 114 is disposed directly against a first end portion of a corresponding PCB 102 such that the patch mounting surface 112 is arranged orthogonally to the PCB mounting surface 108. In one or more non-limiting embodiments, the first and second end portions of the radiator substrate 110 are in direct contact with each other.

[0018] Each radiator substrate 110 is disposed on the patch mounting surface 112 and includes a plurality of radiating antenna elements 116 arranged side by side along the Z-axis. Hereinafter, the radiating antenna element 116 will be described as the patch antenna 116, but other types of radiating antenna elements 116 can be mounted without departing from the scope of the present invention.

[0019] Referring to FIG. 2, the PCB 102 and the radiator substrate 110 included in the dual-polarization PCB array antenna 100 will be illustrated in more detail. The PCB 102 is illustrated together with a trace group 109 including a plurality of conductive traces 111 formed on the PCB mounting surface 108. The trace 111 includes a conductive material (for example, copper) and can be formed on the PCB mounting surface 108 using various manufacturing processes such as, for example, a printed circuit board (PCB) etching process, additive manufacturing (for example, three-dimensional printing). Although five traces 111 are shown, of course, the trace group 109 can include more or fewer traces 111 without departing from the scope of the present invention.

[0020] Further referring to FIG. 2 and further referring to FIGS. 3 and 4, the radiator substrate 110 has a plurality of via hole groups 118 arranged side by side along the Z-axis (see FIG. 4). Each via hole group 118 is placed between a given patch antenna 116 and the first end 119 of the patch mounting surface 112. Each via hole group 118 is formed in the radiator substrate 110 and includes a plurality of via holes 120 that extend completely through from the patch mounting surface 112 to the contact surface 114. Each via hole 120 is aligned with a corresponding trace 111 (for example, shown in FIG. 2) along the Y-axis.

[0021] The through-holes 120 are configured to receive conductive pins 122 arranged in an array along the Z-axis to provide a plurality of pin groups 124. The pins 122 are formed of a conductive material such as copper, for example, and function as terminals. Each conductive pin 122 extends from a mounting end 126 to an opposing contact end 128 and is disposed within a corresponding through-hole 120 (see FIG. 3). Thus, as shown in FIG. 2, the mounting end 126 abuts against the patch mounting surface 112, and the contact end 128 contacts the aligned trace 111. In one or more non-limiting embodiments, the radiator substrate 110 can include one or more substrate traces (not shown) that connect a given patch antenna 116 to the pins 122 included in adjacent pin groups 124. In this way, a signal (e.g., an RF signal) applied to the traces 111 of a given trace group 109 on the PCB 102 can be sent to the patch antenna 116 on the radiator substrate 110 via the pins 122 aligned therewith. Although five pins 122 are shown, more or fewer pins 122 can be included based on the number of traces 111 formed on the PCB mounting surface 108.

[0022] Referring again to FIG. 2, the assembly of the PCB 102, the traces 111, the radiator substrate 110, and the pins 122 establishes an orthogonal PCB interface 200. As described herein, the orthogonal PCB interface 200 arranges the patch mounting surface 112 of the radiator substrate 110 in an orthogonal position with respect to the PCB mounting surface 108 of the PCB 102. This orthogonal arrangement enables the integration of a dual-polarization patch antenna or a stacked patch radiator with the PCB 102 to enable a dual-polarization PCB array antenna 100. In addition, the electrical connection established by the traces 111 and the pins 122 can facilitate a shielded channel interface between the PCB 102 and the patch antenna 116, as will be described in detail later.

[0023] Also, the connection between pin 122 and trace 111 facilitates the transmission and / or reception of dual-polarization RF signals without the need to implement a large and bulky right-angle connector. Figures 5A and 5B illustrate an example of establishing a pin / trace connection. Pin 122 can be aligned above trace 111, for example, using a pick-and-place device, as understood by those skilled in the art. Once aligned, the radiator substrate 110 can be positioned relative to the PCB 102 such that the contact surface 114 abuts the first end 119 of the PCB 102 and the pin 122 contacts the trace 111 (see Figure 5A) (as indicated by the wavy arrow). Then, a conductive filler 130, such as solder, can be deposited on the PCB mounting surface 108 to form a conductive node between the contact end 128 of the pin 122 and the trace 111. (See Figure 5B). Although the conductive filler 130 covers a portion of the pin contact end 128 in the illustration, it can of course be deposited to cover the entire contact end 128.

[0024] Referring to Figure 6, a shielded channel interface 300 provided by the dual-polarization PCB array antenna 100 is shown according to a non-limiting embodiment. As described herein, the dual-polarization PCB array antenna 100 includes one or more PCBs 102 arranged orthogonally to the radiator substrate 110 via an orthogonal PCB interface 200. Although a single PCB 102 and a single radiator substrate 110 are illustrated, additional PCBs 102 and additional substrates 110 can of course be implemented without departing from the scope of the present invention.

[0025] According to the non-limiting embodiment shown in FIG. 6, the PCB 102 includes a first plurality of conductive elements 111a, 111b, and 111c. In one or more non-limiting embodiments, the first plurality of conductive elements includes a first conductive trace 111a, a second conductive trace 111b, and a third conductive trace 111c. In at least one non-limiting embodiment, one or more of the conductive traces 111a-111c are formed on the PCB mounting surface 108 and extend from a first PCB end to a second PCB end. The first trace 111a can be connected to the first port 302, the trace 111b can be connected to the second port 304, and the third conductive trace 111c can be connected to the ground plane using a via (not shown) embedded within the PCB 102. The first and second ports 302 and 304 are shown located at the second PCB end in the illustration, but the locations of the first and second ports 302 and 304 are not limited thereto and may be mounted at different locations.

[0026] The radiator substrate 110 includes a second plurality of conductive elements 122a, 122b, 122c, 122d, and 122e (collectively referred to as 122a-122e). In at least one non-limiting embodiment, the conductive elements 122a-122e can be formed as conductive pins as described herein and function as a plurality of terminals to facilitate the shielded channel interface 300. In at least one non-limiting embodiment, the conductive elements 122a-122e extend perpendicular to the patch mounting surface 112 of the radiator substrate 110. Thus, the second conductive elements (e.g., pins 122a-122e) can contact the corresponding first conductive elements (e.g., traces 111a-111c).

[0027] As shown in FIG. 6, for example, terminal 122b can be connected to the first trace 111a, while terminal 122d can be connected to the second trace 111b. Terminals 122a, 122c, and 122e can be connected to vias (not shown) embedded within the PCB 102 and shorted to the ground plane. Thus, while RF signals are applied to terminals 122b and 122d and transmitted to the first and second terminals 111a and 111b respectively, a ground signal ground (GSG) shielded channel interface 300 is established that enables maintaining the ground potential between both the PCB 102 and the radiator substrate 110 across the entire system. Of course, terminals 122a - 122e are not limited to the GSG configuration, and other terminal configurations that can establish the shielded channel interface 300 can be used without departing from the scope of the present disclosure.

[0028] According to the non - limiting embodiment shown in FIG. 7, the shielded channel interface 300 can be established by using the inner terminals 122b, 122c, and 122d without using the outermost terminals 122a and 122e. In this example, terminal 122c can function as a ground terminal placed (i.e., sandwiched) between the first and second RF terminals 122b and 122d. Thus, an RF signal ground signal (SGS) shielded channel interface 3000 is established that facilitates the signal interface between the PCB 102 and the radiator substrate 110. Although the SGS shielded channel interface 300 is described, the configuration is not limited thereto. For example, by using terminal 122c as an RF terminal placed (i.e., sandwiched) between the first and second ground terminals 122b and 122d, a ground signal ground (GSG) shielded channel interface 300 can be established without departing from the scope of the present disclosure.

[0029] As described herein, various non-limiting embodiments provide an orthogonal interface for implementation in a dual-polarization PCB array antenna. The orthogonal interface overcomes the need to implement a twin PCB, while promoting efficient dual polarization through dual-polarization patches and stacked-patch radiators integrated on one or more PCBs.

[0030] All structural, material, acts, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or act for performing their functions in combination with other claimed elements as specifically claimed. The description of the invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The selection and description of embodiments are made to best explain the principles of the disclosure and its practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.

[0031] Although preferred embodiments of the disclosure have been described, it should be understood that those of ordinary skill in the art can make various improvements and enhancements that are included in the following claims, both now and in the future. These claims should be construed to maintain appropriate protection for the originally described disclosure.

Description of Reference Numerals

[0032] 102 PCB 110 Radiator Substrate 112 Patch Mounting Surface 114 Contact Surface 116 Radiating Antenna Element 122 Conductive Pin 124 Pin Group 200 Orthogonal PCB Interface

Claims

1. A dual-polarization PCB array antenna, comprising: a plurality of PCBs, each PCB extending along a first axis defining a PCB width, a second axis orthogonal to the first axis defining a PCB height, and a third axis orthogonal to the first axis and the second axis defining a PCB length, each PCB having a PCB mounting surface extending along the second axis from a first PCB end to an opposing second PCB end and along the third axis from a third PCB end to a fourth PCB end; the plurality of PCBs; a radiating antenna array including a plurality of radiator substrates, each radiator substrate having a patch mounting surface extending along the first axis from a first substrate end to an opposing second substrate end and along the third axis from a third substrate end to an opposing fourth substrate end; the radiating antenna array; a plurality of orthogonal interfaces configured to arrange the patch mounting surface of a given radiator substrate among the plurality of radiator substrates in an orthogonal position relative to the PCB mounting surface of a given PCB among the plurality of PCBs; the plurality of orthogonal interfaces; and wherein a given orthogonal interface among the plurality of orthogonal interfaces includes a plurality of conductive traces formed on the given PCB mounting surface and a plurality of conductive pins extending through the patch mounting surface and contacting the conductive traces. A dual-polarization PCB array antenna.

2. The dual-polarization PCB array antenna according to claim 1, wherein the radiating antenna array includes a plurality of radiating antenna elements disposed on the patch mounting surface.

3. The dual-polarization PCB array antenna according to claim 2, wherein each radiator substrate is disposed at the first PCB end of a corresponding PCB.

4. The dual-polarization PCB array antenna according to claim 1, wherein the contact between the plurality of conductive traces and the plurality of conductive pins establishes a shielded channel interface.

5. The dual-polarization PCB array antenna according to claim 4, wherein the shielded channel interface includes a ground signal grounding configuration.

6. The dual-polarization PCB array antenna according to claim 4, wherein the shielded channel interface includes a signal grounding signal configuration.

7. A orthogonal printed circuit board (PCB) interface included in a dual-polarization array antenna, wherein the orthogonal PCB interface includes a PCB including a PCB mounting surface including a first plurality of conductive elements, and a radiator substrate including a patch mounting surface including a second plurality of conductive elements, wherein the second plurality of conductive elements are coupled to the first plurality of conductive elements such that the patch mounting surface of the radiator substrate is arranged in an orthogonal position with respect to the PCB mounting surface of the PCB, the first plurality of conductive elements include a plurality of conductive traces formed on the PCB mounting surface, and the second plurality of conductive elements include a plurality of conductive pins extending through the patch mounting surface and contacting the conductive traces, the orthogonal PCB interface.

8. The PCB extends along a first axis defining a PCB width, a second axis orthogonal to the first axis defining a PCB height, and a third axis orthogonal to the first axis and the second axis defining a PCB length, the PCB mounting surface extends along the second axis from a first PCB end to an opposing second PCB end, and extends along the third axis from a third PCB end to a fourth PCB end, the orthogonal PCB interface according to claim 7.

9. The patch mounting surface extends along the first axis from a first substrate end to an opposing second substrate end, and extends along the third axis from a third substrate end to an opposing fourth substrate end, the orthogonal PCB interface according to claim 8.

10. The radiator substrate is disposed at the first PCB end of the PCB, the orthogonal PCB interface according to claim 9.

11. The dual-polarization array antenna includes a plurality of radiating antenna elements disposed on the patch mounting surface, the orthogonal PCB interface according to claim 10.

12. The contact between the plurality of conductive traces and the plurality of conductive pins establishes a shielded channel interface, the orthogonal PCB interface according to claim 7.

13. The shielded channel interface includes a ground signal ground configuration, the orthogonal PCB interface according to claim 12.

14. The shielded channel interface includes a signal ground signal configuration, the orthogonal PCB interface according to claim 12.

15. A shielded channel interface included in a dual-polarization printed circuit board (PCB) array antenna, wherein the shielded channel interface comprises a plurality of first conductive elements coupled to a PCB mounting surface of the PCB, and a plurality of second conductive elements coupled to a patch mounting surface of a radiator substrate, the plurality of second conductive elements extending perpendicularly from the patch mounting surface to establish electrical connections to the plurality of first conductive elements, at least two first connections among the electrical connections are configured to receive a first signal, at least one second connection among the electrical connections is configured to receive a second signal different from the first signal, and the at least one second connection is disposed between the at least two first connections, the patch mounting surface of the radiator substrate is arranged orthogonally to the PCB mounting surface of the PCB, the shielded channel interface. **Claim 16** The shielded channel interface according to claim 15, wherein the electrical connection establishes a ground signal ground configuration. **Claim 17** The shielded channel interface according to claim 16, wherein the electrical connection establishes a signal ground signal configuration.

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