Display substrate, method for manufacturing the same, and display device

Abstract

A display substrate and its manufacturing method, and a display device, the display substrate includes a driving circuit layer disposed on a base, and a light emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer includes a plurality of circuit units, the light emitting structure layer includes a plurality of light emitting devices, at least one circuit unit includes a first power line, an initial signal line, and a pixel driving circuit, the initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersects with the second direction, and an orthogonal projection of the second initial signal line on the base at least partially overlaps with an orthogonal projection of the first power line on the base.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technologies, and particularly relates to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] Organic Light Emitting Diode (abbreviated as OLED) and Quantum-dot Light Emitting Diodes (abbreviated as QLED) are active light-emitting display devices, and have advantages such as self-luminous, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, bendable, and low cost. With the continuous development of display technologies, flexible displays that use OLED or QLED as light-emitting devices and perform signal control by Thin Film Transistor (abbreviated as TFT) have become the main products in the current display field.

Summary of the Invention

Means for Solving the Problems

[0003] The following is an overview of the subject matter to be described in detail in this specification. This overview does not limit the scope of protection of the claims.

[0004] In one aspect, the present disclosure provides a display substrate, including a drive circuit layer installed on a base, and a light-emitting structure layer installed on a side of the drive circuit layer away from the base. The drive circuit layer includes a plurality of circuit units, the light-emitting structure layer includes a plurality of light-emitting devices, at least one circuit unit includes a first power line, an initial signal line, and a pixel drive circuit. The initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction. The first direction intersects the second direction, and at least a part of the orthographic projection of the second initial signal line on the base overlaps with the orthographic projection of the first power line on the base.

[0005] In an exemplary embodiment, the second initial signal lines in at least one circuit unit include an extending portion and a connecting portion that are connected to each other. The extending portion extends along the second direction, the connecting portion extends along the first direction, and the connecting portion is connected to the first initial signal line via a via.

[0006] In an exemplary embodiment, at least a part of the orthographic projection of the extending portion at its base overlaps with at least a part of the orthographic projection of the first power supply line at its base, and at least a part of the orthographic projection of the connecting portion at its base overlaps with at least a part of the orthographic projection of the first initial signal line at its base.

[0007] In an exemplary embodiment, at least one circuit unit includes a second connection electrode. The connecting portion is connected to the second connection electrode via a via, and the second connection electrode is connected to the first initial signal line via a via.

[0008] In an exemplary embodiment, the second connection electrode is connected via a via to a first area of the active layer of the first transistor and a first area of the active layer of the seventh transistor in the pixel driving circuit.

[0009] In an exemplary embodiment, the driving circuit layer includes a plurality of unit rows and a plurality of unit columns. The unit rows include a plurality of circuit units arranged along the first direction, the unit columns include a plurality of circuit units arranged along the second direction. In at least one unit column, the second initial signal lines in adjacent circuit units are connected to each other, or the second initial signal lines in adjacent circuit units are installed at intervals.

[0010] In an exemplary embodiment, the plurality of circuit units includes a first circuit unit connected to a red light-emitting device that emits a red light beam, a second circuit unit connected to a blue light-emitting device that emits a blue light beam, a third circuit unit connected to a first green light-emitting device that emits a green light beam, and a fourth circuit unit connected to a second green light-emitting device that emits a green light beam. The plurality of unit columns includes a first unit column and a second unit column. The first circuit unit and the second circuit unit in the first unit column are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit column are alternately installed along the second direction. At least a part of the second initial signal lines is installed in the first unit column.

[0011] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are installed. At least a part of a first center line of a front projection at the base of the first pixel opening and a second center line of a front projection at the base of the second initial signal line overlap.

[0012] In an exemplary embodiment, the driving circuit layer further includes data signal lines. At least a part of a third center line of a front projection at the base of the second pixel opening and a fourth center line of a front projection at the base of the data signal lines overlap.

[0013] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are provided. The driving circuit layer further includes a data signal line. A second center line of a front projection of an extension of the second initial signal line at a base and a fourth center line of a front projection of the data signal line at a base are located on both sides of a first center line of a front projection of the first pixel opening at a base.

[0014] In an exemplary embodiment, the second center line of the front projection of the extension of the second initial signal line at the base and the fourth center line of the front projection of the data signal line at the base are symmetrically arranged with respect to the first center line of the front projection of the first pixel opening at the base.

[0015] In an exemplary embodiment, the second center line of the front projection of the extension of the second initial signal line at the base and the fourth center line of the front projection of the data signal line at the base are located on both sides of a third center line of the front projection of the second pixel opening at the base.

[0016] In an exemplary embodiment, the second center line of the front projection of the extension of the second initial signal line at the base and the fourth center line of the front projection of the data signal line at the base are symmetrically arranged with respect to the third center line of the front projection of the second pixel opening at the base.

[0017] In an exemplary embodiment, the plurality of circuit units includes a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light. The plurality of unit columns includes a first unit column and a second unit column. The first circuit unit and the second circuit unit in the first unit column are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit column are alternately installed along the second direction. At least a part of the second initial signal lines are installed in the second unit column.

[0018] In an exemplary embodiment, the light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are installed. At least a part of a fifth center line of a front projection at the base of the third pixel opening and a seventh center line of a front projection at the base of a connection part of the second initial signal line overlap.

[0019] In an exemplary embodiment, at least a part of a sixth center line of a front projection at the base of the fourth pixel opening and a seventh center line of a front projection at the base of a connection part of the second initial signal line overlap.

[0020] In an exemplary embodiment, the plurality of circuit units include a first circuit unit connected to a red light-emitting device that emits a red light beam, a second circuit unit connected to a blue light-emitting device that emits a blue light beam, a third circuit unit connected to a first green light-emitting device that emits a green light beam, and a fourth circuit unit connected to a second green light-emitting device that emits a green light beam. The plurality of unit rows include a first unit row and a second unit row. The first circuit unit and the second circuit unit in the first unit row are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit row are alternately installed along the second direction. The second initial signal line is installed in the first unit row and the second unit row.

[0021] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially installed on a base. The semiconductor layer includes active layers of a plurality of transistors in the pixel driving circuit. The first conductive layer includes scanning signal lines and gate electrodes of a plurality of transistors. The second conductive layer includes the first initial signal line. The third conductive layer includes a first power supply line. The fourth conductive layer includes data signal lines and the second initial signal line.

[0022] In an exemplary embodiment, the third conductive layer further includes a second connection electrode. The second connection electrode is connected to the first initial signal line via a via. The second initial signal line is connected to the second connection electrode via a via.

[0023] In an exemplary embodiment, the second conductive layer further includes a shield electrode. The first power supply line is connected to the shield electrode via a via.

[0024] In an exemplary embodiment, a positive projection of at least a part of the shield electrode on the base is located between a positive projection of the data signal line on the base and a positive projection of a second pole of a first transistor in the pixel driving circuit on the base.

[0025] In another aspect, the present disclosure further provides a display device, which includes the above-mentioned display substrate.

[0026] In another aspect, the present disclosure further provides a method for manufacturing a display substrate. The display substrate includes a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. The driving circuit layer includes a plurality of circuit units, and the light-emitting structure layer includes a plurality of light-emitting devices. At least one circuit unit includes a first power line, an initial signal line, and a pixel driving circuit. The initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction. The first direction intersects the second direction. The manufacturing method includes: forming a first initial signal line extending along the first direction on the base; forming a second initial signal line extending along the second direction, and at least a part of a projection of the second initial signal line on the base overlaps a projection of the first power line on the base.

[0027] After reading and understanding the drawings and the detailed description, other aspects can be understood.

[0028] The drawings are provided for understanding the technical solutions of the present disclosure, are a part of the specification, and are used to interpret the technical solutions of the present disclosure together with the embodiments of the present disclosure, rather than to limit the technical solutions of the present disclosure.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0030] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that the embodiments can be implemented in many different forms. As can be easily understood by those skilled in the art, the methods and contents can be converted into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the descriptions of the following embodiments. In the case of no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0031] The proportions of the drawings in the present disclosure may be used as a reference in the actual process, but are not limited thereto. For example, the ratio of the width to the length of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings either. The drawings described in the present disclosure are only structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

[0032] The ordinal numbers such as "first", "second", and "third" in this specification are for avoiding confusion of components and do not limit in terms of quantity.

[0033] In this specification, for convenience, terms indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positions of the components with reference to the drawings. This is for explaining and simplifying this specification and does not indicate or imply that the described device or element must have a specific orientation and be configured and operated in a specific orientation. Therefore, it is not for limiting the present disclosure. The positional relationship of the components can be appropriately changed according to the direction of explaining each component. Therefore, it is not limited to the terms described in the specification and can be appropriately changed in some cases.

[0034] In this specification, unless there are clear regulations and limitations, the terms "attach", "connect", and "couple" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integrated connection. It may be a mechanical connection or an electrical connection. It may be a direct connection, an indirect connection via a linker, or an internal communication between two elements. A person skilled in the art can understand the specific meaning of the above technical terms in this disclosure according to the specific situation.

[0035] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0036] In this specification, the first pole may be the drain electrode and the second pole may be the source electrode, or the first pole may be the source electrode and the second pole may be the drain electrode. When using transistors with opposite polarities, or when the current direction during operation in a circuit changes, etc., the functions of the "source electrode" and the "drain electrode" may be converted with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be converted with each other, and the "source end" and the "drain end" can be converted with each other.

[0037] In this specification, "electrical connection" includes the case where components are connected through an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements with various other functions.

[0038] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. Also, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0039] In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film". Similarly, an "insulating film" may also be changed to an "insulating layer".

[0040] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strict and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and there may be small deformations due to tolerances, and there may also be lead angles, arc sides, and deformations.

[0041] "About" in this disclosure does not strictly limit the boundary and refers to a case where numerical values within the error range of the process and measurement are tolerated.

[0042] FIG. 1 is a schematic structural diagram of a display device. As shown in FIG. 1, the display device includes a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (D1~Dn) respectively. The scan driver is connected to a plurality of scan signal lines (S1~Sm) respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines (E1~Eo) respectively. The pixel array includes a plurality of sub-pixels Pxij, where i and j are natural numbers. At least one sub-pixel Pxij includes a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit includes at least one scan signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller provides a gray value and a control signal conforming to the data driver's standard to the data driver, provides a clock signal, a scan start signal, etc. conforming to the scan driver's standard to the scan driver, and provides a clock signal, an emission stop signal, etc. conforming to the light-emitting driver's standard to the light-emitting driver. The data driver uses the gray value and the control signal received from the timing controller to generate a data voltage to be provided to the data signal lines D1, D2, D3, …, Dn. For example, the data driver can sample the gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1~Dn in units of pixel rows, where n is a natural number. The scan driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3, …, Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide a scan signal having a turn-on level pulse to the scan signal lines S1~Sm. For example, the scan driver is configured in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of a turn-on level pulse to the next-stage circuit under the control of a clock signal, where m is a natural number.The light-emitting driver can generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, …, Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting driver can sequentially provide emission signals having turn-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver is configured in the form of a shift register, and can generate emission signals by sequentially transmitting an emission stop signal provided in the form of a turn-off level pulse under the control of a clock signal to the circuits of the next stage, where o is a natural number.

[0043] FIG. 2a and FIG. 2b are schematic plan views of a display substrate. In an exemplary embodiment, the display substrate includes a plurality of pixel units P arranged in a matrix manner. At least one pixel unit P includes a first sub-pixel P1 that emits one first color light ray, a second sub-pixel P2 that emits one second color light ray, a third sub-pixel P3 that emits two third color light rays, and a fourth sub-pixel P4. Any of the four sub-pixels may include a circuit unit and a light-emitting device. The circuit unit includes a scanning signal line, a data signal line, a light-emitting signal line, and a pixel driving circuit. The pixel driving circuits are respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted from the data signal line and output a corresponding current to the light-emitting device under the control of the scanning signal line and the light-emitting signal line. The light-emitting devices in each sub-pixel are respectively connected to the pixel driving circuit of the sub-pixel where they are located. The light-emitting device is configured to emit light of a corresponding luminance in response to the current output from the pixel driving circuit of the sub-pixel where it is located.

[0044] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light rays, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light rays, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light rays. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal. In an exemplary embodiment, as shown in FIG. 2a, the four sub-pixels may be arranged in a square manner to form a GGRB pixel array. In other exemplary embodiments, as shown in FIG. 2b, the four sub-pixels may be arranged in a diamond manner to form an RGBG pixel array. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal arrangement or a vertical arrangement or other manners. In an exemplary embodiment, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal arrangement, a vertical arrangement, or a "pin" shape or other manners, and the present disclosure is not limited thereto.

[0045] In an exemplary embodiment, a plurality of sub-pixels sequentially installed in the horizontal direction are called pixel rows, a plurality of sub-pixels sequentially installed in the vertical direction are called pixel columns, and the plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array.

[0046] FIG. 3 is a schematic cross-sectional structure diagram of a display substrate, showing the structures of three sub-pixels of the display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate includes a driving circuit layer 102 installed on a base 101, a light-emitting structure layer 103 installed on a side away from the base of the driving circuit layer 102, and a encapsulation layer 104 installed on a side away from the base of the light-emitting structure layer 103. In some possible implementation forms, the display substrate may include other film layers, such as post spacers, etc., and the present disclosure is not limited thereto.

[0047] In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. The driving circuit layer 102 of each sub-pixel may include a plurality of signal lines and a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and storage capacitors. Only one driving transistor 210 and one storage capacitor 211 are illustrated in FIG. 3. The light-emitting structure layer 103 of each sub-pixel may include a plurality of film layers constituting a light-emitting device, and the plurality of film layers may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 via a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light rays of a corresponding color by driving the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked. The first encapsulation layer 401 and the third encapsulation layer 403 may employ an inorganic material, and the second encapsulation layer 402 may employ an organic material. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 and can prevent external water vapor from entering the light-emitting structure layer 103.

[0048] In an exemplary embodiment, the organic light-emitting layer 303 may include a hole injection layer (abbreviated as Hole Injection Layer, HIL), a hole transport layer (abbreviated as Hole Transport Layer, HTL), an electron blocking layer (abbreviated as Electron Block Layer, EBL), a light-emitting layer (abbreviated as Emitting Layer, EML), a hole blocking layer (abbreviated as Hole Block Layer, HBL), an electron transport layer (abbreviated as Electron Transport Layer, ETL), and an electron injection layer (abbreviated as Electron Injection Layer, EIL) that are stacked. In an exemplary embodiment, the hole injection layers and electron injection layers of all sub-pixels may be a common layer that is integrally connected. The hole transport layers and electron transport layers of all sub-pixels may be a common layer that is integrally connected. The hole blocking layers of all sub-pixels may be a common layer that is integrally connected. The light-emitting layers and electron blocking layers of adjacent sub-pixels may slightly overlap or may be isolated.

[0049] In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG. 4 is an equivalent circuit schematic diagram of the pixel driving circuit. As shown in FIG. 4, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C, and the pixel driving circuit is respectively connected to seven signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light-emitting signal line E, an initial signal line INIT, a first power supply line VDD, and a second power supply line VSS).

[0050] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, respectively. The second node N2 is connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively.

[0051] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0052] The control pole of the first transistor T1 is connected to the second scanning signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor is connected to the second node N2. When a turn-on level scanning signal is applied to the second scanning signal line S2, the first transistor T1 transmits an initial voltage to the control pole of the third transistor T3 to initialize the charge amount of the control pole of the third transistor T3.

[0053] The control pole of the second transistor T2 is connected to the first scanning signal line S1, the first pole of the second transistor T2 is connected to the second node N2, and the second pole of the second transistor T2 is connected to the third node N3. When a turn-on level scanning signal is applied to the first scanning signal line S1, the second transistor T2 connects the control pole of the third transistor T3 to the second pole.

[0054] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be referred to as a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and its first electrode.

[0055] The control electrode of the fourth transistor T4 is connected to the first scanning signal line S1. The first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be referred to as a switch transistor, a scan transistor, or the like. When a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0056] The control electrode of the fifth transistor T5 is connected to the light emission signal line E. The first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emission signal line E. The first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When a turn-on level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0057] The control terminal of the seventh transistor T7 is connected to the first scanning signal line S1, the first terminal of the seventh transistor T7 is connected to the initial signal line INIT, and the second terminal of the seventh transistor T7 is connected to the first terminal of the light-emitting device. When a turn-on level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 transmits an initial voltage to the first terminal of the light-emitting device to initialize the amount of charge accumulated at the first terminal of the light-emitting device or to discharge the amount of charge accumulated at the first terminal of the light-emitting device.

[0058] In an exemplary embodiment, the light-emitting device may be an OLED and includes a first terminal (anode) disposed in a stacked manner, an organic light-emitting layer, and a second terminal (cathode). Alternatively, the light-emitting device may be a QLED and includes a first terminal (anode) disposed in a stacked manner, a quantum dot light-emitting layer, and a second terminal (cathode).

[0059] In an exemplary embodiment, the second terminal of the light-emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal, and the signal of the first power supply line VDD is a continuously provided high-level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n - 1). The second scanning signal line S2 of the display row and the first scanning signal line S1 in the pixel driving circuit of the previous display row are the same signal line, and the signal lines of the display panel can be reduced to realize a narrow frame of the display panel.

[0060] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. By adopting the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield of the product can be improved. In some possible embodiments, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0061] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin-film transistor, or an oxide thin-film transistor, or both a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor. The active layer of the low-temperature polysilicon thin-film transistor employs low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor employs an oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. By integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on one display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized to achieve low-frequency driving, reduce power consumption, and improve display quality.

[0062] FIG. 5 is an operation timing diagram of the pixel driving circuit. Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the working process of the pixel driving circuit illustrated in FIG. 4. The pixel driving circuit in FIG. 4 includes seven transistors (the first transistor T1 to The seventh transistor T7 ), one storage capacitor C, and seven signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emission signal line E, initial signal line INIT, first power supply line VDD, and second power supply line VSS). All seven transistors are P-type transistors.

[0063] In an exemplary embodiment, taking an OLED as an example, the working process of the pixel driving circuit may include the following first stage A1, second stage A2, and third stage A3.

[0064] The first stage A1 is called a reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. Since the signal of the second scanning signal line S2 is a low-level signal, the first transistor T1 is turned on, the signal of the initial signal line INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. Since the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0065] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low-level signal, the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second terminal of the storage capacitor C is at a low level, the third transistor T3 is turned on. Due to the signal of the first scanning signal line S1 being a low-level signal, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on. When the second transistor T2 and the fourth transistor T4 are turned on, the data voltage output from the data signal line D is provided to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is stored in the storage capacitor C. The voltage of the second terminal (the second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output from the data signal line D and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing the pre-stored voltage inside it, completing the initialization, and ensuring that the OLED does not emit light. Due to the signal of the second scanning signal line S2 being a high-level signal, the first transistor T1 is turned off. Due to the signal of the light-emitting signal line E being a high-level signal, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0066] The third stage A3 is called the light-emitting stage. The signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. Due to the signal of the light-emitting signal line E being a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the light emission of the OLED.

[0067] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is given by the following equation.

[0068] I = K * (Vgs - Vth) 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * [(Vdd - Vd 2

[0069] In the formula, I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power supply line VDD.

[0070] FIG. 6a is a schematic structural diagram of a driving circuit layer according to an exemplary embodiment of the present disclosure, showing a planar structure of eight circuit units (two unit rows and four unit columns). As shown in FIG. 6a, in a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units. The plurality of circuit units sequentially arranged along the first direction X are referred to as unit rows, and the plurality of circuit units sequentially arranged along the second direction Y are referred to as unit columns. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X and the second direction Y intersect.

[0071] In an exemplary embodiment, at least one circuit unit may include a first power supply line, an initial signal line, and a pixel driving circuit connected to the first power supply line and the initial signal line. The pixel driving circuit may include a plurality of transistors and a storage capacitor. In an exemplary embodiment, the first power supply line may be installed as a signal line for receiving a power supply signal, and the initial signal line may be set to initialize (reset) the storage capacitor.

[0072] In an exemplary embodiment, the initial signal lines of at least one circuit unit include a first initial signal line 31 extending along the first direction X of the main body portion and a second initial signal line 52 extending along the second direction Y of the main body portion, and the first initial signal line 31 and the second initial signal line 52 are connected via vias. In the present disclosure, for A to extend along direction B means that A includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment or an elongated object, the main portion extends along direction B, and the length that the main portion extends along direction B is greater than the length that the secondary portion extends along other directions.

[0073] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 52 may include an extension portion 521 and a connection portion 522 connected to each other. The main body portion of the extension portion 521 extends along the second direction Y, and the main body portion of the connection portion 522 extends along the first direction X. In an exemplary embodiment, the end portion of the connection portion 522 on the side away from the extension portion 521 may be connected to the first initial signal line 31 via a via.

[0074] In an exemplary embodiment, the orthographic projection of at least a part of the connection portion 522 on the base is located within the range of the orthographic projection of the first initial signal line 31 on the base.

[0075] In an exemplary embodiment, the orthographic projection of at least a part of the extension portion 521 on the base is located within the range of the orthographic projection of the first power line 41 on the base.

[0076] FIG. 6b is a schematic diagram of the initial signal lines in the driving circuit layer according to an exemplary embodiment of the present disclosure. As shown in FIG. 6b, the driving circuit layer may include a plurality of unit rows and a plurality of unit columns. The first initial signal line 31 may be installed in each unit row, and the second initial signal line 52 may be installed in the unit columns with intervals, that is, at least one unit column may be arranged between two adjacent second initial signal lines 52 in the first direction X. In an exemplary embodiment, the direction of the unit row may be the first direction X, and the direction of the unit column may be the second direction Y.

[0077] In an exemplary embodiment, the plurality of sub-pixels on the display substrate may include a red sub-pixel R that emits red light, a blue sub-pixel B that emits blue light, a first green sub-pixel G1 that emits green light, and a second green sub-pixel G2 that emits green light. The red sub-pixel R may include a red light-emitting device that emits red light and a first circuit unit Q1 connected to the red light-emitting device. The blue sub-pixel B may include a blue light-emitting device that emits blue light and a second circuit unit Q2 connected to the blue light-emitting device. The first green sub-pixel G1 may include a first green light-emitting device that emits green light and a third circuit unit Q3 connected to the first green light-emitting device. The second green sub-pixel G2 may include a second green light-emitting device that emits green light and a fourth circuit unit Q4 connected to the second green light-emitting device. The first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 constitute one set of circuit units. The four circuit units in at least one set of circuit units may be arranged in a square manner, that is, the four circuit units are arranged in two unit rows and two unit columns. The sub-pixels described in the present disclosure refer to regions divided according to the light-emitting device. The circuit units described in the present disclosure refer to regions divided according to the pixel driving circuit. In an exemplary embodiment, the positions of both the sub-pixels and the circuit units may correspond, or the positions of both the sub-pixels and the circuit units may not correspond.

[0078] In an exemplary embodiment, the plurality of unit columns may include a first unit column and a second unit column. The first unit column refers to a column composed of a plurality of first circuit units Q1 and second circuit units Q2, and the second unit column refers to a column composed of a plurality of third circuit units Q3 and fourth circuit units Q4. The first circuit unit Q1 and the second circuit unit Q2 in the first unit column are alternately installed along the second direction Y, and the third circuit unit Q3 and the fourth circuit unit Q4 in the second unit column are alternately installed along the second direction Y.

[0079] In an exemplary embodiment, the second initial signal line 52 may be disposed in the first unit column. For example, the Nth unit column and the N+2th unit column may be the first unit column, and the N+1th unit column and the N+3th unit column may be the second unit column. Then, the second initial signal line 52 may be disposed in the Nth unit column, the N+2th unit column, the N+4th unit column, …, and the second initial signal line 52 repeats once after leaving one second unit column.

[0080] In another exemplary embodiment, the second initial signal line 52 may be disposed in the second unit column. For example, the Nth unit column and the N+2th unit column may be the first unit column, and the N+1th unit column and the N+3th unit column may be the second unit column. Then, the second initial signal line 52 may be disposed in the N+1th unit column, the N+3th unit column, the N+5th unit column, …, and the second initial signal line 52 repeats once after leaving one first unit column.

[0081] In a further exemplary embodiment, the second initial signal line 52 may be disposed in the first unit column and the second unit column.

[0082] In an exemplary embodiment, the Nth unit column and the N+2th unit column may be the first unit column, and the N+1th unit column and the N+3th unit column may be the second unit column. In the Nth unit column, the circuit unit in the Mth row is the first circuit unit, and the circuit unit in the M+1th row is the second circuit unit. Therefore, the first circuit unit and the second circuit unit in the Nth unit column are alternately disposed along the second direction Y. In the N+2th unit column, the circuit unit in the Mth row is the second circuit unit, and the circuit unit in the M+1th row is the first circuit unit. Therefore, the second circuit unit and the first circuit unit in the N+2th unit column are alternately disposed along the second direction Y.

[0083] In an exemplary embodiment, since the circuit unit at the Nth column of the Mth row and the circuit unit at the (N + 2)th column of the (M + 1)th row are both the first circuit unit, the shape of the second initial signal line in the circuit unit at the Nth column of the Mth row may be the same as the shape of the second initial signal line in the circuit unit at the (N + 2)th column of the (M + 1)th row. Since the circuit unit at the Nth column of the (M + 1)th row and the circuit unit at the (N + 2)th column of the Mth row are both the second circuit unit, the shape of the second initial signal line in the circuit unit at the Nth column of the (M + 1)th row may be the same as the shape of the second initial signal line in the circuit unit at the (N + 2)th column of the Mth row.

[0084] In an exemplary embodiment, in the circuit unit at the Nth column of the Mth row and the circuit unit at the (N + 2)th column of the (M + 1)th row, the extending portion 521 may include a first initial portion, a second initial portion, and a third initial portion that are sequentially connected. The first initial portion and the third initial portion may be parallel to the second direction Y, the second initial portion and the second direction Y may have a first included angle, and the first included angle may be greater than 0° and less than 90°. In an exemplary embodiment, the end of the first initial portion and / or the third initial portion may be connected to the connecting portion 522.

[0085] In an exemplary embodiment, in the circuit unit at the (N + 2)th column of the Mth row and the circuit unit at the Nth column of the (M + 1)th row, the extending portion 521 may include a fourth initial portion, a fifth initial portion, a sixth initial portion, a seventh initial portion, and an eighth initial portion that are sequentially connected. The fourth initial portion, the sixth initial portion, and the eighth initial portion may be parallel to the second direction Y, the fifth initial portion and the second direction Y may have a first included angle, and the seventh initial portion and the second direction Y may have a second included angle. The first included angle may be greater than 0° and less than 90°. The second included angle may be greater than 0° and less than 90°. In an exemplary embodiment, the extending direction of the fifth initial portion and the extending direction of the seventh initial portion may be mirror-symmetrical with respect to the first direction X.

[0086] In some possible exemplary embodiments, the second initial signal line 52 may be disposed in the spaced-apart first unit column or second unit column, that is, three unit columns are disposed between two adjacent second initial signal lines 52 in the first direction X. For example, the second initial signal line 52 may be disposed in the Nth unit column, the N+4th unit column, the N+8th unit column,.... The second initial signal line 52 repeats once by arranging one first unit column and two second unit columns. Alternatively, the second initial signal line 52 may be disposed in the N+1th unit column, the N+5th unit column, the N+9th unit column,.... The second initial signal line 52 repeats once by arranging two first unit columns and one second unit column. In an exemplary embodiment, the number of unit columns disposed between adjacent second initial signal lines 52 is not particularly limited and may be set according to requirements, and the present disclosure does not limit it thereto.

[0087] In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer may include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base. The semiconductor layer may include active layers of a plurality of transistors. The first conductive layer may include scanning signal lines and gate electrodes of a plurality of transistors. The second conductive layer may include the first initial signal line 31. The third conductive layer may include a first power line and first and second poles of a plurality of transistors. The fourth conductive layer may include data signal lines and second initial signal lines 52.

[0088] In an exemplary embodiment, the third conductive layer may further include a second connection electrode 44. The second connection electrode 44 located in the third conductive layer may be connected to the first initial signal line 31 located in the second conductive layer through a via. The second initial signal line 52 located in the fourth conductive layer may be connected to the second connection electrode 44 located in the third conductive layer through a via. In the present disclosure, the second connection electrode may also be referred to as an initial connection electrode.

[0089] In an exemplary embodiment, the second connection electrode 44 is connected through a via to the first area of the active layer of the first transistor and the first area of the active layer of the seventh transistor in the pixel driving circuit.

[0090] In an exemplary embodiment, the second conductive layer may further include a shield electrode, and the first power line is connected to the shield electrode via a via. The orthographic projection of at least a part of the region of the shield electrode on the base is located between the orthographic projection of the data signal line on the base and the orthographic projection of the second pole of the first transistor in the pixel driving circuit on the base.

[0091] In an exemplary embodiment, the driving circuit layer may further include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, and a storage capacitor. The storage capacitor may include a first electrode plate and a second electrode plate, the plurality of transistors may include a first transistor to a seventh transistor, and the third transistor is a driving transistor.

[0092] In an exemplary embodiment, the first conductive layer may include a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, a first electrode plate of the storage capacitor, and gate electrodes of a plurality of transistors. The second conductive layer may include a first initial signal line 31, a second electrode plate of the storage capacitor, a shield electrode, and an electrode plate connection line. The third conductive layer may include a first power line 41, a data connection electrode, a first connection electrode, a second connection electrode 44, a third connection electrode, and a fourth connection electrode. The fourth conductive layer may include a data signal line 51, a second initial signal line 52, and an anode connection electrode.

[0093] In an exemplary embodiment, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a fifth insulating layer. The first insulating layer is disposed between the base and the semiconductor layer, the second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and the fifth insulating layer is disposed between the third conductive layer and the fourth conductive layer.

[0094] Hereinafter, the manufacturing process of the display substrate will be exemplarily described. The "patterning process" described in the present disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as organic material coating, mask exposure, and development for organic materials. Deposition may employ any one or more of sputtering, evaporation, and chemical vapor deposition. Coating may employ any one or more of spray coating, spin coating, and inkjet printing. Etching may employ any one or more of dry etching and wet etching. The present disclosure is not limited thereto. The "thin film" refers to a single-layer thin film fabricated by deposition, coating, or other processes on a base using a certain material. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" is also referred to as a "layer". If the "thin film" requires a patterning process throughout the manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The statement that "A and B are installed in the same layer" described in the present disclosure means that A and B are simultaneously formed by the same patterning process. The "thickness" of the film layer is the size in the direction perpendicular to the display substrate of the film layer. In the exemplary embodiments of the present disclosure, the statement that "the orthographic projection of B is located within the range of the orthographic projection of A", or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0095] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the manufacturing process of the driving circuit layer may include the following operations.

[0096] (1) A semiconductor layer pattern is formed. In an exemplary embodiment, as shown in FIG. 7, the formation of the semiconductor layer pattern includes sequentially depositing a first insulating thin film and a semiconductor thin film on a base, and patterning the semiconductor thin film by a patterning process to form a first insulating layer covering the base and a semiconductor layer disposed on the first insulating layer.

[0097] In an exemplary embodiment, the semiconductor layer of each circuit unit includes the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the seventh active layer 17 may be an integrated structure connected to each other. The sixth active layer 16 of the circuit unit in the Mth row and the seventh active layer 17 of the circuit unit in the (M + 1)th row in each unit column are connected to each other, that is, the semiconductor layers of adjacent circuit units in each unit column are an integrated structure connected to each other.

[0098] In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 in the circuit unit in the Mth row are located on the side away from the circuit unit in the (M + 1)th row of the third active layer 13 of the circuit unit. The first active layer 11 and the seventh active layer 17 are located on the side away from the third active layer 13 of the second active layer 12 and the fourth active layer 14. The fifth active layer 15 and the sixth active layer 16 in the circuit unit in the Mth row are located on the side close to the circuit unit in the (M + 1)th row of the third active layer 13.

[0099] In an exemplary embodiment, the shape of the first active layer 11 may be an "n" shape, the shape of the second active layer 12 may be a "7" shape, the shape of the third active layer 13 may be a "ji" shape, the shape of the fourth active layer 14 may be a "1" shape, and the shapes of the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be an "L" shape.

[0100] In an exemplary embodiment, the active layer of each transistor may include a first area, a second area, and a channel area located between the first area and the second area. In an exemplary embodiment, the first area 11-1 of the first active layer 11 is also the first area 17-1 of the seventh active layer 17, the second area 11-2 of the first active layer 11 is also the first area 12-1 of the second active layer 12, the first area 13-1 of the third active layer 13 is also the second area 14-2 of the fourth active layer 14 and the second area 15-2 of the fifth active layer 15, the second area 13-2 of the third active layer 13 is also the second area 12-2 of the second active layer 12 and the first area 16-1 of the sixth active layer 16, and the second area 16-2 of the sixth active layer 16 is also the second area 17-2 of the seventh active layer 17. In an exemplary embodiment, the first area 14-1 of the fourth active layer 14 and the first area 15-1 of the fifth active layer 15 are separately provided.

[0101] (2) Form a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 8a and 8b, FIG. 8b is a plan schematic view of the first conductive layer in FIG. 8a. The formation of the first conductive layer pattern may include sequentially depositing a second insulating thin film and a first conductive thin film on the base on which the pattern is formed, and patterning the first conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern includes at least a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, and a first electrode plate 24. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0102] As shown in FIGS. 7 to 8b, the main portions of the first scanning signal line 21, the second scanning signal line 22, and the light emission control line 23 extend along the first direction X. The first scanning signal line 21 and the second scanning signal line 22 in the circuit unit of the Mth row are located on the side away from the circuit unit of the (M + 1)th row of the first electrode plate 24 of the circuit unit. The second scanning signal line 22 is located on the side away from the first electrode plate 24 of the first scanning signal line 21 of the circuit unit. The light emission control line 23 may be located on the side close to the circuit unit of the (M + 1)th row of the first electrode plate 24 of the circuit unit.

[0103] In an exemplary embodiment, the first electrode plate 24 is rectangular, and chamfers may be provided at the corners of the rectangle. There is an overlapping area between the orthographic projection of the first electrode plate 24 at the base and the orthographic projection of the third active layer of the third transistor T3 at the base. In an exemplary embodiment, the first electrode plate 24 may also serve as one electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0104] In an exemplary embodiment, the overlapping area between the first scanning signal line 21 and the second active layer 12 serves as the gate electrode of the second transistor T2. A gate electrode block 21-1 protruding toward the second scanning signal line 22 side is provided on the first scanning signal line 21. There is an overlapping area between the orthographic projection of the gate electrode block 21-1 at the base and the orthographic projection of the second active layer 12 at the base, forming the second transistor T2 with a double-gate structure. The overlapping area between the first scanning signal line 21 and the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The overlapping area between the second scanning signal line 22 and the first active layer 11 serves as the gate electrode of the first transistor T1 with a double-gate structure. The overlapping area between the second scanning signal line 22 and the seventh active layer 17 serves as the gate electrode of the seventh transistor T7. The overlapping area between the light emission control line 23 and the fifth active layer 15 serves as the gate electrode of the fifth transistor T5. The overlapping area between the light emission control line 23 and the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.

[0105] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer is used as a mask to conductify the semiconductor layer. Channel regions of the first transistor T1 to the seventh transistor T7 are formed in the semiconductor layer in the area blocked by the first conductive layer. The semiconductor layer in the area not blocked by the first conductive layer is conductified, that is, both the first area and the second area of the first active layer to the seventh active layer are conductified.

[0106] (3) Form the second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 9a and 9b, FIG. 9b is a plan schematic view of the second conductive layer in FIG. 9a. The formation of the second conductive layer pattern includes sequentially depositing a third insulating thin film and a second conductive thin film on the base on which the pattern is formed, and patterning the second conductive thin film by a patterning process to form a third insulating layer covering the first conductive layer and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern includes at least a first initial signal line 31, a second electrode plate 32, a shield electrode 33, and an electrode plate connection line 35. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0107] As shown in FIGS. 7 to 9b, the main part of the first initial signal line 31 extends along the first direction X. The first initial signal line 31 in the circuit unit of the Mth row is located on the side away from the circuit unit of the (M + 1)th row of the second scanning signal line 22 of the circuit unit. The second electrode plate 32 serves as the other electrode plate of the storage capacitor and is located between the first scanning signal line 21 and the light emission control line 23 of the circuit unit. The shield electrode 33 is located between the second scanning signal line 22 and the first scanning signal line 21 (excluding the main part of the gate electrode block 21-1) of the circuit unit. The shield electrode 33 is set to block the influence on important nodes due to data voltage jumps, avoid the influence on the potential of important nodes of the pixel driving circuit due to data voltage jumps, and improve the display effect.

[0108] In an exemplary embodiment, the contour of the second electrode plate 32 is rectangular, and chamfers may be provided at the corners of the rectangle. There is an overlapping area between the orthographic projection of the second electrode plate 32 on the base and the orthographic projection of the first electrode plate 24 on the base. The first electrode plate 24 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit. An opening 34 is provided in the second electrode plate 32, and the opening 34 may be located in the middle of the second electrode plate 32. The opening 34 may be rectangular, whereby the second electrode plate 32 forms an annular structure. The opening 34 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the base includes the orthographic projection of the opening 34 on the base. In an exemplary embodiment, the opening 34 is set to accommodate a first via formed subsequently. The first via is located within the opening 34 to expose the first electrode plate 24. Thereby, the second pole of the first transistor T1 formed subsequently is connected to the first electrode plate 24.

[0109] In an exemplary embodiment, the electrode plate connection line 35 is provided between the second electrode plates 32 of adjacent circuit units in the first direction X or the direction opposite to the first direction X. The first end of the electrode plate connection line 35 is connected to the second electrode plate 32 of the circuit unit. The second end of the electrode plate connection line 35 extends along the first direction X or the direction opposite to the first direction X and is connected to the second electrode plate 32 of the adjacent circuit unit. That is, the electrode plate connection line 35 is set to connect the second electrode plates of adjacent circuit units in one unit row. In an exemplary embodiment, due to the electrode plate connection line 35, the second electrode plates of a plurality of circuit units in one unit row can form an integrated structure connected to each other. The second electrode plate of the integrated structure can be multiplexed as a power signal line. Thereby, a plurality of second electrode plates in one unit row have the same potential, which contributes to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0110] (4) Form a fourth insulating layer pattern. In an exemplary embodiment, as shown in FIGS. 10a and 10b, FIG. 10b is a plan schematic view of a plurality of vias in FIG. 10a, and the formation of the fourth insulating layer pattern includes depositing a fourth insulating thin film on the base on which the pattern is formed and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the second conductive layer. A plurality of vias are provided in each circuit unit, and the plurality of vias include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0111] As shown in FIGS. 7 to 10b, the first via V1 is located within the opening 34 of the second electrode plate 32. The orthographic projection of the base of the first via V1 is located within the range of the orthographic projection of the base of the opening 34. The fourth insulating layer and the third insulating layer within the first via V1 are etched to expose the surface of the first electrode plate 24. The first via V1 is set such that the second pole of the first transistor T1 to be formed subsequently is connected to the first electrode plate 24 through the via.

[0112] In an exemplary embodiment, the second via V2 is located within the range of the orthographic projection of the base of the second electrode plate 32. The orthographic projection of the base of the second via V2 is located within the range of the orthographic projection of the base of the second electrode plate 32. The fourth insulating layer within the second via V2 is etched to expose the surface of the second electrode plate 32. The second via V2 is set such that the first power line to be formed subsequently is connected to the second electrode plate 32 through the via. In an exemplary embodiment, the second via V2 as a power via may include a plurality. The plurality of second vias V2 are sequentially arranged along the second direction Y to improve the connection reliability between the first power line and the second electrode plate 32.

[0113] In an exemplary embodiment, the orthographic projection at the base of the third via V3 is located within the range of the orthographic projection at the base of the fifth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are etched to expose the surface of the first area of the fifth active layer. The third via V3 is set such that a first power line to be formed subsequently is connected to the fifth active layer through the via.

[0114] In an exemplary embodiment, the orthographic projection at the base of the fourth via V4 is located within the range of the orthographic projection at the base of the sixth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched to expose the surface of the second area (which is also the second area of the seventh active layer) of the sixth active layer. The fourth via V4 is set such that the second pole of a sixth transistor T6 to be formed subsequently is connected to the sixth active layer through the via, and the second pole of a seventh transistor T7 to be formed subsequently is connected to the seventh active layer through the via.

[0115] In an exemplary embodiment, the orthographic projection at the base of the fifth via V5 is located within the range of the orthographic projection at the base of the fourth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched to expose the surface of the first area of the fourth active layer. The fifth via V5 is set such that a data signal line to be formed subsequently is connected to the fourth active layer through the via, and the fifth via V5 is referred to as a data write hole.

[0116] In an exemplary embodiment, the orthographic projection at the base of the sixth via V6 is located within the range of the orthographic projection at the base of the second active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched to expose the surface of the first area (which is also the second area of the first active layer) of the second active layer. The sixth via V6 is set such that the second pole of a first transistor T1 to be formed subsequently is connected to the first active layer through the via, and the first pole of a second transistor T2 to be formed subsequently is connected to the second active layer through the via.

[0117] In an exemplary embodiment, the orthographic projection of the base of the seventh via V7 is located within the range of the orthographic projection of the base of the seventh active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched to expose the surface of the first area of the seventh active layer (which is also the first area of the first active layer). The seventh via V7 is set such that the first pole of the seventh transistor T7 to be formed subsequently is connected to the seventh active layer through the via, and the first pole of the first transistor T1 to be formed subsequently is connected to the first active layer through the via.

[0118] In an exemplary embodiment, the orthographic projection of the base of the eighth via V8 is located within the range of the orthographic projection of the base of the shield electrode 33. The fourth insulating layer within the eighth via V8 is etched to expose the surface of the shield electrode 33. The eighth via V8 is set such that the first power line to be formed subsequently is connected to the shield electrode 33 through the via.

[0119] In an exemplary embodiment, the orthographic projection of the base of the ninth via V9 is located within the range of the orthographic projection of the base of the first initial signal line 31. The fourth insulating layer within the ninth via V9 is etched to expose the surface of the first initial signal line 31. The ninth via V9 is set such that the first pole of the seventh transistor T7 to be formed subsequently (which is also the first pole of the first transistor T1) is connected to the first initial signal line 31 through the via.

[0120] (5) Form the third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 11a and 11b, FIG. 11b is a plan schematic view of the third conductive layer in FIG. 11a. The formation of the third conductive layer includes depositing a third conductive thin film on the base where the pattern is formed and patterning the third conductive thin film by a patterning process to form the third conductive layer disposed on the fourth insulating layer. The third conductive layer includes at least a first power line 41, a data connection electrode 42, a first connection electrode 43, a second connection electrode 44, and a third connection electrode 45. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0121] As shown in FIGS. 7 to 11b, the main part of the first power line 41 extends along the second direction Y. The first power line 41 is connected to the second electrode plate 32 via the second via V2, connected to the fifth active layer via the third via V3, and simultaneously connected to the shield electrode 33 via the eighth via V8. Thereby, the shield electrode 33 and the second electrode plate 32 have the same potential as the first power line 41. The shield electrode 33 is connected to the first power line 41, and the base orthographic projection of at least a part of the shield electrode 33 (for example, the protruding part on the right side of the shield electrode 33) is located between the base orthographic projection of the first connection electrode 43 (which is the second pole of the first transistor T1 and the first pole of the second transistor T2, that is, the second node N2) and the base orthographic projection of the subsequently formed data signal line. Therefore, it can effectively block the influence on the important nodes of the pixel driving circuit caused by the data voltage jump, avoid the influence on the potential of the important nodes of the pixel driving circuit caused by the data voltage jump, and improve the display effect.

[0122] In an exemplary embodiment, the base orthographic projection of at least a part of the shield electrode 33 may at least partially overlap with the base orthographic projection of the subsequently formed data signal line. In an exemplary embodiment, the shield electrodes 33 in adjacent circuit units in the first direction X may be connected to each other, thereby reducing the resistance.

[0123] In an exemplary embodiment, the data connection electrode 42 is connected to the first area of the fourth active layer via the fifth via V5, and the data connection electrode 42 is set to be connected to the subsequently formed data signal line.

[0124] In an exemplary embodiment, the first connection electrode 43 extends along the second direction Y. Its first end is connected to the second area of the first active layer (which is also the first area of the second active layer) via the sixth via V6, and its second end is connected to the first electrode plate 24 via the first via V1. Thereby, the first electrode plate 24, the second pole of the first transistor T1, and the first pole of the second transistor T2 have the same potential. In an exemplary embodiment, the first connection electrode 43 may be the second pole of the first transistor T1 and the first pole of the second transistor T2.

[0125] In an exemplary embodiment, the first end of the second connection electrode 44 is connected to the first initial signal line 31 via the ninth via V9, and its second end is connected to the first area of the seventh active layer (which is also the first area of the first active layer) via the seventh via V7. Thereby, the first pole of the seventh transistor T7 and the first pole of the first transistor T1 have the same potential as the first initial signal line 31. In an exemplary embodiment, the second connection electrode 44 may be the first pole of the seventh transistor T7 and the first pole of the first transistor T1. The second connection electrode is set to be connected to a second initial signal line formed subsequently. In the present disclosure, by setting the second connection electrode to be connected to the seventh active layer, the first initial signal line, and the second initial signal line simultaneously, the number of vias and the number of relay electrodes can be reduced, and the wiring space can be saved.

[0126] In an exemplary embodiment, the third connection electrode 45 is connected to the second area of the sixth active layer (which is also the second area of the seventh active layer) via the fourth via V4. Thereby, the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 have the same potential. In an exemplary embodiment, the third connection electrode 45 may be the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7. In an exemplary embodiment, the third connection electrode 45 is set to be connected to an anode connection electrode formed subsequently.

[0127] In an exemplary embodiment, the first power line 41 of at least one circuit unit may be a broken line with unequal widths. Along the second direction Y, the first power line 41 of each circuit unit includes a first power supply part d1, a second power supply part d2, a third power supply part d3, a fourth power supply part d4, and a fifth power supply part d5 that are sequentially connected. The first power supply part d1, the third power supply part d3, and the fifth power supply part d5 may be parallel to the second direction, the second power supply part d2 may be curved in the first direction X, and the fourth power supply part d4 may be curved in the direction opposite to the first direction X. The included angle between the second power supply part d2 and the first power supply part d1 may be greater than 0° and less than 90°. The included angle between the fourth power supply part d4 and the third power supply part d3 may be greater than 0° and less than 90°. A connection part d6 extending in the direction opposite to the first direction X is installed on the fifth power supply part d5. The connection part d6 is set to be connected to the fifth active layer via the third via. By setting the first power line 41 as a broken line, it not only contributes to the layout of the pixel structure but also can reduce the parasitic capacitor between the first power line and the data signal line.

[0128] In an exemplary embodiment, the shapes of the first power lines of each circuit unit may be the same or different. In an exemplary embodiment, the shape of the first power line in the circuit unit at the Nth column and Mth row may be the same as the shape of the first power line in the circuit unit at the (N + 2)th column and (M + 1)th row. The shape of the first power line in the circuit unit at the Nth column and (M + 1)th row may be the same as the shape of the first power line in the circuit unit at the (N + 3)th column and Mth row. The shape of the first power line in the circuit unit at the (N + 1)th column and Mth row may be the same as the shape of the first power line in the circuit unit at the (N + 3)th column and (M + 1)th row. The shape of the first power line in the circuit unit at the (N + 1)th column and (M + 1)th row may be the same as the shape of the first power line in the circuit unit at the (N + 3)th column and Mth row.

[0129] In an exemplary embodiment, the shape of the second connection electrode in each circuit unit of the Nth column and the shape of the second connection electrode in each circuit unit of the (N + 2)th column may be the same. The shape of the second connection electrode in each circuit unit of the (N + 1)th column and the shape of the second connection electrode in each circuit unit of the (N + 3)th column may be the same. The shape of the second connection electrode in the circuit units of the (N + 1)th column and the (N + 3)th column may be an elongated shape extending along the second direction Y. The second connection electrode is set to be connected to the first initial signal line and the first area of the seventh active layer via the ninth via and the seventh via, respectively. The shape of the second connection electrode 44 in the circuit units of the Nth column and the (N + 2)th column may include a first part 44-1 and a second part 44-2 that are connected to each other. The first part 44-1 is an elongated shape extending along the second direction Y, and the second part 44-2 may be rectangular. The second part 44-2 is installed on the side opposite to the first direction X of the first part 44-1. The first part 44-1 is set to be connected to the first initial signal line and the first area of the seventh active layer via the ninth via and the seventh via, respectively. The second part 44-2 is set to be connected to a subsequently formed second initial signal line via a subsequently formed via. Thereby, the connection between the first initial signal line and the second initial signal line is realized.

[0130] In an exemplary embodiment, the shapes of the third connection electrodes of each circuit unit may be the same or different. In an exemplary embodiment, the shape of the third connection electrode in the circuit unit of the Nth column in the Mth row and the shape of the third connection electrode in the circuit unit of the (N + 2)th column in the (M + 1)th row may be the same. The shape of the third connection electrode in the circuit unit of the Nth column in the (M + 1)th row and the shape of the third connection electrode in the circuit unit of the (N + 2)th column in the Mth row may be the same. The shape of the third connection electrode in the circuit unit of the (N + 1)th column in the Mth row and the shape of the third connection electrode in the circuit unit of the (N + 3)th column in the (M + 1)th row may be the same. The shape of the third connection electrode in the circuit unit of the (N + 1)th column in the (M + 1)th row and the shape of the third connection electrode in the circuit unit of the (N + 3)th column in the Mth row may be the same.

[0131] In an exemplary embodiment, the shapes of the data connection electrodes and the first connection electrodes of each circuit unit may be the same or different.

[0132] (6) Form a first planar layer pattern. In an exemplary embodiment, as shown in FIGS. 12a and 12b, FIG. 12b is a planar schematic diagram of a plurality of vias in FIG. 12a. The formation of the first planar layer pattern includes applying a first planar thin film on the base on which the pattern is formed and patterning the first planar thin film by a patterning process to form a first planar layer covering the third conductive layer. The first planar layer is provided with a first 11th via V11, a first 12th via V12, and a first 13th via V13.

[0133] As shown in FIGS. 7 to 12b, the orthographic projection of the first 11th via V11 on the base is located within the range of the orthographic projection of the data connection electrode 42 on the base. The first planar layer within the first 11th via V11 is removed to expose the surface of the data connection electrode 42. The first 11th via V11 is set such that a subsequently formed data signal line is connected to the data connection electrode 42 through the via.

[0134] In an exemplary embodiment, the first 11th via V11 may be elongated. The extension length of the first 11th via V11 in the second direction Y is greater than the extension length in the first direction X. In the present disclosure, by arranging the first 11th via V11 to extend along the second direction Y in an elongated shape, the width of the first 11th via V11 in the first direction X can be reduced, and the inclination degree of the subsequently formed anode can be reduced.

[0135] The orthographic projection of the first 12th via V12 on the base is located within the range of the orthographic projection of the second connection electrode 44 on the base. The first planar layer within the first 12th via V12 is removed to expose the surface of the second connection electrode 44. The first 12th via V12 is set such that a subsequently formed second initial signal line is connected to the second connection electrode 44 through the via.

[0136] The orthographic projection at the base of the 13th via V13 is located within the range of the orthographic projection at the base of the 3rd connection electrode 45. The first flat layer within the 13th via V13 is removed to expose the surface of the 3rd connection electrode 45. The 13th via V13 is set such that the subsequently formed anode connection electrode is connected to the 3rd connection electrode 45 through this via.

[0137] In an exemplary embodiment, the 11th via V11 and the 13th via V13 are installed in all circuit units. The 12th via V12 is installed in each circuit unit in the Nth column and the (N + 2)th column. The 12th via V12 is not installed in each circuit unit in the (N + 1)th column and the (N + 3)th column.

[0138] In an exemplary embodiment, the positions of the 11th via V11 and the 13th via V13 in each circuit unit may be the same or different.

[0139] (7) Form the fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 13a and 13b, FIG. 13b is a plan schematic diagram of the fourth conductive layer in FIG. 13a. The formation of the fourth conductive layer pattern includes depositing a fourth conductive thin film on the base where the pattern is formed and patterning the fourth conductive thin film by a patterning process to form the fourth conductive layer installed on the first flat layer. The fourth conductive layer includes at least a data signal line 51, a second initial signal line 52, and an anode connection electrode 53.

[0140] As shown in FIGS. 7 to 13b, the data signal lines 51 are installed in each unit column. The data signal lines 51 may extend along the second direction Y. The data signal lines 51 are connected to the data connection electrodes 42 through the 11th vias V11. Since the data connection electrodes 42 are connected to the first area of the fourth active layer through the 5th vias V5, the connection between the data signal lines 51 passing through the data connection electrodes 42 and the first area of the fourth active layer is realized, and data signals are written into the fourth transistor T4.

[0141] In an exemplary embodiment, the second initial signal line 52 is disposed in the Nth unit row and the (N + 2)th unit row, and the second initial signal lines 52 of each circuit unit in the unit row are connected to each other. The main body portion of the second initial signal line 52 extends along the second direction Y. The second initial signal line 52 is connected to the second connection electrode 44 via the 12th via V12. Since the second connection electrode 44 is connected to the first initial signal line 31 via the 9th via V9, the connection between the second initial signal line 52 and the first initial signal line 31 through the second connection electrode 44 is realized, and the first initial signal line 31 and the second initial signal line 52 have the same potential. In the present disclosure, by providing the first initial signal line 31 whose main body portion extends along the first direction X and the second initial signal line 52 whose main body portion extends along the second direction Y, the initial signal lines form a net-like structure, effectively reducing the resistance of the initial signal lines, not only reducing the voltage drop of the initial voltage, but also effectively improving the uniformity of the initial voltage in the display substrate, effectively improving the display uniformity, and improving the display quality and display effect.

[0142] In an exemplary embodiment, the anode connection electrode 53 is disposed in at least some of the circuit units. The anode connection electrode 53 is connected to the third connection electrode 45 via the 13th via V13. Since the third connection electrode 45 is connected to the second area of the sixth active layer (which is also the second area of the seventh active layer) via the 4th via V4, the connection between the anode connection electrode 53 and the second area of the sixth active layer (which is also the second area of the seventh active layer) through the third connection electrode 45 is realized.

[0143] In an exemplary embodiment, the second initial signal line 52 in one circuit unit may include an extension portion 521 and a connection portion 522. The extension portion 521 may be a broken line whose main body portion extends along the second direction Y. The connection portion 522 may be a straight line whose main body portion extends along the first direction X. In an exemplary embodiment, the end of the connection portion 522 on the side away from the extension portion 521 may be connected to the second connection electrode 44 via the 12th via V12.

[0144] In an exemplary embodiment, by positioning the orthographic projection of at least a portion of the extension portion 521 at the base within the range of the orthographic projection of the base of the first power line 41, the first power line 41 can effectively block the influence on the crucial nodes of the pixel driving circuit by the second initial signal line 52, not only avoiding the influence on the potential of the crucial nodes of the pixel driving circuit by the initial signal, but also fully utilizing the layout space, avoiding the influence on the light transmittance due to the installation of the second initial signal line, and improving the display effect.

[0145] In an exemplary embodiment, by positioning the orthographic projection of at least a portion of the connection portion 522 at the base within the range of the orthographic projection of the base of the first initial signal line 31, the layout space can be fully utilized, the influence on the light transmittance due to the installation of the second initial signal line can be avoided, and the display effect can be improved.

[0146] In an exemplary embodiment, the shape of the second initial signal line 52 in the circuit unit of the Mth row and Nth column may be the same as the shape of the second initial signal line 52 in the circuit unit of the (M + 1)th row and (N + 2)th column. The shape of the second initial signal line 52 in the circuit unit of the (M + 1)th row and Nth column may be the same as the shape of the second initial signal line 52 in the circuit unit of the Mth row and (N + 2)th column.

[0147] In an exemplary embodiment, in the circuit unit of the Mth row and Nth column and the circuit unit of the (M + 1)th row and (N + 2)th column, the extension portion 521 may include a first initial portion c1, a second initial portion c2, and a third initial portion c3 that are sequentially connected along the second direction Y. The first initial portion c1 and the third initial portion c3 may be parallel to the second direction Y, and the second initial portion c2 may be deflected in the direction opposite to the first direction X. The second initial portion c2 and the second direction Y may have a first included angle θ1, and the first included angle θ1 may be greater than 0° and less than 90°.

[0148] In an exemplary embodiment, in the circuit unit at the N+2nd column of the Mth row and the circuit unit at the Nth column of the M+1th row, the extension part 521 may include a fourth initial part c4, a fifth initial part c5, a sixth initial part c6, a seventh initial part c7, and an eighth initial part c8 that are sequentially connected along the second direction Y. The fourth initial part c4, the sixth initial part c6, and the eighth initial part c8 are parallel to the second direction Y. The fifth initial part c5 and the second direction Y have a first included angle θ1, and the seventh initial part c7 and the second direction Y have a second included angle θ2. The first included angle θ1 may be greater than 0° and less than 90°. The second included angle θ2 may be greater than 0° and less than 90°.

[0149] In an exemplary embodiment, the extending directions of the fifth initial part c5 and the seventh initial part c7 may be mirror-symmetrical with respect to the first direction X.

[0150] In an exemplary embodiment, a data signal line 51 and an anode connection electrode 53 are installed in at least some of the circuit units. A second initial signal line 52 is installed in each circuit unit of the Nth column and the N+2nd column. The second initial signal line 52 is not installed in each circuit unit of the N+1th column and the N+3rd column.

[0151] In an exemplary embodiment, the shapes of the anode connection electrodes in the circuit unit at the Nth column of the Mth row and the circuit unit at the N+2nd column of the M+1th row may be the same. The shape of the anode connection electrode may be rectangular. The shapes of the anode connection electrodes in the circuit unit at the Nth column of the M+1th row and the circuit unit at the N+2nd column of the Mth row may be the same. The shape of the anode connection electrode may be dumbbell-shaped. The shapes of the anode connection electrodes in the circuit unit at the N+1th column of the Mth row and the circuit unit at the N+3rd column of the M+1th row may be the same. The shape of the anode connection electrode may be rectangular. The shapes of the anode connection electrodes in the circuit unit at the N+1th column of the M+1th row and the circuit unit at the N+3rd column of the Mth row may be the same. The shape of the anode connection electrode may be rectangular.

[0152] (8) Form the second flat layer pattern. In an exemplary embodiment, as shown in FIGS. 14a and 14b, FIG. 14b is a plan schematic view of a plurality of vias in FIG. 14a. The formation of the second flat layer pattern includes coating a second flat thin film on the base on which the pattern is formed and patterning the second flat thin film by a patterning process to form a second flat layer covering the fourth conductive layer. The 14th via V14 is installed in the second flat layer.

[0153] As shown in FIGS. 7 to 14b, the orthographic projection of the 14th via V14 on the base is located within the range of the orthographic projection of the anode connection electrode 53 on the base. The second flat layer within the 14th via V14 is removed to expose the surface of the anode connection electrode 53. The 14th via V14 is set so that an anode to be formed subsequently is connected to the anode connection electrode 53 through the via.

[0154] So far, the manufacturing of the driving circuit layer on the base is completed. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units. Each circuit unit may include a pixel driving circuit, a first scanning signal line, a second scanning signal line, a light emission control line, a data signal line, a first power supply line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer sequentially stacked on the base.

[0155] In an exemplary embodiment, after the manufacturing of the driving circuit layer is completed, a light emitting structure layer is manufactured in the driving circuit layer, and the manufacturing process of the light emitting structure layer may include the following operations.

[0156] (9) Form the anode pattern. In an exemplary embodiment, as shown in FIGS. 15a and 15b, FIG. 15b is a plan schematic view of the anode in FIG. 15a. The formation of the anode pattern includes depositing a fifth conductive thin film on the base on which the pattern is formed and patterning the fifth conductive thin film by a patterning process to form an anode pattern installed on the second flat layer. The anode forms a GGRB pixel array.

[0157] As shown in FIGS. 7 to 15b, the anode pattern may include a first anode 71A of the red light-emitting device, a second anode 71B of the blue light-emitting device, a third anode 71C of the first green light-emitting device, and a fourth anode 71D of the second green light-emitting device. A red sub-pixel R that emits red light rays may be formed in the region where the first anode 71A is located, a blue sub-pixel B that emits blue light rays may be formed in the region where the second anode 71B is located, a first green sub-pixel G1 that emits green light rays may be formed in the region where the third anode 71C is located, and a second green sub-pixel G2 that emits green light rays may be formed in the region where the fourth anode 71D is located. The red sub-pixel R and the blue sub-pixel B are sequentially installed along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are sequentially installed along the second direction Y. The first green sub-pixel G1 and the second green sub-pixel G2 are each installed on the first direction X side of the red sub-pixel R and the blue sub-pixel B. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1, and the second green sub-pixel G2 constitute one pixel unit.

[0158] In an exemplary embodiment, in one pixel unit, the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the Nth column and the Mth row. The second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the Nth column and the (M + 1)th row. The third anode 71C is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 1)th column and the Mth row. The fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 1)th column and the (M + 1)th row. In other pixel units, the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 2)th column and the (M + 1)th row. The second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 2)th column and the Mth row. The third anode 71C is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 3)th column and the (M + 1)th row. The fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 3)th column and the Mth row.

[0159] In an exemplary embodiment, the anode connection electrode 53 in at least one circuit unit is connected to the third connection electrode 45 through the 13th via V13, and the third connection electrode 45 is connected to the second area of the sixth active layer (which is also the second area of the seventh active layer) through the 4th via V4. Since the third connection electrode 45 serves as the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, the anode is connected to the sixth transistor T6 and the seventh transistor T7 through the anode connection electrode 53 and the third connection electrode 45. The four anodes in at least one pixel unit are respectively connected corresponding to the pixel driving circuits of the four circuit units in one circuit unit set, realizing that the pixel driving circuit can drive the light emission of the light emitting device.

[0160] In an exemplary embodiment, the positional relationship between the four sub-pixels of one pixel unit and the four circuit units in one circuit unit set may be the same or different. In an exemplary embodiment of the present disclosure, the main part of the first anode 71A is located on the side opposite to the first direction X of the circuit unit to which it is correspondingly connected. The orthographic projection of the base of the first anode 71A and the orthographic projection of the extension of the second initial signal line may at least partially overlap. The main part of the second anode 71B is located on the first direction X side of the circuit unit to which it is correspondingly connected. The orthographic projection of the base of the second anode 71B and the orthographic projection of the base of the data signal line may at least partially overlap. The main part of the third anode 71C is located on the second direction Y side of the circuit unit to which it is correspondingly connected. The main part of the fourth anode 71D is located in the circuit unit of the next row of the circuit unit to which it is correspondingly connected.

[0161] In a possible exemplary embodiment, the main part of the first anode 71A may be located on the first direction X side of the circuit unit to which it is correspondingly connected. The orthographic projection of the base of the first anode 71A and the orthographic projection of the base of the data signal line may at least partially overlap. The main part of the second anode 71B may be located on the side opposite to the first direction X of the circuit unit to which it is correspondingly connected. The orthographic projection of the base of the second anode 71B and the orthographic projection of the extension of the second initial signal line may at least partially overlap.

[0162] In an exemplary embodiment, the shapes and positions of the first anodes 71A in different pixel units may be the same or different. The shapes and positions of the second anodes 71B in different pixel units may be the same or different. The shapes and positions of the third anodes 71C in different pixel units may be the same or different. The shapes and positions of the fourth anodes 71D in different pixel units may be the same or different. In the exemplary embodiment of the present disclosure, the shapes and positions of two first anodes 71A connected to the pixel driving circuits in the circuit unit at the Nth column of the Mth row and the circuit unit at the (N + 2)th column of the (M + 1)th row are the same. The shapes and positions of two second anodes 71B connected to the pixel driving circuits in the circuit unit at the Nth column of the (M + 1)th row and the circuit unit at the (N + 2)th column of the Mth row are the same. The shapes and positions of two third anodes 71C connected to the pixel driving circuits in the circuit unit at the (N + 1)th column of the Mth row and the circuit unit at the (N + 3)th column of the (M + 1)th row are the same. The shapes and positions of two fourth anodes 71D connected to the pixel driving circuits in the circuit unit at the (N + 1)th column of the (M + 1)th row and the circuit unit at the (N + 3)th column of the Mth row are the same.

[0163] In an exemplary embodiment, the shapes and areas of the anodes of the four sub-pixels in one pixel unit may be the same or different. In the exemplary embodiment of the present disclosure, the shapes and areas of the first anode 71A, the second anode 71B, the third anode 71C, and the fourth anode 71D in one pixel unit are all different.

[0164] In an exemplary embodiment, the first anode 71A in the red sub-pixel may include a first anode main body, and the shape of the first anode main body may be an approximate hexagon. In an exemplary embodiment, the first anode 71A may further include a first protrusion 71-1 and a second protrusion 71-2. Both the first protrusion 71-1 and the second protrusion 71-2 are connected to the first anode main body. The first protrusion 71-1 may be a rectangle protruding toward the gate electrode of the third transistor T3 in the pixel driving circuit to which it is connected. The second protrusion 71-2 may be a rectangle protruding toward the sixth transistor T6 in the pixel driving circuit to which it is connected. The first protrusion 71-1 and the second protrusion 71-2 are arranged to adjust the parasitic capacitor of the N3 node in the pixel driving circuit to which they are connected. Thereby, the difference between the parasitic capacitors of the N3 nodes in adjacent circuit units is reduced, the difference in luminance is reduced, and the display effect is improved.

[0165] In an exemplary embodiment, the second anode 71B in the blue sub-pixel may include a second anode main body, and the shape of the second anode main body may be an approximate hexagon. In an exemplary embodiment, the second anode 71B may further include a third protrusion 71-3, a fourth protrusion 71-4, and a fifth protrusion 71-5. The third protrusion 71-3, the fourth protrusion 71-4, and the fifth protrusion 71-5 are all connected to the second anode main body. The third protrusion 71-3 may be a rectangle protruding toward the first power line in the pixel driving circuit to which it is connected. The fourth protrusion 71-4 may be a rectangle protruding away from the first power line in the pixel driving circuit to which it is connected. The fifth protrusion 71-5 may be a polygon protruding toward the sixth transistor T6 in the pixel driving circuit to which it is connected. The third protrusion 71-3, the fourth protrusion 71-4, and the fifth protrusion 71-5 are arranged to adjust the parasitic capacitor of the N3 node in the pixel driving circuit to which they are connected. Thereby, the difference between the parasitic capacitors of the N3 nodes in adjacent circuit units is reduced, the difference in luminance is reduced, and the display effect is improved.

[0166] In an exemplary embodiment, the third anode 71C may include a third anode main body, and the shape of the third anode main body may be an approximate pentagon. In an exemplary embodiment, the third anode 71C may further include a sixth protrusion 71-6. The sixth protrusion 71-6 is connected to the third anode main body. The sixth protrusion 71-6 may be a rectangle protruding toward the sixth transistor T6 in the connected pixel driving circuit. The sixth protrusion 71-6 is installed to adjust the parasitic capacitor of the N3 node in the connected pixel driving circuit. Thereby, the difference between the parasitic capacitors of the N3 nodes in adjacent circuit units is reduced, the difference in luminance is reduced, particularly the difference in luminance between this sub-pixel and the second green sub-pixel is reduced, and the display effect is improved.

[0167] In an exemplary embodiment, the fourth anode 71D may include a fourth anode main body, and the shape of the fourth anode main body may be an approximate pentagon. In an exemplary embodiment, the fourth anode 71D may further include a seventh protrusion 71-7. The seventh protrusion 71-7 is connected to the fourth anode main body. The seventh protrusion 71-7 may be an elongated shape protruding toward the gate electrode of the third transistor T3 in the connected pixel driving circuit. The seventh protrusion 71-7 is installed to adjust the parasitic capacitor of the N3 node in the connected pixel driving circuit. Thereby, the difference between the parasitic capacitors of the N3 nodes in adjacent circuit units is reduced, the difference in luminance is reduced, particularly the difference in luminance between this sub-pixel and the first green sub-pixel is reduced, and the display effect is improved.

[0168] (10) Form a pixel definition layer pattern. In an exemplary embodiment, as shown in FIGS. 16a and 16b, FIG. 16b is a plan schematic view of the pixel definition layer in FIG. 16a. The formation of the pixel definition layer pattern includes applying a pixel definition thin film on the base on which the pattern is formed and patterning the pixel definition thin film by a patterning process to form the pattern of the pixel definition layer 72.

[0169] As shown in FIGS. 7 to 16b, the pattern of the pixel definition layer 72 includes a first pixel opening 73A that exposes the first anode 71A, a second pixel opening 73B that exposes the second anode 71B, a third pixel opening 73C that exposes the third anode 71C, and a fourth pixel opening 73D that exposes the fourth anode 71D.

[0170] In an exemplary embodiment, the orthographic projection of the base of the first pixel opening 73A has a first center line Z1, and the orthographic projection of the extension of the second initial signal line 52 has a second center line. The first center line Z1 is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the first pixel opening 73A in the first direction X. The second center line is a line that extends along the second direction Y and equally divides the orthographic projection of the extension of the second initial signal line in the first direction X. In an exemplary embodiment, the second center line is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the first initial portion c1 in the extension in the first direction X. In an exemplary embodiment, at least a part of the first center line and the second center line overlap. In the present disclosure, by setting the first center line of the first pixel opening 73A and the second center line of the extension of the second initial signal line to overlap at least partially, the second initial signal line in the first pixel opening 73A can maintain left - right symmetry, ensure the flatness of the first anode, and avoid color bleeding at a large viewing angle.

[0171] In an exemplary embodiment, the orthographic projection of the base of the second pixel opening 73B has a third center line Z3, and the orthographic projection of the base of the data signal line 51 has a fourth center line. The third center line Z3 is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the second pixel opening 73B in the first direction X. The fourth center line is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the data signal line in the first direction X. In an exemplary embodiment, at least a part of the third center line and the fourth center line overlap. In the present disclosure, by setting the third center line of the second pixel opening 73B and the fourth center line of the data signal line to overlap at least partially, the data signal line in the second pixel opening 73B can maintain left - right symmetry, ensure the flatness of the second anode, and avoid color bleeding at a large viewing angle.

[0172] The "equally dividing A" described in the present disclosure may mean that the distances between the two sides of the orthographic projection of A at the base and the center line are basically equal. Even if there is a deviation within the allowable range due to the process or tolerance, the distances between the two sides and the center line being basically equal is acceptable. For example, the ratio of the minimum distance between the edges on both sides of the orthographic projection of A at the base and the center line may be about 0.8 to 1.2. The "A and B overlapping" described in the present disclosure does not require A and B to completely overlap, and there may be a deviation within the allowable range due to the process or tolerance.

[0173] In exemplary embodiments, the flatness of the anode may be ensured in other ways. For example, a method of increasing the thickness of the second flat layer can be adopted. Also, the width of the signal line may be increased to substantially match the shape of the anode. Further, the signal line can be divided into two rows on the left and right, and the two rows are located on both sides of the center line and symmetrically laid below both sides of the anode. Additionally, the signal line can be located on both sides of the center line, divided into two lines, and respectively laid on the left and right sides of the anode. The present disclosure is not limited thereto.

[0174] In exemplary embodiments, the subsequent manufacturing process may include adopting a vapor deposition or inkjet printing process to form an organic light-emitting layer, connecting the organic light-emitting layer to the anode through a pixel aperture, forming a cathode in the organic light-emitting layer, and connecting the cathode to the organic light-emitting layer. A encapsulation layer is formed. The encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer that are stacked. The first encapsulation layer and the third encapsulation layer may adopt inorganic materials, and the second encapsulation layer may adopt organic materials. The second encapsulation layer is installed between the first encapsulation layer and the third encapsulation layer and can prevent external water vapor from entering the light-emitting structure layer.

[0175] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be, but is not limited to, one or more of glass and quartz. The flexible base may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible base may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer that are stacked. The materials of the first flexible material layer and the second flexible material layer may employ materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may employ silicon nitride (SiNx) or silica (SiOx) to improve the water and oxygen resistance of the base. The material of the semiconductor layer may employ amorphous silicon (a-si).

[0176] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may employ one or more of metal materials such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo or the like. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first insulating layer is referred to as a buffer layer and is used to improve the base's resistance to hydrogen oxygen. The second insulating layer and the third insulating layer are referred to as a gate insulating (GI) layer, and the fourth insulating layer is referred to as an interlayer insulating (ILD) layer. The active layer may employ materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium-zinc-tin-oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene. That is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The first planarization layer and the second planarization layer may employ an organic material such as resin or the like. The fifth conductive layer may employ a single-layer structure such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure such as ITO / Ag / ITO or the like. The pixel definition layer may employ polyimide, acrylic, or polyethylene terephthalate. The cathode may employ one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy composed of one or more of the above metals.

[0177] As can be seen from the structure and manufacturing process of the above display substrate, in the display substrate according to the present disclosure, a first initial signal line whose main body extends along a first direction and a second initial signal line whose main body extends along a second direction are provided. By connecting the first initial signal line and the second initial signal line through vias, the initial signal lines form a net-like structure, effectively reducing the resistance of the initial signal lines, not only reducing the voltage drop of the initial voltage, but also effectively improving the uniformity of the initial voltage in the display substrate, effectively improving the display uniformity, and improving the display quality and display effect. In the present disclosure, the first initial signal line and the second initial signal line are provided in different conductive layers, and at least a part of the extending portion of the second initial signal line overlaps with the first power line, and at least a part of the connecting portion of the second initial signal line overlaps with the first initial signal line. Thereby, the first power line effectively blocks the influence on the important nodes of the pixel driving circuit by the second initial signal line, not only avoiding the influence on the potential of the important nodes of the pixel driving circuit by the initial signal, but also making full use of the layout space to avoid the influence on the light transmittance caused by the installation of the second initial signal line. In the present disclosure, by providing the second initial signal line in the first unit column, the difference in luminance between two green sub-pixels in the same pixel unit can be avoided, and the display quality can be improved. In the present disclosure, by setting at least a part of the first center line of the first pixel aperture and the second center line of the extending portion of the second initial signal line to overlap, the second initial signal line in the first pixel aperture maintains left-right symmetry, ensures the flatness of the first anode, avoids color crosstalk at a large viewing angle, and can improve the display quality. The manufacturing process according to the present disclosure is well compatible with the conventional manufacturing process, the process is easy to realize, easy to implement, has high production efficiency, low production cost, and high yield.

[0178] FIG. 17a is a schematic structural diagram of another driving circuit layer according to an exemplary embodiment of the present disclosure, and FIG. 17b is a schematic plan view of a fourth conductive layer in FIG. 17a, showing a planar structure of eight circuit units (two unit rows, four unit columns). In an exemplary embodiment, the structures of the data signal lines 51 and the anode connection electrodes 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the driving circuit layer according to this exemplary embodiment are basically approximated to those in the above embodiment. The difference is that the second initial signal line 52 in the fourth conductive layer is installed in some circuit units in one unit column, and two adjacent second initial signal lines 52 in one unit column may be isolated from each other.

[0179] As shown in FIGS. 17a and 17b, in an exemplary embodiment, the main parts of the second initial signal lines 52 are installed in the circuit units at the Nth column and the Mth row and the circuit units at the (N + 2)th column and the (M + 1)th row, respectively. The second initial signal line 52 is connected to the second connection electrode 44 of the circuit unit through the 12th via V12 of the circuit unit, and is also connected to the second connection electrode 44 of the circuit unit in the next row through the 12th via V12 of the circuit unit in the next row. For example, for the circuit unit at the Nth column and the Mth row, the second initial signal line 52 is connected to the second connection electrode 44 of the circuit unit at the Nth column and the Mth row through the 12th via V12 of the circuit unit at the Nth column and the Mth row, and is connected to the second connection electrode 44 of the circuit unit at the Nth column and the (M + 1)th row through the 12th via V12 of the circuit unit at the Nth column and the (M + 1)th row. For the circuit unit at the Nth column and the (M + 1)th row, the second initial signal line 52 is connected to the second connection electrode 44 of the circuit unit at the Nth column and the (M + 1)th row through the 12th via V12 of the circuit unit at the Nth column and the (M + 1)th row, and is connected to the second connection electrode 44 of the circuit unit at the Nth column and the (M + 2)th row through the 12th via V12 of the circuit unit at the Nth column and the (M + 2)th row.

[0180] In an exemplary embodiment, at least one second initial signal line 52 may include an extension portion 521, a first connection portion 523, and a second connection portion 524. The extension portion 521 may be a broken line whose main body extends along the second direction Y. The first connection portion 523 and the second connection portion 524 may be straight lines whose main bodies extend along the first direction X. The first connection portion 523 may be installed in the circuit unit, and the second connection portion 524 may be installed in the circuit unit of the next row. In an exemplary embodiment, the end portion of the first connection portion 523 on the side away from the extension portion 521 is connected to the second connection electrode 44 of the circuit unit through the 12th via V12 of the circuit unit, and the end portion of the second connection portion 524 on the side away from the extension portion 521 is connected to the second connection electrode 44 of the circuit unit of the next row through the 12th via V12 of the circuit unit of the next row. In this way, one second initial signal line 52 can be connected to the first initial signal lines of two unit rows. Thereby, the first initial signal line and the second initial signal line form a net-like structure.

[0181] In an exemplary embodiment, at least a part of the orthographic projection of the extension portion 521 at the base is located within the range of the orthographic projection of the first power line 41 at the base. At least a part of the orthographic projection of the first connection portion 523 and the second connection portion 524 at the base is located within the range of the orthographic projection of the first initial signal line 31 at the base. Thereby, the layout space can be fully utilized to avoid the influence on the light transmittance caused by the installation of the second initial signal line and improve the display effect.

[0182] In this exemplary embodiment, the process of subsequently forming the light-emitting structure layer is basically approximated to the above embodiment. After forming the anode pattern, at least a part of the orthographic projection of the first anode at the base overlaps with at least a part of the orthographic projection of the extension portion of the second initial signal line at the base. At least a part of the first center line of the first pixel aperture overlaps with at least a part of the second center line of the extension portion of the second initial signal line. Thereby, the flatness of the first anode can be ensured and color crosstalk at a large viewing angle can be avoided.

[0183] FIG. 18a is a schematic structural diagram of a further driving circuit layer according to an exemplary embodiment of the present disclosure, and FIG. 18b is a schematic plan view of a fourth conductive layer in FIG. 18a, showing a planar structure of eight circuit units (two unit rows, four unit columns). In an exemplary embodiment, the structures of the data signal lines 51 and the anode connection electrodes 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the driving circuit layer according to this exemplary embodiment are basically approximated to those in the above embodiment. The difference is that the second initial signal lines 52 in the fourth conductive layer are installed in some circuit units in one unit column, and two adjacent second initial signal lines 52 in one unit column may be isolated from each other.

[0184] As shown in FIGS. 18a and 18b, in an exemplary embodiment, the main parts of the second initial signal lines 52 are respectively installed in the circuit units at the Nth column of the (M + 1)th row and the circuit units at the (N + 2)th column of the Mth row. The second initial signal lines 52 are connected to the second connection electrodes 44 of the circuit units through the 12th vias V12 of the circuit units, and are also connected to the second connection electrodes 44 of the circuit units in the next row through the 12th vias V12 of the circuit units in the next row.

[0185] In an exemplary embodiment, the main structure of at least one second initial signal line 52 may include an extension part 521, a first connection part 523, and a second connection part 524. The extension part 521, the first connection part 523, and the second connection part 524 may be approximated to the structures shown in FIG. 17b. One second initial signal line 52 is connected to the first initial signal lines of two unit rows, so that the first initial signal lines and the second initial signal lines form a net-like structure. At least a part of the orthographic projection of the extension part 521 on the base is located within the range of the orthographic projection of the first power line 41 on the base. At least a part of the orthographic projection of the first connection part 523 and the second connection part 524 on the base is located within the range of the orthographic projection of the first initial signal line 31 on the base. Thereby, the layout space can be fully utilized to avoid the influence on the light transmittance caused by the installation of the second initial signal lines and improve the display effect.

[0186] In the exemplary embodiment, the process of subsequently forming the light-emitting structure layer is basically approximated to the above embodiment. After forming the anode pattern, there may be no overlapping region between the orthographic projection of the first anode and the second anode on the base and the orthographic projection of the second initial signal line on the base. The extending portion of the second initial signal line does not pass through any pixel aperture. Thereby, the flatness of the first anode and the second anode can be further ensured, and color crosstalk at a large viewing angle can be avoided.

[0187] FIG. 19a is a schematic structural diagram of a further driving circuit layer according to an exemplary embodiment of the present disclosure, and FIG. 19b is a plan schematic diagram of a fourth conductive layer in FIG. 19a, showing a planar structure of eight circuit units (two unit rows, four unit columns). In the exemplary embodiment, the structures of the data signal line 51 and the anode connection electrode 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the driving circuit layer according to this exemplary embodiment are basically approximated to the above embodiment. The difference is that the second initial signal line 52 in the fourth conductive layer is installed in the N+1 unit column and the N+3 unit column, and the second initial signal lines 52 of each circuit unit in the unit column are connected to each other.

[0188] As shown in FIGS. 19a and 19b, in the exemplary embodiment, the second connection electrode 44 in the circuit units of the N+1 column and the N+3 column includes a first part and a second part that are connected to each other. The main body portion of the second initial signal line 52 extends along the second direction Y. The second initial signal line 52 is connected to the second part of the second connection electrode 44 through the twelfth via V12 in each circuit unit. Thereby, the first initial signal line and the second initial signal line form a net-like structure.

[0189] In the exemplary embodiment, the shape of the second initial signal line 52 in the circuit unit of the N+1 column in the Mth row may be the same as the shape of the second initial signal line 52 in the circuit unit of the N+3 column in the M+1th row. The shape of the second initial signal line 52 in the circuit unit of the N+1 column in the M+1th row may be the same as the shape of the second initial signal line 52 in the circuit unit of the N+3 column in the Mth row.

[0190] In an exemplary embodiment, the second initial signal line 52 in one circuit unit may include an extension portion 525 and a connection portion 526. The extension portion 525 may be a broken line whose main body extends along the second direction Y. The connection portion 526 may be a straight line whose main body extends along the first direction X. In an exemplary embodiment, the end of the connection portion 526 on the side away from the extension portion 525 is connected to the second connection electrode 44 via the 12th via V12.

[0191] In an exemplary embodiment, at least a part of the orthographic projection of the extension portion 525 at the base is located within the range of the orthographic projection of the base of the first power supply line 41. Thus, the first power supply line 41 can effectively block the influence on the important nodes of the pixel driving circuit by the second initial signal line 52, not only avoid the influence on the potential of the important nodes of the pixel driving circuit by the initial signal, but also make full use of the layout space to avoid the influence on the light transmittance due to the installation of the second initial signal line, and improve the display effect.

[0192] In an exemplary embodiment, at least a part of the orthographic projection of the connection portion 526 at the base is located within the range of the orthographic projection of the base of the first initial signal line 31. Thus, the layout space can be fully utilized to avoid the influence on the light transmittance due to the installation of the second initial signal line, and the display effect can be improved.

[0193] In an exemplary embodiment, the number of unit rows placed between adjacent second initial signal lines 52 is not particularly limited and may be set according to requirements, and the present disclosure is not limited thereto.

[0194] In the exemplary embodiment, the process of subsequently forming the light-emitting structure layer is basically approximated to the above embodiment. After forming the anode pattern, at least a part of the orthographic projection of the third anode and the fourth anode on the base overlaps with the orthographic projection of the connection portion of the second initial signal line on the base, but the orthographic projection of the first anode and the second anode on the base does not overlap with the orthographic projection of the second initial signal line on the base, and the orthographic projection of the first pixel opening and the second pixel opening on the base does not overlap with the orthographic projection of the second initial signal line on the base, that is, the second initial signal line does not pass through the first pixel opening and the second pixel opening. Thereby, the flatness of the first anode and the second anode can be ensured, and color crosstalk at a large viewing angle can be avoided.

[0195] In the exemplary embodiment, since the second initial signal line passes through the first green pixel opening and / or the second green pixel opening, the flatness of the third anode and / or the fourth anode can be improved by means such as increasing the thickness of the flat layer in the region where the first green pixel opening and / or the second green pixel opening is located.

[0196] In the exemplary embodiment, the second initial signal line 52 may be installed in some circuit units in the N+1 unit column and the N+3 unit column, and two adjacent second initial signal lines 52 in one unit column may be isolated from each other. For example, by installing the main parts of the second initial signal lines 52 in the circuit unit of the N+1 column of the Mth row and the circuit unit of the N+3 column of the M+1th row respectively, at least a part of the orthographic projection of the third anode formed subsequently on the base overlaps with the orthographic projection of the extension part of the second initial signal line on the base, but there is no overlapping region between the orthographic projection of the fourth anode on the base and the orthographic projection of the extension part of the second initial signal line on the base. Also, for example, by installing the main parts of the second initial signal lines 52 in the circuit unit of the N+1 column of the M+1th row and the circuit unit of the N+3 column of the Mth row respectively, at least a part of the orthographic projection of the fourth anode formed subsequently on the base overlaps with the orthographic projection of the extension part of the second initial signal line on the base, but there is no overlapping region between the orthographic projection of the third anode on the base and the orthographic projection of the extension part of the second initial signal line on the base. The present disclosure is not limited thereto.

[0197] FIG. 20a is a schematic structural diagram of a further driving circuit layer according to an exemplary embodiment of the present disclosure, and FIG. 20b is a schematic plan view of a fourth conductive layer in FIG. 20a, showing the planar structure of eight circuit units (two unit rows, four unit columns). In an exemplary embodiment, the structures of the data signal lines 51 and the anode connection electrodes 53 in the semiconductor layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in the driving circuit layer according to this exemplary embodiment are basically approximated to those in the above embodiment. The difference is that the second initial signal lines 52 in the fourth conductive layer are respectively installed in the Nth unit column, the (N + 1)th unit column, the (N + 2)th unit column, and the (N + 3)th unit column, and the second initial signal lines 52 of each circuit unit in at least one unit column are connected to each other.

[0198] As shown in FIGS. 20a and 20b, in an exemplary embodiment, the second connection electrodes 44 in at least one column of circuit units include a first part and a second part that are connected to each other. The main part of the second initial signal line 52 extends along the second direction Y, and the second initial signal line 52 is connected to the second part of the second connection electrode 44 through the 12th via V12 in each circuit unit. Thus, the first initial signal line and the second initial signal line form a net-like structure, minimizing the resistance of the initial signal line, reducing the voltage drop of the initial voltage, effectively improving the uniformity of the initial voltage on the display substrate, effectively improving the display uniformity, and improving the display quality and display effect.

[0199] In an exemplary embodiment, in the Nth unit column and the (N + 2)th unit column, the second initial signal line 52 of one circuit unit may include an extending portion 521 and a connecting portion 522. The extending portion 521 may be a broken line whose main part extends along the second direction Y. The connecting portion 522 may be a straight line whose main part extends along the first direction X. In an exemplary embodiment, the end of the connecting portion 522 on the side away from the extending portion 521 is connected to the second connection electrode 44 through the 12th via V12.

[0200] In an exemplary embodiment, in the (N + 1)-th unit column and the (N + 3)-th unit column, the second initial signal line 52 of one circuit unit may include an extension portion 525 and a connection portion 526. The extension portion 525 may be a broken line whose main body extends along the second direction Y. The connection portion 526 may be a straight line whose main body extends along the first direction X. In an exemplary embodiment, the end portion of the connection portion 526 on the side away from the extension portion 525 is connected to the second connection electrode 44 via the 12th via V12.

[0201] In an exemplary embodiment, at least a part of the orthographic projection of the extension portion 521 and the extension portion 525 at the base is located within the range of the orthographic projection of the base of the first power supply line 41. Thereby, the first power supply line 41 can effectively block the influence on the important nodes of the pixel driving circuit by the second initial signal line, not only avoid the influence on the potential of the important nodes of the pixel driving circuit by the initial signal, but also make full use of the layout space to avoid the influence on the light transmittance due to the installation of the second initial signal line, and can also improve the display effect.

[0202] In an exemplary embodiment, at least a part of the orthographic projection of the connection portion 522 and the connection portion 526 at the base is located within the range of the orthographic projection of the base of the first initial signal line 31. Thereby, full use can be made of the layout space to avoid the influence on the light transmittance due to the installation of the second initial signal line, and the display effect can be improved.

[0203] In the exemplary embodiment, the process of subsequently forming the light-emitting structure layer is basically approximated to the above embodiment. After forming the anode pattern, at least a part of the orthographic projection of the bases of the first anode, the second anode, the third anode, and the fourth anode overlaps with at least a part of the orthographic projection of the base of the second initial signal line. At least a part of the first center line of the first pixel opening overlaps with at least a part of the second center line of the extension of the second initial signal line. At least a part of the third center line of the second pixel opening overlaps with at least a part of the fourth center line of the data signal line. Thereby, it contributes to removing the difference in flatness between each anode and can avoid color shading at a large viewing angle. Since the second initial signal line passes through the first green pixel opening and / or the second green pixel opening, the flatness of the third anode and / or the fourth anode can be improved by means such as increasing the thickness of the flat layer in the region where the first green pixel opening and / or the second green pixel opening is located.

[0204] In an exemplary embodiment, the second initial signal line 52 may be installed in some circuit units in the Nth unit row, the (N + 1)th unit row, the (N + 2)th unit row, and the (N + 3)th unit row, and two adjacent second initial signal lines 52 in one unit row may be isolated from each other. For example, in the Nth unit row and the (N + 2)th unit row, the second initial signal lines 52 of adjacent circuit units may be connected to each other, but in the (N + 1)th unit row and the (N + 3)th unit row, the second initial signal line 52 may be installed only in the circuit unit at the (N + 1)th column of the Mth row and the circuit unit at the (N + 3)th column of the (M + 1)th row, or the second initial signal line 52 may be installed only in the circuit unit at the (N + 3)th column of the Mth row and the circuit unit at the (N + 1)th column of the (M + 1)th row. Also, for example, in the (N + 1)th unit row and the (N + 3)th unit row, the second initial signal lines 52 of adjacent circuit units may be connected to each other, but in the Nth unit row and the (N + 2)th unit row, the second initial signal line 52 may be installed only in the circuit unit at the Nth column of the Mth row and the circuit unit at the (N + 2)th column of the (M + 1)th row, or the second initial signal line 52 may be installed only in the circuit unit at the (N + 2)th column of the Mth row and the circuit unit at the Nth column of the (M + 1)th row. Further, for example, the second initial signal line 52 may be installed only in the circuit unit at the Nth column of the Mth row and the circuit unit at the (N + 2)th column of the (M + 1)th row. Or, the second initial signal line 52 may be installed only in the circuit unit at the (N + 2)th column of the Mth row and the circuit unit at the Nth column of the (M + 1)th row. Or, the second initial signal line 52 may be installed only in the circuit unit at the (N + 1)th column of the Mth row and the circuit unit at the (N + 3)th column of the (M + 1)th row. Or, the second initial signal line 52 may be installed only in the circuit unit at the (N + 3)th column of the Mth row and the circuit unit at the (N + 1)th column of the (M + 1)th row. The present disclosure is not limited thereto.

[0205] FIG. 21a is another schematic diagram after the anode pattern is formed according to an exemplary embodiment of the present disclosure, and FIG. 21b is a planar schematic diagram of the anode in FIG. 21a, showing the planar structure of eight circuit units (two unit rows, four unit columns). In an exemplary embodiment, the structure of the driving circuit layer according to this exemplary embodiment is basically approximated to the above embodiment. The second initial signal line 52 in the fourth conductive layer is installed in the Nth unit column, the (N + 1)th unit column, the (N + 2)th unit column, and the (N + 3)th unit column, and the second initial signal lines 52 of each circuit unit in the unit column are connected to each other. The difference is that the anodes of the light-emitting structure layer are arranged in a diamond pattern to form an RGBG pixel array.

[0206] As shown in FIGS. 21a and 21b, the anode pattern may include a first anode 71A of a red light-emitting device, a second anode 71B of a blue light-emitting device, a third anode 71C of a first green light-emitting device, and a fourth anode 71D of a second green light-emitting device. A red sub-pixel R that emits red light may be formed in the region where the first anode 71A is located, a blue sub-pixel B that emits blue light may be formed in the region where the second anode 71B is located, a first green sub-pixel G1 that emits green light may be formed in the region where the third anode 71C is located, and a second green sub-pixel G2 that emits green light may be formed in the region where the fourth anode 71D is located. The red sub-pixel R and the blue sub-pixel B are sequentially installed along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are sequentially installed along the first direction X. The first green sub-pixel G1 is installed on the opposite side of the red sub-pixel R and the blue sub-pixel B in the reverse direction of the first direction X, and the second green sub-pixel G2 is installed on the first direction X side of the red sub-pixel R and the blue sub-pixel B. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1, and the second green sub-pixel G2 constitute one pixel unit.

[0207] In an exemplary embodiment, in one pixel unit, the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the Nth column and the Mth row. The second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the Nth column and the (M + 1)th row. The third anode 71C is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 1)th column and the Mth row. The fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N - 1)th column and the Mth row. In other pixel units, the first anode 71A is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 2)th column and the (M + 1)th row. The second anode 71B is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 2)th column and the Mth row. The third anode 71C is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 1)th column and the Mth row. The fourth anode 71D is connected to the anode connection electrode 53 in the circuit unit through the 14th via V14 in the circuit unit at the (N + 3)th column and the Mth row.

[0208] In an exemplary embodiment, at least a part of the orthographic projection of the bases of the first anode 71A and the second anode 71B may overlap with at least a part of the orthographic projection of the extension part of the second initial signal line, and at least a part of the orthographic projection of the bases of the third anode 71C and the fourth anode 71D may overlap with at least a part of the orthographic projection of the connection part of the second initial signal line.

[0209] In an exemplary embodiment, the shapes and positions of the anodes in different pixel units may be the same or different. The shapes and areas of the anodes of the four sub-pixels in one pixel unit may be the same or different. The present disclosure is not limited thereto.

[0210] FIG. 22a is another schematic diagram after a pixel definition layer pattern is formed according to an exemplary embodiment of the present disclosure, and FIG. 22b is a plan schematic diagram of the pixel definition layer in FIG. 22a, showing a planar structure of eight circuit units (two unit rows, four unit columns). In an exemplary embodiment, the structures of the driving circuit layer and the anode according to this exemplary embodiment are basically approximated to those of the above embodiment. The difference is that the openings of the pixel definition layer 72 in the light-emitting structure layer are arranged in a diamond-like manner.

[0211] As shown in FIGS. 22a and 22b, the pattern of the pixel definition layer 72 may include a first pixel opening 73A that exposes the first anode 71A, a second pixel opening 73B that exposes the second anode 71B, a third pixel opening 73C that exposes the third anode 71C, and a fourth pixel opening 73D that exposes the fourth anode 71D.

[0212] In an exemplary embodiment, the orthographic projection of the first pixel opening 73A on a base has a first center line Z1, and the orthographic projection of an extension of the second initial signal line 52 on a base has a second center line. The orthographic projection of the second pixel opening 73B on a base has a third center line Z3, and the orthographic projection of the data signal line 51 on a base has a fourth center line. The first center line Z1 is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the first pixel opening 73A in the first direction X. The second center line is a line that extends along the second direction Y and equally divides the orthographic projection of the extension of the second initial signal line on a base in the first direction X. The third center line Z3 is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the second pixel opening 73B in the first direction X. The fourth center line is a line that extends along the second direction Y and equally divides the orthographic projection of the base of the data signal line in the first direction X.

[0213] "Dividing A equally" as described in the present disclosure may mean that the areas on both sides of the orthographic projection of A on the base by the center line are basically equal. Even if there is a deviation within the allowable range due to the process or tolerance, the areas on both sides being basically equal is acceptable. For example, the ratio of the areas on both sides is about 0.8 to 1.2. "A and B overlapping" as described in the present disclosure does not require A and B to completely overlap, and there may be a deviation within the allowable range due to the process or tolerance.

[0214] In an exemplary embodiment, at least a part of the first center line Z1 and the third center line Z3 may overlap. The second center line and the fourth center line may be located on both sides of the first center line Z1. The second center line and the fourth center line may be located on both sides of the third center line.

[0215] In an exemplary embodiment, the second center line of the second initial signal line and the fourth center line of the data signal line may be symmetrically arranged with respect to the first center line Z1 of the first pixel aperture. The second center line of the second initial signal line and the fourth center line of the data signal line may be symmetrically arranged with respect to the third center line Z3 of the second pixel aperture. In the present disclosure, by setting the extension part of the second initial signal line and the data signal line to be located on both sides of the first center line of the first pixel aperture 73A or the third center line of the second pixel aperture 73B respectively, the flatness of the first anode and the second anode can be ensured, and color bleeding at a large viewing angle can be avoided.

[0216] "The center line A and the center line B are symmetrically arranged with respect to the center line C" as described in the present disclosure means that the ratio of the distance between the center line A and the center line C and the distance between the center line B and the center line C is about 0.8 to 1.2.

[0217] In an exemplary embodiment, by adjusting the position of the anode in the circuit unit, the second center lines of the second initial signal lines all overlap with the first center line of the first pixel aperture and the third center line of the second pixel aperture, or the fourth center lines of the data signal lines all overlap with the first center line of the first pixel aperture and the third center line of the second pixel aperture. The present disclosure is not limited thereto.

[0218] In an exemplary embodiment, the orthographic projection at the base of the third pixel aperture 73C has a fifth center line Z5, the orthographic projection at the base of the fourth pixel aperture 73D has a sixth center line Z6, and the orthographic projection at the base of the connection portion of the second initial signal line 52 has a seventh center line. The fifth center line Z5 is a line that extends along the first direction X and equally divides the orthographic projection at the base of the third pixel aperture 73C in the second direction Y. The sixth center line Z6 is a line that extends along the first direction X and equally divides the orthographic projection at the base of the fourth pixel aperture 73D in the second direction Y. The seventh center line is a line that extends along the first direction X and equally divides the orthographic projection at the base of the connection portion of the second initial signal line 52 in the second direction Y.

[0219] In an exemplary embodiment, at least a part of the fifth center line Z5 and the seventh center line may overlap, and at least a part of the sixth center line Z6 and the seventh center line overlap. In the present disclosure, at least a part of the fifth center line of the third pixel aperture 73C and the seventh center line of the connection portion of the second initial signal line overlap, and at least a part of the sixth center line of the fourth pixel aperture 73D and the seventh center line of the connection portion of the second initial signal line overlap. By being set in this way, the flatness of the third anode and the fourth anode can be ensured, and color bleeding at a large viewing angle can be avoided.

[0220] The above structure of the present disclosure and its manufacturing process are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed according to actual needs, or the configuration process can be increased or decreased. For example, the first initial signal line may be installed in the first conductive layer (GATE 1). Also, for example, the second initial signal line may be installed in the third conductive layer (SD1), and the first power line may be installed in the fourth conductive layer (SD2). The present disclosure is not limited thereto. The display substrate according to the present disclosure can be applied to other display devices including a pixel driving circuit. The present disclosure is not limited thereto.

[0221] The present disclosure further provides a method for manufacturing a display substrate for manufacturing the display substrate according to the above embodiments. In an exemplary embodiment, the display substrate includes a driving circuit layer disposed on a base, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. The driving circuit layer includes a plurality of circuit units, the light-emitting structure layer includes a plurality of light-emitting devices, at least one circuit unit includes a first power line, an initial signal line, and a pixel driving circuit. The initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction. The first direction intersects the second direction. The manufacturing method includes forming a first initial signal line extending along the first direction on the base; forming a second initial signal line extending along the second direction, and at least a part of a projection of the second initial signal line on the base overlaps a projection of the first power line on the base.

[0222] Regarding the display substrate manufactured by the method for manufacturing a display substrate according to the present disclosure, its realization principle and realization effect are The realization principle and realization effect of the display substrate according to the above embodiment similar and will not be repeatedly described here.

[0223] The present disclosure further provides a display device, and the display device includes the above display substrate. The display device may be a product or component having a display function such as a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, a navigator, etc. The embodiments of the present invention are not limited thereto.

[0224] The above are the embodiments disclosed in the present disclosure. The above content is the embodiments used to facilitate the understanding of the present disclosure and is not intended to limit the present invention. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure. However, the patent protection scope of the present invention shall be subject to the appended claims.

Description of Reference Numerals

[0225] 11 First active layer 12 Second active layer 13 Third active layer 14 Fourth active layer 15 Fifth active layer 16 Sixth active layer 17 Seventh active layer 21 First scanning signal line 22 Second scanning signal line 23 Emission control line 24 First electrode plate 31 First initial signal line 32 Second electrode plate 33 Shield electrode 34 Opening 35 Electrode plate connection line 41 First power supply line 42 Data connection electrode 43 First connection electrode 44 Second connection electrode 45 Third connection electrode 51 Data signal line 52 Second initial signal line 53 Anode connection electrode 71 Anode 72 Pixel definition layer 73 Pixel opening 101 Base 102 Driving circuit layer 103 Light-emitting structure layer 104 Encapsulation layer 301 Anode 302 Pixel definition layer 303 Organic light-emitting layer 304 Cathode 401 First encapsulation layer 402 Second encapsulation layer 403 Third encapsulation layer

Claims

1. A display substrate, comprising a drive circuit layer installed on a base and a light-emitting structure layer installed on a side of the drive circuit layer away from the base, wherein the drive circuit layer includes a plurality of circuit units, the light-emitting structure layer includes a plurality of light-emitting devices, at least one circuit unit includes a first power line, an initial signal line, and a pixel drive circuit, the initial signal line includes a first initial signal line extending along a first direction and a second initial signal line extending along a second direction, the first direction intersects the second direction, and at least a part of a projection of the second initial signal line on the base overlaps with at least a part of a projection of the first power line on the base. The second initial signal line in at least one circuit unit includes an extension part and a connection part connected to each other, the extension part extends along the second direction, and the connection part extends along the first direction. At least one circuit unit includes a second connection electrode, the connection part is connected to the second connection electrode through a via, and the second connection electrode is connected to the first initial signal line through a via. The display substrate.

2. The display substrate according to Claim 1, wherein the connection part is connected to the first initial signal line through a via.

3. At least a part of a projection of the extension part on the base overlaps with at least a part of a projection of the first power line on the base, and at least a part of a projection of the connection part on the base overlaps with at least a part of a projection of the first initial signal line on the base. The display substrate according to Claim 2.

4. The second connection electrode is connected to a first area of an active layer of a first transistor and a first area of an active layer of a seventh transistor in the pixel drive circuit through vias. The display substrate according to Claim 1.

5. The drive circuit layer includes a plurality of unit rows and a plurality of unit columns, the unit rows include a plurality of circuit units arranged along the first direction, the unit columns include a plurality of circuit units arranged along the second direction, and in at least one unit column, the second initial signal lines in adjacent circuit units are connected to each other, or the second initial signal lines in adjacent circuit units are arranged at intervals. The display substrate according to Claim 1.

6. The plurality of circuit units includes a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light. The plurality of unit columns includes a first unit column and a second unit column. The first circuit unit and the second circuit unit in the first unit column are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit column are alternately installed along the second direction. At least a part of the second initial signal lines is installed in the first unit column. The display substrate according to claim 5.

7. The light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are installed. At least a part of a first center line of a front projection at the base of the first pixel opening and a second center line of a front projection at the base of the second initial signal line overlap. The display substrate according to claim 6.

8. The driving circuit layer further includes data signal lines. At least a part of a third center line of a front projection at the base of the second pixel opening and a fourth center line of a front projection at the base of the data signal lines overlap. The display substrate according to claim 7.

9. The light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are provided. The driving circuit layer further includes data signal lines. A second center line of a front projection of an extension portion of the second initial signal line at a base and a fourth center line of a front projection of the data signal line at a base are located on both sides of a first center line of a front projection of the first pixel opening at a base. The display substrate according to claim 6.

10. A second center line of a front projection of an extension portion of the second initial signal line at a base and a fourth center line of a front projection of the data signal line at a base are symmetrically installed with respect to a first center line of a front projection of the first pixel opening at a base. The display substrate according to claim 9.

11. A second center line of a front projection of an extension portion of the second initial signal line at a base and a fourth center line of a front projection of the data signal line at a base are located on both sides of a third center line of a front projection of the second pixel opening at a base. The display substrate according to claim 9.

12. A second center line of a front projection of an extension portion of the second initial signal line at a base and a fourth center line of a front projection of the data signal line at a base are symmetrically installed with respect to a third center line of a front projection of the second pixel opening at a base. The display substrate according to claim 11.

13. The plurality of circuit units includes a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light. The plurality of unit columns includes a first unit column and a second unit column. The first circuit unit and the second circuit unit in the first unit column are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit column are alternately installed along the second direction. At least a part of the second initial signal lines are installed in the second unit column. The display substrate according to claim 5.

14. The light-emitting device includes an anode and a pixel definition layer. The anode includes a first anode of the red light-emitting device, a second anode of the blue light-emitting device, a third anode of the first green light-emitting device, and a fourth anode of the second green light-emitting device. In the pixel definition layer, a first pixel opening for exposing the first anode, a second pixel opening for exposing the second anode, a third pixel opening for exposing the third anode, and a fourth pixel opening for exposing the fourth anode are provided. At least a part of a fifth center line of a front projection at the base of the third pixel opening and a seventh center line of a front projection at the base of a connection part of the second initial signal line overlap. The display substrate according to claim 13.

15. At least a part of a sixth center line of a front projection at the base of the fourth pixel opening and a seventh center line of a front projection at the base of a connection part of the second initial signal line overlap. The display substrate according to claim 14.

16. The plurality of circuit units include a first circuit unit connected to a red light-emitting device that emits red light, a second circuit unit connected to a blue light-emitting device that emits blue light, a third circuit unit connected to a first green light-emitting device that emits green light, and a fourth circuit unit connected to a second green light-emitting device that emits green light. The plurality of unit rows include a first unit row and a second unit row. The first circuit unit and the second circuit unit in the first unit row are alternately installed along the second direction. The third circuit unit and the fourth circuit unit in the second unit row are alternately installed along the second direction. The second initial signal line is installed in the first unit row and the second unit row. The display substrate according to claim 5.

17. In a direction perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially installed on the base. The semiconductor layer includes active layers of a plurality of transistors in the pixel driving circuit. The first conductive layer includes scanning signal lines and gate electrodes of a plurality of transistors. The second conductive layer includes the first initial signal line. The third conductive layer includes a first power supply line. The fourth conductive layer includes data signal lines and the second initial signal line. The display substrate according to claim 1.

18. The third conductive layer further includes a second connection electrode, the second connection electrode is connected to the first initial signal line via a via, and the second initial signal line is connected to the second connection electrode via a via. The display substrate according to claim 17.

19. A display device comprising the display substrate according to claim 1.

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