Multilayer ceramic capacitor, mounting substrate, and method for manufacturing multilayer ceramic capacitor

Abstract

To increase the number of laminations of internal electrodes while reducing the height of a multilayer ceramic capacitor.SOLUTION: A multilayer ceramic capacitor includes an element body that has a laminated body in which internal electrode layers are laminated with dielectric layers interposed therebetween, in which the lamination height of the laminated body is greater than the width of the internal electrode layers, and a pair of external electrodes formed on the surface of the element body and alternately connected to the internal electrode layers.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor, a mounting substrate, and a method for manufacturing a multilayer ceramic capacitor.

Background Art

[0002] With the miniaturization and high functionality of electronic devices, the mounting density of electronic components mounted on a mounting substrate has been increasing. Accordingly, In order to reduce the mounting area on the mounting surface side of an IC (Integrated Circuit) chip or the like, a method (LSC (land-side capacitor)) has been proposed in which a multilayer ceramic capacitor is made low-profile and mounted on the opposite side of the mounting surface side of the IC chip.

[0003] In order to make the multilayer ceramic capacitor low-profile, if the body is made thin, the number of internal electrode layers is limited, so there is a limit to increasing the capacitance. Patent Documents 1 and 2 disclose a multilayer ceramic capacitor in which internal electrodes are laminated in the horizontal direction of a mounting substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a configuration in which internal electrodes are laminated in the horizontal direction of a mounting substrate, when the multilayer ceramic capacitor is made low-profile, the width of the internal electrodes becomes small, leading to a decrease in capacitance. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor, a mounting substrate, and a method for manufacturing a multilayer ceramic capacitor that can increase the number of internal electrode layers while achieving low-profile.

Means for Solving the Problem

[0006] According to a multilayer ceramic capacitor according to one aspect of the present invention, in order to solve the above problems, it has a laminate in which internal electrode layers are laminated via dielectric layers, and a body in which the stacking height of the laminate is larger than the width of the internal electrode layer, and a pair of external electrodes formed on the surface of the body and alternately connected to the internal electrode layers.

[0007] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the length of the internal electrode layer is larger than the width of the internal electrode layer.

[0008] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the length of the internal electrode layer is larger than twice the width of the internal electrode layer.

[0009] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the length of the internal electrode layer is larger than the stacking height of the laminate.

[0010] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the thickness of the end portion in the width direction of the internal electrode layer is within a range of 85% or more and 115% or less of the thickness of the central portion in the width direction of the internal electrode layer.

[0011] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the average value of the thickness of the internal electrode layer is 1 μm or less, and the thickness of the internal electrode layer is 0.05 μm or more.

[0012] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the average value of the thickness of the internal electrode layer is 0.5 μm or less, and the thickness of the internal electrode layer is 0.05 μm or more.

[0013] Also, according to a multilayer ceramic capacitor according to one aspect of the present invention, the width of the internal electrode layer is 30 μm or more and 500 μm or less.

[0014] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the width of the internal electrode layer is 30 μm or more and 200 μm or less.

[0015] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the internal electrode layer is a deposited film.

[0016] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the dielectric layer is a fired body of a coating film containing a ceramic component.

[0017] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the internal electrode layer is drawn out alternately on on opposite sides of each other a pair of end faces of the green body, and the pair of external electrodes are continuously formed on the pair of end faces and four faces perpendicular to the pair of end faces, respectively.

[0018] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the internal electrode layer is drawn out on on opposite sides of each other a pair of end faces of the green body, and the pair of external electrodes are continuously formed on the pair of end faces and three faces perpendicular to the pair of end faces, respectively.

[0019] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the pair of external electrodes are formed on on opposite sides of each other one of a pair of faces of the green body in the width direction of the internal electrode layer and not formed on the other face.

[0020] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the internal electrode layer is drawn out only on on opposite sides of each other one of a pair of faces of the green body in the width direction of the internal electrode layer, and the pair of external electrodes are formed spaced apart from the face on which the internal electrode layer is drawn out.

[0021] Further, according to the multilayer ceramic capacitor according to one aspect of the present invention, the drawing positions of the internal electrode layer are set at positions alternately spaced apart in the length direction of the internal electrode layer.

[0022] Further, according to the mounting substrate according to one aspect of the present invention, it is a mounting substrate on which any of the above-described multilayer ceramic capacitors is mounted via a solder layer, and the internal electrode layer of the multilayer ceramic capacitor is laminated in the horizontal direction of the mounting substrate.

[0023] Further, according to the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, a step of forming a body in which an internal electrode layer is laminated via a dielectric layer and the height of the laminate of the internal electrode layer is larger than the width of the internal electrode layer, and a step of forming an external electrode on an end face of the body from which the internal electrode layer is drawn out.

[0024] Further, according to the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, the internal electrode layer is composed of a deposition film containing no ceramic component.

Effect of the Invention

[0025] According to one aspect of the present invention, it is possible to increase the number of internal electrode laminations while reducing the height of the multilayer ceramic capacitor.

Brief Description of the Drawings

[0026]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

Figure 6

Figure 7

Figure 8A

Figure 8B

Figure 8C

Figure 9

Figure 10

Mode for Carrying Out the Invention

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all combinations of the features described in the embodiments are essential to the configuration of the present invention. The configuration of the embodiments can be appropriately modified or changed according to the specifications of the device to which the present invention is applied and various conditions (usage conditions, usage environment, etc.). The technical scope of the present invention is determined by the scope of the claims and is not limited by the following individual embodiments. Also, the drawings used in the following description may differ from the actual structure, scale, shape, etc. in order to make each configuration easier to understand.

[0028] (First Embodiment) FIG. 1 is a perspective view showing a configuration example of the multilayer ceramic capacitor according to the first embodiment, FIG. 2A is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the length direction at the position of the first internal electrode, FIG. 2B is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the length direction at the position of the second internal electrode, FIG. 2C is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the width direction at the position of the element body, and FIG. 2D is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the width direction at the position of the element body when the internal electrode is dome-shaped in the width direction. Note that FIG. 2A is a cross-sectional view cut along the line A1-A1 of FIG. 1, FIG. 2B is a cross-sectional view cut along the line B1-B1 of FIG. 1, and FIG. 2C is a cross-sectional view cut along the line C1-C1 of FIG. 1.

[0029] In FIGS. 1 and 2A to 2C, the multilayer ceramic capacitor 1A includes a body 2 and external electrodes 6A and 6B. The body 2 includes a laminate 2A and cover layers 5A and 5B. The laminate 2A includes internal electrode layers 3A and 3B and a dielectric layer 4. The cover layers 5A and 5B are positioned so as to sandwich the laminate 2A in the stacking direction.

[0030] The internal electrode layers 3A and 3B are drawn out to and stacked on end faces MA and MB of the body 2 via the dielectric layer 4. on opposite sides of each other In FIGS. 1 and 2A to 2C, an example in which a total of 11 layers of the internal electrode layers 3A and 3B are stacked is shown, but the number of stacked layers of the internal electrode layers 3A and 3B is not particularly limited.

[0031] In the following description, the normal direction of the end faces MA and MB of the body 2 is referred to as the length direction DL, the direction perpendicular to the normal direction of the end faces MA and MB of the body 2 and perpendicular to the internal electrode layers 3A and 3B (the stacking direction of the internal electrode layers 3A and 3B) is referred to as the width direction DW, and the direction perpendicular to the normal direction of the end faces MA and MB of the body 2 and horizontal to the internal electrode layers 3A and 3B (the width direction of the internal electrode layers 3A and 3B) may be referred to as the height direction (or the thickness direction of the body 2) DH. inside The internal electrode layers 3A and 3B are stacked in the width direction DW via the dielectric layer 4. element The end faces MA and MB of the body 2 are in the length direction DL on opposite sides of each other within . Also, the cover layers 5A and 5B are in the width direction DW of the body 2 on opposite sides of each other within . The body 2 may be chamfered along the ridge line of the body 2.

[0032] The multilayer ceramic capacitor 1A is mounted on a mounting substrate and is used for removing noise applied to a semiconductor chip mounted on the mounting substrate. product In the direction perpendicular to the mounting surface of the multilayer ceramic capacitor 1A on opposite sides of each other within a pair of surfaces may be referred to as the upper surface and the lower surface. Also, in the horizontal direction of the mounting surface of the multilayer ceramic capacitor 1A on opposite sides of each other within of the surfaces, the surfaces from which the internal electrode layers 3A and 3B are not drawn out may be referred to as a pair of side surfaces.

[0033] The external electrodes 6A and 6B are separated from each other in the longitudinal direction DL of the element body 2 and are formed on the element body 2 in such a way that they are on the opposite side formed on the element body 2 as described above. each The external electrodes 6A and 6B can be continuously formed from each end face MA, MB of the element body 2 over four faces perpendicular to the end faces MA, MB.

[0034] The internal electrode layers 3A and 3B are alternately laminated in the width direction DW of the element body 2 with the dielectric layer 4 therebetween. each The internal electrode layers 3A and 3B can be positioned within the element body 2 in a state of standing upright in the height direction DH of the element body 2. Also, in the longitudinal direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions within the laminate 2A. For example, the internal electrode layer 3A can be arranged on one end face MA side of the element body 2 with respect to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other end face MB side of the element body 2 with respect to the internal electrode layer 3A. Then, the end of the internal electrode layer 3A is drawn out to the end of the dielectric layer 4 on one end face MA side in the longitudinal direction DL of the element body 2 and connected to the external electrode 6A. The end of the internal electrode layer 3B is drawn out to the end of the dielectric layer 4 on the other end face MB side in the longitudinal direction DL of the element body 2 and connected to the external electrode 6B. On the other hand, in the height direction DH of the element body 2, the ends of the internal electrode layers 3A and 3B are covered with the dielectric layer 4. In the height direction DH of the element body 2, the positions of the ends of the internal electrode layers 3A and 3B may be aligned.

[0035] Here, the stacking height TA of the laminate 2A is larger than the width WA of each internal electrode layer 3A, 3B. Note that the stacking direction of the laminate 2A is the width direction DW of the element body 2. The width direction of each internal electrode layer 3A, 3B is the height direction DH of the element body 2. product By increasing the stacking height TA of the laminate 2A, the number of stacked internal electrode layers 3A, 3B can be increased without increasing the height of the element body 2. Therefore, while making the multilayer ceramic capacitor 1A low-profile, the capacitance can be increased.

[0036] Also, the length LA of each internal electrode layer 3A, 3B can be made larger than the width WA of each internal electrode layer 3A, 3B. each The length LA of the internal electrode layers 3A and 3B is preferably greater than twice the width WA of each of the internal electrode layers 3A and 3B. Note that the length direction of each of the internal electrode layers 3A and 3B is the length direction DL of the base body 2. Thereby, it becomes possible to increase the capacitance of the multilayer ceramic capacitor 1A without increasing the height of the base body 2, and the low-profile can be achieved.

[0037] Also, the length LA of each of the internal electrode layers 3A and 3B can be made greater than the stacking height TA of the stacked body 2A. Thereby, it becomes possible to increase the capacitance of the multilayer ceramic capacitor 1A without increasing the height of the base body 2, and the low-profile can be achieved.

[0038] Note that the width WA of each of the internal electrode layers 3A and 3B is preferably 30 μm or more and 500 μm or less, more preferably 30 μm or more and 200 μm or less. The length LA of each of the internal electrode layers 3A and 3B is preferably 1000 μm or more. The number of stacked internal electrode layers 3A and 3B is preferably 450 or more.

[0039] Also, the thickness of the end portion in the width direction of each of the internal electrode layers 3A and 3B is preferably within the range of 85% or more and 115% or less of the thickness of the central portion in the width direction of each of the internal electrode layers 3A and 3B. Here, each of the internal electrode layers 3A and 3B can be formed of a deposited film such as a sputtered film or a vapor-deposited film. each The internal electrode layers 3A and 3B can be made to contain no ceramic component.

[0040] Here, as shown in FIG. 2D, it is assumed that each of the internal electrode layers 3A' and 3B' is formed by firing a coating film containing metal powder. In this case, the base body 2' of FIG. 2D is formed instead of the base body 2 of FIG. 2C. The base body 2' includes a stacked body 2A' instead of the stacked body 2A. In the stacked body 2A', the internal electrode layers 3A' and 3B' are alternately stacked via the dielectric layer 4. Here, when each of the internal electrode layers 3A' and 3B' is formed by firing the coating film, when the width WA of each of the internal electrode layers 3A' and 3B' becomes small, each of the internal electrode layers 3A' and 3B' becomes dome-shaped in the width direction. inside In order to prevent the insulation between the partial electrode layers 3A' and 3B' from degrading, in the laminate 2A', the number of laminations of the internal electrode layers 3A' and 3B' per unit length decreases compared to the laminate 2A, and since the electrode distance increases at the end portions in the width direction of the internal electrode layers 3A' and 3B', a decrease in capacitance is caused.

[0041] On the other hand, in the laminate 2A of Fig. 2C, the thickness of the end portions in the width direction of each of the internal electrode layers 3A and 3B is within the range of 85% or more and 115% or less of the thickness of the central portion in the width direction of each of the internal electrode layers 3A and 3B. For this reason, in the laminate 2A of Fig. 2C, it becomes possible to increase the number of laminations of the internal electrode layers 3A and 3B per unit length compared to the laminate 2A' of Fig. 2D, and it is possible to suppress an increase in the electrode distance at the end portions in the width direction of the internal electrode layers 3A and 3B, and it is possible to suppress a decrease in capacitance.

[0042] Note that the average value of the thickness of each of the internal electrode layers 3A and 3B is preferably 1 μm or less, and the thickness of each of the internal electrode layers 3A and 3B is preferably 0.05 μm or more. More preferably, the average value of the thickness of each of the internal electrode layers 3A and 3B is 0.5 μm or less, and the thickness of each of the internal electrode layers 3A and 3B is 0.05 μm or more.

[0043] The main components of the internal electrode layers 3A and 3B can be selected from metals such as, for example, Cu (copper), Fe (iron), Zn (zinc), Al (aluminum), Sn (tin), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), and may be alloys containing these metals.

[0044] The thickness of the dielectric layer 4 can be in the range of 0.05 μm to 5 μm. The material of the dielectric layer 4 can be mainly composed of, for example, a ceramic material having a perovskite structure. Note that the main component only needs to be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanium zirconate, and titanium oxide.

[0045] The materials of the cover layers 5A and 5B can be mainly composed of, for example, a ceramic material. cal The main component of the ceramic material of the bar layers 5A and 5B may be the same as the main component of the ceramic material of the dielectric layer 4.

[0046] The main component of each of the external electrodes 6A and 6B is a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. Each of the external electrodes 6A and 6B may include, as a conductive layer, an underlayer 7 formed on the element body 2 and a plating layer 9 laminated on the underlayer 7. The underlayer 7 is formed on the element body 2 in a state of being separated from each other in the length direction DL and on the opposite side formed in this way. under The underlayer 7 can be continuously formed from each end face MA and MB of the element body 2 over four faces perpendicular to the end faces MA and MB.

[0047] The metal used as the conductive material for the underlying layer 7 can mainly comprise a metal or an alloy containing at least one selected from, for example, Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The underlying layer 7 may contain a co-material in which metals are mixed. By being mixed in an island shape in the underlying layer 7, the co-material can reduce the difference in the coefficient of thermal expansion between the base body 2 and the underlying layer 7 and relieve the stress applied to the underlying layer 7. The co-material is, for example, a ceramic component that is the main component of the dielectric layer 4. The underlying layer 7 may contain a glass component. By being mixed in the underlying layer 7, the glass component can densify the underlying layer 7. This glass component is, for example, an oxide such as Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0048] Here, the underlying layer 7 is preferably composed of a sintered body of a conductive metal paste. Thereby, while ensuring the adhesion between the base body 2 and the underlying layer 7, it becomes possible to increase the thickness of the underlying layer 7, and while ensuring the strength of each of the external electrodes 6A and 6B, the electrical conductivity with the internal electrode layers 3A and 3B can be ensured.

[0049] The plating layer 9 is continuously formed for each of the external electrodes 6A and 6B so as to cover the underlying layer 7. The plating layer 9 is electrically connected to the internal electrode layers 3A and 3B via the underlying layer 7. Further, the plating layer 9 is electrically connected to the terminals of the mounting substrate via solder.

[0050] The material of the plating layer 9 is, for example, a metal or an alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The plating layer 9 may be a plating layer of a single metal component or a plurality of plating layers of different metal components. The plating layer 9 can have, for example, a three-layer structure including a Cu plating layer 9A formed on the underlying layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A can improve the adhesion of the plating layer 9 to the underlying layer 7. The Ni plating layer 9B can improve the heat resistance of each of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C can improve the wettability of the solder with respect to the plating layer 9.

[0051] FIG. 3 is a flowchart showing an example of a method for manufacturing a multilayer ceramic capacitor according to the first embodiment, FIGS. 4A and 4B are perspective views showing the method for manufacturing a multilayer ceramic capacitor according to the first embodiment, FIG. 4C is a perspective view showing the method for manufacturing a multilayer ceramic capacitor according to a comparative example, and FIGS. 5A to 5H are cross-sectional views showing an example of the method for manufacturing a multilayer ceramic capacitor according to the first embodiment. In FIGS. 5C to 5H, the case where the internal electrode layers 3A and 3B are alternately laminated five layers through the dielectric layer 4 is taken as an example.

[0052] In S1 of FIG. 3, a dispersant and an organic binder and an organic solvent as a molding aid are added to the dielectric material powder, and pulverized and mixed to produce a slurry. The dielectric material powder includes, for example, ceramic powder. The dielectric material powder may contain additives. The additives are, for example, oxides or glasses of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Co (cobalt), Ni, Li (lithium), B, Na (sodium), K (potassium) or Si. The organic binder is, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent is, for example, ethanol or toluene.

[0053] Next, as shown in S2 of FIG. 3, FIGS. 4A and 5A, a slurry containing ceramic powder is applied in a sheet shape on a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. For the application of the slurry, a doctor blade method, a die coater method, a gravure coater method or the like can be used.

[0054] Next, as shown in S3 of FIG. 3, FIGS. 4B and 5B, an internal electrode pattern 23 is formed on the green sheet 24 of the layer for forming the internal electrode layers 3A and 3B among a plurality of green sheets. For the formation of the internal electrode pattern 23, a film formation method such as sputtering or vapor deposition can be used. inside By performing sputtering or vapor deposition through a metal mask having an opening corresponding to the partial electrode pattern 23, a plurality of internal electrode patterns 23 separated in the longitudinal direction and the width direction can be formed on the green sheet 24.

[0055] product In order to reduce the height of the multilayer ceramic capacitor 1A, the width WA of the internal electrode pattern 23 is set to be short. For example, the width WA of the internal electrode pattern 23 is set to be 30 μm or more and 200 μm or less. Here, even when the width WA of the internal electrode pattern 23 is shortened by forming the internal electrode pattern 23 by a film formation method such as sputtering or vapor deposition, the thicknesses of the end portions in the width direction of each of the internal electrode layers 3A and 3B can be set within the range of 85% or more and 115% or less of the thickness of the central portion in the width direction of each of the internal electrode layers 3A and 3B.

[0056] On the other hand, as shown in FIG. 4C, there is a method of forming the internal electrode pattern 23' by applying a conductive paste for internal electrodes to the green sheet 24 of the layer for forming the internal electrode layers 3A' and 3B' in FIG. 2D so as to form a predetermined pattern. 1 A plurality of internal electrode patterns 23' separated in the longitudinal direction and the width direction of the green sheet 24 can be formed on the green sheet 24. The conductive paste for internal electrodes contains a metal powder used as a material for the internal electrode layers 3A' and 3B'. Further, the conductive paste for internal electrodes contains a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for internal electrodes may contain, as a co-material, a ceramic material which is a main component of the dielectric layer 4. For the application of the conductive paste for internal electrodes, a screen printing method, an inkjet printing method, a gravure printing method, or the like is used.

[0057] Here, in the method of forming the internal electrode pattern 23' by applying the conductive paste for internal electrodes, when the width WA of the internal electrode pattern 23' becomes small, each of the internal electrode layers 3A' and 3B' becomes dome-shaped in the width direction. For this reason, in the laminate 2A' in which the internal electrode layers 3A' and 3B' are laminated, the number of laminations of the internal electrode layers 3A' and 3B' per unit length decreases as compared with the laminate 2A in which the internal electrode layers 3A and 3B are laminated, and the electrode distance increases at the end portions in the width direction of the internal electrode layers 3A' and 3B', resulting in a decrease in capacitance.

[0058] Next, as shown in S4 of FIG. 3 and FIG. 5C, a laminated block is produced by stacking a plurality of green sheets 24 on which the internal electrode pattern 23 of FIG. 5B is formed and outer layer green sheets 25A and 25B on which the internal electrode pattern 23 is not formed in a predetermined order. product The internal electrode patterns 23A and 23B of the green sheet 24 adjacent in the layer direction are stacked so as to be alternately shifted in the longitudinal direction of the green sheet 24. Also, a portion where only the internal electrode pattern 23A is stacked in the stacking direction, a portion where the internal electrode patterns 23A and 23B are alternately stacked in the stacking direction, and a portion where only the internal electrode pattern 23B is stacked in the stacking direction are formed.

[0059] Next, as shown in S5 of FIG. 3 and FIG. 5D, the laminated block obtained in the molding step of S4 of FIG. 5 is pressed to crimp the green sheets 24, 25A, and 25B. As a method of pressing the laminated block, for example, a method of hydrostatic pressing the laminated block can be used.

[0060] Next, as shown in S6 of FIG. 3 and FIG. 5E, the laminated block pressed in the crimping step of S5 of FIG. 5 is cut to individualize it into a rectangular parallelepiped-shaped element 2. The cutting of the laminated block is performed at a portion where only the internal electrode pattern 23A is stacked in the stacking direction and a portion where only the internal electrode pattern 23B is stacked in the stacking direction. For cutting the laminated block, for example, a method such as blade dicing can be used.

[0061] figure As shown in 5F, internal electrode layers 3A and 3B alternately laminated via a dielectric layer 4 are formed on the individualized element 2, and cover layers 5A and 5B are formed on the lowermost layer and the uppermost layer in the stacking direction of the laminate 2A. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 at one end face MA of the element 2, and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 at the other end face MB of the element 2.

[0062] Next, as shown in S7 of FIG. 3, the binder contained in the element body 2 fragmented in S6 of FIG. 3 is removed. In removing the binder, for example, the element body 2 is heated in an N2 atmosphere at about 350°C.

[0063] Next, as shown in S8 of FIG. 3 and FIG. 5G, a conductive paste for an underlayer for forming an underlayer 7 is applied to both end faces MA and MB of the element body 2 from which the binder has been removed in S7 of FIG. 3 and four surfaces (upper surface, lower surface, and a pair of side surfaces) on the peripheral surfaces of the respective end faces MA and MB, and then dried. For applying the conductive paste for an underlayer, for example, a dipping method can be used. The conductive paste for an underlayer contains a metal powder or filler used as a conductive material for the underlayer 7. For example, when the metal used as the conductive material for the underlayer 7 is Ni, the conductive paste for an underlayer contains Ni powder or filler. Further, the conductive paste 7 for an underlayer contains, as a co-material, for example, a ceramic component that is the main component of the dielectric layer 4. For example, particles of an oxide ceramic mainly composed of barium titanate (for example, having a D50 particle size of 0.01 μm to 4 μm) are mixed into the conductive paste for an underlayer as a co-material. The conductive paste for an underlayer also contains a binder and a solvent.

[0064] Next, as shown in S9 of FIG. 5 and FIG. 5G, the element body 2 to which the conductive paste for an underlayer has been applied in S8 of FIG. 3 is fired to integrate the internal electrode layers 3A and 3B and the dielectric layer 4, and to form the underlayer 7 integrated with the element body 2. The firing of the element body 2 and the conductive paste for an underlayer is performed, for example, in a firing furnace at 1000 to 1400°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A and 3B, in order to prevent oxidation of the internal electrode layers 3A and 3B, firing can be performed with a reducing atmosphere in the firing furnace. In forming the underlayer 7, a re-oxidation treatment may be performed at a temperature of 600°C to 1000°C in an N2 gas atmosphere.

[0065] Next, as shown in S10 of FIG. 5 and FIG. 5H, a Cu plating layer 9A, a Ni plating layer 9B, and a Sn plating layer 9C are sequentially formed on the base layer 7. Here, the element body 2 on which the base layer 7 is formed is housed in a barrel together with the plating solution, and the plating layer 9 can be formed by energizing while rotating the barrel.

[0066] (Second Embodiment) FIG. 6 is a perspective view showing a configuration example of a multilayer ceramic capacitor according to the second embodiment. In FIG. 6, the multilayer ceramic capacitor 1X includes an element body 2 and external electrodes 6AX, 6BX. The multilayer ceramic capacitor 1X can be configured in the same manner as the multilayer ceramic capacitor 1A in FIG. 1 except that the external electrodes 6AX, 6BX are different.

[0067] The external electrodes 6AX, 6BX are formed on the element body 2 in a state of being separated from each other in the length direction DL. on the opposite side They are formed on the element body 2 as described above. each The external electrodes 6AX, 6BX can be continuously formed from each end face MA, MB of the element body 2 over three faces perpendicular to the end faces MA, MB. That is, the external electrodes 6AX, 6BX are continuously formed from each end face MA, MB of the element body 2 over the lower surface side and a pair of side surfaces of the element body 2X. each The external electrodes 6AX, 6BX are not formed on the upper surface side of the element body 2. Note that the upper ends of the external electrodes 6AX, 6BX may be formed at positions lower than the upper surface of the element body 2 on the side surface side of the element body 2.

[0068] Each external electrode 6AX, 6BX includes a base layer 7X formed on the element body 2 and a plating layer 9X laminated on the base layer 7X. The base layers 7X are formed on the element body 2 in a state of being separated from each other in the length direction DL. on opposite sides of each other They are formed on the element body 2 as described above. under The base layer 7X is continuously formed from each end face MA, MB of the element body 2 over three faces perpendicular to the end faces MA, MB and is connected to the internal electrode layers 3A, 3B respectively. That is, the base layer 7X is continuously formed from each end face MA, MB of the element body 2 over the lower surface side and a pair of side surfaces of the element body 2.under The base layer 7X is not formed on the upper surface side of the base body 2. Note that the upper end of the underlying layer 7X may be formed at a position lower than the upper surface of the base body 2 on the side surface side of the base body 2. However, the upper end of the underlying layer 7X is formed at a position higher than the positions of the internal electrode layers 3A and 3B on the side surface side of the base body 2X.

[0069] The plating layer 9X is continuously formed for each of the external electrodes 6AX and 6BX so as to cover the underlying layer 7X. The plating layer 9X is electrically connected to the internal electrode layers 3A and 3B via the underlying layer 7X. The plating layer 9X can have, for example, a three-layer structure including a Cu plating layer 9AX formed on the underlying layer 7X, a Ni plating layer 9BX formed on the Cu plating layer 9AX, and a Sn plating layer 9CX formed on the Ni plating layer 9BX.

[0070] Here, the multilayer ceramic capacitor 1X includes external electrodes 6AX and 6BX instead of the external electrodes 6A and 6B in FIG. 1, so that the height of the multilayer ceramic capacitor 1 can be reduced.

[0071] (Third Embodiment) FIG. 7 is a perspective view showing a configuration example of a multilayer ceramic capacitor according to the third embodiment. In FIG. 7, the end portions in the width direction DW of the multilayer ceramic capacitor are shown cut at the positions of the internal electrode layers. In FIG. 7, the multilayer ceramic capacitor 1Y includes a base body 2Y and external electrodes 6AY and 6BY. The base body 2Y includes a stacked body 2AY. The stacked body 2AY includes internal electrode layers 3AY and 3BY and a dielectric layer 4Y.

[0072] The internal electrode layers 3AY and 3BY are alternately stacked in the width direction DW of the base body 2Y with the dielectric layer 4Y therebetween. each The internal electrode layers 3AY and 3BY can be positioned within the base body 2Y in a state of standing upright in the height direction DH of the base body 2. Also, in the length direction DL of the base body 2Y, the internal electrode layers 3AY and 3BY are alternately arranged at the same positions within the stacked body 2A. element The extraction positions of the internal electrode layers 3AY and 3BY from the base body 2Y are in the width direction of the internal electrode layers 3AY and 3BYon opposite sides of each other within One of the pair of end faces of the base body 2Y is set only on the end face MY.

[0073] In order to draw out the internal electrode layers 3AY and 3BY from the base body 2Y, lead electrodes RA and RB can be provided on the end face MY side of the base body 2Y. of One lead electrode RA is connected to one end side in the length direction of the internal electrode layer 3AY, and the lead electrode RB is connected to the other end side in the length direction of the internal electrode layer 3BY. Then, the lead electrodes RA and RB are arranged at different positions in the length direction DL of the base body 2Y for each of the internal electrode layers 3AY and 3BY, and are drawn out to the end face MY side of the base body 2Y. Each lead electrode RA of the internal electrode layer 3AY can be made to coincide in position in the width direction DW of the base body 2Y, and each lead electrode RB of the internal electrode layer 3BY can be made to coincide in position in the width direction DW of the base body 2Y.

[0074] Here, the stacking height TY of the laminate 2AY is larger than the width WY of each of the internal electrode layers 3AY and 3BY. Note that the stacking direction of the laminate 2AY is the width direction DW of the base body 2Y. The width direction of each of the internal electrode layers 3AY and 3BY is the height direction DH of the base body 2Y. Also, the length LY of each of the internal electrode layers 3AY and 3BY can be made larger than the width WY of each of the internal electrode layers 3AY and 3BY. Note that the length direction of each of the internal electrode layers 3AY and 3BY is the length direction DL of the base body 2Y. Also, the length LY of each of the internal electrode layers 3AY and 3BY can be made larger than the stacking height TY of the laminate 2A. Note that the materials and thicknesses of the internal electrode layers 3AY and 3BY and the dielectric layer 4Y can be set in the same manner as the materials and thicknesses of the internal electrode layers 3A and 3B and the dielectric layer 4 in FIG. 1.

[0075] The external electrodes 6AY and 6BY are formed in parallel on the end face MY side of the base body 2Y in a state of being separated from each other in the length direction DL of the base body 2Y. Each of the external electrodes 6AY and 6BY includes an underlayer 7Y formed on the end face MY side of the base body 2Y and a plating layer 9Y laminated on the underlayer 7Y. The underlayer 7Y is formed in parallel on the end face MY side of the base body 2Y in a state of being separated from each other in the length direction DL of the base body 2Y, and is connected to the lead electrodes RA and RB, respectively.

[0076] The plating layer 9Y is continuously formed for each of the external electrodes 6AY and 6BY so as to cover the base layer 7Y. The plating layer 9Y is electrically connected to the internal electrode layers 3AY and 3BY via the base layer 7Y. The plating layer 9Y can have, for example, a three-layer structure including a Cu plating layer 9AY formed on the base layer 7Y, a Ni plating layer 9BY formed on the Cu plating layer 9AY, and a Sn plating layer 9CY formed on the Ni plating layer 9BY.

[0077] Here, the multilayer ceramic capacitor 1Y includes the external electrodes 6AY and 6BY instead of the external electrodes 6A and 6B in FIG. 1, so that the height of the multilayer ceramic capacitor can be reduced compared to the multilayer ceramic capacitor 1.

[0078] (Fourth Embodiment) FIG. 8A is a cross-sectional view of the multilayer ceramic capacitor according to the fourth embodiment cut in the longitudinal direction at the position of the first internal electrode, FIG. 8B is a cross-sectional view of the multilayer ceramic capacitor according to the fourth embodiment cut in the longitudinal direction at the position of the second internal electrode, and FIG. 8C is a cross-sectional view of the multilayer ceramic capacitor according to the fourth embodiment cut in the width direction at the position of the body.

[0079] In FIGS. 8A to 8C, the multilayer ceramic capacitor 1C includes a body 2C instead of the body 2 of the multilayer ceramic capacitor 1A in FIGS. 2A to 2C. The body 2C includes a laminate 2AC, cover layers 5A and 5B, and side margin layers 8A and 8B. The laminate 2AC includes internal electrode layers 3A and 3B and a dielectric layer 4.

[0080] The cover layers 5A and 5B are positioned so as to sandwich the laminate 2AC in the stacking direction. The side margin layers 8A and 8B are positioned so as to sandwich the laminate 2AC in the width direction of the internal electrode layers 3A and 3B. The side margin layers 8A and 8B can contact the ends in the width direction of the internal electrode layers 3A and 3B. Note that the stacking direction of the laminate 2AC is the width direction DW of the body 2C, and the width direction of the internal electrode layers 3A and 3B is the height direction DH of the body 2C.

[0081] In the laminate 2AC, the internal electrode layers 3A and 3B are exposed from the dielectric layer 4 in the width direction of the internal electrode layers 3A and 3B. The laminate 2AC can be configured in the same manner as the laminate 2A shown in FIGS. 2A to 2C, except at the points where the internal electrode layers 3A and 3B are exposed from the dielectric layer 4 in the width direction of the internal electrode layers 3A and 3B. However, in the multilayer ceramic capacitor 1C, the internal electrode layers 3A and 3B may be formed by firing a coating film of a conductive paste for internal electrodes. In this case, in the step of forming the internal electrode pattern 23' in FIG. 4C, it is not necessary to separate the internal electrode pattern 23' together with the element body 2C in its width direction. Therefore, the width WA of the internal electrode pattern 23' can be increased, and the internal electrode pattern 23' can be suppressed from becoming dome-shaped in its width direction. Therefore, even when the internal electrode layers 3A and 3B are formed by firing a coating film of a conductive paste for internal electrodes, the thickness of the end portions in the width direction of each of the internal electrode layers 3A and 3B can be set within the range of 85% or more and 115% or less of the thickness of the central portion in the width direction of each of the internal electrode layers 3A and 3B.

[0082] When cutting the laminated block in the process of FIG. 5E, the cutting position in the width direction of the laminated block is set at a position where the conductive paste for internal electrodes is not applied in the multilayer ceramic capacitor 1A, but is set at a position where the conductive paste for internal electrodes is applied in the multilayer ceramic capacitor 1C. For this reason, the internal electrode layers 3A and 3B are exposed from the dielectric layer 4 in the width direction of the internal electrode layers 3A and 3B. Then, side margin layers 8A and 8B are formed so as to sandwich the laminate 2AC in the width direction of the internal electrode layers 3A and 3B after cutting the laminated block. Then, a base layer 7 is formed on the element body 2C on which the side margin layers 8A and 8B are formed in the same process as in FIG. 5G, and further, a plating layer 9 is formed on the base layer 7 in the same process as in FIG. 5H.

[0083] (Fifth Embodiment) FIG. 9 is a cross-sectional view showing a configuration example of a mounting substrate on which the multilayer ceramic capacitor according to the fifth embodiment is mounted. In FIG. 9, land electrodes 42A, 42B, 44A, and 44B are formed on the back side of the mounting substrate 41. The multilayer ceramic capacitor 1A is connected to the land electrodes 42A and 42B via solder layers 43A and 43B respectively attached to the plating layers 9 of the external electrodes 6A and 6B. li The multilayer ceramic capacitor 1A is mounted on the mounting substrate 41 such that the width directions of the internal electrode layers 3A and 3B coincide with the height direction DH of the element body 2. Solder balls 47A and 47B are formed on the land electrodes 44A and 44B on the back side of the mounting substrate 41.

[0084] On the other hand, a semiconductor chip (not shown) is mounted on the front side of the mounting substrate 41. This semiconductor chip may be a microprocessor, a semiconductor memory, an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit).

[0085] Land electrodes 46A and 46B are formed on the back side of the mounting substrate 45. The mounting substrates 41 and 45 are connected to each other via the solder balls 47A and 47B. The mounting substrate 45 can be used as a mother board on which the mounting substrate 41 is mounted.

[0086] A certain interval is maintained between the mounting substrates 41 and 45 via the solder balls 47A and 47B. inside product real A resin 48 for sealing the multilayer ceramic capacitor 1A is provided between the mounting substrates 41 and 45. This resin 48 is, for example, an epoxy resin. This resin 48 may be injected between the mounting substrates 41 and 45 and cured after the mounting substrates 41 and 45 are connected to each other via the solder balls 47A and 47B.

[0087] Here, by mounting the multilayer ceramic capacitor 1A on the back side of the mounting substrate 41, the multilayer ceramic capacitor 1A can be disposed on the back side of the semiconductor chip mounted on the front side of the mounting substrate 41. Therefore, it becomes possible to mount the multilayer ceramic capacitor 1A in proximity to the semiconductor chip mounted on the front side of the mounting substrate 41, and it becomes possible to effectively remove the noise applied to the semiconductor chip.

[0088] Also, by making the stacking height TA of the stacked body 2A larger than the width WA of each of the internal electrode layers 3A, 3B and mounting the multilayer ceramic capacitor 1A on the mounting substrate 41 such that the width directions of the internal electrode layers 3A, 3B coincide with the height direction DH of the body 2, it is possible to lower the height during mounting of the multilayer ceramic capacitor 1A while suppressing a decrease in the capacitance of the multilayer ceramic capacitor 1A. Therefore, the multilayer ceramic capacitor 1A can be accommodated in the gap between the mounting substrates 41 and 45 connected to each other via the solder balls 47A, 47B, and it becomes possible to dispose the multilayer ceramic capacitor 1A on the back side of the semiconductor chip disposed on the front side of the mounting substrate 41, and it becomes possible to effectively remove the noise applied to the semiconductor chip.

[0089] (Example) FIG. 10 is a diagram showing a comparison of the height and capacitance of the multilayer ceramic capacitor according to the example with those of a comparative example. In FIG. 10, it is assumed that the outer size of the multilayer ceramic capacitor 1A in FIG. 1 is 1005, but the same results are obtained even if the outer size is 0603 or 0402 or the like. Examples 1 to 3 show the case where the body 2' in FIG. 2D is used for the multilayer ceramic capacitor 1A, and Examples 4 to 6 show the case where the body 2 in FIG. 2C is used for the multilayer ceramic capacitor 1A. The comparative example is an example where each of the internal electrode layers 3A, 3B is stacked in parallel with respect to the mounting substrate (conventional method).

[0090] In FIG. 10, in the normal manufacturing methods (Comparative Examples 1 to 3), when the number of laminated internal electrode layers 3A and 3B is reduced to lower the profile, the capacitance density significantly decreases. On the other hand, in Examples 1 to 3, since each internal electrode layer 3A' and 3B' is dome-shaped in the width direction and the difference in thickness between the central portion and the end portion of each internal electrode layer 3A' and 3B' becomes large, it causes a decrease in capacitance density. In Examples 4 to 6, it is not necessary to reduce the number of laminated internal electrode layers 3A' and 3B' to lower the profile, and since the difference in thickness between the central portion and the end portion of each internal electrode layer 3A' and 3B' becomes small, the capacitance density could be maintained. Also, in Examples 4 to 6, since the internal electrode layers 3A and 3B are perpendicular to the mounting surface, the flexural strength against the load during mounting of the multilayer ceramic capacitor 1A can also be increased.

Explanation of Reference Numerals

[0091] 1A Multilayer ceramic capacitor 2 Body 2A Laminate 3A, 3B Internal electrode layers 4 Dielectric layer 5A, 5B Cover layers 6A, 6B External electrodes 7 Underlayer 9 Plating layer

Claims

1. A body having a laminate in which a plurality of internal electrode layers are laminated via a dielectric layer, the height of the lamination of the laminate being greater than the width of the internal electrode layer, and a pair of external electrodes formed on the surface of the body and alternately connected to the internal electrode layers. The body has an upper surface, a lower surface, a pair of end faces, and a pair of side faces. The direction of the height of the lamination of the laminate is parallel to the upper surface, the lower surface, and the end faces and perpendicular to the side faces. The direction of the width of the internal electrode layer is parallel to the end faces and the side faces and perpendicular to the upper surface and the lower surface. The plurality of internal electrode layers include a first internal electrode layer and a second internal electrode layer. The first internal electrode layer is exposed at one end face of the body, and the second internal electrode layer is exposed at the other end face of the body. One external electrode is formed on the entire surface of one end face of the body and extends from the one end face to a partial region of the lower surface adjacent to the one end face and a partial region of the pair of side faces, and is not formed on the upper surface. The other external electrode is formed on the entire surface of the other end face of the body and extends from the other end face to a partial region of the lower surface adjacent to the other end face and a partial region of the pair of side faces, and is not formed on the upper surface. Each of the external electrodes has a first side covering portion and a second side covering portion that respectively cover the pair of side faces of the body. The upper ends of the first side covering portion and the second side covering portion are lower than the upper surface of the body. Each of the external electrodes has an end covering portion that covers the end face of the body. The upper end of the end covering portion has a height equal to the height of the upper surface of the body. A multilayer ceramic capacitor characterized by the above.

2. The multilayer ceramic capacitor according to claim 1, wherein the length of the internal electrode layer is greater than the width of the internal electrode layer.

3. The multilayer ceramic capacitor according to claim 2, wherein the length of the internal electrode layer in the direction perpendicular to the end face is greater than twice the width of the internal electrode layer.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the length of the internal electrode layer in the direction perpendicular to the end face is greater than the height of the lamination of the laminate.

5. The laminated ceramic capacitor according to any one of claims 1 to 4, characterized in that the thickness of the end portion in the width direction of the internal electrode layer is within a range of 85% or more and 115% or less of the thickness of the central portion in the width direction of the internal electrode layer.

6. The laminated ceramic capacitor according to any one of claims 1 to 5, characterized in that the average value of the thickness of the internal electrode layer is 1 μm or less, and the thickness of the internal electrode layer is 0.05 μm or more.

7. The laminated ceramic capacitor according to claim 6, characterized in that the average value of the thickness of the internal electrode layer is 0.5 μm or less, and the thickness of the internal electrode layer is 0.05 μm or more.

8. The laminated ceramic capacitor according to any one of claims 1 to 7, characterized in that the width of the internal electrode layer is 30 μm or more and 500 μm or less.

9. The laminated ceramic capacitor according to claim 8, characterized in that the width of the internal electrode layer is 30 μm or more and 200 μm or less.

10. The laminated ceramic capacitor according to any one of claims 1 to 9, characterized in that the internal electrode layer is a deposited film.

11. The laminated ceramic capacitor according to any one of claims 1 to 10, characterized in that the dielectric layer is a fired body of a coating film containing a ceramic component.

12. Each of the external electrodes has an underlayer formed on the element body and a plating layer formed on the underlayer. The underlayer has a first side covering portion and a second side covering portion that respectively cover the lower portions of a pair of side surfaces of the element body. The upper ends of the first side covering portion and the second side covering portion of the underlayer are higher than the position of the internal electrode layer. The laminated ceramic capacitor according to any one of claims 1 to 11.

13. The laminated ceramic capacitor according to claim 12, characterized in that the internal electrode layer has a uniform width.

14. A mounting substrate on which the laminated ceramic capacitor according to any one of claims 1 to 13 is mounted via a solder layer, The internal electrode layer of the laminated ceramic capacitor is oriented perpendicular to the mounting substrate and laminated in the horizontal direction of the mounting substrate. A mounting substrate characterized by this.

15. A method for manufacturing a laminated ceramic capacitor according to any one of claims 1 to 13, A step of forming a body in which an internal electrode layer is laminated via a dielectric layer and the height of the laminate of the internal electrode layers is greater than the width of the internal electrode layer; A method for manufacturing a multilayer ceramic capacitor, comprising a step of forming an external electrode on an end face of the body from which the internal electrode layer has been drawn out.

16. The method for manufacturing a multilayer ceramic capacitor according to claim 15, wherein the internal electrode layer is composed of a deposition film containing no ceramic component.

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