Semiconductor device

Abstract

To provide a compact semiconductor device.SOLUTION: A semiconductor device comprises a transistor, first wiring, a resistive element, and a capacitor. The transistor has a first electrode, a second electrode, and a control electrode provided between the first and second electrodes. The first wiring is electrically connected with the control electrode of the transistor. The resistive element is provided between the transistor and the first wiring, including a first terminal electrically connected with the control electrode. The capacitor is electrically connected with a second terminal of the resistive element. The transistor, the resistive element, and the first wiring are arranged in a first direction. The resistive element and the capacitor are arranged in a second direction crossing the first direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments relate to semiconductor devices.

Background Art

[0002] Monolithic microwave integrated circuits (MMICs) including power amplifiers (HPAs) used in microwave wireless communication and radar transmitters are required to be miniaturized to reduce costs.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments provide a miniaturized semiconductor device.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a transistor, a first wiring, a resistance element, and a first capacitor. The transistor has a first electrode, a second electrode, and a control electrode provided between the first electrode and the second electrode. The first wiring is electrically connected to the control electrode of the transistor. The resistance element is provided between the transistor and the first wiring and includes a first terminal electrically connected to the control electrode. The first capacitor is electrically connected to the second terminal of the resistance element. The transistor, the resistance element, and the first wiring are arranged in a first direction, and the resistance element and the first capacitor are arranged in a second direction intersecting the first direction.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The same parts in the drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationships between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as those in reality. Also, even when representing the same part, the dimensions and ratios may be different from each other depending on the drawings.

[0008] Furthermore, the arrangement and configuration of each part will be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X-direction, Y-direction, and Z-direction, respectively. Also, the Z-direction may be described as upward and the opposite direction as downward.

[0009] FIG. 1 is a circuit diagram showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a power amplifier in which a field effect transistor (hereinafter, transistor Tr) and a stabilization circuit are integrated. Hereinafter, an example using a HEMT (High Electron Mobility Transistor) made of GaN as a material will be described, but the embodiment is not limited thereto. The FET may be, for example, a GaAs MESFET or a GaAs pHEMT.

[0010] As shown in FIG. 1, the semiconductor device 1 includes a transistor Tr, a first wiring TL1, a second wiring TL2, a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2.

[0011] The transistor Tr has a gate terminal G, a source terminal S, and a drain terminal D. The first wiring TL1 is provided between the input terminal P1 and the gate terminal G of the transistor Tr and is electrically connected to the gate terminal G. The second wiring TL2 is provided between the drain terminal D of the transistor Tr and the output terminal P2 and is electrically connected to the drain terminal D.

[0012] The first resistor R1 is connected between the gate terminal G of the transistor Tr and the first wiring TL1. The first resistor R1 is electrically connected to the first wiring TL1 and the gate terminal G. Also, the first resistor R1 and the first capacitor C1 are connected in series. The first terminal of the first capacitor C1 is connected to the first resistor R1, and the second terminal is grounded via a via hole V1.

[0013] The second resistor R2 is connected between the gate terminal G of the transistor Tr and the first wiring TL1. The second resistor R2 is electrically connected to the first wiring TL1 and the gate terminal G. Also, the second resistor R2 and the second capacitor C2 are connected in series. The first terminal of the second capacitor C2 is connected to the second resistor R2, and the second terminal is grounded via the via hole V2.

[0014] The source terminal S of the transistor Tr is electrically connected to the second terminals of the first capacitor C1 and the second capacitor C2, and is grounded via the via holes V1 and V2. The stabilization circuit of the semiconductor device 1 is composed of the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2.

[0015] FIG. 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment. FIG. 2 is a schematic diagram showing the layout of the upper surface of the semiconductor device 1.

[0016] As shown in FIG. 2, the transistor Tr, the first wiring TL1, and the 2 second wiring TL2 are arranged in the first direction (for example, the X direction). The transistor Tr is provided between the first wiring TL1 and the second wiring TL2.

[0017] The semiconductor device 1 further includes a resistance element RD (see FIG. 3(a)). The resistance element RD is provided between the transistor Tr and the first wiring TL1. Note that the broken line shown in FIG. 2 illustrates the outer edge of the resistance layer 17 (see FIG. 3(a)).

[0018] The transistor Tr includes a first electrode 20, a second electrode 30, and a control electrode 40. The first electrode 20 is, for example, a source electrode. The second electrode 30 is, for example, a drain electrode. The control electrode 40 is, for example, a gate electrode.

[0019] As shown in FIG. 2, a plurality of first electrodes 20, a plurality of second electrodes 30, and a plurality of control electrodes 40 are arranged, for example, in the Y direction. The first electrodes 20 and the second electrodes 30 are alternately arranged. The control electrode 40 is arranged between the first electrode 20 and the second electrode 30.

[0020] The plurality of first electrodes 20 are electrically connected by, for example, a third wiring 25 extending in the Y direction. The third wiring 25 is, for example, a source wiring. The third wiring 25 is provided so as to be connected to, for example, a first pad electrode 27a and a second pad electrode 27b. The plurality of first electrodes 20, the first pad electrode 27a, and the second pad electrode 27b are arranged side by side in the Y direction, for example. The plurality of first electrodes 20 are provided between the first pad electrode 27a and the second pad electrode 27b. Also, a via hole V1 is provided under the first pad electrode 27a. A via hole V2 is provided under the second pad electrode 27b.

[0021] The plurality of second electrodes 30 each extend in the X direction and are connected to a second wiring TL2, for example.

[0022] The plurality of control electrodes 40 are provided so as to extend in the X direction from a control wiring 41, for example. The control wiring 41 is provided between the transistor Tr and the first wiring TL1 and extends in the Y direction, for example. The control wiring 41 is, for example, a gate bus wiring.

[0023] A fourth wiring 50 is provided between the first wiring TL1 and the control wiring 41. The fourth wiring 50 extends in the Y direction. The first wiring TL1 is electrically connected to the control wiring 41 across the fourth wiring 50. The control wiring 41 and the fourth wiring 50 are each electrically connected to a resistance element RD (see FIG. 3(a)).

[0024] The fourth wiring 50 is electrically connected to a first capacitor C1 and a second capacitor C2. The first capacitor C1, the first wiring TL1, and the second capacitor C2 are arranged side by side in the Y direction, for example. The first wiring TL1 is provided between the first capacitor C1 and the second capacitor C2.

[0025] The first capacitor C1 includes a first metal layer E1 and a second metal layer E2 laminated in the Y direction. The first capacitor C1 includes a dielectric film (not shown), for example, a silicon nitride film provided between the first metal layer E1 and the second metal layer E2. The first metal layer E1 is electrically connected to the fourth wiring 50 via a wiring portion 53. Also, the second metal layer E2 is electrically connected to the first pad electrode 27a via a wiring portion 29a.

[0026] The first metal layer E1 is electrically connected to the control wiring 41 via the fourth wiring 50 and a resistance element RD. The first resistor R1 (see FIG. 1) represents, for example, the electrical resistance between the control wiring 41 and the first metal layer E1.

[0027] The second capacitor C2 includes a first metal layer E3 and a second metal layer E4 laminated in the Y direction. The second capacitor C2 includes another dielectric film (not shown), for example, a silicon nitride film provided between the first metal layer E3 and the second metal layer E4. The first metal layer E3 is electrically connected to the fourth wiring 50 via a wiring portion 57. Also, the second metal layer E4 is electrically connected to the second pad electrode 27b via a wiring portion 29b.

[0028] The first metal layer E3 is electrically connected to the control wiring 41 via the fourth wiring 50 and a resistance element RD. The second resistor R2 (see FIG. 1) represents, for example, the electrical resistance between the control wiring 41 and the first metal layer E3.

[0029] FIGS. 3(a) to (b) are schematic cross-sectional views showing the semiconductor device 1 according to the embodiment. FIG. 3(a) is a cross-sectional view taken along the line A-A shown in FIG. 2. FIG. 3(b) is a cross-sectional view taken along the line B-B shown in FIG. 2. FIG. 3(c) is a cross-sectional view taken along the line C-C shown in FIG. 2.

[0030] As shown in FIG. 3(a), the semiconductor device 1 further includes a semiconductor substrate 10, a first semiconductor layer 13, a second semiconductor layer 15, a resistance layer 17, a high-resistance region 19, and an insulating film 21. The semiconductor substrate 10 includes, for example, silicon carbide (SiC).

[0031] The first semiconductor layer 13 is provided on the semiconductor substrate 10. The first semiconductor layer 13 contains, for example, gallium nitride (GaN). The first semiconductor layer 13 is epitaxially grown on the semiconductor substrate 10 via, for example, a buffer layer (not shown). The first semiconductor layer 13 is, for example, an undoped layer that is not doped with impurities.

[0032] The second semiconductor layer 15 is provided on the first semiconductor layer 13. The second semiconductor layer 15 contains, for example, aluminum gallium nitride mixed crystal (AlGaN). The second semiconductor layer 15 is a so-called barrier layer. The second semiconductor layer 15 contains, for example, n-type impurities and generates a two-dimensional electron gas at the interface with the first semiconductor layer 13.

[0033] The resistance layer 17 is provided on the first semiconductor layer 13. The resistance layer 17 is provided so as to be separated from the second semiconductor layer 15 by the high-resistance region 19. The resistance layer 17 contains a material having the same composition as the second semiconductor layer 15.

[0034] The high-resistance region 19 is formed, for example, by selectively ion-implanting protons or nitrogen into the first semiconductor layer 13 and the second semiconductor layer 15. The high-resistance region 19 electrically separates, for example, between the transistor Tr and the resistance element RD. Also, the high-resistance region 19 electrically separates the transistor Tr and the resistance element RD from other circuit elements (not shown).

[0035] The insulating film 21 is provided so as to cover the first semiconductor layer 13, the second semiconductor layer 15, and the resistance layer 17. The insulating film 21 is, for example, a silicon nitride film.

[0036] The first electrode 20 is provided on the second semiconductor layer 15. The first electrode 20 is electrically connected to the second semiconductor layer 15 via a contact hole provided in the insulating film 21. The first electrode 20 is electrically connected to the second semiconductor layer 15 via, for example, a contact portion 20c extending in the insulating film 21. Also, a third wiring 25 is provided on the first electrode 20. The third wiring 25 is formed, for example, using a plating method.

[0037] The resistive element RD includes, for example, a resistive layer 17, a first terminal 17g, and a second terminal 17f. The first terminal 17g and the second terminal 17f are provided on the resistive layer 17. The first terminal 17g and the second terminal 17f extend, for example, into contact holes provided in the insulating film 21.

[0038] The control wiring 41 is provided on the insulating film 21 and includes a portion located above the resistive layer 17. The fourth wiring 50 is provided above the resistive layer 17 via the second terminal 17f. The control wiring 41 is electrically connected to the resistive layer 17 by the first terminal 17g. The fourth wiring 50 is electrically connected to the resistive layer 17 by the second terminal 17f.

[0039] The first wiring TL1 and the second wiring TL2 are provided on the insulating film 21. The second semiconductor layer 15 is not provided between the first wiring TL1 and the first semiconductor layer 13, nor between the second wiring TL2 and the first semiconductor layer 13.

[0040] The first wiring TL1 includes a first metal layer 43 and a second metal layer 45. The first metal layer 43 is provided on the insulating film 21 using, for example, a vacuum deposition method. The second metal layer 45 is provided on the first metal layer 43 using, for example, a plating method.

[0041] The second metal layer 45 is connected to the control wiring 41 across the fourth wiring 50. An air gap is provided between the second metal layer 45 and the fourth wiring 50. In this way, the first wiring TL1 is electrically connected to the control wiring 41 and electrically insulated from the fourth wiring 50.

[0042] The second wiring TL2 includes a first metal layer 33 and a second metal layer 35. The first metal layer 33 is provided on the insulating film 21 using, for example, a vacuum deposition method. The second metal layer 35 is provided on the first metal layer 33 using, for example, a plating method.

[0043] The via holes V1 and V2 (see FIG. 2) are provided so as to penetrate the semiconductor substrate 10, the first semiconductor layer 13, and the second semiconductor layer 15 from the back surface of the semiconductor substrate 10 and communicate with the first pad electrode 27a and the second pad electrode 27b, respectively. The first pad electrode 27a and the second pad electrode 27b are electrically connected to a metal layer (not shown) provided on the back surface of the semiconductor substrate 10 via via contacts (not shown) provided inside the via holes V1 and V2.

[0044] As shown in FIG. 3(b), the control electrode 40 is provided on the second semiconductor layer 15 with the insulating film 21 interposed therebetween. The insulating film 21 functions as a gate insulating film, for example. The control electrode 40 is provided so as to be connected to the control wiring 41.

[0045] Above the control electrode 40, a third wiring 25 is provided. An air gap is provided between the third wiring 25 and the control electrode 40. The control electrode 40 is electrically insulated from the third wiring 25.

[0046] As shown in FIG. 3(c), the second electrode 30 is provided on the second semiconductor layer 15. The second electrode 30 is electrically connected to the second semiconductor layer 15 via a contact portion 30c. The contact portion 30c extends, for example, into a contact hole provided in the insulating film 21. Further, the second electrode 30 extends along the surface of the insulating film 21, for example, in the X direction, and is provided so as to be connected to the first metal layer 33 of the second wiring TL2. The second electrode 30 is electrically connected to the second wiring TL2.

[0047] Above the second electrode 30, a third wiring 25 is provided. An air gap is provided between the third wiring 25 and the second electrode 30. The second electrode 30 is electrically insulated from the third wiring 25.

[0048] The semiconductor device 1 according to the embodiment is a MMIC (Monolithic Microwave Integrated Circuit) used for microwave amplification. For example, in order to operate an amplification circuit that outputs several watts of microwaves without parasitic oscillation, it is preferable to add a stabilization circuit including a resistor and a capacitor between the gate terminal G and the ground terminal of the transistor Tr.

[0049] Furthermore, in order to output high-power microwaves, it is desirable to increase the gate width of the transistor Tr. For this purpose, a gate structure in which a plurality of source electrodes and drain electrodes are alternately arranged and gate electrodes are respectively arranged between the source and the drain is used. In such a gate structure, the impedance between the gate and the source decreases, and the impedance of the stabilization circuit also becomes smaller. Therefore, when forming the stabilization circuit monolithically, it is preferable to connect a plurality of resistor elements in parallel to reduce the occupied area of the resistor elements.

[0050] However, in such a configuration, the wiring layout becomes complicated and the parasitic inductance increases. For this reason, in the high-frequency region, the effect of the resistor is lost, and the stability factor (K factor) may become 1 or less. Also, when the capacitor is increased in capacitance to offset the increase in parasitic inductance, the chip size also increases.

[0051] FIGS. 4(a) and (b) are schematic diagrams showing a semiconductor device 2 according to a comparative example. FIG. 4(a) is a schematic plan view showing the semiconductor device 2. FIG. 4(b) is a schematic diagram representing the equivalent circuit of the semiconductor device 2.

[0052] As shown in FIG. 4(a), the semiconductor device 2 includes a transistor Tr disposed between a first wiring TL1 and a second wiring TL2. The gate width of the transistor Tr is, for example, 660 μm. In this example, the stabilization circuit including the first resistor R1 and the first capacitor C1 and the first wiring TL1 are arranged in the Y direction. The first resistor R1 is provided between the first wiring and the first capacitor C1. Furthermore, a via hole V3 for grounding the first capacitor C1 is added.

[0053] The first resistor R1 has a configuration in which, for example, four resistor layers (not shown) of 40 Ω are connected in parallel. The first resistor R1 has a resistance value of 10 Ω. The layout of the wiring TL4 connecting the first wiring TL1 and the first resistor R1 is in a comb shape. The capacitance of the first capacitor C1 is 4 pF.

[0054] As shown in FIG. 4(b), in the semiconductor device 2, wirings TL3 and TL4 are added between the gate terminal G of the transistor Tr and the first resistor R1. For this reason, the inductance of the stabilization circuit increases, and the size of the capacitor C1 also increases.

[0055] FIG. 5 is a graph showing the characteristics of the semiconductor device 2 according to the comparative example. The vertical axis represents the stabilization factor (K factor). The horizontal axis represents the frequency. The semiconductor device 2 is driven, for example, by applying a drain voltage of 30 V via an ideal choke (not shown) and a gate voltage of -2.5 V.

[0056] As shown in FIG. 5, in this example, the stabilization factor becomes less than 1 in the frequency range of 9 GHz to 26 GHz, and parasitic oscillation is likely to occur. This is due to an increase in the inductance of the stabilization circuit. Therefore, when using the semiconductor device 2, it is necessary to further add a stabilization circuit for suppressing parasitic oscillation to an external circuit.

[0057] FIG. 6 is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. The vertical axis represents the stabilization factor (K factor). The horizontal axis represents the frequency.

[0058] As shown in FIG. 6, it can be seen that in the semiconductor device 1, at frequencies of 1 GHz or higher, the stabilization factor is greater than 1, and parasitic oscillation can be suppressed. In the frequency band of 1 GHz or lower, the configuration of the stabilization circuit provided in the external circuit can be simplified.

[0059] Thus, in the semiconductor device 1, the connection configuration of the stabilization circuit including the resistance element RD, the first capacitor C1, and the second capacitor C2 can be simplified compared to the semiconductor device 2. Further, by appropriately arranging the resistance element RD, the first capacitor C1, and the second capacitor C2 in the dead space within the planar arrangement (see FIG. 2), miniaturization of the MMIC can be achieved. That is, by arranging the resistance element RD between the first wiring TL1 and the transistor Tr, the space on the gate side of the transistor Tr can be effectively utilized, and the degree of freedom in arranging the capacitors increases.

[0060] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0061] 1, 2... semiconductor devices, 10... semiconductor substrate, 13... first semiconductor layer, 15... second semiconductor layer, 17... resistance layer, 17f... first terminal, 17g... second terminal, 19... high-resistance region, 20... first electrode, 20c, 30c... contact portion, 21... insulating film, 25... third wiring, 27a... first pad electrode, 27b... second pad electrode, 29a, 29b... wiring portion, 30... second electrode, 33, 43, E1, E3... first metal layer, 35, 45, E2, E4... second metal layer, 40... control electrode, 41... control wiring, 50... fourth wiring, 53, 57... wiring portion, C1... first capacitor, C2... second capacitor, S... source end, D... drain end, G... gate end, P1... input end, P2... output end, R1... first resistor, R2... second resistor, RD... resistance element, TL1... first wiring, TL2... second wiring, TL3, TL4... wiring, Tr... transistor, V1, V2, V3... via hole

Claims

1. A transistor having a first electrode, a second electrode, and a control electrode provided between the first electrode and the second electrode; A first wiring electrically connected to the control electrode of the transistor; A resistance element provided between the transistor and the first wiring and including a first terminal electrically connected to the control electrode; A first capacitor electrically connected to a second terminal of the resistance element; A second capacitor; A semiconductor substrate; Comprising; The transistor, the resistance element, and the first wiring are arranged in a first direction; The resistance element and the first capacitor are arranged in a second direction intersecting the first direction; The second capacitor is electrically connected to the second terminal of the resistance element; The resistance element, the first capacitor, and the second capacitor are arranged in the second direction, and the resistance element is provided between the first capacitor and the second capacitor; The transistor, the resistance element, and the first wiring are provided on the surface of the semiconductor substrate; The first electrode and the first capacitor are connected to a reference potential via a first via hole provided in the semiconductor substrate; The second capacitor is connected to the reference potential via a second via hole provided in the semiconductor substrate; In the second direction, the control electrode is between the second via hole and the first via hole; The direction from the first capacitor to the first via hole is along the first direction; The direction from the second capacitor to the second via hole is along the first direction, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first capacitor and the second capacitor each include a first metal layer electrically connected to the resistance element and a second metal layer electrically insulated from the first metal layer and electrically connected to the first electrode of the transistor.

3. Further comprising a second wiring electrically connected to the second electrode of the transistor; The semiconductor device according to claim 1 or 2, wherein the transistor is provided between the first wiring and the second wiring.

4. A first semiconductor layer provided on the semiconductor substrate; A second semiconductor layer partially provided on the first semiconductor layer; A resistance layer provided on the first semiconductor layer and spaced apart from the second semiconductor layer; Further comprising; The first electrode, the second electrode, and the control electrode of the transistor are provided on the second semiconductor layer. The semiconductor device according to any one of claims 1 to 3, wherein the first terminal and the second terminal of the resistance element are provided on the resistance layer.

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