Memory Cells and Storage Devices

Abstract

Provided is a storage device that occupies a small occupancy area. This memory cell provided with a read-out transistor, a write-in transistor, and a storage capacitor is configured to have the write-in transistor provided above the read-out transistor. Alternatively, the read-out transistor is provided above the write-in transistor. An oxide semiconductor is employed in a semiconductor layer where a channel for the write-in transistor is formed. An oxide semiconductor is employed in a semiconductor layer where a channel for the read-out transistor is formed. A plurality of the memory cells are arranged in a matrix configuration.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may include semiconductor elements and semiconductor circuits. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices. [Background technology]

[0004] BACKGROUND ART In recent years, transistors using an oxide semiconductor or a metal oxide for a channel formation region (oxide semiconductor transistors, hereinafter referred to as OS transistors) have attracted attention (Patent Document 1).

[0005] OS transistors have an extremely small off-state current. Utilizing this, Patent Documents 2 and 3 disclose nonvolatile memories using OS transistors. Nonvolatile memories using OS transistors have no limit to the number of times data can be rewritten, and consume little power when rewriting data. Patent Document 3 also discloses an example of a nonvolatile memory memory cell constructed using only OS transistors.

[0006] In this specification, nonvolatile memory using OS transistors may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to RAM with gain cell type (2T type, 3T type) memory cells. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-115387 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a memory device with a small occupation area.An object of one embodiment of the present invention is to provide a highly reliable memory device.An object of one embodiment of the present invention is to provide a memory device with a large storage capacity.An object of one embodiment of the present invention is to provide a memory device with low manufacturing costs.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing costs.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a memory cell including a read transistor, a write transistor, and a capacitor, in which the write transistor is provided above the read transistor. The read transistor may be provided above the write transistor. An oxide semiconductor is used for a semiconductor layer in which a channel of the write transistor is formed. An oxide semiconductor is preferably used for the semiconductor layer in which a channel of the read transistor is formed. A plurality of memory cells are preferably arranged in a matrix.

[0011] Another embodiment of the present invention is a memory cell including a first transistor, a second transistor, and a capacitor, wherein one of a source or a drain of the first transistor is electrically connected to a first wiring, the other of the source or the drain of the first transistor is electrically connected to a second wiring, one of the source or the drain of the second transistor is electrically connected to a third wiring, the other of the source or the drain of the second transistor is electrically connected to a gate of the first transistor, the gate of the second transistor is electrically connected to a fourth wiring, a capacitor is provided between the gate of the first transistor and a fifth wiring, and the second transistor is provided above the first transistor, wherein the first transistor includes a first oxide semiconductor and the second transistor includes a second oxide semiconductor.

[0012] It is preferable that the channel length of the first transistor is longer than the channel length of the second transistor.

[0013] Another embodiment of the present invention is a memory device including a plurality of the above-described memory cells, including m first wirings and n fourth wirings, where the memory cells are arranged in a matrix of m rows and n columns (m and n are integers of 2 or greater), where the i-th (i is an integer of 1 to m) first wiring is electrically connected to the memory cell arranged in the i-th row, and the j-th (j is an integer of 1 to n) fourth wiring is electrically connected to the memory cell arranged in the j-th column.

[0014] The first oxide semiconductor preferably contains at least one of indium and zinc. The second oxide semiconductor preferably contains at least one of indium and zinc. The first transistor preferably has a back gate. The second transistor preferably has a back gate. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a memory device with a small occupation area can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable memory device can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a memory device with low manufacturing cost can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low manufacturing cost can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0016] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0017] 1A and 1B are a plan view and a cross-sectional view of a memory cell, respectively. FIG. 2 is a cross-sectional view of a memory cell. 3A and 3B are cross-sectional views of a transistor. 4A and 4B are cross-sectional views of a memory cell. 5A to 5C are circuit diagrams of memory cells. Figure 6A is a diagram illustrating the classification of crystalline structures of oxide semiconductors, Figure 6B is a diagram illustrating the XRD spectrum of a CAAC-IGZO film, and Figure 6C is a diagram illustrating the electron microbeam diffraction pattern of a CAAC-IGZO film. 7A and 7B are block diagrams and perspective views illustrating an example of the configuration of a semiconductor device. Fig. 8A is a block diagram illustrating an example of the configuration of a cell array, and Fig. 8B is a circuit diagram of a memory cell. Fig. 9A is a block diagram illustrating an example of the configuration of a cell array, and Fig. 9B is a circuit diagram of a memory cell. FIG. 10 is a cross-sectional view of a memory cell. FIG. 11 is a diagram showing various storage devices by hierarchical level. 12A to 12E are diagrams for explaining application examples of the storage device. 13A to 13H are diagrams showing electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0019] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0020] In addition, in the drawings and the like, the illustration of some components may be omitted in order to make the explanation easier to understand.

[0021] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0022] In this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0023] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0024] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0025] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0026] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of, for example, -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to a state in which two straight lines are arranged at an angle of, for example, 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0027] In this specification and elsewhere, when referring to counting values and measurement values, or to objects, methods, and events that can be converted into counting values or measurement values, terms such as "identical," "same," "equal," or "uniform" are intended to include an error of plus or minus 20%, unless otherwise specified.

[0028] Furthermore, in this specification, the terms "adjacent" and "close to" do not necessarily mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0029] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0030] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0031] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0032] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0033] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0034] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0035] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0036] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0037] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0038] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0039] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0040] In addition, in drawings, etc., to make the potential of wiring, electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written next to the transistor.

[0041] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0042] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "_1", "_2", "[n]", "[m,n]", etc. For example, the second wiring GL may be described as wiring GL[2].

[0043] (Embodiment 1) A structural example of a memory cell 10, which is a memory device according to one embodiment of the present invention, will be described with reference to the drawings.

[0044] FIG. 1A is a plan view of memory cell 10. FIGS. 1B and 2 are cross-sectional views of portion A1-A2 indicated by the dashed-dotted line in FIG. 1A. FIG. 3A is an enlarged view of transistor 120 shown in FIGS. 1B and 2. FIG. 3B is an enlarged view of transistor 110 shown in FIGS. 1B and 2.

[0045] Fig. 4A is a cross-sectional view of a portion B1-B2 indicated by a dashed-dotted line in Fig. 1A. Fig. 4B is a cross-sectional view of a portion C1-C2 indicated by a dashed-dotted line in Fig. 1A. Figs. 5A to 5C are circuit diagrams showing examples of circuit configurations of memory cell 10.

[0046] 1B, 2, 3A, and 3B show cross sections of the transistor in the channel length direction. 4A and 4B show cross sections of the transistor in the channel width direction. Note that for ease of explanation, some components are omitted from Figure 1 and other figures.

[0047] In the drawings and the like, arrows indicating the X direction, Y direction, and Z direction may be used. The X direction, Y direction, and Z direction are mutually orthogonal. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." Furthermore, one of the other two directions may be referred to as the "second direction" or "second direction." Furthermore, the remaining one may be referred to as the "third direction" or "third direction."

[0048] <Configuration example of memory cell 10> First, an example of a circuit configuration of the memory cell 10 will be described. As shown in FIG. 5A, the memory cell 10 includes a transistor 110 and a transistor 120. One of the source or drain of the transistor 110 is electrically connected to a wiring RBL, and the other is electrically connected to a wiring SL. The backgate of the transistor 110 is electrically connected to a wiring BGL1. One of the source or drain of the transistor 120 is electrically connected to a wiring WBL, and the other is electrically connected to a gate of the transistor 110. The gate of the transistor 120 is electrically connected to a wiring WL, and the backgate is electrically connected to a wiring BGL2.

[0049] The memory cell 10 also includes a capacitor 130 between the gate of the transistor 110 and the wiring CL. Alternatively, the capacitor 130 is included between the other of the source or the drain of the transistor 120 and the wiring CL. In this specification and other documents, a node where the gate of the transistor 110 and the other of the source or the drain of the transistor 120 are electrically connected is referred to as a node FN. Therefore, the memory cell 10 includes the capacitor 130 between the node FN and the wiring CL.

[0050] The memory cell 10 has a function of retaining the potential (charge) written to the node FN. Specifically, a voltage that turns on the transistor 120 is supplied to the gate of the transistor 120, thereby bringing the wiring WBL and the node FN into electrical continuity. Then, a charge for setting the node FN to a predetermined voltage is supplied to the node FN through the wiring WBL. Then, a voltage that turns off the transistor 120 is supplied to the gate of the transistor 120. By turning off the transistor 120, the charge written to the node FN is retained.

[0051] The semiconductor layers of the transistor 120 and the transistor 110 can be formed using a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or a combination of these. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0052] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0053] In particular, the transistor 120 is preferably an OS transistor. An oxide semiconductor has a band gap of 2 eV or more, and therefore has a significantly low off-state current. When an OS transistor is used as the transistor 120, charge written to the node FN can be held for a long period of time. By using an OS transistor as the transistor 120, the capacitance 130 can be reduced. Alternatively, the capacitance 130 can be reduced. Therefore, the area occupied by the memory cell 10 can be reduced. When an OS transistor is used as the transistor 120, the memory cell 10 can be called an "OS memory."

[0054] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0055] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0056] Furthermore, because OS memory writes charge to nodes via OS transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required before rewriting data, as is done with flash memory. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for a virtually unlimited number of data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, ensuring high reliability.

[0057] In addition, OS memory does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0058] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory operates stably and has high reliability even in a high-temperature environment. Furthermore, an OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be realized.

[0059] 5B, the back gates of the transistors 120 and 110 may be connected to a common wiring. In FIG. 5B, the back gates are connected to a wiring BGL2.

[0060] 5C , a configuration may be adopted in which the back gates of the transistors 120 and 110 are not provided, as necessary. Also, a configuration may be adopted in which the back gates of either the transistors 120 and 110 are not provided.

[0061] Next, we will explain an example of the stacked structure of the memory cell 10. The memory cell 10 according to one aspect of the present invention has a write layer 11W and a read layer 11R (see FIGS. 1A, 1B, and 2).

[0062] The write layer 11W includes a transistor 120 and a capacitor 130, and the read layer 11R includes a transistor 110. Therefore, in this embodiment and the like, the transistor 120 is provided above the transistor 110. By providing the transistor 120 and the transistor 110 along the Z direction, the area occupied by the memory cell 10 can be reduced. Furthermore, the recording density per unit area can be increased.

[0063] Although the write layer 11W is provided over the readout layer 11R in this embodiment and the like, one embodiment of the present invention is not limited thereto. The readout layer 11R may be provided over the write layer 11W. That is, although the transistor 120 is provided above the transistor 110 in this embodiment and the like, the transistor 110 may be provided above the transistor 120. Note that when the transistor 110 is referred to as a "readout transistor," the transistor 120 may be referred to as a "write transistor."

[0064] The memory cell 10 shown in FIGS. 1A, 1B, and 2 has a conductor 338 on an insulator 301 and an insulator 302 on the conductor 338. The conductor 338 functions as a wiring RBL. The memory cell 10 also has an insulator 312 on the insulator 302, an insulator 314 on the insulator 312, and an insulator 316 on the insulator 314. The memory cell 10 also has a conductor 303 disposed so as to be embedded in the insulators 302, 312, and 314. The memory cell 10 also has a conductor 304 and a conductor 305 (conductor 305a, conductor 305b, and conductor 305c) disposed so as to be embedded in the insulator 316. The memory cell 10 also has an insulator 322 on the insulator 316, the conductor 304, and the conductor 305, an insulator 324 on the insulator 322, an oxide 330a_1 on the insulator 324, and an oxide 330b_1 on the oxide 330a_1.

[0065] The memory cell 10 also has an oxide 343a and an oxide 343b on the oxide 330b_1, a conductor 342a on the oxide 343a, and a conductor 342b on the oxide 343b. In this specification and other documents, the oxide 343a and the oxide 343b may be collectively referred to as the oxide 343. The conductor 342a and the conductor 342b may be collectively referred to as the conductor 342.

[0066] One of the conductor 342a and the conductor 342b functions as a source electrode of the transistor 110, and the other functions as a drain electrode.

[0067] The memory cell 10 also includes an insulator 375 disposed over the conductor 342 and an insulator 380 on the insulator 375. An opening reaching the oxide 330b_1 is provided in the insulator 380 and the insulator 375. The oxide 330c_1, the insulator 350, and the conductor 360 (the conductor 360a and the conductor 360b) are disposed in the opening.

[0068] In this specification and the like, the oxide 330a_1, the oxide 330b_1, and the oxide 330c_1 may be collectively referred to as the oxide 330_1.

[0069] The oxide 330c_1 is provided in contact with the upper surface of the oxide 330b_1 overlapping the opening, the side surface of the oxide 343, the side surface of the conductor 342, the side surface of the insulator 375, and the side surface of the insulator 380. The insulator 350 is provided adjacent to the upper surface of the oxide 330b_1 overlapping the opening, the side surface of the oxide 343, the side surface of the conductor 342, the side surface of the insulator 375, and the side surface of the insulator 380, with the oxide 330c_1 interposed therebetween. The conductor 360 is preferably provided in contact with the insulator 350. As shown in FIGS. 2 and 3B , the upper surfaces of the conductor 360, the insulator 350, and the oxide 330c_1 are arranged so as to substantially coincide with the upper surface of the insulator 380.

[0070] The openings are provided between the conductor 342a and the conductor 342b and between the oxide 343a and the oxide 343b. Therefore, the conductor 360 is provided between the conductor 342a and the conductor 342b and between the oxide 343a and the oxide 343b.

[0071] The memory cell 10 also has an insulator 335 over the insulator 380 and the conductor 360. A contact plug 359 is embedded in the insulator 335, the insulator 380, the insulator 375, the conductor 342a, the oxide 343a, the oxide 330b_1, the oxide 330a_1, the insulator 324, and the insulator 322. An insulator 323 may be provided on a side surface of the contact plug 359. The conductor 342a is electrically connected to the conductor 338 via the contact plug 359, the conductor 304, and the conductor 303.

[0072] Furthermore, a contact plug 352 is embedded in the insulator 335, the insulator 380, and the insulator 375. The contact plug 352 is electrically connected to the conductor 342b.

[0073] The memory cell 10 also has an insulator 326 over an insulator 335, and a conductor 353 and a conductor 332 are embedded in the insulator 326. The conductor 332 is electrically connected to the conductor 342b through a contact plug 352. The conductor 332 functions as a wiring SL.

[0074] Furthermore, a conductor 354 is embedded in the insulator 326 and the insulator 335. The conductor 354 is electrically connected to the conductor 360. Furthermore, it is preferable to provide a conductor 348 on the contact plug 359. The conductor 348, like the conductor 353, is embedded in the insulator 326 and the insulator 335. By providing the conductor 348 on the contact plug 359, it is possible to suppress impurity diffusion from above into the contact plug 359. It is preferable that the conductors 353, 354, 332, and 348 have the same structure as the conductor 305 described below.

[0075] Furthermore, insulator 327 is provided over insulator 326, conductor 353, conductor 354, and conductor 332, and insulator 328 is provided over insulator 327. Oxide 330a_2 is provided over insulator 328, and oxide 330b_2 is provided over oxide 330a_2. Oxide 345a and oxide 345b are provided over oxide 330b_2. Conductor 344a is provided over oxide 345a, and conductor 344b is provided over oxide 345b. In this specification and elsewhere, oxide 345a and oxide 345b may be collectively referred to as oxide 345. Conductor 344a and conductor 344b may be collectively referred to as conductor 344.

[0076] One of the conductor 344a and the conductor 344b functions as a source electrode of the transistor 120, and the other functions as a drain electrode.

[0077] The memory cell 10 also has an insulator 329 arranged to cover the conductor 344 and an insulator 384 on the insulator 329. An opening reaching the oxide 330b_2 is provided in the insulator 329 and the insulator 384. The oxide 330c_2, the insulator 351, and the conductor 361 (the conductor 361a and the conductor 361b) are arranged in the opening.

[0078] In this specification and the like, the oxide 330a_2, the oxide 330b_2, and the oxide 330c_2 may be collectively referred to as the oxide 330_2. Furthermore, the oxide 330_1 and the oxide 330_2 may be collectively referred to as the oxide 330.

[0079] The oxides 330a_1 and 330a_2 may be collectively referred to as the oxide 330a. The oxides 330b_1 and 330b_2 may be collectively referred to as the oxide 330b. The oxides 330c_1 and 330c_2 may be collectively referred to as the oxide 330c.

[0080] The oxide 330c_2 is provided in contact with the upper surface of the oxide 330b_2 overlapping the opening, the side surface of the oxide 345, the side surface of the conductor 344, the side surface of the insulator 329, and the side surface of the insulator 384. The insulator 351 is provided adjacent to the upper surface of the oxide 330b_2 overlapping the opening, the side surface of the oxide 345, the side surface of the conductor 344, the side surface of the insulator 329, and the side surface of the insulator 384, with the oxide 330c_2 interposed therebetween. The conductor 361 is preferably provided in contact with the insulator 351. As shown in FIGS. 2 and 3A , the upper surfaces of the conductor 361, the insulator 351, and the oxide 330c_2 are disposed so as to substantially coincide with the upper surface of the insulator 384.

[0081] The openings are provided between the conductor 344a and the conductor 344b and between the oxide 345a and the oxide 345b. Therefore, the conductor 361 is provided between the conductor 344a and the conductor 344b and between the oxide 345a and the oxide 345b.

[0082] The insulator 384 and the insulator 329 have openings that reach the conductor 344b. The insulator 331 and the conductor 341 are disposed in the openings. The conductor 341 functions as a wiring CL. The conductor 341 and the conductor 344b have an overlapping region with the insulator 331 interposed therebetween. The overlapping region functions as the capacitor 130.

[0083] The memory cell 10 also has an insulator 334 on the insulator 384 and the conductor 361. A contact plug 356 is embedded in the insulator 334, the insulator 384, the insulator 329, the conductor 344a, the oxide 345a, the oxide 330b_2, the oxide 330a_2, the insulator 328, and the insulator 327. The conductor 344b is electrically connected to the conductor 360 via the contact plug 356 and the conductor 354.

[0084] A contact plug 355 is embedded in the insulator 334, the insulator 384, and the insulator 329. The contact plug 355 is electrically connected to the conductor 344a.

[0085] Furthermore, the memory cell 10 has an insulator 336 on the insulator 334, and an insulator 337 on the insulator 336. A conductor 357 is embedded in the insulators 336 and 337. The conductor 357 is provided on a contact plug 355. A conductor 349 may also be provided on the contact plug 356. The conductor 349 is embedded in the insulators 336 and 337. The conductor 349 and the conductor 357 may have the same structure as the conductor 305 described below.

[0086] The memory cell 10 also has an insulator 378 on the insulator 337 and the conductor 357, and the conductor 358 is embedded in the insulator 378. The memory cell 10 also has a conductor 339 on the conductor 358 and the insulator 378. The conductor 339 is electrically connected to the conductor 344a via the conductor 358, the conductor 357, and the contact plug 355. The conductor 339 functions as a wiring WBL.

[0087] Note that an insulator similar to the insulator 323 may be provided on the side surfaces of the contact plug 352 , the contact plug 355 , and the contact plug 356 .

[0088] The conductor 361 functions as a gate electrode of the transistor 120 and also functions as a wiring WL. The conductor 360 functions as a gate electrode of the transistor 110 and also functions as a node FN.

[0089] The insulators 350 and 351 function as gate insulators (also referred to as "first gate insulators"). The insulators 324 and 322, and the insulators 328 and 327 function as back-gate insulators (also referred to as "second gate insulators").

[0090] The conductor 353 functions as a backgate electrode of the transistor 120 and also functions as a wiring BGL2. The conductor 305 functions as a backgate electrode of the transistor 110 and also functions as a wiring BGL1.

[0091] 1B and 2, the conductor 353 functioning as the back gate electrode of the transistor 120 is provided on the readout layer 11R side. Therefore, it can be said that a part of the transistor 120 provided in the write layer 11W is provided on the readout layer 11R side.

[0092] At least a part of a region of the oxide 330_1 that overlaps with the conductor 360 functions as a channel formation region. Similarly, at least a part of a region of the oxide 330_2 that overlaps with the conductor 361 functions as a channel formation region.

[0093] For example, the oxide 330_1 and the oxide 330_2 each have a region 333c that functions as a channel formation region of the transistor and a region 333sd that functions as a source region or drain region (see FIGS. 3A and 3B). In the transistor 110, the region 333c at least partially overlaps with the conductor 360. In other words, the region 333c is provided in a region between the conductor 342a and the conductor 342b. The region 333sd is provided so as to overlap with the conductor 342. Note that the oxide 330_2 included in the transistor 120 is similar to the oxide 330_1 included in the transistor 110.

[0094] The oxide 330_1 and the oxide 330_2 may have the same composition or different compositions.

[0095] The region 333c, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the region 333sd, and is therefore a high-resistance region with a low carrier concentration. The region 333sd, which functions as a source or drain region, has many oxygen vacancies or a high impurity concentration such as hydrogen, nitrogen, or a metal element, which increases the carrier concentration and reduces the resistance. That is, the region 333sd has a higher carrier concentration and a lower resistance than the region 333c.

[0096] Here, the carrier concentration of the region 333c functioning as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 333c functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm-3 It can be said that:

[0097] Furthermore, a region may be formed between the region 333c and the region 333sd, whose carrier concentration is equal to or lower than that of the region 333sd and equal to or higher than that of the region 333c. That is, this region functions as a junction region between the region 333c and the region 333sd. The junction region may have a hydrogen concentration equal to or lower than that of the region 333sd and equal to or higher than that of the region 333c. The junction region may also have oxygen vacancies equal to or lower than those of the region 333sd and equal to or higher than those of the region 333c.

[0098] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 330. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0099] A metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 330 including the channel formation region. The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with such a wide band gap, the off-state current of the transistor can be reduced.

[0100] By reducing the off-state current of the transistor 110, leakage current between the wiring RBL and the wiring SL can be significantly reduced, thereby significantly reducing power consumption of the memory cell 10. Furthermore, by reducing the off-state current of the transistor 120, data retention time of the memory cell 10 can be significantly extended.

[0101] The oxide 330 may be, for example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). For example, the oxide 330 may be In-Ga-Zn oxide, or an oxide obtained by adding tin to In-Ga-Zn oxide (In-Ga-Zn-Sn oxide). Alternatively, the oxide 330 may be In-Ga oxide, In-Zn oxide, or indium oxide.

[0102] The metal oxide can be deposited on a substrate using a sputtering method or the like. Therefore, a memory cell array can be provided over a peripheral circuit, such as a driver circuit, formed on a silicon substrate. This reduces the area occupied by the peripheral circuitry on one chip and increases the area occupied by the memory cell array, thereby increasing the memory capacity of the semiconductor device. Furthermore, by depositing multiple layers of the metal oxide film, the memory cell array can be provided in a stacked configuration. This allows cells to be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D cell array can be configured. Therefore, a semiconductor device with a high memory capacity can be provided by achieving high integration of memory cells.

[0103] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V OH.) and may generate electrons that serve as carriers even when no voltage is applied to the gate electrode of the transistor. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, when no voltage is applied to the gate electrode of the transistor, the region in the oxide semiconductor where a channel is formed preferably has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0104] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-state current or a decrease in field-effect mobility of the transistor. Furthermore, if the oxygen supplied to the source or drain region varies within the substrate plane, the characteristics of the semiconductor device having the transistor will vary.

[0105] Therefore, in the oxide semiconductor, the region 333c that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the region 333sd that functions as a source region or drain region preferably has a high carrier concentration and is n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the region 333sd.

[0106] For example, in manufacturing the transistor 110, openings that overlap with the oxide 330b_1 are formed in parts of the insulator 380 and the insulator 375, and the oxide 330c_1 and the insulator 350 are formed in the openings. Then, microwave treatment is performed in an oxygen-containing atmosphere to remove oxygen vacancies in the region 333c and V O In this case, the oxygen vacancies in the oxide 330c_1 and V O The H is also reduced. Here, the microwave treatment refers to a treatment using, for example, an apparatus having a power supply that generates high-density plasma using microwaves. Note that the microwave treatment may be performed before the formation of the insulator 350.

[0107] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto region 333c. The V of region 333c can be activated by the action of plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 333c, and oxygen vacancies V O can be compensated with oxygen. O H→H+V O This reaction occurs, and the hydrogen concentration in the region 333c can be reduced. O H can be reduced to lower the carrier concentration.

[0108] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 342a and 342b and do not reach the region 333sd. Furthermore, the effects of oxygen plasma can be reduced by the insulators 375 and 380. As a result, during microwave processing, V O A reduction in H and an excessive supply of oxygen do not occur, and a decrease in the carrier concentration in the region 333sd can be prevented.

[0109] In this way, oxygen vacancies and V O By removing H, the region 333c can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region 333sd, which functions as a source region or a drain region, can be prevented, maintaining the n-type conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 110, and suppresses variations in the electrical characteristics of the transistor 110 within the substrate surface.

[0110] When forming the transistor 120, microwave treatment can be performed in the same manner as for the transistor 110.

[0111] By configuring the transistor 120 and the transistor 110 as described above, a semiconductor device with little variation in transistor characteristics can be provided. Furthermore, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device with good reliability can be provided.

[0112] The length of the region 333c in the X direction is defined as the channel length L (see FIGS. 3A and 3B). For example, the channel length L of the transistor 110 is the shortest distance from the end of the conductor 342a to the end of the conductor 342b in the region overlapping with the oxide 330_1 when viewed from the Z direction. The channel length L of the transistor 120 is the shortest distance from the end of the conductor 344a to the end of the conductor 344b in the region overlapping with the oxide 330_2 when viewed from the Z direction.

[0113] The length of the region 333c in the Y direction is defined as the channel width W (see FIGS. 4A and 4B). For example, the channel width W of the transistor 110 is the shortest distance from one end to the other end of the oxide 330b_1 in the region 333c in the Y direction when viewed from the Z direction. For example, the channel width W of the transistor 120 is the shortest distance from one end to the other end of the oxide 330b_2 in the region 333c in the Y direction when viewed from the Z direction.

[0114] As described above, the memory cell 10 according to one embodiment of the present invention does not require the high voltage required in conventional flash memories. Therefore, the channel length L of the transistor can be shortened. This allows the operating speed of the memory cell 10 to be increased. Furthermore, the area occupied by the memory cell 10 can be reduced.

[0115] The channel length L of the transistor 110 and the channel length L of the transistor 120 may be the same or different. By shortening the channel length L of the transistor 110, the read speed of the memory cell 10 can be increased. By shortening the channel length L of the transistor 120, the write speed of the memory cell 10 can be increased.

[0116] The channel width W of the transistor 110 and the channel width W of the transistor 120 may be the same or different. Increasing the channel width W of the transistor 110 can increase the read speed of the memory cell 10. Increasing the channel width W of the transistor 120 can increase the write speed of the memory cell 10.

[0117] Furthermore, by increasing the channel length L, it is possible to reduce variations in Vth of the transistor. Therefore, it is preferable that the channel length L of the transistor 110 functioning as a read transistor is long. In particular, when multilevel information is stored in the memory cell 10, it is preferable that the channel length L of the transistor 110 is long.

[0118] By shortening the channel length L of the transistor 120 functioning as a writing transistor and lengthening the channel length L of the transistor 110 functioning as a reading transistor, a memory cell with high write speed and high read accuracy can be realized.

[0119] The side surfaces of the openings into which the conductors 360 and the like are embedded and / or the side surfaces of the openings into which the conductors 361 and the like are embedded, including the grooves in the oxide 330b, may be approximately perpendicular to the surface on which the oxide 330b is to be formed. However, this embodiment is not limited to this. For example, the bottom of the opening may have a gently curved U-shape. Furthermore, for example, the side surfaces of the openings may be inclined with respect to the surface on which the oxide 330b is to be formed.

[0120] 4A, in a cross-sectional view of the transistor 110 in the channel width direction, a curved surface may be formed between the side surface of the oxide 330b_1 and the top surface of the oxide 330b_1. That is, the ends of the side surface and the top surface may be curved (hereinafter also referred to as rounded). Similarly, as shown in FIG. 4B, in a cross-sectional view of the transistor 120 in the channel width direction, a curved surface may be formed between the side surface of the oxide 330b_2 and the top surface of the oxide 330b_2.

[0121] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 330b_1 (or oxide 330b_2) in the region overlapping with the conductor 342 (or conductor 344), or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the insulator 350 (or insulator 351) and the conductor 360 (or conductor 361) with the oxide 330b_1 (or oxide 330b_2).

[0122] The oxide 330 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxides used for the oxides 330a and 330c, the atomic ratio of the element M to the main metal element is preferably greater than the atomic ratio of the element M to the main metal element in the metal oxide used for the oxide 330b. Furthermore, in the metal oxides used for the oxides 330a and 330c, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 330b. Furthermore, in the metal oxide used for the oxide 330b, the atomic ratio of In to M is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxides 330a and 330c.

[0123] The oxide 330c may have the same composition as the oxide 330b. Alternatively, the oxide 330c may have a stacked structure in which an oxide having the same composition as the oxide 330b and an oxide having the same composition as the oxide 330a are stacked on top of the oxide having the same composition as the oxide 330b.

[0124] Under these conditions, by placing oxide 330a below oxide 330b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below oxide 330a to oxide 330b. Similarly, by placing oxide 330c on oxide 330b, it is possible to suppress the diffusion of impurities and oxygen from structures formed above oxide 330c to oxide 330b.

[0125] The oxide 330b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS contain impurities and defects (oxygen vacancies (V OThe OS transistor has a dense structure with low oxygen vacancy and high crystallinity. This can prevent the source or drain electrode from extracting oxygen from the oxide 330b. This reduces the amount of oxygen extracted from the oxide 330b even when heat treatment is performed, making the OS transistor stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0126] In particular, the CAAC-OS can be made to have a denser structure with higher crystallinity by heat treatment at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not become polycrystallized. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0127] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0128] Here, the conduction band minimum changes smoothly at the junction between the oxides 330a and 330b and at the junction between the oxides 330c and 330b. In other words, the conduction band minimum at the junction between the oxides 330a and 330b and at the junction between the oxides 330c and 330b can be said to change continuously or form a continuous junction. To achieve this, it is advisable to reduce the defect level density in the mixed layers formed at the interfaces between the oxides 330a and 330b and between the oxides 330c and 330b.

[0129] Specifically, when the oxide 330a, the oxide 330b, and the oxide 330c contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 330b is an In-M-Zn oxide, the oxide 330a and the oxide 330c may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0130] For example, oxide 330a and oxide 330c may be metal oxides having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 330b may be metal oxides having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0131] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0132] By configuring the oxide 330a, the oxide 330b, and the oxide 330c as described above, the density of defect states at the interface between the oxide 330a and the oxide 330b can be reduced. Furthermore, the density of defect states at the interface between the oxide 330c and the oxide 330b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the OS transistor can achieve high field-effect mobility, high on-state current, and high frequency characteristics. Using such a transistor as the transistor 120 can improve the write speed. Using such a transistor as the transistor 110 can improve the read speed.

[0133] At least one of the insulators 312, 314, 334, and 336 preferably functions as a barrier insulating layer that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 120 into the transistor 120, the transistor 110, etc. Furthermore, the insulator 323 preferably functions as a barrier insulating layer that suppresses diffusion of impurities such as hydrogen from the side of the contact plug 359 into the contact plug 359.

[0134] Therefore, it is preferable that at least one of insulators 312, 314, 334, 336, and 323 be made of an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., the impurities are less likely to permeate through them). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., the oxygen is less likely to permeate through them). Furthermore, insulator 375 and / or insulator 329 may be made of an insulating material that has the function of suppressing the diffusion of impurities. Furthermore, insulator 375 and / or insulator 329 may be made of an insulating material that has the function of suppressing the diffusion of oxygen.

[0135] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0136] For example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used for the insulators 312, 314, 334, 336, 375, and 329. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 312 and 336. For example, aluminum oxide, which has a high hydrogen capture and fixation function, is preferably used for the insulators 314, 375, 329, and 334. This can prevent impurities such as water and hydrogen from diffusing from the insulator 301 to the transistors 120 and 110 through the insulators 312 and 314. Alternatively, it can prevent impurities such as water and hydrogen from diffusing from insulators located outside the insulator 378 to the transistors 120 and 110. Alternatively, oxygen contained in the insulator 316 and the like can be prevented from diffusing toward the substrate through the insulators 312 and 314. Alternatively, oxygen contained in the insulators 380 and 384 and the like can be prevented from diffusing upward from the transistor 120 through the insulator 378 and the like. In this way, it is preferable to have a structure in which the transistor 120, the transistor 110, and the like are surrounded by the insulators 312, 314, 334, and 336, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0137] The insulators 312, 314, 334, 336, 375, and 329 can be deposited by, for example, a sputtering method. Sputtering does not require the use of hydrogen as a deposition gas, and therefore can reduce the hydrogen concentration in the insulators 312, 314, 334, 336, 375, and 329. Note that the deposition method is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0138] It may also be preferable to reduce the resistivity of the insulators 312 and 336. For example, it may be preferable to reduce the resistivity of the insulators 312 and 336 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 312 and the insulator 336 may be able to reduce charge-up of the conductor 305, the conductor 342, the conductor 360, the conductor 344, or the conductor 361 during treatment using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 312 and the insulator 336 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0139] The insulators 316, 380, 326, and 384 preferably have a lower dielectric constant than the insulator 314. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 316, 380, 326, and 384 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0140] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen, and the term "aluminum nitride oxide" refers to an aluminum material that contains more nitrogen than oxygen.

[0141] The conductor 305 includes conductor 305a, conductor 305b, and conductor 305c. conductor 305a is provided in contact with the bottom surface and sidewall of the opening. conductor 305b is provided so as to be embedded in a recess formed in conductor 305a. Here, the top surface of conductor 305b is lower than the top surface of conductor 305a and the top surface of insulator 316. conductor 305c is provided in contact with the top surface of conductor 305b and the side surface of conductor 305a. Here, the height of the top surface of conductor 305c is approximately the same as the height of the top surface of conductor 305a and the height of the top surface of insulator 316. In other words, conductor 305b is configured to be enclosed by conductors 305a and 305c.

[0142] Here, the conductors 305a and 305c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0143] By using a conductive material capable of reducing hydrogen diffusion for the conductors 305a and 305c, impurities such as hydrogen contained in the conductor 305b can be prevented from diffusing into the oxide 330 via the insulator 324 or the like. Furthermore, by using a conductive material capable of suppressing oxygen diffusion for the conductors 305a and 305c, it is possible to prevent the conductor 305b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 305a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 305a may be made of titanium nitride.

[0144] The conductor 305b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0145] The conductor 305 may function as a back gate electrode. In this case, the Vth of the transistor 110 can be controlled by changing the potential applied to the conductor 305 independently of the potential applied to the conductor 360. Furthermore, applying a negative potential to the conductor 305 can increase the Vth of the transistor 110 and reduce its off-state current. Therefore, applying a negative potential to the conductor 305 can reduce the drain current when the potential applied to the conductor 360 is 0 V compared to not applying a negative potential to the conductor 305.

[0146] The electrical resistivity of the conductor 305 is designed taking into account the potential supplied to the conductor 305, and the film thickness of the conductor 305 is set to match this electrical resistivity. The film thickness of the insulator 316 is approximately the same as that of the conductor 305. Here, it is preferable to make the film thicknesses of the conductor 305 and the insulator 316 as thin as possible within the range permitted by the design of the conductor 305. By making the film thickness of the insulator 316 thin, the absolute amount of impurities such as hydrogen contained in the insulator 316 can be reduced, thereby reducing the diffusion of the impurities into the oxide 330.

[0147] Note that the conductor 305 is preferably larger than the size of a region of the oxide 330 that does not overlap with the conductors 342a and 342b in the channel length direction of the transistor 110 (see FIG. 3B). Furthermore, as shown in FIG. 4A, the conductor 305 preferably extends to a region outside the end portions of the oxides 330a_1 and 330b_1 that intersect with the channel width direction. That is, the conductor 305 and the conductor 360 preferably overlap with each other with an insulator interposed therebetween outside the side surfaces of the oxides 330a_1 and 330b_1 in the channel width direction. With this structure, the channel formation region of the oxide 330 can be electrically surrounded by the electric field of the conductor 360 that functions as a gate electrode (also referred to as a "first gate electrode") and the electric field of the conductor 305 that functions as a backgate electrode (also referred to as a "second gate electrode"). In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0148] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0149] The conductor 305 is also extended in the channel width direction to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 305.

[0150] Note that although the transistor 110 illustrates a case where the conductor 305 has a stacked structure of the conductor 305a, the conductor 305b, and the conductor 305c, the present invention is not limited to this. For example, the conductor 305 may have a single-layer structure, a two-layer structure, or a four-layer or more layer structure.

[0151] Note that the above descriptions of the conductor 305, the insulator 316, the conductor 342, the conductor 360, the transistor 110, etc. can be replaced with descriptions of the conductor 353, the insulator 326, the conductor 344, the conductor 361, the transistor 120, etc.

[0152] The insulators 322 and 327 preferably have a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulators 322 and 327 preferably have a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulators 322 and 327 preferably have a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulators 324 and 328.

[0153] The insulator 322 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 322 is formed using such a material, the insulator 322 functions as a layer that suppresses oxygen release from the oxide 330 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 110 to the oxide 330. Therefore, the insulator 322 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 110 and the generation of oxygen vacancies in the oxide 330. Furthermore, the conductor 305 can be prevented from reacting with the insulator 324 and oxygen contained in the oxide 330.

[0154] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 322 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0155] The insulator 322 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0156] The insulator 324 in contact with the oxide 330_1 preferably contains excess oxygen (oxygen is released by heating). For example, the insulator 324 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 330_1, oxygen vacancies in the oxide 330_1 can be reduced, and the reliability of the transistor can be improved.

[0157] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 324. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0158] In addition, in the manufacturing process of the transistor, it is preferable to perform heat treatment while the surface of the oxide 330 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 330, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0159] By subjecting the oxide 330 to oxygen addition treatment, oxygen vacancies in the oxide 330 are repaired by the supplied oxygen. In other words, O +O→null reaction can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 330, and the hydrogen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 330 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0160] The insulators 322 and 324 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 324 may be formed in an island shape overlapping the oxide 330a. In this case, the insulator 375 is configured to contact the side surface of the insulator 324 and the top surface of the insulator 322.

[0161] Note that the above descriptions of the insulator 322, the insulator 324, the conductor 305, and the transistor 110 can be replaced with descriptions of the insulator 327, the insulator 328, the conductor 353, and the transistor 120.

[0162] An oxide 343 is provided over the oxide 330b_1. The oxide 343 is preferably provided to overlap with the conductor 342. Similarly, an oxide 345 is provided over the oxide 330b_2. The oxide 345 is preferably provided to overlap with the conductor 344.

[0163] The oxide 343 and the oxide 345 preferably have a function of suppressing oxygen permeation. By disposing the oxide 343, which has a function of suppressing oxygen permeation, between the conductor 342 and the oxide 330b_1, the electrical resistance between the conductor 342 and the oxide 330b_1 is reduced, which is preferable. Similarly, by disposing the oxide 345, which has a function of suppressing oxygen permeation, between the conductor 344 and the oxide 330b_2, the electrical resistance between the conductor 344 and the oxide 330b_2 is reduced, which is preferable.

[0164] Such a structure can improve the electrical characteristics and reliability of the transistor 120 and the transistor 110. Note that if the electrical resistance between the conductor 342 and the oxide 330b_1 can be sufficiently reduced, the oxide 343 may not be provided. If the electrical resistance between the conductor 344 and the oxide 330b_2 can be sufficiently reduced, the oxide 345 may not be provided.

[0165] The oxide 343 and the oxide 345 may be a metal oxide containing the element M. In particular, aluminum, gallium, yttrium, or tin may be used as the element M. The oxide 343 and the oxide 345 preferably have a higher concentration of the element M than the oxide 330b. Gallium oxide may be used as the oxide 343 and the oxide 345. Metal oxides such as In-M-Zn oxide may be used as the oxide 343 and the oxide 345. Specifically, the atomic ratio of the element M to In in the metal oxide used for the oxide 343 and the oxide 345 is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 330b. The thickness of the oxide 343 and the oxide 345 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. The oxide 343 and the oxide 345 preferably have crystallinity. When the oxide 343 and the oxide 345 are crystalline, they can suitably suppress the release of oxygen from the oxide 330. For example, if the oxide 343 and the oxide 345 have a crystalline structure such as a hexagonal crystal structure, they may be able to suppress the release of oxygen from the oxide 330.

[0166] For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used as the conductors 342 and 344. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may also be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0167] Note that hydrogen contained in the oxide 330b and the like may diffuse into the conductor 342 or the conductor 344. In particular, by using a nitride containing tantalum for the conductor 342 and the conductor 344, hydrogen contained in the oxide 330b and the like is likely to diffuse into the conductor 342 or the conductor 344, and the diffused hydrogen may bond with nitrogen contained in the conductor 342 or the conductor 344. In other words, hydrogen contained in the oxide 330b and the like may be absorbed by the conductor 342 or the conductor 344.

[0168] Preferably, no curved surface is formed between the side surface and top surface of the conductor 342 and between the side surface and top surface of the conductor 344. By using a conductor without such a curved surface, the cross-sectional area of the conductor 344 in the channel width direction can be increased. This reduces the resistance of the conductor 344 and increases the on-state current of the transistor 120. Similarly, the cross-sectional area of the conductor 342 in the channel width direction can be increased. This reduces the resistance of the conductor 342 and increases the on-state current of the transistor 110.

[0169] The insulator 375 covers the insulator 324, the oxide 330a_1, the oxide 330b_1, the oxide 343, and the conductor 342, and has openings in regions where the insulator 350, the conductor 360, and the like are provided. The insulator 375 is preferably provided in contact with the top surface of the insulator 324, the side surfaces of the oxide 330a_1, the side surfaces of the oxide 330b_1, the side surfaces of the oxide 343, the side surfaces of the conductor 342, and the top surface of the conductor 342. The insulator 375 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 375 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing from above into the oxide 330a_1, the oxide 330b_1, or the insulator 324, and preferably has a function of capturing impurities such as hydrogen.

[0170] The insulator 329 covers the insulator 328, the oxide 330a_2, the oxide 330b_2, the oxide 345, and the conductor 344, and has openings in regions where the insulator 351, the conductor 361, and the like are provided. The insulator 329 is preferably provided in contact with the top surface of the insulator 328, the side surfaces of the oxide 330a_2, the side surfaces of the oxide 330b_2, the side surfaces of the oxide 345, the side surfaces of the conductor 344, and the top surface of the conductor 344. The insulator 329 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 329 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing from above into the oxide 330a_1, the oxide 330b_1, or the insulator 328, and preferably has a function of capturing impurities such as hydrogen.

[0171] The insulators 375 and 329 may be made of, for example, aluminum oxide or silicon nitride.

[0172] By providing the insulator 375 and the insulator 329 as described above, the conductor 342 and the conductor 344 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 380 can be prevented from diffusing into the conductor 342 and the conductor 344. This can prevent the conductor 342 from being directly oxidized by oxygen contained in the insulator 380, which would increase the resistivity and reduce the field-effect mobility and on-current. Furthermore, it can prevent the conductor 344 from being directly oxidized by oxygen contained in the insulator 384, which would increase the resistivity and reduce the field-effect mobility and on-current. In this way, increasing the field-effect mobility and on-current of the transistor 120 can improve the write speed of the memory cell 10. Increasing the field-effect mobility and on-current of the transistor 110 can improve the read speed of the memory cell 10.

[0173] By providing insulator 375, which is in contact with insulator 380 and has a function of capturing impurities such as hydrogen, in the region sandwiched between insulator 312 and insulator 336, the impurities such as hydrogen contained in insulator 380 can be captured and the amount of hydrogen in the region can be kept constant. Furthermore, by providing insulator 329, which is in contact with insulator 384 and has a function of capturing impurities such as hydrogen, the impurities such as hydrogen contained in insulator 384 can be captured and the amount of hydrogen in the region can be kept constant. In this case, it is preferable to use aluminum oxide or the like for insulator 375 and insulator 329.

[0174] Insulators 350 and 351, which function as gate insulators, are preferably disposed in contact with the upper surface of oxide 330b. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, or the like can be used for insulators 350 and 351. Oxides containing silicon, such as silicon oxide and silicon oxynitride, are particularly preferred because they are thermally stable.

[0175] As with the insulator 324, the concentrations of impurities such as water and hydrogen are preferably reduced in the insulators 350 and 351. The thicknesses of the insulators 350 and 351 are preferably 1 nm or more and 20 nm or less.

[0176] Furthermore, a metal oxide may be provided between the insulator 350 and the conductor 360. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 350 to the conductor 360. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 350 to the conductor 360 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 330 can be suppressed. Furthermore, oxidation of the conductor 360 due to oxygen from the insulator 350 can be suppressed. Similarly, a metal oxide may be provided between the insulator 351 and the conductor 361. For example, hafnium oxide or the like can be used as the metal oxide.

[0177] The metal oxide may function as part of the first gate electrode. For example, the metal oxide that can be used as the oxide 330 may be used as the metal oxide. In this case, the electrical resistance of the metal oxide can be reduced by forming the conductor 360a and / or the conductor 361a by a sputtering method, thereby making the metal oxide a conductor. This can be called an OC (Oxide Conductor) electrode.

[0178] The presence of the metal oxide can improve the on-state current of the transistor 110 without weakening the influence of the electric field from the conductor 360. Furthermore, the physical thickness of the insulator 350 and the metal oxide can maintain a distance between the conductor 360 and the oxide 330, thereby suppressing leakage current between the conductor 360 and the oxide 330. Furthermore, the provision of a stacked structure of the insulator 350 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 360 and the oxide 330 and the electric field strength applied from the conductor 360 to the oxide 330. The same applies to the insulator 351 and the conductor 361.

[0179] The conductor 360 preferably includes a conductor 360a and a conductor 360b disposed on the conductor 360a. The conductor 361 preferably includes a conductor 361a and a conductor 361b disposed on the conductor 361a. For example, the conductor 360a is preferably disposed so as to overlap the bottom and side surfaces of the conductor 360b. The conductor 361a is preferably disposed so as to overlap the bottom and side surfaces of the conductor 361b.

[0180] In this embodiment, conductor 360 is shown as a two-layer structure of conductor 360a and conductor 360b, and conductor 361 is shown as a two-layer structure of conductor 361a and conductor 361b, but conductor 360 and conductor 361 may have a single-layer structure or a laminated structure of three or more layers.

[0181] The conductors 360a and 361a are preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen.

[0182] Furthermore, since conductor 360a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 360b caused by oxygen contained in insulator 350. Since conductor 361a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 361b caused by oxygen contained in insulator 351. The conductive material used for conductor 360a and / or conductor 361a may be the same conductive material as that for conductor 305a and / or conductor 305c.

[0183] Furthermore, since conductors 360 and 361 also function as wiring, it is preferable to use conductors with high conductivity. For example, conductors 360b and 361b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. Furthermore, conductors 360b and 361b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0184] In the transistor 110, the conductor 360 is formed in a self-aligned manner to fill an opening formed in the insulator 380 or the like. In the transistor 120, the conductor 361 is formed in a self-aligned manner to fill an opening formed in the insulator 384 or the like. By forming the conductor 360 in this manner, the conductor 360 can be placed in the region between the conductors 342a and 342b without the need for alignment. The same applies to the conductor 361.

[0185] Furthermore, in the channel width direction of the transistor 110, when the bottom surface of the insulator 322 is taken as a reference plane, the height from the reference plane to the bottom surface of the conductor 360 in a region where the conductor 360 and the oxide 330b do not overlap is preferably lower than the height from the reference plane to the bottom surface of the oxide 330b. When the conductor 360, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 330b_1 via the insulator 350 or the like, the electric field of the conductor 360 can be easily applied to the entire channel formation region of the oxide 330b_1. This increases the on-state current of the transistor 110 and improves its frequency characteristics. When the bottom surface of insulator 322 is taken as the reference plane, the difference between the height from the reference plane to the bottom surface of conductor 360 in the region where oxide 330_1 and conductor 360 do not overlap and the height from the reference plane to the bottom surface of oxide 330b_1 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0186] The insulator 380 is provided on the insulator 375, and has openings formed in regions where the insulator 350 and the conductor 360 are to be provided. The insulator 384 is provided on the insulator 329, and has openings formed in regions where the insulator 351 and the conductor 361 are to be provided. The top surfaces of the insulator 380 and the insulator 384 may be flattened.

[0187] The insulators 380 and 384, which function as interlayer films, preferably have a low dielectric constant. The insulator 380 is preferably formed using, for example, the same material as the insulator 316. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form a region containing oxygen that is released by heating.

[0188] Like the insulator 324, the insulators 380 and 384 preferably have an excess oxygen region or excess oxygen. Furthermore, the concentrations of impurities such as water and hydrogen in the insulators 380 and 384 are preferably reduced. For example, the insulators 380 and 384 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing an insulator having excess oxygen near the oxide 330, oxygen vacancies in the oxide 330 can be reduced, improving the reliability of the transistor.

[0189] The insulator 334 is arranged in contact with the top surfaces of the conductor 361, the insulator 351, and the insulator 384. The insulator 334 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing into the insulator 384 from above and preferably has a function of capturing impurities such as hydrogen. The insulator 334 also preferably functions as a barrier insulating film that prevents oxygen from passing through. For example, an insulator such as aluminum oxide may be used as the insulator 334. By providing the insulator 334 in contact with the insulator 384 in the region sandwiched between the insulator 312 and the insulator 378 and having a function of capturing impurities such as hydrogen, the impurities such as hydrogen contained in the insulator 384 can be captured and the amount of hydrogen in the region can be kept constant.

[0190] Insulator 335 is disposed in contact with the upper surfaces of conductor 360, insulator 350, and insulator 380. Insulator 335 functions similarly to insulator 334.

[0191] The insulator 336 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 384. The insulator 336 is disposed on the insulator 384. The insulator 336 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 336 may be formed using silicon nitride deposited by a sputtering method. By depositing the insulator 336 by a sputtering method, a silicon nitride film that is high in density and less likely to form voids can be formed. Alternatively, the insulator 336 may be formed by stacking a silicon nitride film deposited by a CVD method on a silicon nitride film deposited by a sputtering method.

[0192] [Constituent materials of semiconductor device] Hereinafter, constituent materials that can be used for the memory cell 10, which is a memory device according to one embodiment of the present invention, and a semiconductor device including the memory cell 10, will be described.

[0193] [substrate] The memory cell 10, which is a memory device according to one embodiment of the present invention, and a semiconductor device including the memory cell 10 can be provided on a substrate. Examples of the substrate include an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0194] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0195] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0196] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0197] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0198] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0199] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 330, oxygen vacancies in the oxide 330 can be compensated for.

[0200] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0201] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0202] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0203] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0204] [Metal oxides] It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 330. Metal oxides that can be used as the oxide 330 according to the present invention will be described below.

[0205] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0206] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc will be considered.

[0207] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0208] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 6A. Fig. 6A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0209] As shown in FIG. 6A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0210] The structure within the bold frame in Figure 6A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0211] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 6B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 6B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 6B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 6B is 500 nm.

[0212] As shown in Figure 6B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 6B, the peak near 2θ = 31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0213] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 6C shows the diffraction pattern of a CAAC-IGZO film. Figure 6C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 6C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0214] As shown in Figure 6C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0215] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 6A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0216] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0217] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0218] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0219] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0220] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0221] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0222] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0223] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0224] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0225] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0226] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0227] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0228] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0229] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0230] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0231] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0232] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0233] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0234] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0235] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor used in the semiconductor device according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0236] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0237] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0238] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×1012 cm -3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 1000 . In order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. An oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0239] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0240] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0241] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0242] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0243] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0244] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0245] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0246] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0247] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0248] [Other semiconductor materials] The semiconductor material that can be used for the oxide 330 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 330. For example, it is preferable to use a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material or a two-dimensional material) that functions as a semiconductor as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0249] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0250] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0251] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 330. Specific examples of transition metal chalcogenides that can be used as the oxide 330 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0252] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0253] (Embodiment 2) In this embodiment, a configuration example of a semiconductor device 200 including a memory cell 10 (also referred to as a "memory element") will be described.

[0254] 7A is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in FIG. 7A includes a driver circuit 210 and a memory array 220. The memory array 220 includes a plurality of memory cells 10. FIG. 7A illustrates an example in which the memory array 220 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 2).

[0255] The rows and columns extend in directions perpendicular to each other. In this embodiment, the X direction is referred to as the "rows" and the Y direction is referred to as the "columns," but the X direction may also be referred to as the "columns" and the Y direction may also be referred to as the "rows."

[0256] 7A, the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n], and the memory cell 10 in the ith row and jth column (i is an integer between 1 and m, and j is an integer between 1 and n) is indicated as memory cell 10[i,j].

[0257] The drive circuit 210 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212, and a voltage generation circuit 228.

[0258] In the semiconductor device 200, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0259] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 212.

[0260] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit 212 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0261] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0262] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0263] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has the function of selecting the wiring WL specified by the row decoder 221. The column driver 224 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data.

[0264] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0265] PSW241 is the V to the peripheral circuit 215 DD The PSW 242 has the function of controlling the supply of V to the row driver 223. HM Here, the high power supply voltage of the semiconductor device 200 is V DD and the low power supply voltage is GND (ground potential). HM is the high supply voltage used to drive the word line high, and V DD 7A, in the peripheral circuit 215, V DD Although the number of power domains to which power is supplied is set to one, it is also possible to set multiple power domains. In this case, a power switch should be provided for each power domain.

[0266] The driving circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in FIG. 7B, the driving circuit 210 and the memory array 220 may be provided overlapping each other. By providing the driving circuit 210 and the memory array 220 overlapping each other, the signal propagation distance can be shortened. Furthermore, the semiconductor device 200 can be made smaller.

[0267] 8A is a block diagram illustrating an example of the arrangement of memory cells 10 in a memory array 220. The memory array 220 includes m wires WBL and m wires RBL extending in the row direction, and n wires WL, n wires CL, n wires SL, n wires BGL2, and n wires BGL1 extending in the column direction (not shown).

[0268] 8B is a circuit diagram of a memory cell 10[i,j]. The memory cell 10[i,j] includes a transistor 120[i,j], a transistor 110[i,j], and a capacitor 130[i,j]. The gate of the transistor 120[i,j] is electrically connected to the wiring WL[j], which is the wiring WL in the jth column, and the back gate is electrically connected to the wiring BGL2[j], which is the wiring BGL2 in the jth column. In addition, one of the source and drain of the transistor 120[i,j] is electrically connected to the wiring WBL[i], which is the wiring WBL in the i-th row, and the other is electrically connected to the gate of the transistor 110[i,j].

[0269] The back gate of the transistor 110[i,j] is electrically connected to the wiring BGL1[j], which is the wiring BGL1 in the j-th column. One of the source and the drain of the transistor 110[i,j] is electrically connected to the wiring RBL[i], which is the wiring RBL in the i-th row, and the other is electrically connected to the wiring SL[j], which is the wiring SL in the j-th column.

[0270] Furthermore, the memory cell 10[i,j] includes a capacitor 130[i,j] between the gate of the transistor 110[i,j] and the wiring CL[j], which is the wiring CL in the jth column. In this specification and elsewhere, the node where the other of the source or the drain of the transistor 120[i,j] is electrically connected to the gate of the transistor 110[i,j] is referred to as a node FN[i,j]. Therefore, the memory cell 10[i,j] includes a capacitor 130[i,j] between the node FN[i,j] and the wiring CL[j].

[0271] By supplying signals to the wiring WBL[i] and the wiring WL[j], information can be written to the memory cell 10[i,j]. In addition, by supplying signals to the wiring RBL[i] and the wiring SL[j], information stored in the memory cell 10[i,j] can be read. By controlling the signals supplied to each wiring, information can be read from and written to any memory cell 10. Therefore, the semiconductor device 200 can function as a NOR-type memory device.

[0272] FIG. 9A is a block diagram illustrating an example of an arrangement of memory cells 10 in a memory array 220 that is different from that shown in FIG. 8A.

[0273] In the memory array 220 shown in FIG. 9A, the memory cells 10 in odd-numbered columns and the memory cells 10 in even-numbered columns are arranged symmetrically. FIG. 9B shows a circuit diagram of memory cells 10[i,j] and memory cells 10[i,j+1] when j is an odd number. FIG. 10 also shows an example of the cross-sectional structure of memory cells 10[i,j] and memory cells 10[i,j+1]. FIG. 10 is a cross-sectional view corresponding to FIG. 1B and FIG. 2.

[0274] Either the source or the drain of the transistor 120[i,j] and either the source or the drain of the transistor 120[i,j+1] are both electrically connected to the wiring WBL[i]. By arranging the memory cells 10 in the odd-numbered columns and the memory cells 10 in the even-numbered columns symmetrically, both the transistor 120[i,j] and the transistor 120[i,j+1] can be electrically connected to the wiring WBL[i] via a common connection path 365 (see FIG. 10).

[0275] Similarly, both the transistor 110[i,j] and the transistor 110[i,j+1] can be electrically connected to the wiring RBL[i] via a common connection path 366. This further reduces the area occupied by the memory array 220. In addition, the recording density per unit area can be further increased.

[0276] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0277] (Embodiment 3) In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0278] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 11 shows various memory devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the memory capacity and recording density required. Figure 11 shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0279] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0280] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0281] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0282] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0283] A storage device according to one embodiment of the present invention has a high operating speed and is capable of long-term data retention. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0284] A storage device according to one embodiment of the present invention can be applied to, for example, storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0285] Furthermore, a storage device according to an embodiment of the present invention is applicable to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 12A to 12E show schematic diagrams of several configuration examples of removable storage devices. For example, a storage device according to an embodiment of the present invention is processed into a packaged memory chip and used in various storage devices and removable memories.

[0286] 12A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 on the board 1104.

[0287] FIG. 12B is a schematic diagram of the appearance of an SD card, and FIG. 12C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

[0288] FIG. 12D is a schematic diagram of the appearance of an SSD, and FIG. 12E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing a memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into memory chip 1154 of board 1153, etc.

[0289] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0290] (Fourth embodiment) Specific examples of electronic devices including a semiconductor device according to one embodiment of the present invention are illustrated in FIGS.

[0291] <Electronic devices and systems> A semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of such electronic devices include electronic devices with relatively large screens, such as televisions, monitors for desktop or notebook information terminals, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, and sound players. Furthermore, a semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence. Artificial intelligence can be implemented in electronic devices using a semiconductor device according to one embodiment of the present invention.

[0292] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0293] An electronic device according to one embodiment of the present invention may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0294] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0295] [Information terminal] 13A shows a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. As input interfaces, a touch panel is provided on the display unit 5102 and buttons are provided on the housing 5101.

[0296] The information terminal 5100 can execute applications using artificial intelligence using the semiconductor device of one embodiment of the present invention. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display portion 5102, an application that recognizes characters, figures, or the like input by a user to a touch panel included in the display portion 5102 and displays the characters, figures, or the like on the display portion 5102, and an application that performs biometric authentication such as fingerprint or voiceprint authentication.

[0297] 13B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0298] Like the information terminal 5100 described above, the notebook information terminal 5200 can execute applications using artificial intelligence using a semiconductor device according to one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, new artificial intelligence can be developed by using the notebook information terminal 5200.

[0299] 13A and 13B, a smartphone and a notebook type information terminal are used as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be used. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0300] [Game consoles] FIG. 13C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously. A semiconductor device according to one embodiment of the present invention can be incorporated into chips or the like provided on substrates of the housings 5301, 5302, and 5303.

[0301] 13D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0302] A game machine with reduced power consumption can be realized by applying a GPU or a chip that is a semiconductor device according to one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, reduced power consumption reduces heat generated from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0303] Furthermore, the portable game console 5300 can have artificial intelligence by using a semiconductor device according to one embodiment of the present invention.

[0304] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game console 5300, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0305] Furthermore, when playing a game requiring multiple players on the portable game console 5300, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0306] 13C and 13D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the semiconductor device according to an embodiment of the present invention can be applied are not limited to these. Examples of game machines to which the semiconductor device according to an embodiment of the present invention can be applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0307] [Mainframe Computer] A semiconductor device according to one embodiment of the present invention can be applied to a mainframe computer.

[0308] 13E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 13F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0309] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a semiconductor device according to one embodiment of the present invention can be mounted on the board.

[0310] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. Scientific and technological calculations require high-speed processing of enormous amounts of calculations, resulting in high power consumption and large amounts of heat generated by chips. By applying a semiconductor device according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with reduced power consumption can be realized. Furthermore, reducing the power consumption of the supercomputer can reduce heat generated by circuits constituting the supercomputer, thereby reducing the influence of heat on the circuits themselves, peripheral circuits, and modules.

[0311] 13E and 13F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the semiconductor device according to an embodiment of the present invention is applied is not limited to this. Examples of the mainframe computer to which the semiconductor device according to an embodiment of the present invention is applied include a computer (server) that provides services, a mainframe computer (mainframe), etc.

[0312] [Moving object] A semiconductor device according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0313] Fig. 13G is a diagram showing the area around the windshield in the interior of an automobile 5600, which is an example of a moving body. Fig. 13G shows display panel 5601, display panel 5602, and display panel 5603 attached to the dashboard, as well as display panel 5604 attached to a pillar.

[0314] The display panels 5601 to 5603 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, air conditioning settings, etc. The display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, thereby improving the design. The display panels 5601 to 5603 can also be used as lighting devices.

[0315] The display panel 5604 can complement the view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5604 can also be used as a lighting device.

[0316] Since the semiconductor device according to one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for automobiles. The chip can also be used in a system that provides road guidance, hazard prediction, etc. The display panels 5601 to 5604 may be configured to display information such as road guidance and hazard prediction.

[0317] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets). A semiconductor device according to one embodiment of the present invention can be applied to these moving objects to provide them with a system using artificial intelligence.

[0318] [electric appliances] 13H shows an example of an electric appliance, an electric refrigerator-freezer 5700. The electric refrigerator-freezer 5700 includes a housing 5701, a refrigerator door 5702, a freezer door 5703, and the like.

[0319] The electric refrigerator-freezer 5700 can have artificial intelligence by using the semiconductor device according to one embodiment of the present invention in the electric refrigerator-freezer 5700. By using artificial intelligence, the electric refrigerator-freezer 5700 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5700 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5700, and the like.

[0320] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0321] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with descriptions of other electronic devices.

[0322] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0323] 10: memory cell, 110: transistor, 120: transistor, 130: capacitor, 200: semiconductor device, 210: drive circuit, 211: peripheral circuit, 212: control circuit, 215: peripheral circuit, 220: memory array, 221: row decoder, 222: column decoder, 223: row driver, 224: column driver, 225: input circuit, 226: output circuit, 227: sense amplifier, 228: voltage generation circuit, 241: PSW, 242: PSW

Claims

1. a first transistor, a second transistor, and a capacitance element; a memory cell in which a first gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected, a first oxide semiconductor having a channel formation region of the first transistor; a first conductor located above the first oxide semiconductor and functioning as a first gate of the first transistor; a second oxide semiconductor located above the first conductor and having a channel formation region of the second transistor; a second conductor located above the second oxide semiconductor and functioning as a first gate of the second transistor; a third conductor located above the second oxide semiconductor and functioning as the other electrode of the capacitor; a first insulator having a region in contact with an upper surface of the first conductor; a fourth conductor having a region in contact with an upper surface of the first insulator and functioning as a second gate of the second transistor; a fifth conductor having a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the first insulator, the fifth conductor being made of the same material as the fourth conductor; a second insulator having a region in contact with an upper surface of the fourth conductor and a region in contact with an upper surface of the fifth conductor, and having a region located below the second oxide semiconductor; a sixth conductor having a region located below the first oxide semiconductor and electrically connected to one of the source and the drain of the first transistor; a seventh conductor having a region located above the first oxide semiconductor and electrically connected to the other of the source and the drain of the first transistor; the first conductor has a region overlapping with the second oxide semiconductor; the second conductor has a region overlapping with the first oxide semiconductor; the sixth conductor has a function as wiring, the seventh conductor has a function as wiring, the sixth conductor has a region extending in a channel length direction of the first transistor in a plan view, the seventh conductor has a region extending in a direction intersecting a channel length direction of the first transistor in a plan view; the sixth conductor has a region overlapping with a channel formation region of the first transistor, a region overlapping with a channel formation region of the second transistor, and a region overlapping with the capacitive element; the seventh conductor has the same material as the fourth conductor and the fifth conductor, and has a region in contact with the top surface of the first insulator; the second insulator has a region in contact with an upper surface of the seventh conductor, a source or a drain of the second transistor electrically connected to a first gate of the first transistor via the fifth conductor;

2. a first transistor, a second transistor, and a capacitance element; a memory cell in which a first gate of the first transistor, one of a source and a drain of the second transistor, and one electrode of the capacitance element are electrically connected, a first oxide semiconductor having a channel formation region of the first transistor; a first conductor located above the first oxide semiconductor and functioning as a first gate of the first transistor; a second oxide semiconductor located above the first conductor and having a channel formation region of the second transistor; a second conductor located above the second oxide semiconductor and functioning as a first gate of the second transistor; a third conductor located above the second oxide semiconductor and functioning as the other electrode of the capacitor; a first insulator having a region in contact with an upper surface of the first conductor; a fourth conductor having a region in contact with an upper surface of the first insulator and functioning as a second gate of the second transistor; a fifth conductor having a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the first insulator, the fifth conductor being made of the same material as the fourth conductor; a second insulator having a region in contact with an upper surface of the fourth conductor and a region in contact with an upper surface of the fifth conductor, and having a region located below the second oxide semiconductor; a sixth conductor located below the first oxide semiconductor and functioning as a second gate of the first transistor; a seventh conductor having a region located below the first oxide semiconductor and electrically connected to one of the source and the drain of the first transistor; an eighth conductor having a region located above the first oxide semiconductor and electrically connected to the other of the source and the drain of the first transistor; the first conductor has a region overlapping with the second oxide semiconductor; the second conductor has a region overlapping with the first oxide semiconductor; the seventh conductor has a function as wiring, the eighth conductor has a function as wiring, the seventh conductor has a region extending in a channel length direction of the first transistor in a plan view; the eighth conductor has a region extending in a direction intersecting a channel length direction of the first transistor in a plan view; the seventh conductor has a region overlapping with a channel formation region of the first transistor, a region overlapping with a channel formation region of the second transistor, and a region overlapping with the capacitive element; the eighth conductor has the same material as the fourth conductor and the fifth conductor, and has a region in contact with the top surface of the first insulator; the second insulator has a region in contact with the top surface of the eighth conductor, one of the source and the drain of the second transistor is electrically connected to the first gate of the first transistor via the fifth conductor; The fourth conductor and the sixth conductor are electrically connected to each other.

3. In claim 1, the first transistor has a second gate below the first oxide semiconductor; the second transistor has a second gate below the second oxide semiconductor; a second gate of the first transistor and a second gate of the second transistor are electrically connected to each other.

4. In any one of claims 1 to 3, A memory cell in which the channel length of the first transistor is longer than the channel length of the second transistor.

5. a plurality of the memory cells according to any one of claims 1 to 4; The memory device has a plurality of memory cells arranged in a matrix of m rows and n columns (m and n are integers of 2 or more).

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