Gate drive circuit and power conversion device using the same

Abstract

The present invention comprises: a gate drive unit (3) that applies a gate drive voltage to a control terminal of a semiconductor switching element (1) and drives the semiconductor switching element (1); a voltage feedback unit (2) that is connected to a high-potential main terminal of the semiconductor switching element (1) and feeds back, to the gate drive unit (3), a voltage of the high-potential main terminal generated at a turn-off time of the semiconductor switching element (1); and an electric discharge unit (4) that constitutes a path for allowing charges included in the voltage feedback unit (2) to be discharged when turning on the semiconductor switching element (1), toward the high-potential main terminal of the semiconductor switching element (1).

Description

[Technical Field]

[0001] The present disclosure relates to a gate drive circuit and a power conversion device using the same. [Background technology]

[0002] It is generally known that in order to reduce the switching loss of semiconductors such as MOSFETs, the gate resistance can be reduced to increase the switching speed. However, increasing the switching speed at turn-off increases the surge voltage generated by parasitic inductance in the circuit, and if the voltage resistance of the semiconductor is exceeded, it can lead to semiconductor destruction. In other words, there is a trade-off between the switching loss and surge voltage at turn-off.

[0003] To improve this relationship, it has been proposed to connect the drain terminal of MOSFET 30 to the anode terminal of diode 40 via capacitor 42, and to connect the gate terminal of MOSFET 30 to the cathode terminal of diode 40 (for example, Patent Document 1). In this configuration, when the surge voltage at turn-off exceeds a specified voltage, the gate is turned on to release the surge voltage, thereby achieving low loss and low surge voltage.

[0004] Furthermore, there is a configuration for achieving high response in which information on the collector voltage of the IGBT is fed back to the input side of the gate driver (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-288774 [Non-patent literature]

[0006] [Non-Patent Document 1] New drivers with active clamping for high-power IGBTs(2000 International Conference on Power, Energy and Electrical Engineering) Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the invention disclosed in Patent Document 1, when MOSFET 30 is turned off, a charge corresponding to VDD38 is stored in capacitor 42, and when MOSFET 30 is turned on, a current flows from capacitor 42 to the drain terminal of MOSFET 30, causing a drop in gate voltage at gate resistor 36. To solve this problem, diode 40 is implemented to block the current flowing from capacitor 42 to the drain terminal of MOSFET 30. Therefore, this diode 40 needs to be a high-voltage component that can withstand the voltage of VDD38, which poses problems in terms of cost and reliability.

[0008] Furthermore, the configuration disclosed in Non-Patent Document 1 also required the use of high-voltage components to prevent a drop in gate voltage. In particular, when the IGBT is turned on, a minute displacement current flows via the parasitic capacitance of the diode, causing a voltage drop across resistor Rin on the buffer input side, lowering the gate voltage and increasing turn-on loss.

[0009] In order to solve the above problem, the present disclosure aims to provide a power conversion device that can prevent a voltage drop in a gate driver when turned on without using high-voltage semiconductor components in the voltage feedback section. [Means for solving the problem]

[0010] Gate drive circuit according to the present disclosure The roada gate drive unit that applies a gate drive voltage to a control terminal of a semiconductor switching element to drive the semiconductor switching element; a voltage feedback unit that is connected to a high potential main terminal of the semiconductor switching element and feeds back to the gate drive unit the voltage of the high potential main terminal that is generated when the semiconductor switching element is turned off; and a discharge unit that forms a path for discharging the charge contained in the voltage feedback unit to the high potential main terminal side of the semiconductor switching element when the semiconductor switching element is turned on. Moreover, a power conversion device according to the present disclosure includes a gate drive circuit and a semiconductor switching element, and converts externally input power into desired power by the on / off operation of the semiconductor switching element. [Effects of the Invention]

[0011] According to the gate drive circuit of the present disclosure, it is possible to prevent a voltage drop in the gate drive section when the gate is turned on, without using high-voltage semiconductor components in the voltage feedback section. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a circuit diagram of a gate drive circuit according to a first embodiment of the present disclosure. [Figure 2] 1 is a diagram illustrating an example of a partial configuration of a power conversion device according to a first embodiment of the present disclosure. [Figure 3] FIG. 1 is a block diagram of a gate drive circuit according to a first embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram illustrating a configuration example of a buffer circuit according to a first embodiment of the present disclosure. [Figure 5] FIG. 4 is a diagram showing the results of a simulation study comparing the gate drive circuit according to the first embodiment of the present disclosure with a conventional example. [Figure 6] 10A and 10B are diagrams illustrating a mechanism by which a malfunction occurs in a conventional example. [Figure 7] FIG. 10 is a diagram illustrating a gate drive circuit according to a second embodiment of the present disclosure. [Figure 8] FIG. 10 is a block diagram of a gate drive circuit according to a second embodiment of the present disclosure. [Figure 9] FIG. 10 is a diagram illustrating a gate drive circuit according to a third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described with reference to the drawings. Note that the drawings are schematic, and for the sake of convenience, configurations are omitted or simplified. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Furthermore, in the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted to avoid duplication.

[0014] Embodiment 1 FIG. 1 is a circuit diagram of a gate drive circuit according to a first embodiment. FIG. 2 is a diagram showing an example of the configuration of a gate drive circuit of a part of a power conversion device. The power conversion device according to the first embodiment is configured to include a semiconductor switching element 1 (hereinafter also referred to as semiconductor SW element 1), and is, for example, a DC-DC converter, an AC-DC converter, a DC-AC inverter, or an AC-AC inverter that converts an externally input voltage, current, or power into a desired voltage, current, or power. The semiconductor SW element 1 included in the power conversion device is driven by a gate drive circuit 300 shown in FIG. 1.

[0015] 1, the gate drive circuit 300 includes a voltage feedback unit 2, a gate drive unit 3, a discharge unit 4, a first current limiting element 5, and an insulating communication unit 6. The gate drive circuit 300 drives a semiconductor switching element 1 connected to the gate drive circuit 300 based on a command from a higher-level logic unit 7.

[0016] The power conversion device is configured to include one or more gate drive circuits 300. Fig. 2 shows an example in which two gate drive circuits 300 and two semiconductor SW elements 1 are included, with one semiconductor SW element shown as semiconductor SW element 1(a) and the other semiconductor SW element shown as semiconductor SW element 1(b). Also, a configuration including one gate drive circuit is shown as 300(a) and the other gate drive circuit as 300(b).

[0017] As shown in FIG. 2, the gate drive circuit 300(a) is connected to the gate terminal and collector (or drain) terminal of the semiconductor SW element 1(a), the gate drive circuit 300(b) is connected to the gate terminal and collector (or drain) terminal of the semiconductor SW element 1(b), and the emitter (or source) terminal of the semiconductor SW element 1(a) is connected to the collector (or drain) terminal of the semiconductor SW element 1(b). (b) The collector (or drain) terminals of the semiconductor SW element 1(a) and the semiconductor SW element 1(b) are connected to the positive side 200 of the power supply, and the emitter (or source) terminal of the semiconductor SW element 1(b) is connected to the negative side 201 of the power supply. The connection point between the semiconductor SW element 1(a) and the semiconductor SW element 1(b) becomes the output terminal 202. The gate drive circuit 300(a) and the gate drive circuit 300(b) alternately turn on and off the semiconductor SW elements 1(a) and 1(b) to perform power conversion operation, thereby making it possible to extract the desired power from the output terminal 202.

[0018] The configuration of the gate drive circuit 300 will now be described further with reference to FIG. 3. FIG. 3 is a block diagram of the gate drive circuit according to the first embodiment. As shown in FIG. 3, the semiconductor switching element 1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with an anti-parallel diode between the source and drain. It is possible to use either a SiC MOSFET or a Si MOSFET. Active clamp technology, which is effective in reducing both switching loss and surge voltage during turn-off, is more effective in SiC, which is capable of faster switching than Si. Alternatively, an IGBT (Insulated Gate Bipolar Transistor) module with an anti-parallel diode or a GaN-HEMT (Gallium Nitride High Mobility Transistor) may be used. The anti-parallel diode may be a diode built into the MOSFET, or a separate external diode may be provided. In the following, the semiconductor switching element 1 will be described as an example of a MOSFET having an anti-parallel diode between the source and drain.

[0019] The voltage feedback section 2 is connected to the drain side of the semiconductor switching element 1. The voltage feedback section 2 can detect the voltage of the high potential main terminal which is the drain side of the semiconductor switching element 1. The voltage feedback section 2 detects the voltage of the high potential main terminal which is the drain side of the semiconductor switching element 1. High potential main terminal side The voltage rise is fed back to the input side of the gate driver 3. This makes it possible to realize a function (active clamp) that raises the gate voltage and suppresses surge voltage.

[0020] Specifically, the voltage feedback unit 2 includes a high-voltage capacitor 9, a first reverse-blocking diode 8, and a second current-limiting element 10. The capacitor 9 transfers energy from the drain terminal of the semiconductor switching element 1. In other words, the drain terminal of the semiconductor switching element 1 is capacitively coupled by the capacitor 9. The anode of the first reverse-blocking diode 8 is connected to the drain side of the semiconductor switching element 1, and the cathode of the first reverse-blocking diode 8 is connected to the gate driver 3 side. This makes it possible to prevent reverse current when the semiconductor switching element 1 is turned on.

[0021] The second current limiting element 10 is a resistor for limiting current. Specifically, the second current limiting element 10 adjusts the amount of feedback current to the gate signal required for active clamp operation. The resistance value of the second current limiting element 10 is adjusted based on the capacitance of the capacitor 9, the impedance of the first current limiting element 5, the configuration of the gate driver 3, and the capacitance characteristics of the semiconductor switching element 1. Therefore, although the second current limiting element 10 is provided in the first embodiment, it may be unnecessary depending on the circuit design. Alternatively, a constant voltage diode may be used instead of the capacitor 9. In this case, the anode of the constant voltage diode is connected to the gate driver 3, and the cathode is connected to the drain side of the semiconductor switching element 1. This has the effect of masking active clamp operation until the surge voltage reaches a certain voltage. In other words, by disabling active clamp operation until the surge voltage reaches a certain voltage, high-speed switching can be achieved, resulting in reduced losses.

[0022] The same effect can be achieved even if the order of the capacitor 9, first reverse-blocking diode 8, second current limiting element 10, and voltage regulator diode is reversed. Furthermore, some components of the second current limiting element 10 can be omitted. Furthermore, although the voltage feedback unit 2 is connected to the input side of the gate driver 3 in FIG. 3 , the voltage feedback unit 2 may also be connected to the output side of the gate driver 3. When the voltage feedback unit 2 is connected to the input side of the gate driver 3, active clamp operation can be achieved with voltage feedback corresponding to small currents compared to when the voltage feedback unit 2 is connected to the output side of the gate driver 3, allowing the circuit size of the voltage feedback unit 2 to be smaller. Furthermore, when the voltage feedback unit 2 is connected to the output side of the gate driver 3, the output of the gate driver 3 is larger than when the voltage feedback unit 2 is connected to the input side of the gate driver 3, so it does not respond to small noise currents and has better malfunction resistance.

[0023] The gate driver 3 shown in the figure receives the sum of the outputs of the first current limiting element 5 and the second current limiting element 10. The buffer circuit then supplies a current sufficient to charge and discharge the input capacitance of the semiconductor switching element 1. Taking into account the allowable size and required responsiveness, the buffer circuit can be realized, for example, as a circuit composed of bipolar transistors, as shown in Figure 4. Specifically, Figure 4(a) shows a single-stage push-pull (totem-pole) circuit combining an NPN transistor and a PNP transistor. Figure 4(b) shows a multi-stage push-pull (totem-pole) circuit consisting of two or more single-stage push-pull (totem-pole) circuits connected in series. Figure 4(c) shows a composite buffer circuit composed of an N-channel MOSFET, a P-channel MOSFET, a pre-driver that drives them, and an NPN transistor connected in parallel with the source and output of the MOSFET push-pull. A pre-driver is a drive circuit for driving a buffer circuit. The pre-driver shown in Figure 4(c) is an example of a circuit that can generate a HiZ state, which simultaneously turns off both MOSFETs in the buffer circuit.

[0024] Here, we will explain the principles of buffer operation and active clamp operation in the configurations shown in Figures 4(a) to (c). In the single-stage push-pull circuit shown in Figure 4(a), when the gate driver input signal S1 is greater than the base-emitter voltage of the NPN transistor (e.g., 0.7 V), the NPN transistor conducts and outputs a positive voltage. Also, in the single-stage push-pull circuit shown in Figure 4(a), when the gate driver input signal S1 is at low level, the base-emitter voltage falls below a threshold (e.g., -0.7 V), causing the PNP transistor to conduct and output a negative voltage. When the gate driver input signal S1 is at high level, the base-emitter voltage rises above the threshold (e.g., +0.7 V), causing the NPN transistor to conduct and output a positive voltage.

[0025] The multi-stage push-pull circuit shown in Figure 4(b) can achieve stronger buffer capabilities than the single-stage configuration shown in Figure 4(a) by connecting multiple stages in series. In this way, in the buffer circuit shown in Figures 4(a) and 4(b), when the semiconductor switching element 1 is turned off, the collector voltage of the semiconductor switching element 1 rises, causing current to flow through the first reverse-blocking diode 8 of the voltage feedback unit 2, which raises the gate driver input signal S1. This also raises the gate voltage of the semiconductor switching element 1, achieving active clamp operation.

[0026] The composite buffer circuit shown in Figure 4(c) is a circuit that includes a buffer circuit composed of MOSFETs and a bipolar transistor in parallel with the source-side MOSFET of the buffer circuit. When the composite buffer circuit is turned off, a low signal is input from the gate driver input signal S0 to S1 and S2 on the isolated communication unit 6 side, and both the P-channel and N-channel MOSFET outputs are fixed at low. When the semiconductor switch element 1 turns off in this state, the collector voltage of the semiconductor switch element 1 rises. Then, current flows through the first reverse-blocking diode 8 of the voltage feedback unit 2, turning on the NPN transistor. A high-impedance signal is input to S2 of the pre-driver, turning off both the P-channel and N-channel MOSFETs. This allows the NPN transistor to supply a gate current corresponding to the current in the voltage feedback unit 2, raising the gate voltage of the semiconductor switch element 1 and achieving active clamp operation. By using a voltage-driven MOSFET in the buffer circuit, this composite buffer circuit achieves high-speed operation independent of the input current of the upstream stage of the buffer circuit. Note that an active clamp can be realized in the same way as in Figure 4(a) by replacing the NPN transistor in Figure 4(a) with an N-channel MOSFET and the PNP transistor with a P-channel MOSFET as a buffer circuit composed of MOSFETs. In this case, the threshold voltage of the MOSFET (for example, ±2.5V) is higher than the threshold voltage of the bipolar transistor (±0.7V), so a higher drive power supply voltage is required and the drive speed of the buffer is reduced, which are disadvantages.

[0027] The first current limiting element 5 is an element that limits the circuit current in the insulated communication unit 6, while making the input signal of the gate driver 3 have a value different from the output signal of the insulated communication unit 6 by using a feedback signal from the voltage feedback unit 2. The resistance value is adjusted by the capacitance of the capacitor 9, the impedance of the second current limiting element 10, the configuration of the gate driver 3, and the capacitance characteristics of the semiconductor switching element 1.

[0028] The insulated communication unit 6 is composed of an isolator IC that incorporates a photocoupler, pulse transformer, etc., which generates an on / off command signal based on a signal sent from a higher-level logic unit 7 such as a microcomputer while maintaining isolation from the higher-level logic unit 7.

[0029] The discharge unit 4 is disposed between the connection point between the capacitor 9 and the first reverse-blocking diode 8 of the voltage feedback unit 2 and the power supply potential applied to the control terminal when, for example, the semiconductor switching device 1 is turned off. The discharge unit 4 includes a second reverse-blocking diode 11 and an inrush current suppression element 12. The second reverse-blocking diode 11 has an anode connected to the negative potential side of the gate power supply and a cathode connected to the capacitor 9, with the inrush current suppression element 12 connected either before or after it. By providing the discharge unit 4 in this manner, when the semiconductor switching device 1 is turned on, the charge in the capacitor 9, which is charged from the collector terminal of the semiconductor switching device 1 in the direction of the gate signal, is discharged along the path indicated by the dashed-dotted line in FIG. 3 , i.e., the path from the power supply potential applied to the control terminal when the semiconductor switching device 1 is turned off to the drain terminal of the semiconductor switching device 1 via the discharge unit 4, with a discharge time constant CR corresponding to the resistance value R of the inrush current suppression element 12 and the capacitance C of the capacitor 9. Setting this discharge time constant CR to a small value prevents a large reverse voltage from being applied to the first reverse-blocking diode 8 when the semiconductor switching element 1 is turned on. Therefore, a voltage drop in the gate driver 3 when the semiconductor switching element 1 is turned on can be prevented without using high-voltage semiconductor components in the voltage feedback section 2. Furthermore, using low-voltage semiconductor components and high-voltage capacitors makes it possible to create a highly reliable system at lower cost than with high-voltage semiconductor components. Furthermore, it is possible to suppress losses associated with larger size without increasing the system size.

[0030] In the first embodiment, the inrush current suppression element 12 of the discharge unit 4 is configured with a resistor depending on the specifications of the capacitor 9 and the bus voltage, etc., to suppress the inrush current at turn-on. However, this is a design element and is not necessarily required. Furthermore, since the effect of the first embodiment can be obtained by ensuring a path for discharging the charge stored in the capacitor 9 of the voltage feedback unit 2, the anode of the second reverse-blocking diode 11 of the discharge unit 4 can be connected to a point that provides a full-loop discharge path, rather than to the negative potential of the gate power supply. Furthermore, one end of the discharge unit 4 does not have to be the connection point between the capacitor 9 of the voltage feedback unit 2 and the first reverse-blocking diode 8, as described above. It is sufficient that the one end be connected to the voltage feedback unit 2, from the contact of the capacitor 9 on the gate driver 3 side to the gate driver 3.

[0031] Here, the application effect will be explained using the results of analysis and study using SPICE (Simulation Program with Integrated Circuit Emphasis). Figure 5 shows the results of a simulation study conducted based on the circuit block diagram of Figure 3, with and without the discharge unit 4. Figure 5(a) shows the analyzed waveform when there is no discharge unit 4, and Figure 5(b) shows the analyzed waveform when there is the discharge unit 4 of embodiment 1. The bus voltage at turn-on is approximately 600 V, and the current is approximately 1000 A.

[0032] The upper part of Figure 5(a) shows the voltage applied to the first reverse-blocking diode 8 of the voltage feedback unit 2. The upper part of Figure 5(b) shows the waveform of the voltage applied to the first reverse-blocking diode 8 of the voltage feedback unit 2 and the waveform of the discharge current flowing through the inrush current suppression element 12 added to the discharge unit 4. The lower parts of each of Figures 5(a) and 5(b) show the waveforms of the gate-emitter voltage Vge, collector-emitter voltage Vce, and collector current Ic of the semiconductor switching element 1 driven by the gate driver 3.

[0033] In the case of the conventional technology shown in FIG. 5(a) without the discharge unit 4, the voltage applied to the first reverse-blocking diode 8 after turn-on is constant at approximately -600 V, which is opposite in polarity to the voltage across the capacitor 9. On the other hand, in the case of the discharge unit 4 shown in FIG. 5(b), although the voltage momentarily drops to -12 V during discharge, it remains stable at a voltage that is lower by Vf than the voltage applied during turn-on. This is because, as described above, the gate drive circuit 300 according to the first embodiment includes the discharge unit 4, which allows the charge stored in the capacitor 9 of the voltage feedback unit 2 to flow when the semiconductor switching device 1 is off, thereby discharging the charge. The discharge unit 4 can discharge the charge stored in the capacitor 9 of the voltage feedback unit 2 when the semiconductor switching device 1 is off to the drain terminal via a discharge path when the semiconductor switching device 1 is turned on. As a result, a voltage drop across the gate drive unit 3 during turn-on can be prevented without using high-voltage semiconductor components in the voltage feedback unit 2.

[0034] In a configuration in which information on the collector voltage of an IGBT is fed back to the input side of a gate driver to achieve high response, as disclosed in the aforementioned Non-Patent Document 1, a minute current flows through the parasitic capacitance of a diode when the IGBT is turned on. Displacement This current flow causes a voltage drop across resistor Rin on the buffer input side, lowering the gate voltage and increasing turn-on losses. Alternatively, the gate voltage may oscillate during turn-on, resulting in malfunction. The mechanism by which this malfunction occurs is explained below using Figure 6. When the gate turns on (Figure 6 (a)), Vce drops (b), causing a capacitive displacement current to flow in the reverse direction through the reverse-blocking diode via Rin (c). This causes the voltage at the gate driver input via Rin to drop (d), turning the gate off (e). This causes Vce to rise again (f), and current flows forward through the reverse-blocking diode via Rin (g). This switches the voltage drop across Rin to a voltage rise, and the gate driver input rises to the positive voltage of the gate power supply in accordance with the upper logic unit 7 (h). This turns the gate on (i), repeating the operations described in (a) through (f), resulting in the gate repeatedly switching on and off.

[0035] In contrast, in the first embodiment of the present disclosure, a discharge path is secured for discharging the charge stored in the capacitor 9 of the voltage feedback section 2 when the semiconductor switching element 1 is off. This eliminates the need to use high-voltage components in the voltage feedback section 2. The discharge path also constitutes a path from the contact point of the capacitance on the gate driver side to the gate driver. In other words, the discharge section 4 has a path that does not pass through the first current limiting element 5. This prevents a malfunction that occurs when a current discharging the charge stored in the parasitic capacitance of the first reverse-blocking diode 8 of the voltage feedback section 2 at turn-on flows into the gate driver 3, causing a voltage drop in the first current limiting element 5.

[0036] As described above, the gate drive circuit 300 shown in the first embodiment has a gate drive unit 3 that applies a gate drive voltage to the control terminal of the semiconductor switch element 1 to drive the semiconductor switch element 1, and a voltage feedback unit 2 that is connected to the high potential main terminal of the semiconductor switch element 1 and feeds back to the gate drive unit 3 a rise in voltage of the high potential main terminal that occurs when the semiconductor switch element 1 is turned off. This makes it possible to increase the gate voltage and realize the function of suppressing surge voltage. The semiconductor switching element 1 also has a discharge section 4 that forms a path for discharging the capacitance included in the voltage feedback section 2 when it is turned on. This allows the charge stored in the capacitor 9 of the voltage feedback section 2 to flow and be discharged. This makes it possible to prevent a voltage drop in the gate driver 3 when it is turned on without using high-voltage semiconductor components in the voltage feedback section 2. It also makes it possible to prevent a current that discharges the charge stored in the parasitic capacitance of the first reverse-blocking diode 8 when it is turned on from flowing into the gate driver 3. This makes it possible to prevent malfunctions.

[0037] The power conversion device shown in the first embodiment is configured to include one or more gate drive circuits 300 and one or more semiconductor switching elements 1. This makes it possible to prevent a voltage drop in the gate drive unit 3 at turn-on without using high-voltage semiconductor components, and to convert the voltage, current, and power input from the outside into desired voltage, current, and power.

[0038] Embodiment 2 The configuration of a power conversion device according to the second embodiment will be described below with reference to Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are diagrams showing a gate drive circuit 400 according to the second embodiment. As shown in Fig. 7, the power conversion device is configured to include the gate drive circuit 400, and the gate drive circuit 400 includes a voltage feedback unit 2, a gate drive unit 3, a discharge unit 4, a first current limiting element 5, and an insulating communication unit 6. Since this configuration is the same as that of the first embodiment, detailed description of the similar components will be omitted, and the following will describe the parts that are different from the first embodiment.

[0039] In the second embodiment, the configurations of the voltage feedback section 2 and the discharge section 4 of the first embodiment are modified. Specifically, as shown in Fig. 8, the voltage feedback section 2 is configured not to use the first reverse blocking diode 8 for preventing reverse current. In addition, the connection destination of the discharge section 4 is different from that of the first embodiment.

[0040] The discharge unit 4 in the second embodiment is made up of a second reverse blocking diode 11 and an inrush current suppressing element 12. The discharge unit 4 is arranged in parallel with the first current limiting element 5. The second reverse blocking diode 11 has an anode connected to the output side of the insulated communication unit 6 and a cathode connected to the input sides of the voltage feedback unit 2 and the gate driver 3. The inrush current suppression element 12 may be connected either before or after the second reverse blocking diode 11, and FIG. 8 shows the inrush current suppression element 12 connected to the output side of the insulated communication unit 6. The impedance of the inrush current suppression element 12 is set to be smaller than the impedance of the first current limiting element 5.

[0041] By providing the discharge unit 4 in this manner, the charge in the capacitor 9, which is charged in the direction of the gate signal from the collector terminal when the semiconductor switching element 1 is off, can flow from the insulated communication unit 6 through the discharge unit 4 to the collector terminal of the semiconductor switching element 1 when the semiconductor switching element 1 is turned on, and be discharged, as shown by the dashed-dotted line in Figure 8. The provision of the discharge unit 4 ensures the aforementioned path, preventing a voltage drop in the gate driver 3 when the semiconductor switching element 1 is turned on, without requiring the provision of high-voltage semiconductor components in the voltage feedback unit 2. Furthermore, because the discharge unit 4 is configured in parallel with the first current limiting element 5, the first current limiting element 5 does not pass through the main discharge path. This suppresses the voltage drop caused by the first current limiting element 5, making it possible to prevent malfunctions.

[0042] In addition, the inrush current suppression element 12 of the discharge unit 4 is composed of a resistor depending on the specifications of the capacitor 9 and bus voltage, etc., in order to suppress the inrush current at turn-on, but since it is a design element, it is not necessarily required and can be omitted.

[0043] It is also possible to provide both the discharge unit 4 described in the first embodiment and the discharge unit 4 described in the second embodiment, thereby combining a plurality of discharge units 4. In this case, too, it is possible to prevent a voltage drop in the gate driver 3 at turn-on without using high-voltage semiconductor components in the voltage feedback unit 2.

[0044] Embodiment 3 The configuration of a power conversion device according to the third embodiment will be described below with reference to FIG. 9. FIG. 9 is a diagram showing a gate drive circuit 500 according to the third embodiment. As shown in FIG. 9, the power conversion device is configured including the gate drive circuit 500, and the gate drive circuit 500 includes a voltage feedback unit 2, a gate drive unit 3, a discharge unit 4, a first current limiting element 5, and an insulating communication unit 6. Since this configuration is similar to that of the first and second embodiments, detailed description of the similar components will be omitted, and only differences from the first and second embodiments will be described below. Note that although the discharge unit 4 is shown to have the same configuration as that of the second embodiment, it is possible to appropriately apply a configuration that combines the configuration of the first embodiment or the configurations of the discharge units 4 of the first and second embodiments.

[0045] In the first and second embodiments, the invention is described as relating to a gate drive circuit having an active clamp function, but in the third embodiment, a configuration is provided in which the changeover switch 13 can optimize the active clamp operation.

[0046] 9, the gate drive circuit 500 in the third embodiment has a changeover switch 13 and a second current limiting element 10(b) connected in series, and a second current limiting element 10(a) connected in parallel, on the low-voltage side of the capacitor 9 in the voltage feedback section 2. The changeover switch 13 is configured using a changeover semiconductor switching element 14 (hereinafter also referred to as a changeover semiconductor SW element 14), such as a MOSFET.

[0047] Based on information about the current or voltage flowing through the main circuit, the selector switch 13 can predict the surge voltage when the semiconductor switch element 1 is turned on and control the selector switch 13 accordingly. For example, by setting the second current limiting element 10(b) to a sufficiently small value and the second current limiting element 10(a) to a value sufficiently larger than 10(b), the switch 13 can be controlled to turn on or off when the surge voltage exceeds the allowable voltage. This allows the combined resistance of the second current limiting element to be set to a small value determined by the parallel circuit of 10(a) and 10(b), thereby strengthening the effect of the active clamp function and reducing the surge voltage. When the surge voltage does not exceed the allowable voltage, the switch 13 can be controlled to turn on or off, thereby weakening the effect of the active clamp function and reducing loss. In other words, the selector switch 13 can be used to switch between a strong and weak feedback action.

[0048] Here, it has been explained that second current limiting element 10(b) has a sufficiently small value, but depending on the design, second current limiting element 10(b) may be eliminated and a parallel circuit configuration may be used consisting of second current limiting element 10(a) and selector switch 13. In this case, the effectiveness of the active clamp can be significantly changed by turning on and off selector switch 13. Furthermore, for example, when installed in an automotive powertrain or electrical equipment, the active clamp function can be controlled to be stronger (enabled) or weaker (disabled) by turning on and off selector semiconductor SW element 14 in accordance with driving information such as torque or rotation speed in a higher-level command unit.

[0049] In this way, when there is a margin for the surge voltage relative to the allowable voltage, the active clamp function can be weakened (disabled), thereby suppressing the gate voltage increase caused by the active clamp and reducing switching losses.

[0050] So far, we have explained the active clamp circuit at turn-off that achieves both surge voltage reduction and loss reduction. By applying this circuit, the gate voltage rises even when the diode connected in anti-parallel to the semiconductor switching element 1 recovers, so that by temporarily turning on the semiconductor switching element 1, a small amount of short-circuit current flows in the arm of the power conversion device, making it possible to suppress the recovery surge voltage.

[0051] In order to suppress the recovery surge voltage, it is necessary to strengthen the active clamp function in order to raise the gate voltage of the target semiconductor switching element 1 from a negative bias state to the threshold voltage Vth. On the other hand, if the surge voltage at turn-off has a sufficient margin relative to the allowable surge voltage, it may be desirable to weaken the active clamp function in order to reduce loss. Thus, the third embodiment is effective even when there are conflicting requirements for the active clamp function at recovery and turn-off.

[0052] Specifically, by controlling the changeover switch 13 to be off at the time of turn-off, the combined resistance value of the second current limiting element is made sufficiently large to weaken the effect of the active clamp function and achieve low loss, while by controlling the changeover switch 13 to be on at the time of recovery, the combined resistance value of the second current limiting element is made small to strengthen the effect of the active clamp function and achieve suppression of the recovery surge voltage.

[0053] In this way, in addition to the same effects as in the first and second embodiments, it is possible to select between strengthening (enabling) or weakening (disabling) the functions according to the specifications, thereby making it possible to further reduce losses while suppressing surge voltages.

[0054] Although various exemplary embodiments have been described, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed herein. For example, this includes cases where at least one component is modified, added, or omitted, or where at least one component is extracted and combined with components of another embodiment. [Explanation of symbols]

[0055] 1 semiconductor switch element, 2 voltage feedback section, 3 gate drive section, 4 discharge section, 5 first current limiting element, 6 insulating communication section, 7 upper logic section, 8 first reverse blocking diode, 9 capacitor, 10 second current limiting element, 11 second reverse blocking diode, 12 inrush current suppression element, 13 changeover switch, 14 switching semiconductor switch element, 300, 400, 500 gate drive circuit.

Claims

1. a gate driver that applies a gate drive voltage to a control terminal of a semiconductor switching element to drive the semiconductor switching element; a voltage feedback section connected to a high potential main terminal of the semiconductor switching element and feeding back a voltage of the high potential main terminal generated when the semiconductor switching element is turned off to the gate driver; a discharge section that configures a path for discharging charges contained in the voltage feedback section to the high potential main terminal side of the semiconductor switching element when the semiconductor switching element is turned on; A gate drive circuit comprising:

2. 2. The gate drive circuit according to claim 1, wherein the voltage feedback section forms a path from a connection point on the gate drive section side to the high-potential main terminal of the semiconductor switching element.

3. 3. The gate drive circuit according to claim 1, wherein one end of the discharge section is connected to the voltage feedback section.

4. 4. The gate drive circuit according to claim 1, wherein the voltage feedback section has at least one of a capacitor and a voltage regulation diode, and a reverse blocking diode, and is provided between the high potential main terminal and an input side or an output side of the gate drive section.

5. 5. The gate drive circuit according to claim 4, wherein one end of the discharge section is connected between the reverse blocking diode and at least one of the capacitor and the voltage regulation diode that constitute the voltage feedback section.

6. 4. The gate drive circuit according to claim 1, wherein the voltage feedback section includes at least one of a second current limiting element and a reverse blocking diode that rectifies a current from the high potential main terminal to the gate drive section.

7. 6. The gate drive circuit according to claim 3, wherein the other end of the discharge section is connected to a potential side of a power supply that is applied to the control terminal when the gate drive section turns off the semiconductor switching element.

8. a first current limiting element that sets the input signal or output signal of the gate driver to a value different from an on / off command signal based on a signal from a higher-level logic unit, based on a feedback signal from the voltage feedback unit; 8. The gate drive circuit according to claim 1, wherein the discharge section discharges the capacitance included in the voltage feedback section via a path that does not pass through the first current limiting element.

9. The gate drive circuit according to claim 8 , wherein the discharge unit is connected in parallel with the first current limiting element.

10. 10. The gate drive circuit according to claim 1, wherein the gate drive section includes one or more stages of buffer circuits each composed of a bipolar transistor.

11. 11. The gate drive circuit according to claim 1, wherein the gate drive unit includes a composite buffer circuit including a buffer circuit configured with a MOSFET and a bipolar transistor connected in parallel with the source-side MOSFET of the buffer circuit.

12. 12. The gate drive circuit according to claim 1, wherein the voltage feedback section includes a switching semiconductor switching element capable of adjusting the strength of the feedback action.

13. 13. The gate drive circuit according to claim 12, wherein the on / off state of the switching semiconductor switching element is determined based on information about a current or voltage flowing through a main circuit.

14. 13. The gate drive circuit according to claim 12, wherein the on / off state of the switching semiconductor switching element is determined based on information from a higher-level command unit.

15. 15. The gate drive circuit according to claim 12, wherein the switching semiconductor switching element is turned on at a timing when a diode connected in antiparallel to the semiconductor switching element recovers.

16. 16. A power conversion device comprising: the gate drive circuit according to claim 1; and the semiconductor switching element; and converting externally input power by turning on and off the semiconductor switching element.

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