Power Amplifier Circuit

Abstract

To provide a power amplifier circuit which can widen a bandwidth.SOLUTION: A power amplifier circuit 100 includes: a distribution circuit 110; a first carrier amplifier 121 for amplifying a first input signal RF1 and outputting a first output signal RF10; a first peak amplifier 131 for amplifying a second input signal RF3 and outputting a second output signal RF30; a first converter 140; a second carrier amplifier 122 forming a differential pair with the first carrier amplifier, the second carrier amplifier amplifying a third input signal RF2 and outputting a third output signal RF20; a second peak amplifier 132 forming a differential pair with the first peak amplifier, the second peak amplifier amplifying a four input signal RF4 and outputting a fourth output signal RF40; a second converter 150; and a synthesis unit 160 for synthesizing signals output from the first converter and the second converter and outputting an output signal RFout.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power amplifier circuit. [Background technology]

[0002] A Doherty amplifier generally consists of a carrier amplifier, which operates regardless of the power level of the input signal, and a peak amplifier, which is turned off when the power level of the input signal is low and turned on when the power level is high, connected in parallel.The outputs of the carrier amplifier and the peak amplifier are combined using a combiner to operate as a highly efficient power amplifier.

[0003] The combiner uses a quarter-wavelength line, but the quarter-wavelength line is not suitable for miniaturization or broadband. In response to this, a Doherty amplifier that does not use a quarter-wavelength line has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2021-192476 Summary of the Invention [Problem to be solved by the invention]

[0005] The power amplifier circuit described in Patent Document 1 achieves miniaturization and wide bandwidth by not using a quarter-wavelength line. However, there is a demand for a power amplifier circuit with even wider bandwidth.

[0006] Therefore, an object of the present disclosure is to provide a power amplifier circuit that can achieve a wide bandwidth. [Means for solving the problem]

[0007] A power amplifier circuit according to one aspect of the present invention includes: a division circuit that divides an input signal into a first input signal, a second input signal whose phase lags that of the first input signal by approximately 90 degrees, a third input signal whose phase lags that of the first input signal by approximately 180 degrees, and a fourth input signal whose phase lags that of the second input signal by approximately 180 degrees; a first carrier amplifier that amplifies the first input signal and outputs a first output signal; a first peak amplifier that amplifies the second input signal and outputs a second output signal; a first converter including a first transformer formed of a first inductor and a second inductor, a capacitor connected in parallel with the first inductor, and a capacitor connected in parallel with the second inductor, wherein the first output signal is input to one end of the first inductor and the second output signal is input to one end of the second inductor; a second carrier amplifier that forms a differential pair with the first carrier amplifier and amplifies the third input signal and outputs a third output signal; the combiner includes: a second peak amplifier configured to amplify the fourth input signal and output a fourth output signal; a second converter including a second transformer formed of a third inductor and a fourth inductor, a capacitor connected in parallel with the third inductor, and a capacitor connected in parallel with the fourth inductor, wherein the third output signal is input to one end of the third inductor, the fourth output signal is input to one end of the fourth inductor, and the other end of the fourth inductor is electrically connected to the other end of the second inductor; a third transformer formed of a fifth inductor and a sixth inductor; a fifth capacitor connected in parallel with the fifth inductor, and one end of the sixth inductor is electrically connected to one end of the sixth inductor and the other end is electrically connected to an output terminal or ground, wherein one end of the fifth inductor is electrically connected to the other end of the first inductor and the other end is electrically connected to the other end of the third inductor.

[0008] A power amplifier circuit according to one aspect of the present invention includes: a first divider including a first transformer formed of a first inductor and a second inductor; a first capacitor connected in parallel with the first inductor; and a second capacitor connected in parallel with the second inductor, the first divider dividing a first signal input to one end of the first inductor into a first input signal and a second input signal that is delayed in phase by approximately 90 degrees from the first input signal; a first carrier amplifier amplifying the first input signal and outputting a first output signal; a first peak amplifier amplifying the second input signal and outputting a second output signal; and a combining circuit combining the first output signal and the second output signal.

[0009] A power amplifier circuit according to one aspect of the present invention includes a first divider including a first transformer formed of a first inductor and a second inductor, and a capacitor connected in parallel with the second inductor, wherein an input signal is input to one end of the first inductor via a capacitor, and the first divider distributes the input signal from one end of the second inductor as a first input signal and from the other end of the second inductor as a second input signal; a second transformer formed of a third inductor and a fourth inductor, one end of the third inductor is electrically connected to the other end of the first inductor, a capacitor connected in parallel with the third inductor, and a capacitor connected in parallel with the fourth inductor. a second divider that divides a third input signal from one end of the fourth inductor and a fourth input signal from the other end of the fourth inductor; a first carrier amplifier that amplifies the first input signal and outputs a first output signal; a second carrier amplifier that forms a differential pair with the first carrier amplifier and amplifies the second input signal and outputs a second output signal; a first peak amplifier that amplifies the third input signal and outputs a third output signal; a second peak amplifier that forms a differential pair with the first peak amplifier and amplifies the fourth input signal and outputs a fourth output signal; and a combining circuit that combines the first output signal, the second output signal, the third output signal, and the fourth output signal. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a power amplifier circuit capable of achieving a wide bandwidth. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a configuration diagram showing an outline of the configuration of a power amplifier circuit according to a first embodiment. [Figure 2] FIG. 10 is a diagram for explaining broadening of the bandwidth on the output side of the power amplifier circuit. [Figure 3] 10 is a graph showing an example of an improvement in the bandwidth ratio of a power amplifier circuit. [Figure 4] FIG. 1 is a diagram illustrating an example of a power amplifier circuit including a distribution circuit that can be regarded as a voltage source. [Figure 5] 10 is a graph showing a change in the phase difference between the carrier amplifier and the peak amplifier with respect to the ratio of the inductors of the dividing circuit. [Figure 6] FIG. 4 is a diagram illustrating a modification of the power amplifier circuit according to the first embodiment. [Figure 7] FIG. 10 is a diagram illustrating an outline of the configuration of a power amplifier circuit according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. Hereinafter, circuit elements with the same reference numerals will be referred to as the same circuit elements, and redundant description will be omitted.

[0013] Power Amplifier Circuit 100 According to the First Embodiment The configuration of a power amplifier circuit 100 according to the first embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing an outline of the configuration of the power amplifier circuit 100 according to the first embodiment.

[0014] The power amplifier circuit 100 is mounted, for example, on a mobile phone and is used to amplify the power of a signal to be transmitted to a base station. The power amplifier circuit 100 is mounted, for example, on a mobile communication device such as a mobile phone, amplifies the power of an input signal RFin to a level required for transmission to a base station, and outputs the amplified signal RFout. The input signal RFin is a radio frequency (RF) signal modulated according to a predetermined communication method by, for example, an RFIC (Radio Frequency Integrated Circuit). The communication standards of the input signal RFin include, for example, 2G (second generation mobile communication system), 3G (third generation mobile communication system), 4G (fourth generation mobile communication system), 5G (fifth generation mobile communication system), LTE (Long Term Evolution)-FDD (Frequency Division Duplex), LTE-TDD (Time Division Duplex), LTE-Advanced, or LTE-Advanced Pro, and the frequency is, for example, approximately several hundred MHz to several tens of GHz. Note that the communication standards and frequencies of the input signal RFin are not limited to these.

[0015] The power amplifier circuit 100 amplifies an input signal RFin and outputs an output signal RFout. The input signal is an RF signal, and the frequency of the input signal is, for example, about several GHz.

[0016] The power amplifier circuit 100 is a circuit including a Doherty amplifier that improves the matching band on the input side of various amplifiers and improves the frequency characteristics on the output side of various amplifiers to achieve a wider band.

[0017] 1, the power amplifier circuit 100 includes, for example, an input terminal 101, an output terminal 102, a distribution circuit 110, a first carrier amplifier 121, a second carrier amplifier 122, a first peak amplifier 131, a second peak amplifier 132, a first converter 140, a second converter 150, and a combiner 160. Each of the components will be described below.

[0018] For ease of explanation, the input terminal 101 side of the first carrier amplifier 121, the second carrier amplifier 122, the first peak amplifier 131, and the second peak amplifier 132 will be referred to as the "input side," and the output terminal 102 side will be referred to as the "output side."

[0019] The distribution circuit 110 distributes, for example, an input signal RFin that is input into an input signal RF1, an input signal RF2, an input signal RF3, and an input signal RF4.

[0020] The distribution circuit 110 is configured, for example, to output the input signal RF1 to the first carrier amplifier 121, the input signal RF3 to the first peak amplifier 131, the input signal RF2 to the second carrier amplifier 122, and the input signal RF4 to the second peak amplifier 132.

[0021] The distribution circuit 110 includes, for example, a first distributor 111, a second distributor 112, and a third distributor 113.

[0022] First divider 111 outputs input signal RFa and input signal RFb whose phase lags behind input signal RFa by approximately 180 degrees. Approximately 180 degrees includes, for example, a range of 135 degrees to 225 degrees. First divider 111 is formed of, for example, a balun transformer.

[0023] For example, the second divider 112 divides the input signal RFa into an input signal RF1 and an input signal RF3 that is 90 degrees out of phase with the input signal RF1. The second divider 112 includes, for example, a transformer formed by an inductor 112a and an inductor 112b, a capacitor 112c connected in parallel with the inductor 112a, and a capacitor 112d connected in parallel with the inductor 112b.

[0024] The transformer may also have an impedance matching function by adjusting the winding ratio of the inductor 112a and the inductor 112b. This allows the power amplifier circuit 100 to match impedance using the transformer formed on the chip without forming an output matching circuit outside the chip, thereby reducing the circuit size.

[0025] The inductor 112a has one end to which the input signal RFa is input, and the other end electrically connected to a first peak amplifier 131 (described later). The inductor 112b has one end electrically connected to a reference potential, and the other end electrically connected to a first carrier amplifier 121 (described later).

[0026] The capacitors 112c and 112d are provided for, for example, eliminating the effect of parasitic inductance of the transformer and for impedance matching of the transformer.

[0027] That is, the second divider 112, for example, while matching impedance with the load side, divides the input signal RFa input to one end of the inductor 112a into a signal RF1 output to the first carrier amplifier 121 and an input signal RF3 that is output to the first peak amplifier 131 and has a phase delay of 90 degrees relative to the signal RF1.

[0028] For example, the third divider 113 divides the input signal RFb into an input signal RF2 and an input signal RF4 that lags the phase of the input signal RF2 by 90 degrees. The third divider 113 includes, for example, a transformer formed by an inductor 113a and an inductor 113b, a capacitor 113c connected in parallel with the inductor 113a, and a capacitor 113d connected in parallel with the inductor 113b.

[0029] The inductor 113a has one end to which the input signal RFb is input, and the other end electrically connected to a second peak amplifier 132 (described later). The inductor 113b has one end electrically connected to a reference potential, and the other end electrically connected to a second carrier amplifier 122 (described later).

[0030] Capacitor 113c and capacitor 113d are provided for, for example, eliminating the influence of parasitic inductance of a transformer and for impedance matching of the transformer.

[0031] That is, the third divider 113, for example, while matching impedance with the load side, divides the input signal RFb input to one end of the inductor 113a into an input signal RF2 output to the second carrier amplifier 122 and an input signal RF4 that is output to the second peak amplifier 132 and has a phase delay of 90 degrees relative to the input signal RF2.

[0032] Since the division circuit 110 divides the signal into two signals having a phase difference of 90 degrees in the second divider 112 and the third divider 113, a quarter-wave line for operating the circuit as a Doherty amplifier is not required, thereby realizing miniaturization of the power amplifier circuit 100.

[0033] Furthermore, the distribution circuit 110 can achieve a wider bandwidth by adjusting the phase difference between the signals it distributes, as will be described in detail later.

[0034] The first carrier amplifier 121 amplifies the input signal RF1 and outputs an output signal RF10. The first carrier amplifier 121 is biased to be, for example, class AB or class B.

[0035] The second carrier amplifier 122 amplifies the input signal RF2 and outputs an output signal RF20. The second carrier amplifier 122 is biased to be, for example, class AB or class B.

[0036] The first peak amplifier 131 amplifies the input signal RF3 and outputs an output signal RF30. The first peak amplifier 131 is biased to be, for example, class AB or class C.

[0037] The second peak amplifier 132 amplifies the input signal RF4 and outputs the output signal RF40. The second peak amplifier 132 is biased to be, for example, class AB or class C.

[0038] That is, the first carrier amplifier 121 and the second carrier amplifier 122 operate at a power level equal to or greater than zero regardless of the power level of the input signal RFin. On the other hand, the first peak amplifier 131 and the second peak amplifier 132 operate when the voltage level of the input signal RFin is equal to or greater than a level Vback (hereinafter also referred to as "back-off") that is a predetermined level lower than the maximum level Vmax.

[0039] In this way, first peak amplifier 131 and second peak amplifier 132 operate in a region where the power level of input signal RFin is lower by a predetermined level (for example, about 6 dB) from the maximum level and is higher than zero.

[0040] In the power amplifier circuit 100, by combining two types of amplifiers depending on the power level of the input signal, the range in which the first carrier amplifier 121 and the second carrier amplifier 122 operate at saturated output is expanded, thereby improving power efficiency compared to a power amplifier circuit configured with only one type of amplifier.

[0041] In the power amplifier circuit 100, the first carrier amplifier 121 and the second carrier amplifier 122, and the first peak amplifier 131 and the second peak amplifier 132 form a differential pair. The differential pair includes two paired amplifying elements, and amplifies and outputs the potential difference between signals of the same amplitude but opposite phase that are input to the two amplifying elements.

[0042] In this way, when signals of the same amplitude and phase (for example, noise) are input simultaneously to each of the two amplifying elements, the signals of the same amplitude and phase are canceled out. That is, by using differential pairs for the first carrier amplifier 121 and the second carrier amplifier 122 and the first peak amplifier 131 and the second peak amplifier 132, it is possible to suppress the generation of noise and harmonics of the input signals.

[0043] The amplifying elements constituting the differential pair are not particularly limited, but may be, for example, bipolar transistors such as heterojunction bipolar transistors (HBTs) or field effect transistors such as metal-oxide-semiconductor field effect transistors (MOSFETs).

[0044] The first converter 140 combines the output signal RF10 output from the first carrier amplifier 121 with an output signal RF30 whose phase lags behind that of the output signal RF10 by 90 degrees.

[0045] The first converter 140 includes a transformer formed by an inductor 141 and an inductor 142 , a capacitor 143 connected in parallel with the inductor 141 , and a capacitor 144 connected in parallel with the inductor 142 .

[0046] The inductor 141 has one end to which the output signal RF10 is input, and the other end electrically connected to the combiner 160 (described later). The inductor 142 has one end electrically connected to the output of the first peak amplifier 131, and the other end to which power is supplied from the power supply Vcc and is electrically connected to the other end of the inductor 152.

[0047] Capacitor 143 and capacitor 144 are provided to eliminate the influence of parasitic inductance of the transformer, for example, and to match the impedance of the transformer.

[0048] The second converter 150 combines the output signal RF20 output from the second carrier amplifier 122 with an output signal RF40 whose phase lags that of the output signal RF20 by approximately 90 degrees.

[0049] The second converter 150 includes a transformer formed by an inductor 151 and an inductor 152, a capacitor 153 connected in parallel with the inductor 151, and a capacitor 154 connected in parallel with the inductor 152.

[0050] The inductor 151 has one end to which the output signal RF20 is input, and the other end electrically connected to the combiner 160 (described later). The inductor 152 has one end electrically connected to the output of the second peak amplifier 132, and the other end to which power is supplied from the power supply Vcc and is electrically connected to the other end of the inductor 142.

[0051] Capacitor 153 and capacitor 154 are provided to eliminate the influence of parasitic inductance of the transformer, for example, and to match the impedance of the transformer.

[0052] The combiner 160 combines the signals output from the first converter 140 and the second converter 150 to output an output signal RFout.

[0053] The combiner 160 includes a transformer formed by an inductor 161 and an inductor 162, a capacitor 163 connected in parallel with the inductor 161, and a capacitor 164 connected in parallel with the inductor 162. 2 The other end is electrically connected to the output terminal. Or ground and a capacitor 164 electrically connected to the

[0054] One end of inductor 161 is electrically connected to the other end of inductor 141, and the other end is electrically connected to the other end of inductor 151. Power is supplied to the midpoint of inductor 161 from power supply Vcc. Note that the midpoint includes points that are equidistant from one end and the other end of inductor 161, and points in the vicinity of the equidistant points.

[0055] In the power amplifier circuit 100, a broadband can be achieved in the first converter 140, the second converter 150, and the combiner 160. This will be specifically described below.

[0056] <<Output side circuit>> 2 and 3, an operation for achieving a wider bandwidth on the output side of the power amplifier circuit 100 will be described. Fig. 2 is a diagram for explaining the wider bandwidth on the output side of the power amplifier circuit 100. Fig. 3 is a graph showing an example of an improvement in the bandwidth ratio of the power amplifier circuit 100.

[0057] The power amplifier circuit 100 may have a configuration on the input side that provides a phase difference of 90 degrees between the signal input to the carrier amplifier and the signal input to the peak amplifier, where 90 degrees includes a range of, for example, 45 degrees to 135 degrees.

[0058] In the following, for convenience of explaining the bandwidth expansion on the output side of the power amplifier circuit 100, it is assumed that the circuit on the input side of the power amplifier circuit 100 is composed of, for example, a power divider 1100, balun transformers 1200 and 1300, and quarter-wavelength lines, as shown in Fig. 2. Note that the power divider 1100 may be, for example, a Wilkinson divider composed of quarter-wavelength lines connected in parallel with resistive elements electrically connecting one end of the lines. With this configuration, a signal input to the carrier amplifier has a phase difference of 90 degrees with respect to a signal input to the peak amplifier.

[0059] As described above, the first converter 140, the second converter 150, and the combiner 160 are provided on the output side of the power amplifier circuit 100.

[0060] 2, the first peak amplifier 131 is converted into a voltage source by the first converter 140, and the second peak amplifier 132 is converted into a voltage source by the second converter 150. The first peak amplifier 131 and the second peak amplifier 132 converted into voltage sources are connected in series to the first carrier amplifier 121 and the second carrier amplifier 122, respectively, to form a Doherty amplifier.

[0061] In the power amplifier circuit 100, the outputs of the first carrier amplifier 121 and the second carrier amplifier 122 of the differential pair are combined by a combiner 160 that converts the outputs into a current source.

[0062] In this way, in the power amplifier circuit 100, by combining the differential signals by the combiner 160 that converts them into a current source, the frequency characteristics generated by the first converter 140 and the second converter 150 can be canceled out by the frequency characteristics of the combiner 160. This is achieved by the combiner 160 operating to cancel out the frequency characteristics generated by the first converter 140 and the second converter 150. This allows the first carrier amplifier 121 and the second carrier amplifier 122 to operate over a wider band.

[0063] Here, the improvement of the bandwidth ratio of the power amplifier circuit 100 shown in Fig. 2 will be described with reference to Fig. 3. In Fig. 3, the vertical axis indicates the bandwidth ratio for impedance matching, and the horizontal axis indicates the phase difference between the carrier amplifier and the peak amplifier. In Fig. 3, for example, the frequency characteristic of the phase difference in the power amplifier circuit 100 including the combiner 160 shown in Fig. 2 is indicated by the symbol "301," and the frequency characteristic of the phase difference in the power amplifier circuit 100 not including the combiner 160 is indicated by the symbol "302."

[0064] 3, the frequency characteristics of the power amplifier circuit 100 without the combiner 160 are approximately 26% at most even when the phase difference is changed, whereas the frequency characteristics of the power amplifier circuit 100 with the combiner 160 reach a maximum of 39.4% by optimizing the phase difference. In other words, by including the combiner 160, the power amplifier circuit 100 can significantly improve the fractional bandwidth at which impedances are matched.

[0065] Here, the reason why the first converter 140 and the second converter 150 can be regarded as voltage sources will be explained. The dependent matrices of the first converter 140 and the second converter 150 are calculated. When the diagonal elements of the dependent matrices are "0", the first converter 140 and the second converter 150 become circuits that swap voltage and current, multiply them by a constant, and output the result. In other words, when a current source such as a carrier amplifier is connected to the input side of the first converter 140 and the second converter 150, they can each be regarded as a voltage source when viewed from the output side of the first converter 140 and the second converter 150.

[0066] On the other hand, the combiner 160 can be regarded as a current source. When the off-diagonal elements of the dependent matrix of the combiner 160 are "0", and a current source such as a carrier amplifier is connected to the input side of the combiner 160, the combiner 160 can be regarded as a current source when viewed from the load side.

[0067] <<Input side circuit>> 4 and 5, a description will be given of broadening the bandwidth by optimally setting the phase difference in the distribution circuit 110 on the input side of the power amplifier circuit 100. Fig. 4 is a diagram showing an example of a power amplifier circuit 100 including a distribution circuit 110a that can be regarded as a voltage source. Fig. 5 is a graph showing the change in the phase difference between the carrier amplifier and the peak amplifier with respect to the ratio of the inductors of the distribution circuit 110a.

[0068] As described above, the input side of the power amplifier circuit 100 is provided with the divider circuit 110 including the second divider 112 and the third divider 113. This allows the power amplifier circuit 100 to intentionally set the frequency characteristics when dividing the input signal RFin without using a quarter-wave line.

[0069] In the following, as an example, as shown in FIG. 4, regarding optimization of the phase difference on the input side of the power amplifier circuit 100, it is assumed that the power amplifier circuit 100 is configured with a single carrier amplifier 120 and a peak amplifier 130, and includes a distribution circuit 110a.

[0070] The dividing circuit 110a divides, for example, the input signal RFin into an input signal RF11 and an input signal RF12 whose phase lags behind that of the input signal RF11 by 90 degrees.

[0071] The dividing circuit 110a includes, for example, a transformer formed by an inductor 114 and an inductor 115, a capacitor 116 connected in parallel with the inductor 114, and a capacitor 117 connected in parallel with the inductor 115.

[0072] The inductor 114 has one end to which the input signal RFin is input, and the other end electrically connected to the carrier amplifier 120. The inductor 115 has one end electrically connected to a reference potential, and the other end electrically connected to the peak amplifier 130.

[0073] Capacitor 116 and capacitor 117 are provided for, for example, eliminating the effect of parasitic inductance of a transformer and for impedance matching of the transformer.

[0074] In the power amplifier circuit 100 shown in FIG. 4, in the distribution circuit 110a, the windings of the inductors that form the transformer are adjusted, and the ratio between the two inductances is adjusted.

[0075] Referring to Fig. 5, it will be explained how the frequency characteristics of input signals RF11 and RF12 can be adjusted by adjusting the ratio between the two inductances. Fig. 5 is a graph showing the change in phase difference versus the ratio between the two inductances. In Fig. 5, the vertical axis represents the value obtained by normalizing the differentiated phase difference with the center frequency of the design, and the horizontal axis represents the ratio between the two inductances.

[0076] As shown in Fig. 5, the dividing circuit 110a exhibits the characteristic of the curve indicated by the reference numeral 501, and therefore the frequency characteristic of the phase difference can be adjusted by adjusting the inductance ratio of the inductors. In this way, by providing a configuration that can adjust the frequency characteristic of the phase difference, it is possible to set the frequency characteristic of the phase difference that maximizes the relative bandwidth shown in Fig. 3 (for example, a phase difference of 90 degrees in Fig. 3). This makes it possible to achieve a wider bandwidth for the power amplifier circuit 100.

[0077] As described above, in the power amplifier circuit 100 shown in FIG. 1 as well, the phase difference can be adjusted by adjusting the winding ratio of each of the inductors constituting the second divider 112 and the third divider 113 included in the distribution circuit 110, and therefore it is possible to set the phase difference that maximizes the fractional bandwidth shown in FIG. 3.

[0078] The transformer of the distribution circuit 110a may also have an impedance matching function by adjusting the winding ratio of the inductor 114 and the inductor 115. This allows the power amplifier circuit 100 to match impedance using the transformer formed on the chip without forming an output matching circuit outside the chip, thereby reducing the circuit size.

[0079] <<Modifications>> A modified example of the power amplifier circuit 100 will be described with reference to Fig. 6. Fig. 6 is a diagram showing a modified example of the power amplifier circuit 100 according to the first embodiment.

[0080] As shown in FIG. 6, compared to the power amplifier circuit 100, the power amplifier circuit 100a according to the modified example has a configuration in which power is supplied to each of the first carrier amplifier 121, the second carrier amplifier 122, the first peak amplifier 131, and the second peak amplifier 132 through an inductor.

[0081] Specifically, the first carrier amplifier 121 receives a power supply Vcc via an inductor 171 at a node N1 between the first carrier amplifier 121 and one end of the inductor 141 of the first converter 140 .

[0082] Furthermore, the first peak amplifier 131 is supplied with the power supply Vcc via the inductor 173 to a node N3 between the first peak amplifier 131 and one end of the inductor 142 of the first converter 140 .

[0083] In addition, the second carrier amplifier 122 is supplied with the power supply Vcc via the inductor 172 to a node N2 between the second carrier amplifier 122 and one end of the inductor 151 of the second converter 150.

[0084] Furthermore, the second peak amplifier 132 is supplied with the power supply Vcc via an inductor 174 to a node N4 between the second peak amplifier 132 and one end of the inductor 152 of the second converter 150 .

[0085] Here, in the power amplifier circuit 100, when the input signal RFin is at a high frequency, there is a risk that the operation of the combiner 160 may be disturbed due to the parasitic capacitance generated in each amplifier.

[0086] Therefore, in the power amplifier circuit 100a, power is supplied to each amplifier through an inductor, causing parallel resonance between the output parasitic capacitance generated in each amplifier and the inductor. This makes it possible to suppress signal attenuation at high frequencies due to current flowing through the parasitic capacitance, thereby maximizing the performance of the combiner 160.

[0087] Power Amplifier Circuit 200 According to the Second Embodiment A power amplifier circuit 200 according to a second embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram showing an outline of the configuration of the power amplifier circuit 200 according to the second embodiment. In the power amplifier circuit 200 according to the second embodiment, a description of matters common to the above-described embodiments will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned one by one.

[0088] As shown in FIG. 7, the power amplifier circuit 200 differs from the power amplifier circuit 100 according to the first embodiment in the configuration of the input side circuit.

[0089] Specifically, the distribution circuit 210 includes a distributor that can be regarded as a current source (hereinafter referred to as a "current source distributor 211") and a distributor that can be regarded as a voltage source (hereinafter referred to as a "voltage source distributor 212").

[0090] The current source distributor 211 includes, for example, a transformer formed by an inductor 211a and an inductor 211b, and a capacitor 211d connected in parallel with the inductor 211b.

[0091] An input signal RFin is input to one end of inductor 211a via capacitor 211c, and is then split into an input signal RF1 output from one end of inductor 211b and an input signal RF2 output from the other end of inductor 211b.

[0092] The input signal RF1 is input to the first carrier amplifier 221. The input signal RF2 is input to the second carrier amplifier 222.

[0093] The voltage source divider 212 includes, for example, a transformer formed by an inductor 212a and an inductor 212b, a capacitor 212c connected in parallel with the inductor 212a, and a capacitor 212d connected in parallel with the inductor 212b.

[0094] One end of inductor 212a is electrically connected to the other end of inductor 211a. That is, an input signal RFin is input to inductor 212a via inductor 211a. The input signal RFin is then split into an input signal RF3 output from one end of inductor 212b and an input signal RF4 output from the other end of inductor 212b.

[0095] The input signal RF3 is input to the first peak amplifier 231. The input signal RF4 is input to the second peak amplifier 232.

[0096] Here, in the power amplifier circuit 200, when the off-diagonal elements of the subordinate matrix in the current source divider 211 are "0", the current source divider 211 can be regarded as a current source when viewed from the output side.

[0097] Furthermore, in power amplifier circuit 200, when the diagonal elements of the subordinate matrix in voltage source divider 212 are "0", voltage source divider 212 becomes a circuit that swaps the voltage and current, multiplies them by a constant, and outputs the result. That is, in power amplifier circuit 200, when voltage source divider 212 is viewed from the output side, voltage source divider 212 can be regarded as a voltage source.

[0098] In power amplifier circuit 200, the input side circuit in power amplifier circuit 100 was configured by three dividers, first divider 111 to third divider 113, but it can be configured by current source divider 211 and voltage source divider 212, which allows for downsizing. This can be achieved because the phase relationship between the input terminal (input terminal 201 side) and output terminal (output terminal 202 side) of current source divider 211 and voltage source divider 212 is clear.

[0099] Specifically, in the power amplifier circuit 100, when a balun transformer is used for the first divider 111, it is necessary to provide the second divider 112 and the third divider 113 in order to provide a phase difference of approximately 90 degrees between the signals input to the carrier amplifier and the peak amplifier of the differential pair.

[0100] In the power amplifier circuit 200, when a current flows on the input side of the current source divider 211, a current in phase with the current is generated on the output side. That is, an in-phase signal and a signal that is out of phase with the in-phase signal by approximately 180 degrees are generated on the output side of the current source divider 211. Therefore, the input signal RF1 is a signal in phase with the input signal RFin, and the input signal RF2 is a signal whose phase is delayed by approximately 180 degrees from the input signal RFin.

[0101] On the other hand, when a current flows on the input side of voltage source divider 212, a current that is approximately 90 degrees out of phase with the current is generated on the output side. That is, a signal that is approximately 90 degrees out of phase with the current and a signal that is approximately 180 degrees out of phase with the current are generated on the output side of voltage source divider 212. Therefore, third input signal RF3 is a signal that lags in phase with input signal RFin by approximately 90 degrees, and input signal RF4 is a signal that lags in phase with input signal RFin by approximately 270 degrees. Here, the fact that the phases are shifted by approximately 90 degrees in voltage source divider 212 is clear from the fact that in the subordinate matrix of voltage source divider 212, off-diagonal elements are marked with "j," which indicates the imaginary unit, and diagonal elements are not marked with "j," which indicates the imaginary unit.

[0102] As a result, the power amplifier circuit 200 can achieve a wide bandwidth by being configured to be able to set a phase difference that maximizes the relative bandwidth as shown in FIG. 3 (for example, a phase difference of approximately 90 degrees in FIG. 3) while reducing the circuit size.

[0103] 7 shows the output side circuit of power amplifier circuit 200 as being configured with first converter 240, second converter 250, and combiner 260, but is not limited to this. The output side circuit may be any circuit that can combine signals output from first carrier amplifier 221, second carrier amplifier 222, first peak amplifier 231, and second peak amplifier 232, and may be configured, for example, by combining a quarter-wavelength line and a balun transformer.

[0104] ===Summary=== <1> The power amplifier circuit 100 according to the exemplary embodiment of the present disclosure includes a divider circuit 110 that divides an input signal RFin into an input signal RF1 (first input signal), an input signal RF3 (second input signal) whose phase lags behind the input signal RF1 (first input signal) by 90 degrees, an input signal RF2 (third input signal) whose phase lags behind the input signal RF1 (first input signal) by 180 degrees, and an input signal RF4 (fourth input signal) whose phase lags behind the input signal RF3 (second input signal) by 180 degrees; a first peak amplifier 131 that amplifies an input signal RF3 (second input signal) and outputs an output signal RF30 (second output signal); a transformer (first transformer) formed by an inductor 141 (first inductor) and an inductor 142 (second inductor); a capacitor 143 connected in parallel with the first inductor 141 (first inductor); and a capacitor 144 connected in parallel with the inductor 142 (second inductor). a first converter 140 configured to receive an output signal RF10 (first output signal) at one end of an inductor 141 (second inductor) and to receive an output signal RF30 (second output signal) at one end of an inductor 142 (second inductor); a second carrier amplifier 122 that forms a differential pair with the first carrier amplifier 121 and amplifies an input signal RF2 (third input signal) to output an output signal RF20 (third output signal); and a second peak amplifier that forms a differential pair with the first peak amplifier 131 and amplifies an input signal RF4 (fourth input signal) to output an output signal RF40 (fourth output signal). a second converter 150 including a transformer (second transformer) formed by an inductor 132, an inductor 151 (third inductor), and an inductor 152 (fourth inductor), a capacitor 153 connected in parallel with the inductor 151 (third inductor), and a capacitor 154 connected in parallel with the inductor 152 (fourth inductor), wherein an output signal RF20 (third output signal) is input to one end of the inductor 151 (third inductor), and an output signal RF40 (fourth output signal) is input to one end of the inductor 152 (fourth inductor);The power amplifier circuit 100 includes a second converter 150 configured so that the other end of the inductor 152 (fourth inductor) is electrically connected to the other end of the inductor 142, a transformer (third transformer) formed of an inductor 161 (fifth inductor) and an inductor 162 (sixth inductor), a combiner 160 including a capacitor 163 (fifth capacitor) connected in parallel with the inductor 161 (fifth inductor), and a capacitor 164 (sixth capacitor) having one end electrically connected to one end of the inductor 162 (sixth inductor) and the other end electrically connected to the output terminal 102 or ground, wherein one end of the inductor 161 (fifth inductor) is electrically connected to the other end of the inductor 141 (first inductor) and the other end is electrically connected to the other end of the inductor 151 (third inductor). This allows the power amplifier circuit 100 to configure a Doherty amplifier without using a quarter-wavelength line, thereby enabling miniaturization and broadband.

[0105] <2> In the power amplifier circuit 100a (variant example) according to the exemplary embodiment of the present disclosure, the first carrier amplifier 121 is supplied with power supply Vcc via an inductor 171 to a node N1 between the first carrier amplifier 121 and one end of an inductor 141 (first inductor) of the first converter 140, the first peak amplifier 131 is supplied with power supply Vcc via an inductor 173 to a node N3 between the first peak amplifier 131 and one end of an inductor 142 (second inductor) of the first converter 140, the second carrier amplifier 122 is supplied with power supply Vcc via an inductor 172 to a node N2 between the second peak amplifier 132 and one end of an inductor 151 (third inductor) of the second converter 150, and the second peak amplifier 132 is supplied with power supply Vcc via an inductor 174 to a node N4 between the second peak amplifier 132 and one end of an inductor 152 (fourth inductor) of the second converter 150. This makes it possible to suppress signal attenuation at high frequencies due to current flowing through parasitic capacitance, thereby maximizing the performance of the combiner 160.

[0106] <3> In the power amplifier circuit 100 according to the exemplary embodiment of the present disclosure, the distribution circuit 110 includes a first divider 111 that divides an input signal RFin into an input signal RFa (first signal) and an input signal RFb (second signal) that is delayed in phase by 180 degrees from the input signal RFa (first signal), a transformer (fourth transformer) formed by an inductor 112a (seventh inductor) and an inductor 112b (eighth inductor), a capacitor 112c connected in parallel with the inductor 112a (seventh inductor), and a capacitor 112d connected in parallel with the inductor 112b (eighth inductor), and divides the input signal RFa (first signal) input to one end of the inductor 112a (seventh inductor) into an input signal RFb (second signal) that is output via the inductor 112a (seventh inductor). 3 (No. 2 input signal) and the input signal RF output through the inductor 112b (eighth inductor). 1 (No. 1 a second divider 112 that divides an input signal RFb (second signal) input to one end of the inductor 113a (ninth inductor) into an input signal RFb (second signal) that is output through the inductor 113a (ninth inductor), a transformer (fifth transformer) formed by an inductor 113a (ninth inductor) and an inductor 113b (tenth inductor), a capacitor 113c that is connected in parallel with the inductor 113a (ninth inductor), and a capacitor 113d that is connected in parallel with the inductor 113b (tenth inductor), 4 (No. 4 input signal) and the input signal RF output through inductor 113b (tenth inductor). 2 (No. 3 input signal) and a third distributor 113 that distributes the <1> or <2> As a result, the power amplifier circuit 100 includes a distribution circuit 110 that can adjust the phase difference, making it possible to set the phase difference that maximizes the fractional bandwidth shown in FIG. 3, thereby achieving a wider bandwidth.

[0107] <4> In the power amplifier circuit 200 according to the exemplary embodiment of the present disclosure, the division circuit 210 includes a fourth divider including a transformer (sixth transformer) formed of an inductor 211a (eleventh inductor) and an inductor 211b (twelfth inductor) and a capacitor 211d connected in parallel with the inductor 211b (twelfth inductor), wherein an input signal RFin is input to one end of the inductor 211a (eleventh inductor) through the capacitor 211c, and the current source divider 211 (fourth divider) divides the input signal RFin from one end of the inductor 211b (twelfth inductor) as an input signal RF1 and distributes the input signal RFin from the other end of the inductor 211b (twelfth inductor) as an input signal RF2 (third input signal); a transformer (seventh transformer) formed of an inductor 212a (thirteenth inductor) and an inductor 212b (fourteenth inductor) electrically connected to the other end of the inductor 211a (eleventh inductor), a capacitor 212c connected in parallel with the inductor 212a (thirteenth inductor), and a capacitor 212d connected in parallel with the inductor 212b (fourteenth inductor), the voltage source divider 212 (fifth divider) including: an input signal RFin input through the inductor 211a (eleventh inductor) divided as an input signal RF3 (second input signal) from one end of the inductor 212b (fourteenth inductor) and divided as an input signal RF4 (fourth input signal) from the other end of the inductor 212b (fourteenth inductor). <1> or <2> As a result, the power amplifier circuit 200 can be made smaller without using a quarter-wave line, and can set the phase difference that maximizes the fractional bandwidth shown in FIG. 3, thereby achieving a wider bandwidth.

[0108] <5> A power amplifier circuit 100 according to an exemplary embodiment of the present disclosure includes a dividing circuit 110a (first divider) including a transformer (first transformer) formed of an inductor 114 (first inductor) and an inductor 115 (second inductor), a capacitor 116 (first capacitor) connected in parallel with the inductor 114 (first inductor), and a capacitor 117 (second capacitor) connected in parallel with the inductor 115 (second inductor), and an input signal RFin (second divider) input to one end of the inductor 114 (first inductor) is divided into a first divider and a second divider. The power amplifier circuit 100 includes a divider circuit 110a (first divider) that divides an input signal RF11 (first input signal) into an input signal RF11 (first input signal) and an input signal RF12 (second input signal) whose phase lags that of the input signal RF11 (first input signal) by 90 degrees, a carrier amplifier 120 (first carrier amplifier) that amplifies the input signal RF11 (first input signal) and outputs a first output signal, a peak amplifier 130 (first peak amplifier) that amplifies the input signal RF12 (second input signal) and outputs a second output signal, and a combiner 160 that combines the first output signal and the second output signal. This allows the input-side circuit of the power amplifier circuit 100 to be configured without using a quarter-wavelength line, thereby achieving miniaturization. Furthermore, the power amplifier circuit 100 can achieve a wide bandwidth because it is possible to set a phase difference that maximizes the fractional bandwidth of the circuit.

[0109] <6> The power amplifier circuit 100 according to an exemplary embodiment of the present disclosure includes: <5> 1 , the carrier amplifier 120 is a first carrier amplifier 121, and the peak amplifier 130 is a first peak amplifier 131, the third divider 113 further includes a first divider 111 (second divider) that divides an input signal RFin into an input signal RFa (first signal) and an input signal RFb (second signal) whose phase is delayed by 180 degrees from the input signal RFa (first signal), a transformer (second transformer) formed by an inductor 113a (third inductor) and an inductor 113b (fourth inductor), a capacitor 113c connected in parallel with the inductor 113a (third inductor), and a capacitor 113d connected in parallel with the inductor 113b (fourth inductor), and The converter further includes a third divider 113 that divides a signal RFb (second signal) into an input signal RF2 (third input signal) and an input signal RF4 (fourth input signal) whose phase lags behind that of the input signal RF2 (third input signal) by 90 degrees, a second carrier amplifier 122 that forms a differential pair with the first carrier amplifier 121, amplifies the input signal RF2 (third input signal), and outputs an output signal RF20 (third output signal), and a second peak amplifier 132 that forms a differential pair with the first peak amplifier 131, and amplifies the input signal RF4 (fourth input signal), and outputs an output signal RF40 (fourth output signal), and the first converter 140, the second converter 150, and the combiner 160 (combiner) combine the output signal RF10 (first output signal), the output signal RF30 (second output signal), the output signal RF20 (third output signal), and the output signal RF40 (fourth output signal). This allows the input side circuit of the power amplifier circuit 100 to be configured without using a quarter-wave line, thereby realizing miniaturization. Also, the power amplifier circuit 100 can set the phase difference that maximizes the fractional bandwidth of the circuit, thereby realizing a wider bandwidth.

[0110] <7> A power amplifier circuit 200 according to an exemplary embodiment of the present disclosure includes a current source divider 211 (first divider) including a transformer (first transformer) formed of an inductor 211a (first inductor) and an inductor 211b (second inductor), and a capacitor 211d connected in parallel with the inductor 211b (second inductor), in which an input signal RFin is input to one end of the inductor 211a (first inductor) through the capacitor 211c, and the input signal RFin is output from one end of the inductor 211b (second inductor) as an input signal RF1 (first input signal). a current source divider 211 (first divider) that divides the input signal RF1 (second input signal) from the other end of the inductor 211b (second inductor), a transformer (second transformer) formed by an inductor 212a (third inductor) having one end electrically connected to the other end of the inductor 211a (first inductor) and an inductor 212b (fourth inductor), a capacitor 212c that is connected in parallel with the inductor 212a (third inductor), and a capacitor 212d that is connected in parallel with the inductor 212b (fourth inductor), a voltage source divider 212 (second divider) in which an input signal RF3 (third input signal) is distributed from one end of an inductor 212b (fourth inductor) and an input signal RF4 (fourth input signal) is distributed from the other end of the inductor 212b (fourth inductor); a first carrier amplifier 221 that amplifies an input signal RF1 (first input signal) and outputs an output signal RF10 (first output signal); and a second carrier amplifier 222 that forms a differential pair with the first carrier amplifier 221 and amplifies an input signal RF2 (second input signal) and outputs an output signal RF20 (second output signal). 22, a first peak amplifier 231 that amplifies an input signal RF3 (third input signal) and outputs an output signal RF30 (third output signal), a second peak amplifier 232 that forms a differential pair with the first peak amplifier 231 and amplifies an input signal RF4 (fourth input signal) and outputs an output signal RF40 (fourth output signal), and a first converter 240, a second converter 250, and a combiner 260 (combining circuit) that combine the output signal RF10 (first output signal), the output signal RF20 (second output signal), the output signal RF30 (third output signal), and the output signal RF40 (fourth output signal).As a result, the power amplifier circuit 200 can be configured to set the phase difference that maximizes the fractional bandwidth shown in FIG. 3 while reducing the circuit size, thereby achieving a wider bandwidth.

[0111] The above-described embodiments are intended to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. The present disclosure may be modified or improved without departing from its spirit, and equivalents thereof are also included in the present disclosure. In other words, designs modified by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements and their arrangements included in the embodiments are not limited to those exemplified and can be modified as appropriate. [Explanation of symbols]

[0112] 100, 200...power amplifier circuit, 110...distribution circuit, 121, 221...first carrier amplifier, 122, 222...second carrier amplifier, 131, 231...first peak amplifier, 132, 232...second peak amplifier, 140, 240...first converter, 150, 250...second converter, 160, 260...combiner.

Claims

1. a distribution circuit that distributes an input signal into a first input signal, a second input signal that lags the first input signal by 90 degrees in phase, a third input signal that lags the first input signal by 180 degrees in phase, and a fourth input signal that lags the second input signal by approximately 180 degrees in phase; a first carrier amplifier that amplifies the first input signal and outputs a first output signal; a first peak amplifier that amplifies the second input signal and outputs a second output signal; a first converter including a first transformer formed of a first inductor and a second inductor, a capacitor connected in parallel with the first inductor, and a capacitor connected in parallel with the second inductor, wherein the first output signal is input to one end of the first inductor and the second output signal is input to one end of the second inductor; a second carrier amplifier that forms a differential pair with the first carrier amplifier and amplifies the third input signal to output a third output signal; a second peak amplifier that forms a differential pair with the first peak amplifier and amplifies the fourth input signal to output a fourth output signal; a second converter including a second transformer formed of a third inductor and a fourth inductor, a capacitor connected in parallel with the third inductor, and a capacitor connected in parallel with the fourth inductor, wherein the third output signal is input to one end of the third inductor, the fourth output signal is input to one end of the fourth inductor, and the other end of the fourth inductor is electrically connected to the other end of the second inductor; a combiner including a third transformer formed of a fifth inductor and a sixth inductor, a fifth capacitor connected in parallel with the fifth inductor, and a sixth capacitor having one end electrically connected to one end of the sixth inductor and the other end electrically connected to an output terminal or a ground, wherein the fifth inductor has one end electrically connected to the other end of the first inductor and the other end electrically connected to the other end of the third inductor; A power amplifier circuit comprising:

2. the first carrier amplifier is supplied with power through an inductor to a node between the first converter and one end of a first inductor; the first peak amplifier is supplied with power through an inductor to a node between the first converter and one end of a second inductor; the second carrier amplifier is supplied with power through an inductor to a node between the second converter and one end of a third inductor; power is supplied to the second peak amplifier through an inductor to a node between the second peak amplifier and one end of a fourth inductor of the second converter; 2. The power amplifier circuit according to claim 1.

3. The distribution circuit includes: a first divider that divides the input signal into a first signal and a second signal that is delayed in phase by approximately 180 degrees from the first signal; a second divider including a fourth transformer formed of a seventh inductor and an eighth inductor, a capacitor connected in parallel with the seventh inductor, and a capacitor connected in parallel with the eighth inductor, and dividing the first signal input to one end of the seventh inductor into the second input signal output through the seventh inductor and the first input signal output through the eighth inductor; a third divider including a fifth transformer formed of a ninth inductor and a tenth inductor, a capacitor connected in parallel with the ninth inductor, and a capacitor connected in parallel with the tenth inductor, and dividing the second signal input to one end of the ninth inductor into the fourth input signal output through the ninth inductor and the third input signal output through the tenth inductor; 3. The power amplifier circuit according to claim 1, comprising:

4. The distribution circuit includes: a fourth divider including a sixth transformer formed by an eleventh inductor and a twelfth inductor, and a capacitor connected in parallel with the twelfth inductor, wherein the input signal is input to one end of the eleventh inductor via the capacitor, and the fourth divider distributes the input signal from one end of the twelfth inductor as the first input signal and from the other end of the twelfth inductor as the third input signal; a fifth divider including a seventh transformer formed of a thirteenth inductor, one end of which is electrically connected to the other end of the eleventh inductor, and a fourteenth inductor, a capacitor connected in parallel with the thirteenth inductor, and a capacitor connected in parallel with the fourteenth inductor, wherein the fifth divider distributes the input signal input through the eleventh inductor from one end of the fourteenth inductor as the second input signal and from the other end of the fourteenth inductor as the fourth input signal; 3. The power amplifier circuit according to claim 1, comprising:

Images