Resistive memory array

Abstract

A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the lateral periphery of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, pillar electrode, and each SC electrode forms a respective resistive switching cell (e.g., an OxRRAM cell). Vertical groups or banks of these cells can be connected in parallel, each sharing the same pillar electrode. The cells in a vertical cell bank can be written to or read from as a group to limit the effects of non-uniform CF formation in any one or more individual cells in the group.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate generally to the field of semiconductor devices, and more particularly to non-volatile resistive random access memory (ReRAM) arrays. [Background technology]

[0002] Generally, ReRAM is based on a sandwich structure, or cell, that includes a first electrode, a switching layer, and a second electrode. By deliberately applying a specific voltage, a reproducible and reversible resistance change is achieved by controlling the connection and disconnection of conductive filaments (CFs) in the switching layer.

[0003] When the CFs are connected to the electrodes, the ReRAM device is highly conductive and in the low resistance state (LRS). When the CFs are disconnected from the electrodes with a gap, the ReRAM is in the high resistance state (HRS). According to the composition of the CFs, ReRAM can be classified as oxygen vacancy-based ReRAM (OxRRAM) or metal ion-based ReRAM (also known as conductive bridge random access memory, CBRAM).

[0004] The resistance mechanism of CBRAM is explained by the formation of metal ions and their connection to the electrodes, which has been observed and confirmed by microscopy. The resistance switching mechanism of OxRRAM is rather more theoretical and is explained in terms of the migration of oxygen vacancies driven by the combined effects of electric field and thermal effects.

[0005] The movement of oxygen vacancies is stochastic in nature. Therefore, non-uniform CF formation causes stochastic resistance changes in OxRRAM. Non-uniform CF formation can manifest as poor CF formation (e.g., high resistance resistance (HRS) when long resistance resistance (LRS) is intended in OxRRAM cells), excessive CF formation (e.g., long resistance resistance (LRS) when long resistance resistance (HRS) is intended in OxPRAM cells), or variable CF formation across a group of cells (e.g., different low and / or high resistance values across a range of OxRAM cells). Summary of the Invention

[0006] In an embodiment of the present invention, a vertical resistive memory array is presented. The vertical resistive memory array includes a front vertical resistive memory unit including a front resistive random access memory (ReRAM) pillar and a first vertically stacked electrode group connected to a first side of the front ReRAM pillar. The front ReRAM pillar includes a first pillar electrode and a first switching liner around and in contact with a sidewall periphery of the first pillar electrode. The first vertically stacked electrode group includes a first upper single cell (SC) electrode in contact with the first switching liner and a first lower SC electrode in contact with the first switching liner.

[0007] In another embodiment of the present invention, a method for a vertical resistance change memory array is presented. The method includes receiving, by a memory controller, a read request from a requesting device to retrieve data stored in a single memory cell. The method includes applying, by the memory controller, a read potential to a vertical resistance change memory unit including multiple ReRAM cells sharing the same pillar electrode. The method includes determining, by the memory controller, an equivalent resistance of the vertical resistance change memory unit. The method includes determining, by the memory controller, a resistance state of the vertical resistance change memory unit. The method further includes returning, by the memory controller, a data value associated with the determined resistance state of the vertical resistance change memory unit to the requesting device.

[0008] In another embodiment of the present invention, a method for a vertical resistance change memory array is presented. The method includes receiving, by a memory controller, a read request from a requesting device to retrieve data stored in a single memory cell. The method includes applying, by the memory controller, a read potential to a vertical resistance change memory unit including multiple ReRAM cells sharing the same pillar electrode. The method includes determining, by the memory controller, a resistance of each of the multiple ReRAM cells in the vertical resistance change memory unit. The method includes determining, by the memory controller, a combined resistance of each of the multiple ReRAM cells in the vertical resistance change memory unit. The method further includes determining, by the memory controller, a resistance state of the vertical resistance change memory unit from the combined resistance, and returning, by the memory controller, a data value associated with the determined resistance state of the vertical resistance change memory unit to the requesting device.

[0009] These and other embodiments, features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings.

[0010] So that the manner in which the above-recited features of the invention are realized can be understood in detail, a more particular description of the invention briefly summarized above can be had by reference to embodiments thereof which are illustrated in the accompanying drawings.

[0011] It should be noted, however, that the present invention may admit of other equally effective embodiments, and therefore the accompanying drawings illustrate only typical embodiments of the invention and should not be considered as limiting its scope. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a perspective view of a vertical resistance change memory array 100 according to an embodiment of the present invention. [Figure 2A] 1A-1C are cross-sectional views of vertical resistive memory units according to various embodiments of the present invention. [Figure 2B] 1A-1C are cross-sectional views of ReRAM cells according to various embodiments of the present invention. [Figure 2C] FIG. 1 is a circuit diagram of a pair of vertical ReRAM cell banks according to various embodiments of the present invention. [Figure 2D] FIG. 10 is a circuit diagram of a pair of vertical ReRAM cell banks with non-uniform CF formation according to various embodiments of the present invention. [Figure 3A] FIG. 2 is a normal view of wiring and electrode patterns according to an embodiment of the present invention. [Figure 3B] FIG. 2 is a direct view of the wiring and electrode patterns according to the embodiment of the present invention. [Figure 4] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 5] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 6] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 7] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 8] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 9] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 10] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 11] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 12] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 13] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 14] 1A-1C are top-down views of one level of a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 15] 1 is a block diagram of a memory device embodying a vertical resistive memory array according to various embodiments of the present invention. [Figure 16] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 17] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 18] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 19] 1A-1D are diagrams of stages in the fabrication of an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 20] 1A-1C are diagrams illustrating methods of writing data to a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 21] 1A-1C are diagrams illustrating methods of reading data from a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 22] 1A-1C are diagrams illustrating methods of reading data from a vertical resistive change memory array, according to various embodiments of the present invention. [Figure 23] 1A-1C illustrate methods of manufacturing an integrated circuit device including a vertical resistive change memory array, according to various embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict merely exemplary embodiments of the invention. Like numbering in the drawings represents like elements.

[0014] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. These exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description and drawings, well-known features and technical details may be omitted so as not to unnecessarily obscure the presented embodiments.

[0015] Referring to the drawings, in which like components are labeled with like numerals, exemplary fabrication steps for forming an IC device including one or more ReRAM memory cells 100 are shown and described in more detail below. While this description may refer to some components of an IC device in the singular, it should be noted that an IC device may include two or more components. The particular components and cross-sectional orientations depicted in the drawings have been selected to best explain the various embodiments described herein.

[0016] A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the lateral periphery of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, pillar electrode, and each SC electrode forms a respective resistive switching cell (e.g., an OxRRAM cell). Vertical groups or banks of these cells can be connected in parallel, each sharing the same pillar electrode. The cells in a vertical cell bank can be written, read, reset, etc. as a group to limit the effects of non-uniform CF formation in any one or more individual cells in the group.

[0017] For clarity, reference is made herein to various numerals. When a numeral is followed by a subscript, a specific instance of the element of that numeral is referred to. When a numeral does not include a subscript, the element of that numeral is referred to generically.

[0018] FIG. 1 is a perspective view of a vertical resistive memory array 100 according to an embodiment of the present invention.

[0019] The vertical resistance change memory array 100 may include ReRAM pillars 102 and vertically stacked (also referred to herein as vertically aligned) single cell (SC) electrodes 104, each connected to the ReRAM pillars 102. The ReRAM pillars 102 include a switching liner 202 around the periphery of a conductive pillar electrode 204, as depicted in FIG. 2A. The switching liner 202, pillar electrode 204, and each SC electrode 104 are juxtaposed to form a respective ReRAM cell. The vertical resistance change memory array 100 may further include vertically stacked multi-cell (MC) electrodes 106, each connected to at least two SC electrodes 104 by a high resistance element (HRE) 108.

[0020] For example, the vertical resistive memory array 100 may include a front ReRAM pillar 102 f and rear ReRAM pillar 102 r The vertical resistive memory array 100 may include a front side ReRAM pillar 102. f vertically stacked SC electrodes 104 connected to flr and vertically stacked SC electrode 104 fur The vertical resistive memory array 100 may include a front ReRAM pillar 102. f vertically stacked SC electrodes 104 connected to fll and vertically stacked SC electrode 104 ful Similarly, the vertical resistive memory array 100 may further include a rear ReRAM pillar 102. r vertically stacked SC electrodes 104 connected to rlr and vertically stacked SC electrode 104 rur Similarly, the vertical resistive memory array 100 may include rear ReRAM pillars 102. r vertically stacked SC electrodes 104 connected to rll and vertically stacked SC electrode 104 rul and

[0021] The vertical resistive memory array 100 includes vertically stacked MC electrodes 106. lr and MC electrode 106 urand a vertically stacked MC electrode 106. ll and MC electrode 106 ul The MC electrode 106 may further include: lr is HRE108 flr SC electrode 104 flr The HRE 108 rlr SC electrode 104 rlr MC electrode 106 ur is HRE108 fur SC electrode 104 fur The HRE 108 rur SC electrode 104 rur MC electrode 106 ll is HRE108 fll SC electrode 104 fll The HRE 108 rll SC electrode 104 rll MC electrode 106 ul is HRE108 ful SC electrode 104 ful The HRE 108 rul SC electrode 104 rul can be connected to

[0022] SC electrode 104 flr , SC electrode 104 fll , SC electrode 104 rlr , SC electrode 104 rll , MC electrode 106 lr , MC electrode 106 ll , HRE electrode 108 flr , HRE electrode 108 fll , HRE electrode 108 rlr , or HRE electrode 108 rll , or a combination thereof, may be on the same underlying wiring level. For example, the top surfaces of each of such elements may be coplanar, and the bottom surfaces of each of such elements may be coplanar.

[0023] Similarly, the SC electrode 104 fur , SC electrode 104 ful , SC electrode 104 rur, SC electrode 104 rul , MC electrode 106 ur , MC electrode 106 ul , HRE electrode 108 fur , HRE electrode 108 ful , HRE electrode 108 rur , or HRE electrode 108 rul , or a combination thereof, may be on the same upper wiring level. For example, the top surfaces of each of such elements may be coplanar, and the bottom surfaces of each of such elements may be coplanar.

[0024] 1 illustrates a vertical resistance change memory array 100 including a pair of ReRAM pillars 102 and associated vertically aligned wiring features, it should be understood that this particular configuration is not required and that other alternative configurations are possible. For example, the vertical resistance change memory array 100 could include additional ReRAM pillars 102 and associated vertically aligned wiring features, or additional vertically aligned wiring features associated with a pair of ReRAM pillars 102, or both.

[0025] The vertical distance between wiring levels can vary depending on multiple factors and requirements. Similarly, the longitudinal length between wiring features can vary depending on multiple factors and requirements. It should be further understood that each SC electrode 104 and MC electrode 106 can be a patterned conductive element and can be formed of a first conductor material, such as copper (Cu), tungsten (W), etc., and that the HRE 108 can be a patterned conductive element and can be formed of a second conductor material having a higher resistivity than the first conductor, such as tantalum nitride (TaN), titanium nitride (TiN), etc.

[0026] It should further be understood that one MC electrode 106, two or more SC electrodes 104, and two or more associated HREs 108 may be electrically connected. ul is HRE108 fuland electrically connected to and thereby in communication with the HRE108 rul Electrically connected to and therefore in communication with HRE108 ful SC electrode 104 ful is electrically connected to and thereby in communication with the HRE108 rul SC electrode 104 rul is electrically connected to and thereby in communication with the

[0027] It should be appreciated that the vertical resistance change memory array 100 may be operatively disposed above a first metallization level and below a second metallization level in a wafer assembly, and one or more of the features of the vertical resistance change memory array 100 may provide electrical connections and communications between various components of at least the first and second metallization levels of the wafer assembly.

[0028] 2A illustrates a cross-sectional view of a vertical resistance change memory unit 210 according to various embodiments of the present invention. The vertical resistance change memory unit 210 generally includes a single ReRAM pillar 102, vertically stacked SC electrodes 104 in an upper interconnect level, and SC electrodes 104 in a lower interconnect level. The switching liner 202 of the ReRAM pillar 102, the pillar electrode 204 of the ReRAM pillar 102, and each SC electrode 104 are juxtaposed to form a respective ReRAM cell 230. A first group of the vertically stacked SC electrodes 104 may contact a first side of the ReRAM pillar 102, and a second group of the vertically stacked SC electrodes 104 may contact a second side of the ReRAM pillar 102.

[0029] For example, the vertical resistive memory unit 210 l SC electrode 104 la and SC electrode 104 lb and SC electrode 104 lc and SC electrode 104 ld and the ReRAM pillar 102. The switching liner 202, the pillar electrode 204, and the SC electrode 104 la are arranged side by side to form corresponding ReRAM cells 230 laSimilarly, the switching liner 202, the pillar electrode 204, and the SC electrode 104 lb are arranged side by side to form corresponding ReRAM cells 230 lb The ReRAM cell 230 is formed. lc and ReRAM cells 230 ld As a result, the vertical resistance change type memory unit 210 l is the ReRAM cell 230 la and ReRAM cell 230 lb and ReRAM cell 230 lc and ReRAM cell 230 ld and a bank or group of vertically aligned ReRAM cells 230 including:

[0030] Similarly, the vertical resistive memory unit 210 r SC electrode 104 ra and SC electrode 104 rb and SC electrode 104 rc and SC electrode 104 rd and a vertical resistive memory unit 210 l The same ReRAM pillar 102 associated with the switching liner 202, the pillar electrode 204, and the SC electrode 104. ra are arranged side by side to form corresponding ReRAM cells 230 ra Similarly, the switching liner 202, the pillar electrode 204, and the SC electrode 104 rb are arranged side by side to form corresponding ReRAM cells 230 rb The ReRAM cell 230 is formed. rc and ReRAM cells 230 rd As a result, the vertical resistance change type memory unit 210 r is the ReRAM cell 230 ra and ReRAM cell 230 rb and ReRAM cell 230 rc and ReRAM cell 230 rd and a bank or group of vertically aligned ReRAM cells 230 including:

[0031] FIG. 2B illustrates a cross-sectional view of a ReRAM cell 230, according to various embodiments of the present invention.

[0032] ReRAM is a non-volatile solid-state memory technology that exploits the resistance switching changes of insulators, such as binary metal oxides, when an electric field is applied. The basic storage unit ("cell") can be programmed to at least two different states or levels that exhibit different resistive properties. The programmable cell states can be used to represent different data values, enabling the storage of information.

[0033] ReRAM architectures typically consist of a resistive switching memory cell with a metal-insulator-metal structure, commonly referred to as the MIM structure. The structure consists of an insulating layer (I) sandwiched between two metal (M) electrodes. Application of a voltage pulse to a ReRAM cell allows the device to transition from an OFF state, known as HRS, or commonly referred to as logic "0," to an ON state, known as LRS, or commonly referred to as logic "1," or vice versa.

[0034] Typically, when prepared, a ReRAM cell is initially in the HRS state. To switch the device from the HRS to the LRS state, a formation voltage (e.g., a high-voltage pulse, a write voltage, etc.) is applied to allow the formation of CF in the switching layer, thereby switching the ReRAM cell to the LRS state. This process occurs due to the soft breakdown of the metal-insulator-metal (MIM) structure, commonly called "electroforming," and the voltage at which this process occurs is called the formation voltage. To switch a ReRAM cell from the LRS to the HRS state, a voltage pulse called the reset voltage is applied.

[0035] To read data from a ReRAM cell, a read voltage is applied that does not interfere with the cell's current state to determine whether the cell is HRS or LRS. Both LRS and HRS retain their respective values even after the applied voltage is removed, making ReRAM a non-volatile memory.

[0036] The switching of a ReRAM cell is based on the growth of carbon filaments inside an insulating layer. The carbon filaments are channels with nanometer-sized diameters that connect the electrodes of the cell. When the carbon filaments are connected between the electrodes, a highly conductive long-range resonator (LRS) is obtained, and when the filaments are disconnected from the electrodes, a high-resistance resonator (HRS) occurs.

[0037] The exemplary ReRAM cell 230 includes a switching liner 202 located between the SC electrode 104 and the pillar electrode 204. The cell state shown represents the LRS state, in which a CF 206 is formed in the switching liner 202 and contacts, touches, or otherwise connects to both the SC electrode 104 and the pillar electrode 204. When the CF 206 and the respective electrical connections between the SC electrode 104 and the pillar electrode 204 are formed and a read voltage is applied to read the programmed cell state, the resulting read current flows primarily through the CF 206 via a current path from one of the SC electrode 104 and the pillar electrode 204 to the other, rather than through the high-resistivity insulating material of the switching liner 202 in which the CF 206 is not formed.

[0038] To write to the ReRAM cell 230, a write or forming voltage is applied to the SC electrode 104 or the pillar electrode 204, and the resulting programming current flowing through the cell causes breakdown of the switching liner 202 and the formation of a CF 206 connecting the SC electrode 104 and the pillar electrode 204, thereby switching the RRAM cell 200 from the initial HRS to LRS.

[0039] The ReRAM cell 230 is read using the resistance of the cell 230 as a measure of the cell state. A read voltage applied to the SC electrode 104 or pillar electrode 204 causes a read current to flow through the cell 230. The read current depends on the resistance across or between the SC electrode 104 and the pillar electrode 204. A measurement of the cell read current therefore provides an indication of the state of the programmed cell 230. A sufficiently low read voltage is used for this resistance measure to ensure that the application of the read voltage does not interfere with the programmed cell state. The state of the cell 230 can then be detected by comparing the resistance measure with a predetermined reference level for the programmable cell state. To switch the ReRAM cell 230 back from the LRS to the initial HRS, a voltage pulse called a reset voltage is applied to the SC electrode 104 or pillar electrode 204.

[0040] FIG. 2C illustrates a vertical resistive memory unit 210 according to various embodiments of the present invention. l , 210 r As shown, a circuit diagram of a pair of vertical resistive memory units 210 is depicted. l and a vertical resistive memory unit 210 r Since the pillar electrodes 204 are shared, they share a circuit node. The voltage applied at such a node is V 204 In some embodiments, the applied voltage V 204 can be a low or ground potential, a set or write potential, a read potential, a reset potential, etc.

[0041] Vertical Resistive Memory Unit 210 l The voltage applied at each SC electrode 104 associated with l The vertical resistive memory unit 210 is depicted as r The voltage applied at each SC electrode 104 associated with r In some embodiments, V, which is an applied voltage, voltage pulse, etc.l and V r can be high voltages such as forming voltages, read voltages, set / reset voltages, etc. Generally, the SC electrodes 104 are not directly connected in the vertical direction. Therefore, each SC electrode 104 can be physically connected, for example, by the MC electrodes 108 / HREs 108, the VIAs 420 shown in FIG. 18, or other wiring mechanisms, or can be virtually connected by applying the same bias or potential to the corresponding SC electrodes 104.

[0042] Vertical Resistive Memory Unit 210 l may therefore be configured as a first bank or group of vertically aligned ReRAM cells 230 that are programmed, read, and / or reset as a group (i.e., vertical resistive memory units 210 l It should be understood that all vertically aligned ReRAM cells 230 in the vertical resistive memory unit 210 undergo the same program, write, read, reset, etc. operations. l may also be configured as a second bank or group of vertically aligned ReRAM cells 230 that are programmed, read, and / or reset as a group.

[0043] In some embodiments, V l is V r In this way, the vertical resistive memory unit 210 l , 210 r The ReRAM cells 230 in both V l and V r are not equal. In this way, each vertical resistive memory unit 210 l , 210 r The ReRAM cells 230 in the vertical resistive memory unit 210 may be subjected to different and / or simultaneous read, write, and reset operations. lWhile writing to the ReRAM cell 230 in the vertical resistive memory unit 210 r A read from the ReRAM cell 230 inside can be performed simultaneously.

[0044] FIG. 2D illustrates a vertical resistive memory unit 210 having non-uniform CF formation within each ReRAM cell 230 therein, according to various embodiments of the present invention. l , 210 r The circuit diagram of the pair is depicted.

[0045] As suggested herein, non-uniform CF formation can manifest as under-formation of CF 206. This occurs when a ReRAM cell 230 is maintained in its HRS when programmed to be LRS (i.e., LRS is intended but the cell 230 remains in HRS). Non-uniform CF formation can also manifest as over-formation of CF 206. This then occurs when a ReRAM cell 230 retains its LRS even after undergoing a reset operation (i.e., HRS is intended but the cell 230 remains in LRS). For example, as depicted, in a vertical resistive memory unit 210 l In the other ReRAM cells 230 la , 230 lb , and 230 ld In contrast, ReRAM cell 230 lc Poor formation of CF206 may be observed in the ReRAM cell 230. lc As a result of such poor formation of CF206, ReRAM cell 230 lc The HRS can be obtained by the vertical resistive memory unit 210. l 230 other ReRAM cells in la , 230 lb , and 230 ld is the LRS. Alternatively, the ReRAM cell 230 lc As a result of such poor formation of CF206, ReRAM cell 230 lc The LRS may be obtained by the vertical resistive memory unit 210. l230 other ReRAM cells in la , 230 lb , and 230 ld is HRS.

[0046] As also suggested herein, non-uniform CF formation can manifest as varying CF 206 formation across the range of the cells 230. This occurs when the ReRAM cells 230 in the vertical resistive memory unit 210 are subjected to operations such as write, reset, etc., and have different or varying resistance values across the range of the ReRAM cells 230 in the vertical resistive memory unit 210. For example, r Each ReRAM cell in the ra , ReRAM cell 230 rb , ReRAM cell 230 rc , and ReRAM cell 230 rd A reset operation may be performed on each of the vertical resistive memory units 210, which may become HRSs but have relatively different resistance values across them. r Each ReRAM cell in the ra , ReRAM cell 230 rb , ReRAM cell 230 rc , and ReRAM cell 230 rd A write operation may be performed on each of these, which will result in an LRS, but which may have different relative resistances between them.

[0047] To limit the effects of non-uniform CF 206 formation in any one or more individual cells 230 in the vertical resistive memory unit 210, each of the cells 230 may be simultaneously subjected to the same write, reset, program, etc. operation, after which one or more of the cells 230 in the vertical resistive memory unit 210 may experience non-uniform CF 206 formation.

[0048] The group of cells 230 in the vertical resistance change memory unit 210 are further read as a group. During the read operation, the resistance values of each cell 230 can be combined (e.g., the mean, median, mode, trimmed mean, etc. of the resistance values can be determined), and this combined resistance value can be used to determine the resistance state (e.g., LRS, HRS, etc.) of all of the cells 230 in the vertical resistance change memory unit 210. Thus, even if one or more of the cells 230 in the vertical resistance change memory unit 210 individually experience non-uniform CF 206 formation, a normalized resistance state of the group of cells 230 can be determined due to the presence or effect of other cells 230 in the vertical resistance change memory unit 210 that do not experience non-uniform CF 206 formation. The normalized resistance state of the group of cells 230 more accurately indicates the intended LRS or HRS of the cells 230 in the vertical resistive memory unit 210 due to the typically greater number of cells 230 in the unit 210 that did not experience non-uniform CF206 formation, or experienced minor non-uniform CF206 formation, relative to the cells 230 in the unit 210 (i.e., outlier cells) that experienced non-uniform CF206 formation resulting in a large difference in resistance relative to the average resistance of the cells 230 in the unit 210.

[0049] The number of ReRAM cells 230 in a vertical resistive memory unit 210 can be determined from a predetermined acceptable standard deviation of the resistance value of each cell 230 in the unit 210. If the resistance value of each ReRAM cell 230 in the unit 210 varies randomly with respect to the average resistance value of the cells 230 in the unit 210, the standard deviation of the range of the resistance value of each cell 230 in the unit 210 is determined to be smaller by "n" multiplied by the square root of "n", where "n" is the number of ReRAM cells 230 in the vertical resistive memory unit 210.

[0050] 3A and 3B illustrate direct views of a wiring and electrode pattern 250 according to an embodiment of the present invention. As shown in FIG. 3A, the wiring and electrode pattern 250 may be a wiring pattern formed from a first conductive material, in which case the MC electrodes 106, the SC electrodes 104, and the HREs 108 are formed from or with the first conductive material. As shown in FIG. 3B, the wiring and electrode pattern 250 may be a wiring pattern formed from a first conductive material and a second conductive material, in which case the MC electrodes 106 and the SC electrodes 104 are formed from or with the first conductive material, and the HREs 108 are formed from or with the second conductive material.

[0051] It should be understood that the HRE 108 may take the form of serpentine wiring connected to each SC electrode 104 and each MC electrode 106. The HRE 108 may be electrically connected in series to each SC electrode 104 and each MC electrode 106. The HRE 108 serves to reduce, limit, or phase out the current in the ReRAM cell 230. Typically, if the current in the ReRAM cell 230 is too high, non-uniform CF 206 formation may increase. For example, if the current through the ReRAM cell 230 is too high, excess formation may become more likely, which may ultimately cause the ReRAM cell 230 to become stuck in HRS. In this manner, the presence of the HRE 108 phases out, reduces, or otherwise limits the current through the ReRAM cell 230 relative to the current through the ReRAM cell 230 in the absence of the HRE 108.

[0052] The HRE 108 can aid in CF 206 formation by establishing a lower boundary or floor of resistance that sets or limits the current through the ReRAM cell 230. In an illustrative example, an initial voltage of 5 volts is established across the ReRAM cell 230, and the associated HRE is 10 kOhms. Initially, because the switching liner 202 is infinite or otherwise much larger in comparison, the full 5V drops across the ReRAM cell 230 before the CF 206 forms. Once CF 206 formation begins, the resistance of the filament path through the switching liner 202 drops. For example, the resistance through the switching liner 202 drops to 100 kOhms (the total resistance through the HRE 108 and the switching liner 202 is 110 kOhms). At this point, the voltage drop across the switching liner 202 is 5V*10k ohms / 110k ohms across the HRE 108 and 5V*100k ohms / 110k ohms across the switching liner 202. Over time, the CF 206 grows further, and at this point, a 10k ohm filament may be established. Then, 5V*10k ohms / 20k ohms drops across the HRE 108, while 5V*10k ohms / 20k ohms drops across the ReRAM cell 230. At this point, 2.5V drops across the CF 206, and the ReRAM cell 230 may not have enough voltage (or field) drop to induce further oxygen vacancy migration. Therefore, the CF 206 stops growing or forming. In this way, the formation of the CF 206 can be controlled using the external resistance of the HRE 108.

[0053] The HRE 108 may also establish a lower boundary to prevent damage caused by a shorted ReRAM cell 230. If a short is experienced, the HRE 108 effectively becomes a resistive boundary for the shorted ReRAM cell 230 such that excessive current flow through the cell 230 does not occur.

[0054] In some implementations, the SC electrode 104 may include a partial pillar recess, which may be a recess or gap through the SC electrode 104, with a shape associated with the perimeter of the ReRAM pillar 102. For example, the SC electrode 104 fl , SC electrode 104 fr , SC electrode 104 rl , and SC electrode 104 rr may each include a partial pillar recess. The partial pillar recesses of adjacent SC electrodes 104 (i.e., SC electrodes associated with the same ReRAM pillar 102) may together form a pillar recess 252 associated with the entire perimeter of the ReRAM pillar 102. For example, fl and SC electrode 104 fr The respective partial pillar recesses in the f and the SC electrode 104 rl and SC electrode 104 rr The respective partial pillar recesses in the r can be formed.

[0055] The sidewalls of the SC electrode 104 that face or otherwise define the pillar recess 252 may be referred to herein as pillar sidewalls 254, pillar-facing sidewalls 254, and the like.

[0056] 4 illustrates a manufacturing stage 300 of an IC device manufacturing method according to various embodiments of the present invention, in which multiple RRAM levels are formed, each comprising a dielectric layer 406 and a wiring and electrode pattern 250 formed on the dielectric layer 406.

[0057] For example, a dielectric layer 4061 may be formed on the dielectric layer 402 and / or the metal or conductive layer 404. In some implementations, the dielectric layer 402 and / or the metal or conductive layer 404 may be the top layer of a first back-end (BEOL) metallization level.

[0058] The wiring and electrode pattern 2501 may be formed on the dielectric layer 4061. The wiring and electrode pattern 2501 may be formed on the dielectric layer 4061 by subtractive techniques, in which undesired portions of the conductive material layer are removed while desired portions of the conductive material layer are maintained to form the wiring and electrode pattern 2501. In an exemplary implementation, a mask (not shown) may be formed on the conductive material layer (not shown). The mask may be patterned by known photolithography techniques. Portions of the mask may be maintained to protect desired portions of the underlying conductive material layer. The protected desired portions of the conductive material layer are maintained while the undesired portions of the conductive material layer are removed by an etchant. The mask may be removed to expose the desired portions of the conductive material layer, effectively forming the wiring and electrode pattern 2501.

[0059] The wiring and electrode pattern 2501 can be formed on the dielectric layer 4061 by additive techniques, in which a conductive material is added or deposited on the dielectric layer 4061. In an exemplary implementation, a first mask (not shown) can be formed on the dielectric layer 4061. The first mask can be patterned by known photolithography techniques to form first wiring trenches and / or first electrode trenches that expose portions of the underlying dielectric layer 4061. A first conductive material can be electroplated or otherwise deposited on the exposed portions of the underlying dielectric layer 4061 in the first wiring trenches and / or first electrode trenches. A second mask (not shown) can be formed on the first mask and on the first conductive material. The second mask and the first mask can be patterned by known photolithography techniques to form second wiring trenches and / or second electrode trenches that expose portions of the underlying dielectric layer 4061. A second conductive material may be electroplated or otherwise deposited onto exposed portions of the underlying dielectric layer 4061 in the second wiring trenches and / or the second electrode trenches. The first mask and the second mask may be removed, leaving the first conductive material features and the second conductive material features. The first conductive material may effectively form the SC electrodes 104 and the MC electrodes 106, and the second conductive material may effectively form the HREs 108.

[0060] Another dielectric layer 4062 may be formed on the dielectric layer 4061 and on the wiring and electrode pattern 2501. Another wiring and electrode pattern 2502 may be formed on the dielectric layer 4062 using subtractive or additive forming techniques. Another dielectric layer 4063 may be formed on the dielectric layer 4062 and on the wiring and electrode pattern 2502. Another wiring and electrode pattern 2503 may be formed on the dielectric layer 4063 using subtractive or additive forming techniques. Another dielectric layer 4064 may be formed on the dielectric layer 4063 and on the wiring and electrode pattern 2503. Another wiring and electrode pattern 2504 may be formed on the dielectric layer 4064 using subtractive or additive forming techniques. These processes form the dielectric layer 406 on the underlying dielectric layer 406 and on the underlying wiring and electrode pattern 250. n This can be continued until the dielectric layer 406 is formed. n On top of that, other wiring and electrode patterns 250 are formed using subtractive or additive forming techniques. n In some implementations, the dielectric layer 406 n On top and wiring and electrode pattern 250 n Over it, a dielectric layer 408 may be formed.

[0061] The dielectric layers 406, 408, etc. may be layers of octamethylcyclotetrasiloxane (OMCTS), tetraethyl orthosilicate (TEOS), etc., and may have a sheet thickness of 150 nm to 1500 nm.

[0062] Wiring and electrode patterns 250 n The various wiring and electrode patterns 2501 passing through the wiring and electrode patterns 250 nThe pillar recesses 252 associated with adjacent SC electrodes 104 in each of the wiring and electrode patterns 2501 passing through the wiring and electrode pattern 2501 may be formed to be vertically aligned. For example, the centers of the pillar recesses 2521, 2522, 2523, and 2524 may be located, coincident, etc., on the same vertical axis 411.

[0063] 5 illustrates a manufacturing stage 302 of an IC device manufacturing method according to various embodiments of the present invention. In stage 302, pillar trenches 412 are formed.

[0064] The pillar trench 412 may be a trench, hole, well, etc. formed in the stack of dielectric layers 406, 408 through a vertically aligned pillar trench, which may expose the pillar sidewall 254 of the SC electrode 104. As depicted, the pillar trench 412 may expose a portion of the dielectric layer 402.

[0065] The pillar trench 412 can be fabricated by subtractive formation techniques, in which unwanted portions of the dielectric layers 406, 408 are removed. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 408. The mask can be patterned by known photolithography techniques. Portions of the mask can be retained to protect desired portions of the underlying dielectric layers 406, 408. The removed portions of the mask can be vertically aligned with the aligned pillar trenches. The unwanted portions of the dielectric layers 406, 408 can be removed with an etchant, resulting in the formation of the pillar trench 412. The mask can be removed. Various known etch techniques can be utilized to form sidewalls of the trench 412 that are tapered, angled, or sloped relative to the xy plane, or that are orthogonal to the xy plane.

[0066] 6 illustrates a manufacturing stage 304 of an IC device manufacturing method according to various embodiments of the present invention, in which a switching liner 202 is formed within a pillar trench 412.

[0067] The switching liner 202 may be formed by known additive formation techniques. For example, the switching liner 202 may be formed on the sidewalls and lower surface of the trench 412, such as by chemical vapor deposition (CVD).

[0068] Switching liner 202 is H f O x , WO x , TaO x , TiO x , NiO x , SiO x , GeS, GeSe, etc., and may have a thickness of 1 nm to 30 nm.

[0069] 7 illustrates a manufacturing stage 306 of an IC device manufacturing method according to various embodiments of the present invention. In stage 306, pillar electrodes 204 are formed on the switching liners 202 in the pillar trenches 412.

[0070] The pillar electrode 204 may be formed on the switching liner 202 in the pillar trench 412 by an additive technique, in which a conductive material is added or deposited. In an exemplary implementation, a mask (not shown) may be formed on the dielectric layer 408. The mask may be patterned by known photolithography techniques to form an opening above the pillar trench 412. The conductive material may be electroplated or otherwise deposited on the switching liner 202 in the pillar trench 412. The mask may be removed, and the top surface of the pillar electrode 204 may be planarized to match the top surface of the dielectric layer 408 by chemical mechanical polishing (CMP). It should be understood that once the pillar electrode 204 is formed on the switching liner 202, the ReRAM pillar 102 is thereby formed.

[0071] 8 illustrates a manufacturing stage 308 of an IC device manufacturing method according to various embodiments of the present invention. In stage 308, a dielectric layer 414 is formed on the dielectric layer 408, and a wire 416 is formed in the dielectric layer 414.

[0072] In some implementations, the dielectric layer 414 may be the bottom layer of the second BEOL metallization level.

[0073] Wires 416 may be formed in the dielectric layer 414. Wiring trenches may be formed in the dielectric layer 414 by subtractive techniques, in which unwanted portions of the dielectric layer 414 are removed, thereby forming a wiring pattern, while maintaining desired portions of the dielectric layer 414. In an exemplary implementation, a mask (not shown) may be formed on the dielectric layer 414. The mask may be patterned by known photolithography techniques. Unwanted portions of the dielectric layer 414 may be removed with an etchant. The mask may be removed to expose a portion of the upper surface of the dielectric 408 and also to expose the upper surfaces of the ReRAM pillars 102.

[0074] The wires 416 can be formed in the dielectric layer 414 by additive techniques, in which a conductive material is added or deposited in wiring trenches in the dielectric layer 414. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 414. The mask can be patterned by known photolithography techniques to remove portions above the wiring trenches. The conductive material can be electroplated or otherwise deposited in the wiring trenches in the dielectric 414 onto exposed portions of the underlying ReRAM pillars 102. The mask can be removed, and the top surfaces of the wires 416 and the upper surface of the dielectric layer 414 can be planarized by CMP.

[0075] 9 depicts a fabrication stage 310 of an IC device fabrication method according to various embodiments of the present invention. In stage 310, pillar trenches 412 are formed. The pillar trenches 412 may be trenches, holes, wells, etc. formed in the stack of dielectric layers 406, 408 through the vertically aligned pillar trenches 254, which may expose the pillar sidewalls 254 of the SC electrode 104 and a portion of the upper surface of the metal or conductive layer 404.

[0076] 10 depicts a manufacturing stage 312 of an IC device manufacturing method according to various embodiments of the present invention. In stage 312, a switching liner layer 202' is formed in the pillar trenches 412 and over the dielectric layer 408.

[0077] The switching liner 202 may be formed by known additive techniques. For example, a switching liner layer 202′ may be formed on the dielectric layer 408 and on the sidewalls and lower surface of the trench 412 by atomic layer deposition (ALD), physical vapor deposition (PVD), or the like. The switching liner 202′ may be formed by H f O x , WO x , TaO x , TiO x , NiO x , SiO x , GeS, GeSe layers and may have a sheet thickness of 1 nm to 30 nm.

[0078] 11 depicts a manufacturing stage 314 of an IC device manufacturing method according to various embodiments of the present invention. In stage 314, the switching liner layer 202′ is partially removed from the upper surface of the dielectric layer 408 and from the upper surface of the metal or conductor layer 404, but is maintained on the sidewalls of the pillar trenches 412, thereby forming the switching liner 202.

[0079] The switching liner layer 202' can be partially removed by subtractive techniques, whereby portions of the switching liner layer 202' that are not desired are removed while portions of the switching liner layer 202' that are desired are maintained to form the switching liner 202. In an exemplary implementation, a directional etch technique can be utilized to remove the unwanted switching liner layer 202' from the upper surface of the dielectric layer 408 and from the bottom of the pillar trench 412. This etch generally exposes portions of the metal layer 404 within the pillar trench 412.

[0080] 12 depicts a manufacturing stage 316 of an IC device manufacturing method according to various embodiments of the present invention. In stage 316, pillar electrodes 204 are formed on the switching liner 202 and on the metal layer 404 in the pillar trenches 412.

[0081] The pillar electrode 204 may be formed on the switching liner 202 in the pillar trench 412 and on the metal layer 404 by an additive technique, in which a conductive material is added or deposited. In an exemplary implementation, a mask (not shown) may be formed on the dielectric layer 408. The mask may be patterned by known photolithography techniques to form openings above the pillar trench 412. The conductive material may be electroplated or otherwise deposited on the switching liner 202 and on the metal layer 404 in the pillar trench 412. The mask may be removed, and the top surface of the pillar electrode 204 may be planarized to match the top surface of the dielectric layer 408 by chemical mechanical polishing (CMP). It should be understood that once the pillar electrode 204 is formed on the switching liner 202, the ReRAM pillar 102 is thereby formed.

[0082] 13 depicts a manufacturing stage 318 of an IC device manufacturing method according to various embodiments of the present invention. In stage 318, a dielectric layer 414 is formed on dielectric layer 408, and wires 416 are formed in dielectric layer 414.

[0083] In some implementations, the dielectric layer 414 may be the bottom layer of the second BEOL metallization level.

[0084] Wires 416 may be formed in the dielectric layer 414. Wiring trenches may be formed in the dielectric layer 414 by subtractive techniques, in which unwanted portions of the dielectric layer 414 are removed, thereby forming a wiring pattern, while maintaining desired portions of the dielectric layer 414. In an exemplary implementation, a mask (not shown) may be formed on the dielectric layer 414. The mask may be patterned by known photolithography techniques. Unwanted portions of the dielectric layer 414 may be removed with an etchant. The mask may be removed to expose a portion of the upper surface of the dielectric 408 and to expose the upper surfaces of the ReRAM pillars 102.

[0085] The wires 416 can be formed in the dielectric layer 414 by additive techniques, in which a conductive material is added or deposited in wiring trenches in the dielectric layer 414. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 414. The mask can be patterned by known photolithography techniques to remove portions above the wiring trenches. The conductive material can be electroplated or otherwise deposited in the wiring trenches in the dielectric 414 onto exposed portions of the underlying ReRAM pillars 102. The mask can be removed, and the top surfaces of the wires 416 and the upper surface of the dielectric layer 414 can be planarized by CMP.

[0086] It should be understood that the structure of wires 416 and dielectric layers 414 can take the place of conductor or metal layer 404. In other words, a wiring level having a structure of wires 416 and dielectric layers 414 can be used as a base layer within which IC device formation can occur, instead of a potential plane conductor or metal layer 404. In these implementations, the ReRAM pillars 102 can contact the upper wires 416 as depicted and the lower base wires as described.

[0087] 14 depicts a top view of one level of a vertical resistance change memory array 100 according to various embodiments of the present invention. This level of the vertical resistance change memory array 100 includes wiring and electrode patterns 250 with ReRAM pillars 102 each formed in or in place of pillar recesses 252.

[0088] For example, pillar recess 252 r in or instead of pillar electrodes 204 r and Switching Liner 202 r ReRAM Pillar 102 r The pillar recess 252 f in or instead of pillar electrodes 204 f and Switching Liner 202 f ReRAM Pillar 102 f ReRAM pillar 102 r are combined with the corresponding SC electrodes 104 to form the ReRAM pillars 102 rr ReRAM cell 230 on the first side of rl and ReRAM Pillar 102 r ReRAM cell 230 on the second side rr ReRAM pillar 102 is formed. f ReRAM cell 230 on the first side of fl and ReRAM Pillar 102 fr ReRAM cell 230 on the second side fr is formed.

[0089] In some implementations, the MC electrodes 106 include via recesses 419. The via recesses 419 at each level of the vertical resistive memory array 100 may be aligned vertically and generally define the placement of vias that may connect to the MC electrodes 106 at various levels of the vertical resistive memory array 100.

[0090] FIG. 15 illustrates a block diagram of a memory device 500 embodying a vertical resistance change memory array 100 according to various embodiments of the present invention. The device 500 includes the vertical resistance change memory array 100 for storing and / or reading data. Reading and writing data to the vertical resistance change memory array 100 may be performed by a read / write controller, or controller, 510. The controller 510 includes commonly known forms of circuitry for programming appropriate vertically aligned cells 230 in the memory units 210 during data write operations and for performing read measurements to detect the state of each cell 230 in the vertical resistance change memory units 210 during data read operations. During these operations, the read / write controller 510 can address individual vertical resistance change memory units 210 by applying appropriate control signals to the word lines and bit lines of the array 100. Input data to, or to be written to, device 500 may undergo some form of write processing, such as coding for error correction, by write processing module 520 before being provided as input data to controller 510. Similarly, output data by controller 510, or data being read, may be processed by read processing module 530, such as for codeword detection and / or error correction, to recover the original input data.

[0091] The vertical resistance change memory array 100 may store information, for example, in two states of the programmable cells 230. As previously discussed, the programmable cell states correspond to different relative resistances between the respective cells 230. These states include at least HRS and LRS. The states of the programmable cells 230 are typically defined in the controller 510 based on a predetermined reference value or range of values of a measure of the combined resistance of the vertical resistance change memory units 210 used for read sensing. To program the vertical resistance change memory units 210 in a write operation, the controller 510 applies corresponding voltages to the MC electrodes 106, for example, by applying a write voltage, set voltage, program voltage, etc., at the SC electrodes 104 and a ground / low potential, for example, at the pillar electrodes 204, such that the resulting programming signals set the associated cells 230 to the desired state (e.g., LRS).

[0092] In a read operation, a (lower) read voltage is applied to the vertical resistive memory unit 210 and the resulting current flowing through these cells 230 is measured to obtain the resistance of these cells 230. The controller 510 can then detect the state of the programmed cells 230 of the vertically aligned cells 230 by combining the measured resistances of these cells 230 and comparing the combined measured resistance with the appropriate reference value described above.

[0093] In a reset operation, the controller 510 applies voltages to the vertical resistive memory unit 210 such that a corresponding reset voltage is applied at the SC electrode 104 and, for example, a ground potential / low potential is applied at the pillar electrode 204, such that the resulting reset signal effectively resets the associated cell 230 back to the HRS state.

[0094] 16 depicts a manufacturing stage 330 of an IC device manufacturing method according to various embodiments of the present invention. In stage 330, multiple RRAM levels are formed, each comprising a dielectric layer 406 and a wiring and electrode pattern 250 formed on the dielectric layer 406. In some implementations, stage 330 can be the same stage 300.

[0095] Various wiring and electrode patterns 2501 to 250 n may be formed to vertically align the via recesses 419 within the vertically aligned MC electrode 106. For example, the centers of the via recesses 4191, 4192, 4193, and 4194 may be positioned, aligned, etc. on the same vertical axis 415.

[0096] 17 depicts manufacturing stage 332 of an IC device manufacturing method according to various embodiments of the present invention. In stage 332, a via trench 413 is formed. In some implementations, stage 332 may be the same as stage 302 or stage 310.

[0097] The via trench 413 may be a trench, hole, well, etc. formed in the stack of dielectric layers 406, 408 through a vertically aligned via recess 419. As depicted, the pillar trench 412 may expose a portion of the dielectric layer 402 or the metal or conductor layer 404.

[0098] The via trench 413 can be fabricated by subtractive formation techniques, in which unwanted portions of the dielectric layers 406, 408 are removed. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 408. The mask can be patterned by known photolithography techniques. Portions of the mask can be retained to protect desired portions of the underlying dielectric layers 406, 408. The removed portions of the mask can be vertically aligned with the aligned via recesses 419. The unwanted portions of the dielectric layers 406, 408 can be removed with an etchant, resulting in the formation of the via trench 413. The mask can be removed. Various known etch techniques can be utilized to form sidewalls of the via trench 413 that are tapered, angled, or inclined relative to the xy plane, or that are orthogonal to the xy plane.

[0099] 18 depicts fabrication stage 334 of an IC device fabrication method according to various embodiments of the present invention. In stage 334, vias 420 are formed in via trenches 413 and on dielectric layer 402 or conductor or metal layer 404. In some implementations, stage 334 may occur before stages 304 or 312, in which case switching liner 202 or switching liner layer 202′ is not formed in via trenches 413.

[0100] The vias 420 can be formed in the via trenches 413 by additive techniques, in which case a conductive material is added or deposited. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 408. The mask can be patterned by known photolithography techniques to form openings above the via trenches 413. A conductive material can be electroplated or otherwise deposited in the via trenches 413, in contact with the sidewalls of the via recesses 419 of the MC electrodes 106 and in contact with the dielectric layer 402 or the conductor or metal layer 404. The mask can be removed, and the top surface of the vias 420 can be planarized to match the top surface of the dielectric layer 408 by chemical mechanical polishing (CMP).

[0101] 19 depicts manufacturing stage 335 of an IC device manufacturing method, according to various embodiments of the present invention. In stage 335, a dielectric layer 414 is formed on dielectric layer 408, and wires 417 are formed in dielectric layer 414. In some implementations, stage 335 may be the same as stage 308 or stage 318.

[0102] Wires 417 may be formed in the dielectric layer 414. Wiring trenches may be formed in the dielectric layer 414 by subtractive techniques, in which unwanted portions of the dielectric layer 414 are removed, thereby forming the wiring pattern, while maintaining desired portions of the dielectric layer 414. In an exemplary implementation, a mask (not shown) may be formed on the dielectric layer 414. The mask may be patterned by known photolithography techniques. Unwanted portions of the dielectric layer 414 may be removed with an etchant. The mask may be removed to expose portions of the upper surface of the dielectric 408 and to expose the upper surfaces of the vias 420.

[0103] The wires 417 can be formed in the dielectric layer 414 by additive techniques, in which a conductive material is added or deposited in wiring trenches in the dielectric layer 414. In an exemplary implementation, a mask (not shown) can be formed on the dielectric layer 414. The mask can be patterned by known photolithography techniques to remove portions above the wiring trenches. The conductive material can be electroplated or otherwise deposited in the wiring trenches in the dielectric 414 onto exposed portions of the underlying vias 420. The mask can be removed, and the top surfaces of the wires 417 and the upper surface of the dielectric layer 414 can be planarized by CMP.

[0104] 20 illustrates a method 700 for writing data to a vertical resistance change memory array 100 according to various embodiments of the present invention. The method 700 may be implemented by the controller 500, a controller unit in a processor, or other known memory array controller. The method 700 may begin at block 702 and continue by receiving a request to write a data value (block 703). For example, the controller 500 may receive a request from a processor or other requesting device to write a data value (e.g., a high "1" or a low "0") to a particular single cell.

[0105] The method 700 may continue by determining whether the data value is associated with an HRS or an LRS (blocks 704, 706). For example, a high "1" data value indicates an LRS, and a low "0" data value indicates an HRS. Thus, if the data value associated with the write request is a high "1," the controller 500 determines that the vertical resistance change memory unit 210 should be programmed to an LRS. Similarly, if the data value associated with the write request is a low "0," the controller 500 determines that the vertical resistance change memory unit 210 should be programmed to, maintained in, etc. an HRS.

[0106] The method 700 may continue if the LRS is determined by applying a high write voltage to the vertical resistance change memory unit 210 (block 708). For example, the controller 500 applies a voltage to the MC electrode 106 that corresponds to the high write voltage at the SC electrode 104 (block 712) and applies a ground / low voltage to the pillar electrode 204 associated with the SC electrode 104 (block 710). Alternatively, the controller 500 may apply a ground or low voltage to the MC electrode 106 that corresponds to the ground or low voltage at the SC electrode 104, and apply a high voltage to the pillar electrode 204.

[0107] The method 700 may continue by programming each of the cells 230 in the vertical resistive memory unit 210 that are LRS (pending any non-uniform formation of CF 206) so that they effectively store a high data value of "1" (block 714).

[0108] The method 700 may continue if the HRS is determined by applying a low write voltage, ground voltage, etc. to the vertical resistance change memory unit 210 (block 716). For example, the controller 500 applies a ground / low voltage to the MC electrode 106 that corresponds to the ground or low write voltage at the SC electrode 104 (block 720) and applies a ground / low voltage to the pillar electrode 204 associated with the SC electrode 104 (block 718). Alternatively, the controller 500 may apply a ground or low voltage to the MC electrode 106 that corresponds to the ground or low voltage at the SC electrode 104 and may also apply a low or ground voltage to the pillar electrode 204.

[0109] The method 700 may continue by programming each of the cells 230 in the vertical resistive memory unit 210 that are HRS (pending any non-uniform formation of CF 206) by passing a corresponding low or no current through each of the cells 230 so that they effectively store a low data value of "0" (block 722). The method 700 may end at block 724.

[0110] It should be appreciated that the controller 500 can receive a request to store a particular data value in a single or particular cell, and can then program the cell 230 in the vertical resistive memory unit 210 with that data value.

[0111] 21 illustrates a method 750 for reading data from a vertical resistive memory array according to various embodiments of the present invention. The method 750 may be implemented by the controller 500, a controller unit in a processor, or other known memory array controller. The method 750 may begin at block 752 and continue by receiving a request to read a data value (block 754). For example, the controller 500 may receive a request to read a data value (e.g., a high "1" or a low "0") from a particular single cell.

[0112] The method 750 may continue by determining the resistance across each cell 230 in the vertical resistive change memory unit 210. In an example implementation, the resistance across each cell 230 in the vertical resistive change memory unit 210 may be determined by setting a bank iteration variable “x” equal to 0 (block 756).

[0113] The method 750 may continue by applying a read voltage to ReRAM cell "x" in the vertical resistive memory unit 210 (block 758). For example, the controller 500 applies a voltage to the MC 106 and a low / ground voltage to the pillar electrode 204 such that a corresponding read voltage is applied at the SC electrode "x." Alternatively, the controller 500 applies a read voltage to the pillar electrode and a ground / low potential at the SC electrode "x."

[0114] The method 750 may continue by sensing the current through ReRAM cell “x” in the vertical resistive memory unit 210 (block 760). For example, the controller 500 measures or senses the current through ReRAM cell “x” as a result of applying a read voltage.

[0115] The method 750 may continue by determining the resistance of ReRAM cell “x” in the vertical resistive memory unit 210 from the sensed current flowing through ReRAM cell “x” (block 762). For example, the controller 500 determines the resistance of ReRAM cell “x” from the sensed current flowing through ReRAM cell “x.”

[0116] The method 750 may continue by determining whether ReRAM cell "x" is the last one in the vertical resistance change memory unit 210 (block 764). If ReRAM cell "x" is not the last one in the vertical resistance change memory unit 210, the bank iteration variable "x" is incremented (block 766) and the method 750 returns to block 758 until the resistance of each cell 230 in the vertical resistance change memory unit 210 has been determined. As depicted, 758, 760, 762, 764, and 766 may be performed sequentially by applying a loop of blocks. Alternatively, such a loop may be performed in parallel to simultaneously determine the respective resistance of each of the cells 230 in the vertical resistance change memory unit 210.

[0117] The method 750 may continue by combining the determined resistances of the ReRAM cells in the vertical resistance change memory units 210 (block 768). For example, the controller 500 may calculate a resistance mean of the determined resistances of the ReRAM cells in the vertical resistance change memory units 210, the controller 500 may calculate a resistance median of the determined resistances of the ReRAM cells in the vertical resistance change memory units 210, or the controller 500 may calculate a resistance mode of the determined resistances of the ReRAM cells in the vertical resistance change memory units 210. In particular implementations, the controller 500 may calculate a resistance trim median of the determined resistances of the ReRAM cells in the vertical resistance change memory units 210, where a predetermined amount or percentage of the highest determined resistance, or a predetermined amount or percentage of the lowest determined resistance, or both, are discarded in determining the resistance trim median. For example, when ten ReRAM cells 230 are in the vertical resistive memory unit 210, the controller 500 may exclude or otherwise discard one highest determined resistance and one lowest determined resistance of the group of ReRAM cells 230 and calculate an average resistance value over a range of eight values. The combined resistance value (e.g., mean, median, mode, trimmed mean, etc.) of each of the determined resistance values of the ReRAM cells 230 in the vertical bank or group, determined in block 768, is defined herein as the combined resistance.

[0118] The method 750 may continue by determining whether the combined resistance is greater than or less than a predetermined threshold (block 770). The predetermined threshold may be an expected or theoretical resistance measure associated with the ReRAM cells 230 in the vertical resistive change memory unit 210, where if the combined resistance is greater than the threshold, a weighting, majority, etc. of the cells 230 in the vertical resistive change memory unit 210 is essentially programmed to HRS, and if the combined resistance is less than the threshold, a weighting, majority, etc. of the cells 230 in the vertical resistive change memory unit 210 is essentially programmed to LRS.

[0119] If the combined resistance is less than a threshold, the method 750 may continue by effectively determining that the vertical resistance change memory unit 210 stores a data value associated with the LRS (block 772). For example, the controller 500 may determine that the vertical resistance change memory unit 210 stores a high "1" if the combined resistance is less than a threshold. The method 750 may continue by returning the data value associated with the LRS to the requesting device (block 774). For example, the controller 500 may return a high "1" data value to the requesting device (e.g., a processor).

[0120] If the combined resistance is greater than a threshold, the method 750 may continue by effectively determining that the vertical resistance change memory unit 210 stores a data value associated with the HRS (block 776). For example, the controller 500 may determine that the vertical resistance change memory unit 210 stores a low "0" if the combined resistance is greater than a threshold. The method 750 may continue by returning the data value associated with the LRS to the requesting device (block 778). For example, the controller 500 may return a high "1" data value to the requesting device (e.g., a processor).

[0121] The method 750 may continue by resetting the cell 230 in the vertical resistance change memory unit 210 if a reset operation is required (block 780). For example, the controller 500 may receive a reset request. The controller 500 may then reset the cell 230 in the vertical resistance change memory unit 210, for example, by applying a reset voltage to the associated SC electrode 104 and a ground / low voltage to the shared pillar electrode 204. The method 750 may end at block 782. Alternatively, the controller 500 may reset the cell 230 in the vertical resistance change memory unit 210, for example, by applying a reset voltage to the pillar electrode 204 and a ground / low voltage to the associated SC electrode 104. The method 750 may end at block 782.

[0122] It should be appreciated that the controller 500 can receive a request to return a particular data value in a single or particular cell, and can then read the cells 230 in the vertical resistive memory unit 210 to ascertain the collective data value stored in the vertical resistive memory unit 210 and return that value to the requesting device.

[0123] 22 illustrates a method 850 for reading data from a vertical resistance change memory array according to various embodiments of the present invention. The method 850 may be implemented by the controller 500, a controller unit in a processor, or other known memory array controller. The method 850 may begin at block 852 and continue by receiving a request to read a data value (block 854). For example, the controller 500 may receive a request from a processor or other requesting device to read a data value (e.g., a high "1" or a low "0") from a particular single cell.

[0124] The method 850 may continue by determining the resistance across the vertical resistance change memory unit 210. This may be accomplished by applying a read voltage to each SC electrode 104 of the cells 230 in the vertical resistance change memory unit 210 (block 856). For example, the controller 500 applies a voltage to the MC 106 such that a corresponding read voltage is applied to each SC electrode 104 of the cells 230 in the vertical resistance change memory unit 210.

[0125] The method 850 may continue by sensing (block 858) a current through the vertical resistance change memory unit 210. For example, the controller 500 measures or senses a current through the vertical resistance change memory unit 210 as a result of applying a read voltage at each SC electrode of the cells 230 in the vertical resistance change memory unit 210.

[0126] The method 850 may continue by determining an equivalent resistance of the vertical resistance change memory unit 210 from the sensed current flowing through the vertical resistance change memory unit 210 (block 860). For example, the controller 500 determines an equivalent resistance of the vertical resistance change memory unit 210 from the sensed current flowing through the vertical resistance change memory unit 210.

[0127] The method 850 may continue by determining whether the equivalent resistance is greater than or less than a predetermined threshold (block 862). The predetermined threshold may be an expected or theoretical resistance measure associated with the ReRAM cells 230 in the vertical resistance change memory unit 210, where if the equivalent resistance is greater than the threshold, a weight, majority, etc. of the cells 230 in the vertical resistance change memory unit 210 are essentially programmed in HRS, and if the equivalent resistance is less than the threshold, a weight, majority, etc. of the cells 230 in the vertical resistance change memory unit 210 are essentially programmed in LRS.

[0128] If the equivalent resistance value is less than the threshold value, the method 850 may continue by effectively determining that the vertical resistance change memory unit 210 stores a data value associated with the LRS (block 864). For example, the controller 500 may determine that the vertical resistance change memory unit 210 stores a high "1" if the equivalent resistance is less than the threshold value. The method 850 may continue by returning the data value associated with the LRS to the requesting device (block 866). For example, the controller 500 may return a high "1" data value to the requesting device (e.g., a processor).

[0129] If the equivalent resistance value is greater than the threshold value, the method 850 may continue by effectively determining that the vertical resistance change memory unit 210 stores a data value associated with the HRS (block 868). For example, the controller 500 may determine that the vertical resistance change memory unit 210 stores a low "0" if the equivalent resistance is greater than the threshold value. The method 850 may continue by returning the data value associated with the LRS to the requesting device (block 870). For example, the controller 500 may return a high "1" data value to the requesting device (e.g., a processor).

[0130] The method 850 may continue by resetting the cell 230 in the vertical resistance change memory unit 210 if a reset operation is required (block 872). For example, the controller 500 may receive a reset request. The controller 500 may then reset the cell 230 in the vertical resistance change memory unit 210, for example, by applying a reset voltage to the associated SC electrode 104 and a ground / low voltage to the shared pillar electrode 204. Alternatively, the controller 500 may reset the cell 230 in the vertical resistance change memory unit 210, for example, by applying a reset voltage to the pillar electrode 204 and a ground / low voltage to the associated SC electrode 104. The method 750 may end at block 782. The method 850 may end at block 874.

[0131] It should be appreciated that the controller 500 can receive a request to return a particular data value in a single or particular cell, and can then read from the vertical resistive memory unit 210 to ascertain the collective data value stored in the vertical resistive memory unit 210 and return that value to the requesting device.

[0132] 23 illustrates a method 800 for fabricating an IC device including a vertical resistive memory array 100 according to various embodiments of the present invention. The method 800 may be used to fabricate IC devices such as processors, memories, ASICs, FPGAs, etc.

[0133] The method 800 begins at block 802 and continues by forming a first dielectric layer (block 804). For example, a dielectric layer 4061 is formed over the dielectric layer 402, the conductor or metal layer 404, or the like.

[0134] The method 800 may continue by forming a first wiring and electrode layer on the first dielectric layer (block 806). For example, wiring and electrode pattern 2501 is formed on dielectric layer 4061.

[0135] The method 800 may continue by forming a second dielectric layer over the first wiring and electrode layer and over the first dielectric layer (block 808). For example, a dielectric layer 4062 is formed over the wiring and electrode pattern 2501 and over the dielectric layer 4061.

[0136] The method 800 may continue by forming a second wiring and electrode layer on the second dielectric layer (block 810). For example, wiring and electrode pattern 2502 may be formed on dielectric layer 4062. Pillar recesses associated with SC electrodes of the first wiring and electrode layer may be vertically aligned with pillar recesses associated with SC electrodes of the second wiring and electrode layer (block 812). For example, pillar recess 2521 associated with SC electrode 1041 of wiring and electrode pattern 2501 may be vertically aligned with pillar recess 2522 associated with SC electrode 1042 of second wiring and electrode pattern 2502. VIA recesses associated with MC electrodes of the first wiring and electrode layer may be vertically aligned with VIA recesses associated with SC electrodes of the second wiring and electrode layer (block 814). For example, a via recess 4191 associated with an MC electrode 1061 of the wiring and electrode pattern 2501 may be vertically aligned with a via recess 4192 associated with an MC electrode 1062 of the second wiring and electrode pattern 2502 .

[0137] The method 800 may continue by forming a pillar trench through the first wiring and electrode layer and through the second wiring and electrode layer, thereby exposing pillar sidewalls of the SC electrodes of the first wiring and electrode layer and pillar sidewalls of the SC electrodes of the second wiring and electrode layer (block 816). For example, pillar trench 412 is formed through wiring and electrode pattern 2501, wiring and electrode pattern 2502, dielectric layer 4062, and dielectric layer 4061. Pillar trench 412 exposes pillar sidewall 2541 of SC electrode 1041 and pillar sidewall 2542 of SC electrode 1042. Pillar trench 412 may also expose a portion of underlying dielectric layer 402, a portion of underlying conductor or metal layer 404, a portion of underlying conductor or wire, etc.

[0138] The method 800 may continue by forming a switching liner on the sidewalls of the pillar trench (block 818). For example, a switching liner 202 is formed on the sidewalls of the pillar trench 412. The switching liner 202 may also be formed on the lower surface of the pillar trench 412, or in other words, on the portion of the dielectric layer 402 exposed by the pillar trench 412. The switching liner is connected to the pillar sidewalls of the SC electrodes of the first wiring and electrode layer and the pillar sidewalls of the SC electrodes of the second wiring and electrode layer (block 820). For example, the switching liner 202 may contact the exposed pillar sidewall 2541 of the SC electrode 1041 and also contact the exposed pillar sidewall 2542 of the SC electrode 1042.

[0139] Method 800 may continue by forming a via trench through the first wiring and electrode layer and the second wiring and electrode layer, thereby exposing sidewalls of the MC electrodes of the first wiring and electrode layer and sidewalls of the MC electrodes of the second wiring and electrode layer (block 822). For example, via trench 413 is formed through wiring and electrode pattern 2501, wiring and electrode pattern 2502, dielectric layer 4062, and dielectric layer 4061. Via trench 413 exposes sidewalls of via recess 419 of MC electrode 1061 and sidewalls of via recess 419 of MC electrode 1062. Via trench 413 may also expose a portion of underlying dielectric layer 402, a portion of underlying conductor or metal layer 404, a portion of underlying conductor or wire, etc.

[0140] The method 800 may continue by forming a pillar electrode on the switching liner in the pillar trench (block 824). For example, the pillar electrode 204 is formed on the switching liner 202 in the pillar trench 412.

[0141] Method 800 may continue by forming a via in the via trench (block 826). For example, via 420 is formed in via trench 413. The via is connected to the via recess sidewalls of the MC electrode of the first wiring and electrode layer and the via recess sidewalls of the MC electrode of the second wiring and electrode layer (block 828). For example, via 420 contacts the sidewalls of the exposed via recess 419 of MC electrode 1061 and also contacts the sidewalls of the exposed via recess 419 of MC electrode 1062.

[0142] The method 800 may continue by forming a first wiring feature with the top dielectric layer that contacts the pillar electrode, and forming a second wiring feature in the top dielectric layer that contacts the via (block 830). For example, a dielectric layer 408 is formed on the dielectric layer 4062. A wire 416 is formed in the dielectric layer 408 that contacts the pillar electrode 204, and a wire 417 is formed in the dielectric layer 408 that contacts the via 420. The method 800 may end at block 832.

[0143] It should be understood that the fabrication steps described in the various blocks herein or depicted in FIG. 23 do not have to be performed in the order presented, but may be performed in any order to efficiently fabricate an IC device including the vertical resistive memory array 100 as described herein.

[0144] In the accompanying drawings and this description, embodiments of the present invention and their features and components have been illustrated and described. Those skilled in the art will appreciate that any specific designations used herein are merely for convenience, and that the present invention is not limited by the specific processes identified and / or suggested by such designations. It is therefore desired that the embodiments described herein be considered in all respects as illustrative and not restrictive, and that reference be made to the appended claims to determine the scope of the invention.

[0145] The exemplary methods and techniques described herein may be used in the manufacture or verification of IC chips. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., as a single wafer containing multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads affixed to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded wiring). The chip is then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product may be any product containing an integrated circuit chip, ranging, by way of non-limiting example, from toys and other low-end applications to sophisticated computer products with numerous components, such as a display, keyboard or other input device, or central processor, or a combination thereof.

[0146] References herein to terms such as "vertical," "horizontal," and the like are made by way of example and not limitation, for purposes of establishing a frame of reference. The term "horizontal," as used herein, is defined as a conventional plane or a plane parallel to the surface of dielectric layer 402, metal or conductor layer 404, etc., regardless of the actual orientation of the IC device in space. The term "vertical" refers to a direction perpendicular to the horizontal direction defined above. Terms such as "on," "above," "below," "side" (e.g., as found on a "sidewall"), "higher," "lower," "over," "top," "under," and "beneath" are defined relative to the horizontal plane. It is understood that various other frames of reference may be employed to describe the present invention without departing from the scope of the present invention. The present disclosure also discloses the following inventions. <Appendix 1> 1. A vertical resistive memory array, comprising: a front-side vertical resistive random access memory (RRAM) unit comprising a front-side RRAM pillar and a first vertically stacked electrode group connected to a first side of the front-side RRAM pillar; the front-side RRAM pillar comprises a first pillar electrode and a first switching liner around and in contact with a sidewall periphery of the first pillar electrode; the first vertically stacked electrode group comprises a first upper single cell (SC) electrode in contact with the first switching liner and a first lower SC electrode in contact with the first switching liner; Vertical resistive memory array. <Appendix 2> The front side vertical resistive memory unit comprises: 2. The vertical resistance change memory array of claim 1, further comprising a second group of vertically stacked electrodes connected to a second side of the front RRAM pillar, the second group of vertically stacked electrodes comprising a second upper SC electrode in contact with the first switching liner and a second lower SC electrode in contact with the first switching liner. <Appendix 3> a rear-side vertical resistive memory unit comprising a rear-side RRAM pillar and a third vertically stacked electrode group connected to a first side of the rear-side RRAM pillar; the rear RRAM pillar comprises a second pillar electrode and a second switching liner around a sidewall periphery of the second pillar electrode; the third vertically stacked electrode group comprises a third upper SC electrode in contact with the second switching liner and a third lower SC electrode in contact with the second switching liner; 3. The vertical resistive memory array of claim 2. <Appendix 4> The rear side vertical resistive memory unit comprises: 4. The vertical resistance change memory array of claim 3, further comprising a fourth vertically stacked electrode group connected to a second side of the rear RRAM pillar, the fourth vertically stacked electrode group comprising a fourth upper SC electrode in contact with the second switching liner and a fourth lower SC electrode in contact with the second switching liner. <Appendix 5> 5. The vertical resistive memory array of claim 4, further comprising a first upper multi-cell (MC) electrode connected to the first upper SC electrode and connected to the third upper SC electrode. <Appendix 6> 6. The vertical resistive memory array of claim 5, further comprising a second upper MC electrode connected to the second upper SC electrode and connected to the fourth upper SC electrode. <Appendix 7> 7. The vertical resistive memory array of claim 6, comprising a first lower MC electrode connected to the first lower SC electrode and connected to the third lower SC electrode. <Appendix 8> 8. The vertical resistive memory array of claim 7, further comprising a second lower MC electrode connected to the second lower SC electrode and connected to the fourth lower SC electrode. <Appendix 9> 1. A method for a vertical resistive memory array, comprising: receiving, by the memory controller, from a requesting device, a read request to retrieve data stored in a single memory cell; applying a read potential to a vertical resistive memory unit including a plurality of ReRAM cells sharing the same pillar electrode by the memory controller; determining, by the memory controller, an equivalent resistance of the vertical resistive change memory unit; determining, by the memory controller, a resistance state of the vertical resistive change memory unit; and returning, by the memory controller, a data value associated with the determined resistance state of the vertical resistive change memory unit to the requesting device. <Appendix 10> 10. The method of claim 9, wherein the vertical resistance change memory unit further comprises a plurality of single cell (SC) electrodes and a switching liner contacting the outer periphery of a sidewall of the pillar electrode around the outer periphery of the sidewall. <Appendix 11> 11. The method of claim 10, wherein each of the plurality of SC electrodes has a pillar-facing sidewall in contact with the switching liner. <Appendix 12> applying the read potential to the vertical resistive memory unit applying a low or ground potential to the pillar electrodes by the memory controller; applying, by the memory controller, a read potential to each of the plurality of SC electrodes. <Appendix 13> sensing, by the memory controller, a current flowing through the vertical resistive memory unit caused by the read potential being applied to the vertical resistive memory unit; 13. The method of claim 12, further comprising: <Appendix 14> 14. The method of claim 13, wherein the equivalent resistance of the vertical resistance change memory unit is determined from the sensed current flowing through the vertical resistance change memory unit. <Appendix 15> 1. A method for a vertical resistive memory array, comprising: receiving, by the memory controller, from a requesting device, a read request to retrieve data stored in a single memory cell; applying a read potential to a vertical resistive memory unit including a plurality of ReRAM cells sharing the same pillar electrode by the memory controller; determining, by the memory controller, a resistance of each of the plurality of ReRAM cells in the vertical resistive memory unit; determining, by the memory controller, a combined resistance of each of the plurality of ReRAM cells in the vertical resistive memory unit; determining, by the memory controller, a resistance state of the vertical resistive change memory unit from the combined resistance; and returning, by the memory controller, a data value associated with the determined resistance state of the vertical resistive change memory unit to the requesting device. <Appendix 16> 16. The method of claim 15, wherein the vertical resistance change memory unit further comprises a plurality of single cell (SC) electrodes and a switching liner contacting the outer periphery of a sidewall of the pillar electrode around the outer periphery of the sidewall. <Appendix 17> 17. The method of claim 16, wherein each of the plurality of SC electrodes has a pillar-facing sidewall in contact with the switching liner. <Appendix 18> applying the read potential to the vertical resistive memory unit applying a low or ground potential to the pillar electrodes by the memory controller; applying, by the memory controller, a read potential to each of the plurality of SC electrodes. <Appendix 19> sensing, by the memory controller, a current flowing through each of the plurality of ReRAM cells in the vertical resistive memory unit caused by applying the read potential to the vertical resistive memory unit; 19. The method of claim 18, further comprising: <Appendix 20> 20. The method of claim 19, wherein the combined resistance of the vertical resistance change memory unit is determined from the sensed current flowing through each of the plurality of ReRAM cells in the vertical resistance change memory unit.

Claims

1. 1. A vertical resistive memory array, comprising: a front vertical resistive random access memory (RRAM) unit comprising a front vertical stacked electrode group connected to a first side of the front vertical RRAM pillar; the front RRAM pillar comprises a first pillar electrode and a first switching liner around and in contact with a sidewall periphery of the first pillar electrode; the first vertically stacked electrode group comprises: a first upper single cell (SC) electrode in contact with a first upper resistive element and in contact with the first switching liner, thereby contacting the front RRAM pillar; and a first lower SC electrode in contact with a first lower resistive element and in contact with the first switching liner, thereby contacting the front RRAM pillar. Vertical resistive memory array.

2. The front-side vertical resistive memory unit comprises:

2. The vertical resistance change memory array of claim 1, further comprising: a second group of vertically stacked electrodes connected to a second side of the front RRAM pillar, the second group of vertically stacked electrodes comprising: a second upper SC electrode in contact with a second upper resistive element and in contact with the front RRAM pillar by contacting the first switching liner; and a second lower SC electrode in contact with a second lower resistive element and in contact with the front RRAM pillar by contacting the first switching liner.

3. a rear vertical resistive memory unit comprising a rear RRAM pillar and a third vertically stacked electrode group connected to a first side of the rear RRAM pillar; the rear RRAM pillar comprises a second pillar electrode and a second switching liner around a sidewall periphery of the second pillar electrode; the third vertically stacked electrode group comprises: a third upper SC electrode in contact with a third upper resistive element and in contact with the second switching liner, thereby contacting the rear RRAM pillar; and a third lower SC electrode in contact with a third lower resistive element and in contact with the second switching liner, thereby contacting the rear RRAM pillar.

3. The vertical resistive memory array of claim 2.

4. The rear side vertical resistive memory unit comprises:

4. The vertical resistance change memory array of claim 3, further comprising: a fourth vertically stacked electrode group connected to a second side of the rear RRAM pillar, the fourth vertically stacked electrode group comprising: a fourth upper SC electrode in contact with a fourth upper resistive element and in contact with the rear RRAM pillar by contacting the second switching liner; and a fourth lower SC electrode in contact with a fourth lower resistive element and in contact with the rear RRAM pillar by contacting the second switching liner.

5. 5. The vertical resistive memory array of claim 4, further comprising a first upper multi-cell (MC) electrode connected to the first upper resistive element and connected to the third upper resistive element.

6. 6. The vertical resistive memory array of claim 5, further comprising a second upper MC electrode connected to said second upper resistive element and connected to said fourth upper resistive element.

7. 7. The vertical resistive memory array of claim 6, comprising a first lower MC electrode connected to said first lower resistive element and connected to said third lower resistive element.

8. 8. The vertical resistive memory array of claim 7, further comprising a second lower MC electrode connected to said second lower resistive element and connected to said fourth lower resistive element.

9. A vertical resistance change memory array as described in any one of claims 1 to 8, wherein the first upper resistive element, the first lower resistive element, or both have the form of serpentine wiring.

10. A vertical resistance change memory array as described in any one of claims 1 to 9, wherein the first upper SC electrode and the first lower SC electrode are physically or virtually connected.

11. A vertical resistance change memory array as described in any one of claims 1 to 10, configured so that a plurality of vertically aligned cells formed by the first vertically stacked electrode group are programmed, read, or reset, or a combination thereof, as a single group.

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