Display device

Abstract

To provide a display device capable of easily achieving high resolution.SOLUTION: A display device includes: a plurality of pixels that are provided on a substrate and contain light emitting elements, respectively; a first scanning line for applying an i-th scanning signal and a second canning line for applying an (i+1)-th scanning signal that are provided with each of the pixels; a data line for applying a data signal; a power source line for applying a drive power source; a reference voltage line for applying a reference voltage; a first transistor for controlling a current of the light emitting element; a second transistor connected between the data line and a first gate electrode of the first transistor and turned on by the i-th scanning signal; a third transistor connected between the reference voltage line and a first electrode of the first transistor and turned on by the (i+1)-th scanning signal; and a fourth transistor connected between the power supply line and a second electrode of the first transistor and turned off when a light emission control signal is supplied to a light emission control line. The fourth transistor is a different type from the first to the third transistors.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device including pixels. [Background technology]

[0002] 2. Description of the Related Art With the growing interest in information displays and the increasing demand for portable information media, the demand and commercialization of display devices is becoming increasingly intense.

[0003] In particular, as the demand for higher resolution in recent display devices increases, the pixel size is becoming smaller, while the structure of the circuit included in the pixel is becoming increasingly complex. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Publication No. 10-2018-0078476 [Patent Document 2] Korean Patent Publication No. 10-2018-0127882 [Patent Document 3] U.S. Patent No. 10,199,447 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can easily achieve high resolution. [Means for solving the problem]

[0006] a first transistor connected between the data line and a first gate electrode of the first transistor and turned on by the i-th scan signal; a third transistor connected between the reference voltage line and a first electrode of the first transistor and turned on by the i+1-th scan signal; and a fourth transistor connected between the power line and a second electrode of the first transistor and turned off when a light emission control signal is supplied to a light emission control line.

[0007] In one embodiment of the present invention, the fourth transistor may be a transistor of a different type from the first to third transistors.

[0008] In one embodiment of the present invention, the first to third transistors may be oxide transistors, and the fourth transistor may be a polysilicon transistor.

[0009] In one embodiment of the present invention, the display device may further include a buffer film and a gate insulating film provided in this order on the substrate, and first to fourth insulating films provided in this order on the gate insulating film.

[0010] In one embodiment of the present invention, the display device may include first to third conductive patterns provided on the first insulating film and spaced apart from one another, wherein the first conductive pattern may overlap the first transistor in a plan view, the second conductive pattern may overlap the second transistor in a plan view, and the third conductive pattern may overlap the third transistor in a plan view.

[0011] In one embodiment of the present invention, the first gate electrode of the first transistor, the second gate electrode of the second transistor, the third gate electrode of the third transistor, and the first and second scanning lines may be provided on the third insulating film, the fourth gate electrode of the fourth transistor may be provided on the gate insulating film, the gate electrode of the second transistor may be electrically connected to the second conductive pattern, and the gate electrode of the third transistor may be electrically connected to the third conductive pattern.

[0012] In an embodiment of the present invention, the first transistor may include a first active pattern disposed on the second insulating film, a first gate electrode disposed on the third insulating film, and the first electrode and the second electrode respectively contacting both ends of the first active pattern, wherein the first conductive pattern may be electrically connected to one of the first and second electrodes of the first transistor.

[0013] In an embodiment of the present invention, the display device may further include a storage capacitor including a lower electrode disposed on the first insulating film and an upper electrode overlapping the lower electrode with the second and third insulating films interposed therebetween, wherein the lower electrode may be integral with the first conductive pattern, and the upper electrode may be integral with the first gate electrode.

[0014] In an embodiment of the present invention, the display device may further include an opening between the first gate electrode of the first transistor and the first conductive pattern, where a portion of the third insulating film is removed to expose a portion of the second insulating film, and the opening may overlap the first gate electrode of the first transistor and the first conductive pattern in a plan view.

[0015] In one embodiment of the present invention, the reference voltage line, the data line, and the power supply line may be provided on the fourth insulating film.

[0016] In one embodiment of the present invention, the display device may further include a connection wiring provided on the fourth insulating film, the connection wiring electrically connecting the third transistor and the light emitting element.

[0017] In one embodiment of the present invention, the display device may further include a protective film provided on the connection wiring, wherein the light-emitting element may include a first electrode provided on the protective film and electrically connected to the connection wiring via a contact hole penetrating the protective film, a light-emitting layer provided on the first electrode, and a second electrode provided on the light-emitting layer. [Effects of the Invention]

[0018] According to one embodiment of the present invention, a display device capable of achieving high resolution can be provided by securing an overlapping area between a first electrode and a second electrode sandwiching an insulating layer, thereby securing the capacitance of a storage capacitor.

[0019] In addition, according to one embodiment of the present invention, a shielding member is disposed between a data line transmitting a data signal and a driving transistor, thereby minimizing parasitic capacitance between the data line and the driving transistor, thereby providing a display device that minimizes signal changes in the driving transistor due to changes in the data signal and the resulting vertical crosstalk.

[0020] The effects of the embodiments of the present invention are not limited to those described above, and various other effects are included within the present specification. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a plan view showing a display device according to an embodiment of the present invention; [Figure 2] 2 is a block diagram showing an embodiment of a pixel and a driving unit in the display device of FIG. 1. FIG. [Figure 3] 3 is a circuit diagram showing the electrical connection relationship of components included in one of the pixels shown in FIG. 2 based on one embodiment. [Figure 4] FIG. 3 is a plan view schematically showing one pixel shown in FIG. 2. [Figure 5] FIG. 5 is a cross-sectional view taken along line AA' in FIG. [Figure 6] FIG. 5 is a cross-sectional view taken along line BB' in FIG. [Figure 7] FIG. 10 is a plan view schematically illustrating one pixel according to another embodiment of the present invention. [Figure 8] FIG. 10 is a plan view schematically illustrating a pixel according to yet another embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view taken along line CC' in FIG. 8. [Figure 10] FIG. 9 is a cross-sectional view taken along the line DD' in FIG. [Figure 11] FIG. 10 is a plan view schematically illustrating a pixel according to yet another embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view taken along the line EE' in FIG. [Figure 13] FIG. 12 is a cross-sectional view taken along the line FF' in FIG. [Figure 14] FIG. 10 is a plan view schematically illustrating a pixel according to yet another embodiment of the present invention. [Figure 15] FIG. 15 is a cross-sectional view taken along line GG' in FIG. [Figure 16] FIG. 15 is a cross-sectional view taken along line HH' in FIG. [Figure 17] FIG. 10 is a plan view schematically illustrating a pixel according to yet another embodiment of the present invention. [Figure 18] FIG. 10 is a plan view schematically illustrating a pixel according to yet another embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view taken along line II' in FIG. [Figure 20] FIG. 19 is a cross-sectional view taken along the line JJ' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0022] Because the present invention can be modified in various ways and can take various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it should be understood that this is not to limit the invention to the particular forms disclosed, and that the invention includes all modifications, equivalents, and alternatives falling within the spirit and technical scope of the invention.

[0023] In describing each drawing, like reference numerals are used for like elements. Dimensions of structures in the accompanying drawings have been exaggerated for clarity. Terms such as "first," "second," etc. are used to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a "second element," and similarly, a second element may be referred to as a "first element," without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0024] In this application, the use of terms such as "comprises" or "has" indicates the presence of a specified feature, numeral, step, operation, component, part, or combination thereof, but does not preclude the presence or addition of one or more other features, numerals, steps, operations, components, parts, or combinations thereof. Furthermore, when a layer, film, region, plate, or other part is referred to as being "on" another part, it includes not only the case where it is "directly on" the other part, but also the case where there is another part between them. Furthermore, when a layer, film, region, plate, or other part is referred to as being formed on another part, the direction of formation is not limited to the top direction, but also includes the case where it is formed on the side or bottom direction. Conversely, when a layer, film, region, plate, or other part is referred to as being "under" another part, it includes not only the case where it is "directly under" the other part, but also the case where there is another part between them.

[0025] Hereinafter, preferred embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the singular expression also includes the plural expression unless the context clearly indicates the singular expression only.

[0026] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention.

[0027] Referring to FIG. 1, a display device according to one embodiment of the present invention may include a substrate SUB, pixels PXL provided on the substrate SUB, a driving unit provided on the substrate SUB for driving the pixels PXL, and a wiring unit (not shown) for connecting the pixels PXL and the driving unit.

[0028] The substrate SUB may include a display area DA and a non-display area NDA.

[0029] The display area DA may be an area where pixels PXL that display video are provided. Each pixel PXL will be described later.

[0030] The non-display area NDA may be an area where a driver for driving the pixels PXL and part of the wiring (not shown) connecting the pixels PXL and the driver are provided.

[0031] The display area DA may have various shapes. For example, the display area DA may be formed in various shapes, such as a closed polygon with straight sides, a circle or ellipse with curved sides, a semicircle or semi-ellipse with straight and curved sides, etc. When the display area DA includes multiple regions, each region may also be formed in various shapes, such as a closed polygon with straight sides, a semicircle or semi-ellipse with curved sides, etc. In one embodiment of the present invention, a case where the display area DA is formed as one quadrilateral region with straight sides will be described.

[0032] The non-display area NDA may be provided on at least one side of the display area DA, for example, the non-display area NDA may surround the periphery of the display area DA.

[0033] The pixels PXL are provided in a display area DA on a substrate SUB and may be connected to wiring. Each pixel PXL is the minimum unit for displaying an image, and a plurality of pixels PXL may be provided.

[0034] The pixel PXL may include a light-emitting element (not shown) that emits white light and / or colored light, and a pixel circuit for driving the light-emitting element. The pixel circuit may include at least one transistor connected to the light-emitting element. Each pixel PXL may emit one of red, green, and blue colors, although the present invention is not limited thereto. Each pixel PXL may also emit one of cyan, magenta, yellow, and white colors.

[0035] A plurality of pixels PXL may be provided and may be arranged along rows extending in a first direction DR1 and columns extending in a second direction DR2 intersecting the first direction DR1. The arrangement of the pixels PXL is not particularly limited, and they may be arranged in various shapes.

[0036] The driving unit provides signals to each pixel PXL via the wiring unit, thereby controlling the driving of each pixel PXL. For convenience of explanation, the wiring unit is omitted from Figure 1, and the wiring unit will be described later.

[0037] The driver may include a scan driver SDV for transmitting scan signals to the pixels PXL via scan lines, a light emitting driver EDV for transmitting light emitting control signals to the pixels PXL via light emitting control lines, a data driver DDV for transmitting data signals to the pixels PXL via data lines, and a timing controller (not shown). The timing controller can control the scan driver SDV, the light emitting driver EDV, and the data driver DDV.

[0038] In one embodiment of the present invention, the scan driver SDV, the light emitting driver EDV, and the data driver DDV may be disposed in the non-display area NDA of the substrate SUB, and the positions of the scan driver SDV, the light emitting driver EDV, and / or the data driver DDV may be changed as needed.

[0039] FIG. 2 is a block diagram showing an embodiment of the pixel and the driver in the display device of FIG.

[0040] 1 and 2, a display device according to an embodiment of the present invention may include a pixel PXL, a driving unit, and a wiring unit.

[0041] The driver may include a scan driver SDV, a light emitting driver EDV, a data driver DDV, and a timing controller TC.

[0042] In FIG. 2, the positions of the scan driver SDV, light emitting driver EDV, data driver DDV, and timing controller TC are set for the convenience of explanation, and may be arranged at other positions within the display device when the display device is actually realized.

[0043] The pixel PXL may include a light-emitting element (not shown) that emits light and a pixel circuit (not shown) for driving the light-emitting element. The pixel circuit may include at least one transistor for driving the light-emitting element. Each pixel PXL can compensate for changes in the electrical characteristics of the corresponding pixel PXL in real time using the pixel circuit.

[0044] The wiring unit may include data lines DL1 to DLm arranged in the display area DA and applying data voltages (or data signals) from the driver to the pixels PXL, scan lines S1 to Sn applying scan signals to the pixels PXL, emission control lines E1 to En applying emission control signals to the pixels PXL, and a reference voltage line (not shown) used to sense the electrical characteristics of the pixels PXL. Depending on the embodiment, two or more scan signals may be applied to each pixel PXL.

[0045] The pixels PXL may be provided in the display area DA. Each pixel PXL may receive a data signal from a corresponding data line when a scan signal is supplied from the corresponding scan line. Each pixel PXL receiving the data signal may control the amount of current flowing from the first drive power supply ELVDD applied via the power supply line PL to the second drive power supply ELVSS via the light emitting element (not shown). Each pixel PXL may be connected to a reference voltage line (not shown), and an initialization power supply Vint (or a reference voltage) may be applied to each pixel PXL via the reference voltage line. The reference voltage line will be described later with reference to FIG. 3.

[0046] The scan driver SDV can apply scan signals to the scan lines S1 to Sn in response to a first gate signal GCS1 from the timing controller TC. For example, when the scan signals are sequentially supplied to the scan lines S1 to Sn, the scan driver SDV can sequentially select the pixels PXL in units of horizontal lines.

[0047] The light emitting driver EDV can apply a light emitting control signal to the light emitting control lines E1 to En in response to the second gate signal GCS2 from the timing controller TC. For example, the light emitting driver EDV can supply the light emitting control signal to the light emitting control lines E1 to En in sequence.

[0048] The light emission control signal may be set to have a wider pulse width than the scanning signal. For example, the light emission control signal supplied to the i-th (i: natural number) light emission control line Ei may be supplied so as to overlap at least partially with the scanning signal supplied to the (i-1)-th scanning line Si-1 and the scanning signal supplied to the i-th scanning line Si.

[0049] Furthermore, the light emitting control signal may be set to an off voltage (e.g., a high voltage) so that the transistor included in the pixel PXL is turned off, and the scan signal may be set to a gate on voltage (e.g., a low voltage) so that the transistor included in the pixel PXL is turned on.

[0050] The data driver DDV can supply data signals to the data lines DL1 to DLm in response to the data control signal DCS. The data signals supplied to the data lines DL1 to DLm can be supplied to the pixels PXL selected by the scan signal.

[0051] The timing control unit TC supplies gate control signals GCS1 and GCS2 generated based on a timing signal supplied from the outside to the scan driver SDV and the light emitting driver EDV, respectively, and can supply a data control signal DCS to the data driver DDV.

[0052] Each of the gate control signals GCS1 and GCS2 may include a start pulse and a clock signal. The start pulse controls the timing of the first scan signal or the first light emission control signal. The clock signal is used to shift the start pulse.

[0053] The data control signal DCS includes a source start pulse and a clock signal, where the source start pulse controls the point in time when data sampling starts, and the clock signal controls the sampling operation.

[0054] In a sensing mode for measuring deviations in the electrical characteristics of each pixel PXL before shipment of the product or while the product is in operation, the data voltage (or data signal) is generated by converting test data received from a grayscale-luminance measurement system (not shown) to generate a sensing data voltage (or data signal), and the sensing data voltage is supplied to the sensing target pixel PXL via the data lines DL1 to DLm. The grayscale-luminance measurement system senses the electrical characteristics of each pixel PXL, and based on the sensing results, derives a compensation value (offset) for the pixel PXL that compensates for deviations in the electrical characteristics between the pixels PXL, particularly deviations in the threshold voltages of the drive transistors, and stores the compensation value for the pixel PXL in a memory (not shown) or updates an already stored value.

[0055] The gray-scale-luminance measurement system used in the sensing mode may be electrically connected to the memory during operation in the sensing mode.

[0056] In a normal drive mode, when power is applied to the display device, the compensation value from the memory is loaded into the internal compensation memory of the data driver DDV. The data driver DDV may include a sensing unit (not shown). The sensing unit may be configured to sense each electrical characteristic of the pixel PXL, for example, the threshold voltage of the driving transistor, during an aging process before product shipment and transmit the sensed electrical characteristic to a grayscale-luminance measurement system. For example, in the case of an application, the sensing unit may sense each electrical characteristic of the pixel PXL in a normal drive mode after product shipment and update the compensation value in real time. However, this is not limited to the application.

[0057] In one embodiment of the present invention, each pixel PXL can compensate for the threshold voltage of the driving element using an external compensation method. The pixel PXL can compensate for only the electron mobility and temperature deviation of the driving element using an internal compensation method. The pixel PXL can compensate for the electron mobility and temperature deviation of the driving element in real time using the internal compensation method without sampling the threshold voltage of the driving element and compensating for the threshold voltage. Therefore, the present invention can be advantageously applied to applications requiring high-speed driving at a frame rate of 120 Hz or more.

[0058] FIG. 3 is a circuit diagram illustrating the electrical connections of components included in one of the pixels shown in FIG. 2 according to one embodiment.

[0059] In FIG. 3, not only the components included in each pixel shown in FIG. 2 but also the area in which the components are provided are collectively referred to as pixel PXL.

[0060] Referring to FIGS. 1 to 3, each pixel PXL may include a light emitting element OLED and a pixel circuit PXC electrically connected to the light emitting element OLED to drive the light emitting element OLED.

[0061] The anode of the light emitting element OLED may be connected to the pixel circuit PXC. The light emitting element OLED generates light of a predetermined brightness corresponding to the amount of current supplied from the pixel circuit PXC. To this end, during a driving period of the display device, the second driving power source ELVSS may be set to a voltage lower than the first driving power source ELVDD.

[0062] The pixel circuit PXC can control the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via the light emitting element OLED in response to a data signal (or data voltage). To this end, the pixel circuit PXC may include first to fourth transistors T1 to T4 and a storage capacitor Cst.

[0063] One electrode of the first transistor T1 (driving transistor) may be connected to a power line PL to which the first driving power source ELVDD is applied via the fourth transistor T4, and the other electrode may be connected to a second node N2. The first transistor T1 controls the amount of current flowing from the first driving power source ELVDD to the second driving power source ELVSS via the light-emitting element OLED in response to the voltage of the first node N1, which is its gate electrode.

[0064] In an embodiment of the present invention, the first transistor T1 may be an oxide transistor. An oxide transistor refers to a transistor including an oxide semiconductor as a semiconductor forming the transistor. For example, the first transistor T1 may be implemented as an NMOS including an oxide semiconductor with a low off-current. Specific oxide semiconductors will be described later. Here, the off-current refers to a leakage current that flows between one electrode and the other electrode of a transistor when the transistor is in an off-state. A thin film transistor with a low off-current has a low leakage current even when the off-state is prolonged, thereby minimizing a change in luminance of the pixel PXL when the pixel PXL is driven at a low speed. The other electrode of the first transistor T1 may be electrically connected to a first conductive pattern made of a conductive material. Here, the first conductive pattern may be disposed below the first transistor T1 and may partially overlap the first transistor T1.

[0065] The second transistor T2 (switching transistor) may be connected to the gate electrode of the first transistor T1 via a j-th data line DLj connected to each pixel PXL and a first node N1. The gate electrode of the second transistor T2 may be connected to an i-th scan line Si connected to the corresponding pixel PXL. The second transistor T2 is turned on by an i-th scan signal applied to the i-th scan line Si to supply the data voltage transmitted from the j-th data line DLj to the first node N1. The second transistor T2 may include one electrode connected to the j-th data line DLj and another electrode connected to the first node N1.

[0066] In one embodiment of the present invention, the second transistor T2 may be an oxide transistor. For example, the second transistor T2 may be realized as an NMOS including an oxide semiconductor with a low off-state current. The gate electrode of the second transistor T2 may be connected to a second conductive pattern made of a conductive material. Here, the second conductive pattern may be disposed below the second transistor T2 and may partially overlap with the second transistor T2.

[0067] In a display device according to an embodiment of the present invention, the frame rate can be lowered to reduce power consumption when a still image is displayed, and the pixels PXL can be driven at a low speed. In this case, the data update period becomes longer, which may cause leakage current in each pixel PXL, resulting in flicker. When the brightness of the pixels PXL fluctuates periodically, the user may perceive the flicker. Therefore, if the second transistor T2, which has a long off period, is implemented as an NMOS including an oxide semiconductor with a low off current, the leakage current can be reduced during low-speed driving, thereby minimizing the flicker phenomenon.

[0068] The third transistor T3 (sensing transistor) may be connected between the first transistor T1 and a j-th reference voltage line RFj to which a reference voltage Vref is applied. For example, one electrode of the third transistor T3 may be connected to the j-th reference voltage line RFj, and the other electrode of the third transistor T3 may be connected to the other electrode of the first transistor T1 via the second node N2.

[0069] A gate electrode of the third transistor T3 may be connected to the (i+1)th scan line Si+1 connected to the corresponding pixel PXL. Here, the reference voltage Vref may be a voltage lower than the first driving power supply ELVDD and / or the data voltage, for example, the voltage of the initialization power supply Vint. The third transistor T3 is turned on by the (i+1)th scan signal supplied to the (i+1)th scan line Si+1 during a predetermined sensing period to electrically connect the jth reference voltage line RFj and the first transistor T1.

[0070] The third transistor T3 may operate to supply the reference voltage Vref (or the initialization power supply Vint) transmitted through the jth reference voltage line RFj to the second node N2, or to sense the voltage or current of the second node N2 or the jth reference voltage line RFj.

[0071] In one embodiment of the present invention, the third transistor T3 may be an oxide transistor. For example, the third transistor T3 may be realized as an NMOS including an oxide semiconductor with a low off-state current. The gate electrode of the third transistor T3 may be connected to a third conductive pattern made of a conductive material. Here, the third conductive pattern may be disposed below the third transistor T3 and may partially overlap with the third transistor T3.

[0072] Depending on the embodiment, the sensing period may be a period during which characteristic information (e.g., the threshold voltage of the first transistor T1) of each pixel PXL arranged in the display area DA is extracted. During the sensing period, the first transistor T1 can be turned on by supplying a predetermined reference voltage that turns on the first transistor T1 to the first node N1 via the jth data line DLj and the second transistor T2, or by connecting each pixel PXL to a current source. Also, the first transistor T1 can be connected to the jth reference voltage line RFj by supplying the (i+1)th scan signal to the third transistor T3 to turn on the third transistor T3. Thus, characteristic information of each pixel PXL, including the threshold voltage of the first transistor T1, can be extracted via the jth reference voltage line RFj and transmitted to a sensing unit of the data driver DDV. The characteristic information extracted via the jth reference voltage line RFj may be used to convert image data so that characteristic deviations between the pixels PXL are compensated for.

[0073] The first to third conductive patterns will be described in detail later with reference to FIG.

[0074] The fourth transistor T4 is connected between the power line PL and the first transistor T1 and can switch the current path between the power line PL and the first transistor T1 in response to an emission control signal. The gate electrode of the fourth transistor T4 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. One electrode of the fourth transistor T4 may be connected to one electrode of the first transistor T1, and the other electrode of the fourth transistor T4 may be connected to the power line PL. The fourth transistor T4 is turned off when an emission control signal of a gate-off voltage is supplied to the i-th emission control line Ei, and is turned on otherwise. In one embodiment of the present invention, the fourth transistor T4 may be a polysilicon transistor. A polysilicon transistor refers to a transistor that includes polysilicon as a semiconductor forming the transistor. For example, the fourth transistor T4 may be implemented as a PMOS including a polysilicon semiconductor.

[0075] The storage capacitor Cst stores a data voltage and may be connected between the first node N1 and the second node N2.

[0076] The pixel circuit PXC described above can compensate for the threshold voltage of the first transistor T1, which is the driving transistor, using an external compensation method, and can compensate for the element characteristics of the first transistor T1, such as electron mobility or temperature deviation, in real time every frame period using an internal compensation method.

[0077] 4 is a plan view schematically showing one pixel shown in FIG. 2, FIG. 5 is a cross-sectional view taken along line A-A' in FIG. 4, and FIG. 6 is a cross-sectional view taken along line B-B' in FIG. 4.

[0078] For convenience, the light emitting elements connected to the first and third transistors T1 and T3 are omitted from FIG.

[0079] Figures 4 to 6 show, based on one pixel PXL arranged in the i-th pixel row and j-th pixel column in the display area DA, the scanning lines Si, Si+1, the i-th light-emitting control line Ei, the j-th reference voltage line RFj, the j-th data line DLj, and the power supply line PL connected to the pixel PXL.

[0080] For ease of explanation, the scanning line of the i-th row will be referred to as the "first scanning line Si," the scanning line of the i+1-th row will be referred to as the "second scanning line Si+1," the i-th light-emitting control line Ei will be referred to as the "light-emitting control line Ei," the j-th data line DLj will be referred to as the "data line DLj," and the j-th reference voltage line RFj will be referred to as the "reference voltage line RFj."

[0081] Furthermore, in Figures 4 to 6, the structure of the pixel PXL is illustrated in a simplified manner, such as showing each electrode as a single electrode layer and each insulating layer as a single insulating layer, but the present invention is not limited to this.

[0082] Additionally, in one embodiment of the present invention, a "connection" between two components can refer to both an electrical connection and a physical connection.

[0083] 1 to 6, a display device according to an embodiment of the present invention may include a substrate SUB, a wiring portion, and a pixel PXL.

[0084] The substrate SUB may be made of a material that can transmit light, including a transparent insulating material, and may be a rigid substrate or a flexible substrate.

[0085] Rigid substrates may include, for example, glass substrates, quartz substrates, glass-ceramic substrates, and crystalline glass substrates.

[0086] The flexible substrate may include a film substrate and a plastic substrate including a polymeric organic material, for example, polyethersulfone (PES), polyacrylate (PEI), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), triacetate cellulose (TAC), and cellulose acetate propionate (CAP).

[0087] It is desirable that the material applied to the substrate SUB be resistant (or heat-resistant) to high processing temperatures during the manufacturing process of the display device. In one embodiment of the present invention, the substrate SUB may be entirely or at least partially flexible.

[0088] A plurality of insulating films and a plurality of conductive layers may be disposed on the substrate SUB.

[0089] In one embodiment of the present invention, the insulating film may include, for example, a buffer film BFL, a first gate insulating film GI1, first and second interlayer insulating films ILD1 and ILD2, a second gate insulating film GI2, a third interlayer insulating film ILD3, and a protective film PSV, which are stacked in this order on a substrate SUB.

[0090] A conductive layer may be provided and / or formed between the above-mentioned insulating films. In one embodiment of the present invention, the conductive layer may include, for example, a first conductive layer provided on the first gate insulating film GI1, a second conductive layer provided on the first interlayer insulating film ILD1, a third conductive layer provided on the second gate insulating film GI2, and a fourth conductive layer provided on the third interlayer insulating film ILD3.

[0091] Each of the pixels PXL may be provided in a pixel area PXA included in the display area DA of the substrate SUB.

[0092] The pixels PXL may be arranged in a matrix and / or stripe pattern in the display area DA on the substrate SUB by a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 intersecting the pixel rows, but the present invention is not limited thereto. Depending on the embodiment, the pixels PXL may be arranged in the display area DA on the substrate SUB in various currently known arrangement patterns.

[0093] The wiring section provides signals to each of the pixels PXL provided in the display area DA, and may include scanning lines Si, Si+1, data lines DLj, light emission control lines Ei, power supply lines PL, and reference voltage lines RFj.

[0094] The scan lines Si and Si+1 may extend in a first direction DR1 and may include a first scan line Si and a second scan line Si+1 arranged in sequence along a second direction DR2 intersecting the first direction DR1.

[0095] A corresponding scan signal may be applied to each of the scan lines Si and Si+1. For example, the i-th scan signal may be applied to the first scan line Si, and the i+1-th scan signal may be applied to the second scan line Si+1. In one embodiment of the present invention, the scan lines Si and Si+1 may be provided and / or formed on the second gate insulating film GI2. The scan lines Si and Si+1 may be a third conductive layer provided on the second gate insulating film GI2.

[0096] Here, the second gate insulating film GI2 may be an inorganic insulating film containing an inorganic material. For example, the second gate insulating film GI2 may include at least one of metal oxides such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx). The second gate insulating film GI2 may be formed as a single film or as a multi-film structure of at least two or more layers. When the second gate insulating film GI2 is formed as a multi-film structure, each layer may be formed of the same material or different materials. The second gate insulating film GI2 may be made of silicon oxide (SiOx) and have a thickness of about 20 nm to 300 nm. For example, the second gate insulating film GI2 may be made of silicon oxide (SiOx) with a thickness of about 140 nm. However, the present invention is not limited thereto. Depending on the embodiment, the second gate insulating film GI2 may be an organic insulating film containing an organic material.

[0097] The light-emitting control line Ei may extend in the first direction DR1 and be provided in each pixel PXL. A light-emitting control signal may be applied to the light-emitting control line Ei. The light-emitting control line Ei may be provided in a layer different from the scan lines Si and Si+1 and may be provided and / or formed on the first gate insulating film GI1. The light-emitting control line Ei may be a first conductive layer provided on the first gate insulating film GI1.

[0098] The first gate insulating film GI1 may be made of an inorganic insulating film containing an inorganic material. The first gate insulating film GI1 may contain the same material as the second gate insulating film GI2, but the present invention is not limited to this. For example, the first gate insulating film GI1 may be made of silicon oxide (SiOx) and have a thickness of about 20 nm to 300 nm. For example, the first gate insulating film GI1 may be made of silicon oxide (SiOx) with a thickness of about 120 nm.

[0099] The data line DLj may extend in the second direction DR2. A data voltage (or a data signal) may be applied to the data line DLj. In an embodiment of the present invention, the data line DLj may be disposed and / or formed on a third interlayer insulating film ILD3. The data line DLj may be a fourth conductive layer disposed on the third interlayer insulating film ILD3.

[0100] The third interlayer insulating film ILD3 may be an inorganic insulating film containing an inorganic material. The third interlayer insulating film ILD3 may be formed of a single film or multiple films. For example, the third interlayer insulating film ILD3 may be formed of multiple films including first and second sub-interlayer insulating films ILD3_1 and ILD3_2 stacked in sequence. The first sub-interlayer insulating film ILD3_1 may be made of silicon oxide (SiOx) and have a thickness of about 20 nm to 300 nm. For example, the first sub-interlayer insulating film ILD3_1 may be made of silicon oxide (SiOx) and have a thickness of about 300 nm. The second sub-interlayer insulating film ILD3_2 may be made of silicon oxide (SiOx) and have a thickness of about 20 nm to 300 nm. For example, the second sub-interlayer insulating film ILD3_2 may be made of silicon oxide (SiOx) and have a thickness of about 200 nm. However, the present invention is not limited thereto. Depending on the embodiment, the third interlayer insulating film ILD3 may be made of a single film, such as an organic insulating film containing an organic material.

[0101] The reference voltage line RFj may extend along the second direction DR2 and be spaced apart from the data line DLj. A reference voltage Vref may be applied to the reference voltage line RFj. The reference voltage line RFj may be disposed in the same layer as the data line DLj and may include the same material as the data line DLj. In an embodiment of the present invention, the reference voltage line RFj may be disposed and / or formed on a third interlayer insulating film ILD3. The reference voltage line RFj may be a fourth conductive layer disposed on the third interlayer insulating film ILD3.

[0102] The power lines PL may extend in the second direction DR2 and be spaced apart from the data lines DLj. In plan view, pixel circuits PXC may be arranged between the power lines PL and the data lines DLj. One of first and second driving power sources ELVDD and ELVSS, for example, the first driving power source ELVDD, may be applied to the power lines PL.

[0103] In a plan view, the reference voltage line RFj, the data line DLj, and the power supply line PL may be arranged in this order along the first direction DR1 and spaced apart from one another. For example, the reference voltage line RFj may be arranged on one side of the data line DLj, and the power supply line PL may be arranged on the other side. In one embodiment of the present invention, the data line DLj may be arranged closer to the reference voltage line RFj than the power supply line PL on the third interlayer insulating film ILD3.

[0104] Each of the pixels PXL may include a pixel circuit layer PCL having a pixel circuit PXC and a display element layer DPL having a light-emitting element OLED that emits light.

[0105] For convenience, the pixel circuit layer PCL will be described first, and then the display element layer DPL will be described.

[0106] The pixel circuit layer PCL may include a buffer film BFL provided on the substrate SUB, a pixel circuit PXC provided on the buffer film BFL, and a protective film PSV provided on the pixel circuit PXC.

[0107] The buffer layer BFL is disposed on the substrate SUB and can prevent impurities from diffusing into the pixel circuit PXC. The buffer layer BFL may include an inorganic insulating film containing an inorganic material. For example, the buffer layer BFL may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and metal oxide such as aluminum oxide (AlOx). The buffer layer BFL may be formed as a single layer or as a multi-layer structure, i.e., at least two layers. When the buffer layer BFL is formed as a multi-layer structure, each layer may be formed of the same material or different materials. For example, the buffer layer BFL may be formed as a double layer structure including a first layer made of silicon nitride (SiNx) and having a thickness of about 50 nm to 140 nm, and a second layer made of silicon oxide (SiOx) and having a thickness of about 20 nm to 300 nm. However, the present invention is not limited thereto, and the buffer layer BFL may be omitted depending on the material and process conditions of the substrate SUB.

[0108] The pixel circuit PXC may include first to fourth transistors T1 to T4 and a storage capacitor Cst provided on the buffer film BFL.

[0109] The first transistor T1 (drive transistor) may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1.

[0110] The first gate electrode GE1 may be connected to the second source region SE2 of the second transistor T2 via a fourth connection wiring CNL4. The first gate electrode GE1 may be provided and / or formed on the second gate insulating film GI2. In one embodiment of the present invention, the first gate electrode GE1 may be a third conductive layer provided on the second gate insulating film GI2, and may be provided in the same layer as the first and second scan lines Si, Si+1 and may include the same material.

[0111] The fourth connection line CNL4 may be a fourth conductive layer provided and / or formed on the third interlayer insulating film ILD3. The fourth connection line CNL4 may be provided in the same layer as the reference voltage line RFj, the data line DLj, and the power supply line PL and may include the same material.

[0112] One end of the fourth connection line CNL4 may be connected to the first gate electrode GE1 via a first contact hole CH1 that penetrates the third interlayer insulating film ILD3, and the other end of the fourth connection line CNL4 may be connected to the second source region SE2 of the second transistor T2 via a second contact hole CH2 that penetrates the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order.

[0113] The first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. For example, the first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be formed of an oxide semiconductor. The first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be made of an oxide semiconductor with a thickness of about 30 nm to 60 nm, but the present invention is not limited to this.Here, oxide semiconductors include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), and composite oxides thereof such as indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (Zn-In-O), zinc-tin oxide (Zn-Sn-O), and indium-gallium-zinc oxide (InGaZnO4). Indium-gallium oxide (In-Ga-O), indium-tin oxide (In-Sn-O), indium-zirconium oxide (In-Zr-O), indium-zirconium-zinc oxide (In-Zr-Zn-O), indium-zirconium-tin oxide (In-Zr-Sn-O), indium-zirconium-gallium oxide (In-Zr-Ga-O), indium-aluminum oxide (In-Al-O), indium-zinc-aluminum oxide (In-Zn-Al-O), indium-tin-aluminum oxide (In-Sn-Al-O), indium-aluminum-gallium oxide (In-Al-Ga-O), indium-tantalum oxide (In-Ta-O), indium-tantalum-zinc oxide (In-Ta-Zn-O), indium-tantalum-tin oxide (In-Ta-Sn-O), indium-tantalum-gallium oxide (In-Ta-Ga-O ), indium-germanium oxide (In-Ge-O), indium-germanium-zinc oxide (In-Ge-Zn-O), indium-germanium-tin oxide (In-Ge-Sn-O), indium-germanium-gallium oxide (In-Ge-Ga-O), titanium-indium-zinc oxide (Ti-In-Zn-O), and hafnium-indium-zinc oxide (Hf-In-Zn-O).

[0114] When the first active pattern ACT1, the first source region SE1, and the first drain region DE1 are made of an oxide semiconductor material, a separate protective layer may be added to protect the oxide semiconductor, which is vulnerable to external environments such as high temperatures. The first active pattern ACT1, the first source region SE1, and the first drain region DE1 may be formed on a second interlayer insulating film ILD2.

[0115] The first active pattern ACT1 may be a region overlapping with the first gate electrode GE1 and may be a channel region of the first transistor T1. If the first active pattern ACT1 is formed long, the channel region of the first transistor T1 may also be formed long. In this case, the driving range of the gate voltage (or gate signal) applied to the first transistor T1 is widened. This allows for precise control of the gray scale of the light (or light) emitted from the light emitting element OLED.

[0116] The first source region SE1 may be connected to one end of the first active pattern ACT1 and to the third source region SE3 of the third transistor T3.

[0117] The first drain region DE1 may be connected to the other end of the first active pattern ACT1 and may be connected to the fourth drain region DE4 of the fourth transistor T4 via a fifth connection line CNL5.

[0118] The above-mentioned first active pattern ACT1, first source region SE1, and first drain region DE1 may be provided and / or formed on the second interlayer insulating film ILD2.

[0119] The second interlayer insulating film ILD2 may be an inorganic insulating film containing an inorganic material. For example, the second interlayer insulating film ILD2 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and metal oxide, such as aluminum oxide (AlOx). The second interlayer insulating film ILD2 may be formed as a single film or as a multi-layer film, such as at least two layers. In one embodiment of the present invention, the second interlayer insulating film ILD2 may be formed as a single film of silicon oxide (SiOx) with a thickness of about 20 nm to 300 nm. For example, the second interlayer insulating film ILD2 may be formed as a single film of silicon oxide (SiOx) with a thickness of about 300 nm. However, the present invention is not limited thereto. Depending on the embodiment, the second interlayer insulating film ILD2 may be formed as an organic insulating film containing an organic material or as a multi-layer film, such as at least two layers.

[0120] One end of the fifth connection wiring CNL5 may be connected to the fourth drain region DE4 of the fourth transistor T4 via a tenth contact hole CH10 that passes through the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in that order, and the other end of the fifth connection wiring CNL5 may be connected to the first drain region DE1 of the first transistor T1 via an eleventh contact hole CH11 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in that order.

[0121] A first conductive pattern BML1 may be disposed between the above-described first transistor T1 and the substrate SUB. The first conductive pattern BML1 may overlap the first transistor T1 when viewed in a plan view. In one embodiment of the present invention, the first conductive pattern BML1 may be provided and / or formed on the first interlayer insulating film ILD1. The first conductive pattern BML1 may be a second conductive layer provided on the first interlayer insulating film ILD1.

[0122] In one embodiment of the present invention, the first interlayer insulating film ILD1 may be an inorganic insulating film containing an inorganic material. For example, the first interlayer insulating film ILD1 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and metal oxide such as aluminum oxide (AlOx). The first interlayer insulating film ILD1 may be formed as a single film or as a multi-film structure, such as at least two or more films. The first interlayer insulating film ILD1 may be formed as a single film of silicon nitride (SiNx) with a thickness of about 50 nm to 140 nm. For example, the first interlayer insulating film ILD1 may be formed of silicon nitride (SiNx) with a thickness of about 140 nm, but the present invention is not limited thereto.

[0123] The first conductive pattern BML1 may be connected to the first connection line CNL1 via a thirteenth contact hole CH13 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order.

[0124] The first connection wiring CNL1 may be disposed and / or formed on the third interlayer insulating film ILD3 and overlap the first transistor T1 and the first conductive pattern BML1. In an embodiment of the present invention, the first connection wiring CNL1 may be a fourth conductive layer disposed on the third interlayer insulating film ILD3. The first connection wiring CNL1 may be disposed in the same layer as the reference voltage line RFj, the data line DLj, the power supply line PL, etc. and may include the same material. The first connection wiring CNL1 may be connected to the first source region SE1 of the first transistor T1 via a twelfth contact hole CH12 that sequentially penetrates the second gate insulating film GI2 and the third interlayer insulating film ILD3.

[0125] In one embodiment of the present invention, the first connection line CNL1 may be connected to the first source region SE1 of the first transistor T1 through the twelfth contact hole CH12 and to the first conductive pattern BML1 through the thirteenth contact hole CH13. As a result, the first source region SE1 of the first transistor T1 can be connected to the first conductive pattern BML1 through the first connection line CNL1.

[0126] As described above, when the first conductive pattern BML1 is connected to the first source region SE1 of the first transistor T1, a margin of the swing width of the second driving power supply ELVSS can be secured, and in this case, the driving range of the gate voltage applied to the first gate electrode GE1 of the first transistor T1 can be widened.

[0127] The second transistor T2 (switching transistor) may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2.

[0128] The second gate electrode GE2 may be provided integrally with the first scanning line Si and connected to the first scanning line Si. The second gate electrode GE2 may be provided as a part of the first scanning line Si or may be provided in a shape that protrudes from the first scanning line Si.

[0129] The second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. For example, the second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be formed of an oxide semiconductor that is not doped with impurities or is doped with impurities. The second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be formed of an oxide semiconductor with a thickness of approximately 30 nm to 60 nm.

[0130] The second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be provided on the second interlayer insulating film ILD2.

[0131] The second active pattern ACT2 is a region overlapping with the second gate electrode GE2 and may be a channel region of the second transistor T2.

[0132] The second source region SE2 may be connected to one end of the second active pattern ACT2 and to the first gate electrode GE1 of the first transistor T1 via a fourth connection line CNL4.

[0133] The second drain region DE2 may be connected to the other end of the second active pattern ACT2. The second drain region DE2 may also be connected to the data line DLj via a sixth contact hole CH6 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in that order. This allows the data voltage (or data signal) supplied to the data line DLj to be transmitted to the second drain region DE2 when the second transistor T2 is turned on.

[0134] The second conductive pattern BML2 may be disposed between the second transistor T2 and the substrate SUB. The second conductive pattern BML2 may overlap the second transistor T2 when viewed in a plan view. The second conductive pattern BML2 may be provided in the same layer as the first conductive pattern BML1 and may include the same material as the first conductive pattern BML1. For example, the second conductive pattern BML2 may be disposed between the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2. The second conductive pattern BML2 may be connected to the second connection wiring CNL2 via a fourth contact hole CH4.

[0135] The second connection wiring CNL2 may be a fourth conductive layer provided and / or formed on the third interlayer insulating film ILD3. The second connection wiring CNL2 may be connected to the second conductive pattern BML2 via a fourth contact hole CH4 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order. The second connection wiring CNL2 may also be connected to the second gate electrode GE2 of the second transistor T2 via a fifth contact hole CH5 that passes through the third interlayer insulating film ILD3.

[0136] In one embodiment of the present invention, the second connection wiring CNL2 may be connected to the second conductive pattern BML2 through the fourth contact hole CH4 and connected to the second gate electrode GE2 through the fifth contact hole CH5. As a result, the second gate electrode GE2 can be connected to the second conductive pattern BML2 through the second connection wiring CNL2.

[0137] As described above, when the second conductive pattern BML2 is connected to the second gate electrode GE2 of the second transistor T2, a voltage of the same level as the voltage supplied to the second gate electrode GE2 can be transmitted to the second conductive pattern BML2, which can be advantageous for charging the gate voltage of the first transistor T1, which is the driving transistor, when the second conductive pattern BML2 is connected to the second gate electrode GE2 of the second transistor T2.

[0138] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source region SE3, and a third drain region DE3.

[0139] The third gate electrode GE3 may be integral with the second scanning line Si+1 and connected to the second scanning line Si+1. The third gate electrode GE3 may be provided as a part of the second scanning line Si+1 or may be provided in a shape that protrudes from the second scanning line Si+1.

[0140] The third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be semiconductor patterns made of polysilicon, amorphous silicon, an oxide semiconductor, or the like. For example, the third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be formed of an oxide semiconductor that is not doped with impurities or is doped with impurities. The third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be formed of an oxide semiconductor with a thickness of approximately 30 nm to 60 nm.

[0141] The third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be provided on the second interlayer insulating film ILD2.

[0142] The third active pattern ACT3 is a region overlapping with the third gate electrode GE3, and may be a channel region of the third transistor T3.

[0143] The third source region SE3 may be connected to one end of the third active pattern ACT3, and may also be connected to the first source region SE1 of the first transistor T1.

[0144] The third drain region DE3 may be connected to the other end of the third active pattern ACT3 and the reference voltage line RFj via a seventh contact hole CH7 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order.

[0145] A third conductive pattern BML3 may be disposed between the above-described third transistor T3 and the substrate SUB. The third conductive pattern BML3 may be a second conductive layer provided on the first interlayer insulating film ILD1. The third conductive pattern BML3 may be provided in the same layer as the first and second conductive patterns BML1 and BML2.

[0146] The third conductive pattern BML3 may be connected to the third connection line CNL3 via a ninth contact hole CH9 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order.

[0147] The third connection line CNL3 may be a fourth conductive layer provided on the third interlayer insulating film ILD3. The third connection line CNL3 may be connected to the third gate electrode GE3 of the third transistor T3 via an eighth contact hole CH8 that penetrates the third interlayer insulating film ILD3.

[0148] In one embodiment of the present invention, the third connection line CNL3 may be connected to the third gate electrode GE3 of the third transistor T3 through an eighth contact hole CH8 and to the third conductive pattern BML3 through a ninth contact hole CH9. As a result, the third gate electrode GE3 of the third transistor T3 may be connected to the third conductive pattern BML3 through the third connection line CNL3.

[0149] As described above, when the third conductive pattern BML3 is connected to the third gate electrode GE3 of the third transistor T3, a voltage of the same level as the voltage supplied to the third gate electrode GE3 can be transmitted to the third conductive pattern BML3. When the third conductive pattern BML3 is connected to the third gate electrode GE3 of the third transistor T3, the on-current (Ion) increases, and the electrical characteristics of the third transistor T3 can be improved.

[0150] The fourth transistor T4 may include a fourth gate electrode GE4, a fourth active pattern ACT4, a fourth source region SE4, and a fourth drain region DE4.

[0151] The fourth gate electrode GE4 may be connected to the light-emitting control line Ei. The fourth gate electrode GE4 may be provided integrally with the light-emitting control line Ei and connected to the light-emitting control line Ei. The fourth gate electrode GE4 may be provided as a part of the light-emitting control line Ei, or may be provided in a shape that protrudes from the light-emitting control line Ei.

[0152] The fourth active pattern ACT4, the fourth source region SE4, and the fourth drain region DE4 may be provided on the buffer film BFL.

[0153] The fourth active pattern ACT4, the fourth source region SE4, and the fourth drain region DE4 may be formed of a polysilicon semiconductor layer that is not doped with impurities or that is doped with impurities. For example, the fourth source region SE4 and the fourth drain region DE4 may be formed of a polysilicon semiconductor layer that is doped with impurities, and the fourth active pattern ACT4 may be formed of a polysilicon semiconductor layer that is not doped with impurities.

[0154] The fourth active pattern ACT4 is a region overlapping with the fourth gate electrode GE4, and may be a channel region of the fourth transistor T4.

[0155] The fourth source region SE4 may be connected to one end of the fourth active pattern ACT4 and may also be connected to the power line PL via a third contact hole CH3 that passes through the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order.

[0156] The fourth drain region DE4 may be connected to the other end of the fourth active pattern ACT4 and may be connected to the first drain region DE1 of the first transistor T1 via a tenth contact hole CH10, a fifth connection line CNL5, and an eleventh contact hole CH11.

[0157] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0158] The lower electrode LE may be provided integrally with the first conductive pattern BML1 that overlaps with the first transistor T1. When the lower electrode LE is provided integrally with the first conductive pattern BML1, the lower electrode LE can be regarded as one region of the first conductive pattern BML1.

[0159] The upper electrode UE may be disposed on the lower electrode LE and overlap with the lower electrode LE. Increasing the overlapping area between the upper electrode UE and the lower electrode LE can increase the capacitance of the storage capacitor Cst. The upper electrode UE may be formed integrally with the first gate electrode GE1 of the first transistor T1. When the upper electrode UE is formed integrally with the first gate electrode GE1, the upper electrode UE can be regarded as a region of the first gate electrode GE1. As a result, the upper electrode UE can be electrically connected to the second source region SE2 of the second transistor T2 via the first contact hole CH1, the fourth connection line CNL4, and the second contact hole CH2.

[0160] The protective film PSV may be provided on components corresponding to the fourth conductive layer, such as the reference voltage lines RFj, the data lines DLj, the power supply lines PL, and the first to fifth connection lines CNL1 to CNL5.

[0161] The passivation film PSV may be formed as an organic insulating film, an inorganic insulating film, or the organic insulating film disposed on the inorganic insulating film. Here, the inorganic insulating film may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and a metal oxide such as aluminum oxide (AlOx). The organic insulating film may include an organic insulating material that can transmit light. The organic insulating film may include at least one of, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin. In one embodiment of the present invention, the passivation film PSV may be made of an organic insulating film, such as a polyimide resin, which is advantageous for planarization, and may have a thickness of about 1600 nm, although the present invention is not limited thereto.

[0162] Next, the display element layer DPL will be described.

[0163] The display element layer DPL may include a light-emitting element OLED and a pixel defining layer PDL.

[0164] The light-emitting element OLED may include a first electrode AE, a second electrode CE, and an emitting layer EML disposed between the two electrodes AE and CE. One of the first and second electrodes AE and CE may be an anode electrode, and the other may be a cathode electrode. When the light-emitting element OLED is a top-emitting organic light-emitting element, the first electrode AE may be a reflective electrode, and the second electrode CE may be a transmissive electrode. In one embodiment of the present invention, the light-emitting element OLED is a top-emitting organic light-emitting element, and the first electrode AE is an anode electrode.

[0165] The first electrode AE may be disposed and / or formed on the passivation film PSV. The first electrode AE may be connected to the first connection line CNL1 through a fourteenth contact hole CH14 that penetrates the passivation film PSV. Thus, the first electrode AE may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 through the first connection line CNL1. The first electrode AE may include a reflective film (not shown) that can reflect light and transparent conductive films (not shown) disposed above and below the reflective film. For example, the first electrode AE may be formed of a multi-layer structure including a lower transparent conductive film made of indium tin oxide (ITO), a reflective film made of silver (Ag) disposed on the lower transparent conductive film, and an upper transparent conductive film made of indium tin oxide (ITO) disposed on the reflective film. In this case, the lower transparent conductive film may have a thickness of about 5 nm, the reflective film may have a thickness of about 85 nm, and the upper transparent conductive film may have a thickness of about 7 nm. At least one of the lower transparent conductive film, the reflective film, and the upper transparent conductive film may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3, respectively.

[0166] In the above-described embodiment, the first electrode AE is described as being made of a multilayer structure in which ITO / Ag / ITO are stacked in this order, but the present invention is not limited thereto. Depending on the embodiment, the first electrode AE may be made of a single layer made of a transparent metal oxide such as indium tin oxide (ITO).

[0167] A pixel defining layer PDL may be disposed on the first electrode AE. The pixel defining layer PDL may have an opening that exposes a portion of the first electrode AE, for example, the upper surface of the first electrode AE. The pixel defining layer PDL may be an organic insulating layer containing an organic material. For example, the pixel defining layer PDL may be made of a polyimide resin and have a thickness of about 1500 nm to 1600 nm. However, the present invention is not limited to this.

[0168] An emission layer EML may be provided on an upper surface of the first electrode AE exposed by the opening of the pixel defining layer PDL, and a second electrode CE may be provided on the emission layer EML.

[0169] The light-emitting layer EML may be disposed on the exposed upper surface of the first electrode AE. The light-emitting layer EML may have a multilayer thin film structure including at least a light-generation layer. The light-emitting layer EML may include a hole injection layer for injecting holes, a hole transport layer having excellent hole transport properties and suppressing the movement of uncombined electrons in the light-generation layer to increase the chance of hole and electron recombination, a light-generation layer that emits light by recombination of the injected electrons and holes, a hole blocking layer for suppressing the movement of uncombined holes in the light-generation layer, an electron transport layer for smoothly transporting electrons to the light-generation layer, and an electron injection layer for injecting electrons.

[0170] The color of light generated by the light-generating layer may be one of red, green, blue, and white, but is not limited thereto in this embodiment. For example, the color of light generated by the light-generating layer of the emitting layer EML may be one of magenta, cyan, and yellow. The hole injection layer, hole transport layer, hole blocking layer, electron transport layer, and electron injection layer may be a common layer connected to adjacent light-emitting regions.

[0171] A thin-film sealing film TFE may be provided on the second electrode EL2 to cover the second electrode EL2.

[0172] The thin film encapsulation film TFE may be composed of a single layer or multiple layers. The thin film encapsulation film TFE may include multiple insulating films that cover the light-emitting element OLED. Specifically, the thin film encapsulation film TFE may include at least one inorganic film and at least one organic film. For example, the thin film encapsulation film TFE may have a structure in which inorganic films and organic films are alternately stacked. Depending on the embodiment, the thin film encapsulation film TFE may be an encapsulation substrate that is disposed on the light-emitting element OLED and bonded to the substrate SUB by a sealant.

[0173] Meanwhile, a display device according to an embodiment of the present invention may further include a touch sensor (not shown) provided on the thin film encapsulation film TFE. The touch sensor is disposed on a surface of the substrate SUB in a direction in which an image is emitted and can receive a touch input from a user. The touch sensor can recognize a touch event on the display device through a user's hand or another input means.

[0174] According to the above-described embodiment, each pixel PXL realizes the first to third transistors T1 to T3, among the transistors included in the pixel circuit PXC, as oxide transistors, thereby minimizing leakage current and improving the characteristics of each element, thereby easily realizing a high-resolution display device.

[0175] Furthermore, according to the above-described embodiment, the first to third conductive patterns BML1, BML2, BML3 are arranged between the substrate SUB and the first to third transistors T1 to T3 realized by oxide transistors, thereby making it possible to prevent the element characteristics of the first to third transistors T1 to T3 from being changed by light entering the back surface of the substrate SUB.

[0176] In addition, according to the above-described embodiment, the first conductive pattern BML1 is connected to the first source region SE1 of the first transistor T1, so that the first transistor T1 performs a drain sync operation during the initialization period (or reset period), which is advantageous for shortening the initialization period. Also, the swing margin of the second driving power source ELVSS is secured, which can widen the driving range of the gate voltage applied to the first gate electrode GE1 of the first transistor T1.

[0177] Furthermore, as described above, by using the first conductive pattern BML1 as one electrode of the storage capacitor Cst, for example, the lower electrode LE, it is possible to secure sufficient space for forming the storage capacitor Cst within the narrow space of the pixel area PXA, thereby providing a display device that can easily achieve high resolution.

[0178] FIG. 7 is a plan view schematically illustrating one pixel according to another embodiment of the present invention.

[0179] In FIG. 7, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0180] The pixel shown in Figure 7 may have a configuration substantially similar to that of the pixel shown in Figure 4, except that the data line DLj is arranged closer to the power supply line PL than the reference voltage line RFj. Therefore, in Figure 7, differences from the above-mentioned embodiment will be mainly described to avoid redundant explanation. Parts not particularly described in the embodiment of Figure 7 are similar to the above-mentioned embodiment, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0181] 1 to 3 and 7, each pixel PXL may be provided in a pixel area PXA included in a display area DA of a substrate SUB.

[0182] The pixel area PXA may include scanning lines Si, Si+1, a light emission control line Ei, a reference voltage line RFj, a data line DLj, and a power supply line PL connected to the pixel circuit PXC.

[0183] The reference voltage lines RFj, the power supply lines PL, and the data lines DLj may be provided in a form extending along the second direction DR2. Alternatively, the reference voltage lines RFj, the power supply lines PL, and the data lines DLj may be arranged along the first direction DR1 and spaced apart from one another. In one embodiment of the present invention, the reference voltage lines RFj, the power supply lines PL, and the data lines DLj may be provided on a third interlayer insulating film (see ILD3 in FIG. 5) and spaced apart from one another.

[0184] A reference voltage line RFj may be spaced apart at a predetermined distance from one side of the data line DLj, and a power line PL may be spaced apart at a predetermined distance from the other side. The distance between the data line DLj and the reference voltage line RFj may be different from the distance between the data line DLj and the power line PL. For example, the distance between the data line DLj and the power line PL may be narrower than the distance between the data line DLj and the reference voltage line RFj. In this case, the data line DLj may be disposed closer to the power line PL than the reference voltage line RFj.

[0185] When viewed in a plane, the first to third transistors T1 to T3 and the storage capacitor Cst included in the pixel circuit PXC may be arranged between the reference voltage line RFj and the data line DLj. In one embodiment of the present invention, the reference voltage line RFj and the data line DLj may be arranged apart from each other with some components included in the pixel circuit PXC sandwiched therebetween when viewed in a plane.

[0186] As described above, when the data line DLj is disposed closer to the power supply line PL than the reference voltage line RFj, the distance between the first gate electrode GE1 of the first transistor T1 and the data line DLj can be further secured compared to the pixel shown in Figure 4. This can prevent crosstalk by blocking vertical cap coupling (e.g., parasitic capacitor) formed between the first gate electrode GE1 of the first transistor T1 and the data line DLj.

[0187] FIG. 8 is a plan view schematically showing one pixel according to yet another embodiment of the present invention, FIG. 9 is a cross-sectional view along line CC' in FIG. 8, and FIG. 10 is a cross-sectional view along line DD' in FIG. 8.

[0188] In FIG. 8, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0189] The pixels shown in FIGS. 8 to 10 may have substantially similar configurations to the pixel shown in FIG. 4, except that the data lines DLj and the power supply lines PL are arranged in a layer different from that of the reference voltage lines RFj, and the first and third transistors T1 and T3 are electrically connected to the light-emitting element OLED via a bridge pattern BRP.

[0190] Therefore, to avoid redundant explanation, differences from the above-described embodiment will be mainly described in Figures 8 to 10. Portions not specifically described in the embodiment of Figures 8 to 10 are the same as those in the above-described embodiment, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0191] 1 to 3 and 8 to 10, a display device according to an embodiment of the present invention may include a substrate SUB, a wiring portion, and a pixel PXL.

[0192] A buffer film BFL, a first gate insulating film GI1, first and second interlayer insulating films ILD1 and ILD2, a second gate insulating film GI2, a third interlayer insulating film ILD3, a first protective film PSV1, and a second protective film PSV2 may be stacked in this order on the substrate SUB. Also, a plurality of conductive layers may be provided and / or formed between the insulating films.

[0193] In one embodiment of the present invention, the conductive layer may include, for example, a first conductive layer provided on the first gate insulating film GI1, a second conductive layer provided on the first interlayer insulating film ILD1, a third conductive layer provided on the second gate insulating film GI2, a fourth conductive layer provided on the third interlayer insulating film ILD3, and a fifth conductive layer provided on the first protective film PSV1.

[0194] Each pixel PXL may be provided in a pixel area PXA included in a display area DA of the substrate SUB.

[0195] In the pixel area PXA, first and second scan lines Si, Si+1, a light emission control line Ei, a data line DLj, a reference voltage line RFj, and a power supply line PL may be arranged.

[0196] When viewed in a plan view, the first and second scan lines Si, Si+1 and the emission control line Ei may extend along a first direction DR1 and be arranged along a second direction DR2. The first and second scan lines Si, Si+1 and the emission control line Ei may be provided in different layers. For example, the first and second scan lines Si, Si+1 may be provided on a second gate insulating film GI2, and the emission control line Ei may be provided on a first gate insulating film GI1. In one embodiment of the present invention, the first and second scan lines Si, Si+1 may be provided in a third conductive layer, and the emission control line Ei may be provided in a first conductive layer.

[0197] In one embodiment of the present invention, the power line PL may include a first power line PL1 and a second power line PL2. The first and second power lines PL1 and PL2 may extend along the second direction DR2. The first power line PL1 may be provided and / or formed on a third interlayer insulating film ILD3, and the second power line PL2 may be provided and / or formed on a first protective film PSV1. The first power line PL1 may be a fourth conductive layer, and the second power line PL2 may be a fifth conductive layer. Here, the first protective film PSV1 may have the same configuration as the protective film PSV described with reference to FIGS. 4 to 6.

[0198] The first power supply line PL1 and the second power supply line PL2 may be connected via a fifteenth contact hole CH15 that penetrates the third interlayer insulating film ILD3.

[0199] When viewed in a plane, the reference voltage lines RFj, the data lines DLj, and the power supply lines PL may extend along the second direction DR2 and be arranged in the order of the reference voltage lines RFj, the data lines DLj, and the power supply lines PL along the first direction DR1.

[0200] The reference voltage line RFj and the first power supply line PL1 may be provided and / or formed in the same layer, and the data line DLj and the second power supply line PL2 may be provided in the same layer. For example, the reference voltage line RFj may be provided on the third interlayer insulating film ILD3, and the data line DLj may be provided on the first passivation film PSV1. In one embodiment of the present invention, the reference voltage line RFj may be in the fourth conductive layer, and the data line DLj may be in the fifth conductive layer.

[0201] Each pixel PXL may include a pixel circuit layer PCL having a pixel circuit PXC and a display element layer DPL having a light-emitting element OLED.

[0202] In one embodiment of the present invention, the pixel circuit layer PCL may include a buffer film BFL provided on a substrate SUB, a pixel circuit PXC provided on the buffer film BFL, and first and second protective films PSV1 and PSV2 provided on the pixel circuit PXC.

[0203] The pixel circuit PXC may include first to fourth transistors T1 to T4 and a storage capacitor Cst. The pixel circuit PXC may also include a first conductive pattern BML1 connected to the first transistor T1, a second conductive pattern BML2 connected to the second transistor T2, and a third conductive pattern BML3 connected to the third transistor T3.

[0204] Of the first to fourth transistors T1 to T4, the first to third transistors T1 to T3 may be realized by oxide transistors, and the fourth transistor T4 may be realized by a polysilicon transistor.

[0205] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1. A first conductive pattern BML1 may be disposed below the first transistor T1.

[0206] The first conductive pattern BML1 may overlap the first transistor T1. For example, the first conductive pattern BML1 may be disposed below the first gate electrode GE1 of the first transistor T1 and overlap the first gate electrode GE1.

[0207] The first gate electrode GE1 may be a third conductive layer provided on the second gate insulating film GI2. The first gate electrode GE1 may overlap the first conductive pattern BML1 with at least one insulating film sandwiched therebetween. For example, the first gate electrode GE1 may overlap the first conductive pattern BML1 with a second interlayer insulating film ILD2 and a second gate insulating film GI2 sandwiched therebetween. This allows capacitance to be formed between the first gate electrode GE1 and the first conductive pattern BML1 due to cap coupling.

[0208] Depending on the embodiment, an opening OPN formed by removing a portion of the second gate insulating film GI2 may be provided between the first gate electrode GE1 and the first conductive pattern BML1. The opening OPN may be formed by removing a portion of an insulating film provided in a region where the first gate electrode GE1 and the first conductive pattern BML1 overlap, for example, a portion of the second gate insulating film GI2. Due to the opening OPN formed by removing a portion of the second gate insulating film GI2 disposed between the first gate electrode GE1 and the first conductive pattern BML1, only the second interlayer insulating film ILD2 may be provided between the first gate electrode GE1 and the first conductive pattern BML1, as shown in FIGS. 9 and 10 .

[0209] When only the second interlayer insulating film ILD2 is provided between the first gate electrode GE1 and the first conductive pattern BML1, the distance between the first gate electrode GE1 and the first conductive pattern BML1 can be narrowed compared to when the second interlayer insulating film ILD2 and the second gate insulating film GI2 are sequentially provided between the first gate electrode GE1 and the first conductive pattern BML1, thereby further increasing capacitance due to cap coupling formed between the first gate electrode GE1 and the first conductive pattern BML1.

[0210] Furthermore, a first connection wiring CNL1 may be arranged on a region where the first gate electrode GE1 and the first conductive pattern BML1 overlap. The first connection wiring CNL1 may be arranged on the third interlayer insulating film ILD3 and overlap with the first gate electrode GE1 with the third interlayer insulating film ILD3 sandwiched therebetween. This allows capacitance to be formed between the first gate electrode GE1 and the first connection wiring CNL1 due to cap coupling.

[0211] As described above, a capacitance may be formed between the first conductive pattern BML1 and the first gate electrode GE1 with the second interlayer insulating film ILD2 sandwiched therebetween, and a capacitance may be formed between the first gate electrode GE1 and the first connection line CNL1 with the third interlayer insulating film ILD3 sandwiched therebetween. In one embodiment of the present invention, the first conductive pattern BML1 may be a first storage electrode forming the storage capacitor Cst, the first gate electrode GE1 may be a second storage electrode forming the storage capacitor Cst, and the first connection line CNL1 may be a third storage electrode forming the storage capacitor Cst.

[0212] The first source region SE1 of the first transistor T1 may be connected to the first conductive pattern BML1 via a twelfth contact hole CH12, a first connection line CNL1, and a thirteenth contact hole CH13. For example, the first source region SE1 may be connected to the first connection line CNL1 via the twelfth contact hole CH12 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in that order, and the first connection line CNL1 may be connected to the first conductive pattern BML1 via the thirteenth contact hole CH13 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in that order. This allows the first source region SE1 to be connected to the first conductive pattern BML1 via the twelfth contact hole CH12, the first connection line CNL1, and the thirteenth contact hole CH13.

[0213] The first drain region DE1 of the first transistor T1 may be connected to the fourth drain region DE4 of the fourth transistor T4 via an eleventh contact hole CH11, a fifth connection line CNL5, and a tenth contact hole CH10.

[0214] The tenth to thirteenth contact holes CH10 to CH13 may have the same configuration as the tenth to thirteenth contact holes CH10 to CH13 described with reference to FIGS.

[0215] A first protective film PSV1 may be provided on the first connection line CNL1. A bridge pattern BRP may be disposed on the first protective film PSV1. In an embodiment of the present invention, the bridge pattern BRP may be a fifth conductive layer provided on the first protective film PSV1, and may be provided in the same layer and made of the same material as the data line DLj and the second power line PL2. The bridge pattern BRP may be disposed spaced apart from the data line DLj and the second power line PL2. The bridge pattern BRP may be connected to the first connection line CNL1 through a fourteenth contact hole CH14 penetrating the first protective film PSV1.

[0216] A second protective film PSV2 may be formed on the bridge pattern BRP, the data line DLj, and the second power line PL2. The second protective film PSV2 may include the same material as the first protective film PSV1. For example, the second protective film PSV2 may be made of an organic insulating film including an organic material that is advantageous for planarization. A polyimide resin may be selected as the organic insulating film. In this case, the second protective film PSV2 may have a thickness of about 1600 nm, but the present invention is not limited to this.

[0217] The bridge pattern BRP may be connected to the first electrode AE of the light emitting element OLED through a seventeenth contact hole CH17 that penetrates the second passivation layer PSV2. As a result, the first electrode AE may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 through the bridge pattern BRP and the first connection line CNL1.

[0218] The above-mentioned fourteenth contact hole CH14 and seventeenth contact hole CH17 may have a size relatively larger than that of contact holes penetrating an inorganic insulating film made of an inorganic material due to the material properties of the insulating film disposed thereunder, for example, the first protective film PSV1 and the second protective film PSV2. The fourteenth contact hole CH14 and the seventeenth contact hole CH17 may have a size (or area) larger than that of the first to thirteenth contact holes CH1 to CH13 and the fifteenth and sixteenth contact holes CH15 and CH16.

[0219] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2. A second conductive pattern BML2 may be disposed below the second transistor T2.

[0220] The second gate electrode GE2 may be formed integrally with the first scanning line Si, and the second active pattern ACT2 may overlap the second gate electrode GE2.

[0221] The second source region SE2 may be connected to one end of the second active pattern ACT2. The second source region SE2 may also be connected to the first gate electrode GE1 of the first transistor T1 via the second contact hole CH2, the fourth connection line CNL4, and the first contact hole CH1. The first and second contact holes CH1 and CH2 may have the same configuration as the first and second contact holes CH1 and CH2 described with reference to FIGS.

[0222] The second drain region DE2 may be connected to the other end of the second active pattern ACT2. The second drain region DE2 may also be connected to the sixth connection line CNL6 via a sixth contact hole CH6 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order. The sixth contact hole CH6 may have the same configuration as the sixth contact hole CH6 described with reference to FIGS. 4 to 6.

[0223] The sixth connection line CNL6 may be connected to the data line DLj through a sixteenth contact hole CH16 that penetrates the first protective film PSV1. This allows the second drain region DE2 to be connected to the data line DLj through the sixth contact hole CH6, the sixth connection line CNL6, and the sixteenth contact hole CH16. This allows the data voltage (or data signal) supplied to the data line DLj to be transmitted to the second drain region DE2 when the second transistor T2 is turned on.

[0224] The second conductive pattern BML2 may be connected to the second gate electrode GE2 of the second transistor T2 via a fourth contact hole CH4, a second connection wiring CNL2, and a fifth contact hole CH5. The fourth and fifth contact holes CH4 and CH5 may have the same configuration as the fourth and fifth contact holes CH4 and CH5 described with reference to FIGS.

[0225] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source region SE3, and a third drain region DE3. A third conductive pattern BML3 may be disposed below the third transistor T3.

[0226] The third gate electrode GE3 may be integral with the second scan line Si+1, and the third active pattern ACT3 may overlap the third gate electrode GE3.

[0227] The third source region SE3 may be connected to one end of the third active pattern ACT3 and the first source region SE1 of the first transistor T1.

[0228] The third drain region DE3 may be connected to the other end of the third active pattern ACT3. The third drain region DE3 may also be connected to the reference voltage line RFj via a seventh contact hole CH7. The seventh contact hole CH7 may have the same configuration as the seventh contact hole CH7 described with reference to FIGS. 4 to 6.

[0229] The third conductive pattern BML3 may be connected to the third gate electrode GE3 of the third transistor T3 via a ninth contact hole CH9, a third connection wiring CNL3, and an eighth contact hole CH8. The eighth and ninth contact holes CH8 and CH9 may have the same configuration as the eighth and ninth contact holes CH8 and CH9 described with reference to FIGS.

[0230] The fourth transistor T4 may include a fourth gate electrode GE4, a fourth active pattern ACT4, a fourth source region SE4, and a fourth drain region DE4.

[0231] The fourth gate electrode GE4 may be integral with the light-emitting control line Ei, and the fourth active pattern ACT4 may overlap the fourth gate electrode GE4.

[0232] The fourth source region SE4 may be connected to one end of the fourth active pattern ACT4. The fourth source region SE4 may also be connected to the first power supply line PL1 via a third contact hole CH3. The third contact hole CH3 may have the same configuration as the third contact hole CH3 described with reference to FIGS. 4 to 6.

[0233] The fourth drain region DE4 may be connected to the other end of the fourth active pattern ACT4 and may be connected to the first drain region DE1 of the first transistor T1 via a tenth contact hole CH10, a fifth connection line CNL5, and an eleventh contact hole CH11.

[0234] Meanwhile, in one embodiment of the present invention, the power line PL may overlap with a portion of the components included in the pixel circuit PXC, for example, a portion of the first transistor T1, and cover that portion when viewed in a plan view. For example, as shown in FIG. 8, if the second power line PL2 of the power line PL is extended to cover that portion of the first transistor T1, the second power line PL2 may block vertical capacitive coupling formed between the data line DLj and the first gate electrode GE1 of the first transistor T1. This prevents crosstalk between the data line DLj and the first transistor T1, thereby reducing image quality defects caused by the crosstalk.

[0235] As described above, the capacitance can be further increased by cap coupling formed between the first conductive pattern BML1 and the first gate electrode GE1 due to the opening OPN formed by removing a portion of the insulating film disposed between the first conductive pattern BML1 and the first gate electrode GE1 of the first transistor T1, thereby further increasing the capacitance of the storage capacitor Cst in each pixel PXL.

[0236] Also, as described above, by extending the power supply line PL to cover the first transistor T1, it is possible to block the vertical cap coupling formed between the data line DLj and the first gate electrode GE1 of the first transistor T1.

[0237] Furthermore, as described above, by using the first conductive pattern BML1 as the first electrode of the storage capacitor Cst, the first gate electrode GE1 as the second electrode of the storage capacitor Cst, and the first connection line CNL1 as the third electrode of the storage capacitor Cst, it is possible to ensure sufficient space for forming the storage capacitor Cst within the narrow space of the pixel region PXA of each pixel PXL, thereby providing a display device that can easily achieve high resolution.

[0238] FIG. 11 is a plan view schematically showing one pixel according to yet another embodiment of the present invention, FIG. 12 is a cross-sectional view taken along line E-E' in FIG. 11, and FIG. 13 is a cross-sectional view taken along line F-F' in FIG. 11.

[0239] In FIG. 11, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0240] 11 to 13, the following description will focus on the differences from the above-described embodiment to avoid repetitive explanation. Parts of the present invention that are not particularly described are the same as those of the above-described embodiment, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0241] 1 to 3 and 11 to 13, a display device according to an embodiment of the present invention may include a substrate SUB, a wiring portion, and a pixel PXL.

[0242] A plurality of insulating films and a plurality of conductive layers may be provided and / or formed on the substrate SUB.

[0243] In one embodiment of the present invention, the insulating film may include, for example, a buffer film BFL, a first gate insulating film GI1, first and second interlayer insulating films ILD1 and ILD2, a second gate insulating film GI2, a third interlayer insulating film ILD3, a first protective film PSV1, and a second protective film PSV2, which are stacked in this order on the substrate SUB. The buffer film BFL, the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI, the third interlayer insulating film ILD3, the first protective film PSV1, and the second protective film PSV2 have the same configuration as the buffer film BFL, the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, the third interlayer insulating film ILD3, the first protective film PSV1, and the second protective film PSV2 described with reference to FIGS. 4 and 8, and therefore will only be briefly described.

[0244] Conductive layers may be provided and / or formed between the above-mentioned insulating films. In one embodiment of the present invention, the conductive layers may include, for example, a first conductive layer provided on the first gate insulating film GI1, a second conductive layer provided on the first interlayer insulating film ILD1, a third conductive layer provided on the second gate insulating film GI2, a fourth conductive layer provided on the third interlayer insulating film ILD3, and a fifth conductive layer provided on the first protective film PSV1.

[0245] Each pixel PXL may be provided in a pixel area PXA included in a display area DA of the substrate SUB. Each pixel PXL may include a pixel circuit layer PCL including a pixel circuit PXC and a display element layer DPL including a light-emitting element OLED.

[0246] In a pixel area PXA where each pixel PXL is provided, first and second scan lines Si, Si+1, an emission control line Ei, a reference voltage line RFj, a data line DLj, and a power line PL may be arranged. The first and second scan lines Si, Si+1, an emission control line Ei, a reference voltage line RFj, a data line DLj, and a power line PL have the same configuration as the first and second scan lines Si, Si+1, an emission control line Ei, a reference voltage line RFj, a data line DLj, and a power line PL described with reference to FIGS. 4 and 8, and therefore will only be briefly described.

[0247] The first and second scan lines Si and Si+1 may be a third conductive layer provided on the second gate insulating film GI2, and the light-emitting control line Ei may be a first conductive layer provided on the first gate insulating film GI1. The reference voltage line RFj may be a fourth conductive layer provided on the third interlayer insulating film ILD3, and the data line DLj and the power supply line PL may be a fifth conductive layer provided on the first protective film PSV1.

[0248] The pixel circuit layer PCL may include a buffer film BFL, a pixel circuit PXC provided on the buffer film BFL, and first and second protective films PSV1 and PSV2 provided on the pixel circuit PXC. The pixel circuit layer PCL may also include first to third conductive patterns BML1 to BML3 connected to the components included in the pixel circuit PXC.

[0249] The pixel circuit PXC may include first to fourth transistors T1 to T4 and a storage capacitor Cst. Of the first to fourth transistors T1 to T4, the first to third transistors T1 to T3 may be implemented as oxide transistors, and the fourth transistor T4 may be implemented as a polysilicon transistor. Furthermore, of the first to fourth transistors T1 to T4, the first transistor T1 may be a drive transistor.

[0250] The first transistor T1 may include a first gate electrode GE1, a first active pattern ACT1, a first source region SE1, and a first drain region DE1.

[0251] The first gate electrode GE1 is a third conductive layer provided on the second gate insulating film GI2, and may be provided in the same layer as the first and second scan lines Si, Si+1 and may contain the same material. The first gate electrode GE1 may be connected to the fourth connection line CNL4 via a second contact hole CH2 that penetrates the third interlayer insulating film ILD3.

[0252] In one embodiment of the present invention, the fourth connection line CNL4 may be a fourth conductive layer provided on the third interlayer insulating film ILD3. The fourth connection line CNL4 may be provided in the same layer as the reference voltage line RFj and may include the same material. The fourth connection line CNL4 may be connected to the first gate electrode GE1 through a second contact hole CH2. The fourth connection line CNL4 may also be connected to the second source region SE2 of the second transistor T2 through a third contact hole CH3 that sequentially penetrates the second gate insulating film GI2 and the third interlayer insulating film ILD3. This allows the first gate electrode GE1 to be connected to the second source region SE2 through the second contact hole CH2, the fourth connection line CNL4, and the third contact hole CH3.

[0253] The first active pattern ACT1 is a region overlapping with the first gate electrode GE1 and may be a channel region of the first transistor T1. The first active pattern ACT1 may be provided on the second interlayer insulating film ILD2.

[0254] The first source region SE1 may be connected to one end of the first active pattern ACT1 and the third source region SE3.

[0255] The first drain region DE1 may be connected to the other end of the first active pattern ACT1, and may be connected to the fourth drain region DE4 of the fourth transistor T4 via a fifth connection line CNL5.

[0256] The fifth connection wiring CNL5 may be connected to the first drain region DE1 via a tenth contact hole CH10 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in that order. The fifth connection wiring CNL5 may also be connected to the fourth drain region DE4 via an eleventh contact hole CH11 that passes through the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in that order.

[0257] In one embodiment of the present invention, a first conductive pattern BML1 may be disposed below the first transistor T1. As a result, the first conductive pattern BML1 may overlap the first transistor T1. For example, the first conductive pattern BML1 may overlap the first gate electrode GE1 of the first transistor T1.

[0258] The first conductive pattern BML1 may be a second conductive layer provided on the first interlayer insulating film ILD1. The first conductive pattern BML1 may be connected to the first connection wiring CNL1 via a fifteenth contact hole CH15 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order. The first conductive pattern BML1 may include an opening OPN that corresponds to a region where the first contact hole CH1 is to be formed.

[0259] The first connection wiring CNL1 may be a fourth conductive layer provided on the third interlayer insulating film ILD3. The first connection wiring CNL1 may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 via a fourteenth contact hole CH14 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order.

[0260] As a result, the first conductive pattern BML1 may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 via the fifteenth contact hole CH15, the first connection wiring CNL1, and the fourteenth contact hole CH14.

[0261] A region of the first connection wiring CNL1 may be exposed to the outside through a 16th contact hole CH16 that penetrates the first protective film PSV1. The region of the first connection wiring CNL1 exposed to the outside may be connected to a bridge pattern BRP provided on the first protective film PSV1 through the 16th contact hole CH16.

[0262] The bridge pattern BRP is a fifth conductive layer disposed on the first passivation film PSV1 and may be disposed in the same layer as the data line DLj and the power line PL and may include the same material. A region of the bridge pattern BRP may be exposed to the outside through an 18th contact hole CH18 penetrating the second passivation film PSV2. The exposed bridge pattern BRP may be connected to the first electrode AE of the light-emitting element OLED through the 18th contact hole CH18. As a result, the first electrode AE of the light-emitting element OLED may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 through the 18th contact hole CH18, the bridge pattern BRP, the 16th contact hole CH16, and the first connection line CNL1.

[0263] Meanwhile, in one embodiment of the present invention, a lower electrode LE may be disposed between the substrate SUB and the first conductive pattern BML1. The lower electrode LE is a first conductive layer disposed on the first gate insulating film GI1, and may be disposed in the same layer as the light-emitting control line Ei and may contain the same material. The lower electrode LE may overlap the first conductive pattern BML1. The first conductive pattern BML1 may overlap the lower electrode LE with a first interlayer insulating film ILD1 sandwiched therebetween.

[0264] In one embodiment of the present invention, the lower electrode LE may be connected to the fourth connection line CNL4 via a first contact hole CH1 that sequentially penetrates the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3. The fourth connection line CNL4 is connected to the second source region SE2 of the second transistor T2, and the second source region SE2 is connected to the first gate electrode GE1. Therefore, a gate voltage (or gate signal) applied to the first gate electrode GE1 can be ultimately transmitted to the fourth connection line CNL4 and the lower electrode LE.

[0265] A fourth connection wiring CNL4 may be provided on the first gate electrode GE1. When viewed in a plan view, the lower electrode LE, the first conductive pattern BML1, the first gate electrode GE1, and the fourth connection wiring CNL4 may overlap one another.

[0266] The first conductive pattern BML1 overlaps the lower electrode LE with a first interlayer insulating film ILD1 sandwiched therebetween, the first gate electrode GE1 overlaps the first conductive pattern BML1 with a second interlayer insulating film ILD2 and a second gate insulating layer GI2 sandwiched therebetween, and the fourth connection line CNL4 overlaps the first gate electrode GE1 with a third interlayer insulating film ILD3 sandwiched therebetween. As a result, a capacitance due to cap coupling may be formed between the lower electrode LE and the first conductive pattern BML1, a capacitance due to cap coupling may be formed between the first conductive pattern BML1 and the first gate electrode GE1, and a capacitance due to cap coupling may be formed between the first gate electrode GE1 and the fourth connection line CNL4. These capacitances may collectively form the capacitance of the storage capacitor Cst of each pixel PXL.

[0267] In one embodiment of the present invention, the lower electrode LE may be a first electrode of the storage capacitor Cst, the first conductive pattern BML1 may be a second electrode of the storage capacitor Cst, the first gate electrode GE1 may be a third electrode of the storage capacitor Cst, and the fourth connection wiring CNL4 may be a fourth electrode of the storage capacitor Cst.

[0268] The second transistor T2 may include a second gate electrode GE2, a second active pattern ACT2, a second source region SE2, and a second drain region DE2. In one embodiment of the present invention, the second active pattern ACT2, the second source region SE2, and the second drain region DE2 may be disposed on a second interlayer dielectric film ILD2.

[0269] The second gate electrode GE2 may be provided integrally with the first scanning line Si. The second gate electrode GE2 may be a third conductive layer provided on the second gate insulating film GI2.

[0270] The second active pattern ACT2 is a region overlapping with the second gate electrode GE2, and may be the channel region of the second transistor T2.

[0271] The second source region SE2 may be connected to one end of the second active pattern ACT2 and connected to the first gate electrode GE of the first transistor T1 via a fourth connection line CNL4.

[0272] The second drain region DE2 may be connected to the other end of the second active pattern ACT2 and connected to the seventh connection line CNL7 via a fifth contact hole CH5 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order.

[0273] The seventh connection line CNL7 is a fourth conductive layer provided on the third interlayer insulating film ILD3 and may be provided in the same layer and made of the same material as the reference voltage line RFj. The seventh connection line CNL7 may be connected to the data line DLj through a sixth contact hole CH6 that penetrates the first passivation film PSV1. This allows the second drain region DE2 to be connected to the data line DLj through the fifth contact hole CH5, the seventh connection line CNL7, and the sixth contact hole CH6. This allows the data voltage (or data signal) applied to the data line DLj to be transmitted to the second drain region DE2.

[0274] In one embodiment of the present invention, a second conductive pattern BML2 may be disposed below the second transistor T2, so that the second conductive pattern BML2 may overlap the second transistor T2.

[0275] The second conductive pattern BML2 may be a second conductive layer provided on the first interlayer insulating film ILD1. The second conductive pattern BML2 may be connected to the second connection wiring CNL2 via a seventh contact hole CH7 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order.

[0276] The second connection wiring CNL2 may be connected to the second conductive pattern BML2 via a seventh contact hole CH7. The second connection wiring CNL2 may also be connected to the second gate electrode GE2 via an eighth contact hole CH8 that penetrates the third interlayer insulating film ILD3. This allows the second gate electrode GE2 to be connected to the second conductive pattern BML2 via the eighth contact hole CH8, the second connection wiring CNL2, and the seventh contact hole CH7.

[0277] The third transistor T3 may include a third gate electrode GE3, a third active pattern ACT3, a third source region SE3, and a third drain region DE3. In one embodiment of the present invention, the third active pattern ACT3, the third source region SE3, and the third drain region DE3 may be disposed on the second interlayer dielectric film ILD2.

[0278] The third gate electrode GE3 may be provided integrally with the second scan line Si+1. The third gate electrode GE3 may be a third conductive layer provided on the second gate insulating film GI2.

[0279] The third active pattern ACT3 is a region overlapping with the third gate electrode GE3, and may be a channel region of the third transistor T3.

[0280] The third source region SE3 may be connected to one end of the third active pattern ACT3 and connected to the first source region SE1 of the first transistor T1.

[0281] The third drain region DE3 may be connected to the other end of the third active pattern ACT3 and to the reference voltage line RFj via a ninth contact hole CH9 that passes through the second gate insulating film GI2 and the third interlayer insulating film ILD3 in this order.

[0282] In an embodiment of the present invention, a third conductive pattern BML3 may be disposed below the third transistor T3, so that the third conductive pattern BML3 may overlap the third transistor T3.

[0283] The third conductive pattern BML3 may be a second conductive layer provided on the first interlayer insulating film ILD1. The third conductive pattern BML3 may be connected to the third connection wiring CNL3 via a twelfth contact hole CH12 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order.

[0284] The third connection wiring CNL3 may be connected to the third gate electrode GE3 via a thirteenth contact hole CH13 that penetrates the third interlayer insulating film ILD3, thereby allowing the third gate electrode GE3 to be connected to the third conductive pattern BML3 via the thirteenth contact hole CH13, the third connection wiring CNL3, and the twelfth contact hole CH12.

[0285] The fourth transistor T4 may include a fourth gate electrode GE4, a fourth active pattern ACT4, a fourth source region SE4, and a fourth drain region DE4. In one embodiment of the present invention, the fourth active pattern ACT4, the fourth source region SE4, and the fourth drain region DE4 may be provided on the buffer film BFL.

[0286] The fourth gate electrode GE4 may be provided integrally with the light-emission control line Ei. The fourth gate electrode GE4 may be a first conductive layer provided on the first gate insulating film GI1.

[0287] The fourth active pattern ACT4 is a region overlapping with the fourth gate electrode GE4, and may be a channel region of the fourth transistor T4.

[0288] The fourth source region SE4 may be connected to one end of the fourth active pattern ACT4 and connected to the sixth connection wiring CNL6 via a fourth contact hole CH4 that sequentially penetrates the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3.

[0289] The sixth connection wiring CNL6 may be connected to the fourth source region SE4 via the fourth contact hole CH4, and may be connected to the power line PL via the seventeenth contact hole CH17 that penetrates the first protective film PSV1. This allows the fourth source region SE4 to be connected to the power line PL via the fourth contact hole CH4, the sixth connection wiring CNL6, and the seventeenth contact hole CH17. This allows the first drive power supply ELVDD applied to the power line PL to be transmitted to the fourth source region SE4.

[0290] The fourth drain region DE4 is connected to the other end of the fourth active pattern ACT4, and may be connected to the first drain region DE1 of the first transistor T1 via the eleventh contact hole CH11, the fifth connection wiring CNL5, and the tenth contact hole CH10.

[0291] In the above-described embodiment, a fourth active pattern ACT4, a fourth source region SE4, and a fourth drain region DE4 may be disposed on the buffer film BFL of each pixel PXL. In one embodiment of the present invention, the fourth active pattern ACT4, the fourth source region SE4, and the fourth drain region DE4 are semiconductor patterns made of polysilicon and may have a thickness of about 50 nm, but the present invention is not limited to this. A first gate insulating film GI1 may be disposed on the fourth active pattern ACT4, the fourth source region SE4, and the fourth drain region DE4.

[0292] In the above-described embodiment, the light-emitting control line Ei and the lower electrode LE may be disposed on the first gate insulating film GI1 of each pixel PXL. The light-emitting control line Ei and the lower electrode LE may be a first conductive layer. The light-emitting control line Ei and the lower electrode LE may be made of a conductive material, for example, a metal. The light-emitting control line Ei and the lower electrode LE may be formed as a single layer using a single material or a mixture of materials selected from the group consisting of molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. Alternatively, the light-emitting control line Ei and the lower electrode LE may be formed as a double-layer or multi-layer structure using low-resistance materials such as molybdenum (Mo), aluminum (Al), or silver (Ag) to reduce wiring resistance. In one embodiment of the present invention, the light-emitting control line Ei and the lower electrode LE may be formed as a single layer containing molybdenum (Mo). However, the materials of the light-emitting control line Ei and the lower electrode LE are not limited to those in the above-described embodiment. A first interlayer insulating film ILD1 may be provided on the light-emitting control line Ei and the lower electrode LE.

[0293] First to third conductive patterns BML1 to BML3 may be disposed on the first interlayer insulating film ILD1 of each pixel PXL, spaced apart from one another. The first to third conductive patterns BML1 to BML3 may be second conductive layers. The first conductive pattern BML1 may include an opening OPN exposing a portion of the first interlayer insulating film ILD1 disposed thereunder. The first to third conductive patterns BML1 to BML3 may include the same material as the light-emitting control line Ei and the lower electrode LE, or may include one or more materials selected from the materials exemplified as materials for the light-emitting control line Ei and the lower electrode LE. In one embodiment of the present invention, the first to third conductive patterns BML1 to BML3 may be formed of a single film made of molybdenum (Mo). However, the material of the first to third conductive patterns BML1 to BML3 is not limited to that in the above embodiment. A second interlayer insulating film ILD2 may be disposed on the first to third conductive patterns BML1 to BML3.

[0294] First to third active patterns ACT1, ACT2, ACT3, first to third source regions SE1, SE2, SE3, and first to third drain regions DE1, DE2, DE3 may be arranged on the second interlayer insulating film ILD2 of each pixel PXL. The first to third active patterns ACT1, ACT2, ACT3, first to third source regions SE1, SE2, SE3, and first to third drain regions DE1, DE2, DE3 may be made of an oxide semiconductor. For example, the first to third active patterns ACT1, ACT2, ACT3, first to third source regions SE1, SE2, SE3, and first to third drain regions DE1, DE2, DE3 may be made of indium-gallium-zinc oxide (InGaZnO4). However, the materials of the first to third active patterns ACT1, ACT2, ACT3, the first to third source regions SE1, SE2, SE3, and the first to third drain regions DE1, DE2, DE3 are not limited to those in the above-described embodiment. A second gate insulating film GI2 may be provided on the first to third active patterns ACT1, ACT2, ACT3, the first to third source regions SE1, SE2, SE3, and the first to third drain regions DE1, DE2, DE3.

[0295] The first and second scan lines Si, Si+1 and the first to third gate electrodes GE1, GE2, and GE3 may be disposed on the second gate insulating film GI2 of each pixel PXL. The first and second scan lines Si, Si+1, and the first to third gate electrodes GE1, GE2, and GE3 may be a third conductive layer. The second gate electrode GE2 may be integral with the first scan line Si, and the third gate electrode GE3 may be integral with the second scan line Si+1. The first and second scan lines Si, Si+1, and the first to third gate electrodes GE1, GE2, and GE3 may include the same material as the emission control line Ei and the lower electrode LE, or may include one or more materials selected from the materials exemplified as the materials for the emission control line Ei and the lower electrode LE. In an embodiment of the present invention, the first and second scan lines Si, Si+1, and the first to third gate electrodes GE1, GE2, and GE3 may be formed of a multi-layer structure including a first layer made of titanium (Ti) and a second layer made of molybdenum (Mo). However, the materials of the first and second scan lines Si, Si+1 and the first to third gate electrodes GE1, GE2, GE3 are not limited to those in the above-described embodiment. A third interlayer insulating film ILD3 may be provided on the first and second scan lines Si, Si+1 and the first to third gate electrodes GE1, GE2, GE3.

[0296] The reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 may be disposed on the third interlayer insulating film ILD3 of each pixel PXL. The reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 may be a fourth conductive layer. The reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 may contain the same material as the light-emitting control line Ei and the lower electrode LE, or may contain one or more materials selected from the materials exemplified as the materials constituting the light-emitting control line Ei and the lower electrode LE. In one embodiment of the present invention, the reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 may be formed as a multi-layer film in which a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti) are stacked in this order. However, the materials of the reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 are not limited to those in the above-described embodiment. A first protective film PSV1 may be provided on the reference voltage line RFj and the first to seventh connection wires CNL1 to CNL7.

[0297] The data line DLj, the power line PL, and the bridge pattern BRP may be disposed on the first passivation film PSV1 of each pixel PXL. The data line DLj, the power line PL, and the bridge pattern BRP may be a fifth conductive layer. The data line DLj, the power line PL, and the bridge pattern BRP may include the same material as the emission control line Ei and the lower electrode LE, or may include one or more materials selected from the materials exemplified as the materials constituting the emission control line Ei and the lower electrode LE. In an embodiment of the present invention, the data line DLj, the power line PL, and the bridge pattern BRP may be formed as a multi-layer structure in which a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti) are sequentially stacked. However, the materials of the data line DLj, the power line PL, and the bridge pattern BRP are not limited to those of the above embodiment. A second passivation film PSV may be disposed on the data line DLj, the power line PL, and the bridge pattern BRP.

[0298] In one embodiment of the present invention, the power line PL may partially overlap the first transistor T1 in a plan view to cover a portion of the first transistor T1. By extending the power line PL to cover a portion of the first transistor T1, the power line PL can block vertical capacitive coupling formed between the data line DLj and the first gate electrode GE1 of the first transistor T1. This prevents crosstalk between the data line DLj and the first transistor T1, thereby reducing image quality defects caused by the crosstalk.

[0299] As described above, the capacitance of the storage capacitor Cst in each pixel PXL can be further ensured by the bottom electrode LE, the first conductive pattern BML1, the first gate electrode GE1, and the fourth connection line CNL4, which are overlapped with at least one insulating film sandwiched therebetween, thereby enabling each pixel PXL to be driven more stably.

[0300] Furthermore, as described above, by using each of the first conductive pattern BML1, the first transistor T1, and the fourth connection line CNL4 as an electrode of the storage capacitor Cst, it is possible to ensure sufficient space for forming the storage capacitor Cst within the narrow space of the pixel area PXA, thereby providing a display device that can easily achieve high resolution.

[0301] FIG. 14 is a plan view schematically showing one pixel according to yet another embodiment of the present invention, FIG. 15 is a cross-sectional view taken along line G-G' in FIG. 14, and FIG. 16 is a cross-sectional view taken along line H-H' in FIG. 14.

[0302] In FIG. 14, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0303] The pixels shown in FIGS. 14 to 16 may have a configuration substantially similar to that of the pixel shown in FIG. 11, except that a shielding member SDL is disposed between the data line DLj and the first transistor T1.

[0304] Therefore, to avoid redundant explanation, differences from the above-described embodiment will be mainly described in Figures 14 to 16. Portions not specifically described in the embodiment of Figures 14 to 16 are the same as those in the above-described embodiment, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0305] 1 to 3 and 14 to 16, a display device according to an embodiment of the present invention may include a substrate SUB, a wiring portion, and a pixel PXL.

[0306] Each pixel PXL may be provided in a pixel area PXA included in a display area DA of the substrate SUB.

[0307] In the pixel area PXA in which each pixel PXL is arranged, first and second scan lines Si, Si+1, a light emission control line Ei, a reference voltage line RFj, a data line DLj, and a power supply line PL may be arranged.

[0308] The first and second scan lines Si and Si+1 may be a third conductive layer provided on the second gate insulating film GI2, and the light-emitting control line Ei may be a first conductive layer provided on the first gate insulating film GI1. The reference voltage line RFj may be a fourth conductive layer provided on the third interlayer insulating film ILD3, and the data line DLj and the power supply line PL may be a fifth conductive layer provided on the first protective film PSV1.

[0309] Each pixel PXL may include a pixel circuit layer PCL having a pixel circuit PXC and a display element layer DPL having a light-emitting element OLED.

[0310] The pixel circuit layer PCL may include a buffer film BFL, a lower electrode LE, first to fourth transistors T1 to T4, and first to third conductive patterns BML1 to BML3. The pixel circuit layer PCL may also include an insulating film provided between components provided in each of the first to fourth transistors T1 to T4.

[0311] Of the first to fourth transistors T1 to T4, the first to third transistors T1 to T3 may be realized by oxide transistors, and the fourth transistor T4 may be realized by a polysilicon transistor.

[0312] In one embodiment of the present invention, a shielding member SDL may be disposed between the data line DLj and the first transistor T1, as shown in Fig. 14. The shielding member SDL may overlap at least a portion of the data line DLj when viewed in a plan view, but the present invention is not limited to this.

[0313] The shielding member SDL may be a fourth conductive layer provided on the third interlayer insulating film ILD3. The shielding member SDL may be provided in the same layer as the reference voltage line RFj and the first to seventh connection lines CNL1 to CNL7 described with reference to FIGS. 11 to 13 and may contain the same material.

[0314] The shielding member SDL may be connected to the fourth source region SE4 of the fourth transistor T4 via a 19th contact hole CH19 that passes through the buffer film BFL, the first gate insulating film GI1, the first and second interlayer insulating films ILD1 and ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in that order.

[0315] The fourth source region SE4 may be connected to the power line PL via the fourth contact hole CH4, the sixth connection line CNL6, and the seventeenth contact hole CH17. As a result, the shielding member SDL can be connected to the power line PL via the nineteenth contact hole CH19, the fourth source region SE4, the fourth contact hole CH4, the sixth connection line CNL6, and the seventeenth contact hole CH17. As a result, the voltage of the first driving power source ELVDD applied to the power line PL can be transmitted to the shielding member SDL.

[0316] In each pixel PXL, the first gate electrode GE1 of the first transistor T1, which is used as one electrode of the storage capacitor Cst, may be formed wide to ensure the capacitance of the storage capacitor Cst. If the area of the first gate electrode GE1 is large, the distance between the first gate electrode GE1 and the data line DLj may become short. In this case, vertical capacitive coupling (e.g., parasitic capacitance) may be formed between the first gate electrode GE1 and the data line DLj, and crosstalk may occur, in which the gate voltage (or gate signal) applied to the first gate electrode GE1 changes depending on the change in the data voltage (or data signal) applied to the data line DLj.

[0317] In an embodiment of the present invention, a shielding member SDL may be disposed between the data line DLj and a portion of the first transistor T1, for example, the first gate electrode GE1, to minimize vertical capacitive coupling between the data line DLj and the first gate electrode GE1, thereby preventing interference between the data voltage (or data signal) transmitted through the data line DLj and the gate voltage (or gate signal) applied to the first gate electrode GE1 of the first transistor T1.

[0318] FIG. 17 is a plan view schematically showing one pixel according to yet another embodiment of the present invention.

[0319] In FIG. 17, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0320] The pixel shown in Fig. 17 may have a configuration substantially similar to that of the pixel shown in Fig. 14, except for the position of the shielding member SDL. Therefore, to avoid redundant explanation in Fig. 17, the following description will focus on differences from the embodiment described above. Portions of the embodiment in Fig. 17 that are not particularly described are similar to the example described above, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0321] 1 to 3 and 17, each pixel PXL may be provided in a pixel area PXA included in a display area DA of a substrate SUB.

[0322] The pixel area PXA may include scanning lines Si, Si+1, a light emission control line Ei, a reference voltage line RFj, a data line DLj, and a power supply line PL connected to the pixel circuit PXC.

[0323] In one embodiment of the present invention, a shielding member SDL may be disposed between the data line DLj and a portion of the pixel circuit PXC, for example, the first transistor T1. The shielding member SDL may be disposed between the data line DLj and the first gate electrode GE1 of the first transistor T1.

[0324] In one embodiment of the present invention, the shielding member SDL may be provided integrally with the first connection line CNL1 and connected to the first connection line CNL1. When the shielding member SDL is provided integrally with the first connection line CNL1, the shielding member SDL can be regarded as one region of the first connection line CNL1.

[0325] The first connection wiring CNL1 may be connected to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 via a fourteenth contact hole CH14 that passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, and the third interlayer insulating film ILD3 in this order. This allows a voltage applied to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 to be transmitted to the first connection wiring CNL1. As described above, the shielding member SDL is integral with the first connection wiring CNL1, so that a voltage applied to the first source region SE1 of the first transistor T1 and the third source region SE3 of the third transistor T3 can be transmitted to the shielding member SDL.

[0326] When the shielding member SDL is disposed between the data line DLj and the first gate electrode GE1 of the first transistor T1, vertical capacitive coupling between the data line DLj and the first gate electrode GE1 can be minimized.

[0327] Figure 18 is a plan view schematically showing a pixel according to yet another embodiment of the present invention, Figure 19 is a cross-sectional view along line II' in Figure 18, and Figure 20 is a cross-sectional view along line J-J' in Figure 18.

[0328] In FIG. 18, for convenience, the light emitting element OLED connected to the first and third transistors T1 and T3 is omitted.

[0329] The pixels shown in Figures 18 to 20 may have a configuration substantially similar to that of the pixel shown in Figure 11, except that the positions of the data lines DLj and power supply lines PL are changed. Therefore, to avoid redundant explanation in Figures 18 to 20, the following description will focus on differences from the above-mentioned embodiment. Parts of the embodiment in Figures 18 to 20 that are not particularly described are similar to the above-mentioned embodiment, and the same numbers indicate the same components, and similar numbers indicate similar components.

[0330] 1 to 3 and 18 to 20, each pixel PXL may be provided in a pixel area PXA included in a display area DA of a substrate SUB.

[0331] The pixel region PXA may be arranged with scan lines Si, Si+1, a light emission control line Ei, a reference voltage line RFj, a data line DLj, and a power supply line PL. The pixel region PXA may also be arranged with first to fourth transistors T1 to T4, first to third conductive patterns BML1 to BML3, a bottom electrode LE, and first to seventh connecting wires CNL1 to CNL7.

[0332] In a plan view, the reference voltage lines RFj, the data lines DLj, and the power supply lines PL may extend along the second direction DR2 and be arranged in this order along the first direction DR1. In one embodiment of the present invention, the reference voltage lines RFj may be provided in a different layer from the data lines DLj and the power supply lines PL. For example, the reference voltage lines RFj may be a fourth conductive layer provided on the third interlayer insulating film ILD3, and the data lines DLj and the power supply lines PL may be a fifth conductive layer provided on the first protective film PSV1.

[0333] When viewed in a plane, the reference voltage line RFj, the power supply line PL, and the data line DLj may be spaced apart from one another. The power supply line PL may be located between the reference voltage line RFj and the data line DLj. In one embodiment of the present invention, the power supply line PL may overlap a portion of the first transistor T1, for example, the first gate electrode GE1, to cover the first gate electrode GE1.

[0334] In the pixel area PXA in which each pixel PXL is provided, when the reference voltage line RFj, the power supply line PL, and the data line DLj are arranged in that order along the first direction DR1, the distance between the data line DLj and some components of the pixel circuit PXC, for example, the first transistor T1, can become even greater.

[0335] When the distance between the data line DLj and the first transistor T1 becomes greater and the first transistor T1 is covered by the power line PL, the effect of changes in the data voltage (or data signal) applied to the data line DLj on the gate voltage (or gate signal) applied to the first transistor T1 is reduced, thereby blocking vertical cap coupling (e.g., parasitic capacitor) formed between the data line DLj and the first transistor T1 and minimizing image quality defects due to crosstalk.

[0336] Although the present invention has been described above with reference to preferred embodiments, it will be understood that those skilled in the art or those with ordinary knowledge in the art can modify and change the present invention in various ways without departing from the spirit and technical scope of the present invention as set forth in the appended claims.

[0337] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims

1. a plurality of pixels provided on a substrate, each including a light-emitting element; a first scanning line provided for each pixel, for applying an i-th scanning signal (i is a natural number), and a second scanning line for applying an i+1-th scanning signal; a data line provided in each of the pixels for applying a data signal; a power supply line provided in each of the pixels for applying a driving power supply; a reference voltage line provided in each of the pixels for applying a reference voltage; a first transistor for controlling a current of the light emitting element; a second transistor connected between the data line and the first gate electrode of the first transistor and turned on by the i-th scanning signal; a third transistor connected between the reference voltage line and the first electrode of the first transistor and turned on by the (i+1)th scanning signal; a fourth transistor connected between the power supply line and the second electrode of the first transistor and turned off when a light emission control signal is supplied to a light emission control line; the fourth transistor is a transistor of a type different from the first to third transistors, a buffer film and a gate insulating film provided in this order on the substrate; The display device further comprises first to fourth insulating films provided in this order on the gate insulating film.

2. 2. The display device according to claim 1, wherein the first to third transistors are formed of oxide transistors, and the fourth transistor is formed of a polysilicon transistor.

3. the first insulating film includes first to third conductive patterns spaced apart from one another; 2. The display device according to claim 1, wherein the first conductive pattern overlaps the first transistor when viewed in a plane, the second conductive pattern overlaps the second transistor when viewed in a plane, and the third conductive pattern overlaps the third transistor when viewed in a plane.

4. a first gate electrode of the first transistor, a second gate electrode of the second transistor, a third gate electrode of the third transistor, and the first and second scanning lines are provided on the third insulating film; a fourth gate electrode of the fourth transistor is provided on the gate insulating film; a gate electrode of the second transistor electrically connected to the second conductive pattern; 4. The display device according to claim 3, wherein a gate electrode of the third transistor is electrically connected to the third conductive pattern.

5. The first transistor is a first active pattern provided on the second insulating film; the first gate electrode provided on the third insulating film; the first electrode and the second electrode respectively contacting both ends of the first active pattern, The display device of claim 4 , wherein the first conductive pattern is electrically connected to one of the first and second electrodes of the first transistor.

6. a storage capacitor including a lower electrode disposed on the first insulating film and an upper electrode overlapping the lower electrode with the second and third insulating films interposed therebetween; The lower electrode is integral with the first conductive pattern, and the upper electrode is 6. The display device according to claim 5, wherein the light emitting element is provided integrally with the light receiving electrode.

7. 6. The display device of claim 5, further comprising an opening in which a portion of the third insulating film is removed between the first gate electrode of the first transistor and the first conductive pattern to expose a portion of the second insulating film.

8. 8. The display device according to claim 7, wherein the opening overlaps the first gate electrode of the first transistor and the first conductive pattern when viewed in plan.

9. 6. The display device according to claim 5, wherein the reference voltage line, the data line, and the power supply line are provided on the fourth insulating film.

10. 10. The display device according to claim 9, further comprising a connection wiring provided on the fourth insulating film, the connection wiring electrically connecting the third transistor and the light emitting element.

11. The semiconductor device further includes a protective film provided on the connection wiring, The light-emitting element is a first electrode provided on the protective film and electrically connected to the connection wiring via a contact hole that penetrates the protective film; a light-emitting layer provided on the first electrode; 11. The display device according to claim 10, further comprising: a second electrode provided on the light-emitting layer.

Images