Electronics and Drive Systems

Abstract

To provide an electronic circuit capable of suppressing ringing of a current flowing when a switching element is turned on.SOLUTION: An electronic circuit has a drive circuit that supplies a drive current to a control terminal of a first switching element and increases the drive current in accordance with first time at which a current flowing through a second switching element connected to a first terminal or a second terminal of the first switching element becomes zero.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to electronic circuits and drive systems. [Background technology]

[0002] In the field of power electronics, semiconductor switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are widely used. In circuits that include these switching elements, power loss can be reduced by increasing the speed of the switching operation of the elements. However, increasing the speed of the switching operation of the elements can cause ringing in the current that flows, for example, when the element is turned on. This current ringing not only causes noise but also accelerates the degradation of the elements.

[0003] There is a technology that uses an optimization method based on a simulated annealing algorithm to find a drive current waveform that reduces ringing of the current flowing through a switching element, power loss, etc. However, this technology does not guarantee that the found drive current waveform is a globally optimal solution, and it is also difficult to interpret its qualitative meaning. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] “General-Purpose Clocked Gate Driver IC with Programmable 63-Level Drivability to Optimize Overshoot and Energy Loss in Switching by a Simulated Annealing Algorithm”, Koutarou Miyazaki, et. al, IEEE Trans. on Industry Application, Vol. 53, No 3, May / June / 2017 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure is made to solve the above-mentioned problems, and aims to provide an electronic circuit that can suppress ringing of a current that flows when a switching element is turned on. [Means for solving the problem]

[0006] In order to solve the above problem, the present disclosure provides a drive circuit that supplies a drive current to a control terminal of a first switching element and increases the drive current according to a first time when the current flowing through a second switching element connected to the first terminal or the second terminal of the first switching element becomes zero.

[0007] The electronic circuit according to the present disclosure also includes a drive circuit that supplies a drive current to a control terminal of a first switching element and reduces the drive current of the first switching element during a second period between a first time when the current flowing through a second switching element connected to the first terminal or the second terminal of the first switching element becomes zero and a second time when the current flowing through the first switching element begins to increase. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a motor control system according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing the internal configuration of a control device. [Figure 3] 1 is an equivalent circuit when the first switching element is turned on. [Figure 4] 6 is a timing chart illustrating the operation when the first switching element is turned on. [Figure 5] Equivalent circuit when the resonant loop in Figure 3 is formed. [Figure 6A] One of the divided equivalent circuits of the equivalent circuit in Figure 5, using the principle of superposition. [Figure 6B] The other equivalent circuit obtained by dividing the equivalent circuit in Figure 5 using the principle of superposition. [Figure 7] 4 is a timing chart illustrating a first method for suppressing ringing. [Figure 8] FIG. 4 is a diagram illustrating a first method for suppressing ringing. [Figure 9] 10 is a timing chart illustrating a second method for suppressing ringing. [Figure 10] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 11] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 12] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 13] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 14] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 15] 6 is a timing chart illustrating a modification of the first method for suppressing ringing. [Figure 16A] FIG. 2 is a diagram illustrating the definition of "step-like" in the present disclosure. [Figure 16B] FIG. 2 is a diagram illustrating the definition of "lamp-shaped" in the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, identical or corresponding elements are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0010] (Embodiment 1) 1 is a diagram illustrating a configuration of a motor control system 100 according to a first embodiment of the present disclosure. The motor control system 100 includes a three-phase AC motor 1 as a load, a DC power supply Vdc, switching elements 21-26 that configure a three-phase inverter circuit 20, and drive circuits 10a-10f that drive the switching elements 21-26, respectively. The motor control system 100 also includes a control circuit 30 that controls the drive circuits 10a-10f, and an analog-to-digital (A / D) converter 31.

[0011] The switching elements 21 and 22 are N-channel MOSFETs, each having a drain terminal as a first terminal, a source terminal as a second terminal, and a gate terminal as a control terminal. The switching elements 21 and 22 form a U-phase arm pair of the inverter circuit 20. The drive circuit 10a controls the gate current serving as the drive current for the switching element 21, thereby controlling the switching operation, i.e., turn-on and turn-off, of the switching element 21. The drive circuit 10b controls the gate current for the switching element 22, thereby controlling the switching operation of the switching element 22.

[0012] Similarly, switching element 23 and switching element 24 are N-channel MOSFETs. Switching element 23 and switching element 24 form a V-phase arm pair of inverter circuit 20. Drive circuit 10c controls the gate current of switching element 23 to control the switching operation of switching element 23. Drive circuit 10d controls the gate current of switching element 24 to control the switching operation of switching element 24.

[0013] Similarly, switching element 25 and switching element 26 are N-channel MOSFETs. Switching element 25 and switching element 26 form a W-phase arm pair of inverter circuit 20. Drive circuit 10e controls the gate current of switching element 25 to control the switching operation of switching element 25. Drive circuit 10f controls the gate current of switching element 26 to control the switching operation of switching element 26.

[0014] The A / D converter 31 converts the current values of the U, V, and W phases of the motor 1 into digital signals and outputs them to the control circuit 30. Based on the current values of each phase of the motor 1 received from the A / D converter 31, the control circuit 30 provides waveform information of the gate currents serving as drive currents for the switching elements 21-26 to the drive circuits 10a-10f of the switching elements 21-26, respectively.

[0015] FIG. 2 is a diagram showing the internal configuration of the control circuit 30. The control circuit 30 includes a detection circuit 30a, a memory circuit 30b including multiple lookup tables (LUT_1 to LUT_N), and a selection circuit 30c. The detection circuit 30a detects the operating states of the switching elements 21 to 26 based on the current values of the U, V, and W phases of the motor 1 received from an A / D converter 31. Alternatively, the detection circuit 30a may detect the operating states of the switching elements 21 to 26 based on temperature information received from a temperature sensor (not shown) built into the motor 1. Furthermore, the detection circuit 30a may detect the operating states of the switching elements 21 to 26 based on signals received from a control microcomputer (not shown) in addition to or instead of the A / D converter 31.

[0016] Alternatively, the current value of each phase of the motor 1 may be detected from the voltage of the parasitic inductance at the source terminal of each of the switching elements 21, 23, and 25, and the operating states of the switching elements 21 to 26 may be detected based on this. Alternatively, a current detection transformer may be provided at the drain terminal of each of the switching elements 21, 23, and 25 to detect the current value of each phase of the motor 1, and the operating states of the switching elements 21 to 26 may be detected based on this. In other words, the method of detecting the operating states of the switching elements 21 to 26 shown in Figure 1 is merely one example, and the operating states of the switching elements 21 to 26 can also be detected by various other methods.

[0017] Each lookup table in the memory circuit 30b stores waveform information of the gate currents of the switching elements 21 to 26. The selection circuit 30c selects one of the pieces of waveform information of the gate currents from the memory circuit 30b based on the operating states of the switching elements 21 to 26 detected by the detection circuit 30a. The waveform information of the gate currents selected by the selection circuit 30c is provided to the drive circuits 10a to 10f of the switching elements 21 to 26, respectively. Alternatively, each lookup table in the memory circuit 30b may be provided inside the drive circuits 10a to 10e.

[0018] The present disclosure aims to suppress ringing of the current that flows when a switching element is turned on. In the following explanation, we will focus on switching element 21 and explain in detail the operation of drive circuit 10a when turning on switching element 21. However, the following explanation also applies to the other switching elements 22 to 26 and drive circuits 10b to 10f.

[0019] Hereinafter, switching element 21 will be referred to as a "first switching element." Furthermore, switching element 22, which is paired with first switching element 21 to form a U-phase arm pair, will be referred to as a "second switching element."

[0020] Fig. 3 is an equivalent circuit diagram of the first switching element 21 in Fig. 1 when it is turned on. When the first switching element 21 is turned on in Fig. 1, the second switching element 22 is in the off state. In Fig. 3, the second switching element 22 in the off state is represented by a diode Dio and a parasitic capacitor Cdio.

[0021] The inductor Lload represents the inductance of the load, that is, the motor 1. The inductor Ld represents the parasitic inductance of the wiring connecting the drain terminal of the first switching element 21 and the drain terminal of the second switching element 22.

[0022] The first switching element 21 has a parasitic capacitor Cgs between the gate and source, a parasitic capacitor Cgd between the gate and drain, and a parasitic capacitor Cds between the drain and source. A gate current Ig is output from the drive circuit 10a as a drive current for the first switching element 21.

[0023] The operation of the first switching element 21 driven by the drive circuit 10a when it is turned on will be explained below based on the equivalent circuit in Figure 3. Please also refer to the time chart in Figure 4. In the following time charts including Figure 4, the drain voltage is indicated by a dashed line.

[0024] 4, the gate current Ig output from the drive circuit 10a is 0, and the gate voltage of the first switching element 21 is also 0. Therefore, the first switching element 21 is in the off state, the drain current Id is 0, and the drain voltage Vd, indicated by the dashed-dotted line in the figure, is equal to the voltage Vdio on the anode side of the diode Dio.

[0025] At time t1, the drive circuit 10a increases the gate current Ig in a stepwise manner to Ig0, which starts charging the parasitic capacitor Cgs between the gate and source of the first switching element 21, causing the gate voltage of the first switching element 21 to rise in a ramp-like manner.

[0026] At time t2, when the gate voltage of the first switching element 21 exceeds the threshold voltage, a channel is formed and the drain current Id begins to flow. The drain current Id increases as the gate voltage rises. At this time, the diode Dio is in the on state, and the voltage Vdio on its anode side remains constant. Meanwhile, as the drain current Id flows, a voltage is generated across the inductor Ld, and the drain voltage Vd decreases.

[0027] At time t3, when the drain current Id becomes equal to the DC current Idc flowing through the inductor Lload, the diode Dio turns off and the anode voltage Vdio drops. At this time, a resonant loop like the one shown in Figure 3 is formed, causing ringing in the drain current Id. The equivalent circuit when the resonant loop of Figure 3 is formed is shown in Figure 5.

[0028] In the equivalent circuit of Fig. 5, the current source Ig0 on the left side represents the gate current at time t3. The current Id(t) is the drain current of the first switching element 21. The voltage Vo is the voltage across the inductor Ld at the start of resonance at time t3, and is equal to the difference between the diode voltage Vdio at time t3 in Fig. 3 and the drain voltage Vd of the first switching element 21. Furthermore, the constant current source Idc on the upper side of Fig. 5 represents the current charging the inductor Lload in Fig. 3, and the constant current source Ich on the lower side represents the channel current of the first switching element 21.

[0029] In the equivalent circuit of FIG. 5, the channel current Ich of the first switching element 21 can be written as follows using the transconductance gm of the first switching element 21, the voltage Vg of the gate-source parasitic capacitor Cgs, and the current Idc:

[0030]

number

[0031] The above equation can also be written as follows, using the fact that the voltage of the parasitic capacitor Cgs is Vg=(Ig0 / Cgs)t:

[0032]

number

[0033] Let us consider obtaining the time waveform of the drain current Id(t) when the first switching element 21 is turned on from the equivalent circuit of Fig. 5. Here, using the principle of superposition, we will consider the equivalent circuit of Fig. 5 divided into the equivalent circuit of Fig. 6A and the equivalent circuit of Fig. 6B.

[0034] First, for the equivalent circuit in Figure 6A, the equation for the drain current Id(t) is given by the following equation (3). Here, we use the fact that the voltage across the inductor Ld is equal to the differential value of the current Id(t) flowing through the inductor Ld multiplied by the inductance Ld. Furthermore, equations (4) and (5) are the initial conditions for equation (3).

[0035]

number

[0036] The solution to the above equation is given by the following equation (6).

[0037]

number

[0038] In the above equation (6), the first term on the right side represents the resonant current determined by the voltage Vo across the inductor Ld at the start of resonance, and its amplitude is proportional to the voltage Vo across the inductor Ld at the start of resonance and inversely proportional to the angular frequency ω and the inductance Ld. The second term on the right side represents the DC current flowing through the inductor Ld, which does not contribute to resonance.

[0039] Next, for the equivalent circuit of Fig. 6B, the equation for the drain current Id(t) is given by the following equation (9): Furthermore, equations (10) and (11) are the initial conditions for equation (9).

[0040]

number

[0041] The solution to the above equation is given by the following equation (12), where ω and Ctot are the same as in equations (7) and (8).

[0042]

number

[0043] In the above equation (12), the first term on the right side represents the resonant current generated by the gate current Ig0 at the start of resonance, and its phase is shifted by 180 degrees from the phase of the first term on the right side of the above equation (6). Also, the second term on the right side represents the current that does not contribute to resonance and flows through the parasitic capacitor Cdio.

[0044] By adding together equation (6), which is the solution to the equivalent circuit of Figure 6A, and equation (12), which is the solution to the equivalent circuit of Figure 6B, the solution to the equivalent circuit of Figure 5, i.e., the time waveform of the drain current Id(t) when the first switching element 21 is turned on, can be obtained.

[0045]

number

[0046] Observing the right-hand side of the above equation (13), it can be seen that the ringing of the drain current Id(t) that occurs when the first switching element 21 is turned on is caused by the resonant current represented by the second and third terms on the right-hand side. In particular, the second term on the right-hand side is a resonant current determined by the voltage Vo across the inductor Ld at the start of resonance, and its amplitude is proportional to the voltage Vo across the inductor Ld at the start of resonance and inversely proportional to the angular frequency ω and the inductance Ld.

[0047] Therefore, a first method for suppressing the ringing of the drain current Id(t) that occurs when the first switching element 21 is turned on is to reduce the voltage Vo across the inductor Ld at the start of resonance at time t3 in FIG. 4.

[0048] 7, the drive circuit 10a according to the first embodiment reduces the gate current Ig in a stepwise manner immediately before the time t3 at which resonance starts, thereby reducing the rate of increase of the drain current Id of the first switching element 21 and the rate of change of the current flowing through the inductor Ld, thereby reducing the voltage Vo across the inductor Ld at the start of resonance at the time t3. This reduces the amplitude of the resonant current generated when the first switching element 21 is turned on.

[0049] In the above, it was stated that the gate current Ig is reduced in a stepwise manner "just before" the time t3 when resonance begins. However, more generally, the gate current Ig can be reduced in the period between the first time (t3) when the current flowing through the second switching element 22 becomes zero and a resonance loop is formed, and the second time (t2) when the drain current Id of the first switching element 21 begins to increase.

[0050] Furthermore, the greater the gate current Ig is reduced, the more the amplitude of the resonant current is reduced, but the greater the loss during switching operation. Therefore, the target value for reducing the gate current Ig may be determined as a current value that reduces the experimentally observed noise peak value due to ringing in the drain current Id by a desired amount. Specifically, as described above, the amplitude of the resonant current in the second term on the right side of Equation (13) is proportional to the voltage Vo across the parasitic inductor Ld at the first time (t3) when resonance begins. As shown in FIG. 8, to reduce the noise peak value by, for example, 0.45 dB, the voltage Vo is reduced by 0.45 dB. When the voltage Vo is reduced by 0.45 dB, the true value (volts) of the voltage Vo is reduced by approximately 5 percent compared to the voltage Vi when the gate current Ig is not reduced, as shown in FIG. 7.

[0051] Therefore, the target value for reducing the gate current Ig is, for example, a value such that the voltage Vo across the parasitic inductance Ld at the first time (t3) is reduced by 5 percent compared to the case (Vi) in which the gate current Ig is not reduced.

[0052] Next, comparing the second and third terms on the right-hand side of the above equation (13), they are out of phase with each other by 180 degrees. Therefore, a second method for suppressing the ringing of the drain current Id(t) that occurs when the first switching element 21 is turned on can be to increase the gate current Ig in a stepwise manner at the start of resonance at time t3 in Fig. 4, thereby making the amplitude of the second term on the right-hand side equal to the amplitude of the third term on the right-hand side, thereby canceling them out.

[0053] To achieve this, the drive circuit 10a according to the first embodiment increases the gate current Ig in a stepwise manner at time t3 when resonance starts, as shown in Fig. 9. The target value Igsor of the gate current at this time is determined to satisfy the following equation (14) so that the amplitudes of the second and third terms on the right side of equation (13) are equal.

[0054]

number

[0055] When the above equation is solved for the target value Igsor, the following equation (15) is obtained.

[0056]

number

[0057] In this way, the resonant current generated when the first switching element 21 is turned on is canceled out. It is most preferable that the timing for increasing the gate current Ig stepwise coincides exactly with time t3, but a slight error around time t3 is acceptable. Generally, a sufficient effect can be expected if the gate current Ig can be increased to the target value Igsor within a specific period before or after the first time (t3), which is the time when the current flowing through the second switching element 22 becomes zero and a resonant loop is formed, and the period is, for example, 0.25 times the resonant frequency period T=2π / ω or less.

[0058] As described above, the switching element drive circuit 10a according to the first embodiment increases the gate current Ig of the first switching element 21 in accordance with the first time (t3) at which the current flowing through the second switching element 22 connected to the drain terminal of the first switching element 21 becomes zero.

[0059] Specifically, the drive circuit 10a increases the gate current Ig of the first switching element 21 during a first period before or after a first time point (t3). The first period is preferably a period equal to or less than 0.25 times the period T of the resonant frequency, which is calculated from the angular frequency ω determined by the above equations (7) and (8).

[0060] Due to the above-described features, in the switching element drive circuit 10a according to the first embodiment, the resonant current generated when the first switching element 21 is turned on is cancelled out, thereby suppressing ringing of the drain current Id.

[0061] Preferably, in the drive circuit 10a, the gate current Ig of the first switching element 21 is increased stepwise during the first period, and the target value Igsor is determined by the above equation (15). However, even if it is not strictly equal to equation (15), a sufficient effect can be expected as long as it is within a range of about 0.25 to 1.25 times equation (15).

[0062] Furthermore, the switching element drive circuit 10a according to the first embodiment reduces the gate current Ig of the first switching element 21 during a second period between a first time (t3) when the current flowing through the second switching element 22 connected to the drain terminal of the first switching element 21 becomes zero and a second time (t2) when the drain current Id of the first switching element 21 starts to increase. This reduces the amplitude of the resonant current generated when the first switching element 21 is turned on, thereby further suppressing ringing in the drain current Id.

[0063] Preferably, in the drive circuit 10a, during the second period, the gate current Ig of the first switching element 21 is reduced in a stepwise manner, and the target value is, for example, a value such that the voltage Vo across the parasitic inductance Ld at the first time point (t3) is reduced by a predetermined percentage (for example, 5 percent) compared to the case (Vi) in which the gate current Ig is not reduced.

[0064] In the second period, the gate current Ig of the first switching element 21 may be decreased in steps in multiple steps, as shown in FIG. 10. Alternatively, the gate current Ig of the first switching element 21 may be increased in steps at least once during the process of decreasing the gate current Ig in steps, as shown in FIG. 11. The value of the gate current Ig after the increase may be greater than the value at the start of the second period. By providing multiple steps of decrease and increase in this way, the timing of increasing the gate current Ig at the first time (t3) can be finely adjusted.

[0065] Alternatively, during the second period, as shown in FIG. 12, the gate current Ig of the first switching element 21 may be decreased in a ramp-like manner, and the gate current Ig may be kept constant at the first time (t3). This allows the voltage Vo across the parasitic inductor Ld to be almost zero at the first time (t3). As a result, the amplitude of the resonant current can be significantly reduced. While the waveform of the drain current Id(t) that flows when the gate current Ig is decreased in a ramp-like manner in this manner is strictly different from the waveform expressed by equation (13), simulation analysis confirmed this behavior. Therefore, by decreasing the gate current Ig in a ramp-like manner, ringing of the drain current Id can be suppressed. Regarding the target value for decreasing the gate current Ig, the same discussion as in the second method above applies.

[0066] 13, the gate current Ig may be increased in a ramp-like manner after the first time point (t3) and then set to a constant value. Simulations have confirmed that if the gate current Ig is increased in a ramp-like manner instead of a step-like manner after the first time point (t3), the resonant current corresponding to the third term on the right side of the above equation (13) will not be generated. Therefore, if the amplitude of the resonant current is sufficiently reduced by decreasing the gate current Ig in a ramp-like manner during the second period, it is effective to increase the gate current Ig in a ramp-like manner instead of a step-like manner after the first time point (t3).

[0067] 14, the gate current Ig of the first switching element 21 may be decreased in a ramp-like manner in multiple steps during the second period. Also, as shown in Fig. 15, the gate current Ig of the first switching element 21 may be increased in a ramp-like manner at least once during the process of decreasing the gate current Ig in a ramp-like manner during the second period. The value of the gate current Ig after the increase may be larger than the value at the start of the second period. (Variation) In the first embodiment described above, the three-phase inverter circuit 20 is configured by the switching elements 21 to 26. Therefore, the first switching element and the second switching element are both N-channel MOSFETs. Instead, for example, when configuring a converter circuit, the first switching element is an N-channel MOSFET and the second switching element is a diode.

[0068] Furthermore, the switching elements 21 to 26 are not limited to MOSFETs. For example, the switching elements 21 to 26 may be IGBTs. In this case, the switching elements 21 to 26 are N-channel IGBTs, with the first terminals being collector terminals, the second terminals being emitter terminals, and the control terminals being gate terminals.

[0069] Furthermore, the switching elements 21 to 26 may be BJTs (Bipolar Junction Transistors). In this case, the switching elements 21 to 26 are npn-type BJTs, with the first terminals being collector terminals, the second terminals being emitter terminals, and the control terminals being base terminals.

[0070] As the semiconductors that form the switching elements 21 to 26, various materials such as Si (Silicon), SiC (Silicon Carbide), or GaN (Gallium Nitride) can be used.

[0071] Finally, the definitions of "step-like" and "ramp-like" in this disclosure will be explained. As shown in FIG. 16A, a step-like waveform is a waveform that includes a period in which the current slope is zero in the section between time 1 and time 2 when the current changes. As shown in FIG. 16B, a ramp-like waveform is a waveform that does not include a period in which the current slope is zero in the section between time 1 and time 2 when the current changes. A step-like waveform is a waveform in which the period in which the current slope is zero in the section between time 1 and time 2 when the current changes is equal to or longer than a predetermined period. A ramp-like waveform may be a waveform in which the period in which the current slope is zero in the section between time 1 and time 2 when the current changes is shorter than a predetermined period. Furthermore, a current slope of zero does not necessarily mean a slope that is strictly zero, but also includes a slope within a range that can be considered to be zero in terms of driving a switching element.

[0072] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the disclosure. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, and combinations can be made without departing from the spirit of the disclosure. These embodiments and modifications thereof are included in the scope and spirit of the disclosure, as well as in the disclosure described in the claims and their equivalents. [Explanation of symbols]

[0073] 1 motor 10a Drive circuit 10b Drive circuit 10c Drive circuit 10d Drive circuit 10e Drive circuit 10f drive circuit 20 Inverter circuit 21 Switching element (first switching element) 22 switching element (second switching element) 24 Switching element 25 Switching element 26 Switching element 27 Switching element 30 Control circuit 30a Detection circuit 30b Memory circuit 30c Selection circuit 31 A / D converter Cdio Parasitic capacitor of the second switching element Cds is the drain-source parasitic capacitor Cgd Parasitic capacitor between gate and drain Cgs Gate-source parasitic capacitor Dio Diode gm transconductance Ich channel current Idc DC current flowing through inductor Lload Ig Gate current (drive current) Id Drain current Ld: Parasitic inductance of the wiring connecting the first switching element and the second switching element Lload Motor inductance Vd Drain voltage Vdc DC power supply Vdio Voltage on the anode side of the diode Vg Voltage of the parasitic capacitor Cgs Vo is the voltage across the parasitic inductor Ld at the start of resonance

Claims

1. a drive circuit for supplying a drive current to a control terminal of a first switching element connected in series to a second switching element at a first terminal or a second terminal; When the second switching element is in an off state, the first switching element is turned on to form a resonant loop, The drive circuit increases the drive current in response to a first time when the current flowing through the second switching element becomes zero and the resonant loop is formed.

2. the drive circuit increases a drive current of the first switching element during a first period before or after the first time point, with the first time point being used as a reference; 2. The electronic circuit according to claim 1, wherein the first period is determined based on a parasitic capacitance of the first switching element, a parasitic capacitance of the second switching element, and a parasitic inductance of a wiring connecting the first switching element and the second switching element.

3. the drive circuit increases the drive current of the first switching element in a stepwise manner during the first period; 3. The electronic circuit according to claim 2, wherein the target value of the drive current is determined based on a drain parasitic capacitance of the first switching element, a gate parasitic capacitance of the first switching element, a transconductance of the first switching element, the parasitic inductance of the wiring connecting the first switching element and the second switching element, and a voltage across the parasitic inductance at the first time.

4. 4. The electronic circuit according to claim 1, wherein the drive circuit reduces the drive current of the first switching element in a second period between the first time point and a second time point at which an increase in the current flowing through the first switching element begins.

5. the drive circuit reduces the drive current of the first switching element in a stepwise manner during the second period; 5. The electronic circuit according to claim 4, wherein the target value of the drive current is a value that reduces a voltage across a parasitic inductance of a wiring that connects the first switching element and the second switching element at the first time by a predetermined percentage compared to a case in which the drive current is not reduced.

6. The electronic circuit according to claim 5 , wherein the drive circuit reduces the drive current of the first switching element in a stepwise manner in a plurality of times during the second period.

7. 7. The electronic circuit according to claim 5, wherein the drive circuit increases the drive current of the first switching element in a stepwise manner at least once during the second period while decreasing the drive current in a stepwise manner.

8. A driving circuit for supplying a driving current to a control terminal of a first switching element connected in series to a second switching element at a first terminal or a second terminal, When the second switching element is in an off state, the first switching element is turned on to form a resonant loop, The drive circuit reduces the drive current of the first switching element during a second period between a first time when the current flowing through the second switching element becomes zero and the resonant loop is formed, and a second time when the current flowing through the first switching element begins to increase.

9. the drive circuit reduces the drive current of the first switching element in a stepwise manner during the second period; 9. The electronic circuit according to claim 8, wherein the target value of the drive current is a value that causes a voltage across a parasitic inductance of a wiring connecting the first switching element and the second switching element at the first time to decrease by a predetermined percentage compared to a case in which the drive current is not reduced.

10. The electronic circuit according to claim 8 , wherein the drive circuit reduces the drive current of the first switching element in a stepwise manner in a plurality of times during the second period.

11. 11. The electronic circuit according to claim 9, wherein the drive circuit increases the drive current of the first switching element in a stepwise manner at least once during the second period while decreasing the drive current in a stepwise manner.

12. 9. The electronic circuit according to claim 8, wherein the drive circuit reduces the drive current of the first switching element in a ramp-like manner during the second period, and sets the drive current to a constant value at the first time.

13. 13. The electronic circuit according to claim 12, wherein the target value of the drive current is a value that causes a voltage across a parasitic inductance of a wiring that connects the first switching element and the second switching element at the first time to decrease by a predetermined percentage compared to a case in which the drive current is not reduced.

14. The electronic circuit of claim 13 , wherein the drive circuit increases the drive current in a ramp manner after the first time point and then makes the drive current a constant value.

15. 15. The electronic circuit according to claim 12, wherein the drive circuit reduces the drive current of the first switching element in a ramp-like manner in a plurality of steps during the second period.

16. The electronic circuit according to any one of claims 12 to 15, wherein the drive circuit increases the drive current of the first switching element in a ramp-like manner at least once during the second period while decreasing the drive current of the first switching element in a ramp-like manner.

17. An electronic circuit according to any one of claims 1 to 16; a control circuit that provides waveform information of the drive current to the drive circuit of the electronic circuit; Equipped with The drive circuit generates the drive current based on the waveform information.

18. The control circuit a detection circuit that detects an operating state of the first switching element; a storage device that stores a plurality of pieces of waveform information of the driving current; a selection circuit that selects one of the waveform information of the driving current from the storage device based on the operating state of the first switching element detected by the detection circuit; 20. The drive system of claim 17, comprising:

19. 20. The drive system of claim 18, including the first switching element.

20. The drive system according to claim 18 , further comprising a power conversion circuit including an arm pair formed by the first switching element and the second switching element.

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