Mobile device, envelope tracking system, and method for amplifying radio frequency signals in a mobile device

Abstract

To provide an envelope tracking system in which changes in power amplifier supply voltage arising from envelope tracking are compensated.SOLUTION: An envelope tracking system includes a power amplifier 250 that receives power from a power amplifier supply voltage VPA and amplifies a radio frequency (RF) signal RFIN. The power amplifier includes: an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal; a Wilson current minor 232; and a field-effect transistor NFET 231 for amplifying the RF signal. The Wilson current mirror includes: an input that receives a reference current IREF from a reference current source 236; and an output connected to the power amplifier supply voltage. The NFET amplifies an RF input signal to generate an RF output signal RFOUT. Additionally, a gate of the NFET is biased by an internal voltage of the Wilson current mirror and a source receives a ground voltage, while a drain receives the power amplifier supply voltage from a choke inductor 235.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] Embodiments of the present invention relate to electronic systems, and more particularly to radio frequency (RF) electronic devices. The present invention relates to a power amplifier for use in a power amplifier. [Background technology]

[0002] A power amplifier is a device used in radio frequency (RF) communication systems to generate power for transmission through an antenna. It is used to amplify the RF signal to extend battery life and / or achieve a suitable transmit power level. It is important to manage the power of the RF signal transmission to provide a

[0003] Examples of RF communication systems that have one or more power amplifiers include mobile phones, tablets, and base stations. Stations, network access points, customer premises equipment (CPE), laptops and This includes, but is not limited to, wireless electronic devices, such as cellular standards, wireless local area networks, and Wireless LAN (WLAN) standards, and / or any other suitable communications standards. In wireless devices, power amplifiers can be used to amplify RF signals. RF signals are, for example, fifth generation (5G) cellular signals in Frequency Range 1 (FR1). 410MHz to 7.125GHz for 5G communications, or the frequency range 2( FR2) in the range of about 24.250 GHz to about 52.600 GHz, about 30 kHz It may have a frequency in the range of ~300 GHz. Summary of the Invention

[0004] In certain embodiments, the present disclosure relates to a mobile device. a transceiver configured to generate a radio frequency signal; US201301222633 - Power management including an envelope tracker configured to generate a power amplifier supply voltage that varies over time - Google Patents a power amplifier supply voltage for amplifying the radio frequency signal and receiving power from the power amplifier supply voltage; and a front-end system including a power amplifier configured to receive the power. an input configured to receive a reference current; and an input electrically connected to a power amplifier supply voltage. and a field effect transistor configured to amplify a radio frequency signal. a transistor that is biased based on an internal voltage of the current mirror; and a field effect transistor having a gate.

[0005] In various embodiments, the internal voltage of the current mirror decreases with decreasing power amplifier supply voltage. and decreases in response to an increase in the power amplifier supply voltage.

[0006] In a number of embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor. It is a transistor.

[0007] In some embodiments, the power amplifier further comprises a power amplifier supply voltage section and a field effect A choke inductor is electrically connected between the drain of the transistor and the choke inductor.

[0008] In some embodiments, the current mirror is a Wilson current mirror.

[0009] In various embodiments, the power amplifier further comprises a gate bias of the field effect transistor. configured to buffer the internal voltage of the current mirror to generate the reference voltage. According to certain embodiments, the buffer includes a zero-shift buffer. a first depletion mode transistor and a second depletion mode transistor configured to provide a The transistor includes a voltage-mode transistor.

[0010] In some embodiments, the current mirror is configured to output an internal voltage. a first mirror transistor having a drain, a second mirror transistor, and a third mirror transistor; a third mirror transistor and a fourth mirror transistor; The transistor is connected in series between the input of the current mirror and the ground voltage. The fourth mirror transistor and the second mirror transistor are connected to the output of the current mirror and ground. In some embodiments, the first mirror transistor is connected in series with the voltage section. The gate of the second mirror transistor is connected to the gate of the third mirror transistor. According to various embodiments, the gate of the second mirror transistor is connected to the gate of the fourth mirror transistor. The drain of the first mirror transistor is connected to the gate of the second mirror transistor, and the drain of the third mirror transistor is connected to the gate of the The drain of the transistor is connected to the gate of the third mirror transistor.

[0011] In some embodiments, the power amplifier is further configured to generate a reference current. Includes a current source.

[0012] In some embodiments, the envelope tracker is configured to output a plurality of regulated voltages. and a DC / DC converter based on the plurality of regulated voltages and the envelope of the radio frequency signal. a modulator configured to generate a modulator output voltage at an output based on the modulator output voltage; and a modulator output filter coupled between the power amplifier supply voltage section and the modulator output section.

[0013] In various embodiments, the envelope trackers are coupled to each other to generate the power amplifier supply voltage. The DC / DC converter and the error amplifier are configured to operate in parallel with each other.

[0014] In certain embodiments, the present disclosure relates to an envelope tracking system. is configured to generate a power amplifier supply voltage that varies in relation to the envelope of the radio frequency signal. an envelope tracker configured to amplify the radio frequency signal and the power amplifier supply voltage; and a power amplifier configured to receive power from the reference voltage. an input configured to receive a power amplifier signal; and an output electrically connected to a power amplifier supply voltage. A current mirror and a field effect transistor configured to amplify a radio frequency signal. Therefore, a current mirror having a gate biased based on the internal voltage of the current mirror is generated. and field effect transistors.

[0015] In various embodiments, the internal voltage of the current mirror decreases with decreasing power amplifier supply voltage. and decreases in response to an increase in the power amplifier supply voltage.

[0016] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor. It is a transistor.

[0017] In some embodiments, the power amplifier further comprises a power amplifier supply voltage section and a field effect A choke inductor is electrically connected between the drain of the transistor and the choke inductor.

[0018] In various embodiments, the current mirror is a Wilson current mirror.

[0019] In some embodiments, the power amplifier further comprises a gate barrier of the field effect transistor. Configured to buffer the internal voltage of the current mirror to generate the bias voltage According to certain embodiments, the buffer includes a zero buffer. a first depletion mode transistor and a second depletion mode transistor configured to provide a Includes a region-mode transistor.

[0020] In some embodiments, the current mirror is configured to output an internal voltage. a first mirror transistor having a drain, a second mirror transistor, and a third mirror transistor; a third mirror transistor and a fourth mirror transistor; The transistor is connected in series between the input of the current mirror and the ground voltage. The fourth mirror transistor and the second mirror transistor are connected to the output of the current mirror and ground. In some embodiments, the first mirror transistor is connected in series with the voltage section. The gate of the second mirror transistor is connected to the gate of the third mirror transistor. In various embodiments, the gate of the second mirror transistor is connected to the gate of the fourth mirror transistor. The drain of the first mirror transistor is connected to the gate of the second mirror transistor, and the drain of the third mirror transistor is connected to the gate of the The drain of the transistor is connected to the gate of the third mirror transistor.

[0021] In some embodiments, the power amplifier is further configured to generate a reference current. Includes a current source.

[0022] In some embodiments, the envelope tracker is configured to output a plurality of regulated voltages. and a DC / DC converter based on the plurality of regulated voltages and the envelope of the radio frequency signal. a modulator configured to generate a modulator output voltage at an output based on the modulator output voltage; and a modulator output filter coupled between the power amplifier supply voltage section and the modulator output section.

[0023] In some embodiments, the envelope tracker is configured to generate the power amplifier supply voltage. It includes a DC / DC converter and an error amplifier configured to operate in parallel with each other.

[0024] In certain embodiments, the present disclosure provides a method for amplifying radio frequency signals in a mobile device. The method uses an envelope tracker to track a signal that varies relative to the envelope of the radio frequency signal. generating a power amplifier supply voltage corresponding to the power amplifier; and supplying the power amplifier with the power amplifier supply voltage. and applying power to the radio frequency using a field effect transistor of the power amplifier. amplifying the signal and using the internal voltage of the current mirror of the power amplifier to generating a gate bias voltage for the effect transistor, A reference current is applied to the input of the current mirror and the power amplifier supply voltage is applied to the output of the current mirror. This includes being able to

[0025] In various embodiments, the method includes: switching a current mirror in response to a decrease in the power amplifier supply voltage; Increasing the internal voltage of the power amplifier and increasing the current mirror and reducing the internal voltage of the

[0026] In some embodiments, the field effect transistor is a short channel metal oxide semiconductor transistor. It is a transistor.

[0027] In a number of embodiments, the method further comprises: This involves applying a supply voltage to the drain of a field effect transistor.

[0028] In some embodiments, the current mirror is a Wilson current mirror.

[0029] In various embodiments, the method further comprises: This involves buffering the internal voltage of the current mirror to generate

[0030] In a number of embodiments, the method further comprises generating the reference current using a current source. Includes:

[0031] In some embodiments, generating the power amplifier supply voltage comprises a DC / DC converter. outputting a plurality of regulated voltages from the converter; and modulating the plurality of regulated voltages using a modulator. generating a modulator output voltage based on the voltage and an envelope of the radio frequency signal; A power filter is used to filter the modulator output voltage to generate the power amplifier supply voltage. This includes filtering.

[0032] In some embodiments, generating the power amplifier supply voltage comprises parallel operating This involves tracking the envelope using a DC / DC converter and an error amplifier. [Brief explanation of the drawings]

[0033] [Figure 1] FIG. 1 is a schematic diagram of an embodiment of a mobile device. [Figure 2] 1 is a schematic diagram of an embodiment of a transmission system for transmitting a radio frequency (RF) signal from a mobile device. [Figure 3]FIG. 1 is a schematic diagram of a power amplifier according to an embodiment. [Figures 4A-4D] Figure 4A is a graph of an example of power gain versus output power for a power amplifier without adaptive bias, Figure 4B is a graph of an example of power gain versus output power for a power amplifier with adaptive bias, Figure 4C is a graph of an example of quiescent drain current versus supply voltage for a power amplifier without adaptive bias, and Figure 4D is a graph of an example of quiescent drain current versus supply voltage for a power amplifier with adaptive bias. [Figure 5] FIG. 10 is a schematic diagram of a power amplifier according to another embodiment. [Figures 6A-6D] Figure 6A is a graph of an example of amplitude distortion versus load power for a power amplifier with adaptive bias but no buffer. Figure 6B is a graph of an example of amplitude distortion versus load power for a power amplifier with adaptive bias and a buffer. Figure 6C is a graph of an example of phase distortion versus load power for a power amplifier with adaptive bias but no buffer. Figure 6D is a graph of an example of phase distortion versus load power for a power amplifier with adaptive bias and a buffer. [Figures 7A-7B] 7A and 7B are graphs of an example of drain current versus drain voltage for a short-channel metal-oxide-semiconductor (MOS) transistor, respectively. [Figure 8A-8B] Figure 8A is an example graph of power amplifier supply voltage versus time; and Figure 8B is another example graph of power amplifier supply voltage versus time. [Figure 9A] FIG. 1 is a schematic diagram of an envelope tracking system according to an embodiment. [Figure 9B] FIG. 10 is a schematic diagram of an envelope tracking system according to another embodiment. [Figure 10] FIG. 10 is a schematic diagram of an envelope tracking system according to another embodiment. [Figures 11A-11B] Figure 11A is a schematic diagram of one embodiment of a packaged module, and Figure 11B is a schematic cross-sectional view of the packaged module taken along line 11B-11B in Figure 11A. [Figure 12] FIG. 2 is a schematic diagram of an embodiment of a phone board. DETAILED DESCRIPTION OF THE INVENTION

[0034] The following detailed description of certain embodiments represents various descriptions of specific embodiments. However, the innovations described herein are defined and covered, for example, by the claims. In this description, the same reference numerals refer to the same Reference is made to the drawings which may show identical or functionally similar elements. It is further understood that elements shown in the drawings are not necessarily to scale. The embodiments may include more elements than shown in the drawings and / or may include more elements than shown in the drawings. Additionally, some embodiments may include a subset of features from more than one drawing. Any suitable combination may be incorporated.

[0035] FIG. 1 is a schematic diagram of an example of a mobile device 100. The mobile device 100 is a Band system 1, transceiver 2, front-end system 3, antenna 4, power management system The device includes a system 5, a memory 6, a user interface 7 and a battery 8.

[0036] The mobile device 100 may be 2G, 3G, 4G (LTE, LTE Advanced, and LTE Advanced). Advanced Pro), 5G, WLAN (e.g. Wi-Fi), WPAN (e.g. Bluetooth) -Tooth (registered trademark) and ZigBee (registered trademark), WMAN (e.g. WiMax ), and / or communicate using a variety of communication technologies, including but not limited to GPS technology. It can be used to trust.

[0037] The transceiver 2 generates RF signals for transmission and receives incoming RF signals from the antenna 4. It will be appreciated that various functions associated with transmitting and receiving RF signals This functionality is achieved by one or more components collectively represented in FIG. 1 as transceiver 2. In one example, separate components may be used to handle certain types of RF signals. (eg, a separate circuit or die).

[0038] The front-end system 3 transmits and / or receives signals from the antenna 4. In the illustrated embodiment, the front end system The system 3 includes a power amplifier (PA) 11, a low noise amplifier (LNA) 12, a filter 13, a switch 1 includes a switch 14 and a duplexer 15. However, other implementations are possible.

[0039] For example, the front-end system 3 may include a signal amplifier for transmission, a received signal amplifier, a signal amplifier, and a signal amplifier. filtering, switching between different bands, switching between different power modes, Switching between transmit and receive modes, duplexing signals, multiplexing signals plexing (e.g., diplexing or triplexing), or any of these A number of functions can be provided, including but not limited to combinations.

[0040] In certain implementations, the mobile device 100 supports carrier aggregation. This allows for flexibility to increase peak data rates. is a combination of frequency division duplexing (FDD) and time division duplexing (TDD). It can be used for both single and multiple carriers or channels. Carrier aggregation is the aggregation of adjacent carriers within the same operating frequency band. Carrier aggregation may also be discontinuous, and may include: and / or may include frequency separated carriers in different bands.

[0041] Antenna 4 may include antennas used for a variety of different types of communications. For example, antenna 4 may transmit and / or receive signals associated with a wide variety of frequencies and communication standards. may include an antenna associated with receiving.

[0042] In certain implementations, the antenna 4 is used for MIMO communications and / or switched diversity. For example, MIMO communication supports multiplexing over a single radio frequency channel. MIMO communication uses multiple antennas to transmit multiple data streams. High signal-to-noise ratio, improved coding, and / or spatial multiplexing differences in the wireless environment Switched diversity benefits from reduced signal interference due to differences in This refers to the communications that an antenna is selected to operate at a particular time. A set of metrics based on various factors such as bit error rate and / or signal strength indicators. A switch can be used to select a particular antenna from the antennas.

[0043] The mobile device 100 may, in certain implementations, operate with beamforming. For example, the front-end system 3 may be a phase control system in which the variable phase is controlled by the transceiver 2. Additionally, the phase shifter may be used for transmitting signals using the antenna 4 and / or The antennas are controlled to provide beam formation and directivity for reception. In the context of signal transmission, the phase of the transmitted signal applied to antenna 4 is determined by the phase of the transmitted signal radiated from antenna 4. The signals propagating in a given direction are combined using constructive and destructive interference. The signal strength is controlled to generate an aggregate transmit signal that indicates the beam quality of the signal reception. In this context, phase refers to the amount of signal that is transmitted when the signal is arriving at the antenna 4 from a particular direction. In a given implementation, the antenna 4 is controlled to receive the signal energy. The antenna may include one or more arrays of multiple antenna elements to enhance beamforming.

[0044] The baseband system 1 receives various user inputs and outputs (I / O) such as voice and data. ) is coupled to a user interface 7 to facilitate processing of the baseband system 1. is a digital representation of the transmit signal that the transceiver 2 processes to generate an RF signal for transmission. The baseband system 1 also provides the received signal provided by the transceiver 2. As shown in Figure 1, the baseband system 1 processes a digital representation of a mobile The wireless device 100 is coupled to a memory 6 to facilitate operation of the wireless device 100 .

[0045] The memory 6 may be used to facilitate operation of the mobile device 100 and / or to store user information. for a variety of purposes, such as storing data and / or instructions to provide can be used for.

[0046] The power management system 5 provides a number of power management functions for the mobile device 100. The power management system 5 includes an envelope tracker 60. As shown in FIG. The system 5 receives a battery voltage from a battery 8. The battery 8 is used in the portable device 100. The battery may be any suitable battery, including, for example, a lithium ion battery.

[0047] The mobile device 100 of FIG. 1 includes a power amplifier implemented in accordance with one or more aspects of the present disclosure. However, the teachings herein may be applied to a wide variety of RF communication systems. The present invention is applicable to RF communication systems implemented in various ways.

[0048] FIG. 2 illustrates an embodiment of a transmission system 130 for transmitting RF signals from a mobile device. 1 is a schematic diagram of a transmitter system 130. The transmitter system 130 includes a battery 101, an envelope tracker 102, a power amplifier 103, and a power amplifier 104. amplifier 103, directional coupler 104, diplexing switching circuit 105, antenna 106, a baseband processor 107, a signal delay circuit 108, and a digital predistortion a differential photodiode (DPD) circuit 109, an I / Q modulator 110, an observation receiver 111, and an intermodulation detection circuit circuit 112, an envelope delay circuit 121, a coordinate rotation digital computation (CORDIC) circuit 122, It includes a shaping circuit 123 , a digital-to-analog converter 124 and a reconstruction filter 125 .

[0049] The transmitter system 130 of FIG. 2 includes a power amplifier implemented in accordance with one or more aspects of the present disclosure. However, the teachings herein may be applied to a wide variety of RF communication systems. The present invention is applicable to RF communication systems implemented in various ways.

[0050] The baseband processor 107 generates a sinusoidal wave or signal of the desired amplitude, frequency and phase. The I signal operates to generate I and Q signals corresponding to the signal components. The Q signal is used to represent the in-phase component of the sine wave, and the Q signal is used to represent the quadrature component of the sine wave. These can be equivalent representations of sine waves. In a given implementation, the I signal The Q and Q signals are provided to an I / Q modulator 110 in digital format. Processor 107 may be any suitable processor configured to process baseband signals. For example, the baseband processor 107 may be a digital signal processor, a microprocessor, or It may include a processor, a programmable core, or any combination thereof.

[0051] The signal delay circuit 108 delays the envelope signal and the RF signal RF IN The relative alignment with The signal delay circuit 1 provides an adjustable delay to the I and Q signals to aid in controlling the The delay amount provided by the delay circuit 08 is controlled based on the amount of intermodulation detected by the intermodulation detection circuit 112. can be.

[0052] The DPD circuit 109 digitally converts the delayed I and Q signals from the signal delay circuit 108 into Operates to provide shaping and generate digitally pre-distorted I and Q signals In the illustrated embodiment, the DPD provided by DPD circuit 109 is an intermodulation detection circuit. The DPD circuit 109 is controlled based on the amount of intermodulation detected by the power amplifier 112. 03 and / or increase the efficiency of the power amplifier 103.

[0053] The I / Q modulator 110 receives the digitally pre-distorted I and Q signals. , these signals are RF signals RF IN For example, I / Q modulation The converter 110 includes a DAC configured to convert the I and Q signals to an analog format. a mixer for upconverting the I and Q signals to a radio frequency; The resulting I and Q signals are combined to produce an RF signal suitable for amplification by power amplifier 103. In certain implementations, the I / Q modulator 110 may include a signal combiner for processing may include one or more filters configured to filter the frequency content of the signal being transmitted. do.

[0054] The envelope delay circuit 121 delays the I and Q signals from the baseband processor 107. Additionally, the CORDIC circuit 122 processes the delayed I and Q signals and outputs R F signal RF IN Figure 2 shows the CORDIC Although an implementation using circuit 122 is shown, the envelope signal may be obtained in other ways. can.

[0055] The shaping circuit 123 shapes the digital envelope signal to improve the performance of the transmission system 130. In certain implementations, the shaping circuit 123 operates as follows: A shaping table that maps the envelope signal levels to corresponding shaped envelope signal levels. Line shaping helps control the linearity, distortion and / or efficiency of the power amplifier 103 can be done.

[0056] In the illustrated embodiment, the shaped envelope signal is converted to an analog envelope signal by the DAC 124. Additionally, the analog envelope signal is converted into a digital signal by an envelope tracker. by a reconstruction filter 125 to generate an envelope signal suitable for use by 102. In certain implementations, the reconstruction filter 125 is a low-pass filter. This includes data.

[0057] Continuing with reference to FIG. 2, the envelope tracker 102 receives the envelope from the reconstruction filter 125. The signal is received and the battery voltage V BATT and its envelope signal is Use RF signal RF IN The power for the power amplifier 103 varies in relation to the envelope of Amplifier supply voltage V PA The power amplifier 103 outputs the RF signal rf IN In this example, the duplexing switching circuit 105 an amplified RF signal RF OUT Give.

[0058] The directional coupler 104 is connected to the output of the power amplifier 103 and duplexed by the switching amplifier. This is placed between the input of the circuit 105. This allows duplexing switching It is possible to measure the output power of the power amplifier 103 without including the insertion loss of the circuit 105. The detected output signal from the directional coupler 104 is provided to an observation receiver 111. The detector 111 down-converts the I and Q signal components of the detected output signal. and a mixer that generates I and Q observation signals from the downconverted signal. Includes a DAC.

[0059] The intermodulation detection circuit 112 receives the I observation signal and the Q observation signal and the baseband processor 107. Additionally, an intermodulation detection circuit 112 determines intermodulation products with the I and Q signals from the controls the DPD provided by the DPD circuit 109 and / or the delay of the signal delay circuit 108. By doing so, the envelope signal and the RF signal RF IN Controls alignment relative to .

[0060] By including a feedback path from the output of the power amplifier 103 and the baseband , the I and Q signals can be dynamically adjusted to optimize the operation of the transmission system 130. For example, by configuring the transmission system 130 in this manner, power control can be provided. This may assist in compensating for transmitter impairments and / or performing DPD.

[0061] Although shown as a single stage, power amplifier 103 may include one or more stages. Furthermore, RF communication systems, such as mobile devices, may contain multiple power amplifiers. In such an implementation, different power amplifiers may be provided with separate envelope trackers; and and / or one or more shared envelope trackers may be used.

[0062] Adaptive bias for power amplifiers operating with envelope tracking.

[0063] Envelope tracking is the measurement of the power amplifier supply voltage in relation to the envelope of the RF signal amplified by the power amplifier. By efficiently controlling the voltage level of the supply voltage, the power added efficiency (PAE) of the power amplifier can be improved. This is a technique that can be used to increase the RF signal envelope. As the RF signal envelope decreases, the voltage supplied to the power amplifier may also increase. This causes the voltage supplied to the power amplifier to drop, reducing power consumption.

[0064] In one example, the envelope tracker generates a power amplifier supply voltage based on the envelope signal. This includes DC / DC converters that operate in combination with error amplifiers to achieve the desired output voltage. The C converter and the error amplifier can be electrically connected in parallel with each other, and The to-DC converter can track the low frequency components of the envelope signal, while the error amplifier It is possible to track high frequency components of tangle signals, e.g., the switches of a DC / DC converter. the filtering frequency can be reduced to be lower than the maximum frequency component of the envelope signal; An error amplifier adjusts the gap at the output of the converter to generate the power amplifier supply voltage. In certain implementations, a DC / DC converter and The error amplifier can be coupled via a combiner.

[0065] In another example, the envelope tracker has multiple outputs that generate regulated voltages at different voltage levels. Controlling the boost switch and selecting the appropriate regulated voltage over time based on the envelope signal A bank of switches and outputs of the switch bank for generating a power amplifier supply voltage. and a filter for filtering the force.

[0066] A power amplifier with adaptive bias for envelope tracking applications is provided herein. In certain embodiments, the envelope tracking system includes a power amplifier that amplifies the RF signal. a power amplifier receiving power from a power amplifier supply voltage section; and a power amplifier generating a power amplifier based on an envelope of an RF signal. and an envelope tracker for generating a power amplifier supply voltage based on the RF signal. a field effect transistor (FET) that amplifies the reference current, an input section that receives the reference current, and a power amplifier and a current mirror having an output connected to the power supply voltage. The voltage is used to bias the gate of the FET, causing the FET to Changes in the power amplifier supply voltage resulting from tangle tracing are compensated for.

[0067] Implementing adaptive bias in a power amplifier compensates for the non-idealities of the power amplifier FETs. For example, such adaptive biasing may be used to compensate for channel length modulation and / or drain induction. This helps compensate for the barrier lowering that would otherwise occur due to the RF gain vs. power amplifier supply voltage. This results in high variations in pressure.

[0068] In a given implementation, a FET is a short-channel metal-oxide-semiconductor (MOS) transistor. A short-channel MOS transistor is implemented as a fixed number of transistor nonidealities. Adaptive biasing allows short-channel MOS transistors to be used in power amplifiers despite the The auxiliary transistor can be used without significantly degrading the performance of the power amplifier. Short channel MOS transistors are low cost and / or allow for high integration. It can be made in a process that allows Therefore, it is desirable to implement power amplifiers using short channel MOS transistors.

[0069] In certain implementations, a current is also used to generate the gate bias voltage of the FET. The buffer buffers the internal voltage of the side mirror. This improves the bandwidth and speeds up the bias transient response of the power amplifier. , amplitude distortion and phase distortion are improved.

[0070] Current mirrors can be implemented in a wide variety of ways. In one implementation: The current mirror is implemented as a Wilson current mirror. For example, The MOSFET is an n-type field-effect transistor arranged as a four-transistor Wilson current mirror. It can be implemented using transistors (NFETs). For example, four transistors The drain-source voltage of the first NFET in the Wilson mirror decreases as the output voltage decreases. , so increasing the gain of the power amplifier as the power amplifier supply voltage decreases It is well suited to.

[0071] 3 is a schematic diagram of a power amplifier 250 according to one embodiment. , NFET 231, Wilson current mirror 232, input DC blocking capacitor 2 33, output DC blocking capacitor 234, choke inductor 235 and reference current source 2 Including 36.

[0072] Although FIG. 3 illustrates one embodiment of a power amplifier with adaptive biasing, The teachings are applicable to power amplifiers implemented in a wide variety of ways.

[0073] The power amplifier 250 receives an RF input signal RF at its RF input terminal. IN received and amplified RF output signal RF OUT In the illustrated embodiment, the input DC The lock capacitor 233 is connected to the gate of the NFET 231 independently of the DC voltage at the RF input terminal. A resistor is connected between the RF input terminal and the gate of NFET231 to allow for voltage biasing. Additionally, an output DC blocking capacitor 234 is connected to the drain voltage of NFET 231. from the DC voltage at the RF output terminal. Connected between the F output terminal.

[0074] As shown in FIG. 3, choke inductor 235 applies a current to the drain of NFET 231. Power amplifier supply voltage V PAThe power amplifier supply voltage V PA is the envelope disclosed herein. may be generated by any of the following: can.

[0075] NFET 231 receives the RF input signal RF IN is amplified to produce the RF output signal RF OUT Generated Additionally, the gate of NFET 231 is connected to the internal In addition, the source of NFET231 is biased by a ground voltage. The drain of NFET 231 receives the power from choke inductor 235 to the power amplifier Supply voltage V PA In a given implementation, NFET 231 is an n-type metal oxide semiconductor. It is implemented as a NMOS transistor. For example, the NFET 231 is a short-channel It may be an NMOS transistor.

[0076] The Wilson current mirror 232 receives the reference current I from the reference current source 236. REF Receive and a power amplifier supply voltage V PA and an output connected to Wilson The current mirror 232 includes a first current mirror NFET 241 and a second current mirror NF ET242, the third current mirror NFET243 and the fourth current mirror NFET244 Includes:

[0077] As shown in FIG. 3, the first current mirror NFET 241 and the second current mirror 2 42 each include a source connected to ground. The gate of NFET 241 is connected to the gate and drain of the second current mirror NFET 242. and is connected to the source of the fourth current mirror NFET 244. The output of the Wilson current mirror 232 is connected to the fourth current mirror NFET 244. The input of the Wilson current mirror 232 is connected to the drain of the fourth current mirror. to the gate of the third current mirror NFET 244, and to the gate of the third current mirror NFET 243. and drain of the first current mirror NFET 241. The drains of the three current mirror NFETs 243 are connected together.

[0078] In the illustrated embodiment, the internal voltage of the Wilson current mirror 232 is adaptively biased. The internal voltage is applied to the gate of NFET 231 to provide the internal voltage. In this case, it corresponds to the drain voltage of the first current mirror NFET 241.

[0079] The Wilson current mirror 232 receives a reference current I at its input. REF Mira The output stage operates by filtering to generate an output current at the output. Power amplifier supply voltage V PA As the voltage changes, the driver of the first current mirror NFET 241 The drain voltage also varies so that the output current tracks the input current. Wilson Cullen As a result of adjusting the mirror 232, the power amplifier supply voltage V PA As decreases, the first current source The drain-source voltage of NFET 241 increases.

[0080] The drain voltage of the first current mirror NFET 241 is the power amplifier supply voltage V PA Decrease It is well suited to increasing the gain of the power amplifier as the power amplifier supply voltage V PAIt is well suited to reducing the gain of the power amplifier as increases, i.e. The Wilson current mirror 232 compensates for gain variations resulting from power supply variations. The adaptive bias is applied to NFET 231 to compensate for the Short-channel effects (e.g., well suited to compensate for channel length modulation and / or drain-induced barrier lowering .

[0081] FIG. 4A is a graph of an example of power gain versus output power for a power amplifier without adaptive biasing. .

[0082] FIG. 4B is a graph of an example of power gain versus output power for a power amplifier with adaptive bias. .

[0083] As shown by comparing Figures 4A and 4B, adaptive biasing reduces gain variability. is reduced (for example, from about 15 dB to about 3 dB in this example).

[0084] FIG. 4C shows an example graph of quiescent drain current versus supply voltage for a power amplifier without adaptive bias. It is Fu.

[0085] FIG. 4D is a graph of an example of quiescent drain current versus supply voltage for a power amplifier with adaptive bias. It is Fu.

[0086] As shown by comparing Figures 4C and 4D, adaptive biasing reduces the quiescent drain voltage. The flow variability is reduced (e.g., from about 12x to about 1.25x in this example). (This is the case.)

[0087] 5 is a schematic diagram of a power amplifier 280 according to another embodiment. , NFET 231, Wilson current mirror 232, input DC blocking capacitor 2 33, output DC blocking capacitor 234, choke inductor 235, reference current source 27 0 and buffer 270.

[0088] The power amplifier 280 of FIG. 5 is similar to the power amplifier 250 of FIG. 3, except that the power amplifier 280 The first current mirror NFET 231 generates the gate bias voltage for the NFET 231. 2. The difference is that it further includes a buffer 270 for buffering the drain voltage of 241.

[0089] In the illustrated embodiment, buffer 270 is implemented as a zero-shift buffer. The zero-shift buffer is composed of a first depletion-mode (d-mode) FET 271 and a These include 2d-mode FETs 272, such as junction field effect transistors (JF The drain of the first d-mode FET 271 may be a Schottky gate FET. is the battery voltage V BATT While the gate of the first d-mode FET 271 is subjected to The internal voltage of the current mirror 232 is received. Additionally, the gate of the second d-mode FET 272 is also received. The drain of the second d-mode FET 272 is connected to A node that outputs a gate bias voltage to bias the NFET231 of the power amplifier. In the node, the first d-mode FET 271 is connected to the source of the first d-mode FET 271.

[0090] The inclusion of buffer 270 provides improved bandwidth and and improved transient response is achieved.

[0091] FIG. 6A shows the amplitude distortion versus load power (l) for a power amplifier with adaptive bias but no buffer. 1 is a graph showing an example of load power.

[0092] FIG. 6B shows the amplitude distortion versus load power (lo 1 is a graph showing an example of ad power.

[0093] As shown by comparing Figures 6A and 6B, combining a buffer with adaptive biasing By using it in this way, amplitude distortion is reduced (AM / AM).

[0094] FIG. 6C shows an example of phase distortion versus load power for a power amplifier with adaptive bias but no buffer. Here is an example graph.

[0095] FIG. 6D is an example of phase distortion versus load power for a buffered power amplifier with adaptive bias. This is a graph of

[0096] As shown by comparing Figures 6C and 6D, combining a buffer with adaptive biasing This reduces phase distortion (AM / PM).

[0097] FIG. 7A shows an example graph of drain current versus drain voltage for a short-channel MOS transistor. The drain current of a short-channel MOS transistor at different gate-source voltages is Various plots of current versus drain voltage are drawn. plots both with and without channel length modulation (dashed plot) and with channel length modulation (solid plot) Includes:

[0098] FIG. 7B is a graph of an example of drain current versus gate voltage for a short-channel MOS transistor. The graph shows the transistor threshold voltage shift resulting from drain-induced barrier lowering. An example is depicted.

[0099] 8A and 8B show two examples of power amplifier supply voltage versus time.

[0100] In FIG. 8A, graph 447 shows the relationship between the voltage of RF signal 441 and power amplifier supply voltage 443. An example of a signal versus time is shown in Figure 4. An RF signal 441 has an envelope 442.

[0101] Importantly, the power amplifier supply voltage 443 of the power amplifier is For example, a voltage having an amplitude smaller than the amplitude of the RF signal. Powering the power amplifier using the power amplifier supply voltage clips the RF signal, This can lead to signal distortion and / or other problems. It may be important to keep power 43 greater than envelope 442. However, The voltage difference between the amplifier supply voltage 443 and the envelope 442 of the RF signal 441 is preferably reduced. The area between the power amplifier supply voltage 443 and the envelope 442 is preferably This is because it can represent lost energy that can increase the power consumption and heat generated in the wireless device. do.

[0102] In FIG. 8B, a graph 448 shows the relationship between the voltage of the RF signal 441 and the power amplifier supply voltage 444. 8B shows an example of power amplifier supply voltage 443 versus time. The amplifier supply voltage 444 varies in relation to the envelope 442 of the RF signal 441. The area between the power amplifier supply voltage 444 and the envelope 442 in FIG. Since the area between the amplified supply voltage 443 and the envelope 442 is smaller, the graph 4 of FIG. 48 can be associated with a power amplifier with high energy efficiency.

[0103] FIG. 9A is a schematic diagram of an envelope tracking system 500 according to one embodiment. The tracking system 500 includes a power amplifier 501 and an envelope tracker 502. 1 amplifies the radio frequency signal 503.

[0104] The envelope tracker 502 generates an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 502 receives a power amplifier that supplies power to the power amplifier 501. Amplifier supply voltage V PA Generates.

[0105] The illustrated envelope tracker 502 includes a DC / DC converter 511 and an error amplifier 512. These are combined together and based on the envelope signal 504 generate the power amplifier supply voltage V PA In the illustrated embodiment, the output of the DC / DC converter 511 and the output of the error amplifier 512 are combined using a combiner 515 .

[0106] The envelope tracker 502 of FIG. 9A is implemented by switching regulators operating in parallel with each other to generate R 1 shows an example of analog envelope tracking that tracks the envelope of an F signal.

[0107] FIG. 9B is a schematic diagram of an envelope tracking system 540 according to another embodiment. The tracking system 540 includes a power amplifier 501 and an envelope tracker 532. 1 amplifies the radio frequency signal 503.

[0108] The envelope tracker 532 generates an envelope signal 504 corresponding to the envelope of the radio frequency signal 503. Additionally, the envelope tracker 532 receives a power amplifier that supplies power to the power amplifier 501. Amplifier supply voltage V PA Generates.

[0109] The illustrated envelope tracker 532 includes a multi-level switching circuit 535. In one embodiment, a multi-level switching circuit generates regulated voltages at different voltage levels. A multi-output DC / DC converter that selects the appropriate regulated voltage over time based on the envelope signal. a plurality of switches for controlling the selection of a power amplifier supply voltage; and a filter for filtering the force.

[0110] Envelope tracker 532 of FIG. 9B illustrates an example of MLS envelope tracking.

[0111] FIG. 10 is a schematic diagram of an envelope tracking system according to another embodiment. The system 600 includes a power amplifier 501 and an envelope tracker 602. The power amplifier 501 The radio frequency signal 503 is amplified.

[0112] The envelope tracker 602 receives an envelope signal corresponding to the envelope of the radio frequency signal 503. In this example, the envelope signal is differential. Additionally, the envelope tracker 602 The power amplifier supply voltage V that powers the amplifier 501 PA Generates.

[0113] The illustrated envelope tracker 602 includes an envelope amplifier 611, a first comparator 621, a second comparator 622, and a a third comparator 622, a third comparator 623, a coding and dithering circuit 624, and a multi-output boost It includes a switch 625, a filter 626, a switch bank 627, and a capacitor bank 630. The capacitor bank 630 includes a first capacitor 631, a second capacitor 632, and a third capacitor 633. Additionally, the switch bank 627 includes a first switch 641, a second switch 642, a third switch 643, a fourth switch 644, a fifth switch 645, a sixth switch 646, a sixth switch 647, a sixth switch 648, a sixth switch 649, a sixth switch 650, a sixth switch 651, a sixth switch 652, a sixth switch 653, a sixth switch 654, a sixth switch 655, a sixth switch 656, a sixth switch 657, a sixth switch 658, a sixth switch 659, a sixth switch 660, a sixth switch 661, a sixth switch 662, a sixth switch 663, a sixth switch 664, a sixth switch 665, a sixth switch 666, a sixth switch 667, a sixth switch 668, a sixth switch 669, a sixth switch 670, a sixth switch 6 The second switch 642 and the third switch 643 are included.

[0114] The envelope amplifier 611 amplifies the envelope signal and outputs the amplified envelope signal to the first comparator 621- The first comparator 621 to the third comparator 623 output the amplified envelope signal. The comparison is made with a first threshold T1, a second threshold T2, and a third threshold T3. The result is provided to the coding and dithering circuit 624. A logic circuit 624 processes the results and controls the selection of the switches in the switch bank 627. The coding and dithering circuit 624 activates the switch while using switching and / or dithering to reduce artifacts resulting from opening and closing the switch can be reduced.

[0115] Although an example with three comparators is shown, more or fewer comparators may be used. Furthermore, the coding and dithering circuit 624 may be omitted and other embodiments may be used. In the first example, coding is used. In the second example, dithering is used but In the third example, no coding or dithering is used. do not have.

[0116] The multi-output boost switch 625 is BATT To give a DC / DC conversion of Based on the first regulated voltage V MLS1 , the second regulated voltage V MLS2 and third adjusted Voltage V MLS3 Although an example with three regulated voltages is shown, However, the multi-output boost switch 625 can generate a regulated voltage that is greater or less than this. In certain implementations, at least a portion of these regulated voltages may be Battery voltage V BATT In some configurations, these adjusted The voltage is greater than or equal to the battery voltage V BATT buck voltage, which has a voltage lower than is.

[0117] The capacitor bank 630 generates the regulated voltage generated by the multi-output boost switch 625. For example, capacitors 631 to 633 are decoupling capacitors. Acts as a shitter.

[0118] Filter 626 processes the output of switch bank 627 to generate the power amplifier supply voltage V PA The selection of the switches 641 to 643 is controlled over time based on the envelope signal. This allows the power amplifier supply voltage V to track the envelope signal. PA occurs.

[0119] 11A is a schematic diagram of one embodiment of a packaged module 800. 11B is a schematic cross-sectional view of the packaged module 800 taken along line 11B-11B in FIG. 11A. This is a typical diagram.

[0120] The packaged module 800 includes an IC or die 801, a surface mount component 802, and a 3, wire bonds 808, a package substrate 820 and an encapsulation structure 840. The substrate 820 includes pads 806 formed from conductors disposed thereon. Die 801 includes pads 804, and wire bonds 808 connect pads 804 of die 801. It is used to electrically connect to pad 806 on package substrate 820 .

[0121] Die 801 is a power amplifier that can be implemented according to any of the embodiments herein. Includes 846.

[0122] The package substrate 820 supports the die 801 and, for example, surface mount capacitors and / or It receives multiple components such as surface mount components 803, which may include inductors. It may be configured to accommodate this.

[0123] As shown in FIG. 11B, the packaged module 800 is A plurality of contacts are located on the opposite side of the die 800 from the side used to attach the die 801. The packaged module 800 is shown to include tact pads 832. By configuring the packaged module 800, it is possible to use the packaged module 800 in a manner similar to that of a phone board in a wireless device. Examples of contact pads 832 include RF signals, Bias signals, power low voltages and / or power high voltages are applied to the die 801 and / or surface mount components. 11B, the contact pad 803 may be configured to provide a The electrical connection between the lead 832 and the die 801 is by a connection 833 through the package substrate 820. The connections 833 are associated with vias and conductors in the multi-layer laminate packaging substrate. 820, such as a connection made by a semiconductor device. do.

[0124] In some embodiments, the packaged module 800 may also include, for example, One or more packaging structures that provide protection and / or ease of handling of the package-like module 800. Such a package structure may include a package substrate 820 and a An overmold or encapsulation structure 84 formed over the assembled component and die. May contain 0.

[0125] It will be appreciated that the packaged module 800 may be configured with electrical connections based on wire bonds. Although described in the following context, one or more features of the present disclosure may also be used in, for example, flip chips. The present invention may also be implemented in other package configurations, including a chip configuration.

[0126] 12 is a schematic diagram of an embodiment of a phone board 900. The phone board 900 is shown in FIG. 1A and 11B. For clarity, the module 800 shown in FIG. Although not shown, the phone board 900 may include additional components and structures. good.

[0127] application

[0128] Some of the embodiments described above provide examples relating to wireless devices or mobile phones. However, the principles and advantages of those embodiments may be applied to any device requiring a power amplifier. The invention can be used in other systems or devices.

[0129] Such an envelope tracker can be implemented in a variety of electronic devices. Examples may include consumer electronic products, components for such consumer electronic products, electronic test equipment, etc. Examples of electronic devices also include, but are not limited to, memory chips, memory modules, optical fibers, and network or other communications network circuitry, and disk driver circuitry, Consumer electronic products include, but are not limited to, mobile phones, telephones, televisions, computers, Computer monitors, computers, handheld computers, personal digital assistants Tanto (PDA), microwave oven, refrigerator, car, stereo system, cassette recorder or player, DVD player, CD player, VCR, MP3 player, radio, video Cameras, cameras, digital cameras, portable memory chips, washing machines, dryers, washing / drying machines This includes printers, copiers, facsimile machines, scanners, multi-function peripheral devices, wristwatches, clocks, etc. Additionally, electronic devices may include unfinished products.

[0130] summary

[0131] Throughout this specification and claims, unless the context clearly indicates otherwise, The terms "including" and "including" are used in an inclusive sense as opposed to an exclusive or exhaustive sense, i.e., " The term "including but not limited to" should be interpreted as meaning "including but not limited to" as generally used herein. The term "coupled" refers to either direct connection or connection via one or more intermediate elements. Similarly, the word "connected" as used generally herein refers to two or more elements that can be connected. Two or more components that can be either directly connected or connected via one or more intermediate elements Additionally, the words "here," "above," "below," and words of similar import refer to the above elements. When used in this application, it refers to the application as a whole and not to any specific portion of the application. Terms in the above detailed description may be used in the singular or plural where the context permits. Each of the terms "or" can also include the plural or the singular. and "or" covers all of the following interpretations of that word: Any item in the list, all items in the list, and any combination of items in the list is.

[0132] Furthermore, the following are among others: "can," "might," "may," "might," "even Conditional language such as "if," "like," etc., used herein generally refers to situations where the Unless stated or understood otherwise by the context of use, a given embodiment that one embodiment includes certain features, elements and / or conditions while other embodiments do not. That is, such conditional language is intended to convey the characteristics, elements, and / or states The embodiment may be in any aspect necessary for one or more embodiments, or one or more embodiments may be necessary. These characteristics, elements and / or or determining whether a state is included in or performed in any specific embodiment. The term "inventory" is not generally intended to imply that the specification contains logic that

[0133] The above detailed description of embodiments of the present invention is not intended to be exhaustive, i.e., to limit the invention to the above disclosure. It is not intended to be limited to the precise form, and specific embodiments of the invention and examples thereof are illustrative. While the above description is for illustrative purposes, those skilled in the art will recognize that various equivalents are within the scope of the present invention. Modifications are possible. For example, although processes or blocks are presented in a given order, alternative implementations may be used. Embodiments may involve performing routines having steps in a different order or systems having blocks. The system can be used, and some processes or blocks can be deleted, moved, added, or subdivided. Each of these processes or blocks may be The processes or blocks may be implemented in various different ways. Although these processes or blocks may be shown as They can be done in parallel or at different times.

[0134] The teachings of the present invention provided herein are not necessarily limited to the systems described above, but may also be used in other The various embodiment elements and acts described above may also be applied to other systems. These can be combined to give different embodiments.

[0135] While several embodiments of the present invention have been described, these embodiments are presented by way of example only. and are not intended to limit the scope of the present disclosure. The novel methods and systems disclosed herein may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the methods and systems described herein are within the scope of this disclosure. The appended claims and their equivalents are intended to encompass within the scope of this disclosure. It is intended to cover such forms or modifications as come within the scope and spirit of the present invention.

Claims

1. 1. A mobile device, comprising: a transceiver configured to generate a radio frequency signal; a power management system including an envelope tracker configured to control a voltage level of a power amplifier supply voltage section based on an envelope of the radio frequency signal; a front-end system including a power amplifier configured to amplify the radio frequency signal and receive power from the power amplifier supply voltage; Including, the power amplifier includes a current mirror having an input configured to receive a reference current, an output electrically connected to the power amplifier supply voltage, and a node outputting a gate bias voltage; The power amplifier further comprises: a field effect transistor configured to amplify the radio frequency signal; a first depletion mode transistor having a gate connected to the node of the current mirror and a source connected to the gate of the field effect transistor; , including mobile devices.

2. 10. The portable device of claim 1, wherein the power amplifier further comprises a second depletion-mode transistor having a drain connected to the gate of the field-effect transistor.

3. 3. The portable device of claim 2, wherein a gate of the second depletion mode transistor is connected to a source of the second depletion mode transistor.

4. 4. The portable device of claim 3, wherein the gate of the second depletion-mode transistor and the source of the second depletion-mode transistor are connected to a ground voltage.

5. further comprising a battery; 2. The portable device of claim 1, wherein said first depletion-mode transistor has a drain receiving a battery voltage from said battery.

6. The current mirror comprises: a first mirror transistor having a drain connected to the node; a second mirror transistor having a gate connected to the gate of the first mirror transistor; a third mirror transistor having a drain connected to the input and a source connected to the node; The mobile device of claim 1 , comprising:

7. 7. The portable device of claim 6, wherein the gate of the third mirror transistor is connected to the input.

8. 7. The portable device of claim 6, wherein the current mirror further comprises a fourth mirror transistor having a gate connected to the gate of the third mirror transistor and a drain connected to the power amplifier supply voltage.

9. The portable device of claim 8 , wherein the source of the fourth mirror transistor is connected to the drain of the second mirror transistor.

10. The portable device of claim 9 , wherein the drain of the second mirror transistor is connected to the gate of the second mirror transistor.

11. The portable device of claim 6 , wherein the source of the first mirror transistor and the source of the second mirror transistor are connected to a ground voltage.

12. The portable device of claim 1 , wherein the power amplifier further comprises a current source configured to generate the reference current.

13. 1. An envelope tracking system comprising: an envelope tracker configured to control a voltage level of the power amplifier supply voltage section based on an envelope of the radio frequency signal; a power amplifier configured to amplify the radio frequency signal and to receive power from the power amplifier supply voltage; Including, the power amplifier includes a current mirror having an input configured to receive a reference current, an output electrically connected to the power amplifier supply voltage, and a node outputting a gate bias voltage; The power amplifier further comprises: a field effect transistor configured to amplify the radio frequency signal; a first depletion mode transistor having a gate connected to the node of the current mirror and a source connected to the gate of the field effect transistor; An envelope tracking system, including:

14. 14. The envelope tracking system of claim 13, wherein the power amplifier further includes a second depletion-mode transistor having a drain connected to the gate of the field-effect transistor.

15. 15. The envelope tracking system of claim 14, wherein the gate of the second depletion mode transistor is connected to the source of the second depletion mode transistor.

16. 16. The envelope tracking system of claim 15, wherein the gate of the second depletion mode transistor and the source of the second depletion mode transistor are connected to a ground voltage.

17. further comprising a battery; 14. The envelope tracking system of claim 13, wherein said first depletion-mode transistor has a drain receiving a battery voltage from said battery.

18. The current mirror comprises: a first mirror transistor having a drain connected to the node; a second mirror transistor having a gate connected to the gate of the first mirror transistor; a third mirror transistor having a drain connected to the input and a source connected to the node; 14. The envelope tracking system of claim 13, comprising:

19. 1. A method of radio frequency signal amplification in a mobile device, comprising: using an envelope tracker to control the voltage level of the power amplifier supply voltage section based on the envelope of the radio frequency signal; powering a power amplifier using the power amplifier supply voltage; amplifying the radio frequency signal using a field effect transistor of the power amplifier; biasing the field effect transistor using a current mirror having an output electrically connected to the power amplifier supply voltage; Including, Biasing the field effect transistor of the power amplifier comprises: receiving a reference current at an input of the current mirror; outputting a gate bias voltage from a node of the current mirror; applying the gate bias voltage to the field effect transistor using a first depletion mode transistor having a gate connected to the node of the current mirror and a source connected to the gate of the field effect transistor; and giving A method comprising:

20. 20. The method of claim 19, wherein biasing the field effect transistor of the power amplifier further comprises controlling the gate of the field effect transistor using a second depletion mode transistor having a drain connected to the gate of the field effect transistor.

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