Semiconductor Module

Abstract

To preferably suppress a void from being formed in soldering etc., when a top surface of a semiconductor chip and a wire are connected by soldering etc.SOLUTION: There is provided a semiconductor module that comprises a first semiconductor chip and a second semiconductor chip connected in parallel, a first electric wire connecting with a top surface of the first semiconductor chip, and a second electric wire connecting with a top surface of the second semiconductor chip, wherein the electric wires each have a plate-like chip connection part joined to the top surface of the semiconductor chip, the area of the top surface of the first semiconductor chip is equal to the area of the top surface of the second semiconductor chip, and a chip connection part of the first electric wire is different in shape from a chip connection part of the second electric wire.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] BACKGROUND ART In a module including a semiconductor chip such as an insulated gate bipolar transistor (IGBT), a structure in which the top surface of the semiconductor chip is connected to wiring such as a lead frame has been known (see, for example, Patent Document 1). Patent Document 1: JP 2019-186510 A Summary of the Invention [Problem to be solved by the invention]

[0003] When connecting the upper surface of a semiconductor chip to wiring with solder or the like, it is preferable to suppress the occurrence of voids in the solder or the like. [Means for solving the problem]

[0004] To solve the above problems, one aspect of the present invention provides a semiconductor module including a first semiconductor chip and a second semiconductor chip connected in parallel. The semiconductor module may include a first wiring connected to an upper surface of the first semiconductor chip and a second wiring connected to an upper surface of the second semiconductor chip. In any of the above semiconductor modules, each of the wirings may have a plate-shaped chip connection portion bonded to the upper surface of the semiconductor chip. In any of the above semiconductor modules, the area of the upper surface of the first semiconductor chip may be the same as the area of the upper surface of the second semiconductor chip. In any of the above semiconductor modules, the shape of the chip connection portion of the first wiring may be different from the shape of the chip connection portion of the second wiring.

[0005] In any of the above semiconductor modules, each of the semiconductor chips may have a semiconductor substrate and a protective layer selectively provided on an upper surface of the semiconductor substrate. In any of the above semiconductor modules, the first semiconductor chip may have a diode element above the semiconductor substrate, and the protective layer of the first semiconductor chip may cover the diode element.

[0006] In any of the semiconductor modules described above, each of the semiconductor chips may include emitter electrodes provided in a plurality of regions above the semiconductor substrate, and the diode element may be disposed between the emitter electrodes.

[0007] In any of the semiconductor modules described above, the diode element may be disposed so as to overlap a central position of the semiconductor substrate.

[0008] In any of the semiconductor modules described above, the protective layer of the first semiconductor chip may have a first extending protective portion that covers the diode element and extends in a first direction on the top surface of the first semiconductor chip.

[0009] In any of the above semiconductor modules, the protective layer of the second semiconductor chip may have a second extending protective portion that covers a part of a second region of the second semiconductor chip at a position corresponding to a first region in which the diode element of the first semiconductor chip is provided and that has the same size as the first region, and that extends in the first direction on the top surface of the second semiconductor chip. In a top view of any of the above semiconductor modules, an area of the second extending protective portion may be smaller than an area of the first extending protective portion.

[0010] In any of the semiconductor modules described above, the first extended protection portion may have a diode protection portion covering the diode element and a narrow portion extending from the diode protection portion and having a width smaller than that of the diode protection portion. In any of the semiconductor modules described above, the second extended protection portion may have a width smaller than that of the diode protection portion.

[0011] In any of the semiconductor modules described above, the width of the second extended protective portion may be the same as the width of the narrow portion.

[0012] In any of the semiconductor modules described above, the chip connection portion of the first wiring may have a side that surrounds the diode element when viewed from above, and a slit may be provided from a part of the side to a position that overlaps with the diode element.

[0013] In any of the above semiconductor modules, the chip connection portion of the second wiring may be located in the second semiconductor chip at a position corresponding to a first region in which the diode element is provided in the first semiconductor chip, and may overlap with a second region of the same size as the first region.

[0014] In any of the semiconductor modules described above, the semiconductor substrate of the first semiconductor chip may have a first lifetime adjusting portion, in which the defect density shows a peak, at a position that does not overlap the protective layer in a top view.

[0015] In any of the semiconductor modules described above, the semiconductor substrate of the second semiconductor chip may have a second lifetime adjusting section in which the defect density shows a peak at a position corresponding to the first lifetime adjusting section in a top view.

[0016] In any of the semiconductor modules described above, the second semiconductor chip may include a gate runner provided below the second extending protective portion.

[0017] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a diagram illustrating an example of a semiconductor module 200 according to an embodiment of the present invention. [Figure 2] 10 is a diagram showing an example of an insulating circuit board 260. FIG. [Figure 3] 3 is a cross-sectional view taken along the line AA in FIG. 2. [Figure 4] FIG. 2 is a top view showing an example of a semiconductor chip 100-a. [Figure 5] FIG. 2 is a top view showing an example of a semiconductor chip 100-b. [Figure 6] 10 is a diagram showing an example of the arrangement of a protective layer 150 on the upper surface of a semiconductor chip 100-a. [Figure 7] 10 is a diagram showing an example of the arrangement of a protective layer 150 on the upper surface of a semiconductor chip 100-b. [Figure 8] FIG. 10 is a diagram illustrating an example of a chip connection portion 252-a connected to the top surface of a semiconductor chip 100-a. [Figure 9] FIG. 10 is a diagram illustrating an example of a chip connection portion 252-b connected to the top surface of a semiconductor chip 100-b. [Figure 10] 10 is a diagram showing an example of the arrangement of a transistor section 70, a diode section 80, and a gate runner 48 on the top surface of a semiconductor chip 100-a. [Figure 11] 10 is a diagram showing an example of the arrangement of a transistor section 70, a diode section 80, and a gate runner 48 on the top surface of a semiconductor chip 100-b. [Figure 12] FIG. 12 is an enlarged view of a region C in FIG. 10 or 11. [Figure 13] FIG. 13 is a diagram showing an example of the bb cross section in FIG. [Figure 14] 10 is a diagram showing an example of the arrangement of a lifetime adjusting section 94 in a semiconductor chip 100-a. FIG. [Figure 15] 10 is a diagram showing an example of the arrangement of a lifetime adjusting section 94 in a semiconductor chip 100-b. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification and drawings, elements having substantially the same functions and configurations are designated by the same reference numerals to avoid repetitive explanations, and elements not directly related to the present invention may be omitted from illustration. Furthermore, in one drawing, elements having the same functions and configurations may be designated by the same reference numerals, and the reference numerals may be omitted for other elements.

[0021] In this specification, one side in a direction parallel to the depth direction of a semiconductor chip is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0022] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0023] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] FIG. 1 is a diagram showing an example of a semiconductor module 200 according to an embodiment of the present invention. The semiconductor module 200 may function as a power conversion device such as an inverter. The semiconductor module 200 includes one or more insulating circuit boards 260. In this specification, orthogonal axes on a plane on which the one or more insulating circuit boards 260 are provided are defined as the X-axis and Y-axis, and an axis perpendicular to the XY plane is defined as the Z-axis. FIG. 1 shows an example of the arrangement of each component on the XY plane.

[0025] The semiconductor module of this example includes three insulating circuit boards 260, each constituting an arm of a U layer, a V layer, and a W layer. One or more semiconductor chips 100 are mounted on the insulating circuit board 260. The insulating circuit board 260 may also be provided with a circuit pattern 226 and a lead frame 250 that are electrically connected to the semiconductor chip 100. The lead frame 250 is an example of wiring connected to the top surface of the semiconductor chip 100. The wiring may be a wire or the like. The semiconductor chip 100 is protected by a resin case 210 that surrounds the insulating circuit board 260 and a resin package 214 that includes a sealing resin 212 filled in the resin case 210.

[0026] The semiconductor chip 100 may include an insulated gate bipolar transistor (IGBT), a diode such as an FWD (Free Wheel Diode), an RC (Reverse Conducting)-IGBT which is a combination of these, and a MOS transistor.

[0027] Resin case 210 is provided to surround space 194 that houses insulating circuit board 260. One or more terminals 86 may be provided exposed in resin case 210. Terminal 86 is electrically connected to insulating circuit board 260 via terminal connection portion 198. Resin case 210 may also be provided with through holes 84 into which fastening members such as screws for fixing a cooling device or the like can be inserted.

[0028] In this example, the resin case 210 is molded from a resin such as a thermosetting resin that can be formed by injection molding, or an ultraviolet-curing resin that can be formed by UV molding, etc. The resin may include one or more polymer materials selected from, for example, polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, acrylic resin, etc.

[0029] In this example, the sealing resin 212 is provided inside the resin case 210. The sealing resin 212 is, for example, but not limited to, epoxy resin or silicone gel. The sealing resin 212 can protect the insulating circuit board 260.

[0030] Each semiconductor chip 100 has a semiconductor substrate made of a semiconductor material such as silicon. The same power semiconductor elements may be formed on the semiconductor substrate of each semiconductor chip 100. For example, an IGBT may be formed on each semiconductor substrate, or an IGBT and an FWD may be formed on each semiconductor substrate. The semiconductor substrate of each semiconductor chip 100 may be the same size. In other words, the semiconductor substrate of each semiconductor chip 100 may have the same area of the top surface and the same thickness in the direction perpendicular to the top surface. In other words, each semiconductor chip 100 may be provided with power semiconductor elements with the same characteristics.

[0031] Furthermore, at least one semiconductor chip 100 has a diode element (not shown) above the semiconductor substrate. In the example of FIG. 1, the semiconductor chip 100-a has the diode element. The diode element functions, for example, as part of a temperature detection unit that detects the temperature of the semiconductor chip 100-a. However, the function of the diode element is not limited to temperature detection. The diode element may function, for example, as a protection diode that defines an upper limit voltage applied between predetermined nodes of the semiconductor chip 100-a, or may be used for other purposes. The diode element may be a PN junction diode in which a P-type region and an N-type region are provided in polysilicon. An insulating film such as BPSG or an oxide film is formed between the diode element and the semiconductor substrate.

[0032] At least one semiconductor chip 100 does not have the above-described diode element. In the example of FIG. 1, the semiconductor chip 100-b does not have a diode element. The semiconductor module 200 of this example has the semiconductor chip 100-a and the semiconductor chip 100-b on each insulating circuit substrate 260. The semiconductor chip 100-a and the semiconductor chip 100-b are electrically connected in parallel on the insulating circuit substrate 260. Control signals of the same waveform may be input to the semiconductor chip 100-a and the semiconductor chip 100-b. For example, gate signals of the same waveform are input to the semiconductor chip 100-a and the semiconductor chip 100-b.

[0033] The semiconductor chip 100-a may be controlled based on the characteristics of the diode element, such as the voltage or current. For example, if the diode element functions as a temperature detector, the semiconductor chip 100-a is controlled based on the temperature detected by the diode element. As an example, the semiconductor chip 100-a is controlled to an off state when the temperature detected by the diode element is equal to or higher than a predetermined value. The semiconductor chip 100-b may be controlled based on the characteristics of the diode element of the semiconductor chip 100-a provided in parallel therewith.

[0034] In FIG. 1, the arrow indicates the direction in which the coolant flows in the semiconductor module 200. In the direction in which the coolant flows, the semiconductor chip 100-a may be disposed downstream of the semiconductor chip 100-b. In this case, the semiconductor chip 100-a is more difficult to cool than the semiconductor chip 100-b, and therefore the temperature of the semiconductor chip 100-a is more likely to rise. Therefore, by controlling the semiconductor chip 100-a and the semiconductor chip 100-b so that the temperature of the semiconductor chip 100-a does not exceed a predetermined temperature, the temperature of the semiconductor chip 100-b can also be controlled to be below the predetermined temperature. This structure allows the diode element in the semiconductor chip 100-b to be omitted, thereby reducing the manufacturing cost of the semiconductor chip 100-b. Furthermore, the control of multiple semiconductor chips 100 can be simplified.

[0035] FIG. 2 is a diagram showing an example of an insulating circuit board 260. Here, an insulating circuit board 260 constituting one layer of arms is shown as a representative example, but the other boards have a similar configuration. In this example, insulating circuit board 260 has a circuit pattern 226 on one side and a heat sink 222 (see FIG. 3) on the other side. Circuit pattern 226 and heat sink 222 may be formed by bonding a copper plate, an aluminum plate, or a plate made of these materials to an insulating substrate 220 made of silicon nitride ceramics, aluminum nitride ceramics, or the like, directly or via a brazing layer.

[0036] In this example, semiconductor chip 100 is bonded to circuit pattern 226 provided on the upper surface of insulating circuit board 260 via bonding layer 230 such as solder (see FIG. 3). The upper surface of semiconductor chip 100 is connected to lead frame 250 via bonding layer 232 such as solder (see FIG. 3). Lead frame 250 connects semiconductor chip 100 to circuit pattern 226 via bonding layer 234 such as solder (see FIG. 3).

[0037] The lead frame 250 is a member made of a metal material such as copper or aluminum. At least a portion of the surface of the lead frame 250 may be plated with nickel or the like. At least a portion of the surface of the lead frame 250 may be coated with resin or the like. The lead frame 250 may have a plate-like portion. A plate-like shape refers to a shape in which the areas of two opposing main surfaces are larger than the areas of the other surfaces. At least the portion of the lead frame 250 that connects to the semiconductor chip 100 may be plate-shaped. The lead frame 250 may be formed by bending a single metal plate.

[0038] The circuit pattern 226 transmits signals or power by being electrically connected to the semiconductor chip 100 or the lead frame 250. The circuit pattern 226 may include multiple island regions 226A, 226B, and 226C. A plurality of semiconductor chips 100 may be arranged in one island region 226A or 226B of the circuit pattern 226. A plurality of semiconductor chips 100 arranged in one island region 226A or 226B may be connected to the same island region 226B or 226C by the lead frame 250. In the example of FIG. 2, two semiconductor chips 100-a and 100-b aligned in the Y-axis direction are connected in parallel to the same island region 226B or 226C by two lead frames 250.

[0039] The semiconductor chip 100 of this example is a vertical chip with electrodes (e.g., an emitter electrode and a collector electrode) formed on the top and bottom surfaces. The semiconductor chip 100 is connected to the circuit pattern 226 by the electrodes formed on the bottom surface, and is connected to the lead frame 250 by the electrodes formed on the top surface. Note that the semiconductor chip 100 is not limited to a vertical chip. The semiconductor chip 100 may have electrodes on its top surface that are connected to the circuit pattern 226. In this case, the circuit pattern 226 and the electrodes may be connected by wires or the like.

[0040] Terminal connection portion 198 connects circuit pattern 226 to terminal 86 shown in Fig. 1. Terminal connection portion 198 may be a plate- or rod-shaped member made of metal, or may be a wire-shaped member. This electrically connects semiconductor chip 100 to terminal 86.

[0041] Fig. 3 is a cross-sectional view taken along line AA in Fig. 2. Fig. 3 shows an example of the arrangement of each component when projected onto the XZ plane. On this side, the semiconductor module 200 includes an insulating substrate 220, a heat sink 222, a bonding layer 224, a cooling section 216, a circuit pattern 226, bonding layers 230, 232, and 234, a semiconductor chip 100, a lead frame 250, and a sealing resin 212.

[0042] The heat sink 222 may cover the entire lower surface of the insulating substrate 220. The heat sink 222 may be formed of a metal such as copper. The bonding layer 224 bonds the heat sink 222 to the cooling unit 216. The bonding layer 224 is made of solder or the like. The cooling unit 216 contains a refrigerant such as water inside. As shown in FIG. 1 , the refrigerant flows in a predetermined direction inside the cooling unit 216. The direction of the refrigerant flow is determined by the position where the refrigerant is introduced into the cooling unit 216, the position where the refrigerant is discharged to the outside of the cooling unit 216, and fins and the like that form a refrigerant flow path inside the cooling unit 216. The cooling unit 216 cools the semiconductor chip 100 via the heat sink 222 and the like.

[0043] The circuit pattern 226 is disposed on the upper surface of the insulating substrate 220. The circuit pattern 226 may be formed of the same material as the heat sink 222, or may be formed of a different material. The semiconductor chip 100 is connected to the upper surface of the island region 226A by a bonding layer 230. The bonding layer 230 bonds the semiconductor chip 100 to the island region 226 by a conductive material such as solder.

[0044] The lead frame 250 connects the semiconductor chip 100 and the island region 226B. In this example, the lead frame 250 has a chip connection portion 252, a circuit pattern connection portion 256, and a bridge portion 254. The chip connection portion 252 is a portion bonded to the upper surface of the semiconductor chip 100 by the bonding layer 232. The circuit pattern connection portion 256 is a portion connected to the upper surface of the island region 226B by the bonding layer 234. The chip connection portion 252 and the circuit pattern connection portion 256 may be plate-like portions that are approximately parallel to the XY plane. Note that "approximately parallel" refers to an angle of, for example, 10 degrees or less. In this example, the area of the chip connection portion 252 is larger than the area of the circuit pattern connection portion 256. The areas of the chip connection portion 252 and the circuit pattern connection portion 256 may be, for example, the areas of the upper surfaces of the plate-like portions connected to the semiconductor chip 100 and the island region 226B.

[0045] The bridge portion 254 connects the chip connection portion 252 and the circuit pattern connection portion 256. The bridge portion 254 is disposed away from conductive members such as the circuit pattern 226. In this example, the bridge portion 254 is disposed above the circuit pattern 226, etc., and is provided so as to straddle the circuit pattern 226, etc., from the chip connection portion 252 to the circuit pattern connection portion 256.

[0046] 1 and 2 is provided in the bridge portion 254. The opening 274 penetrates the bridge portion 254 in the Z-axis direction. This allows the sealing resin 212 to reliably spread above and below the lead frame 250.

[0047] The sealing resin 212 is provided inside the resin case 210. The sealing resin 212 may fill the space 194 of the resin case 210 so that the semiconductor chip 100, the lead frame 250, and the circuit pattern 226 are not exposed.

[0048] It is preferable to suppress the occurrence of voids in a bonding layer such as solder. In the semiconductor module 200, the semiconductor chip 100 is a heat source, and the chip connection portion 252 connected to the semiconductor chip 100 repeatedly expands and contracts due to temperature changes. For this reason, it is preferable to suppress the occurrence of voids in the bonding layer 232 as much as possible.

[0049] FIG. 4 is a top view showing an example of a semiconductor chip 100-a. The semiconductor chip 100-a includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has edges 102 in a top view. In this specification, the term "top view" refers to the projection of the position of a specific component, such as the semiconductor substrate 10 or the semiconductor chip 100, onto the top surface of the component. The semiconductor substrate 10 in this example has two pairs of edges 102 facing each other in a top view. FIG. 4 shows a pair of edges 102-1 and 102-2 facing each other. In FIG. 4, the direction parallel to the edges 102-1 and 102-2 is the Y-axis direction, and the direction perpendicular to the edges 102-1 and 102-2 is the X-axis direction.

[0050] The semiconductor substrate 10 has an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor chip 100 is controlled to an on-state. The active portion 120 is a region where a transistor such as an IGBT or a diode such as an FWD is provided. The active portion 120 may be a region covered by the emitter electrodes 52. In this case, the region sandwiched between the emitter electrodes 52 in a top view may also be the active portion 120. Furthermore, if a guard ring or a field plate is provided annularly along the outer periphery of the semiconductor substrate 10, the region surrounded by the guard ring or field plate may also be the active portion 120. The guard ring is a P-type region extending from the upper surface of the semiconductor substrate 10 to a position deeper than the base region 14 (described later). The field plate is a conductive member provided above the upper surface of the semiconductor substrate 10. An insulating film is provided between the field plate and the semiconductor substrate 10. The guard ring and field plate may be provided so as to pass between the gate pad 50 (described later) and the edge 102-1.

[0051] The semiconductor chip 100-a includes a diode element 178, an emitter electrode 52, and a gate pad 50. The emitter electrode 52 and the gate pad 50 are electrodes containing a metal such as aluminum. An insulating film is provided between the emitter electrode 52 and the gate pad 50 and the semiconductor substrate 10. The emitter electrode 52 and the gate pad 50 are connected to the semiconductor substrate 10 via contact holes provided in the insulating film. The insulating film and contact holes are omitted from FIG. 4.

[0052] The emitter electrode 52 is disposed above the active section 120. The emitter electrode 52 is connected to the active section 120 via the contact hole described above. Wiring such as a lead frame 250 is connected to the upper surface of the emitter electrode 52, and a predetermined emitter voltage is applied to it. The emitter electrode 52 and the gate pad 50 are provided separately from each other in a top view. Wiring such as a wire is connected to the upper surface of the gate pad 50, and a predetermined gate voltage is applied to it. The gate voltage applied to the gate pad 50 is supplied to the transistor section of the active section 120 by a gate runner or the like, which will be described later.

[0053] The diode element 178 in this example is a PN junction diode disposed above the semiconductor substrate 10. The diode element 178 may function as a temperature detection unit. The diode element 178 may be disposed approximately in the center of the semiconductor substrate 10 in a top view. For example, the diode element 178 may cover the center position of the semiconductor substrate 10. The diode element 178 may be sandwiched between the emitter electrodes 52 in a top view. The emitter electrode 52 in this example is divided into at least two regions, and the diode element 178 is sandwiched between the two regions of the emitter electrode 52. In another example, at least a portion of the diode element 178 may be disposed so as to overlap the emitter electrode 52. In this case, an insulating film is provided between the diode element 178 and the emitter electrode 52.

[0054] The semiconductor chip 100-a may have an anode pad 174 and a cathode pad 176. The anode pad 174 is electrically connected to the anode of a diode element 178, and the cathode pad 176 is electrically connected to the cathode of the diode element 178. The anode pad 174 and the cathode pad 176 may be connected to the diode element 178 by wiring made of polysilicon, aluminum, or the like.

[0055] As an example, the gate pad 50 is arranged on the edge 102-1 side, and the anode pad 174 and the cathode pad 176 are arranged on the edge 102-2 side. The edge 102-1 side refers to the edge 102-1 side of the semiconductor substrate 10 from the center in the X-axis direction, and the edge 102-2 side refers to the edge 102-2 side of the semiconductor substrate 10 from the center. The gate pad 50 may be arranged between the emitter electrode 52 and the edge 102-1. The anode pad 174 and the cathode pad 176 may be arranged between the emitter electrode 52 and the edge 102-2.

[0056] The diode element 178 may be disposed between the gate pad 50 and the anode pad 174 or the cathode pad 176. That is, in a top view, the diode element 178 may be disposed so that a line connecting any point on the gate pad 50 and any point on the anode pad 174 or the cathode pad 176 passes through the diode element 178. In this example, the gate pad 50, the diode element 178, and the anode pad 174 or the cathode pad 176 are aligned in the X-axis direction. The diode element 178 may be disposed so as to overlap the center position between the gate pad 50 and the anode pad 174 or the cathode pad 176.

[0057] The semiconductor chip 100-a may further include a current sense pad 172. A current sense region 110 may be provided in the semiconductor substrate 10 below the current sense pad 172. The current sense region 110 may be provided electrically in parallel with the transistor portion in the active portion 120 and may include a transistor portion having a similar structure. In a top view, the current sense region 110 is smaller than the active portion 120. The current flowing in the active portion 120 can be estimated from the current flowing in the current sense region 110. The current sense pad 172 may be arranged between the emitter electrode 52 and the edge 102-2.

[0058] 5 is a top view showing an example of a semiconductor chip 100-b. The semiconductor chip 100-b differs from the semiconductor chip 100-a in that it does not have a diode element 178. Other structures are similar to those of the semiconductor chip 100-a. However, the semiconductor chip 100-b of this example does not have an anode pad 174, a cathode pad 176, a current sense pad 172, or a current sense region 110. Furthermore, it does not have wiring that connects the anode pad 174 and the cathode pad 176 to the diode element 178.

[0059] The semiconductor chip 100-b has the same size and shape as the semiconductor chip 100-a when viewed from above. The gate pad 50 is disposed at the same position on the semiconductor chip 100-a and the semiconductor chip 100-b.

[0060] The emitter electrode 52 of the semiconductor chip 100-b may have the same shape as the emitter electrode 52 of the semiconductor chip 100-a when viewed from above, or may have a different shape. The emitter electrode 52 of the semiconductor chip 100-b in this example has a different shape from the emitter electrode 52 of the semiconductor chip 100-a when viewed from above. The emitter electrode 52 of the semiconductor chip 100-b does not need to be separated into multiple regions. The emitter electrode 52 of the semiconductor chip 100-b may cover the region where the diode element 178 was provided in the semiconductor chip 100-a. As described above, by omitting the diode element 178 and the like in the semiconductor chip 100-b, the cost of the semiconductor chip 100-b can be reduced.

[0061] FIG. 6 is a diagram showing an example of the arrangement of a protective layer 150 on the top surface of the semiconductor chip 100-a. The protective layer 150 selectively covers the upper portion of the top surface of the semiconductor substrate 10. In FIG. 6, the area where the protective layer 150 is arranged is indicated by diagonal hatching. The protective layer 150 is arranged on the emitter electrode 52, the gate pad 50, the anode pad 174, the cathode pad 176, and the current sense pad 172, and covers at least a portion of these electrodes and pads. Each electrode and each pad has an area not covered by the protective layer 150. A lead frame 250 or wiring such as a wire is connected to this area. The protective layer 150 is also arranged on the diode element 178, covering the entire diode element 178. The protective layer 150 is made of polyimide or the like, and protects each electrode, each pad, and the diode element 178.

[0062] The semiconductor chip 100-a may have a protective layer 150-1 that covers a portion of the gate pad 50. The protective layer 150-1 may be provided so as to cover an end portion of the gate pad 50. The semiconductor chip 100-a may have a protective layer 150-2 that covers the anode pad 174, the cathode pad 176, and the current sense pad 172. The protective layer 150-2 may be provided so as to cover an end portion of each of the anode pad 174, the cathode pad 176, and the current sense pad 172.

[0063] The semiconductor chip 100-a may have a protective layer 150-3 that covers the edge of the semiconductor substrate 10. The protective layer 150-3 may cover the region between the emitter electrode 52 and the edge 102. The protective layer 150-3 may also cover a portion of the emitter electrode 52. A guard ring or a field plate may be provided below the protective layer 150-3.

[0064] The semiconductor chip 100-a may have a protective layer 150-4 that covers the entire diode element 178. The protective layer 150-4 is an example of a diode protection unit. The protective layer 150-4 in this example covers a predetermined first region 301. The first region 301 includes a region in which the diode element 178 is provided when viewed from above. In this example, the region in which the protective layer 150-4 is provided is defined as the first region 301. The first region 301 may be larger than the protective layer 150-4. However, the first region 301 does not include any protective layer 150 other than the protective layer 150-4 and the protective layer 150-7a. The first region 301 may be a region that includes the center Ac of the semiconductor substrate 10 when viewed from above.

[0065] The semiconductor chip 100-a has a protective layer 150-7a extending from the protective layer 150-4. The protective layer 150-7a is provided with its longitudinal axis in a predetermined direction (the X-axis direction in FIG. 6). The semiconductor chip 100-a of this example has a protective layer 150-7a extending from the protective layer 150-4 toward the gate pad 50 and connected to the protective layer 150-1. The protective layer 150-7a may cover the wiring connected to the diode element 178. The semiconductor chip 100-a may also have a protective layer 150-7a extending from the protective layer 150-4 to the opposite side of the gate pad 50 and connected to the protective layer 150-2a. A gate runner may be disposed below the protective layer 150-7a.

[0066] The width W1 of the protective layer 150-4 in the Y-axis direction is larger than the width W2 of the protective layer 150-7a. That is, the protective layer 150-4 covers the diode element 178 and is a portion of the protective layer 150 extending in the X-axis direction that has a larger width in the Y-axis direction. The protective layer 150-7a is an example of a narrow portion that extends from the diode protection portion and is narrower than the diode protection portion. Providing the protective layer 150-4 allows the diode element 178 to be appropriately protected. The protective layer 150-4 and the protective layer 150-7a may be disposed between the two emitter electrodes 52 shown in FIG. 4. The protective layer 150-4 and the protective layer 150-7a may overlap the emitter electrode 52.

[0067] The semiconductor chip 100-a may have protective layers 150-5 and 150-6 that divide the upper surface of the semiconductor substrate 10 into regions 152-1, 152-2, and 152-3. The protective layers 150-5 and 150-6 may be provided across the upper surface of the semiconductor substrate 10 in the Y-axis direction. The region 152-1 is a region where the gate pad 50 is provided, the region 152-2 is a region where the anode pad 174 and the cathode pad 176 are provided, and the region 152-3 is a region where the diode element 178 is disposed. In this embodiment, the region 152-3 is divided into two in the Y-axis direction by the protective layers 150-7a and 150-4.

[0068] In this example, region 152-3 has a larger area than both region 152-1 and region 152-2. Protective layer 150-5 may be connected to protective layer 150-2. In this example, protective layer 150-5 is connected to the tip of protective layer 150-2 in the X-axis direction. Protective layer 150-6 may be connected to protective layer 150-1. In this example, protective layer 150-6 is connected to the tip of protective layer 150-1 in the X-axis direction.

[0069] A connection material such as solder may be provided on the upper surface of the emitter electrode 52 exposed in the region 152-3. This allows a lead frame 250 or wiring such as a wire to be connected to the upper surface of the emitter electrode 52. By increasing the area of the region 152-3, these wirings can be easily connected.

[0070] Furthermore, separating the region 152-3 and the region 152-1 with the protective layer 150-6 can prevent the solder and the like in the region 152-3 from flowing to the gate pad 50. Furthermore, providing the region 152-2 on the opposite side of the region 152-1 can prevent the position of the solder and the like from becoming uneven on the top surface of the semiconductor substrate 10. Furthermore, arranging the protective layer 150 as shown in FIG. 6 can prevent the semiconductor chip 100 from warping.

[0071] FIG. 7 is a diagram showing an example of the arrangement of the protective layer 150 on the upper surface of the semiconductor chip 100-b. The protective layer 150 selectively covers an upper portion of the upper surface of the semiconductor substrate 10. In the semiconductor chip 100-b, a region corresponding to and having the same size as the first region 301 of the semiconductor chip 100-a is defined as the second region 302. Because the semiconductor chip 100-b does not have a diode element 178, it is not necessary to provide a protective layer 150-4 to protect the diode element 178. Therefore, the first area in the first region 301 where the protective layer 150 is provided is larger than the second area in the second region 302 where the protective layer 150 is provided. In other words, the second area is smaller than the first area.

[0072] The emitter electrode 52 is connected to wiring such as the lead frame 250 by solder or the like. In this case, if a protective layer 150 is disposed at the joint between the wiring and the emitter electrode 52, voids are likely to occur in the solder or the like. According to this example, the area of the protective layer 150 at the portion of the semiconductor chip 100-b that is connected to the wiring can be reduced. This makes it possible to suppress the occurrence of voids in the joint of the solder or the like. This therefore improves the connection reliability between the semiconductor chip 100-b and the wiring such as the lead frame 250.

[0073] The semiconductor chip 100-b of this example has a protective layer 150-7b instead of the protective layers 150-7a and 150-4 in the semiconductor chip 100-a. The arrangement of the other protective layers 150 may be the same as in the semiconductor chip 100-a. However, the semiconductor chip 100-b of the example in FIG. 7 has a protective layer 150-2b instead of the protective layer 150-2a in the semiconductor chip 100-a. The protective layer 150-2b does not have openings that expose the pads such as the anode pad 174.

[0074] The protective layer 150-7b is provided at a position corresponding to the protective layer 150-7a. In other words, the value obtained by dividing the distance between the protective layer 150-7b and the edge 102 in the Y-axis direction by the length of the semiconductor chip 100-b in the Y-axis direction is the same as the value obtained by dividing the distance between the protective layer 150-7a and the edge 102 in the Y-axis direction by the length of the semiconductor chip 100-a in the Y-axis direction. When the semiconductor chips 100-a and 100-b have the same size in top view, the protective layer 150-7b is provided at the same position as the protective layer 150-7a.

[0075] In this example, the protective layer 150-7b extends in the X-axis direction from the gate pad 50 to the protective layer 150-2b. The protective layer 150-7b may cover a central position Ac of the semiconductor substrate 10. The width of the protective layer 150-7b in the Y-axis direction is W3. The width W3 of the protective layer 150-7b may be smaller than the width W1 of the protective layer 150-4 throughout the entire protective layer 150-7b. In the example of FIG. 7, the protective layer 150-7b has a uniform width W3 throughout. That is, the width of the protective layer 150-7b of the semiconductor chip 100-b at a position corresponding to the diode element 178 of the semiconductor chip 100-a is smaller than the width of the protective layer 150-4 of the semiconductor chip 100-a.

[0076] The second region 302 is a region located at a position corresponding to the first region 301. In other words, the value obtained by dividing the distance in each direction between the center position of the second region 302 and the edge 102 in a top view by the length in each direction of the semiconductor chip 100-b is equal to the value obtained by dividing the distance in each direction between the center position of the first region 301 and the edge 102 by the length in each direction of the semiconductor chip 100-a. When the areas of the top surfaces of the semiconductor chips 100-a and 100-b are the same, the first region 301 and the second region 302 are provided at the same position. Note that even when the areas of the top surfaces of the semiconductor chips 100-a and 100-b are different, the sizes of the first region 301 and the second region 302 are the same.

[0077] The second region 302 covers the entire protective layer 150-7b in the Y-axis direction. The width of the second region 302 in the Y-axis direction is greater than the width W3. The second region 302 overlaps with the protective layer 150-7b over the entire length in the X-axis direction. The second region 302 may be a region that includes the center position Ac of the semiconductor chip 100-b. The second region 302 does not include any part of the protective layer 150 other than the protective layer 150-7b.

[0078] 6, the first region 301 includes a protective layer 150-4. On the other hand, the second region 302 includes a protective layer 150-7b that is narrower than the protective layer 150-4. Therefore, the area of the protective layer 150 in the second region 302 is smaller than the area of the protective layer 150 in the first region 301. The width W3 of the protective layer 150-7b may be the same as the width W2 of the protective layer 150-7a.

[0079] The protective layer 150-4 and the protective layer 150-7a shown in FIG. 6 are referred to as the first extended protective portion. The first extended protective portion covers the diode element 178 and extends in the X-axis direction. The protective layer 150-7b shown in FIG. 7 is referred to as the second extended protective portion. The second extended protective portion covers a portion of the second region 302 and extends in the X-axis direction. The area of the second extended protective portion is smaller than the area of the first extended protective portion. This can suppress the occurrence of voids in the semiconductor chip 100-b.

[0080] 8 is a diagram illustrating an example of a chip connection portion 252-a connected to the upper surface of the semiconductor chip 100-a. The chip connection portion 252-a is a part of the lead frame 250 that functions as a first wiring.

[0081] The chip connection portion 252-a is a plate-shaped conductive member that is joined by solder or the like to the emitter electrode 52 on the upper surface of the semiconductor chip 100-a. The chip connection portion 252-a may have a shape that does not overlap with the diode element 178 in top view. The chip connection portion 252-a may have a shape that does not overlap with the protective layer 150-4.

[0082] The chip connection portion 252-a has a side 310-a that surrounds the diode element 178 in top view. The side 310-a may surround the protective layer 150-4. The chip connection portion 252-a in this example has two sets of two sides 310-a that are arranged in parallel. The chip connection portion 252-a may be rectangular in top view.

[0083] The chip connection portion 252-a may have a slit 312 extending from a portion of one of the sides 310-a to a position where it overlaps with the diode element 178. The slit 312 is a portion where the chip connection portion 252-a is not provided. The slit 312 may expose the entire diode element 178, or may expose the entire protective layer 150-4. With this configuration, even in the semiconductor chip 100-a, the area where the chip connection portion 252-a and the protective layer 150 overlap can be reduced, thereby suppressing the occurrence of voids. The slit 312 may be provided so as to expose a portion of the protective layer 150-7a. The slit 312 may be provided extending in the X-axis direction along the protective layer 150-7a.

[0084] 9 is a diagram illustrating an example of a chip connection portion 252-b connected to the upper surface of the semiconductor chip 100-b. The chip connection portion 252-b is a part of the lead frame 250 that functions as a second wiring.

[0085] The chip connection portion 252-b is a plate-shaped conductive member that is joined by solder or the like to the emitter electrode 52 on the upper surface of the semiconductor chip 100-b. The chip connection portion 252-b may overlap the second region 302 in a top view. In this example, since the area of the protective layer 150 in the second region 302 is small, even if the chip connection portion 252-b overlaps the second region 302, the occurrence of voids can be suppressed. According to this example, the bonding area between the chip connection portion 252-b and the emitter electrode 52 can be ensured.

[0086] The chip connection portion 252-b has sides 310-b that surround the second region 302 in top view. The chip connection portion 252-b in this example has two sets of two sides 310-b that are arranged in parallel. The chip connection portion 252-b may be rectangular in top view.

[0087] 8 and 9, the chip connection portion 252-a and the chip connection portion 252-b may have different shapes in a top view. This makes it possible to suppress the occurrence of voids depending on the structure of each semiconductor chip 100. In another example, the chip connection portion 252-a and the chip connection portion 252-b may have the same shape in a top view. Both the chip connection portion 252-a and the chip connection portion 252-b may have the shape shown in FIG. 8 or may have the shape shown in FIG. 9.

[0088] 10 is a diagram showing an example of the arrangement of the transistor section 70, the diode section 80, and the gate runner 48 on the top surface of the semiconductor chip 100-a. In FIG. 10, the pads and electrodes such as the gate pad 50, as well as the protective layer 150, are omitted. In FIG. 10, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." The transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction.

[0089] 10, the gate runners 48 are indicated by dashed lines. The gate runners 48 are wiring formed of a conductive material such as impurity-doped polysilicon or metal. The gate runners 48 supply the gate voltage applied to the gate pad 50 to each transistor portion 70. A protective layer 150 may be provided above the gate runners 48.

[0090] The semiconductor chip 100-a may have a gate runner 48-3 arranged to surround the active portion 120 in a top view. The gate runner 48-3 may be arranged below a protective layer 150-3.

[0091] The semiconductor chip 100-a may have a gate runner 48-1 that surrounds the gate pad 50 in a top view. The gate runner 48-1 may be disposed below a protective layer 150-1.

[0092] The semiconductor chip 100-a may have a gate runner 48-2 that surrounds the anode pad 174 and the cathode pad 176 in a top view. The gate runner 48-2 may further surround the current sense pad 172. The gate runner 48-2 may be disposed below the protective layer 150-2.

[0093] The semiconductor chip 100-a may have a gate runner 48-5 that surrounds the diode element 178 in a top view. The gate runner 48-5 may be disposed below the protective layer 150-4.

[0094] The semiconductor chip 100-a may have a gate runner 48-4 extending in the X-axis direction. The gate runner 48-4 may have a portion extending from the gate runner 48-1 in the X-axis direction and connecting to the gate runner 48-5. The gate runner 48-4 may have a portion extending from the gate runner 48-2 in the X-axis direction and connecting to the gate runner 48-5. The gate runner 48-4 may be disposed below the protective layer 150-7a. By providing the gate runner 48, the transistor portion 70, which is far from the gate pad 50, can also be controlled with a short delay time.

[0095] 11 is a diagram showing an example of the arrangement of the transistor section 70, the diode section 80, and the gate runner 48 on the top surface of the semiconductor chip 100-b. The arrangement of the transistor section 70 and the diode section 80 in the semiconductor chip 100-b may be the same as the arrangement of the transistor section 70 and the diode section 80 in the semiconductor chip 100-a. The widths in the Y-axis direction of the transistor section 70 and the diode section 80 may be the same in the semiconductor chip 100-a and the semiconductor chip 100-b.

[0096] Furthermore, the semiconductor chip 100-b may have the same arrangement of gate runners 48 as the semiconductor chip 100-a. However, the semiconductor chip 100-b does not have a gate runner 48-5. In the semiconductor chip 100-b, a gate runner 48-4 is provided linearly from gate runner 48-1 to gate runner 48-2. The gate runner 48-4 is arranged below the protective layer 150-7b. This makes it possible to omit the wide protective layer 150-4 that covers the gate runner 48-5.

[0097] 12 is an enlarged view of region C in FIG. 10 or 11. Region C is a region that includes gate runner 48, transistor portion 70, and diode portion 80. Semiconductor chip 100 of this example includes gate trench portion 40, dummy trench portion 30, well region 11, emitter region 12, base region 14, and contact region 15 provided inside the upper surface side of semiconductor substrate 10.

[0098] 12 shows the area where the emitter electrode 52 is provided. In this example, the emitter electrode 52 is provided in an area that does not overlap with the gate runner 48, but it may overlap with the gate runner 48. In this case, an insulating film is provided between the emitter electrode 52 and the gate runner 48. An interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate 10, but is omitted in FIG. 12. In this example, a contact hole 56 and a contact hole 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film.

[0099] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the upper surface of the semiconductor substrate. An insulating film such as a thermal oxide film is provided between the connection portion 25 and the semiconductor substrate.

[0100] An insulating film such as a thermal oxide film is provided between the gate runner 48 and the semiconductor substrate 10. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the dummy conductive portion in the dummy trench portion 30. The gate runner 48 in this example is provided so as to overlap with an end portion 41 of the gate trench portion 40. The end portion 41 is the end portion of the gate trench portion 40 that is closest to the gate runner 48. At the end portion 41 of the gate trench portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10 and comes into contact with the gate runner 48.

[0101] The emitter electrode 52 is formed of a material containing metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. Furthermore, the emitter electrode 52 may have a plug formed by embedding tungsten or the like in the contact hole so as to contact the barrier metal and aluminum or the like.

[0102] The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction in the region of the transistor portion 70. The arrangement direction in Figure 12 is the X-axis direction. In the transistor portion 70, the one or more gate trench portions 40 and the one or more dummy trench portions 30 may be provided alternately along the arrangement direction.

[0103] The gate trench portion 40 of this example may have two extension portions 39 (portions of the trench that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two extension portions 39. The extension direction in FIG. 12 is the Y-axis direction. It is preferable that at least a portion of the tip portion 41 is curved. By connecting the ends of the linear shapes along the extension direction of the two extension portions 39 of the gate trench portion 40 with the tip portion 41, electric field concentration at the ends of the extension portions 39 can be alleviated.

[0104] The dummy trench portions 30 of this example are provided between the extension portions 39 of the gate trench portions 40. These dummy trench portions 30 may have a linear shape extending in the extension direction.

[0105] The transistor section 70 may have an intermediate region 90 at the boundary adjacent to the diode section 80, where no emitter region is provided on the surface. Furthermore, in the transistor section 70, a plurality of dummy trench sections 30 may be continuously arranged in the portion adjacent to the intermediate region 90. The dummy trench sections 30 provided in the portion adjacent to the intermediate region 90 may also have an extension portion 29 and a tip portion 31. The tip portion 31 and the extension portion 29 have the same shapes as the tip portion 41 and the extension portion 39. The dummy trench section 30 having the tip portion 31 and the linear dummy trench section 30 may have the same length in the extension direction.

[0106] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is provided within a predetermined range, away from the contact hole 54. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction are provided in the well region 11.

[0107] A base region 14 is provided in the mesa portion 60 sandwiched between the trench portions. The mesa portion is a region of the semiconductor substrate sandwiched between the trench portions, located above the deepest bottom of the trench portion. The base region 14 is of the second conductivity type, which has a lower doping concentration than the well region 11. In this example, the base region 14 is of P- type, and the well region 11 is of P+ type.

[0108] A contact region 15 of a second conductivity type having a doping concentration higher than that of the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. In this example, the contact region 15 is P+ type. The well region 11 may be provided away from the contact region 15 that is located at the end of the contact region 15 in the extension direction of the trench portion, in the direction of the gate runner 48. In the transistor portion 70, an emitter region 12 of a first conductivity type having a doping concentration higher than that of the semiconductor substrate 10 is selectively provided on a part of the upper surface of the contact region 15. In this example, the emitter region 12 is N+ type.

[0109] Each of the contact regions 15 and the emitter regions 12 is provided from one adjacent trench portion to the other adjacent trench portion. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are provided so as to be exposed on the top surface of the mesa portion 60 alternately along the extension direction of the trench portions.

[0110] In another example, the contact region 15 and the emitter region 12 may be provided in a stripe pattern along the extension direction in the mesa portion 60 of the transistor section 70. For example, the emitter region 12 is provided in a region adjacent to the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0111] The mesa portion 60 of the diode portion 80 does not need to be provided with the emitter region 12. Furthermore, the mesa portion 60 of the intermediate region 90 is provided with the contact region 15 over a larger area than the mesa portion 60 of the transistor portion 70.

[0112] In the transistor section 70, the contact holes 54 are provided above the contact region 15 and the emitter region 12. The contact holes 54 are not provided in the regions corresponding to the base region 14 and the well region 11. In the diode section 80, the contact holes 54 are provided above the contact region 15 and the base region 14.

[0113] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate. In Fig. 12, the region where the cathode region 82 is provided is indicated by a dotted line. A P+ type collector region may be provided in a region adjacent to the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. Although Fig. 12 shows one mesa section 60 of the diode section 80, the diode section 80 may have multiple mesa sections 60 in the X-axis direction.

[0114] An N+ type accumulation region 16 is provided in at least a portion of the transistor section 70. In Fig. 12, the region where the accumulation region 16 is provided is indicated by a dotted line. The accumulation region 16 may be provided below the emitter region 12 or the contact region 15 in each mesa section 60.

[0115] 13 is a diagram showing an example of the bb cross section in FIG. 12. The bb cross section is an XZ plane passing through the emitter region 12. In this cross section, the semiconductor chip 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.

[0116] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are made of a conductive material such as metal. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 is referred to as the depth direction.

[0117] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the cross section.

[0118] In this cross section, an N+ type emitter region 12, a P- type base region 14, and an N+ type accumulation region 16 are provided in this order from the upper surface 21 side of the semiconductor substrate 10 in the transistor section 70.

[0119] In this cross section, a P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode section 80. The diode section 80 of this example does not have an accumulation region 16. In other examples, the diode section 80 may also have an accumulation region 16. Furthermore, a contact region 15 is provided on the upper surface 21 of the semiconductor substrate 10 in the mesa section 60 adjacent to the transistor section 70.

[0120] In the transistor section 70, an N-type drift region 18 is provided below the accumulation region 16. By providing the accumulation region 16, which has a higher concentration than the drift region 18, between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0121] In this example, the accumulation region 16 is provided in each mesa portion 60 of the transistor portion 70. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. In the diode portion 80, a drift region 18 is provided on the lower surface of the base region 14. In both the transistor portion 70 and the diode portion 80, an N+ type buffer region 20 is provided below the drift region 18.

[0122] The buffer region 20 is provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0123] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. In the active section 120, a projected region overlapping with the cathode region 82 in the Z-axis direction is defined as the diode section 80. That is, the projected region of the cathode region 82 projected onto the upper surface 21 of the semiconductor substrate 10 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10 is defined as the diode section 80. The region obtained by extending the projected region in the Y-axis direction to the well region may also be defined as the diode section 80. In the active section 120, the projected region of the collector region 22 projected onto the upper surface 21 of the semiconductor substrate 10 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10, and in which predetermined unit components including the emitter region 12 and the contact region 15 are regularly arranged is defined as the transistor section 70. The semiconductor chip 100-a and the semiconductor chip 100-b may have the same total area of the emitter regions 12 in a top view. The semiconductor chip 100-a and the semiconductor chip 100-b may have the same total area of the cathode regions 82 in a top view.

[0124] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the top surface 21 of the semiconductor substrate 10. Each trench extends from the top surface 21 of the semiconductor substrate 10 through the base region 14 to reach the drift region 18. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also extends through these regions to reach the drift region 18. The trenches penetrating the doped regions are not limited to those formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include those formed after the trenches are formed.

[0125] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench portion 40. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate insulating film 42 within the gate trench portion 40. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0126] The gate conductive portion 44 includes a region facing the base region 14 with the gate insulating film 42 interposed therebetween. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0127] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided more inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0128] The semiconductor chip 100 may have a lifetime adjustment portion 94 where the defect density shows a peak. In FIG. 13 , the position of the crystal defects 92 in the depth direction is schematically indicated by a cross. By providing the crystal defects 92 that bond with carriers, the carrier lifetime can be adjusted. The lifetime adjustment portion 94 may be disposed on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side refers to the region from the center of the semiconductor substrate 10 in the depth direction to the upper surface 21. The lifetime adjustment portion 94 can be formed by injecting charged particles such as helium from the upper surface 21 side of the semiconductor substrate 10. The lifetime adjustment portion 94 may be disposed below each trench portion. The lifetime adjustment portion 94 may be provided over the entire diode portion 80 in the X-axis direction. This allows the reverse recovery time of the diode portion 80 to be adjusted. The lifetime adjustment portion 94 may also be provided in the intermediate region 90. The lifetime adjustment portion 94 may also be provided in a partial region of the transistor portion 70.

[0129] Fig. 14 is a diagram showing an example of the arrangement of the lifetime adjustment unit 94 in the semiconductor chip 100-a. Fig. 14 shows a lifetime adjustment unit 94-1a adjacent to the protective layer 150-7a in the Y-axis direction and a lifetime adjustment unit 94-2a adjacent to the protective layer 150-4 in the Y-axis direction.

[0130] It is preferable that any of the lifetime adjusting portions 94 be provided at positions that do not overlap with the protective layer 150. When charged particles are injected from the top surface 21 side, if the charged particles are also injected at positions that overlap with the protective layer 150, the range of the charged particles will change between the region where the protective layer 150 is provided and the region where the protective layer 150 is not provided. This causes variations in the depth positions of the lifetime adjusting portions 94, resulting in variations in the characteristics of the semiconductor chip 100.

[0131] The lifetime adjustment unit 94-1a is spaced a distance Y1 from the protective layer 150-7a in the Y-axis direction. The distance Y1 may be 1 μm or more, or may be 5 μm or more. The lifetime adjustment unit 94-2a is spaced a distance Y2 from the protective layer 150-4 in the Y-axis direction. The distance Y2 may be the same as the distance Y1. Because the protective layer 150-4 protrudes in the Y-axis direction more than the protective layer 150-7a, the position of the lifetime adjustment unit 94-2a in the Y-axis direction is shifted away from the protective layer 150-7a relative to the position of the lifetime adjustment unit 94-1a in the Y-axis direction.

[0132] The cathode region 82 may also have a region adjacent to the protective layer 150-7a and a region adjacent to the protective layer 150-4 shifted in the Y-axis direction, similar to the lifetime adjustment section 94. The other structures of the diode section 80 and the transistor section 70 may also have a region adjacent to the protective layer 150-7a and a region adjacent to the protective layer 150-4 shifted in the Y-axis direction, similar to the lifetime adjustment section 94. A P-type well region 11 formed deeper than the base region 14 may be provided below the protective layer 150-7a and the protective layer 150-4.

[0133] FIG. 15 is a diagram showing an example of the arrangement of the lifetime adjustment unit 94 in the semiconductor chip 100-b. FIG. 15 shows a lifetime adjustment unit 94-1b provided at a position corresponding to the lifetime adjustment unit 94-1a, and a lifetime adjustment unit 94-2b provided at a position corresponding to the lifetime adjustment unit 94-2a. The term "corresponding positions" may mean that the positions in the X-axis direction are the same. When the semiconductor chip 100-a and the semiconductor chip 100-b have different sizes in the X-axis direction, the term "corresponding positions" may mean that the value obtained by dividing the distance in the X-axis direction between the lifetime adjustment unit 94 and the edge 102 by the length in the X-axis direction of the corresponding semiconductor chip 100 is equal. In this example, too, it is preferable that none of the lifetime adjustment units 94 be provided at positions that overlap the protective layer 150.

[0134] The lifetime adjusting portion 94-1b is spaced apart from the protective layer 150-7b in the Y-axis direction by a distance Y3, which may be the same as the distance Y1.

[0135] The lifetime adjusting unit 94-2b is spaced a distance Y4 in the Y-axis direction from the protective layer 150-7b. The position of the lifetime adjusting unit 94-2b in the Y-axis direction corresponds to the position of the lifetime adjusting unit 94-2a in the Y-axis direction. Therefore, the distance Y4 is greater than the distance Y3. This structure allows the arrangement of the lifetime adjusting unit 94 to be the same in the semiconductor chip 100-a and the semiconductor chip 100-b, thereby reducing the difference in characteristics between the semiconductor chips 100-a and 100-b.

[0136] The cathode region 82 may also be shifted in position in the Y-axis direction, similar to the lifetime adjustment section 94. The arrangement of the cathode region 82 can be made the same in the semiconductor chip 100-a and the semiconductor chip 100-b, thereby reducing the difference in characteristics between the semiconductor chip 100-a and the semiconductor chip 100-b. Similar to the lifetime adjustment section 94, the other structures of the diode section 80 and the transistor section 70 may also be shifted in position in the Y-axis direction.

[0137] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0138] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 connection portion, 29 extension portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film film, 39...extension portion, 40...gate trench portion, 41...tip portion, 42...gate insulating film, 44...gate conductive portion, 48...gate runner, 50...gate pad, 52...emitter electrode, 54...contact hole, 56...contact hole, 60...mesa portion, 70...transistor portion, 80...diode portion, 82...cathode region, 84...through hole, 86...terminal, 90...intermediate region, 92...crystal defects, 94...lifetime adjusting portion, 100...semiconductor chip, 102...edge, 110...current sense region, 120...active portion, 150...protective layer, 152...region, 172...current sense pad, 174...anode pad, 176...cathode pad, 178...diode element, 194...space, 198...terminal connection portion, 200...semiconductor module, 210...resin case, 212...sealing resin, 214...resin package 2. Heat sink, 216... cooling portion, 220... insulating substrate, 222... heat sink, 226... circuit pattern, 226A, 226B, 226C... island region, 224, 230, 232, 234... bonding layer, 250... lead frame, 252... chip connection portion, 254... bridge portion, 256... circuit pattern connection portion, 260... insulating circuit board, 274... opening, 301... first region, 302... second region, 310... side, 312... slit

Claims

1. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip connected in parallel; a first wiring connected to an upper surface of the first semiconductor chip; a second wiring connected to the top surface of the second semiconductor chip; Equipped with each of the wirings has a plate-shaped chip connection portion joined to the top surface of the semiconductor chip; the area of the top surface of the first semiconductor chip is the same as the area of the top surface of the second semiconductor chip; the chip connection portion of the first wiring and the chip connection portion of the second wiring have different shapes; Each of the semiconductor chips includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a protective layer selectively provided on the upper surface of the semiconductor substrate; and the first semiconductor chip has a diode element above the semiconductor substrate, the protection layer of the first semiconductor chip covers the diode element, The second semiconductor chip does not have a diode element above the semiconductor substrate. Semiconductor module.

2. A semiconductor device comprising: a first semiconductor chip and a second semiconductor chip connected in parallel; a first wiring connected to an upper surface of the first semiconductor chip; a second wiring connected to the top surface of the second semiconductor chip; Equipped with each of the wirings has a plate-shaped chip connection portion joined to the top surface of the semiconductor chip; the area of the top surface of the first semiconductor chip is the same as the area of the top surface of the second semiconductor chip; the chip connection portion of the first wiring and the chip connection portion of the second wiring have different shapes; Each of the semiconductor chips includes: a semiconductor substrate; a protective layer selectively provided on the upper surface of the semiconductor substrate; emitter electrodes provided in a plurality of regions above the semiconductor substrate; and the first semiconductor chip has a diode element above the semiconductor substrate, the protection layer of the first semiconductor chip covers the diode element, the diode element is disposed between the emitter electrodes, the protective layer of the first semiconductor chip covers the diode element and has a first extending protective portion extending in a first direction on the top surface of the first semiconductor chip; the protective layer of the second semiconductor chip has a second extending protective portion that covers a part of a second region in the second semiconductor chip at a position corresponding to a first region in which the diode element of the first semiconductor chip is provided and that has the same size as the first region, and that extends in the first direction on the top surface of the second semiconductor chip; When viewed from above, the area of the second extending protective portion is smaller than the area of the first extending protective portion. Semiconductor module.

3. each of the semiconductor chips includes emitter electrodes provided in a plurality of regions above the semiconductor substrate; The diode element is disposed between the emitter electrodes. The semiconductor module according to claim 1 .

4. The diode element is disposed so as to overlap the center position of the semiconductor substrate.

4. The semiconductor module according to claim 2.

5. The first extended protective portion is a diode protection portion covering the diode element; a narrow portion that is provided extending from the diode protection portion and has a width smaller than that of the diode protection portion; and The second extended protection portion has a width smaller than that of the diode protection portion. The semiconductor module according to claim 2 .

6. The width of the second extended protective portion is the same as the width of the narrow portion. The semiconductor module according to claim 5 .

7. The chip connection portion of the first wiring has a side that surrounds the diode element in a top view, and a slit is provided from a part of the side to a position that overlaps with the diode element.

3. The semiconductor module according to claim 1.

8. The chip connection portion of the second wiring is located in the second semiconductor chip at a position corresponding to a first region in which the diode element is provided in the first semiconductor chip, and overlaps with a second region having the same size as the first region.

3. The semiconductor module according to claim 1.

9. the semiconductor substrate of the first semiconductor chip has a first lifetime adjusting portion, in a position not overlapping with the protective layer in a top view, where a defect density shows a peak; The semiconductor substrate of the second semiconductor chip has a second lifetime adjusting section in which the defect density shows a peak at a position corresponding to the first lifetime adjusting section in a top view.

3. The semiconductor module according to claim 1.

10. The second semiconductor chip includes a gate runner provided below the second extending protective portion.

7. The semiconductor module according to claim 2, 5 or 6.

11. A portion of the chip connection portion of the second wiring overlaps a portion of the protective layer. The semiconductor module according to claim 1 .

12. A portion of the chip connection portion of the first wiring overlaps a portion of the protective layer; The entire chip connection portion of the first wiring does not overlap the diode element. The semiconductor module according to claim 1 .

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