Semiconductor device and data storage system including the same

Abstract

To provide a data storage system including a semiconductor device.SOLUTION: A semiconductor device 100 includes: a peripheral circuit structure PERI, including a first substrate 201 and a circuit element 220 on the first substrate; a memory structure CELL, including a second substrate 101 in an upper part of the first substrate, a first horizontal conductive layer 102 extending on the second substrate, a second horizontal conductive layer 104 arranged on the first horizontal conductive layer, a gate electrode 130 deposited on the second horizontal conductive layer separately along a first direction and a channel layer extending along the first direction through the gate electrode, and separations regions MS1 and MS2a, extending in a second direction through the gate electrode and being separate from each other along a third direction; and a penetration wire region TR1, extending along the first direction and having a penetration contact plug 170 for electrically connecting the memory structure and the peripheral circuit structure. The separation region MS1 penetrates the second horizontal conductive layer and is separated from the first horizontal conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a data storage system including the same. [Background technology]

[0002] In data storage systems that require data storage, semiconductor devices capable of storing large amounts of data are required. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-33244 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor device with improved reliability and a data storage system including the same. [Means for solving the problem]

[0005] In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a first substrate and a peripheral circuit structure including circuit elements on the first substrate; a second substrate disposed on the first substrate; gate electrodes stacked and spaced apart from each other along a first direction perpendicular to one surface of the second substrate; channel structures extending through the gate electrodes and along the first direction, each including a channel layer; isolation regions extending through the gate electrodes in a second direction perpendicular to the first direction, and spaced apart from each other along a third direction perpendicular to the first and second directions; and isolation regions extending on the second substrate and spaced apart from each other along a third direction perpendicular to the first and second directions. a memory cell structure including a first horizontal conductive layer in contact with the channel layer of each of the first and second substrates, a horizontal insulating layer arranged alongside the first horizontal conductive layer, and a second horizontal conductive layer arranged on the first horizontal conductive layer and in contact with a support region of the second substrate where the first horizontal conductive layer and the horizontal insulating layer are not arranged; and a through wiring region arranged between first isolation regions of the isolation regions, the through wiring region including an insulating region and a through contact plug penetrating the insulating region and the second substrate in the first direction to electrically connect the memory cell structure and the peripheral circuit structure, wherein a first portion of the support region extends along the first isolation region.

[0006] According to another aspect of the present invention, which has been made to achieve the above object, a semiconductor device includes: a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a second substrate disposed on top of the first substrate; a first horizontal conductive layer extended on the second substrate; a second horizontal conductive layer disposed on the first horizontal conductive layer; gate electrodes stacked spaced apart on the second horizontal conductive layer along a first direction; channel structures extending through the gate electrodes along the first direction and each including a channel layer; and isolation regions extending through the gate electrodes in a second direction different from the first direction and arranged spaced apart along a third direction different from the first and second directions; and a through wiring region including a through contact plug extending in the first direction and electrically connecting one or more components of the memory cell structure to one or more circuit components of the peripheral circuit structure, wherein the isolation region includes a first isolation region arranged adjacent to the through contact plug along the third direction, and the first isolation region penetrates the second horizontal conductive layer and is spaced apart from the first horizontal conductive layer.

[0007] In order to achieve the above object, one aspect of the present invention provides a data storage system comprising a semiconductor device and a controller electrically connected to the semiconductor device through input / output pads, the semiconductor device including: a first substrate and a peripheral circuit structure including circuit elements on the first substrate; a second substrate disposed on the first substrate; a first horizontal conductive layer extending on the second substrate; a second horizontal conductive layer disposed on the first horizontal conductive layer; gate electrodes stacked on the second horizontal conductive layer in a first direction and spaced apart from each other; channel structures each including a channel layer extending through the gate electrode in the first direction; and a memory cell structure including isolation regions extending through the gate electrode in a second direction different from the first direction and spaced apart along a third direction different from the first and second directions; an input / output pad electrically connected to the circuit element; and a through wiring region including a through contact plug extending in the first direction and electrically connecting one or more components of the memory cell structure to one or more circuit components of the peripheral circuit structure, the isolation region including a first isolation region arranged adjacent to the through contact plug along the third direction, the first isolation region penetrating the second horizontal conductive layer and spaced apart from the first horizontal conductive layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor device and a data storage system including this semiconductor device that can improve reliability by arranging an isolation region adjacent to a through-wiring region so that it overlaps with a support region.

[0009] The various yet significant advantages and effects of the present invention are not limited to the above-mentioned contents, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic plan view of a first example of a semiconductor device according to an embodiment. [Figure 2a]FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 2b] FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 2c] FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 3] FIG. 2 is a schematic plan view of a second example of a semiconductor device according to an embodiment. [Figure 4a] FIG. 4 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 4b] FIG. 4 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 5a] FIG. 10 is a plan view of a third example of a semiconductor device according to an embodiment. [Figure 5b] FIG. 10 is a plan view of a fourth example of a semiconductor device according to an embodiment. [Figure 6] FIG. 10 is a plan view of a fifth example of a semiconductor device according to an embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device of FIG. [Figure 8] FIG. 10 is a plan view of a sixth example of a semiconductor device according to an embodiment. [Figure 9] FIG. 10 is a cross-sectional view of another example of a semiconductor device according to an embodiment. [Figure 10a] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10c] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10d] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10e] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10f] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10g] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10h] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 10i] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] 1 is a diagram illustrating a data storage system including a semiconductor device according to an embodiment. [Figure 12] 1 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an embodiment. [Figure 13] FIG. 13 is a cross-sectional view schematically showing the semiconductor package of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 is a schematic plan view of a first example of a semiconductor device according to an embodiment.

[0013] Figures 2a to 2c are schematic cross-sectional views of the semiconductor device of Figure 1. Figures 2a to 2c show cross sections taken along the cutting lines II', II-II', and III-III' in Figure 1, respectively.

[0014] 1 to 2c, a semiconductor device 100 includes a peripheral circuit structure PERI including a first substrate 201 and a memory cell structure CELL including a second substrate 101, and first and second through wiring regions (TR1, TR2) each including a through contact plug 170 that electrically connects the peripheral circuit structure PERI and the memory cell structure CELL. The memory cell structure CELL is disposed above the peripheral circuit structure PERI, and the first and second through wiring regions (TR1, TR2) are disposed to connect the memory cell structure CELL and the peripheral circuit structure PERI by passing through the memory cell structure CELL. In one embodiment, the memory cell structure CELL may be disposed below the peripheral circuit structure PERI.

[0015] The peripheral circuit structure PERI includes a first substrate 201, source / drain regions 205 and an element isolation layer 210 in the first substrate 201, circuit elements 220 arranged on the first substrate 201, circuit contact plugs 270, circuit wiring lines 280, and a peripheral region insulating layer 290.

[0016] The first substrate 201 has an upper surface extending in the X and Y directions. An active region is defined in the first substrate 201 by an isolation layer 210. Impurity-containing source / drain regions 205 are disposed in a portion of the active region. The first substrate 201 includes a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The first substrate 201 is provided as a bulk wafer or an epitaxial layer.

[0017] The circuit elements 220 include planar transistors. Each circuit element 220 includes a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 are disposed in the first substrate 201 on either side of the circuit gate electrode 225.

[0018] A peripheral region insulating layer 290 is disposed on the first substrate 201 and on the circuit elements 220. Circuit contact plugs 270 penetrate the peripheral region insulating layer 290 and are connected to the source / drain regions 205. Electrical signals are applied to the circuit elements 220 through the circuit contact plugs 270. In a region not shown, the circuit contact plugs 270 are also connected to the circuit gate electrodes 225. Circuit wiring lines 280 are connected to the circuit contact plugs 270 and are disposed in multiple layers.

[0019] The memory cell structure CELL includes a second substrate 101 having a first region R1 and a second region R2, a first horizontal conductive layer 102 on the first region R1 of the second substrate 101, a horizontal insulating layer 110 arranged alongside the first horizontal conductive layer 102 on the second region R2 of the second substrate 101, a second horizontal conductive layer 104 on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a gate electrode 130 stacked on the second horizontal conductive layer 104, first and second isolation regions MS1, MS2a, and MS2b extending through a stacked structure GS of the gate electrode 130, an upper isolation region SS that penetrates a portion of the stacked structure GS, and a channel structure CH arranged to penetrate the stacked structure GS. The memory cell structure CELL further includes an interlayer insulating layer 120, a wiring line 180, and a cell region insulating layer 190 alternately stacked on the second substrate 101 around the gate electrode 130.

[0020] The first region R1 of the second substrate 101 is a region where memory cells are arranged, where gate electrodes 130 are vertically stacked and channel structures CH are arranged. The second region R2 is a region where gate electrodes 130 extend to different lengths, where the memory cells are electrically connected to peripheral circuit structures PER1. The second region R2 is arranged at least in one direction, for example, in the X direction, at least at one end of the first region R1.

[0021] The second substrate 101 has an upper surface extending in the X and Y directions. The second substrate 101 includes a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor includes silicon, germanium, or silicon-germanium. The second substrate 101 further includes an impurity. The second substrate 101 is provided as a polycrystalline semiconductor layer, such as a polycrystalline silicon layer, or an epitaxial layer.

[0022] The first and second horizontal conductive layers (102, 104) are sequentially stacked on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 does not extend into the second region R2 of the second substrate 101, and the second horizontal conductive layer 104 extends into the second region R2.

[0023] The first horizontal conductive layer 102 functions as a part of the common source line of the semiconductor device 100, for example, functions as the common source line together with the second substrate 101. As shown in the enlarged view of Figure 2a, the first horizontal conductive layer 102 is directly connected to the channel layer 140 around the channel layer 140.

[0024] The second horizontal conductive layer 104 contacts the second substrate 101 in a support region SR, which is a region where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 bends and extends onto the second substrate 101 while covering the ends of the first horizontal conductive layer 102 or the horizontal insulating layer 110 in the support region SR. The support region SR is a region for supporting an upper structure including the second horizontal conductive layer 104 when the first horizontal conductive layer 102 is formed.

[0025] As shown in FIG. 1 , in the first region R1, a portion of the support region SR overlaps with the first isolation region MS1 adjacent to the first through wiring region TR1 and extends in the X direction. In this specification, "overlapping" means that two regions overlap in the layout. However, as shown in FIGS. 2A and 2B , the first isolation region MS1 is structured to penetrate the support region SR, and is not structured to be located on the second horizontal conductive layer 104 of the support region SR. A portion of the support region SR extends along the first isolation region MS1 adjacent to the first through wiring region TR1. A support region SR is further disposed between the first isolation region MS1 and the first through wiring region TR1, overlapping the support region SR. The support region SR is disposed to extend in the Y direction at the boundary between the first region R1 and the second region R2. However, depending on the embodiment, the support region SR extending in the Y direction may be omitted.

[0026] In the second region R2, the support region SR is arranged to overlap all of the first and second isolation regions (MS1, MS2a, MS2b) and extend in the X direction. The support region SR extends continuously between at least some of the adjacent second isolation regions (MS2a, MS2b) along the X direction. In addition, a support region SR extending from a region overlapping the second auxiliary isolation region MS2b is further arranged between each of the first isolation regions MS1 and the second through wiring region TR2, which are arranged to overlap the support region SR. However, the arrangement of the support region SR in the second region R2 may be variously modified depending on the embodiment.

[0027] In this embodiment, the first and second isolation regions (MS1, MS2a, MS2b) that are closest to the first and second through wiring regions (TR1, TR2) along the Y direction overlap the support region SR, thereby preventing the etching agent from damaging the upper structure and causing defects in the through contact plug 170 when removing the horizontal insulating layer 110 to form the first horizontal conductive layer 102.

[0028] The first and second horizontal conductive layers 102 and 104 include a semiconductor material, for example, both of the first and second horizontal conductive layers 102 and 104 include polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 is a doped layer, and the second horizontal conductive layer 104 is a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. However, depending on the embodiment, the second horizontal conductive layer 104 may be replaced with an insulating layer.

[0029] The horizontal insulating layer 110 is disposed on the second substrate 101 alongside the first horizontal conductive layer 102 in at least a part of the second region R2. The horizontal insulating layer 110 includes first to third horizontal insulating layers (111, 112, 113) stacked in sequence on the second region R2 of the second substrate 101. The horizontal insulating layer 110 is a layer that remains after a portion of it is replaced by the first horizontal conductive layer 102 during the manufacturing process of the semiconductor device 100.

[0030] The horizontal insulating layer 110 includes silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first and third horizontal insulating layers (111, 113) and the second horizontal insulating layer 112 include different insulating materials. The first and third horizontal insulating layers (111, 113) include the same material. For example, the first and third horizontal insulating layers (111, 113) are made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of the same material as the sacrificial insulating layer 118.

[0031] The gate electrodes 130 are stacked vertically on the second substrate 101 and spaced apart to form a stack structure GS. The gate electrodes 130 include a lower gate electrode 130L forming a gate of a ground selection transistor, memory gate electrodes 130M forming a plurality of memory cells, and an upper gate electrode 130U forming a gate of a string selection transistor. The number of memory gate electrodes 130M forming memory cells is determined depending on the capacity of the semiconductor device 100. Depending on the embodiment, the upper and lower gate electrodes (130U, 130L) may each be one or more and may have the same or different structure as the memory gate electrode 130M. In one embodiment, the gate electrode 130 further includes a gate electrode 130 forming an erase transistor disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L and used for an erase operation using the gate induced drain leakage (GIDL) phenomenon. Furthermore, some of the gate electrodes 130, for example, the memory gate electrode 130M adjacent to the upper or lower gate electrode (130U, 130L), are dummy gate electrodes.

[0032] The gate electrodes 130 are stacked vertically and spaced apart on the first region R1 and extend from the first region R1 to the second region R2 by different lengths, forming a stepped structure. As shown in FIG. 2c, the gate electrodes 130 form a stepped structure between the gate electrodes 130 along the X direction. In one embodiment, at least some of the gate electrodes 130 form a gate group consisting of a certain number of gate electrodes 130, for example, two to six gate electrodes 130, and form a stepped structure between the gate groups along the X direction. In this case, the gate electrodes 130 of one gate group are also arranged to have a stepped structure in the Y direction. Due to the stepped structure, the gate electrodes 130 form a stepped shape in which the lower gate electrodes 130 extend longer than the upper gate electrodes 130, providing ends exposed to the upper part of the interlayer insulating layer 120. In one embodiment, the gate electrodes 130 have an upward thickness at the ends.

[0033] 1, the gate electrodes 130 are arranged to be separated from each other in the Y direction by a first isolation region MS1 extending in the X direction. The gate electrodes 130 between a pair of first isolation regions MS1 form one memory block, but the scope of the memory block is not limited thereto. Some of the gate electrodes 130, for example, the memory gate electrode 130M, form one layer within one memory block.

[0034] The gate electrode 130 includes a metal material, such as tungsten (W). In some embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In one embodiment, the gate electrode 130 further includes a diffusion barrier, such as tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0035] The interlayer insulating layers 120 are disposed between the gate electrodes 130. Like the gate electrodes 130, the interlayer insulating layers 120 are also disposed to be spaced apart from each other in a direction perpendicular to the top surface of the second substrate 101 and extend in the X direction. The interlayer insulating layers 120 include an insulating material such as silicon oxide or silicon nitride.

[0036] The first and second isolation regions (MS1, MS2a, MS2b) are arranged to extend in the X direction through the gate electrode 130. The first and second isolation regions (MS1, MS2a, MS2b) are arranged parallel to each other. The first and second isolation regions (MS1, MS2a, MS2b) are connected to the second substrate 101 by passing through the entire gate electrode 130 stacked on the second substrate 101. The first isolation region MS1 extends in the X direction, and the second isolation regions MS2a, MS2b extend intermittently between a pair of first isolation regions MS1 or are arranged only in a partial region. For example, the second central isolation region MS2a extends in the first region R1 and extends intermittently in the X direction in the second region R2. The second auxiliary isolation region MS2b is arranged only in the second region R2 and extends intermittently in the X direction. However, depending on the embodiment, the arrangement order and number of the first and second isolation regions (MS1, MS2a, MS2b) are not limited to those shown in FIG.

[0037] The first and second isolation regions (MS1, MS2a, MS2b) are not arranged overlapping the first and second through wiring regions (TR1, TR2), but are arranged spaced apart from the first and second through wiring regions (TR1, TR2). The first and second isolation regions (MS1, MS2a, MS2b) arranged closest to the first and second through wiring regions (TR1, TR2) overlap the support region SR. Specifically, of the first and second isolation regions (MS1, MS2a, MS2b), a pair of first isolation regions MS1 arranged closest to the first through wiring region TR1 in the Y direction overlaps the support region SR. Of the first and second isolation regions (MS1, MS2a, MS2b), a pair of first isolation regions MS1 arranged closest to the second through wiring region TR2 in the Y direction also overlaps the support region SR. However, depending on the arrangement of the first and second isolation regions (MS1, MS2a, MS2b), the isolation region closest to the first and second through-via regions (TR1, TR2) may be one of the second isolation regions (MS2a, MS2b). As shown in Figures 2a and 2b, the first isolation region MS1 closest to the first and second through-via regions (TR1, TR2) contacts the second horizontal conductive layer 104 on both sides of its lower end in the Y direction and is separated from the first horizontal conductive layer 102. The first isolation region MS1 is also separated from the horizontal insulating layer 110.

[0038] In the first region R1, the first and second isolation regions (MS1, MS2a, MS2b) except for a pair of first isolation regions MS1 arranged closest to the first through-via region TR1 along the Y direction are spaced apart from the support region SR so as not to overlap with the support region SR. For example, as shown in FIG. 2a, the second central isolation region MS2a adjacent to the first isolation region MS1 along the Y direction is arranged to penetrate the first horizontal conductive layer 102 at its lower end. Between the first isolation region MS1 and the second central isolation region MS2a, the side surfaces of the first horizontal conductive layer 102 and the horizontal insulating layer 110 contact each other. For example, the horizontal insulating layer 110 is interposed between the first isolation region MS1 and the first horizontal conductive layer 102 along the Y direction.

[0039] 2a and 2b, an isolation insulating layer 105 is disposed in the first and second isolation regions (MS1, MS2a, MS2b). The isolation insulating layer 105 has a shape in which its width decreases toward the second substrate 101 due to a high aspect ratio, but is not limited thereto, and may have side surfaces perpendicular to the top surface of the second substrate 101. In one embodiment, a conductive layer is further disposed in the isolation insulating layer 105 in the first and second isolation regions (MS1, MS2a, MS2b). In this case, the conductive layer functions as a common source line of the semiconductor device 100 or a contact plug connected to the common source line.

[0040] As shown in FIG. 1, the upper isolation region SS extends in the X direction in the first region R1 between the first isolation region MS1 and the second central isolation region MS2a and between the second central isolation region MS2a. The upper isolation region SS is disposed in a region where the first through-via region TR1 is not disposed. The upper isolation region SS is disposed to penetrate a portion of the gate electrodes 130, including the uppermost upper gate electrode 130U among the gate electrodes 130. The upper isolation region SS includes, for example, the upper gate electrode 130U, and separates a total of three gate electrodes 130 from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper isolation region SS may vary depending on the embodiment. The upper gate electrodes 130U separated by the upper isolation region SS form different string selection lines. The upper isolation region SS includes an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0041] The channel structures CH each form one memory cell string and are arranged in rows and columns in the first region R1, spaced apart from one another. The channel structures CH may be arranged in a lattice pattern or in a zigzag pattern in one direction. The channel structures CH have a columnar shape and have sloping side surfaces that become thinner as they approach the second substrate 101 according to the aspect ratio. In one embodiment, the channel structures CH arranged within a certain range from the first through-via region TR1 are dummy channels that do not actually form memory cell strings.

[0042] As shown in the enlarged view of FIG. 2a, a channel layer 140 is disposed within the channel structure CH. In the channel structure CH, the channel layer 140 is formed in an annular shape surrounding the channel-buried insulating layer 150 therein. However, depending on the embodiment, the channel layer 140 may have a columnar or rectangular shape without the channel-buried insulating layer 150. The channel layer 140 is connected to the first horizontal conductive layer 102 at its bottom. The channel layer 140 includes a semiconductor material such as polycrystalline silicon or single-crystalline silicon.

[0043] In the channel structure CH, a channel pad 155 is disposed on the channel layer 140. The channel pad 155 is disposed to cover an upper surface of the channel-buried insulating layer 150 and to be electrically connected to the channel layer 140. The channel pad 155 includes, for example, doped polycrystalline silicon.

[0044] The gate dielectric layer 145 is disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the gate dielectric layer 145 includes a tunneling layer, a charge storage layer, and a blocking layer stacked in sequence from the channel layer 140. The tunneling layer tunnels charges to the charge storage layer and includes, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer is a charge trap layer or a floating gate conductive layer. The blocking layer includes silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In one embodiment, at least a portion of the gate dielectric layer 145 extends horizontally along the gate electrode 130.

[0045] The dummy channel structures DCH have the same or similar structure as the channel structures CH and are arranged spaced apart from each other in rows and columns in a part of the first region R1 and the second region R2. The dummy channel structures DCH are not electrically connected to an upper wiring structure or, unlike the channel structures CH, do not form memory cell strings in the semiconductor device 100. In the first region R1, the dummy channel structures DCH are arranged in a region adjacent to the first through-via region TR1 and a region adjacent to the second region R2.

[0046] 2a and 2b, dummy channel structures DCH disposed adjacent to the first and second through-via regions (TR1, TR2) are disposed to penetrate the horizontal insulating layer 110 along the Z direction. The dummy channel structures DCH are surrounded at their lower portions by the second horizontal conductive layer 104 and the horizontal insulating layer 110 and are spaced apart from the first horizontal conductive layer 102. Specifically, the dummy channel structure DCH closest to the first and second through-via regions (TR1, TR2), for example, the first dummy channel structure, penetrates the interlayer insulating layer 120 and the sacrificial insulating layer 118 and penetrates the second horizontal conductive layer 104 and the horizontal insulating layer 110 at its lower end.

[0047] A dummy channel structure DCH, e.g., a second dummy channel structure, disposed next to the first dummy channel structure and adjacent to the first and second through-via regions (TR1, TR2), penetrates the interlayer insulating layer 120 and the gate electrode 130, and penetrates the second horizontal conductive layer 104 and the horizontal insulating layer 110 at its lower end. The second dummy channel structure is disposed, for example, within a first distance D1 along the Y direction from the first isolation region MS1, which is closest to the first and second through-via regions (TR1, TR2). The first distance D1 is, for example, in the range of about 400 μm to about 500 μm. In FIG. 2a, a channel structure CH disposed between the second central isolation region MS2a and the dummy channel structure DCH is also functionally a dummy channel structure and is referred to as a third dummy channel structure. In this case, the third dummy channel structure has a structure in which the channel layer 140 contacts the first horizontal conductive layer 102, similar to the channel structure CH.

[0048] The first and second through wiring regions (TR1, TR2) include wiring structures for electrically connecting the memory cell structure CELL and the peripheral circuit structure PERI to each other. The first through wiring region TR1 is disposed to penetrate the first region R1, and the second through wiring region TR2 is disposed to penetrate the second region R2. The first and second through wiring regions (TR1, TR2) include through contact plugs 170 extending in the Z direction through the second substrate 101 and an insulating region IR surrounding the through contact plugs 170. For example, one first through wiring region TR1 is disposed for each of a plurality of memory blocks, and one second through wiring region TR2 is disposed for each of a plurality of memory blocks. However, the number, size, arrangement, and shape of the first and second through wiring regions (TR1, TR2) may vary depending on the embodiment. For example, in some embodiments, one second through wiring region TR2 is also disposed for each of a plurality of memory blocks along the Y direction.

[0049] 1, the first and second through wiring regions (TR1, TR2) are arranged spaced apart from the first and second isolation regions (MS1, MS2a, MS2b). For example, the first and second through wiring regions (TR1, TR2) are arranged at the center of the pair of first isolation regions MS1, spaced apart from the first isolation regions MS1 adjacent to each other along the Y direction. With this arrangement, the sacrificial insulating layer 118 remains in the first and second through wiring regions (TR1, TR2).

[0050] The insulating region IR is disposed adjacent to the second substrate 101 and the gate electrode 130, penetrating the memory cell structure CELL. The insulating region IR may or may not include the gate electrode 130, and includes an insulating laminate structure made of an insulating material. The insulating region IR includes a substrate insulating layer 160, which is a first insulating layer disposed adjacent to the second substrate 101 and at the same height as the second substrate 101, and an interlayer insulating layer 120 and a sacrificial insulating layer 118, which are second and third insulating layers alternately stacked on the upper surface of the substrate insulating layer 160.

[0051] The substrate insulating layer 160, which is a first insulating layer, is disposed in a region where portions of the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 have been removed, and is disposed so as to be surrounded by the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104. The lower surface of the substrate insulating layer 160 is coplanar with the lower surface of the second substrate 101 or is located at a lower level than the lower surface of the second substrate 101. Depending on the embodiment, the substrate insulating layer 160 may include multiple insulating layers. The second insulating layer is formed by extending the interlayer insulating layer 120, and is therefore located at substantially the same height as the interlayer insulating layer 120. The third insulating layer includes a sacrificial insulating layer 118 and is located at substantially the same height as the gate electrode 130. When the first and second through-via regions (TR1, TR2) are defined based on the substrate insulating layer 160 region, the sacrificial insulating layer 118 extends partially outside the first and second through-via regions (TR1, TR2).

[0052] The substrate insulating layer 160, the interlayer insulating layer 120, and the sacrificial insulating layer 118, which form the insulating region IR, are made of insulating materials. For example, the substrate insulating layer 160, the interlayer insulating layer 120, and the sacrificial insulating layer 118 each include silicon oxide, silicon nitride, or silicon oxynitride. The substrate insulating layer 160 and the sacrificial insulating layer 118 may have different widths or may have the same width, depending on the embodiment.

[0053] The through contact plug 170 extends vertically through the entire insulating region IR and perpendicularly to the top surface of the second substrate 101 to electrically connect the memory cell structure CELL to the circuit element 220 of the peripheral circuit structure PERI. For example, the through contact plug 170 electrically connects the gate electrode 130 or the channel structure CH of the memory cell structure CELL to the circuit element 220 of the peripheral circuit structure PERI. The through contact plug 170 is connected at its upper portion to a wiring line 180, which is an upper wiring structure, but may also be connected to a separate contact plug depending on the embodiment. The through contact plug 170 is connected at its lower portion to a circuit wiring line 280, which is a lower wiring structure.

[0054] The via contact plugs 170 penetrate the interlayer insulating layer 120 and the sacrificial insulating layer 118 in the insulating region IR and penetrate the substrate insulating layer 160 below. The number, shape, and configuration of the via contact plugs 170 in each of the first and second via wiring regions (TR1, TR2) may vary depending on the embodiment. Depending on the embodiment, the via contact plugs 170 may have a shape in which multiple layers are connected. Also, depending on the embodiment, a wiring structure in the form of a wiring line may be further disposed in the insulating region IR in addition to the via contact plugs 170. The via contact plugs 170 include a conductive material, such as tungsten (W), copper (Cu), or aluminum (Al).

[0055] As shown in FIG. 1, the gate contact plug 175 is connected to the gate electrode 130, the upper surface of which is exposed at the upper portion of the gate electrode 130 in the second region R2.

[0056] The wiring line 180 constitutes an upper wiring structure electrically connected to a memory cell in the memory cell structure CELL. The wiring line 180 is electrically connected to, for example, the gate electrode 130 or the channel structure CH. The number of contact plugs and wiring lines constituting the wiring structure may vary depending on the embodiment. The wiring line 180 includes a metal, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0057] The cell region insulating layer 190 is disposed to cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 is made of an insulating material.

[0058] FIG. 3 is a schematic plan view of a second example of a semiconductor device according to an embodiment.

[0059] Figures 4a and 4b are schematic cross-sectional views of the semiconductor device of Figure 3. Figures 4a and 4b illustrate cross sections along section lines II' and II-II' of Figure 3, respectively.

[0060] 3 to 4b, the semiconductor device 100a differs from the embodiment of FIGS. 1 to 2c in the arrangement of the support region SRa, which is the region where the second horizontal conductive layer 104 directly contacts the second substrate 101. Specifically, the support region SRa arranged closest to the first and second through-hole wiring regions (TR1, TR2) is the support region SRa that overlaps the first isolation region MS1. Unlike the embodiment of FIGS. 1 to 2c, the support region SRa is not arranged between the first isolation region MS1, which is closest to the first and second through-hole wiring regions (TR1, TR2) along the Y direction, and the first and second through-hole wiring regions (TR1, TR2). As a result, as shown in FIGS. 4a and 4b, the support region SRa is not arranged below the ends of the sacrificial insulating layer 118 that form the first and second through-hole wiring regions (TR1, TR2).

[0061] As described above, the arrangement of the supporting region SRa, which is arranged independently without overlapping with the first and second isolation regions MS1, MS2a, and MS2b, may be variously changed depending on the embodiment.

[0062] 5a and 5b are plan views of third and fourth examples of semiconductor devices according to an embodiment.

[0063] 5a, the semiconductor device 100b differs from the embodiment of FIGS. 1 to 4b in the arrangement of the support region SRb, which is the region where the second horizontal conductive layer 104 directly contacts the second substrate 101. Specifically, in the second region R2, the support region SRb does not overlap all of the first and second isolation regions (MS1, MS2a, MS2b), but overlaps the first and second isolation regions (MS1, MS2a, MS2b) only in certain regions around the first and second through-hole wiring regions (TR1, TR2). For example, within a box region a second distance D2 in the X and Y directions from the second through-hole wiring region TR2, the first and second isolation regions (MS1, MS2a, MS2b) overlap the support region SRb. Even around the first through-hole wiring region TR1, portions of the first isolation region MS1 adjacent in the Y direction and the second isolation regions (MS2a, MS2b) adjacent in the X direction overlap the support region SRb.

[0064] In one embodiment, only one of the first and second isolation regions (MS1, MS2a, MS2b) adjacent to the first and second through wiring regions (TR1, TR2) in the X direction and the first and second isolation regions (MS1, MS2a, MS2b) adjacent to the first and second through wiring regions (TR1, TR2) in the Y direction overlaps the support region SRb. In this case, the first and second isolation regions (MS1, MS2a, MS2b) that do not overlap the support region SRb are arranged at a predetermined distance, for example, about 600 μm or more, from the first and second through wiring regions (TR1, TR2). In another embodiment, the support region SRb is arranged to extend in the Y direction between the first region R1 and the second region R2, and is omitted.

[0065] 5b, in the semiconductor device 100c, similar to the embodiment of FIG. 5a, in the second region R2, the support region SRc is arranged to overlap only the first and second isolation regions (MS1, MS2a, MS2b) adjacent to the first and second through-wiring regions (TR1, TR2). However, unlike the embodiment of FIG. 5a, the support region SRc extends to the other end along the extension direction of each of the first and second isolation regions (MS1, MS2a, MS2b).

[0066] In one embodiment, the support region SRc is arranged to overlap only the second isolation region (MS2a, MS2b) adjacent to the first and second through wiring regions (TR1, TR2) in the X direction, or only the first isolation region MS1 adjacent to the first and second through wiring regions (TR1, TR2) in the Y direction. Also, in one embodiment, the support region SRc arranged to extend in the Y direction between the first region R1 and the second region R2 is omitted.

[0067] FIG. 6 is a plan view of a fifth example of a semiconductor device according to an embodiment.

[0068] Fig. 7 is a cross-sectional view of the semiconductor device of Fig. 6. Fig. 7 illustrates a cross section taken along line II' of Fig. 6.

[0069] 6 and 7, the semiconductor device 100d differs from the embodiment of FIGS. 1 to 4b in the arrangement of the support region SRd, which is the region where the second horizontal conductive layer 104 directly contacts the second substrate 101. Specifically, in the first region R1, the first and second isolation regions (MS1, MS2a) adjacent to the first through-hole wiring region TR1 along the Y direction overlap the support region SRd. For example, not only the first isolation region MS1 closest to the first through-hole wiring region TR1 along the Y direction, but also the second central isolation region MS2a adjacent thereto are arranged to overlap the support region SRd. In this case, as shown in FIG. 7, the channel structure adjacent to the second central isolation region MS2a overlapping the support region SRd is a dummy channel structure DCH that penetrates the horizontal insulating layer 110 at its bottom.

[0070] In this manner, in one embodiment, a plurality of first and second isolation regions (MS1, MS2a, MS2b) adjacent to the first and second through wiring regions (TR1, TR2) are arranged to overlap the support region SRd.

[0071] FIG. 8 is a plan view of a sixth example of a semiconductor device according to an embodiment.

[0072] 8, the semiconductor device 100e differs from the embodiment of FIGS. 1 to 4b in the arrangement of the support region SRe, which is a region where the second horizontal conductive layer 104 directly contacts the second substrate 101. Specifically, in the first region R1, the support region SRe is arranged to overlap not only the first isolation region MS1 adjacent to the first through-hole wiring region TR1 along the Y direction, but also the first and second isolation regions (MS1, MS2a) spaced apart from the first through-hole wiring region TR1. For example, the support region SRe is arranged intermittently in an island shape along the first and second isolation regions (MS1, MS2a) spaced apart from the first through-hole wiring region TR1.

[0073] FIG. 9 is a cross-sectional view of another example of a semiconductor device according to an embodiment.

[0074] 9, in the semiconductor device 100f, the stacked structure of the gate electrode 130 is composed of vertically stacked lower and upper stacked structures, and the channel structure CHf includes vertically stacked first and second channel structures CH1 and CH2. The dummy channel structure DCHf is also arranged in the same shape as the channel structure CHf. This structure of the channel structure CHf can be introduced to stably form the channel structure CHf when there are a relatively large number of stacked gate electrodes 130.

[0075] The channel structure CHf has a shape in which a lower first channel structure CH1 and an upper second channel structure CH2 are connected, and has a bent portion due to the difference in width in the connection region. The channel structure CHf is in a state in which the channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 150 are connected to each other between the first channel structure CH1 and the second channel structure CH2. A channel pad 155 is disposed only on the upper end of the upper second channel structure CH2. However, depending on the embodiment, the first channel structure CH1 and the second channel structure CH2 may each include a channel pad 155. In this case, the channel pad 155 of the first channel structure CH1 is connected to the channel layer 140 of the second channel structure CH2. A relatively thick upper interlayer insulating layer 125 is disposed on the top of the lower stack structure. However, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be variously changed depending on the embodiment.

[0076] 10a to 10i are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment, and show an area corresponding to the area shown in FIG.

[0077] Referring to FIG. 10a, a peripheral circuit structure PERI including circuit elements 220 and lower wiring structures is formed on a first substrate 201, a second substrate 101 on which a memory cell structure CELL is provided is formed on top of the peripheral circuit structure PERI, and a horizontal insulating layer 110 is formed.

[0078] First, an isolation layer 210 is formed in a first substrate 201, and then a circuit gate dielectric layer 222 and a circuit gate electrode 225 are sequentially formed on the first substrate 201. The isolation layer 210 is formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 are formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 is formed of silicon oxide, and the circuit gate electrode 225 is formed of at least one of, but not limited to, polysilicon or a metal silicide layer. Next, a spacer layer 224 and source / drain regions 205 are formed on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. Depending on the embodiment, the spacer layer 224 may be composed of multiple layers. Next, an ion implantation process is performed to form the source / drain regions 205.

[0079] The circuit contact plug 270 of the lower wiring structure is formed by partially forming the peripheral region insulating layer 290, then etching away a portion of it, and filling it with a conductive material. The circuit wiring line 280 is formed, for example, by depositing a conductive material and then patterning it.

[0080] The peripheral region insulating layer 290 is made up of a plurality of insulating layers, a portion of which is formed in each step of forming the lower wiring structure, and a portion of which is formed on the uppermost circuit wiring line 280, so that the peripheral region insulating layer 290 is ultimately formed to cover the circuit elements 220 and the lower wiring structure.

[0081] Next, the second substrate 101 is formed on the peripheral region insulating layer 290. The second substrate 101 is made of, for example, polycrystalline silicon and is formed by a CVD process. The polycrystalline silicon that forms the second substrate 101 contains impurities.

[0082] Next, first to third horizontal insulating layers (111, 112, 113) constituting the horizontal insulating layer 110 are sequentially stacked on the second substrate 101. The horizontal insulating layer 110 is a layer that will be partially replaced by the first horizontal conductive layer 102 of FIG. 2a in a subsequent process. The first and third horizontal insulating layers (111, 113) contain a different material from the second horizontal insulating layer 112. For example, the first and third horizontal insulating layers (111, 113) are made of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is made of the same material as the sacrificial insulating layer 118.

[0083] The first to third horizontal insulating layers (111, 112, 113) are removed in the support region SR by a patterning process, so that the horizontal insulating layer 110 is formed only in the region excluding the support region SR, and the second substrate 101 is exposed in the support region SR.

[0084] Referring to FIG. 10 b , a second horizontal conductive layer 104 is formed on the horizontal insulating layer 110 .

[0085] The second horizontal conductive layer 104 is formed on the horizontal insulating layer 110 and contacts the second substrate 101 at the support region SR. Thus, the second horizontal conductive layer 104 bends along the edge of the horizontal insulating layer 110 to cover the edge and extend onto the second substrate 101.

[0086] Referring to FIG. 10c, a substrate insulating layer 160 is formed penetrating the second substrate 101, and sacrificial insulating layers 118 and interlayer insulating layers 120 are alternately stacked thereon.

[0087] The substrate insulating layer 160 is formed by removing portions of the second substrate 101, horizontal insulating layer 110, and second horizontal conductive layer 104 in the areas corresponding to the first and second through-hole wiring regions (TR1, TR2) and then filling the areas with an insulating material. The substrate insulating layer 160 may be formed over the entire area of the first and second through-hole wiring regions (TR1, TR2), or may be formed to be smaller than the entire area. After filling the insulating material, a planarization process is further performed using a chemical mechanical polishing (CMP) process. As a result, the top surface of the substrate insulating layer 160 is substantially coplanar with the top surface of the second horizontal conductive layer 104.

[0088] Next, the sacrificial insulating layer 118 is a layer that will be partially replaced by the gate electrode 130 (see FIG. 2a) in a subsequent process. The sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120 and is formed of a material that has etching selectivity and can be etched under specific etching conditions with respect to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 is made of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 is made of a different material from the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. Depending on the embodiment, the thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118 may not all be the same. The thicknesses and the number of layers formed may vary from those shown in the figure. As a result, the insulating regions IR of the first and second through-via regions (TR1, TR2) are formed.

[0089] Next, a cell region insulating layer 190 is formed to cover the upper portion of the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120.

[0090] Referring to FIG. 10d, a channel structure CH and a dummy channel structure DCH are formed through the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120.

[0091] First, the upper isolation region SS is formed by removing a portion of the sacrificial insulating layer 118 and the interlayer insulating layer 120. The upper isolation region SS is formed by exposing the region where the upper isolation region SS will be formed using a separate mask layer, removing a predetermined number of the sacrificial insulating layer 118 and the interlayer insulating layer 120 from the top, and then depositing an insulating material. The upper isolation region SS extends downward in the Z direction beyond the region where the upper gate electrode 130U of FIG. 1 will be formed.

[0092] Next, the channel structures CH and the dummy channel structures DCH are formed by anisotropically etching the sacrificial insulating layer 118, the interlayer insulating layer 120, and the horizontal insulating layer 110 to form hole-shaped channel holes, which are then filled. In one embodiment, the dummy channel structures DCH are formed to be larger than the channel structures CH. Depending on the height of the stacked structures, the sidewalls of the channel holes may not be perpendicular to the top surface of the second substrate 101. The channel holes are formed by recessing a portion of the second substrate 101.

[0093] Next, at least a portion of the gate dielectric layer 145, the channel layer 140, the channel buried insulating layer 150, and the channel pad 155 are sequentially formed in each channel hole to form the channel structure CH and the dummy channel structure DCH. The gate dielectric layer 145 is formed to a uniform thickness using an ALD or CVD process. In this step, all or part of the gate dielectric layer 145 is formed, and a portion that extends vertically to the second substrate 101 along the channel hole is formed in this step. The channel layer 140 is formed on the gate dielectric layer 145 in the channel hole. The channel buried insulating layer 150 is formed to fill the channel hole and is made of an insulating material. However, depending on the embodiment, a conductive material other than the channel buried insulating layer 150 may be used to fill the gap between the channel layers 140. The channel pad 155 is made of a conductive material, for example, polycrystalline silicon.

[0094] Referring to FIG. 10e, openings (OP1, OP2) are formed through the stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120, and sacrificial spacers 115 are formed on the inner walls of the openings (OP1, OP2).

[0095] First, before forming the openings OP, a cell region insulating layer 190 is further formed on the channel structure CH and the dummy channel structure DCH. The openings OP1 and OP2 are formed at the positions of the first and second isolation regions MS1, MS2a, and MS2b in FIG. 1. The openings OP1 and OP2 are formed by forming a mask layer using a photolithography process and anisotropically etching the stacked structure. The openings OP1 and OP2 are formed in the form of trenches extending in the X direction.

[0096] The sacrificial spacers 115 are formed on the inner walls of the openings OP1 and OP2. The sacrificial spacers 115 include a material that has etching selectivity with respect to the sacrificial insulating layer 118, the interlayer insulating layer 120, and the horizontal insulating layer 110. For example, the sacrificial spacers 115 include polycrystalline silicon.

[0097] The first opening OP1 overlapping the horizontal insulating layer 110 is formed so that the upper surface of the horizontal insulating layer 110 is exposed at its lower end, and then the lower end is extended when the sacrificial spacer 115 is formed, so that the second horizontal insulating layer 112 is exposed at its lower end. The second opening OP2 overlapping the support region SR is formed so that the second substrate 101 is exposed at its lower end by penetrating the second horizontal conductive layer 104.

[0098] Referring to FIG. 10f, the sacrificial spacer 115 is partially oxidized to form a sacrificial oxide layer 116, and then the second horizontal insulating layer 112 is removed to form a first tunnel portion TL1.

[0099] The sacrificial oxide layer 116 is formed by partially oxidizing the sacrificial spacer 115. According to an embodiment, before forming the sacrificial oxide layer 116, a wet etching process may be further performed to partially remove the first and third horizontal insulating layers (111, 113) below the first opening OP1. In this case, after the first and third horizontal insulating layers (111, 113) are partially removed, the exposed second horizontal conductive layer 104 and the second substrate 101 are also oxidized during the process of forming the sacrificial oxide layer 116.

[0100] Next, the second horizontal insulating layer 112 exposed through the first opening OP1 is selectively removed to form the first tunnel portion TL1, for example, by a wet etching process.

[0101] The openings adjacent to the first and second through-hole regions (TR1, TR2) are second openings OP2 formed to overlap the support region SR. As a result, the second horizontal insulating layer 112 is not disposed or removed below the second openings OP2, which prevents the etchant used to remove the second horizontal insulating layer 112 from flowing upward and damaging the upper structures, thereby preventing damage to the insulating regions IR of the first and second through-hole regions (TR1, TR2).

[0102] Referring to FIG. 10g, the first and third horizontal insulating layers (111, 113) are removed within the first tunnel portion TL1, the first horizontal conductive layer 102 is formed, and then a portion of the sacrificial insulating layer 118 is removed through the openings (OP1, OP2) to form the second tunnel portion TL2.

[0103] The first and third horizontal insulating layers 111 and 113 are selectively removed with respect to the interlayer insulating layer 120. When the first and third horizontal insulating layers 111 and 113 are removed, a portion of the gate dielectric layer 145 exposed in the area where the second horizontal insulating layer 112 has been removed is also removed, exposing the channel layer 140 through the first tunnel portion TL1. The first horizontal conductive layer 102 is formed by depositing a conductive material in the first tunnel portion TL1 where the horizontal insulating layer 110 has been removed. Next, the sacrificial spacer 115 and the sacrificial oxide layer 116 are removed.

[0104] Next, the sacrificial insulating layer 118 is removed from areas excluding the first and second through-hole regions (TR1, TR2) (see FIG. 1) and their surroundings. The sacrificial insulating layer 118 is selectively removed with respect to the interlayer insulating layer 120, the first horizontal conductive layer 102, the second horizontal conductive layer 104, and the substrate insulating layer 160, for example, by wet etching. As a result, a plurality of second tunnel portions TL2 are formed between the interlayer insulating layers 120, and partial sidewalls of the channel structures CH and the dummy channel structures DCH are exposed through the second tunnel portions TL2.

[0105] The regions where the first and second through wiring regions (TR1, TR2) are formed include regions where the sacrificial insulating layer 118 remains because they are separated from the openings (OP1, OP2) and cannot be reached by the etchant. Therefore, the first and second through wiring regions (TR1, TR2) are formed in the center of the openings (OP1, OP2) between adjacent openings (OP1, OP2). The region where the sacrificial insulating layer 118 remains does not coincide with the region where the substrate insulating layer 160 is disposed. Therefore, when the first and second through wiring regions (TR1, TR2) are defined based on the substrate insulating layer 160, the sacrificial insulating layer 118 can be described as being located not only inside the first and second through wiring regions (TR1, TR2) but also around the first and second through wiring regions (TR1, TR2).

[0106] Referring to FIG. 10h, a conductive material is filled in the second tunnel portion TL2 to form the gate electrode 130, and an isolation insulating layer 105 is formed in the openings OP1 and OP2.

[0107] The second tunnel portion TL2 is filled with a conductive material forming the gate electrode 130. The conductive material may include metal, polycrystalline silicon, or a metal silicide material. The side of the gate electrode 130 contacts the side of the sacrificial insulating layer 118. After forming the gate electrode 130, the conductive material deposited in the openings OP1 and OP2 is removed through an additional process.

[0108] The isolation insulating layer 105 is formed to fill the openings (OP1, OP2).

[0109] Referring to FIG. 10i, via holes VH for forming through contact plugs 170 (see FIG. 2a) are formed in the first and second through wiring regions TR1 and TR2.

[0110] Before forming the via holes VH, a cell region insulating layer 190 is further formed to cover the isolation insulating layer 105. Next, via holes VH are formed to penetrate the cell region insulating layer 190 and the insulating region IR. At the bottom ends of the via holes VH, the circuit wiring lines 280 of the peripheral circuit structure PERI are exposed.

[0111] Next, referring to FIG. 2a, the via hole VH is filled with a conductive material to form a through contact plug 170, thereby forming first and second through wiring regions (TR1, TR2), and a wiring line 180 connected to the upper end of the through contact plug 170 is formed to manufacture the semiconductor device 100.

[0112] FIG. 11 is a diagram schematically illustrating a data storage system including a semiconductor device according to an embodiment.

[0113] 11 , a data storage system 1000 includes a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The data storage system 1000 is a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 is a solid state drive device (SSD) device, a Universal Serial Bus (USB), a computer system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0114] The semiconductor device 1100 is a non-volatile memory device, such as the NAND flash memory device described above with reference to FIGS. 1 to 9. The semiconductor device 1100 includes a first structure 1100F and a second structure 1100S on the first structure 1100F. In one embodiment, the first structure 1100F is disposed beside the second structure 1100S. The first structure 1100F is a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0115] In the second structure 1100S, each memory cell string CSTR includes lower transistors (LT1, LT2) adjacent to a common source line CSL, upper transistors (UT1, UT2) adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiment.

[0116] In one embodiment, the upper transistors (UT1, UT2) comprise string select transistors, and the lower transistors (LT1, LT2) comprise ground select transistors. The gate lower lines (LL1, LL2) are the gate electrodes of the lower transistors (LT1, LT2), respectively. The word line WL is the gate electrode of the memory cell transistor MCT, and the gate upper lines (UL1, UL2) are the gate electrodes of the upper transistors (UT1, UT2), respectively.

[0117] In one embodiment, the lower transistors (LT1, LT2) include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors (UT1, UT2) include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 is used in an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0118] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 are electrically connected to the decoder circuit 1110 through first connecting lines 1115 that extend from the first structure 110F to the second structure 1100S. The bit line BL is electrically connected to the page buffer 1120 through second connecting lines 1125 that extend from the first structure 110F to the second structure 1100S.

[0119] In the first structure 110F, a decoder circuit 1110 and a page buffer 1120 perform control operations on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 are controlled by a logic circuit 1130. The semiconductor device 1000 communicates with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 is electrically connected to the logic circuit 1130 through an input / output connecting wiring 1135 extended to the second structure 1100S within the first structure 110F.

[0120] The controller 1200 includes a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the data storage system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 controls the multiple semiconductor devices 1000.

[0121] The processor 1210 controls the overall operation of the data storage system 1000, including the controller 1200. The processor 1210 operates according to predetermined firmware and controls the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 includes a NAND interface 1221 that processes communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be written to the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. are transmitted through the NAND interface 1221. The host interface 1230 provides a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 controls the semiconductor device 1100 in response to the control command.

[0122] FIG. 12 is a perspective view schematically illustrating a data storage system including a semiconductor device according to an embodiment.

[0123] 12, a data storage system 2000 according to an embodiment of the present invention includes a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 are connected to the controller 2002 by wiring patterns 2005 formed on the main board 2001.

[0124] The main board 2001 includes a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 vary depending on the communication interface between the data storage system 2000 and the external host. In one embodiment, the data storage system 2000 communicates with the external host via one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Storage (UFS). In one embodiment, the data storage system 2000 operates using power supplied from the external host through the connector 2006. The data storage system 2000 further includes a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0125] The controller 2002 records data to or reads data from the semiconductor package 2003 to improve the operating speed of the data storage system 2000 .

[0126] DRAM 2004 is a buffer memory for reducing the speed difference between semiconductor package 2003, which is a data storage space, and an external host. DRAM 2004 included in data storage system 2000 also operates as a kind of cache memory, providing space for temporarily storing data during control operations for semiconductor package 2003. When data storage system 2000 includes DRAM 2004, controller 2002 further includes a DRAM controller for controlling DRAM 2004 in addition to a NAND controller for controlling semiconductor package 2003.

[0127] The semiconductor package 2003 includes first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b includes a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each of the semiconductor chips 2200, a connecting structure 2400 that electrically connects the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 that covers the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0128] The package substrate 2100 is a printed circuit board including package upper pads 2130. Each semiconductor chip 2200 includes input / output pads 2210. The input / output pads 2210 correspond to the input / output pads 1101 in FIG. 11. Each semiconductor chip 2200 includes a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 includes the semiconductor device described above with reference to FIGS. 1 to 9.

[0129] In one embodiment, the connecting structure 2400 is a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 are electrically connected to each other by a bonding wire method and are electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages (2003a, 2003b), the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV) instead of the connecting structure 2400 using a bonding wire method.

[0130] In one embodiment, the controller 2002 and the semiconductor chip 2200 are included in one package. In another embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0131] Fig. 13 is a cross-sectional view schematically illustrating the semiconductor package of Fig. 12. Fig. 13 illustrates one embodiment of the semiconductor package 2003 of Fig. 12, and conceptually illustrates a region obtained by cutting the semiconductor package 2003 of Fig. 12 along cutting line IV-IV'.

[0132] 13, in a semiconductor package 2003, a package substrate 2100 is a printed circuit board. The package substrate 2100 includes a package substrate body 2120, upper package pads 2130 disposed on the upper surface of the package substrate body 2120, lower package pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper package pads 2130 and the lower package pads 2125 within the package substrate body 2120. The upper package pads 2130 are electrically connected to a connecting structure 2400. The lower package pads 2125 are connected to a wiring pattern 2005 of a main substrate 2010 of a data storage system 2000 through a conductive connecting portion 2800, as shown in FIG. 12.

[0133] Each of the semiconductor chips 2200 includes a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 includes a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 includes a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an isolation region 3230 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a gate contact plug 175 (see FIG. 1) electrically connected to a word line WL (see FIG. 11) of the gate stack structure 3210. As described above with reference to FIGS. 1 to 2b, in each of the semiconductor chips 2200, the first isolation region MS1 adjacent to the through wiring region TR1 overlaps the support region SR.

[0134] Each of the semiconductor chips 2200 includes a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 passes through the gate stack structure 3210 and is further disposed outside the gate stack structure 3210. Each of the semiconductor chips 2200 further includes an input / output connecting wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and an input / output pad 2210 electrically connected to the input / output connecting wiring 3265.

[0135] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0136] BL Bit Line CELL Memory cell structure CH, CHf channel structure CH1, CH2 1st and 2nd channel structures CSL Common Source Line CSTR Memory Cell String DCH, DCHf dummy channel structure GS laminated structure IR isolation area LL1, LL2 1st and 2nd gate lower lines LT1 Lower erase control transistor (lower transistor) LT2 Ground selection transistor (lower transistor) MCT memory cell transistor MS1, MS2 1st and 2nd separation area MS2a 2nd (center) separation area MS2b 2nd (auxiliary) separation area OP1, OP2 (first, second) openings PERI Peripheral Circuit Structure R1, R2 1st, 2nd area SS upper separation area SR support area SRa, SRb, SRc, SRd, SRe support area TL1, TL2 1st and 2nd tunnel sections TR1, TR2 1st and 2nd through wiring area UT1 String selection transistor (upper transistor) UT2 Upper erase control transistor (upper transistor) UL1, UL2 1st and 2nd gate upper lines VH Beer Hall WL Word Line 100, 100a, 100b, 100c, 100d, 100e, 1100 semiconductor device 101 Second board 102, 104 First and second horizontal conductive layers 105 Separation insulating layer 110 Horizontal insulation layer 111, 112, 113 1st to 3rd horizontal insulating layers 115 Sacrificial Spacer 116 Sacrificial oxide layer 118 Sacrificial insulating layer (third insulating layer) 120 Interlayer insulating layer (second insulating layer) 130 gate electrode 130L, 130U Lower and upper gate electrodes 130M memory gate electrode 140 Channel Layer 145 Gate Dielectric Layer 150 channel buried insulation layer 155 Channel Pad 160 Substrate insulating layer (first insulating layer) 170 through contact plug 175 Gate contact plug 180 Wiring Line 190 Cell area insulating layer 201 First board 205 Source / Drain Region 210 Element isolation layer 220 Circuit Elements 222 Circuit gate dielectric layer 224 spacer layer 225 Circuit gate electrode 270 Circuit Contact Plug 280 Circuit Wiring Line 290 Peripheral area insulating layer 1000 Data Storage System 1100F, 3100 1st structure 1100S, 3200 2nd structure 1101, 2210 Input / Output Pads 1110 decoder circuit 1115, 1125 1st and 2nd connection wiring 1120 page buffers 1130 Logic Circuit 1135, 3265 input / output connection wiring 1200, 2002 controller 1210 processor 1220 NAND controller 1221 NAND interface (I / F) 1230 Host Interface (I / F) 2000 Data Storage System 2001, 2010 main board 2003 Semiconductor Package 2003a, 2003b First and second semiconductor packages 2004 DRAM 2005 Wiring Pattern 2006 Connector 2100 package substrate 2120 Package substrate main body 2125, 2130 Lower and upper package pads 2135 Internal wiring 2200 semiconductor chips 2300 Adhesive layer 2400 Connected structures 2500 molding layer 2800 Conductive connection part 3010 Semiconductor substrate 3110 Peripheral wiring 3205 Common Source Line 3210 Gate stack structure 3220 Channel Structures 3230 Separation area 3240 bit lines 3245 Through Wiring

Claims

1. a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a memory cell structure including: a second substrate disposed on the first substrate; gate electrodes stacked and spaced apart from each other along a first direction perpendicular to one surface of the second substrate; channel structures extending through the gate electrodes along the first direction and each including a channel layer; isolation regions extending through the gate electrodes in a second direction perpendicular to the first direction and spaced apart from each other along a third direction perpendicular to the first and second directions; first horizontal conductive layers extending on the second substrate and contacting the channel layers of the channel structures; a horizontal insulating layer disposed next to the first horizontal conductive layer; and a second horizontal conductive layer disposed on the first horizontal conductive layer and contacting a support region of the second substrate where the first horizontal conductive layer and the horizontal insulating layer are not disposed; a through wiring region including an insulating region and a through contact plug that penetrates the insulating region and the second substrate in the first direction and electrically connects the memory cell structure and the peripheral circuit structure, the through wiring region being disposed between first isolation regions among the isolation regions; a first portion of the support region extending along the first separation region; the isolation region further includes second isolation regions spaced apart from the first isolation regions along the third direction, the second isolation region is spaced apart from the support region so as not to overlap the support region; a first insulating layer formed on the first insulating layer and a second insulating layer formed on the second insulating layer; a first insulating layer formed on the first insulating layer and a second insulating layer formed on the second insulating layer;

2. 2. The semiconductor device of claim 1, wherein each of the first isolation regions contacts the second horizontal conductive layer on both sides of the first isolation region in the third direction and is spaced apart from the first horizontal conductive layer.

3. the second substrate has a first region and a second region; the gate electrode is stacked along the first direction in the first region and defines a stepped shape along the second direction in the second region; The semiconductor device according to claim 1 , wherein the through wiring region is disposed in the first region.

4. the memory cell structure further includes a dummy channel structure disposed around the first isolation region; The semiconductor device according to claim 1 , wherein the dummy channel structure penetrates the horizontal insulating layer.

5. The semiconductor device according to claim 1 , wherein the second portion of the support region extends in the second direction between the through wiring region and the first isolation region along the third direction.

6. A peripheral circuit structure including a first substrate and circuit elements on the first substrate; a memory cell structure including: a second substrate disposed on the first substrate; gate electrodes stacked and spaced apart from each other along a first direction perpendicular to one surface of the second substrate; channel structures extending through the gate electrodes along the first direction and each including a channel layer; isolation regions extending through the gate electrodes in a second direction perpendicular to the first direction and spaced apart from each other along a third direction perpendicular to the first and second directions; first horizontal conductive layers extending on the second substrate and contacting the channel layers of the channel structures; a horizontal insulating layer disposed next to the first horizontal conductive layer; and a second horizontal conductive layer disposed on the first horizontal conductive layer and contacting a support region of the second substrate where the first horizontal conductive layer and the horizontal insulating layer are not disposed; a through wiring region including an insulating region and a through contact plug that penetrates the insulating region and the second substrate in the first direction and electrically connects the memory cell structure and the peripheral circuit structure, the through wiring region being disposed between first isolation regions among the isolation regions; a first portion of the support region extending along the first separation region; the isolation regions further include second isolation regions adjacent to each of the first isolation regions; The semiconductor device, wherein the second isolation region is disposed in the support region and penetrates the second horizontal conductive layer.

7. the second substrate has a first region and a second region; the gate electrode is stacked along the first direction in the first region and defines a stepped shape along the second direction in the second region; The semiconductor device according to claim 1 , wherein the through wiring region is disposed in the second region.

8. 8. The semiconductor device according to claim 7, wherein the support region is disposed so as to surround at least a part of the isolation region adjacent to the through-wiring region along the second direction and the third direction.

9. the horizontal insulating layer includes a first horizontal insulating layer, a second horizontal insulating layer, and a third horizontal insulating layer sequentially stacked on the second substrate; 2. The semiconductor device according to claim 1, wherein the first horizontal insulating layer and the third horizontal insulating layer contain the same material.

10. a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a memory cell structure including: a second substrate disposed on the first substrate; a first horizontal conductive layer extended on the second substrate; a horizontal insulating layer disposed alongside the first horizontal conductive layer; a second horizontal conductive layer disposed on the first horizontal conductive layer and in contact with a support region of the second substrate where the first horizontal conductive layer and the horizontal insulating layer are not disposed; gate electrodes stacked on the second horizontal conductive layer and spaced apart from each other along a first direction; channel structures extending through the gate electrodes along the first direction and each including a channel layer; and isolation regions extending through the gate electrodes in a second direction different from the first direction and disposed spaced apart from each other along a third direction different from the first and second directions; a through wiring region including through contact plugs extending in the first direction and electrically connecting one or more components of the memory cell structure and one or more circuit components of the peripheral circuit structure, the isolation region includes a first isolation region disposed adjacent to the through contact plug along the third direction; the first isolation region penetrates the second horizontal conductive layer and is spaced apart from the first horizontal conductive layer; the separation region further includes a second separation region spaced apart from the support region; the first isolation region is disposed between the second isolation region and the through wiring region; The semiconductor device, wherein the second isolation region penetrates the first horizontal conductive layer and the second horizontal conductive layer.

11. the memory cell structure further includes a first dummy channel structure and a second dummy channel structure disposed between each of the first isolation regions and each of the second isolation regions; The semiconductor device of claim 10 , wherein the channel layer of each of the first dummy channel structures contacts the first horizontal conductive layer.

12. The semiconductor device of claim 11 , wherein each channel layer of the second dummy channel structure is spaced apart from the first horizontal conductive layer.

13. The semiconductor device of claim 11 , wherein the horizontal insulating layer is disposed between the second substrate and the second horizontal conductive layer and surrounds the second dummy channel structure.

14. 11. The semiconductor device of claim 10, wherein the second horizontal conductive layer directly contacts the second substrate on both sides of the first isolation region along the third direction to define each of the support regions.

15. A semiconductor device as described in Claim 14, characterized in that the second horizontal conductive layer is extended conformally onto each end of the horizontal insulating layer on both sides of the first isolation region along the third direction.

16. 1. A data storage system comprising: a semiconductor device; and a controller electrically coupled to the semiconductor device through an input / output pad, The semiconductor device includes: a peripheral circuit structure including a first substrate and circuit elements on the first substrate; a memory cell structure including: a second substrate disposed on the first substrate; a first horizontal conductive layer extended on the second substrate; a second horizontal conductive layer disposed on the first horizontal conductive layer; gate electrodes stacked on the second horizontal conductive layer in a first direction and spaced apart from each other; channel structures extending through the gate electrodes in the first direction and including channel layers; and isolation regions extending through the gate electrodes in a second direction different from the first direction and spaced apart from each other in a third direction different from the first and second directions; an input / output pad electrically connected to the circuit element; a through wiring region including through contact plugs extending in the first direction and electrically connecting one or more components of the memory cell structure and one or more circuit components of the peripheral circuit structure, the isolation region includes a first isolation region disposed adjacent to the through contact plug along the third direction; the first isolation region penetrates the second horizontal conductive layer and is spaced apart from the first horizontal conductive layer; The memory cell structure of the semiconductor device further includes a horizontal insulating layer extending alongside the first horizontal conductive layer, the second horizontal conductive layer directly contacts the second substrate in a support region where the first horizontal conductive layer and the horizontal insulating layer are not disposed; a first portion of the support region contacting the first separation region and extending along the first separation region; The data storage system of claim 1, wherein the second portion of the support region extends in the second direction between the through wiring region and the first isolation region along the third direction.

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