Power supply circuit and semiconductor device

Abstract

To provide a power supply circuit that starts in a shorter period of a time and is capable of protecting the application of ESD stress, and a semiconductor device.SOLUTION: According to an embodiment, a power supply circuit includes a first transistor, a feedback voltage generation circuit, a first voltage generation circuit, and a protection circuit. The first transistor is connected between an input terminal for receiving an input voltage and an output terminal for outputting an output voltage. The feedback voltage generation circuit divides the output voltages to generate a feedback voltage. The first voltage generation circuit supplies voltage to a first control terminal of the first transistor through a first node such that the output voltage coincides with or approximates a setting value on the basis of the feedback voltage and a reference voltage. The protection circuit outputs voltage to the first control terminal such that the first transistor becomes non-conductive or assumes a state showing a prescribed high resistance value in the case where the input voltage exceeds a first threshold voltage to thereby increase within a prescribed time.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a power supply circuit and a semiconductor device. [Background technology]

[0002] Semiconductor devices incorporate electrostatic protection circuits to protect internal circuits from electrostatic discharge (ESD) stress. However, when ESD stress with a fast rise time is applied, the electrostatic protection circuits do not function properly and there is a risk of damaging the internal circuits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-257225 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a power supply circuit and a semiconductor device that can provide protection against the application of ESD stress. [Means for solving the problem]

[0005] According to this embodiment, the power supply circuit includes a first transistor, a feedback voltage generation circuit, a first voltage generation circuit, and a protection circuit. The first transistor is connected between an input terminal that receives an input voltage and an output terminal that outputs an output voltage. The feedback voltage generation circuit divides the output voltage to generate a feedback voltage. The first voltage generation circuit supplies a voltage to a first control terminal of the first transistor via a first node based on the feedback voltage and a reference voltage so that the output voltage matches or approximates a set value. When the input voltage increases beyond a first threshold voltage within a predetermined time, the protection circuit outputs a voltage to the first control terminal that causes the first transistor to become non-conductive or exhibit a predetermined high resistance value. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic configuration diagram showing an example of an integrated circuit of a semiconductor device. [Figure 2] Block diagram showing an example configuration of a digital isolator for one channel. [Figure 3] FIG. 2 is a circuit diagram showing a configuration example of a power supply circuit. [Figure 4] FIG. 2 is a circuit diagram showing a configuration example of a protection circuit. [Figure 5] 1A and 1B are diagrams illustrating an example of an electrostatic protection circuit and an operation of the protection circuit. [Figure 6] FIG. [Figure 7] FIG. 1 is a circuit diagram showing a configuration example of a power supply circuit of a comparative example. [Figure 8] FIG. 10 is a diagram showing a simulation result of a comparative example. [Figure 9] FIG. 10 is a circuit diagram showing an example of the configuration of a protection circuit according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram showing an example of the configuration of a protection circuit according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the characteristic configurations and operations of the power supply circuit and the semiconductor device will be mainly described, but the power supply circuit and the semiconductor device may have configurations and operations that are omitted from the following description.

[0008] (First embodiment) FIG. 1 is a schematic diagram showing an example of an integrated circuit of a semiconductor device 1. The semiconductor device 1 is configured as, for example, an 8-pin integrated circuit. As shown in FIG. 1, the semiconductor device 1 is, for example, an example of a two-channel digital isolator using galvanic isolation. The semiconductor device 1 has a power supply pin arrangement and a GND pin arrangement on the primary side and the secondary side, respectively. Furthermore, the semiconductor device 1 is a chip using two or more withstand voltage levels: a high withstand voltage for an external interface and a low withstand voltage for internal use. For example, 5 volts is used as the high withstand voltage for the external interface, and 1.5 volts is used as the low withstand voltage for internal use.

[0009] In this digital isolator, an input signal input to a signal input terminal VIN1 on the primary side is output as an output signal from a signal output terminal VOUT1 on the secondary side via a galvanically isolated transformer. For example, when a logic signal of "1" is input to the signal input terminal VIN1, the modulated signal passes through the galvanically isolated transformer, is demodulated, and the logic signal of "1" is output from the signal output terminal VOUT1. Note that, although this embodiment will be described using a digital isolator as an example of the configuration of the semiconductor device 1, this is not limiting. For example, the present invention can be applied to the configuration of semiconductor devices other than digital isolators as long as they are circuits that require protection functions against ESD stress.

[0010] Fig. 2 is a block diagram showing an example configuration of one channel of the digital isolator 2 shown in Fig. 1. As shown in Fig. 2, the digital isolator 2 is composed of a primary-side chip 10 and a secondary-side chip 20 that are galvanically isolated from each other. The digital isolator 2 includes a plurality of power supply circuits 100, an input buffer 102, a first level shifter 104, a modulator 106, a drive circuit (DRV) 108, a transformer 110, an amplifier (RF Amp) 112, a detection circuit 114, a second level shifter 116, and an output buffer 118.

[0011] The lower part of FIG. 2 schematically shows the signals output by each circuit. The vertical axis indicates the signal level, and the horizontal axis indicates time. Signals G100 to G106 indicate corresponding signals. That is, the diagram shows how signal G100 changes over time as signals G102 to G106. More specifically, signal G100 indicates an example of a square wave logic signal input from signal input terminal VIN1 to input buffer 102. For example, a 5-volt high input (HIGH INPUT) corresponds to "1," and a 0-volt low input (LOW INPUT) corresponds to "0."

[0012] Signal G102 represents a 500 megahertz (MHz) on-off keying (OOK) signal output from drive circuit 108. Signal G104 represents a detection circuit signal output from detection circuit 114. Signal G106 represents an example of a square wave logic signal output from output terminal VOUT1. For example, a high input (HIGH INPUT) of 5 volts (V) corresponds to "1," and a low input (LOW INPUT) of 0 volts corresponds to "0."

[0013] As shown in FIG. 2 , the high-speed circuit block A10 must operate at high speed, and is therefore composed of MOS (metal-oxide-semiconductor) elements capable of high-speed operation. Because high-speed MOS elements have low breakdown voltages and low power supply voltages, the power supply circuit 100 regulates an external voltage (Vdd1 or Vdd2), for example, from 5 volts to a low voltage, for example, 1.5 volts, and supplies the voltage to the high-speed circuit block A10. Because the high-speed circuit block A10 has a lower breakdown voltage than circuits in other regions, it is vulnerable to electrostatic discharge (ESD). Therefore, in this embodiment, the power supply circuit 100 is configured to include a protection circuit to protect each circuit in the high-speed circuit block A10 from ESD stress such as electrostatic discharge. This suppresses transmission of overvoltage and other stresses from the power supply circuit 100 to the high-speed circuit block A10, even if ESD stress such as electrostatic discharge or a high voltage that rises in a short time, for example, 20 nanoseconds (nsec), that occurs when the power supply that supplies power to the VDD1 terminal 5 is turned on is applied to the semiconductor device 1. Details of the power supply circuit 100 will be described later.

[0014] A square-wave logic signal G100, for example, is input to the input buffer 102. This logic signal G100 is a square-wave signal of, for example, 150 Mbps (bits per second). The input buffer 102 outputs the square-wave logic signal G100 to the first level shifter 104 while maintaining the shape of the square wave.

[0015] The first level shifter 104 changes the amplitude of the logic signal G100. For example, the first level shifter 104 converts a 5 volt HIGH INPUT square wave into a 1.5 volt square wave.

[0016] The modulator 106 has an oscillator and generates a high-frequency differential on-off keying signal G102 in response to the square wave signal input from the first level shifter 104, and outputs the signal to the drive circuit 108. This on-off keying signal G102 is a signal in which a modulated signal is carried on a 500 MHz carrier wave. Note that, although a 500 MHz carrier wave is used in this embodiment, this is not limiting. For example, a carrier wave of several hundred MHz to several GHz may be generated.

[0017] The driver circuit 108 drives the transformer 110 to transmit the 500 MHz on-off keying signal G102 to the secondary chip 20. The transformer 110 transmits the on-off keying signal G102 to the secondary chip 20 while maintaining galvanic isolation. The transformer 110 according to this embodiment includes two transformers, thereby enhancing insulation performance and improving functional safety. Alternatively, a single transformer may be used for applications where insulation performance is not as important. Furthermore, while the semiconductor device 1 according to this embodiment uses magnetic coupling for galvanic isolation, this is not a limitation. For example, capacitive coupling or optical coupling may also be used. Furthermore, although the semiconductor device 1 according to this embodiment transmits an on-off keying signal, this is not a limitation. For example, frequency modulation, edge signal transmission, or a signal combining these may also be used.

[0018] The amplifier 112 amplifies the input signal from the transformer 110 and outputs it to the detection circuit 114. The detection circuit 114 detects the input differential on-off keying signal, outputs a detection circuit output G104, converts it into a 1.5 V square wave, and outputs it to the second level shifter 116.

[0019] The second level shifter 116 converts the square wave of 1.5 volts and 0 volts into a square wave logic signal G106 of 5 volts and 0 volts and outputs it to the output buffer 118. The output buffer 118 outputs the logic signal G106 from the output terminal VOUT1 while maintaining the square waveform of the logic signal G106. In this way, the digital isolator 2 modulates the logic signal G100 input to the signal input terminal VIN1 and outputs the demodulated logic signal G106 from the signal output terminal VOUT1 while maintaining galvanic isolation between the primary-side chip 10 and the secondary-side chip 20. Note that the configuration of the digital isolator 2 is an example and is not limited to this circuit configuration.

[0020] Fig. 3 is a circuit diagram showing an example configuration of the power supply circuit 100. As shown in Fig. 3, the power supply circuit 100 is, for example, a linear regulator (LDO: Low Drop Output), and includes a first transistor 130, an output capacitor C10, a feedback voltage generation circuit 132, an error amplifier 134, an electrostatic protection circuit 136, and a protection circuit 200. Note that the error amplifier 134 according to this embodiment corresponds to the first voltage generation circuit, and the electrostatic protection circuit 136 corresponds to the fourth transistor.

[0021] The protection circuit 200 outputs a control voltage that renders the first transistor 130 non-conductive or in a state exhibiting a predetermined high resistance value when the input voltage to the VDD1 terminal 5 increases beyond a first threshold Vthm (see FIG. 5, described later) within a predetermined time. This high resistance value is a resistance value that, for example, makes the potential between the VOUT output node 7 and the GND terminal 8 equal to or lower than the breakdown voltage of a high-speed MOS when ESD stress is applied to the VDD1 terminal 5. In other words, the control voltage is set to a high resistance value corresponding to the expected ESD stress. The protection circuit 200 includes a second transistor 202 and a voltage generation circuit 204. Details of the protection circuit 200 will be described later with reference to FIG. 4. The voltage generation circuit 204 according to this embodiment corresponds to the second voltage generation circuit, and the VOUT output node 7 corresponds to the output terminal.

[0022] 3, the power supply circuit 100 includes a first transistor 130 configured between a VDD1 terminal 5 and a VOUT output node 7. The first transistor 130 is, for example, a PMOS (p-Channel Metal-Oxide Semiconductor) transistor, with a source connected to the VDD1 terminal 5, a drain connected to the VOUT output node 7, and a gate connected to a node n2. Note that the node n2 according to this embodiment corresponds to the first node.

[0023] A high-speed circuit block A10 is connected as a load between the VOUT output node 7 and the GND terminal 8. Similarly, an output capacitor C10 and a feedback voltage generating circuit 132 are connected in parallel with the high-speed circuit block A10 between the VOUT output node 7 and the GND terminal 8.

[0024] The feedback voltage generating circuit 132 has two resistors R12 and R14 connected in series between the VOUT output node 7 and the GND terminal 8. The feedback voltage generating circuit 132 generates a divided voltage proportional to the output voltage Vout as a feedback voltage FB from a node n4 between the resistors R12 and R14.

[0025] A DC voltage Vdd of, for example, 5 volts is input from a battery, storage battery, or other DC power supply (not shown) to the VDD1 terminal 5. A voltage corresponding to the set output voltage Vout, for example, 1.5 volts, is set as the reference voltage VREF.

[0026] The inverting input terminal of the error amplifier 134 is connected to node n4. A feedback voltage FB is input to the inverting input terminal. A reference voltage VREF is input to the non-inverting input terminal. The output terminal of the error amplifier 134 is connected to the gate, which is the control terminal of the first transistor 130. The error amplifier 134 amplifies the error between the reference voltage VREF and the feedback voltage FB and outputs a voltage ER corresponding to the error to the control terminal (gate) of the first transistor 130. The source-drain resistance of the first transistor 130 varies depending on the voltage ER applied to the gate. The source-drain voltage of the first transistor 130 is adjusted by the voltage ER applied to the gate. The output voltage Vout is stabilized by feedback control using the error amplifier 134, with the target value being Vout = VREF × (R12 + R14) / R14. That is, the reference voltage VREF and the resistance values of the resistors R12 and R14 are set so that Vout is 1.5 volts.

[0027] The power supply circuit 100 is provided with an electrostatic protection circuit 136. The electrostatic protection circuit 136 is connected between the VDD1 terminal 5 and the GND terminal 8. The GND terminal 8 is a potential terminal with a lower potential than the potential Vdd applied to the VDD1 terminal 5, and the potential is set to 0 volts, for example.

[0028] Furthermore, for example, the electrostatic protection circuit 136 snaps back when the voltage input to the VDD1 terminal 5 exceeds a predetermined snapback voltage Vs (see FIG. 5, described later). As a result, the impedance between the VDD1 terminal 5 and the GND terminal 8 decreases, forming a path for the ESD current.

[0029] This electrostatic protection circuit 136 is, for example, an electrostatic protection transistor connected between the VDD1 terminal 5 and the GND terminal 8. More specifically, this electrostatic protection transistor is, for example, an NMOS (n-Channel Metal-Oxide Semiconductor) transistor, a so-called ggNMOS (Gate Grounded NMOS) transistor whose gate and source are connected to the GND terminal 8.

[0030] In this electrostatic protection circuit 136, when electrostatic discharge is applied to the VDD1 terminal 5, the substrate potential rises due to an avalanche current generated by avalanche breakdown at the drain end of the NMOS transistor, and a parasitic bipolar device operates. The operation of this parasitic bipolar device forms a low-impedance current path between the drain and source of the NMOS transistor, allowing a current caused by electrostatic discharge to flow, thereby protecting the circuitry connected between the VDD1 terminal 5 and the GND terminal 8.

[0031] 4 is a circuit diagram showing an example configuration of the protection circuit 200. As shown in FIG. 4, the protection circuit 200 includes a second transistor 202 and a voltage generation circuit 204. The second transistor 202 is, for example, a PMOS transistor, and has a source connected to the VDD1 terminal 5 and a drain connected to the gate, which is the control terminal, of the first transistor 130. Because the first transistor 130 is, for example, a PMOS transistor, when the voltage at the drain of the second transistor 202 increases in the positive direction, the resistance of the first transistor 130 increases, and when the voltage exceeds a predetermined threshold voltage, the first transistor 130 turns off.

[0032] The voltage generation circuit 204 controls the voltage of the gate, which is the control terminal of the second transistor 202, in response to the input voltage of the VDD1 terminal 5. For example, when a positive surge voltage is applied to the VDD1 terminal 5 and exceeds a first threshold Vthm (see FIG. 5), the voltage generation circuit 204 applies a control voltage to the control terminal of the second transistor 202, which causes the second transistor 202 to be conductive or have a predetermined low resistance close to the conductive state. When the second transistor 202 is conductive or has a predetermined low resistance close to the conductive state, the drain voltage of the second transistor 202 becomes the voltage Vdd of the VDD1 terminal 5. Alternatively, the drain voltage of the second transistor 202 approaches the voltage Vdd of the VDD1 terminal 5. Note that the positive surge voltage may include not only electrostatic discharge but also a voltage generated when the input power supply to the VDD1 terminal 5 is turned on. The voltage generation circuit 204 is configured to output a control voltage in response to ESD stress that rises sharply, for example, within 20 nanoseconds.

[0033] More specifically, the voltage generating circuit 204 includes a first capacitor C20, a first resistor R20, a second resistor R22, and a third transistor 206. The first capacitor C20 is connected between the VDD1 terminal 5 and a node n6. The first capacitor C20 has a capacitance of, for example, 2 picofarads (pF). Note that a capacitor may also be referred to as a "capacitor." In addition, the node n6 according to this embodiment corresponds to the second node.

[0034] Furthermore, a first resistor R20 is connected between the GND terminal 8 and the node n6. The first resistor R20 has a resistance of, for example, 30 kiloohms (kΩ). The combination of the first capacitor C20 and the first resistor R20 can be set according to, for example, a transient state when the input power supply to the VDD1 terminal 5 is turned on, or ESD stress due to electrostatic discharge.

[0035] The third transistor 206 is, for example, an NMOS transistor, and has a drain connected to node n8 and a source connected to the GND terminal 8. The gate, which is the control terminal of the third transistor 206, is connected to node n6. Note that node n8 in this embodiment corresponds to the third node. One end of the second resistor R22 is connected to node n8, and the other end is connected to the VDD1 terminal 5.

[0036] Here, we will explain the second elements. The second elements are sometimes called dummy elements. In the manufacturing process of transistors, characteristics variations can become large due to the influence of pattern density and surrounding devices. For this reason, multiple second elements are arranged in regions at the edge or adjacent to the region where multiple first elements, i.e., NMOS transistors or PMOS transistors, are configured. In this way, for example, an integrated circuit is composed of a first element group consisting of multiple first elements and a second element group consisting of multiple second elements arranged closer to the edge of the integrated circuit than the first element group. These second element groups are elements arranged to reduce characteristics variations in the manufacturing process of, for example, NMOS transistors or PMOS transistors, and as described above, are element groups arranged closer to the edge of the integrated circuit than the first element group. In other words, in the manufacturing process of the second elements, it is difficult to uniformly influence the surroundings when forming the second elements. As a result, the performance of the second elements varies compared to the first elements.

[0037] According to this embodiment, the second transistor 202 and the third transistor 206 operate as switches, so they operate digitally and do not require precision. Therefore, even when using a second element, the conditions for controlling the operation of the second transistor 202 and the third transistor 206 can be satisfied. Furthermore, the amount of current flowing through the second element is smaller than that of the first element, and the area can be reduced. That is, the second transistor 202 and the third transistor 206 according to this embodiment can be used by connecting wiring to the second element, which would normally be a dummy element and not connected to wiring. As described above, this second element is disposed closer to the end of the integrated circuit comprising the first transistor 130 than the first transistor 130. For example, this second element is disposed at the end of the integrated circuit comprising the first transistor 130. This allows the semiconductor device 1 to be further miniaturized.

[0038] The above is an explanation of an example of the configuration of the semiconductor device 1. An example of the operation of the electrostatic protection circuit 136 and the protection circuit 200 will now be explained using FIG. 5 while also referring to FIGS. 3 and 4. FIG. 5 is a diagram illustrating an example of the operation of the electrostatic protection circuit 136 and the protection circuit 200. In FIG. 5(a), the horizontal axis represents time, and the vertical axis represents a positive surge voltage as the Vdd voltage input to the VDD1 terminal 5. In FIG. 5(b), the horizontal axis represents time, and the vertical axis represents the voltage Vx of node n6 (see FIG. 4). In FIG. 5(c), the horizontal axis represents time, and the vertical axis represents the current Ix flowing through node n8 (see FIG. 4). The interval between time t0 and time t1 is, for example, 20 nanoseconds.

[0039] As shown in FIG. 5(a), an example will be described in which electrostatic discharge is applied as a positive surge voltage (ESD voltage) at time t0. When a positive surge voltage is applied between the VDD input terminal 5 and the GND terminal 8, the Vdd voltage rises sharply. Then, when the Vdd voltage reaches the snapback voltage Vs of the ggNMOS transistor of the electrostatic protection circuit 136 at time t1, the parasitic bipolar device of the ggNMOS operates, becoming a hold voltage Vh and allowing ESD current to flow. The first threshold voltage Vthm is a threshold voltage that, when the Vdd voltage exceeds this first threshold voltage Vthm, renders the first transistor 130 non-conductive or in a state exhibiting a predetermined high resistance value.

[0040] When an ESD current flows, the Vdd voltage gradually drops. In this embodiment, the voltage that is applied between the VDD input terminal 5 and the GND terminal 8 due to an electrical discharge and that rises sharply may be referred to as ESD stress. The ESD stress that may be experimentally applied to the semiconductor device 1 is the Human Body Model (HBM). FIG. 5(a) shows an example in which a 2 kilovolt (kV) human body model is applied as a positive surge voltage.

[0041] At this time, as shown in FIG. 5(b), the voltage Vx at the node n6 (see FIG. 4) rises sharply along with the sharp rise in the voltage Vdd in accordance with the transient characteristics of the first capacitor C20 (see FIG. 4) and the first resistor R20 (see FIG. 4), and exceeds the first voltage Vthn, which is the threshold voltage of the third transistor 206, at time t2. The first voltage Vthn is a voltage corresponding to the first threshold voltage Vthm. The voltage Vx continues to rise in accordance with the rise in the voltage Vdd, and reaches the hold voltage Vh at time t1. After the rise in the voltage Vx ends, the voltage decreases with a time constant of 60 nanoseconds (assuming the capacitance of the first capacitor C20 is 2 picofarads and the capacitance of the first resistor R20 is 30 kilohms), and at time t3, the hold voltage Vh falls below the threshold voltage Vthn of the third transistor 206. This time constant only needs to be designed to be 20 nanoseconds or longer, the time it takes for ESD (HBM) to rise, and it operates with a relatively small time constant. Also, because the time constant is relatively small, it is possible to design it with small capacitance and resistance.

[0042] At this time, as shown in FIG. 5(c), voltage Vx exceeds first voltage Vthn, which is the threshold voltage, between times t2 and t3, causing current Ix to flow between the source and drain of third transistor 206. This current is limited by voltage Vdd / first resistor R20. For example, when hold voltage Vh is 10 volts and first resistor R20 is 10 kilohms, current Ix is 1 milliampere (mA). Therefore, a large current does not flow through third transistor 206, reducing the risk of breakdown.

[0043] Then, a voltage drop occurs due to the current Ix and the second resistor R22, causing the potential of the gate of the second transistor 202 to drop, and the second transistor 202 to turn on (become conductive). Furthermore, as the second transistor 202 turns on (becomes conductive), a voltage Vdd or close to Vdd is applied to the gate of the first transistor 130, causing the first transistor 130 to turn off (become non-conductive) or to have a resistance close to the non-conductive state, as described above. A simulation example of the voltage at the VOUT output node 7 after the first transistor 130 turns off (becomes non-conductive) or has a resistance close to the non-conductive state will be described later with reference to FIG. 6. As described above, both the second transistor 202 and the third transistor 206 pass small amounts of current and operate as switches, making it possible to reduce the area of the power supply circuit 100 by using a second element or the like.

[0044] 6 is a diagram showing the results of a simulation when a positive surge voltage (ESD voltage) of 2 kilovolts is applied between the VDD input terminal 5 and the GND terminal 8. The horizontal axis represents time, and the vertical axis represents voltage.

[0045] Line L7A indicates the Vdd voltage, and line L7B indicates the voltage at the VOUT output node 7. As shown in FIG. 6, even if the Vdd voltage changes suddenly, the voltage at the VOUT output node 7 is suppressed to 2 volts or less. That is, as described above, when the second transistor 202 is turned on, the Vdd voltage is applied to the gate of the first transistor 130, and when the first transistor 130 is turned off or has a resistance value close to that of the non-conductive state, the voltage at the VOUT output node 7 is suppressed to 2 volts or less. As can be seen from this, even if a positive surge voltage (ESD voltage) is applied as ESD stress, the circuits within the high-speed circuit block A10 will not exceed their withstand voltage and will be protected.

[0046] Fig. 7 is a circuit diagram showing a configuration example of a comparative example power supply circuit 100. As shown in Fig. 7, the comparative example power supply circuit 100 is a power supply circuit in which a protection circuit 200 is not implemented.

[0047] FIG. 8 shows, as a comparative example, the results of a simulation performed on the power supply circuit 100 shown in FIG. 7. The simulation results are obtained when a 2-kilovolt positive surge voltage (ESD voltage) is applied between the VDD input terminal 5 and the GND terminal 8. The horizontal axis represents time, and the vertical axis represents voltage. Line L8A represents the Vdd voltage, and line L8B represents the voltage at the VOUT output node 7. As shown in FIG. 8, in the power supply circuit 100 without the protection circuit 200, the initial value of the gate voltage of the first transistor 130 is 0. The bandwidth of the error amplifier 134 is several MHz. Therefore, when the VDD voltage changes suddenly, the first transistor 130 turns on, causing the voltage at the VOUT output node 7 to rise to 6V or higher. This can cause the circuits in the high-speed circuit block A10 to exceed their withstand voltage, potentially resulting in breakdown.

[0048] As described above, in the semiconductor device 1 according to this embodiment, when the input voltage of the VDD1 terminal 5 increases beyond the first threshold Vthn within a predetermined time, the protection circuit 200 outputs to the control terminal of the first transistor 130 a voltage that causes the first transistor 130 to become non-conductive or to have a resistance value approaching non-conduction. This makes it possible to suppress the voltage of the VOUT output node 7, to which one end of the first transistor 130 is connected, below a predetermined value, even if a positive surge voltage (ESD voltage) exceeding the first threshold Vthn is applied within the predetermined time. Therefore, circuits within the high-speed circuit block A10 are protected without exceeding their breakdown voltage.

[0049] (Second embodiment) The semiconductor device 1 according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the protection circuit 200 further includes a transistor that sets the voltage of the VOUT output node 7 to the ground GND potential. The following describes the differences from the semiconductor device 1 according to the first embodiment.

[0050] 9 is a circuit diagram showing an example of the configuration of a protection circuit 200 according to the second embodiment. As shown in FIG. 9, a voltage generation circuit 204 differs from the protection circuit 200 according to the first embodiment in that it further includes a fifth transistor 208.

[0051] The fifth transistor 208 is an element equivalent to the third transistor 206, and is an NMOS transistor having a threshold voltage Vthn, with its drain connected to the VOUT output node 7 and its source connected to the GND terminal 8. The gate, which is the control terminal of the fifth transistor 208, is connected to the node n6.

[0052] With this configuration, as shown in FIG. 5(b) above, the voltage Vx at the node n6 rises along with the steep rise in the voltage Vdd in accordance with the transient characteristics of the first capacitor C20 and the first resistor R20, and exceeds the threshold voltage Vthn of the fifth transistor 208 at time t2. When the voltage Vx stops rising, the voltage drops, and at time t3, the hold voltage Vh falls below the threshold voltage Vthn of the third transistor 206. As a result, the fifth transistor 208 is in a conductive state from time t2 to time t3. Therefore, the potential of the VOUT output node 7 becomes equal to the potential of the GND terminal 8 between time t2 and time t3. As can be seen from this, the potential of the VOUT output node 7 can be made equal to the potential of the GND terminal 8 between time t2 and time t3, regardless of the state of the first transistor 130. Therefore, the circuits in the high-speed circuit block A10 and the like do not exceed the withstand voltage between time t2 and time t3 regardless of the state of the first transistor 130, and are protected more stably.

[0053] (Third embodiment) The semiconductor device 1 according to the third embodiment differs from the semiconductor device 1 according to the first embodiment in that the protection circuit 200 is configured with a resistor and a capacitor connected in series. The differences from the semiconductor device 1 according to the first embodiment will be described below.

[0054] Fig. 10 is a circuit diagram showing an example of the configuration of a protection circuit 200 according to the third embodiment. As shown in Fig. 10, the voltage generation circuit 204 differs from the protection circuit 200 according to the first embodiment in that it is composed of a third resistor R24 and a second capacitor C22.

[0055] One end of the third resistor R24 is connected to the VDD input terminal 5, and the other end of the third resistor R24 is connected to a node n10. One end of the second capacitor C22 is connected to the node n10, and the other end of the second capacitor C22 is connected to the GND terminal 8. Note that the node n10 in this embodiment corresponds to the fourth node.

[0056] When a positive surge voltage is applied to the VDD input terminal 5, a current flows through the third resistor R24, and a voltage drop occurs due to the current and the third resistor R24. This causes the second transistor 202 to be conductive (ON). With the second transistor 202 in a conductive state (ON), the Vdd voltage is applied to the gate of the first transistor 130, causing it to be in a non-conductive state (OFF) or a resistance value close to that of the non-conductive state. As a result, the potential of the VOUT output node 7 is suppressed within the withstand voltage of the high-speed circuit block A10, as in the case of FIG. 6 described above.

[0057] In this way, even if a voltage that rises sharply within a predetermined time, for example, 20 nanoseconds, is applied, it is possible to suppress the voltage at the VOUT output node 7 to which one end of the first transistor 130 is connected. As a result, the circuits in the high-speed circuit block A10 are protected without exceeding their withstand voltage.

[0058] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0059] 1: semiconductor device, 100: power supply circuit, 5: VDD1 terminal (input terminal), 7: VOUT output node (output terminal), 8: GND terminal (ground terminal), 130: first transistor, 132: feedback voltage generation circuit, 134: error amplifier (first voltage generation circuit), 136: electrostatic protection circuit (fourth transistor), 200: protection circuit, 202: second transistor, 204: voltage generation circuit (second voltage generation circuit), 206: third transistor, 208: fifth transistor, C20: first capacitor, C22: second capacitor, FB: feedback voltage, n2: first node, n6: second node, n8: third node, n10: fourth node, R20: first resistor, R22: second resistor, R24: third resistor, VREF: reference voltage, Vthn: first potential, Vthm: first threshold voltage.

Claims

1. a first transistor connected between an input terminal for inputting an input voltage and an output terminal for outputting an output voltage; a feedback voltage generating circuit that divides the output voltage to generate a feedback voltage; a first voltage generating circuit that supplies a voltage to a first control terminal of the first transistor via a first node based on the feedback voltage and a reference voltage so that the output voltage matches or approximates a set value; a protection circuit that outputs a voltage to the first control terminal when the input voltage increases beyond a first threshold voltage within a predetermined time, causing the first transistor to become non-conductive or to exhibit a predetermined high resistance value; Equipped with The protection circuit includes: a second transistor connected between the input terminal and the first node; a second voltage generating circuit that supplies a voltage to a second control terminal of the second transistor in response to a time change of the input voltage; and The second voltage generating circuit a first capacitor connected between the input terminal and a second node; a first resistor connected between the second node and a ground terminal; a third transistor having a third control terminal connected to the second node and connected between the ground terminal and a third node; a second resistor connected between the input terminal and the third node; the third node is connected to the second control terminal; a fourth NMOS transistor having a gate and a source connected to the ground terminal and a drain connected to the input terminal; the first threshold voltage is set lower than a snapback voltage of the fourth transistor, The protection circuit outputs a voltage to the first control terminal such that the first transistor is non-conductive or exhibits a predetermined high resistance value when the potential of the second node reaches a first potential corresponding to the first threshold voltage.

2. The protection circuit includes: If the potential of the second node reaches a potential corresponding to the first threshold voltage within 20 nanoseconds, 2. The power supply circuit according to claim 1, wherein the third transistor is turned on, the second transistor is subsequently turned on, and a voltage is output to the first control terminal via the second transistor that is now turned on, such that the first transistor has a resistance value that makes it non-conductive or approaching non-conductivity.

3. a first transistor connected between an input terminal for inputting an input voltage and an output terminal for outputting an output voltage; a feedback voltage generating circuit that divides the output voltage to generate a feedback voltage; a first voltage generating circuit that supplies a voltage to a first control terminal of the first transistor via a first node based on the feedback voltage and a reference voltage so that the output voltage matches or approximates a set value; a protection circuit that outputs a voltage to the first control terminal when the input voltage increases beyond a first threshold voltage within a predetermined time, causing the first transistor to become non-conductive or to exhibit a predetermined high resistance value; Equipped with The protection circuit includes: a second transistor connected between the input terminal and the first node; a second voltage generating circuit that supplies a voltage to a second control terminal of the second transistor in response to a time change of the input voltage; and The second voltage generating circuit a first capacitor connected between the input terminal and a second node; a first resistor connected between the second node and a ground terminal; a third transistor having a third control terminal connected to the second node and connected between the ground terminal and a third node; a second resistor connected between the input terminal and the third node; the third node is connected to the second control terminal; The second voltage generating circuit a fifth control terminal connected to the second node, and a fifth transistor connected between the ground terminal and the output terminal.

4. The second voltage generating circuit 3. The power supply circuit according to claim 1, further comprising: a fifth transistor having a fifth control terminal connected to the second node and connected between the ground terminal and the output terminal.

5. 3. The power supply circuit according to claim 2, wherein the first transistor, the second transistor, and the third transistor are configured as an integrated circuit, the integrated circuit having a first element group and a second element group arranged on an end side of the integrated circuit with respect to the first element group, the first transistor being any element in the first element group, and at least one of the second transistor and the third transistor being any element in the second element group.

6. 1. A semiconductor device that modulates a logic signal input to a signal input terminal of a primary-side chip and outputs the demodulated logic signal from a signal output terminal of the secondary-side chip while maintaining galvanic isolation between the primary-side chip and a secondary-side chip, A power supply circuit according to any one of claims 1 to 5, A semiconductor device driven by the output voltage supplied from the power supply circuit.

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